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class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_Scalable"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Xeon Scalable</span> </div> </a> <ul id="toc-Xeon_Scalable-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Xeon_6" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_6"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Xeon 6</span> </div> </a> <ul id="toc-Xeon_6-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Xeon_D" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_D"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Xeon D</span> </div> </a> <ul id="toc-Xeon_D-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Xeon_W" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_W"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Xeon W</span> </div> </a> <ul id="toc-Xeon_W-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Overview" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Overview"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Overview</span> </div> </a> <ul id="toc-Overview-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-P6-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#P6-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>P6-based Xeon</span> </div> </a> <button aria-controls="toc-P6-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle P6-based Xeon subsection</span> </button> <ul id="toc-P6-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Pentium_II_Xeon" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Pentium_II_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Pentium II Xeon</span> </div> </a> <ul id="toc-Pentium_II_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Pentium_III_Xeon" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Pentium_III_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Pentium III Xeon</span> </div> </a> <ul id="toc-Pentium_III_Xeon-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-NetBurst-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#NetBurst-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>NetBurst-based Xeon</span> </div> </a> <button aria-controls="toc-NetBurst-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle NetBurst-based Xeon subsection</span> </button> <ul id="toc-NetBurst-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Xeon_(DP)_and_Xeon_MP_(32-bit)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_(DP)_and_Xeon_MP_(32-bit)"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Xeon (DP) and Xeon MP (32-bit)</span> </div> </a> <ul id="toc-Xeon_(DP)_and_Xeon_MP_(32-bit)-sublist" class="vector-toc-list"> <li id="toc-Foster" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Foster"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.1</span> <span>Foster</span> </div> </a> <ul id="toc-Foster-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Prestonia" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Prestonia"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.2</span> <span>Prestonia</span> </div> </a> <ul id="toc-Prestonia-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gallatin" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Gallatin"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1.3</span> <span>Gallatin</span> </div> </a> <ul id="toc-Gallatin-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Xeon_(DP)_and_Xeon_MP_(64-bit)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Xeon_(DP)_and_Xeon_MP_(64-bit)"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>Xeon (DP) and Xeon MP (64-bit)</span> </div> </a> <ul id="toc-Xeon_(DP)_and_Xeon_MP_(64-bit)-sublist" class="vector-toc-list"> <li id="toc-Nocona_and_Irwindale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Nocona_and_Irwindale"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2.1</span> <span>Nocona and Irwindale</span> </div> </a> <ul id="toc-Nocona_and_Irwindale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cranford_and_Potomac" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Cranford_and_Potomac"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2.2</span> <span>Cranford and Potomac</span> </div> </a> <ul id="toc-Cranford_and_Potomac-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Dual-Core_Xeon" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Dual-Core_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3</span> <span>Dual-Core Xeon</span> </div> </a> <ul id="toc-Dual-Core_Xeon-sublist" class="vector-toc-list"> <li id="toc-"Paxville_DP"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Paxville_DP""> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3.1</span> <span>"Paxville DP"</span> </div> </a> <ul id="toc-"Paxville_DP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-7000-series_"Paxville_MP"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7000-series_"Paxville_MP""> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3.2</span> <span>7000-series "Paxville MP"</span> </div> </a> <ul id="toc-7000-series_"Paxville_MP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-7100-series_"Tulsa"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7100-series_"Tulsa""> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3.3</span> <span>7100-series "Tulsa"</span> </div> </a> <ul id="toc-7100-series_"Tulsa"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5000-series_"Dempsey"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5000-series_"Dempsey""> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3.4</span> <span>5000-series "Dempsey"</span> </div> </a> <ul id="toc-5000-series_"Dempsey"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Pentium_M_(Yonah)_based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Pentium_M_(Yonah)_based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Pentium M (Yonah) based Xeon</span> </div> </a> <button aria-controls="toc-Pentium_M_(Yonah)_based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Pentium M (Yonah) based Xeon subsection</span> </button> <ul id="toc-Pentium_M_(Yonah)_based_Xeon-sublist" class="vector-toc-list"> <li id="toc-LV_(ULV),_"Sossaman"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#LV_(ULV),_"Sossaman""> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>LV (ULV), "Sossaman"</span> </div> </a> <ul id="toc-LV_(ULV),_"Sossaman"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Core-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Core-based Xeon</span> </div> </a> <button aria-controls="toc-Core-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Core-based Xeon subsection</span> </button> <ul id="toc-Core-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Dual-Core" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Dual-Core"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1</span> <span>Dual-Core</span> </div> </a> <ul id="toc-Dual-Core-sublist" class="vector-toc-list"> <li id="toc-3000-series_"Conroe"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#3000-series_"Conroe""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1.1</span> <span>3000-series "Conroe"</span> </div> </a> <ul id="toc-3000-series_"Conroe"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-3100-series_"Wolfdale"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#3100-series_"Wolfdale""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1.2</span> <span>3100-series "Wolfdale"</span> </div> </a> <ul id="toc-3100-series_"Wolfdale"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5100-series_"Woodcrest"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5100-series_"Woodcrest""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1.3</span> <span>5100-series "Woodcrest"</span> </div> </a> <ul id="toc-5100-series_"Woodcrest"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5200-series_"Wolfdale-DP"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5200-series_"Wolfdale-DP""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1.4</span> <span>5200-series "Wolfdale-DP"</span> </div> </a> <ul id="toc-5200-series_"Wolfdale-DP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-7200-series_"Tigerton"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7200-series_"Tigerton""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1.5</span> <span>7200-series "Tigerton"</span> </div> </a> <ul id="toc-7200-series_"Tigerton"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Quad-Core_and_Six-Core_Xeon" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Quad-Core_and_Six-Core_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2</span> <span>Quad-Core and Six-Core Xeon</span> </div> </a> <ul id="toc-Quad-Core_and_Six-Core_Xeon-sublist" class="vector-toc-list"> <li id="toc-3200-series_"Kentsfield_"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#3200-series_"Kentsfield_""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.1</span> <span>3200-series "Kentsfield "</span> </div> </a> <ul id="toc-3200-series_"Kentsfield_"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-3300-series_"Yorkfield"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#3300-series_"Yorkfield""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.2</span> <span>3300-series "Yorkfield"</span> </div> </a> <ul id="toc-3300-series_"Yorkfield"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5300-series_"Clovertown"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5300-series_"Clovertown""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.3</span> <span>5300-series "Clovertown"</span> </div> </a> <ul id="toc-5300-series_"Clovertown"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5400-series_"Harpertown"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5400-series_"Harpertown""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.4</span> <span>5400-series "Harpertown"</span> </div> </a> <ul id="toc-5400-series_"Harpertown"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-7300-series_"Tigerton_QC"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7300-series_"Tigerton_QC""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.5</span> <span>7300-series "Tigerton QC"</span> </div> </a> <ul id="toc-7300-series_"Tigerton_QC"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-7400-series_"Dunnington"" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7400-series_"Dunnington""> <div class="vector-toc-text"> <span class="vector-toc-numb">6.2.6</span> <span>7400-series "Dunnington"</span> </div> </a> <ul id="toc-7400-series_"Dunnington"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Nehalem-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Nehalem-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Nehalem-based Xeon</span> </div> </a> <button aria-controls="toc-Nehalem-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Nehalem-based Xeon subsection</span> </button> <ul id="toc-Nehalem-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-3400-series_"Lynnfield"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#3400-series_"Lynnfield""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>3400-series "Lynnfield"</span> </div> </a> <ul id="toc-3400-series_"Lynnfield"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-3400-series_"Clarkdale"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#3400-series_"Clarkdale""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>3400-series "Clarkdale"</span> </div> </a> <ul id="toc-3400-series_"Clarkdale"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-W3500-series_"Bloomfield"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#W3500-series_"Bloomfield""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.3</span> <span>W3500-series "Bloomfield"</span> </div> </a> <ul id="toc-W3500-series_"Bloomfield"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5500-series_"Gainestown"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#5500-series_"Gainestown""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.4</span> <span>5500-series "Gainestown"</span> </div> </a> <ul id="toc-5500-series_"Gainestown"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-C3500/C5500-series_"Jasper_Forest"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#C3500/C5500-series_"Jasper_Forest""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.5</span> <span>C3500/C5500-series "Jasper Forest"</span> </div> </a> <ul id="toc-C3500/C5500-series_"Jasper_Forest"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-W3600/5600-series_"Gulftown"_&_"Westmere-EP"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#W3600/5600-series_"Gulftown"_&_"Westmere-EP""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.6</span> <span>W3600/5600-series "Gulftown" & "Westmere-EP"</span> </div> </a> <ul id="toc-W3600/5600-series_"Gulftown"_&_"Westmere-EP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-6500/7500-series_"Beckton"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#6500/7500-series_"Beckton""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.7</span> <span>6500/7500-series "Beckton"</span> </div> </a> <ul id="toc-6500/7500-series_"Beckton"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E7-x8xx-series_"Westmere-EX"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E7-x8xx-series_"Westmere-EX""> <div class="vector-toc-text"> <span class="vector-toc-numb">7.8</span> <span>E7-x8xx-series "Westmere-EX"</span> </div> </a> <ul id="toc-E7-x8xx-series_"Westmere-EX"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Sandy_Bridge-_and_Ivy_Bridge-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Sandy_Bridge-_and_Ivy_Bridge-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Sandy Bridge- and Ivy Bridge-based Xeon</span> </div> </a> <button aria-controls="toc-Sandy_Bridge-_and_Ivy_Bridge-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Sandy Bridge- and Ivy Bridge-based Xeon subsection</span> </button> <ul id="toc-Sandy_Bridge-_and_Ivy_Bridge-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-E3-12xx-series_"Sandy_Bridge"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx-series_"Sandy_Bridge""> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>E3-12xx-series "Sandy Bridge"</span> </div> </a> <ul id="toc-E3-12xx-series_"Sandy_Bridge"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E3-12xx_v2-series_"Ivy_Bridge"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx_v2-series_"Ivy_Bridge""> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2</span> <span>E3-12xx v2-series "Ivy Bridge"</span> </div> </a> <ul id="toc-E3-12xx_v2-series_"Ivy_Bridge"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E5-14xx/24xx_series_"Sandy_Bridge-EN"_and_E5-16xx/26xx/46xx-series_"Sandy_Bridge-EP"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E5-14xx/24xx_series_"Sandy_Bridge-EN"_and_E5-16xx/26xx/46xx-series_"Sandy_Bridge-EP""> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3</span> <span>E5-14xx/24xx series "Sandy Bridge-EN" and E5-16xx/26xx/46xx-series "Sandy Bridge-EP"</span> </div> </a> <ul id="toc-E5-14xx/24xx_series_"Sandy_Bridge-EN"_and_E5-16xx/26xx/46xx-series_"Sandy_Bridge-EP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E5-14xx_v2/24xx_v2_series_"Ivy_Bridge-EN"_and_E5-16xx_v2/26xx_v2/46xx_v2_series_"Ivy_Bridge-EP"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E5-14xx_v2/24xx_v2_series_"Ivy_Bridge-EN"_and_E5-16xx_v2/26xx_v2/46xx_v2_series_"Ivy_Bridge-EP""> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4</span> <span>E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP"</span> </div> </a> <ul id="toc-E5-14xx_v2/24xx_v2_series_"Ivy_Bridge-EN"_and_E5-16xx_v2/26xx_v2/46xx_v2_series_"Ivy_Bridge-EP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E7-28xx_v2/48xx_v2/88xx_v2_series_"Ivy_Bridge-EX"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E7-28xx_v2/48xx_v2/88xx_v2_series_"Ivy_Bridge-EX""> <div class="vector-toc-text"> <span class="vector-toc-numb">8.5</span> <span>E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX"</span> </div> </a> <ul id="toc-E7-28xx_v2/48xx_v2/88xx_v2_series_"Ivy_Bridge-EX"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Haswell-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Haswell-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Haswell-based Xeon</span> </div> </a> <button aria-controls="toc-Haswell-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Haswell-based Xeon subsection</span> </button> <ul id="toc-Haswell-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-E3-12xx_v3_series_"Haswell-WS"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx_v3_series_"Haswell-WS""> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1</span> <span>E3-12xx v3 series "Haswell-WS"</span> </div> </a> <ul id="toc-E3-12xx_v3_series_"Haswell-WS"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E5-16xx/26xx_v3_series_"Haswell-EP"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E5-16xx/26xx_v3_series_"Haswell-EP""> <div class="vector-toc-text"> <span class="vector-toc-numb">9.2</span> <span>E5-16xx/26xx v3 series "Haswell-EP"</span> </div> </a> <ul id="toc-E5-16xx/26xx_v3_series_"Haswell-EP"-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-E7-48xx/88xx_v3_series_"Haswell-EX"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E7-48xx/88xx_v3_series_"Haswell-EX""> <div class="vector-toc-text"> <span class="vector-toc-numb">9.3</span> <span>E7-48xx/88xx v3 series "Haswell-EX"</span> </div> </a> <ul id="toc-E7-48xx/88xx_v3_series_"Haswell-EX"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Broadwell-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Broadwell-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Broadwell-based Xeon</span> </div> </a> <button aria-controls="toc-Broadwell-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Broadwell-based Xeon subsection</span> </button> <ul id="toc-Broadwell-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-E3-12xx_v4_series_"Broadwell-H"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx_v4_series_"Broadwell-H""> <div class="vector-toc-text"> <span class="vector-toc-numb">10.1</span> <span>E3-12xx v4 series "Broadwell-H"</span> </div> </a> <ul id="toc-E3-12xx_v4_series_"Broadwell-H"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Skylake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Skylake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Skylake-based Xeon</span> </div> </a> <button aria-controls="toc-Skylake-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Skylake-based Xeon subsection</span> </button> <ul id="toc-Skylake-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-E3-12xx_v5_series_"Skylake-S"" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx_v5_series_"Skylake-S""> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1</span> <span>E3-12xx v5 series "Skylake-S"</span> </div> </a> <ul id="toc-E3-12xx_v5_series_"Skylake-S"-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Kaby_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Kaby_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Kaby Lake-based Xeon</span> </div> </a> <button aria-controls="toc-Kaby_Lake-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Kaby Lake-based Xeon subsection</span> </button> <ul id="toc-Kaby_Lake-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-E3-12xx_v6_series" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#E3-12xx_v6_series"> <div class="vector-toc-text"> <span class="vector-toc-numb">12.1</span> <span>E3-12xx v6 series</span> </div> </a> <ul id="toc-E3-12xx_v6_series-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Coffee_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Coffee_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>Coffee Lake-based Xeon</span> </div> </a> <button aria-controls="toc-Coffee_Lake-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Coffee Lake-based Xeon subsection</span> </button> <ul id="toc-Coffee_Lake-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-E_(Server/Workstation)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Coffee_Lake-E_(Server/Workstation)"> <div class="vector-toc-text"> <span class="vector-toc-numb">13.1</span> <span>Coffee Lake-E (Server/Workstation)</span> </div> </a> <ul id="toc-Coffee_Lake-E_(Server/Workstation)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake-E_Refresh_(Server/Workstation)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Coffee_Lake-E_Refresh_(Server/Workstation)"> <div class="vector-toc-text"> <span class="vector-toc-numb">13.2</span> <span>Coffee Lake-E Refresh (Server/Workstation)</span> </div> </a> <ul id="toc-Coffee_Lake-E_Refresh_(Server/Workstation)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Comet_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Comet_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>Comet Lake-based Xeon</span> </div> </a> <ul id="toc-Comet_Lake-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cascade_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cascade_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>Cascade Lake-based Xeon</span> </div> </a> <button aria-controls="toc-Cascade_Lake-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cascade Lake-based Xeon subsection</span> </button> <ul id="toc-Cascade_Lake-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Variants" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Variants"> <div class="vector-toc-text"> <span class="vector-toc-numb">15.1</span> <span>Variants</span> </div> </a> <ul id="toc-Variants-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cooper_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cooper_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">16</span> <span>Cooper Lake-based Xeon</span> </div> </a> <ul id="toc-Cooper_Lake-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ice_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Ice_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">17</span> <span>Ice Lake-based Xeon</span> </div> </a> <ul id="toc-Ice_Lake-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Rocket_Lake-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Rocket_Lake-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">18</span> <span>Rocket Lake-based Xeon</span> </div> </a> <ul id="toc-Rocket_Lake-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sapphire_Rapids-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Sapphire_Rapids-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">19</span> <span>Sapphire Rapids-based Xeon</span> </div> </a> <button aria-controls="toc-Sapphire_Rapids-based_Xeon-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Sapphire Rapids-based Xeon subsection</span> </button> <ul id="toc-Sapphire_Rapids-based_Xeon-sublist" class="vector-toc-list"> <li id="toc-Features" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Features"> <div class="vector-toc-text"> <span class="vector-toc-numb">19.1</span> <span>Features</span> </div> </a> <ul id="toc-Features-sublist" class="vector-toc-list"> <li id="toc-CPU" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#CPU"> <div class="vector-toc-text"> <span class="vector-toc-numb">19.1.1</span> <span>CPU</span> </div> </a> <ul id="toc-CPU-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-I/O" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#I/O"> <div class="vector-toc-text"> <span class="vector-toc-numb">19.1.2</span> <span>I/O</span> </div> </a> <ul id="toc-I/O-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Emerald_Rapids-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Emerald_Rapids-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">20</span> <span>Emerald Rapids-based Xeon</span> </div> </a> <ul id="toc-Emerald_Rapids-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Granite_Rapids-based_Xeon" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Granite_Rapids-based_Xeon"> <div class="vector-toc-text"> <span class="vector-toc-numb">21</span> <span>Granite Rapids-based Xeon</span> </div> </a> <ul id="toc-Granite_Rapids-based_Xeon-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Supercomputers" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Supercomputers"> <div class="vector-toc-text"> <span class="vector-toc-numb">22</span> <span>Supercomputers</span> </div> </a> <ul id="toc-Supercomputers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">23</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">24</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">25</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">26</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Xeon</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 32 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-32" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">32 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B2%D9%8A%D9%88%D9%86" title="زيون – Arabic" lang="ar" hreflang="ar" data-title="زيون" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Xeon" title="Xeon – Catalan" lang="ca" hreflang="ca" data-title="Xeon" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Xeon" title="Xeon – Czech" lang="cs" hreflang="cs" data-title="Xeon" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – German" lang="de" hreflang="de" data-title="Intel Xeon" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Xeon" title="Xeon – Estonian" lang="et" hreflang="et" data-title="Xeon" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Spanish" lang="es" hreflang="es" data-title="Intel Xeon" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/Xeon" title="Xeon – Esperanto" lang="eo" hreflang="eo" data-title="Xeon" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Basque" lang="eu" hreflang="eu" data-title="Intel Xeon" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%BE%D8%B1%D8%AF%D8%A7%D8%B2%D9%86%D8%AF%D9%87_%D8%B2%D8%A6%D9%88%D9%86" title="پردازنده زئون – Persian" lang="fa" hreflang="fa" data-title="پردازنده زئون" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Xeon" title="Xeon – French" lang="fr" hreflang="fr" data-title="Xeon" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%A0%9C%EC%98%A8" title="제온 – Korean" lang="ko" hreflang="ko" data-title="제온" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Indonesian" lang="id" hreflang="id" data-title="Intel Xeon" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Xeon" title="Xeon – Italian" lang="it" hreflang="it" data-title="Xeon" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/Xeon" title="Xeon – Hebrew" lang="he" hreflang="he" data-title="Xeon" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Xeon" title="Xeon – Hungarian" lang="hu" hreflang="hu" data-title="Xeon" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Xeon" title="Xeon – Dutch" lang="nl" hreflang="nl" data-title="Xeon" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Xeon" title="Xeon – Japanese" lang="ja" hreflang="ja" data-title="Xeon" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Xeon" title="Xeon – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Xeon" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-oc mw-list-item"><a href="https://oc.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Occitan" lang="oc" hreflang="oc" data-title="Intel Xeon" data-language-autonym="Occitan" data-language-local-name="Occitan" class="interlanguage-link-target"><span>Occitan</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Xeon" title="Xeon – Polish" lang="pl" hreflang="pl" data-title="Xeon" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Xeon" title="Xeon – Portuguese" lang="pt" hreflang="pt" data-title="Xeon" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Xeon" title="Xeon – Romanian" lang="ro" hreflang="ro" data-title="Xeon" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Xeon" title="Xeon – Russian" lang="ru" hreflang="ru" data-title="Xeon" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Xeon" title="Xeon – Simple English" lang="en-simple" hreflang="en-simple" data-title="Xeon" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Xeon" title="Xeon – Slovak" lang="sk" hreflang="sk" data-title="Xeon" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/Xeon" title="Xeon – Serbian" lang="sr" hreflang="sr" data-title="Xeon" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Finnish" lang="fi" hreflang="fi" data-title="Intel Xeon" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Xeon" title="Xeon – Swedish" lang="sv" hreflang="sv" data-title="Xeon" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Intel_Xeon" title="Intel Xeon – Turkish" lang="tr" hreflang="tr" data-title="Intel Xeon" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Xeon" title="Xeon – Ukrainian" lang="uk" hreflang="uk" data-title="Xeon" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Line of Intel server and workstation processors</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with <a href="/wiki/Xenon" title="Xenon">Xenon</a> or <a href="/wiki/Intel_Xe" title="Intel Xe">Intel Xe</a>.</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">For the English music producer, see <a href="/wiki/Sophie_(musician)" title="Sophie (musician)">Sophie (musician)</a>.</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Xeon</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Intel-Xeon-Badge-2024.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/Intel-Xeon-Badge-2024.jpg/250px-Intel-Xeon-Badge-2024.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/Intel-Xeon-Badge-2024.jpg/330px-Intel-Xeon-Badge-2024.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/31/Intel-Xeon-Badge-2024.jpg/500px-Intel-Xeon-Badge-2024.jpg 2x" data-file-width="3000" data-file-height="3000" /></a></span><div class="infobox-caption">Logo since 2024</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">June 1998<span class="noprint">; 26 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">June 1998</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">400 MHz to 5.3 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">100 MT/s to 1.6 GT/s</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a> speeds</th><td class="infobox-data">4.8 GT/s to 24 GT/s</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> speeds</th><td class="infobox-data">2.0 GT/s to 16 GT/s</td></tr><tr><th scope="row" class="infobox-label">Data width</th><td class="infobox-data">Up to 64 bits</td></tr><tr><th scope="row" class="infobox-label">Address width</th><td class="infobox-data">Up to 64 bits</td></tr><tr><th scope="row" class="infobox-label">Virtual address width</th><td class="infobox-data">Up to 57 bits</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">Up to 80 KB per core</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">Up to 2 MB per core</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">Up to 320 MB per socket</td></tr><tr><th scope="row" class="infobox-label">L4 cache</th><td class="infobox-data">Up to 64<span class="nowrap"> </span>GB <a href="/wiki/High_Bandwidth_Memory#HBM2E" title="High Bandwidth Memory">HBM2e</a><sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Server_(computing)" title="Server (computing)">Servers</a></li><li><a href="/wiki/Workstation" title="Workstation">Workstations</a></li><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded systems</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">250 nm to Intel 3 and TSMC N5</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a></li><li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a></li><li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></li><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li><li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></li><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li><li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a></li><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li><li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a></li><li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a></li><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li><li><a href="/wiki/Golden_Cove_(microarchitecture)" class="mw-redirect" title="Golden Cove (microarchitecture)">Golden Cove</a></li><li><a href="/wiki/Golden_Cove_(microarchitecture)#Raptor_Cove" class="mw-redirect" title="Golden Cove (microarchitecture)">Raptor Cove</a></li><li><a href="/w/index.php?title=Redwood_Cove_(microarchitecture)&action=edit&redlink=1" class="new" title="Redwood Cove (microarchitecture) (page does not exist)">Redwood Cove</a></li><li><a href="/w/index.php?title=Crestmont_(microarchitecture)&action=edit&redlink=1" class="new" title="Crestmont (microarchitecture) (page does not exist)">Crestmont</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Instructions</th><td class="infobox-data"><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a>, <a href="/wiki/FMA3" class="mw-redirect" title="FMA3">FMA3</a>, <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a>, <a href="/wiki/Advanced_Vector_Extensions#AVX-VNNI" title="Advanced Vector Extensions">AVX-VNNI</a>, <a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a>, <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Intel_Software_Guard_Extensions" class="mw-redirect" title="Intel Software Guard Extensions">SGX</a>, <a href="/wiki/Intel_SHA_extensions" class="mw-redirect" title="Intel SHA extensions">SHA</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">TXT</a>, <a href="/wiki/VT-x" class="mw-redirect" title="VT-x">VT-x</a>, <a href="/wiki/VT-d" class="mw-redirect" title="VT-d">VT-d</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Up to 64 cores per socket (up to 128 threads per socket)</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Random-access_memory" title="Random-access memory">Memory (RAM)</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Up to 4 TB and 8 channels per socket</li><li>Up to <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 with <a href="/wiki/Error_correction_code" title="Error correction code">ECC</a> support</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></th><td class="infobox-data"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel Graphics Technology</a> (some models only)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Co-processor" class="mw-redirect" title="Co-processor">Co-processor</a></th><td class="infobox-data"><a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> (2010–2020)</td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Slot_2" title="Slot 2">Slot 2</a></li><li><a href="/wiki/Socket_603" title="Socket 603">Socket 603</a></li><li><a href="/wiki/Socket_604" title="Socket 604">Socket 604</a></li><li><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></li><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li><li><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></li><li><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></li><li><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></li><li><a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a></li><li><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></li><li><a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011-3</a></li><li><a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a></li><li><a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151v2</a></li><li><a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a></li><li><a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a></li><li><a href="/wiki/LGA_2066" title="LGA 2066">LGA 2066</a></li><li><a href="/wiki/LGA_3647" title="LGA 3647">LGA 3647</a></li><li><a href="/wiki/LGA_4189" title="LGA 4189">LGA 4189</a></li><li><a href="/wiki/LGA_4677" title="LGA 4677">LGA 4677</a></li><li><a href="/wiki/LGA_7529" title="LGA 7529">LGA 7529</a></li></ul></div></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon E</li><li>Xeon D</li><li>Xeon w3<sup id="cite_ref-Xeon_W_series_2-0" class="reference"><a href="#cite_note-Xeon_W_series-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li><li>Xeon w5<sup id="cite_ref-Xeon_W_series_2-1" class="reference"><a href="#cite_note-Xeon_W_series-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li><li>Xeon w7<sup id="cite_ref-Xeon_W_series_2-2" class="reference"><a href="#cite_note-Xeon_W_series-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li><li>Xeon w9<sup id="cite_ref-Xeon_W_series_2-3" class="reference"><a href="#cite_note-Xeon_W_series-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></li><li>Xeon Bronze</li><li>Xeon Silver</li><li>Xeon Gold</li><li>Xeon Platinum</li><li>Xeon Max<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></li></ul></div></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Variant</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Itanium" title="Itanium">Itanium</a> (2001–2020)</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a></td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Supported</td></tr></tbody></table> <p><b>Xeon</b> (<span class="rt-commentedText nowrap"><span class="IPA nopopups noexcerpt" lang="en-fonipa"><a href="/wiki/Help:IPA/English" title="Help:IPA/English">/<span style="border-bottom:1px dotted"><span title="/ˈ/: primary stress follows">ˈ</span><span title="'z' in 'zoom'">z</span><span title="/iː/: 'ee' in 'fleece'">iː</span><span title="/ɒ/: 'o' in 'body'">ɒ</span><span title="'n' in 'nigh'">n</span></span>/</a></span></span>; <a href="/wiki/Help:Pronunciation_respelling_key" title="Help:Pronunciation respelling key"><i title="English pronunciation respelling"><span style="font-size:90%">ZEE</span>-on</i></a>) is a brand of <a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> designed, manufactured, and marketed by <a href="/wiki/Intel" title="Intel">Intel</a>, targeted at the non-consumer <a href="/wiki/Workstation" title="Workstation">workstation</a>, <a href="/wiki/Server_(computing)" title="Server (computing)">server</a>, and <a href="/wiki/Embedded_system" title="Embedded system">embedded</a> markets. It was introduced in June 1998. Xeon processors are based on the same architecture as regular desktop-grade CPUs, but have advanced features such as support for <a href="/wiki/ECC_memory" title="ECC memory">error correction code (ECC) memory</a>, higher <a href="/wiki/Multi-core_processor" title="Multi-core processor">core</a> counts, more <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> lanes, support for larger amounts of RAM, larger <a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">cache memory</a> and extra provision for enterprise-grade <a href="/wiki/Reliability,_availability_and_serviceability" title="Reliability, availability and serviceability">reliability, availability and serviceability</a> (RAS) features responsible for handling hardware exceptions through the <a href="/wiki/Machine_Check_Architecture" title="Machine Check Architecture">Machine Check Architecture</a> (MCA). They are often capable of safely continuing execution where a normal processor cannot due to these extra RAS features, depending on the type and severity of the <a href="/wiki/Machine-check_exception" title="Machine-check exception">machine-check exception</a> (MCE). Some also support multi-socket systems with two, four, or eight sockets through use of the <a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Ultra Path Interconnect</a> (UPI) bus, which replaced the older <a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QuickPath Interconnect</a> (QPI) bus. </p> <figure class="mw-default-size mw-halign-center" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_E5-1620,_front_and_back.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_Xeon_E5-1620%2C_front_and_back.jpg/250px-Intel_Xeon_E5-1620%2C_front_and_back.jpg" decoding="async" width="220" height="133" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_Xeon_E5-1620%2C_front_and_back.jpg/330px-Intel_Xeon_E5-1620%2C_front_and_back.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_Xeon_E5-1620%2C_front_and_back.jpg/500px-Intel_Xeon_E5-1620%2C_front_and_back.jpg 2x" data-file-width="5524" data-file-height="3348" /></a><figcaption>Intel Xeon E5-1620's front and back</figcaption></figure> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Branding">Branding</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=1" title="Edit section: Branding"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <i>Xeon</i> brand has been maintained over several generations of <a href="/wiki/IA-32" title="IA-32">IA-32</a> and <a href="/wiki/X86-64" title="X86-64">x86-64</a> processors. The P6-based models added the <i>Xeon</i> moniker to the end of the name of their corresponding desktop processor, but all models since 2001 used the name <i>Xeon</i> on its own. The <i>Xeon</i> CPUs generally have more <a href="/wiki/CPU_cache" title="CPU cache">cache</a> and <a href="/wiki/Multi-core_processor" title="Multi-core processor">cores</a> than their desktop counterparts in addition to multiprocessing capabilities. </p> <style data-mw-deduplicate="TemplateStyles:r1273380762/mw-parser-output/.tmulti">.mw-parser-output .tmulti .multiimageinner{display:flex;flex-direction:column}.mw-parser-output .tmulti .trow{display:flex;flex-direction:row;clear:left;flex-wrap:wrap;width:100%;box-sizing:border-box}.mw-parser-output .tmulti .tsingle{margin:1px;float:left}.mw-parser-output .tmulti .theader{clear:both;font-weight:bold;text-align:center;align-self:center;background-color:transparent;width:100%}.mw-parser-output .tmulti .thumbcaption{background-color:transparent}.mw-parser-output .tmulti .text-align-left{text-align:left}.mw-parser-output .tmulti .text-align-right{text-align:right}.mw-parser-output .tmulti .text-align-center{text-align:center}@media all and (max-width:720px){.mw-parser-output .tmulti .thumbinner{width:100%!important;box-sizing:border-box;max-width:none!important;align-items:center}.mw-parser-output .tmulti .trow{justify-content:center}.mw-parser-output .tmulti .tsingle{float:none!important;max-width:100%!important;box-sizing:border-box;text-align:center}.mw-parser-output .tmulti .tsingle .thumbcaption{text-align:left}.mw-parser-output .tmulti .trow>.thumbcaption{text-align:center}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .tmulti .multiimageinner span:not(.skin-invert-image):not(.skin-invert):not(.bg-transparent) img{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .tmulti .multiimageinner span:not(.skin-invert-image):not(.skin-invert):not(.bg-transparent) img{background-color:white}}</style><div class="thumb tmulti tnone center"><div class="thumbinner multiimageinner" style="width:293px;max-width:293px"><div class="trow"><div class="theader" style="text-align:center">Xeon branding</div></div><div class="trow"><div class="tsingle" style="margin-right:10px;width:140px;max-width:140px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel_Xeon_(2020).svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/Intel_Xeon_%282020%29.svg/250px-Intel_Xeon_%282020%29.svg.png" decoding="async" width="138" height="138" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/Intel_Xeon_%282020%29.svg/330px-Intel_Xeon_%282020%29.svg.png 2x" data-file-width="992" data-file-height="992" /></a></span></div><div class="thumbcaption text-align-center">(2020–2023)</div></div><div class="tsingle" style="width:140px;max-width:140px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Badge-2024.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/Intel-Xeon-Badge-2024.jpg/250px-Intel-Xeon-Badge-2024.jpg" decoding="async" width="138" height="138" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/31/Intel-Xeon-Badge-2024.jpg/330px-Intel-Xeon-Badge-2024.jpg 2x" data-file-width="3000" data-file-height="3000" /></a></span></div><div class="thumbcaption text-align-center">(2024–present)</div></div></div></div></div> <div class="mw-heading mw-heading3"><h3 id="Xeon_Scalable">Xeon Scalable</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=2" title="Edit section: Xeon Scalable"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Xeon Scalable brand for high-performance server was introduced in May 2017 with the Skylake-based Xeon Platinum 8100 series. Xeon Scalable processors range from dual socket to 8 socket support. Within the Xeon Scalable brand, there exists the hierarchy of Xeon Bronze, Silver, Gold and Platinum. </p> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1273380762/mw-parser-output/.tmulti" /><div class="thumb tmulti tnone center"><div class="thumbinner multiimageinner" style="width:591px;max-width:591px"><div class="trow"><div class="theader" style="text-align:center">Xeon Scalable branding</div></div><div class="trow"><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Bronze-Badge-2017.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/8/86/Intel-Xeon-Bronze-Badge-2017.png/250px-Intel-Xeon-Bronze-Badge-2017.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/86/Intel-Xeon-Bronze-Badge-2017.png/330px-Intel-Xeon-Bronze-Badge-2017.png 2x" data-file-width="1280" data-file-height="1280" /></a></span></div><div class="thumbcaption text-align-center">Xeon Bronze <br /> (2017–2019)</div></div><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Silver-Badge-2017.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Intel-Xeon-Silver-Badge-2017.png/137px-Intel-Xeon-Silver-Badge-2017.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Intel-Xeon-Silver-Badge-2017.png/206px-Intel-Xeon-Silver-Badge-2017.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c2/Intel-Xeon-Silver-Badge-2017.png/274px-Intel-Xeon-Silver-Badge-2017.png 2x" data-file-width="1280" data-file-height="1280" /></a></span></div><div class="thumbcaption text-align-center">Xeon Silver <br /> (2017–2019)</div></div><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Gold-Badge-2017.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/Intel-Xeon-Gold-Badge-2017.png/137px-Intel-Xeon-Gold-Badge-2017.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4f/Intel-Xeon-Gold-Badge-2017.png/206px-Intel-Xeon-Gold-Badge-2017.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4f/Intel-Xeon-Gold-Badge-2017.png/274px-Intel-Xeon-Gold-Badge-2017.png 2x" data-file-width="1280" data-file-height="1280" /></a></span></div><div class="thumbcaption text-align-center">Xeon Gold <br /> (2017–2019)</div></div><div class="tsingle" style="width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Platinum-Badge-2017.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/Intel-Xeon-Platinum-Badge-2017.png/250px-Intel-Xeon-Platinum-Badge-2017.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cd/Intel-Xeon-Platinum-Badge-2017.png/330px-Intel-Xeon-Platinum-Badge-2017.png 2x" data-file-width="1280" data-file-height="1280" /></a></span></div><div class="thumbcaption text-align-center">Xeon Platinum <br /> (2017–2019)</div></div></div><div class="trow"><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Bronze-Badge-2020.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/7/71/Intel-Xeon-Bronze-Badge-2020.png/137px-Intel-Xeon-Bronze-Badge-2020.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/71/Intel-Xeon-Bronze-Badge-2020.png/206px-Intel-Xeon-Bronze-Badge-2020.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/71/Intel-Xeon-Bronze-Badge-2020.png/274px-Intel-Xeon-Bronze-Badge-2020.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div><div class="thumbcaption text-align-center">Xeon Bronze <br /> (2020–2023)</div></div><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Silver-Badge-2020.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/Intel-Xeon-Silver-Badge-2020.png/250px-Intel-Xeon-Silver-Badge-2020.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/Intel-Xeon-Silver-Badge-2020.png/330px-Intel-Xeon-Silver-Badge-2020.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div><div class="thumbcaption text-align-center">Xeon Silver <br /> (2020–2023)</div></div><div class="tsingle" style="margin-right:10px;width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Gold-Badge-2020.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/c/ca/Intel-Xeon-Gold-Badge-2020.png/250px-Intel-Xeon-Gold-Badge-2020.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/ca/Intel-Xeon-Gold-Badge-2020.png/330px-Intel-Xeon-Gold-Badge-2020.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div><div class="thumbcaption text-align-center">Xeon Gold <br /> (2020–2023)</div></div><div class="tsingle" style="width:139px;max-width:139px"><div class="thumbimage" style="height:137px;overflow:hidden"><span typeof="mw:File"><a href="/wiki/File:Intel-Xeon-Platinum-Badge-2020.png" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/7/73/Intel-Xeon-Platinum-Badge-2020.png/250px-Intel-Xeon-Platinum-Badge-2020.png" decoding="async" width="137" height="137" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/73/Intel-Xeon-Platinum-Badge-2020.png/330px-Intel-Xeon-Platinum-Badge-2020.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div><div class="thumbcaption text-align-center">Xeon Platinum <br /> (2020–2023)</div></div></div></div></div> <p>In April 2024, Intel announced at its Vision event that the Xeon Scalable brand would be retired, beginning with 6th generation Xeon processors codenamed <a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a> and <a href="/wiki/Granite_Rapids" title="Granite Rapids">Granite Rapids</a> that will now be referred to as "Xeon 6" processors.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> This change brings greater emphasis on processor generation numbers.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Xeon_6">Xeon 6</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=3" title="Edit section: Xeon 6"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>With the launch of Intel's <a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a> line of processors, branding for mainstream server processors switched to Xeon #, with the # being the generation of the processor, such as Xeon 6 for the 6th generation of Xeon processors, this naming convention also carries over to the Granite Rapids line of server CPUs.<sup id="cite_ref-:0_6-0" class="reference"><a href="#cite_note-:0-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>Xeon 6 is split into two product lines, the E series and P series, which, respectively, are all E core and all P core designs. For example, the Xeon 6 6700E line is an all <a href="/wiki/Intel_Core" title="Intel Core">E core</a> based (Sierra Forest) line of processors.<sup id="cite_ref-:0_6-1" class="reference"><a href="#cite_note-:0-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Xeon_D">Xeon D</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=4" title="Edit section: Xeon D"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Xeon_D" title="Xeon D">Xeon D</a> is targeted towards microserver and edge computing markets with lower power consumption and integrated I/O blocks such as <a href="/wiki/Network_interface_controller" title="Network interface controller">network interface controllers</a>. This allows Xeon D processors to function as SoCs that do not require a separate southbridge PCH.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> It was announced in 2014 and the first Xeon D processors were released in March 2015. Xeon D processors come in an <a href="/wiki/Solder_ball" title="Solder ball">soldered</a> <a href="/wiki/Ball_grid_array" title="Ball grid array">BGA</a> package rather than in a socketable form factor. Xeon D was introduced to compete with emerging ARM hyperscale server solutions that offered greater multi-threaded performance and power effiency.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Xeon_W">Xeon W</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=5" title="Edit section: Xeon W"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Xeon_W" title="Xeon W">Xeon W</a> branding is used for Xeon workstation processors. It was first introduced in August 2017 with the release of the <a href="/wiki/Skylake_(microarchitecture)#Workstation_processors" title="Skylake (microarchitecture)">Skylake</a>-based Xeon W-2100 series workstation processors. With Sapphire Rapids-WS workstation processors that launched in March 2023, Intel introduced tiers within Xeon W. Xeon w3, w5, w7 and w9 was designed to emulate the Core i3, i5, i7 and i9 branding that Intel had been using for its desktop processors. </p> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=6" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Some shortcomings that make Xeon processors unsuitable for most consumer-grade desktop PCs include lower <a href="/wiki/Clock_rate" title="Clock rate">clock rates</a> at the same price point (since servers run more tasks in parallel than desktops, core counts are more important than clock rates), and, usually, the lack of an integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing unit</a> (GPU). Processor models prior to <a href="/wiki/Sapphire_Rapids#Sapphire_Rapids-WS_(Workstation)" title="Sapphire Rapids">Sapphire Rapids-WS</a> lack support for <a href="/wiki/Overclocking" title="Overclocking">overclocking</a> (with the exception of <a href="/wiki/Skylake_(microarchitecture)#Xeon_High-end_desktop_processors_(Skylake-X)" title="Skylake (microarchitecture)">Xeon W-3175X</a>). Despite such disadvantages, Xeon processors have always had popularity among some desktop users (video editors and other <a href="/wiki/Power_user" title="Power user">power users</a>), mainly due to higher core count potential, and higher performance to price ratio vs. the <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a> in terms of total computing power of all cores. Since most Intel Xeon CPUs lack an integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a>, systems built with those processors require a discrete graphics card or a separate GPU if <a href="/wiki/Computer_monitor" title="Computer monitor">computer monitor</a> output is desired. </p><p>Intel Xeon is a distinct product line from the similarly named Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a>. The first-generation Xeon Phi is a completely different type of device more comparable to a graphics card; it is designed for a <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> slot and is meant to be used as a multi-core coprocessor, like the <a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a>. In the second generation, Xeon Phi evolved into a main processor more similar to the Xeon. It conforms to the same socket as a Xeon processor and is x86-compatible; however, as compared to Xeon, the design point of the Xeon Phi emphasizes more cores with higher memory bandwidth. </p> <table class="wikitable" style="border:0; font-size:90%; background:white"> <caption>Intel Xeon processor family: <a href="/wiki/Server_(computing)" title="Server (computing)">Server</a> </caption> <tbody><tr> <th width="10px!" style="background-color: #FFF; border-width:0;"> </th> <th colspan="3" style="background-color:#dff;">1 or 2 Sockets<br /><small>UP/DP/3000/5000/E3/E5-1xxx and 2xxx/E7-2xxx/D/E/W series<br />Bronze/Silver/Gold (non H)/Platinum (non H)/Max</small> </th> <th colspan="3" style="background-color:#dff;">4 or 8 Sockets<br /><small>MP/7000/E5-4xxx/E7-4xxx and 8xxx series</small><small>Gold (H)/Platinum (H)</small> </th></tr> <tr> <th style="text-align:left; vertical-align: bottom;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;">Node</div></th> <th>Code named</th> <th># of<br />Cores</th> <th>Release<br />date</th> <th>Code named</th> <th># of<br />Cores</th> <th>Release<br />date </th></tr> <tr style="background-color:#F8EEDD;"> <td rowspan="2" style="text-align:left; vertical-align: bottom;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>250 nm</b></div> </td> <td colspan="3" rowspan="2" style="background-color: #FFF;"></td> <td><abbr title="Pentium II based">Drake</abbr></td> <td>1</td> <td>Jun 1998 </td></tr> <tr style="background-color:#F8EEDD;"> <td>Tanner</td> <td>1</td> <td>Mar 1999 </td></tr> <tr style="background-color:#FFF8EE;"> <td rowspan="2" style="text-align:left; vertical-align: bottom;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>180 nm</b></div> </td> <td>Cascades (256 KB L2 cache)</td> <td>1</td> <td>Oct 1999</td> <td>Cascades (700 and 900 MHz models only)</td> <td>1</td> <td>May 2000 </td></tr> <tr style="background-color:#FFF8EE;"> <td><abbr title="Pentium 4 based">Foster</abbr></td> <td>1</td> <td>May 2001</td> <td><abbr title="Pentium 4 based">Foster MP</abbr></td> <td>1</td> <td>Mar 2002 </td></tr> <tr style="background-color:#F8F6F8;"> <td rowspan="2" style="text-align:left; vertical-align: bottom;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>130 nm</b></div> </td> <td>Prestonia</td> <td>1</td> <td>Feb 2002</td> <td colspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#F8F6F8;"> <td>Gallatin DP</td> <td>1</td> <td>Jul 2003</td> <td>Gallatin</td> <td>1</td> <td>Nov 2002 </td></tr> <tr style="background-color:#EEF6EE;"> <td rowspan="4" style="text-align:left; vertical-align:center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>90 nm</b></div> </td> <td><abbr title="64 bit Architecture">Nocona</abbr></td> <td>1</td> <td>Jun 2004 </td> <td><abbr title="64 bit Architecture">Cranford</abbr></td> <td>1</td> <td>Mar 2005 </td></tr> <tr style="background-color:#EEF8EE;"> <td colspan="3" style="background-color: #FFF;"></td> <td>Potomac</td> <td>1</td> <td>Mar 2005 </td></tr> <tr style="background-color:#EEF8EE;"> <td><abbr title="64 bit Architecture">Irwindale</abbr></td> <td>1</td> <td>Feb 2005</td> <td colspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#EEF8EE;"> <td>Paxville DP</td> <td>2</td> <td>Oct 2005</td> <td>Paxville</td> <td>2</td> <td>Nov 2005 </td></tr> <tr style="background-color:#EEF8F8;"> <td rowspan="7" style="text-align:left; vertical-align: center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>65 nm</b></div> </td> <td>Dempsey</td> <td>2</td> <td>May 2006</td> <td>Tulsa</td> <td>2</td> <td>Aug 2006 </td></tr> <tr style="background-color:#EEF8F8;"> <td>Sossaman</td> <td>2</td> <td>Mar 2006</td> <td colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#EEF8F8;"> <td>Woodcrest</td> <td>2</td> <td>Jun 2006 </td></tr> <tr style="background-color:#EEF8F8;"> <td>Conroe</td> <td>2</td> <td>Oct 2006 </td></tr> <tr style="background-color:#EEF8F8;"> <td>Clovertown</td> <td>4</td> <td>Nov 2006</td> <td>Tigerton/Tigerton QC</td> <td>2/4</td> <td>Sep 2007 </td></tr> <tr style="background-color:#EEF8F8;"> <td>Allendale</td> <td>2</td> <td>Jan 2007</td> <td colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#EEF8F8;"> <td>Kentsfield</td> <td>4</td> <td>Jan 2007 </td></tr> <tr style="background-color:#EEF5FF;"> <td rowspan="8" style="text-align:left; vertical-align: center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>45 nm</b></div> </td> <td>Wolfdale DP</td> <td>2</td> <td>Nov 2007 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Harpertown</td> <td>4</td> <td>Nov 2007</td> <td>Dunnington QC/Dunnington</td> <td>4/6</td> <td>Sep 2008 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Wolfdale</td> <td>2</td> <td>Feb 2008</td> <td colspan="3" rowspan="5" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#EEF5FF;"> <td>Yorkfield</td> <td>4</td> <td>Mar 2008 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Bloomfield (W35xx)</td> <td>4</td> <td>Mar 2009 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Gainestown (55xx)</td> <td>2/4</td> <td>Mar 2009 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Lynnfield (34xx)</td> <td>4</td> <td>Sep 2009 </td></tr> <tr style="background-color:#EEF5FF;"> <td>Beckton (65xx)</td> <td>4/6/8</td> <td>Mar 2010</td> <td>Beckton (75xx)</td> <td>4-8</td> <td>Mar 2010 </td></tr> <tr style="background-color:#EEEEFF;"> <td rowspan="5" style="text-align:left; vertical-align: center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>32 nm</b></div> </td> <td>Westmere-EP (56xx)</td> <td>2-6</td> <td>Mar 2010</td> <td colspan="3" rowspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#EEEEFF;"> <td>Gulftown (W36xx)</td> <td>6</td> <td>Mar 2010 </td></tr> <tr style="background-color:#EEEEFF;"> <td>Clarkdale (L34xx)</td> <td>2</td> <td>Mar 2010 </td></tr> <tr style="background-color:#EEEEFF;"> <td>Westmere-EX (E7-2xxx)</td> <td>6-10</td> <td>Apr 2011</td> <td>Westmere-EX (E7-4xxx/8xxx)</td> <td>6-10</td> <td>Apr 2011 </td></tr> <tr style="background-color:#EEEEFF;"> <td>Sandy Bridge-DT/EN/EP</td> <td>2-8</td> <td>Mar 2012</td> <td>Sandy Bridge-EP (E5-46xx)</td> <td>4-8</td> <td>May 2012 </td></tr> <tr style="background-color:#F8ECFC;"> <td rowspan="4" style="text-align:left; vertical-align:center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>22 nm</b></div> </td> <td>Ivy Bridge (E3/E5-1xxx/E5-2xxx v2)</td> <td>2-12</td> <td>Sep 2013</td> <td>Ivy Bridge-EP (E5-46xx v2)</td> <td>4-12</td> <td>Mar 2014 </td></tr> <tr style="background-color:#F8ECFC;"> <td>Ivy Bridge-EX (E7-28xx v2)</td> <td>12/15</td> <td>Feb 2014</td> <td>Ivy Bridge-EX (E7-48xx/88xx v2)</td> <td>6-12/15</td> <td>Feb 2014 </td></tr> <tr style="background-color:#F8ECFC;"> <td>Haswell (E3/E5-1xxx/E5-2xxx v3)</td> <td>2-18</td> <td>Sep 2014</td> <td>Haswell-EP (E5-46xx v3)</td> <td>6-18</td> <td>Jun 2015 </td></tr> <tr style="background-color:#F8ECFC;"> <td colspan="3" style="background-color: #FFF;"></td> <td>Haswell-EX (E7-48xx/88xx v3)</td> <td>4-18</td> <td>May 2015 </td></tr> <tr style="background-color:#F8EEDD;"> <td rowspan="6" style="text-align:left; vertical-align:center;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>14 nm</b></div> </td> <td>Broadwell (E3/E5-1xxx/E5-2xxx v4)</td> <td>4-22</td> <td>Jun 2015</td> <td colspan="3" style="background-color: #FFF; border-width:0;" rowspan="3"> </td></tr> <tr style="background-color:#F8EEDD;"> <td>Skylake-S/H (E3-1xxx v5)</td> <td>4</td> <td>Oct 2015 </td></tr> <tr style="background-color:#F8EEDD;"> <td>Kaby Lake-S/H (E3-1xxx v6)</td> <td>4</td> <td>Mar 2017 </td></tr> <tr style="background-color:#F8EEDD;"> <td>Skylake-W/SP (Bronze and Silver)</td> <td>4-28</td> <td>Jun 2017</td> <td>Skylake-SP (Gold and Platinum)</td> <td>4-28</td> <td>Jul 2017 </td></tr> <tr style="background-color:#F8EEDD;"> <td><span class="nowrap">Cascade Lake-W/SP (Bronze/Silver/R/U)</span></td> <td>4-28</td> <td>Apr 2019</td> <td><span class="nowrap">Cascade Lake-SP (Gold (non-R/U)/Platinum)</span></td> <td>4-28</td> <td>Apr 2019 </td></tr> <tr style="background-color:#F8EEDD;"> <td colspan="3" style="background-color: #FFF;"></td> <td>Cooper Lake-SP</td> <td>8-28</td> <td>Jun 2020 </td></tr> <tr style="background-color:#FAF2C8;"> <td rowspan="2" style="text-align:left; vertical-align:bottom;"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>10 nm</b></div> </td> <td>Ice Lake-SP/W</td> <td>8-40</td> <td>Apr 2021</td> <td colspan="3" rowspan="2" style="background-color: #FFF; border-width:0;"> </td></tr> <tr style="background-color:#FAF2C8;"> <td>Ice Lake-D</td> <td>2-20</td> <td>Feb 2022 </td></tr> <tr style="background-color:#FDFFC2;"> <td rowspan="2"><div style="display: inline-block; transform: rotate(-90deg);; width:12px !important;"><b>Intel 7</b></div></td> <td>Sapphire Rapids-SP/WS/HBM</td> <td>6-56</td> <td>Jan 2023</td> <td>Sapphire Rapids-SP</td> <td>8-60</td> <td>Jan 2023 </td></tr> <tr style="background-color:#FDFFC2;"> <td>Emerald Rapids-SP</td> <td>8-64</td> <td>Dec 2023</td> <td colspan="3" style="background-color: #FFF; border-width:0;"> </td></tr> <tr> <th colspan="7"><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">List of Intel Xeon processors</a> </th></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="P6-based_Xeon">P6-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=7" title="Edit section: P6-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Pentium_II_Xeon"><span class="anchor" id="Drake"></span>Pentium II Xeon</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=8" title="Edit section: Pentium II Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors#"Drake"_(250_nm)" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">List of Intel P6-based Xeon microprocessors § "Drake" (250 nm)</a></div> <figure class="mw-default-size mw-halign-left" typeof="mw:File/Thumb"><a href="/wiki/File:Pentium_II_Xeon_450_512.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/Pentium_II_Xeon_450_512.jpg/310px-Pentium_II_Xeon_450_512.jpg" decoding="async" width="310" height="226" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/Pentium_II_Xeon_450_512.jpg/465px-Pentium_II_Xeon_450_512.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/6/66/Pentium_II_Xeon_450_512.jpg 2x" data-file-width="600" data-file-height="438" /></a><figcaption>450 MHz Pentium II Xeon with 512 KB L2 cache: The cartridge cover has been removed.</figcaption></figure> <p>The first Xeon-branded processor was the Pentium II Xeon (code-named "<b>Drake</b>"). It was released in 1998, replacing the <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> in Intel's high-end server lineup. The Pentium II Xeon was a "<i><a href="/wiki/Deschutes_(microprocessor)" class="mw-redirect" title="Deschutes (microprocessor)">Deschutes</a></i>" <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a> (and shared the same product code: 80523) with a full-speed 512 kB (1 kB = 1024 B), 1 MB (1 MB = 1024 kB = 1024<sup>2</sup> B), or 2 MB <a href="/wiki/CPU_cache" title="CPU cache">L2 cache</a>. The L2 cache was implemented with custom 512 kB SRAMs developed by Intel. The number of SRAMs depended on the amount of cache. A 512 kB configuration required one SRAM, a 1 MB configuration: two SRAMs, and a 2 MB configuration: four SRAMs on both sides of the PCB. Each SRAM was a 12.90 mm by 17.23 mm (222.21 mm<sup>2</sup>) die fabricated in a 0.35 μm four-layer metal CMOS process and packaged in a cavity-down wire-bonded <a href="/wiki/Land_grid_array" title="Land grid array">land grid array</a> (LGA).<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> The additional cache required a larger module and thus the Pentium II Xeon used a larger slot, <a href="/wiki/Slot_2" title="Slot 2">Slot 2</a>. It was supported by the <a href="/w/index.php?title=Intel_440GX&action=edit&redlink=1" class="new" title="Intel 440GX (page does not exist)">i440GX</a> dual-processor workstation <a href="/wiki/Chipset" title="Chipset">chipset</a> and the <a href="/w/index.php?title=Intel_450NX&action=edit&redlink=1" class="new" title="Intel 450NX (page does not exist)">i450NX</a> quad- or octo-processor server chipset. </p> <div class="mw-heading mw-heading3"><h3 id="Pentium_III_Xeon"><span class="anchor" id="Tanner"></span><span class="anchor" id="Cascades"></span>Pentium III Xeon</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=9" title="Edit section: Pentium III Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors#"Tanner"_(250_nm)" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">List of Intel P6-based Xeon microprocessors § "Tanner" (250 nm)</a>, and <a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors#"Cascades"_(180_nm)" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">§ "Cascades" (180 nm)</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg/220px-Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg" decoding="async" width="220" height="286" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg/330px-Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/02/Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg/440px-Intel_Pentium_III_Xeon_550_MHz_Slot_2_geoeffnet.jpg 2x" data-file-width="1229" data-file-height="1600" /></a><figcaption>Back of a Pentium III Xeon with its cover set aside; there is a heatsink on the front side (underneath) of the circuit board.</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_pentium_iii_xeon_800_sl4h8_observe.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Intel_pentium_iii_xeon_800_sl4h8_observe.png/220px-Intel_pentium_iii_xeon_800_sl4h8_observe.png" decoding="async" width="220" height="186" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Intel_pentium_iii_xeon_800_sl4h8_observe.png/330px-Intel_pentium_iii_xeon_800_sl4h8_observe.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b8/Intel_pentium_iii_xeon_800_sl4h8_observe.png/440px-Intel_pentium_iii_xeon_800_sl4h8_observe.png 2x" data-file-width="1109" data-file-height="938" /></a><figcaption>Front of a Pentium III Xeon circuit board without its heatsink</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel@180nm@P6@Cascades@Pentium_III_Xeon@SL4XW_DSCx1_polysilicon_microscope_stitched@5x_(24203772488).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/7c/Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg/220px-Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg" decoding="async" width="220" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/7c/Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg/330px-Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/7c/Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg/440px-Intel%40180nm%40P6%40Cascades%40Pentium_III_Xeon%40SL4XW_DSCx1_polysilicon_microscope_stitched%405x_%2824203772488%29.jpg 2x" data-file-width="11880" data-file-height="9699" /></a><figcaption>Die shot of a Cascades Pentium III Xeon</figcaption></figure> <p>In 1999, the <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a> Xeon was replaced by the <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a> Xeon. Reflecting the incremental changes from the Pentium II "<i><a href="/wiki/Deschutes_(microprocessor)" class="mw-redirect" title="Deschutes (microprocessor)">Deschutes</a></i>" core to the Pentium III "<i><a href="/wiki/Katmai_(microprocessor)" class="mw-redirect" title="Katmai (microprocessor)">Katmai</a></i>" core, the first Pentium III Xeon, named "<b>Tanner</b>", was just like its predecessor except for the addition of <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE) and a few cache controller improvements. The product codes for <b>Tanner</b> mirrored that of <i>Katmai</i>; 80525. </p><p>The second version, named "<b>Cascades</b>", was based on the Pentium III "<i><a href="/wiki/Coppermine_(microprocessor)" class="mw-redirect" title="Coppermine (microprocessor)">Coppermine</a></i>" core. The "<b>Cascades</b>" Xeon used a 133 MT/s front side bus and relatively small 256 kB on-die L2 cache resulting in almost the same capabilities as the <a href="/wiki/Slot_1" title="Slot 1">Slot 1</a> <i>Coppermine</i> processors, which were capable of dual-processor operation but not quad-processor or octa-processor operation. </p><p>To improve this situation, Intel released another version, officially also named "<b>Cascades</b>", but often referred to as "<b>Cascades 2 MB</b>". That came in two variants: with 1 MB or 2 MB of L2 cache. Its bus speed was fixed at 100 MT/s, though in practice the cache was able to offset this. The product code for <b>Cascades</b> mirrored that of <i>Coppermine</i>; 80526. </p> <div class="mw-heading mw-heading2"><h2 id="NetBurst-based_Xeon">NetBurst-based Xeon <span class="anchor" id="Netburst-based_Xeon"></span></h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=10" title="Edit section: NetBurst-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Xeon_(DP)_and_Xeon_MP_(32-bit)"><span id="Xeon_.28DP.29_and_Xeon_MP_.2832-bit.29"></span>Xeon (DP) and Xeon MP (32-bit)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=11" title="Edit section: Xeon (DP) and Xeon MP (32-bit)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Foster">Foster</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=12" title="Edit section: Foster"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Foster"_(180_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Foster" (180 nm)</a>, and <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Foster_MP"_(180_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">§ "Foster MP" (180 nm)</a></div> <p>In mid-2001, the Xeon brand was introduced ("Pentium" was dropped from the name). The initial variant that used the new <a href="/wiki/NetBurst" title="NetBurst">NetBurst microarchitecture</a>, "<b>Foster</b>", was slightly different from the desktop <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> ("<i><a href="/wiki/Pentium_4#Willamette" title="Pentium 4">Willamette</a></i>"). It was a decent<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag may need clarification or removal of jargon. (March 2017)">clarification needed</span></a></i>]</sup> chip for workstations, but for server applications it was almost always outperformed by the older Cascades cores with a 2 MB L2 cache and AMD's <a href="/wiki/Athlon" title="Athlon">Athlon MP</a><sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:AUDIENCE" class="mw-redirect" title="Wikipedia:AUDIENCE"><span title="An editor has requested that an example be provided. (March 2017)">example needed</span></a></i>]</sup>. Combined with the need to use expensive <a href="/wiki/RDRAM" title="RDRAM">Rambus Dynamic RAM</a>, the Foster's sales were somewhat unimpressive<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:AUDIENCE" class="mw-redirect" title="Wikipedia:AUDIENCE"><span title="An editor has requested that an example be provided. (March 2017)">example needed</span></a></i>]</sup>. </p><p>At most two Foster processors could be accommodated in a <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP) system built with a mainstream chipset, so a second version (<b>Foster MP</b>) was introduced with 512 KB or 1 MB L3 cache and the Jackson <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-Threading</a> capacity. This improved performance slightly, but not enough to lift it out of third place. It was also priced much higher than the dual-processor (DP) versions. The <i>Foster</i> shared the 80528 product code with Willamette. </p> <div class="mw-heading mw-heading4"><h4 id="Prestonia">Prestonia</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=13" title="Edit section: Prestonia"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Prestonia"_(130_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Prestonia" (130 nm)</a></div> <p>In 2002 Intel released a <a href="/wiki/130_nanometer" class="mw-redirect" title="130 nanometer">130 nm</a> version of Xeon branded CPU, codenamed "<b>Prestonia</b>". It supported Intel's new Hyper-Threading technology and had a 512 kB L2 cache. This was based on the "<i><a href="/wiki/Pentium_4#Northwood" title="Pentium 4">Northwood</a></i>" Pentium 4 core. A new server chipset, <a href="/wiki/Intel_Xeon_chipsets#NetBurst-based_Xeon_chipsets" class="mw-redirect" title="Intel Xeon chipsets">E7500</a> (which allowed the use of dual-channel <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>), was released to support this processor in servers, and soon the bus speed was boosted to 533 MT/s (accompanied by a new socket and two new chipsets: the E7501 for servers and the E7505 for workstations). The <i>Prestonia</i> performed much better than its predecessor and noticeably better than Athlon MP. The support of new features in the E75xx series also gave it a key advantage over the Pentium III Xeon and Athlon MP branded CPUs (both stuck with rather old chipsets), and it quickly became the top-selling server/workstation processor. </p> <div class="mw-heading mw-heading4"><h4 id="Gallatin"><span class="anchor" id="Gallatin"></span> Gallatin</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=14" title="Edit section: Gallatin"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Gallatin</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Xeon_DP_Gallatin_(SL7AE),_Socket_604.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/45/Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg/250px-Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg" decoding="async" width="220" height="201" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/45/Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg/330px-Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/45/Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg/500px-Xeon_DP_Gallatin_%28SL7AE%29%2C_Socket_604.jpg 2x" data-file-width="760" data-file-height="696" /></a></span></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">March 2003</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2004</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">0F7x</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80537</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.50 GHz to 3.20 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">400 MT/s to 533 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">8 kB + 12 kuOps trace cache</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">512 kB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">1 MB, 2 MB, 4 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP and MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">130 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>1</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_603" title="Socket 603">Socket 603</a> <a href="/wiki/Socket_604" title="Socket 604">Socket 604</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon</li></ul></div></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Gallatin"_(130_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Gallatin" (130 nm)</a>, and <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Gallatin"_(130_nm)_2" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">§ "Gallatin" MP (130 nm)</a></div> <p>Subsequent to the <i>Prestonia</i> was the "<b>Gallatin</b>", which had an L3 cache of 1 MB or 2 MB. Its Xeon MP version, which succeeded <i>Foster MP</i>, was popular in servers. Later experience with the 130 nm process allowed Intel to create the Xeon MP branded <i>Gallatin</i> with 4 MB cache. The Xeon branded <i>Prestonia</i> and <i>Gallatin</i> were designated 80532, like Northwood. </p> <div class="mw-heading mw-heading3"><h3 id="Xeon_(DP)_and_Xeon_MP_(64-bit)"><span id="Xeon_.28DP.29_and_Xeon_MP_.2864-bit.29"></span>Xeon (DP) and Xeon MP (64-bit)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=15" title="Edit section: Xeon (DP) and Xeon MP (64-bit)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Nocona_and_Irwindale">Nocona and Irwindale</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=16" title="Edit section: Nocona and Irwindale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Pentium 4 § Prescott</a>, <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Nocona"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Nocona" (90 nm)</a>, and <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Irwindale"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">§ "Irwindale" (90 nm)</a></div> <p>Due to a lack of success with Intel's <a href="/wiki/Itanium" title="Itanium">Itanium</a> and Itanium 2 processors, AMD was able to introduce <a href="/wiki/X86-64" title="X86-64">x86-64</a>, a 64-bit extension to the <a href="/wiki/X86_architecture" class="mw-redirect" title="X86 architecture">x86 architecture</a>. Intel followed suit by including <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a> (formerly EM64T; it is almost identical to <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>) in the <a href="/wiki/90_nanometer" class="mw-redirect" title="90 nanometer">90 nm</a> version of the Pentium 4 ("<i><a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Prescott</a></i>"), and a Xeon version codenamed "<b>Nocona</b>" with 1 MB L2 cache was released in 2004. Released with it were the E7525 (workstation), E7520 and E7320 (both server) chipsets, which added support for <a href="/wiki/PCI_Express#PCI_Express_1.0a" title="PCI Express">PCI Express 1.0a</a>, <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> and <a href="/wiki/SATA#SATA_revision_1.0_(1.5_Gbit/s,_150_MB/s,_Serial_ATA-150)" title="SATA">Serial ATA 1.0a</a>. The Xeon was noticeably slower than AMD's Opteron, although it could be faster in situations where Hyper-Threading came into play. </p><p>A slightly updated core called "<b>Irwindale</b>" was released in early 2005, with 2 MB L2 cache and the ability to have its clock speed reduced during low processor demand. Although it was a bit more competitive than the <i>Nocona</i> had been, independent <a rel="nofollow" class="external text" href="https://web.archive.org/web/20051228212744/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2591">tests</a> showed that AMD's Opteron still outperformed <i>Irwindale</i>. Both of these Prescott-derived Xeons have the product code 80546. </p> <div class="mw-heading mw-heading4"><h4 id="Cranford_and_Potomac">Cranford and Potomac</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=17" title="Edit section: Cranford and Potomac"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Pentium 4 § Prescott</a>, <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Cranford"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Cranford" (90 nm)</a>, and <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Potomac"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">§ "Potomac" (90 nm)</a></div> <p>64-bit Xeon MPs were introduced in April 2005. The cheaper "<b>Cranford</b>" was an MP version of <i>Nocona</i>, while the more expensive "<b>Potomac</b>" was a <i>Cranford</i> with 8 MB of L3 cache. Like Nocona and Irwindale, they also have product code 80546. </p> <div class="mw-heading mw-heading3"><h3 id="Dual-Core_Xeon">Dual-Core Xeon</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=18" title="Edit section: Dual-Core Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id=""Paxville_DP""><span id=".22Paxville_DP.22"></span>"Paxville DP"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=19" title="Edit section: "Paxville DP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Paxville_DP"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Paxville DP" (90 nm)</a>, and <a href="/wiki/Pentium_D#Smithfield" title="Pentium D">Pentium D § Smithfield</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Paxville</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">October 2005</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">August 2008</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">0F48</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80551, 80560</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2.667 GHz to 3.0 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">667 MT/s to 800 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2×2 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server, MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">90 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_604" title="Socket 604">Socket 604</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon</li></ul></div></td></tr></tbody></table> <p>The first <a href="/wiki/Multi-core_(computing)" class="mw-redirect" title="Multi-core (computing)">dual-core</a> CPU branded Xeon, codenamed <b>Paxville DP</b>, product code 80551, was released by Intel on October 10, 2005. Paxville DP had <a href="/wiki/NetBurst" title="NetBurst">NetBurst microarchitecture</a>, and was a dual-core equivalent of the single-core <a href="#Nocona_and_Irwindale">Irwindale</a> (related to the <a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a> branded "<a href="/wiki/Pentium_D#Smithfield" title="Pentium D">Smithfield</a>") with 4 MB of L2 cache (2 MB per core). The only Paxville DP model released ran at 2.8 GHz, featured an 800 MT/s front side bus, and was produced using a <a href="/wiki/90_nanometer" class="mw-redirect" title="90 nanometer">90 nm process</a>. </p> <div class="mw-heading mw-heading4"><h4 id="7000-series_"Paxville_MP""><span id="7000-series_.22Paxville_MP.22"></span>7000-series "Paxville MP"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=20" title="Edit section: 7000-series "Paxville MP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Paxville_MP"_(90_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Paxville MP" (90 nm)</a></div> <p>An MP-capable version of Paxville, codenamed <b>Paxville MP</b>, product code 80560, was released on November 1, 2005. There are two versions: one with 2 MB of L2 cache (1 MB per core), and one with 4 MB of L2 (2 MB per core). Paxville MP, called the dual-core Xeon 7000-series, was produced using a 90 nm process. Paxville MP clock ranges between 2.67 GHz and 3.0 GHz (model numbers 7020–7041), with some models having a 667 MT/s FSB, and others having an 800 MT/s FSB. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>7020 </td> <td>2.66 GHz </td> <td rowspan="2">2 × 1 MB </td> <td>667 MT/s </td> <td rowspan="4">165 W </td></tr> <tr> <td>7030 </td> <td>2.80 GHz </td> <td>800 MT/s </td></tr> <tr> <td>7040 </td> <td rowspan="2">3.00 GHz </td> <td rowspan="2">2 × 2 MB </td> <td>667 MT/s </td></tr> <tr> <td>7041 </td> <td>800 MT/s </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="7100-series_"Tulsa""><span id="7100-series_.22Tulsa.22"></span>7100-series "Tulsa"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=21" title="Edit section: 7100-series "Tulsa""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Tulsa"_(65_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Tulsa" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Tulsa</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">August 2006</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">August 2008</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">0F68</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80550</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2.50 GHz to 3.50 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">667 MT/s to 800 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2×1 MB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">16 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">65 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_604" title="Socket 604">Socket 604</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 71xx</li></ul></div></td></tr></tbody></table> <p>Released on August 29, 2006,<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> the 7100 series, codenamed <b>Tulsa</b> (product code 80550), is an improved version of Paxville MP, built on a 65 nm process, with 2 MB of L2 cache (1 MB per core) and up to 16 MB of L3 cache. It uses <a href="/wiki/Socket_604" title="Socket 604">Socket 604</a>.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Tulsa was released in two lines: the N-line uses a 667 MT/s FSB, and the M-line uses an 800 MT/s FSB. The N-line ranges from 2.5 GHz to 3.5 GHz (model numbers 7110N-7150N), and the M-line ranges from 2.6 GHz to 3.4 GHz (model numbers 7110M-7140M). L3 cache ranges from 4 MB to 16 MB across the models.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">L3 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>7110N </td> <td>2.50 GHz </td> <td rowspan="9">2 MB </td> <td rowspan="4">4 MB </td> <td>667 MT/s </td> <td rowspan="4"><span aria-hidden="true" style="visibility:hidden;color:transparent;">0</span>95 W </td></tr> <tr> <td>7110M </td> <td>2.60 GHz </td> <td>800 MT/s </td></tr> <tr> <td>7120N </td> <td rowspan="2">3.00 GHz </td> <td>667 MT/s </td></tr> <tr> <td>7120M </td> <td>800 MT/s </td></tr> <tr> <td>7130N </td> <td>3.16 GHz </td> <td rowspan="2">8 MB </td> <td>667 MT/s </td> <td rowspan="5">150 W </td></tr> <tr> <td>7130M </td> <td>3.20 GHz </td> <td>800 MT/s </td></tr> <tr> <td>7140N </td> <td>3.33 GHz </td> <td rowspan="3">16 MB </td> <td>667 MT/s </td></tr> <tr> <td>7140M </td> <td>3.40 GHz </td> <td>800 MT/s </td></tr> <tr> <td>7150N </td> <td>3.50 GHz </td> <td>667 MT/s </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="5000-series_"Dempsey""><span id="5000-series_.22Dempsey.22"></span><span class="anchor" id="Dempsey"></span>5000-series "Dempsey"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=22" title="Edit section: 5000-series "Dempsey""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors#"Dempsey"_(65_nm)" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">List of Intel NetBurst-based Xeon microprocessors § "Dempsey" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Dempsey</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">May 2006</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">August 2008</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2.50 GHz to 3.73 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">667 MT/s to 1066 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">4 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">65nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 50xx</li></ul></div></td></tr></tbody></table> <p>On May 23, 2006, Intel released the dual-core CPU (Xeon branded 5000 series) codenamed <b>Dempsey</b> (product code 80555). Released as the Dual-Core Xeon 5000-series, Dempsey is a <a href="/wiki/NetBurst" title="NetBurst">NetBurst microarchitecture</a> processor produced using a <a href="/wiki/65_nanometer" class="mw-redirect" title="65 nanometer">65 nm process</a>, and is virtually identical to Intel's "<a href="/wiki/Pentium_D#Presler" title="Pentium D">Presler</a>" <a href="/wiki/Pentium_Extreme_Edition" class="mw-redirect" title="Pentium Extreme Edition">Pentium Extreme Edition</a>, except for the addition of SMP support, which lets Dempsey operate in dual-processor systems. Dempsey ranges between 2.50 GHz and 3.73 GHz (model numbers 5020–5080). Some models have a 667 MT/s FSB, and others have a 1066 MT/s FSB. Dempsey has 4 MB of L2 cache (2 MB per core). A Medium Voltage model, at 3.2 GHz and 1066 MT/s FSB (model number 5063), has also been released. Dempsey also introduces a new interface for Xeon processors: <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a>, also known as <b>Socket J</b>. Dempsey was the first Xeon core in a long time to be somewhat competitive with its Opteron-based counterparts, although it could not claim a decisive lead in any performance metric – that would have to wait for its successor, the Woodcrest. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed (GHz) </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>5020 </td> <td>2.50 GHz </td> <td rowspan="8">2 × 2 MB </td> <td rowspan="4">667 MT/s </td> <td rowspan="4">95 W </td></tr> <tr> <td>5030 </td> <td>2.66 GHz </td></tr> <tr> <td>5040 </td> <td>2.83 GHz </td></tr> <tr> <td>5050 </td> <td>3.00 GHz </td></tr> <tr> <td>5060 </td> <td rowspan="2">3.20 GHz </td> <td rowspan="4">1.07 GT/s </td> <td>130 W </td></tr> <tr> <td>5063 </td> <td>95 W </td></tr> <tr> <td>5070 </td> <td>3.46 GHz </td> <td rowspan="2">130 W </td></tr> <tr> <td>5080 </td> <td>3.73 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Pentium_M_(Yonah)_based_Xeon"><span id="Pentium_M_.28Yonah.29_based_Xeon"></span>Pentium M (Yonah) based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=23" title="Edit section: Pentium M (Yonah) based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="LV_(ULV),_"Sossaman""><span id="LV_.28ULV.29.2C_.22Sossaman.22"></span><span class="anchor" id="Sossaman"></span>LV (ULV), "Sossaman"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=24" title="Edit section: LV (ULV), "Sossaman""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Pentium_M_(Yonah)-based_Xeon_microprocessors#"Sossaman"_(65_nm)" class="mw-redirect" title="List of Intel Pentium M (Yonah)-based Xeon microprocessors">List of Intel Pentium M (Yonah)-based Xeon microprocessors § "Sossaman" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Sossaman</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:2.00_GHz_Xeon_LV_Sossaman_processor.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/56/2.00_GHz_Xeon_LV_Sossaman_processor.jpg/220px-2.00_GHz_Xeon_LV_Sossaman_processor.jpg" decoding="async" width="220" height="213" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/56/2.00_GHz_Xeon_LV_Sossaman_processor.jpg/330px-2.00_GHz_Xeon_LV_Sossaman_processor.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/56/2.00_GHz_Xeon_LV_Sossaman_processor.jpg/440px-2.00_GHz_Xeon_LV_Sossaman_processor.jpg 2x" data-file-width="1046" data-file-height="1012" /></a></span></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2006</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2008</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">06Ex</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80539</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.667 GHz to 2.167 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">667 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">65 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Enhanced_Pentium_M_(microarchitecture)" class="mw-redirect" title="Enhanced Pentium M (microarchitecture)">Enhanced Pentium M</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_M" title="Socket M">Socket M</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon</li></ul></div></td></tr></tbody></table> <p>On March 14, 2006, Intel released a dual-core processor codenamed <b>Sossaman</b> and branded as <i>Xeon</i> LV (low-voltage). Subsequently, an ULV (ultra-low-voltage) version was released. The <i>Sossaman</i> was a low-/ultra-low-power and double-processor capable CPU (like <a href="/wiki/AMD_Quad_FX_platform" title="AMD Quad FX platform">AMD Quad FX</a>), based on the "<i><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></i>" processor, for ultradense non-consumer environment (i.e., targeted at the blade-server and embedded markets), and was rated at a <a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">thermal design power</a> (TDP) of 31 W (LV: 1.66 GHz, 2 GHz and 2.16 GHz) and 15 W (ULV: 1.66 GHz).<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> As such, it supported most of the same features as earlier Xeons: Virtualization Technology, 667 MT/s front side bus, and dual-core processing, but did not support 64-bit operations, so it could not run 64-bit server software, such as <a href="/wiki/Microsoft_Exchange_Server" title="Microsoft Exchange Server">Microsoft Exchange Server</a> 2007, and therefore was limited to 16 GB of memory. A planned successor, codenamed "<i><a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a> MP</i>" was to be a drop-in upgrade to enable <i>Sossaman</i>-based servers to upgrade to 64-bit capability. However, this was abandoned in favor of low-voltage versions of the <i><a href="#5100-series_"Woodcrest"">Woodcrest LV</a></i> processor leaving the <i>Sossaman</i> at a dead-end with no upgrade path. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>ULV 1.66 </td> <td rowspan="2">1.66 GHz </td> <td rowspan="4">2 MB </td> <td rowspan="4">667 MT/s </td> <td>15 W </td></tr> <tr> <td>LV 1.66 </td> <td rowspan="3">31 W </td></tr> <tr> <td>LV 2.00 </td> <td>2.00 GHz </td></tr> <tr> <td>LV 2.16 </td> <td>2.16 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Core-based_Xeon">Core-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=25" title="Edit section: Core-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Dual-Core">Dual-Core</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=26" title="Edit section: Dual-Core"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="3000-series_"Conroe""><span id="3000-series_.22Conroe.22"></span><span class="anchor" id="Conroe"></span>3000-series "Conroe"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=27" title="Edit section: 3000-series "Conroe""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe (microprocessor)</a> and <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Conroe"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Conroe" (65 nm)</a></div> <p>The 3000 series, codenamed <b>Conroe</b> (product code 80557) dual-core Xeon (branded) CPU,<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> released at the end of September 2006, was the first Xeon for single-CPU operation and is designed for entry-level uniprocessor servers. The same processor is branded as <a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2 Duo</a> or as <a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> and <a href="/wiki/Celeron" title="Celeron">Celeron</a>, with varying features disabled. They use <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> (Socket T), operate on a 1066 MT/s front-side bus, support Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology and Intel Virtualization Technology but do not support hyper-threading. Conroe processors with a number ending in "5" have a 1333 MT/s FSB.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>3040 </td> <td>1.86 GHz </td> <td rowspan="2">2 MB </td> <td rowspan="4">1066 MT/s </td> <td rowspan="9">65 W </td></tr> <tr> <td>3050 </td> <td rowspan="2">2.13 GHz </td></tr> <tr> <td>3055* </td> <td rowspan="7">4 MB </td></tr> <tr> <td>3060 </td> <td>2.4 GHz </td></tr> <tr> <td>3065 </td> <td>2.33 GHz </td> <td>1333 MT/s </td></tr> <tr> <td>3070 </td> <td rowspan="2">2.66 GHz </td> <td>1066 MT/s </td></tr> <tr> <td>3075 </td> <td>1333 MT/s </td></tr> <tr> <td>3080* </td> <td>2.93 GHz </td> <td>1066 MT/s </td></tr> <tr> <td>3085 </td> <td>3.00 GHz </td> <td>1333 MT/s </td></tr></tbody></table> <ul><li>Models marked with an asterisk (*) are not present in Intel's Ark database.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading4"><h4 id="3100-series_"Wolfdale""><span id="3100-series_.22Wolfdale.22"></span><span class="anchor" id="Wolfdale"></span>3100-series "Wolfdale"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=28" title="Edit section: 3100-series "Wolfdale""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Wolfdale_(microprocessor)" title="Wolfdale (microprocessor)">Wolfdale (microprocessor)</a>, <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Wolfdale"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Wolfdale" (45 nm)</a>, and <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Wolfdale-CL"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">§ "Wolfdale-CL" (45 nm)</a></div> <p>The 3100 series, codenamed <b>Wolfdale</b> (product code 80570) dual-core Xeon (branded) CPU, was just a rebranded version of the Intel's mainstream <a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2 Duo</a> E7000/E8000 and <a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> E5000 processors, featuring the same <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm process</a> and 6 MB of L2 cache. Unlike most Xeon processors, they only support single-CPU operation. They use <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> (Socket T), operate on a 1333 MT/s front-side bus, support Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology and Intel Virtualization Technology but do not support Hyper-Threading. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E3110 </td> <td rowspan="2">3.00 GHz </td> <td rowspan="3">6 MB </td> <td rowspan="3">1333 MT/s </td> <td>65 W </td></tr> <tr> <td>L3110 </td> <td>45 W </td></tr> <tr> <td>E3120 </td> <td>3.16 GHz </td> <td>65 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="5100-series_"Woodcrest""><span id="5100-series_.22Woodcrest.22"></span><span class="anchor" id="Woodcrest"></span>5100-series "Woodcrest"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=29" title="Edit section: 5100-series "Woodcrest""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Woodcrest"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Woodcrest" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Woodcrest</caption><tbody><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"><a href="/wiki/File:Intel_Xeon_DP_5110_Woodcrest.jpeg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/01/Intel_Xeon_DP_5110_Woodcrest.jpeg/250px-Intel_Xeon_DP_5110_Woodcrest.jpeg" decoding="async" width="250" height="229" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/01/Intel_Xeon_DP_5110_Woodcrest.jpeg/500px-Intel_Xeon_DP_5110_Woodcrest.jpeg 1.5x" data-file-width="803" data-file-height="736" /></a></span></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2006<span class="noprint">; 19 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2006</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2009<span class="noprint">; 16 years ago</span><span style="display: none;"> (<span class="dtend">2009</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">06Fx</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80556</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.60 GHz to 3.0 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s to 1333 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">128 KB (64 KB (32 KB instruction + 32 KB data) x 2)</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">4<span class="nowrap"> </span>MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="/wiki/65_nm_process" title="65 nm process">65nm</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core/Merom</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 51xx</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Variants</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Clovertown</li><li>Tigerton</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="#5000-series_"Dempsey"">Dempsey</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="#5200-series_"Wolfdale-DP">Wolfdale-DP</a></td></tr></tbody></table> <p>On June 26, 2006, Intel released the dual-core CPU (Xeon branded 5100 series) codenamed <b>Woodcrest</b> (product code 80556); it was the first Intel <a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core/Merom microarchitecture</a> processor to be launched on the market. It is a dual-processor server and workstation version of the <a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2</a> processor. Intel claimed that it provides an 80% boost in performance, while reducing power consumption by 20% relative to the 5000 series <i>Dempsey</i>. </p><p>Most models have a 1333<span class="nowrap"> </span>MT/s FSB, except for the 5110 and 5120, which have a 1066<span class="nowrap"> </span>MT/s FSB. The fastest processor (5160) operates at 3.0<span class="nowrap"> </span>GHz. All Woodcrest processors use the <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> (Socket J) socket and all except two models have a TDP of 65<span class="nowrap"> </span>W. The 5160 has a TDP of 80<span class="nowrap"> </span>W and the 5148LV (2.33<span class="nowrap"> </span>GHz) has a TDP of 40<span class="nowrap"> </span>W. The previous generation Xeons had a TDP of 130<span class="nowrap"> </span>W. All models support Intel 64 (Intel's x86-64 implementation), the <a href="/wiki/NX_bit" title="NX bit">XD bit</a>, and <a href="/wiki/X86_virtualization" title="X86 virtualization">Virtualization Technology</a>, with the <a href="/wiki/Demand-based_switching" title="Demand-based switching">Demand-based switching</a> power management option only on Dual-Core Xeon 5140 or above. Woodcrest has 4 MB of shared L2 cache. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>5110 </td> <td>1.60 GHz </td> <td rowspan="9">4 MB </td> <td rowspan="3">1066 MT/s </td> <td rowspan="2">65 W </td></tr> <tr> <td>5120 </td> <td rowspan="2">1.83 GHz </td></tr> <tr> <td>5128 </td> <td>40 W </td></tr> <tr> <td>5130 </td> <td>2.0 GHz </td> <td>1333 MT/s </td> <td>65 W </td></tr> <tr> <td>5138 </td> <td>2.13 GHz </td> <td>1066 MT/s </td> <td>35 W </td></tr> <tr> <td>5140 </td> <td rowspan="2">2.33 GHz </td> <td rowspan="4">1333 MT/s </td> <td>65 W </td></tr> <tr> <td>5148 </td> <td>40 W </td></tr> <tr> <td>5150 </td> <td>2.66 GHz </td> <td>65 W </td></tr> <tr> <td>5160 </td> <td>3.00 GHz </td> <td>80 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="5200-series_"Wolfdale-DP""><span id="5200-series_.22Wolfdale-DP.22"></span><span class="anchor" id="Wolfdale-DP"></span>5200-series "Wolfdale-DP"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=30" title="Edit section: 5200-series "Wolfdale-DP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Wolfdale-DP"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Wolfdale-DP" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Wolfdale-DP</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2007</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">1067x</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80573</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.866 GHz to 3.50 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s to 1600 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">6 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>2</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 52xx</li></ul></div></td></tr></tbody></table> <p>On November 11, 2007, Intel released the dual-core CPU (Xeon branded 5200 series) codenamed <b>Wolfdale-DP</b> (product code 80573).<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> It is built on a <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm process</a> like the desktop Core 2 Duo and Xeon <a href="/wiki/Wolfdale_(microprocessor)" title="Wolfdale (microprocessor)">Wolfdale</a>, featuring Intel 64 (Intel's x86-64 implementation), the <a href="/wiki/NX_bit" title="NX bit">XD bit</a>, and <a href="/wiki/X86_virtualization" title="X86 virtualization">Virtualization Technology</a>. It is unclear whether the <a href="/wiki/Demand-based_switching" title="Demand-based switching">Demand-based switching</a> power management is available on the L5238.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Wolfdale has 6 MB of shared L2 cache. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed (GHz) </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E5205 </td> <td>1.86 GHz </td> <td rowspan="6">6 MB </td> <td>1066 MT/s </td> <td>65 W </td></tr> <tr> <td>L5238 </td> <td>2.66 GHz </td> <td rowspan="4">1333 MT/s </td> <td>35 W </td></tr> <tr> <td>L5240 </td> <td>3.00 GHz </td> <td>40 W </td></tr> <tr> <td>X5260 </td> <td>3.33 GHz </td> <td rowspan="3">80 W </td></tr> <tr> <td>X5270 </td> <td>3.50 GHz </td></tr> <tr> <td>X5272 </td> <td>3.40 GHz </td> <td>1600 MT/s </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="7200-series_"Tigerton""><span id="7200-series_.22Tigerton.22"></span><span class="anchor" id="Tigerton-DC"></span>7200-series "Tigerton"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=31" title="Edit section: 7200-series "Tigerton""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Tigerton-DC"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Tigerton-DC" (65 nm)</a></div> <p>The 7200 series, codenamed <b>Tigerton</b> (product code 80564) is an MP-capable processor, similar to the <a href="#Tigerton">7300</a> series, but, in contrast, there is a single dual-core die.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E7210 </td> <td>2.40 GHz </td> <td rowspan="2">4 MB </td> <td rowspan="2">1066 MT/s </td> <td rowspan="2">80 W </td></tr> <tr> <td>E7220 </td> <td>2.93 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Quad-Core_and_Six-Core_Xeon">Quad-Core and Six-Core Xeon</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=32" title="Edit section: Quad-Core and Six-Core Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="3200-series_"Kentsfield_""><span id="3200-series_.22Kentsfield_.22"></span><span class="anchor" id="Kentsfield"></span>3200-series "Kentsfield "</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=33" title="Edit section: 3200-series "Kentsfield ""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield (microprocessor)</a> and <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Kentsfield"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Kentsfield" (65 nm)</a></div> <p>Intel released rebranded versions of its quad-core (2×2) Core 2 Quad processor as the Xeon 3200-series (product code 80562) on January 7, 2007.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> The 2 × 2 "quad-core" (dual-die dual-core<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup>) comprised two separate dual-core die next to each other in one CPU package. The models are the X3210, X3220 and X3230, running at 2.13 GHz, 2.4 GHz and 2.66 GHz, respectively.<sup id="cite_ref-dailytech_quad-xeon_25-0" class="reference"><a href="#cite_note-dailytech_quad-xeon-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> Like the 3000-series, these models only support single-CPU operation and operate on a 1066 MT/s front-side bus. It is targeted at the "blade" market. The X3220 is also branded and sold as <a href="/wiki/List_of_Intel_Core_2_microprocessors#.22Kentsfield.22_.2865_nm.29" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core2 Quad Q6600</a>, the X3230 as Q6700. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>X3210 </td> <td>2.13 GHz </td> <td rowspan="3">4 MB × 2 </td> <td rowspan="3">1066 MT/s </td> <td rowspan="2">100/105 W </td></tr> <tr> <td>X3220 </td> <td>2.40 GHz </td></tr> <tr> <td>X3230 </td> <td>2.66 GHz </td> <td>100 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="3300-series_"Yorkfield""><span id="3300-series_.22Yorkfield.22"></span><span class="anchor" id="Yorkfield"></span>3300-series "Yorkfield"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=34" title="Edit section: 3300-series "Yorkfield""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Yorkfield_(microprocessor)" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield (microprocessor)</a>, <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Yorkfield"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Yorkfield" (45 nm)</a>, and <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Yorkfield-CL"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">§ "Yorkfield-CL" (45 nm)</a></div> <p>Intel released relabeled versions of its quad-core <a href="/wiki/List_of_Intel_Core_2_microprocessors#.22Yorkfield.22_.2845_nm.29" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Quad Yorkfield</a> Q9300, Q9400, Q9x50 and QX9770 processors as the Xeon 3300-series (product code 80569). This processor comprises two separate dual-core dies next to each other in one CPU package and manufactured in a <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm process</a>. The models are the X3320, X3330, X3350, X3360, X3370 and X3380, being rebadged Q9300, Q9400, Q9450, Q9550, Q9650, QX9770, running at 2.50 GHz, 2.66 GHz, 2.66 GHz, 2.83 GHz, 3.0 GHz, and 3.16 GHz, respectively. The L2 cache is a unified 6 MB per die (except for the X3320 and X3330 with a smaller 3 MB L2 cache per die), and a front-side bus of 1333 MHz. All models feature Intel 64 (Intel's x86-64 implementation), the <a href="/wiki/NX_bit" title="NX bit">XD bit</a>, and <a href="/wiki/X86_virtualization" title="X86 virtualization">Virtualization Technology</a>, as well as <a href="/wiki/Demand-based_switching" title="Demand-based switching">Demand-based switching</a>. </p><p>The <a href="/wiki/Yorkfield_(microprocessor)#Yorkfield_CL" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield-CL</a> (product code 80584) variant of these processors are X3323, X3353 and X3363. They have a reduced TDP of 80W and are made for single-CPU <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> systems instead of <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a>, which is used in all other Yorkfield processors. In all other respects, they are identical to their Yorkfield counterparts. </p> <div class="mw-heading mw-heading4"><h4 id="5300-series_"Clovertown""><span id="5300-series_.22Clovertown.22"></span><span class="anchor" id="Clovertown"></span>5300-series "Clovertown"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=35" title="Edit section: 5300-series "Clovertown""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Clovertown"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Clovertown" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Clovertown</caption><tbody><tr><td colspan="2" class="infobox-image"><span typeof="mw:File"><a href="/wiki/File:Xeon_X5355_Clovertown.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/84/Xeon_X5355_Clovertown.jpg/250px-Xeon_X5355_Clovertown.jpg" decoding="async" width="250" height="233" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/84/Xeon_X5355_Clovertown.jpg/375px-Xeon_X5355_Clovertown.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/84/Xeon_X5355_Clovertown.jpg/500px-Xeon_X5355_Clovertown.jpg 2x" data-file-width="800" data-file-height="744" /></a></span></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2006</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">06Fx</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80563</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.60 GHz to 3.0 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s to 1333 </td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2×4 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">65 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Core_(microarchitecture)" class="mw-redirect" title="Core (microarchitecture)">Core</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 53xx</li></ul></div></td></tr></tbody></table> <p>A quad-core (2×2) successor of the Woodcrest for DP segment, consisting of two dual-core Woodcrest chips in one package similarly to the dual-core Pentium D branded CPUs (two single-core chips) or the quad-core <a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield</a>. All Clovertowns use the <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> package. The Clovertown has been usually implemented with two Woodcrest dies on a <a href="/wiki/Multi-Chip_Module" class="mw-redirect" title="Multi-Chip Module">multi-chip module</a>, with 8 MB of L2 cache (4 MB per die). Like Woodcrest, lower models use a 1066 MT/s FSB, and higher models use a 1333 MT/s FSB. Intel released <b>Clovertown</b>, product code 80563, on November 14, 2006<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> with models E5310, E5320, E5335, E5345, and X5355, ranging from 1.6 GHz to 2.66 GHz. All models support MMX, SSE, SSE2, SSE3, SSSE3, Intel 64, XD bit (an NX bit implementation), <a href="/wiki/Intel_VT" class="mw-redirect" title="Intel VT">Intel VT</a>. The E and X designations are borrowed from Intel's Core 2 model numbering scheme; an ending of -0 implies a 1066 MT/s FSB, and an ending of -5 implies a 1333 MT/s FSB.<sup id="cite_ref-dailytech_quad-xeon_25-1" class="reference"><a href="#cite_note-dailytech_quad-xeon-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> All models have a TDP of 80 W with the exception of the X5355, which has a TDP of 120 W, and the X5365, which has a TDP of 150 W. A low-voltage version of Clovertown with a TDP of 50 W has a model numbers L5310, L5320 and L5335 (1.6 GHz, 1.86 GHz and 2.0 GHz respectively). The 3.0 GHz X5365 arrived in July 2007, and became available in the <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> <a href="/wiki/Mac_Pro" title="Mac Pro">Mac Pro</a><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> on April 4, 2007.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> The X5365 performs up to around 38 <a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a> in the LINPACK benchmark.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E5310 </td> <td rowspan="2">1.60 GHz </td> <td rowspan="9">4 MB × 2 </td> <td rowspan="4">1066 MT/s </td> <td>80 W </td></tr> <tr> <td>L5310 </td> <td>50 W </td></tr> <tr> <td>E5320 </td> <td rowspan="2">1.86 GHz </td> <td>80 W </td></tr> <tr> <td>L5320 </td> <td>50 W </td></tr> <tr> <td>E5335 </td> <td rowspan="2">2.00 GHz </td> <td rowspan="5">1333 MT/s </td> <td>80 W </td></tr> <tr> <td>L5335 </td> <td>50 W </td></tr> <tr> <td>E5345 </td> <td>2.33 GHz </td> <td>80 W </td></tr> <tr> <td>X5355 </td> <td>2.66 GHz </td> <td>120 W </td></tr> <tr> <td>X5365 </td> <td>3.00 GHz </td> <td>150 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="5400-series_"Harpertown""><span id="5400-series_.22Harpertown.22"></span><span class="anchor" id="Harpertown"></span>5400-series "Harpertown"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=36" title="Edit section: 5400-series "Harpertown""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Harpertown"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Harpertown" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Harpertown</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2007</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">1067x</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80574</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2.0 GHz to 3.40 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s to 1600 </td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2 × 6 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 54xx</li><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2 Quad</a> QX9775</li></ul></div></td></tr></tbody></table> <p>On November 11, 2007 Intel presented <a href="/wiki/Yorkfield" title="Yorkfield">Yorkfield</a>-based Xeons – called Harpertown (product code 80574) – to the public.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> This family consists of dual die quad-core CPUs manufactured on a <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm process</a> and featuring 1066 MHz, 1333 MHz, 1600 MHz front-side buses, with TDP rated from 40 W to 150 W depending on the model. These processors fit in the <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> package. All models feature Intel 64 (Intel's x86-64 implementation), the <a href="/wiki/NX_bit" title="NX bit">XD bit</a>, and <a href="/wiki/X86_virtualization" title="X86 virtualization">Virtualization Technology</a>. All except the E5405 and L5408 also feature <a href="/wiki/Demand-based_switching" title="Demand-based switching">Demand-based switching</a>. The supplementary character in front of the model-number represents the thermal rating: an L depicts a TDP of 40 W or 50 W, an E depicts 80 W whereas an X is 120 W TDP or above. The speed of 3.00 GHz comes as four models, two models with 80 W TDP two other models with 120 W TDP with 1333 MHz or 1600 MHz front-side bus respectively. The fastest Harpertown is the X5492 whose TDP of 150 W is higher than those of the Prescott-based Xeon DP but having twice as many cores. (The X5482 is also sold under the name "Core 2 Extreme QX9775" for use in the <a href="/wiki/Intel_Skulltrail" title="Intel Skulltrail">Intel Skulltrail</a> system.) </p><p>Intel 1.6 GT/s front-side bus Xeon processors will drop into the Intel 5400 (Seaburg) chipset whereas several mainboards featuring the Intel 5000/5200-chipset are enabled to run the processors with a 1333 MHz front-side bus speed. Seaburg features support for dual <span class="nowrap">PCIe 2.0 x16</span> slots and up to 128 GB of memory.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E5405 </td> <td>2.00 GHz </td> <td rowspan="18">2 × 6 MB </td> <td>1333 MT/s </td> <td>80 W </td></tr> <tr> <td>L5408 </td> <td>2.13 GHz </td> <td>1066 MT/s </td> <td>40 W </td></tr> <tr> <td>E5410 </td> <td rowspan="2">2.33 GHz </td> <td rowspan="11">1333 MT/s </td> <td>80 W </td></tr> <tr> <td>L5410 </td> <td>50 W </td></tr> <tr> <td>E5420 </td> <td rowspan="2">2.50 GHz </td> <td>80 W </td></tr> <tr> <td>L5420 </td> <td>50 W </td></tr> <tr> <td>E5430 </td> <td rowspan="2">2.66 GHz </td> <td>80 W </td></tr> <tr> <td>L5430 </td> <td>50 W </td></tr> <tr> <td>E5440 </td> <td>2.83 GHz </td> <td>80 W </td></tr> <tr> <td>X5450 </td> <td rowspan="2">3.00 GHz </td> <td>120 W </td></tr> <tr> <td>E5450 </td> <td>80 W </td></tr> <tr> <td>X5460 </td> <td>3.16 GHz </td> <td rowspan="2">120 W </td></tr> <tr> <td>X5470 </td> <td>3.33 GHz </td></tr> <tr> <td>E5462 </td> <td>2.80 GHz </td> <td rowspan="5">1600 MT/s </td> <td rowspan="2">80 W </td></tr> <tr> <td>E5472 </td> <td rowspan="2">3.00 GHz </td></tr> <tr> <td>X5472 </td> <td>120 W </td></tr> <tr> <td>X5482 </td> <td>3.20 GHz </td> <td rowspan="2">150 W </td></tr> <tr> <td>X5492 </td> <td>3.40 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="7300-series_"Tigerton_QC""><span id="7300-series_.22Tigerton_QC.22"></span><span class="anchor" id="Tigerton"></span>7300-series "Tigerton QC"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=37" title="Edit section: 7300-series "Tigerton QC""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Tigerton"_(65_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Tigerton" (65 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Tigerton</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2007</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">06Fx</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80564<br />80565</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.60 GHz to 2.933 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">2×2 or 2×4 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">65 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Core_(microarchitecture)" class="mw-redirect" title="Core (microarchitecture)">Core</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_604" title="Socket 604">mPGA604</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 72xx</li><li>Xeon 73xx</li></ul></div></td></tr></tbody></table> <p>The 7300 series, codenamed <b>Tigerton QC</b> (product code 80565) is a four-socket (packaged in <a href="/wiki/Socket_604" title="Socket 604">Socket 604</a>) and more capable <a href="/wiki/Quad-core_processor" class="mw-redirect" title="Quad-core processor">quad-core processor</a>, consisting of two <a href="/wiki/Dual_core" class="mw-redirect" title="Dual core">dual core</a> Core 2 architecture silicon chips on a single ceramic module, similar to Intel's Xeon 5300 series Clovertown processor modules.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p><p>The 7300 series uses Intel's Caneland (Clarksboro) platform. </p><p>Intel claims the 7300 series Xeons offer more than twice the performance per watt as Intel's previous generation 7100 series. The 7300 series' Caneland chipset provides a point to point interface allowing the full front side bus bandwidth per processor. </p><p>The 7xxx series is aimed at the large server market, supporting configurations of up to 32 CPUs per host. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L2 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th></tr> <tr> <td>E7310 </td> <td>1.60 GHz </td> <td rowspan="2">2×2 MB </td> <td rowspan="6">1066 MT/s </td> <td rowspan="4">80 W </td></tr> <tr> <td>E7320 </td> <td>2.13 GHz </td></tr> <tr> <td>E7330 </td> <td rowspan="2">2.40 GHz </td> <td>2×3 MB </td></tr> <tr> <td>E7340 </td> <td rowspan="3">2×4 MB </td></tr> <tr> <td>L7345 </td> <td>1.86 GHz </td> <td>50 W </td></tr> <tr> <td>X7350 </td> <td>2.93 GHz </td> <td>130 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="7400-series_"Dunnington""><span id="7400-series_.22Dunnington.22"></span><span class="anchor" id="Dunnington"></span>7400-series "Dunnington"</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=38" title="Edit section: 7400-series "Dunnington""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors#"Dunnington"_(45_nm)" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">List of Intel Core-based Xeon microprocessors § "Dunnington" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Dunnington</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2008</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">106D1</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80582</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">2.133 GHz to 2.66 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">1066 MT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">6 × 96 KB</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">3 × 3 MB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">16 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>6</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Socket_604" title="Socket 604">mPGA604</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 74xx</li></ul></div></td></tr></tbody></table> <p><b>Dunnington</b><sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> – the last CPU of the Penryn generation and Intel's first <a href="/wiki/Multi-core" class="mw-redirect" title="Multi-core">multi-core</a> (above two) die – features a single-die six- (or <i>hexa-</i>) core design with three unified 3 MB L2 caches (resembling three merged <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm</a> dual-core Wolfdale-3M dies), and 96 kB L1 cache (Data) and 16 MB of L3 cache. It features a 1.07 GT/s <a href="/wiki/Front_Side_Bus" class="mw-redirect" title="Front Side Bus">FSB</a>, fits into the Tigerton's mPGA604 socket, and is compatible with both the Intel Caneland and IBM X4 chipsets. These processors support DDR2-1066 (533 MHz), and have a maximum <a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a> below 130 W. They are intended for blades and other stacked computer systems. Availability was scheduled for the second half of 2008. It was followed shortly by the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem microarchitecture</a>. Total transistor count is 1.9 billion.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p><p>Announced on September 15, 2008.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L3 cache </th> <th scope="col">FSB </th> <th scope="col">TDP </th> <th scope="col">Cores </th></tr> <tr> <td>E7420 </td> <td rowspan="2">2.13 GHz </td> <td>8 MB </td> <td rowspan="7">1066 MT/s </td> <td rowspan="3">90 W </td> <td rowspan="4">4 </td></tr> <tr> <td>E7430 </td> <td>12 MB </td></tr> <tr> <td>E7440 </td> <td>2.40 GHz </td> <td>16 MB </td></tr> <tr> <td>L7445 </td> <td>2.13 GHz </td> <td rowspan="3">12 MB </td> <td>50 W </td></tr> <tr> <td>E7450 </td> <td>2.40 GHz </td> <td>90 W </td> <td rowspan="3">6 </td></tr> <tr> <td>L7455 </td> <td>2.13 GHz </td> <td>65 W </td></tr> <tr> <td>X7460 </td> <td>2.66 GHz </td> <td>16 MB </td> <td>130 W </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Nehalem-based_Xeon">Nehalem-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=39" title="Edit section: Nehalem-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="3400-series_"Lynnfield""><span id="3400-series_.22Lynnfield.22"></span><span class="anchor" id="Lynnfield"></span>3400-series "Lynnfield"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=40" title="Edit section: 3400-series "Lynnfield""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield (microprocessor)</a> and <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Lynnfield"_(45_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Lynnfield" (45 nm)</a></div> <p>Xeon 3400-series processors based on <b>Lynnfield</b> are designed for entry-level servers compared to Bloomfield, which is designed for uniprocessor workstations. Like Bloomfield, they are quad-core single-package processors based on the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem microarchitecture</a>, but were introduced almost a year later, in September 2009. The same processors are marketed for mid-range to high-end desktops systems as <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> and <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a>. They have two integrated memory channels as well as <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> and <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> (DMI) links, but no <a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QuickPath Interconnect</a> (QPI) interface. </p> <div class="mw-heading mw-heading3"><h3 id="3400-series_"Clarkdale""><span id="3400-series_.22Clarkdale.22"></span><span class="anchor" id="Clarkdale"></span>3400-series "Clarkdale"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=41" title="Edit section: 3400-series "Clarkdale""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale (microprocessor)</a> and <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Clarkdale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Clarkdale" (MCP, 32 nm)</a></div> <p>At low end of the 3400-series is not a Lynnfield but a <b>Clarkdale</b> processor, which is also used in the Core i3-500 and Core i5-600 processors as well as the Celeron G1000 and G6000 Pentium series. A single model was released in March 2010, the Xeon L3406. Compared to all other Clarkdale-based products, this one does not support integrated graphics, but has a much lower thermal design power of just 30 W. Compared to the Lynnfield-based Xeon 3400 models, it only offers two cores. </p> <div class="mw-heading mw-heading3"><h3 id="W3500-series_"Bloomfield""><span id="W3500-series_.22Bloomfield.22"></span><span class="anchor" id="Bloomfield"></span>W3500-series "Bloomfield"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=42" title="Edit section: W3500-series "Bloomfield""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield (microprocessor)</a> and <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Bloomfield"_(45_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Bloomfield" (45 nm)</a></div> <p><b>Bloomfield</b> (or <b>Nehalem-E</b>) is the codename for the successor to the Xeon 3300 series, is based on the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem microarchitecture</a> and uses the same <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm</a> manufacturing methods as Intel's <a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn</a>. The first processor released with the Nehalem architecture is the high-end desktop <a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a>, which was released in November 2008. This is the server version for single CPU systems. This is a <b>single-socket</b> Intel Xeon processor designed for uniprocessor workstations. </p><p>The performance improvements over the previous Xeon 3300 series are based mainly on: </p> <ul><li>Integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a> supporting three memory channels of <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> UDIMM (Unbuffered) or RDIMM (Registered)</li> <li>A new point-to-point processor interconnect <i><a href="/wiki/QuickPath" class="mw-redirect" title="QuickPath">QuickPath</a></i>, replacing the legacy front side bus</li> <li>Simultaneous multithreading by multiple cores and <a href="/wiki/Hyper-threading" title="Hyper-threading">hyper-threading</a> (2× per core).</li> <li><a href="/wiki/Turbo_Boost" class="mw-redirect" title="Turbo Boost">Turbo Boost</a>, an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed</li></ul> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L3 cache </th> <th scope="col">QPI speed </th> <th scope="col">DDR3 speed </th> <th scope="col">TDP </th> <th scope="col">Cores </th> <th scope="col">Threads </th> <th scope="col"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo-Boost</a> </th></tr> <tr> <td>W3503</td> <td>2.40 GHz</td> <td rowspan="2">4 MB</td> <td rowspan="7">4.8 GT/s</td> <td rowspan="7">1066 MT/s</td> <td rowspan="9">130 W</td> <td colspan="2" rowspan="2">2</td> <td rowspan="2">No </td></tr> <tr> <td>W3505</td> <td>2.53 GHz </td></tr> <tr> <td>W3520</td> <td>2.66 GHz</td> <td rowspan="7">8 MB</td> <td rowspan="7">4</td> <td rowspan="7">8</td> <td rowspan="7">Yes </td></tr> <tr> <td>W3530</td> <td>2.80 GHz </td></tr> <tr> <td>W3540</td> <td>2.93 GHz </td></tr> <tr> <td>W3550</td> <td>3.06 GHz </td></tr> <tr> <td>W3565</td> <td>3.20 GHz </td></tr> <tr> <td>W3570</td> <td>3.2 GHz</td> <td rowspan="2">6.4 GT/s</td> <td rowspan="2">1333 MT/s </td></tr> <tr> <td>W3580</td> <td>3.33 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="5500-series_"Gainestown""><span id="5500-series_.22Gainestown.22"></span><span class="anchor" id="Gainestown"></span><span class="anchor" id="5500-series"></span><span class="anchor" id="Gainestown"></span><span class="anchor" id="Nehalem-EP"></span>5500-series "Gainestown"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=43" title="Edit section: 5500-series "Gainestown""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Gainestown"_(45_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Gainestown" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Gainestown</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2008</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">106Ax</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80602</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.866 GHz to 3.333 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">4×256 kB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">8 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand name</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 55xx</li></ul></div></td></tr></tbody></table> <p><b>Gainestown</b> or <b>Nehalem-EP</b> (Efficient Performance), the successor to Wolfdale-DP, and Harpertown, is based on the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem microarchitecture</a> and uses the same <a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm</a> manufacturing methods. The first processor released with the Nehalem microarchitecture is the high-end desktop <a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a>, which was released in November 2008. Server processors of the Xeon 55xx range were first supplied to testers in December 2008.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </p><p>The performance improvements over Wolfdale-DP and Harpertown processors are based mainly on: </p> <ul><li>Monolithic design for quad-core models</li> <li>Integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a> supporting three memory channels of <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> memory with ECC support.</li> <li>A new point-to-point processor interconnect <i><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QuickPath</a></i>, replacing the legacy front side bus. Gainestown has two QuickPath interfaces.</li> <li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> (2× per core, starting from 5518), that was already present in NetBurst-based processors</li> <li><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a>, an overclocking technology that allows the CPU to run at a clock speed higher than the base speed as needed</li></ul> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L3 cache </th> <th scope="col">QPI speed </th> <th scope="col">DDR3 speed </th> <th scope="col">TDP </th> <th scope="col">Cores </th> <th scope="col">Threads </th> <th scope="col">Turbo-Boost </th></tr> <tr> <td>E5502 </td> <td>1.87 GHz </td> <td rowspan="6">4 MB </td> <td rowspan="6">4.8 GT/s </td> <td rowspan="6">800 MT/s </td> <td rowspan="4">80 W </td> <td colspan="2" rowspan="2">2 </td> <td rowspan="6">No </td></tr> <tr> <td>E5503 </td> <td rowspan="2">2.00 GHz </td></tr> <tr> <td>E5504 </td> <td rowspan="15">4 </td> <td rowspan="4">4 </td></tr> <tr> <td>E5506 </td> <td rowspan="2">2.13 GHz </td></tr> <tr> <td>L5506 </td> <td>60 W </td></tr> <tr> <td>E5507 </td> <td>2.26 GHz </td> <td>80 W </td></tr> <tr> <td>L5518 </td> <td>2.13 GHz </td> <td rowspan="11">8 MB </td> <td rowspan="6">5.86 GT/s </td> <td rowspan="6">1066 MT/s </td> <td>60 W </td> <td rowspan="11">8 </td> <td rowspan="11">Yes </td></tr> <tr> <td>E5520 </td> <td rowspan="2">2.26 GHz </td> <td>80 W </td></tr> <tr> <td>L5520 </td> <td>60 W </td></tr> <tr> <td>E5530 </td> <td rowspan="2">2.40 GHz </td> <td>80 W </td></tr> <tr> <td>L5530 </td> <td>60 W </td></tr> <tr> <td>E5540 </td> <td>2.53 GHz </td> <td>80 W </td></tr> <tr> <td>X5550 </td> <td>2.66 GHz </td> <td rowspan="5">6.4 GT/s </td> <td rowspan="5">1333 MT/s </td> <td rowspan="3">95 W </td></tr> <tr> <td>X5560 </td> <td>2.80 GHz </td></tr> <tr> <td>X5570 </td> <td>2.93 GHz </td></tr> <tr> <td>W5580 </td> <td>3.20 GHz </td> <td rowspan="2">130 W </td></tr> <tr> <td>W5590 </td> <td>3.33 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="C3500/C5500-series_"Jasper_Forest""><span id="C3500.2FC5500-series_.22Jasper_Forest.22"></span><span class="anchor" id="Jasper_Forest"></span><span class="anchor" id="C3500/C5500-Series"></span>C3500/C5500-series "Jasper Forest"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=44" title="Edit section: C3500/C5500-series "Jasper Forest""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Jasper_Forest"_(45_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Jasper Forest" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Jasper Forest</caption><tbody><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2010</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">present</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">106Ex</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80612</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.733 GHz to 2.40 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">4×256 kB</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">8 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">UP/DP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon C35xx (UP)</li><li>Xeon C55xx (DP)</li><li>Celeron P1xxx (UP)</li></ul></div></td></tr></tbody></table> <p><b>Jasper Forest</b> is a Nehalem-based embedded processor with <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> connections on-die, core counts from 1 to 4 cores and power envelopes from 23 to 85 watts.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p><p>The uni-processor version without QPI comes as LC35xx and EC35xx, while the dual-processor version is sold as LC55xx and EC55xx and uses QPI for communication between the processors. Both versions use a DMI link to communicate with the 3420 that is also used in the 3400-series Lynfield Xeon processors, but use an <a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a> package that is otherwise used for processors with QPI but no DMI or PCI Express links. The CPUID code of both Lynnfield and Jasper forest is 106Ex, i.e., family 6, model 30. </p><p>The <a href="/wiki/Celeron" title="Celeron">Celeron</a> P1053 belongs into the same family as the LC35xx series, but lacks some <a href="/wiki/Reliability,_availability_and_serviceability_(computer_hardware)" class="mw-redirect" title="Reliability, availability and serviceability (computer hardware)">RAS</a> features that are present in the Xeon version. </p> <div class="mw-heading mw-heading3"><h3 id="W3600/5600-series_"Gulftown"_&_"Westmere-EP""><span id="W3600.2F5600-series_.22Gulftown.22_.26_.22Westmere-EP.22"></span><span class="anchor" id="Gulftown"></span><span class="anchor" id="Westmere-EP"></span>W3600/5600-series "Gulftown" & "Westmere-EP"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=45" title="Edit section: W3600/5600-series "Gulftown" & "Westmere-EP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Gulftown_(microprocessor)" class="mw-redirect" title="Gulftown (microprocessor)">Gulftown (microprocessor)</a>, <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Gulftown"_(32_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Gulftown" (32 nm)</a>, and <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Westmere-EP"_(32_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">§ "Westmere-EP" (32 nm)</a></div> <p><b>Gulftown</b> and <b>Westmere-EP</b>, six-core 32 nm architecture <a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a>-based processors, are the basis for the Xeon 36xx and 56xx series and the <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a>-980X. It launched in the first quarter of 2010. The 36xx-series follows the 35xx-series Bloomfield uni-processor model while the 56xx-series follows the 55xx-series Gainestown dual-processor model and both are socket compatible to their predecessors. </p> <table class="wikitable sortable"> <tbody><tr> <th scope="col">Model </th> <th scope="col">Speed </th> <th scope="col">L3 cache </th> <th scope="col">QPI speed </th> <th scope="col">DDR3 speed </th> <th scope="col">TDP </th> <th scope="col">Cores </th> <th scope="col">Threads </th> <th scope="col">Turbo-Boost </th></tr> <tr> <td>W3670</td> <td>3.20 GHz</td> <td rowspan="3">12 MB</td> <td>4.8 GT/s</td> <td>1066 MT/s</td> <td rowspan="3">130 W</td> <td rowspan="3">6</td> <td rowspan="3">12</td> <td rowspan="3">Yes </td></tr> <tr> <td>W3680</td> <td>3.33 GHz</td> <td rowspan="2">6.4 GT/s</td> <td rowspan="2">1333 MT/s </td></tr> <tr> <td>W3690</td> <td>3.46 GHz </td></tr> <tr> <td>E5603</td> <td>1.60 GHz</td> <td>4 MB</td> <td rowspan="4">4.8 GT/s</td> <td>800 MT/s</td> <td rowspan="3">80 W</td> <td rowspan="8">4</td> <td rowspan="4">4</td> <td rowspan="4">No </td></tr> <tr> <td>E5606</td> <td>2.13 GHz</td> <td rowspan="2">8 MB</td> <td rowspan="7">1066 MT/s </td></tr> <tr> <td>E5607</td> <td>2.26 GHz </td></tr> <tr> <td>L5609</td> <td rowspan="2">1.86 GHz</td> <td rowspan="24">12 MB</td> <td rowspan="2">40 W </td></tr> <tr> <td>L5618</td> <td rowspan="11">5.86 GT/s</td> <td rowspan="4">8</td> <td rowspan="22">Yes </td></tr> <tr> <td>E5620</td> <td>2.40 GHz</td> <td>80 W </td></tr> <tr> <td>L5630</td> <td>2.13 GHz</td> <td>40 W </td></tr> <tr> <td>E5630</td> <td>2.53 GHz</td> <td>80 W </td></tr> <tr> <td>L5638</td> <td>2.00 GHz</td> <td rowspan="3">1333 MT/s</td> <td rowspan="3">60 W</td> <td rowspan="3">6</td> <td rowspan="3">12 </td></tr> <tr> <td>L5639</td> <td>2.13 GHz </td></tr> <tr> <td>L5640</td> <td>2.26 GHz </td></tr> <tr> <td>E5640</td> <td>2.66 GHz</td> <td>1066 MT/s</td> <td>80 W</td> <td>4</td> <td>8 </td></tr> <tr> <td>L5645</td> <td rowspan="2">2.40 GHz</td> <td rowspan="10">1333 MT/s</td> <td>60 W</td> <td rowspan="5">6</td> <td rowspan="5">12 </td></tr> <tr> <td>E5645</td> <td rowspan="2">80 W </td></tr> <tr> <td>E5649</td> <td>2.53 GHz </td></tr> <tr> <td>X5650</td> <td>2.66 GHz</td> <td rowspan="12">6.4 GT/s</td> <td rowspan="6">95 W </td></tr> <tr> <td>X5660</td> <td>2.80 GHz </td></tr> <tr> <td>X5667</td> <td>3.06 GHz</td> <td>4</td> <td>8 </td></tr> <tr> <td>X5670</td> <td>2.93 GHz</td> <td>6</td> <td>12 </td></tr> <tr> <td>X5672</td> <td>3.20 GHz</td> <td>4</td> <td>8 </td></tr> <tr> <td>X5675</td> <td>3.06 GHz</td> <td>6</td> <td>12 </td></tr> <tr> <td>X5677</td> <td>3.46 GHz</td> <td>130 W</td> <td>4</td> <td>8 </td></tr> <tr> <td>X5679</td> <td>3.20 GHz</td> <td>1066 MT/s</td> <td>115 W</td> <td rowspan="2">6</td> <td rowspan="2">12 </td></tr> <tr> <td>X5680</td> <td>3.33 GHz</td> <td rowspan="3">1333 MT/s</td> <td rowspan="4">130 W </td></tr> <tr> <td>X5687</td> <td>3.60 GHz</td> <td>4</td> <td>8 </td></tr> <tr> <td>X5690</td> <td>3.46 GHz</td> <td>6</td> <td>12 </td></tr> <tr> <td>X5698</td> <td>4.40 GHz</td> <td>1066 MT/s</td> <td>2</td> <td>4 </td> <td>No </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="6500/7500-series_"Beckton""><span id="6500.2F7500-series_.22Beckton.22"></span><span class="anchor" id="Beckton"></span><span class="anchor" id="Nehalem-EX"></span>6500/7500-series "Beckton"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=46" title="Edit section: 6500/7500-series "Beckton""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Beckton"_(45_nm)" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Beckton" (45 nm)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546" /><table class="infobox"><caption class="infobox-title">Beckton</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Xeon_Beckton_with_and_without_heat_spreader.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/21/Xeon_Beckton_with_and_without_heat_spreader.jpg/220px-Xeon_Beckton_with_and_without_heat_spreader.jpg" decoding="async" width="220" height="102" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/21/Xeon_Beckton_with_and_without_heat_spreader.jpg/330px-Xeon_Beckton_with_and_without_heat_spreader.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/21/Xeon_Beckton_with_and_without_heat_spreader.jpg/440px-Xeon_Beckton_with_and_without_heat_spreader.jpg 2x" data-file-width="3098" data-file-height="1443" /></a></span><div class="infobox-caption">Xeon E7530 (with and without the heat spreader)</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">March 30, 2010<span class="noprint">; 15 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2010-03-30</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">Q4 2012</td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/Intel" title="Intel">Intel</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/CPUID" title="CPUID">CPUID</a> code</th><td class="infobox-data">206Ex</td></tr><tr><th scope="row" class="infobox-label">Product code</th><td class="infobox-data">80604</td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.733 GHz to 2.667 GHz</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QPI</a> speeds</th><td class="infobox-data">6.4 GT/s</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">256<span class="nowrap"> </span>KB per core</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">Up to 24<span class="nowrap"> </span>MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">DP/MP Server</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">45 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>4-8</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li><a href="/wiki/LGA_1567" title="LGA 1567">LGA 1567</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409" /><div class="plainlist"><ul><li>Xeon 65xx (DP)</li><li>Xeon 75xx (MP)</li></ul></div></td></tr></tbody></table> <p><b>Beckton</b> or <b>Nehalem-EX</b> (Expandable server market) is a Nehalem-based processor with up to eight cores and uses buffering inside the chipset to support up to 16 standard DDR3 DIMMs per CPU socket without requiring the use of FB-DIMMs.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> Unlike all previous Xeon MP processors, Nehalem-EX uses the new <a href="/wiki/LGA_1567" title="LGA 1567">LGA 1567</a> (Socket LS) package, replacing the <a href="/wiki/Socket_604" title="Socket 604">Socket 604</a> used in the previous models, up to Xeon <a href="#7400-series_"Dunnington"">7400 "Dunnington"</a>. The 75xx models have four QuickPath interfaces, so it can be used in up-to eight-socket configurations, while the 65xx models are only for up to two sockets. Designed by the Digital Enterprise Group (DEG) Santa Clara and Hudson Design Teams, Beckton is manufactured on the P1266 (45 nm) technology. Its launch in March 2010 coincided with that of its direct competitor, AMD's <a href="/wiki/Opteron" title="Opteron">Opteron</a> 6xxx "Magny-Cours".<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> </p><p>Most models limit the number of cores and QPI links as well as the L3 cache size in order to get a broader range of products out of the single chip design. </p> <div class="mw-heading mw-heading3"><h3 id="E7-x8xx-series_"Westmere-EX""><span id="E7-x8xx-series_.22Westmere-EX.22"></span><span class="anchor" id="Westmere-EX"></span>E7-x8xx-series "Westmere-EX"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=47" title="Edit section: E7-x8xx-series "Westmere-EX""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Nehalem-based_Xeon_microprocessors#"Westmere-EX"_(32_nm)_Expandable" class="mw-redirect" title="List of Intel Nehalem-based Xeon microprocessors">List of Intel Nehalem-based Xeon microprocessors § "Westmere-EX" (32 nm) Expandable</a></div> <p><b>Westmere-EX</b> is the follow-on to Beckton/Nehalem-EX and the first Intel processor to have ten CPU cores. The microarchitecture is the same as in the six-core Gulftown/Westmere-EP processor, but it uses the <a href="/wiki/LGA_1567" title="LGA 1567">LGA 1567</a> package like Beckton to support up to eight sockets. </p><p>Starting with Westmere-EX, the naming scheme has changed once again, with "E7-xxxx" now signifying the high-end line of Xeon processors using a package that supports larger than two-CPU configurations, formerly the 7xxx series. Similarly, the 3xxx uniprocessor and 5xxx dual-processor series turned into E3-xxxx and E5-xxxx, respectively, for later processors. </p> <div class="mw-heading mw-heading2"><h2 id="Sandy_Bridge-_and_Ivy_Bridge-based_Xeon">Sandy Bridge- and Ivy Bridge-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=48" title="Edit section: Sandy Bridge- and Ivy Bridge-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="E3-12xx-series_"Sandy_Bridge""><span id="E3-12xx-series_.22Sandy_Bridge.22"></span><span class="anchor" id="Sandy_Bridge"></span><span class="anchor" id="E3"></span>E3-12xx-series "Sandy Bridge"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=49" title="Edit section: E3-12xx-series "Sandy Bridge""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> and <a href="/wiki/List_of_Intel_Sandy_Bridge-based_Xeon_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Sandy Bridge-based Xeon microprocessors">List of Intel Sandy Bridge-based Xeon microprocessors § "Sandy Bridge" (32 nm)</a></div> <p>The <b>Xeon E3-12xx</b> line of processors, introduced in April 2011, uses the <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> chips that are also the base for the Core i3/i5/i7-2xxx and Celeron/Pentium Gxxx products using the same <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a> socket, but with a different set of features disabled. Notably, the Xeon variants include support for <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a>, <a href="/wiki/VT-d" class="mw-redirect" title="VT-d">VT-d</a> and <a href="/wiki/Trusted_execution" class="mw-redirect" title="Trusted execution">trusted execution</a> that are not present on the consumer models, while only some Xeon E3 enable the integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> that is present on Sandy Bridge. Like its Xeon 3400-series predecessors, the Xeon E3 only supports operation with a single CPU socket and is targeted at entry-level workstations and servers. The CPUID of this processor is 0206A7h, the product code is 80623. </p> <div class="mw-heading mw-heading3"><h3 id="E3-12xx_v2-series_"Ivy_Bridge""><span id="E3-12xx_v2-series_.22Ivy_Bridge.22"></span><span class="anchor" id="Ivy_Bridge"></span><span class="anchor" id="E3-V2"></span>E3-12xx v2-series "Ivy Bridge"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=50" title="Edit section: E3-12xx v2-series "Ivy Bridge""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (microarchitecture)</a> and <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">List of Intel Ivy Bridge-based Xeon microprocessors § "Ivy Bridge" (22 nm)</a></div> <p><b>Xeon E3-12xx v2</b> is a minor update of the Sandy Bridge-based E3-12xx, using the 22 nm shrink, and providing slightly better performance while remaining backwards compatible. They were released in May 2012 and mirror the desktop Core i3/i5/i7-3xxx parts. </p> <div class="mw-heading mw-heading3"><h3 id="E5-14xx/24xx_series_"Sandy_Bridge-EN"_and_E5-16xx/26xx/46xx-series_"Sandy_Bridge-EP""><span id="E5-14xx.2F24xx_series_.22Sandy_Bridge-EN.22_and_E5-16xx.2F26xx.2F46xx-series_.22Sandy_Bridge-EP.22"></span><span class="anchor" id="E5"></span>E5-14xx/24xx series "Sandy Bridge-EN" and E5-16xx/26xx/46xx-series "Sandy Bridge-EP"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=51" title="Edit section: E5-14xx/24xx series "Sandy Bridge-EN" and E5-16xx/26xx/46xx-series "Sandy Bridge-EP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E</a>, <a href="/wiki/List_of_Intel_Sandy_Bridge-based_Xeon_microprocessors#"Sandy_Bridge-E"_(32_nm)" class="mw-redirect" title="List of Intel Sandy Bridge-based Xeon microprocessors">List of Intel Sandy Bridge-based Xeon microprocessors § "Sandy Bridge-E" (32 nm)</a>, <a href="/wiki/List_of_Intel_Sandy_Bridge-based_Xeon_microprocessors#"Sandy_Bridge-EN"_(32_nm)_Entry" class="mw-redirect" title="List of Intel Sandy Bridge-based Xeon microprocessors">§ "Sandy Bridge-EN" (32 nm) Entry</a>, and <a href="/wiki/List_of_Intel_Sandy_Bridge-based_Xeon_microprocessors#"Sandy_Bridge-EP"_(32_nm)_Efficient_Performance" class="mw-redirect" title="List of Intel Sandy Bridge-based Xeon microprocessors">§ "Sandy Bridge-EP" (32 nm) Efficient Performance</a></div> <p>The <b>Xeon E5-16xx</b> processors follow the previous Xeon 3500/3600-series products as the high-end single-socket platform, using the <a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a> package introduced with this processor. They share the Sandy Bridge-E platform with the single-socket Core i7-38xx and i7-39xx processors. The CPU chips have no integrated GPU but eight CPU cores, some of which are disabled in the entry-level products. The <b>Xeon E5-26xx</b> line has the same features but also enables multi-socket operation like the earlier Xeon 5000-series and Xeon 7000-series processors. </p> <div class="mw-heading mw-heading3"><h3 id="E5-14xx_v2/24xx_v2_series_"Ivy_Bridge-EN"_and_E5-16xx_v2/26xx_v2/46xx_v2_series_"Ivy_Bridge-EP""><span id="E5-14xx_v2.2F24xx_v2_series_.22Ivy_Bridge-EN.22_and_E5-16xx_v2.2F26xx_v2.2F46xx_v2_series_.22Ivy_Bridge-EP.22"></span><span class="anchor" id="E5-V2"></span>E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=52" title="Edit section: E5-14xx v2/24xx v2 series "Ivy Bridge-EN" and E5-16xx v2/26xx v2/46xx v2 series "Ivy Bridge-EP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Ivy_Bridge-EN" class="mw-redirect" title="Ivy Bridge-EN">Ivy Bridge-EN/EP</a>, <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E5-1xxx_v2_(uniprocessor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">List of Intel Ivy Bridge-based Xeon microprocessors § Xeon E5-1xxx v2 (uniprocessor)</a>, <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E5-2xxx_v2_(dual-processor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">§ Xeon E5-2xxx v2 (dual-processor)</a>, and <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E5-4xxx_v2_(quad-processor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">§ Xeon E5-4xxx v2 (quad-processor)</a></div> <p>The <b>Xeon E5 v2</b> line was an update, released in September 2013 to replace the original Xeon E5 processors with a variant based on the Ivy Bridge shrink. The maximum number of CPU cores was raised to 12 per processor module and the total L3 cache was upped to 30 MB.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> The consumer version of the Xeon E5-16xx v2 processor is the <a href="/wiki/List_of_Intel_Core_i7_processors#"Ivy_Bridge-E"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 processors">Core i7-48xx and 49xx</a>. </p> <div class="mw-heading mw-heading3"><h3 id="E7-28xx_v2/48xx_v2/88xx_v2_series_"Ivy_Bridge-EX""><span id="E7-28xx_v2.2F48xx_v2.2F88xx_v2_series_.22Ivy_Bridge-EX.22"></span><span class="anchor" id="E7-V2"></span>E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=53" title="Edit section: E7-28xx v2/48xx v2/88xx v2 series "Ivy Bridge-EX""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Ivy_Bridge-EX" class="mw-redirect" title="Ivy Bridge-EX">Ivy Bridge-EX</a>, <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E7-28xx_v2_(dual-processor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">List of Intel Ivy Bridge-based Xeon microprocessors § Xeon E7-28xx v2 (dual-processor)</a>, <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E7-48xx_v2_(quad-processor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">§ Xeon E7-48xx v2 (quad-processor)</a>, and <a href="/wiki/List_of_Intel_Ivy_Bridge-based_Xeon_microprocessors#Xeon_E7-88xx_v2_(octa-processor)" class="mw-redirect" title="List of Intel Ivy Bridge-based Xeon microprocessors">§ Xeon E7-88xx v2 (octa-processor)</a></div> <p>The <b>Xeon E7 v2</b> line was an update, released in February 2014 to replace the original Xeon E7 processors with a variant based on the Ivy Bridge shrink. There was no Sandy Bridge version of these processors but rather a Westmere version. </p> <div class="mw-heading mw-heading2"><h2 id="Haswell-based_Xeon">Haswell-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=54" title="Edit section: Haswell-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Haswell_(microarchitecture)#Server_processors" title="Haswell (microarchitecture)">Haswell (microarchitecture) § Server processors</a></div> <div class="mw-heading mw-heading3"><h3 id="E3-12xx_v3_series_"Haswell-WS""><span id="E3-12xx_v3_series_.22Haswell-WS.22"></span><span class="anchor" id="E3-V3"></span>E3-12xx v3 series "Haswell-WS"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=55" title="Edit section: E3-12xx v3 series "Haswell-WS""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Haswell-based_Xeon_microprocessors#"Haswell-WS"_(22_nm)" class="mw-redirect" title="List of Intel Haswell-based Xeon microprocessors">List of Intel Haswell-based Xeon microprocessors § "Haswell-WS" (22 nm)</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_E3-1241_v3_CPU.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Intel_Xeon_E3-1241_v3_CPU.jpg/220px-Intel_Xeon_E3-1241_v3_CPU.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Intel_Xeon_E3-1241_v3_CPU.jpg/330px-Intel_Xeon_E3-1241_v3_CPU.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Intel_Xeon_E3-1241_v3_CPU.jpg/440px-Intel_Xeon_E3-1241_v3_CPU.jpg 2x" data-file-width="1024" data-file-height="768" /></a><figcaption>Intel Xeon E3-1241 v3 CPU, sitting atop the inside part of its retail box that contains an OEM fan-cooled <a href="/wiki/Heatsink" class="mw-redirect" title="Heatsink">heatsink</a> </figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_E3_1220v3_pin_side.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Intel_Xeon_E3_1220v3_pin_side.jpg/220px-Intel_Xeon_E3_1220v3_pin_side.jpg" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Intel_Xeon_E3_1220v3_pin_side.jpg/330px-Intel_Xeon_E3_1220v3_pin_side.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2a/Intel_Xeon_E3_1220v3_pin_side.jpg/440px-Intel_Xeon_E3_1220v3_pin_side.jpg 2x" data-file-width="2448" data-file-height="3264" /></a><figcaption>Intel Xeon E3-1220 v3 CPU, pin side</figcaption></figure> <p>Introduced in May 2013, <b>Xeon E3-12xx v3</b> is the first Xeon series based on the Haswell microarchitecture. It uses the new <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a> socket, which was introduced with the desktop Core i5/i7 Haswell processors, incompatible with the LGA 1155 that was used in Xeon E3 and E3 v2. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is better power efficiency. </p> <div class="mw-heading mw-heading3"><h3 id="E5-16xx/26xx_v3_series_"Haswell-EP""><span id="E5-16xx.2F26xx_v3_series_.22Haswell-EP.22"></span><span class="anchor" id="E5-V3"></span><span class="anchor" id="HASWELL-EP"></span>E5-16xx/26xx v3 series "Haswell-EP"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=56" title="Edit section: E5-16xx/26xx v3 series "Haswell-EP""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/List_of_Intel_Haswell-based_Xeon_microprocessors#"Haswell-EN"_(22_nm)_Entry" class="mw-redirect" title="List of Intel Haswell-based Xeon microprocessors">List of Intel Haswell-based Xeon microprocessors § "Haswell-EN" (22 nm) Entry</a>, and <a href="/wiki/List_of_Intel_Haswell-based_Xeon_microprocessors#"Haswell-EP"_(22_nm)_Efficient_Performance" class="mw-redirect" title="List of Intel Haswell-based Xeon microprocessors">§ "Haswell-EP" (22 nm) Efficient Performance</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_E5-1650_v3_CPU.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c6/Intel_Xeon_E5-1650_v3_CPU.jpg/250px-Intel_Xeon_E5-1650_v3_CPU.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c6/Intel_Xeon_E5-1650_v3_CPU.jpg/330px-Intel_Xeon_E5-1650_v3_CPU.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c6/Intel_Xeon_E5-1650_v3_CPU.jpg/500px-Intel_Xeon_E5-1650_v3_CPU.jpg 2x" data-file-width="1024" data-file-height="768" /></a><figcaption>Intel Xeon E5-1650 v3 CPU; its retail box contains no OEM heatsink.</figcaption></figure> <p>Introduced in September 2014, <b>Xeon E5-16xx v3</b> and <b>Xeon E5-26xx v3</b> series use the new <a href="/wiki/LGA_2011-v3" class="mw-redirect" title="LGA 2011-v3">LGA 2011-v3</a> socket, which is incompatible with the LGA 2011 socket used by earlier Xeon E5 and E5 v2 generations based on Sandy Bridge and Ivy Bridge microarchitectures. Some of the main benefits of this generation, compared to the previous one, are improved power efficiency, higher core counts, and bigger <a href="/wiki/Last_level_cache" class="mw-redirect" title="Last level cache">last level caches</a> (LLCs). Following the already used nomenclature, Xeon E5-26xx v3 series allows dual-socket operation. </p><p>One of the new features of this generation is that Xeon E5 v3 models with more than 10 cores support <a href="/wiki/Cluster_on_die" class="mw-redirect" title="Cluster on die">cluster on die</a> (COD) operation mode, allowing CPU's multiple columns of cores and LLC slices to be logically divided into what is presented as two <a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">non-uniform memory access</a> (NUMA) CPUs to the operating system. By keeping data and instructions local to the "partition" of CPU which is processing them, thus decreasing the LLC access latency, COD brings performance improvements to NUMA-aware operating systems and applications.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="E7-48xx/88xx_v3_series_"Haswell-EX""><span id="E7-48xx.2F88xx_v3_series_.22Haswell-EX.22"></span><span class="anchor" id="E7-V3"></span>E7-48xx/88xx v3 series "Haswell-EX"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=57" title="Edit section: E7-48xx/88xx v3 series "Haswell-EX""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Haswell-based_Xeon_microprocessors#"Haswell-EX"_(22_nm)_Expandable" class="mw-redirect" title="List of Intel Haswell-based Xeon microprocessors">List of Intel Haswell-based Xeon microprocessors § "Haswell-EX" (22 nm) Expandable</a></div> <p>Introduced in May 2015, <b>Xeon E7-48xx v3</b> and <b>Xeon E7-88xx v3</b> series provide higher core counts, higher per-core performance and improved reliability features, compared to the previous Xeon E7 v2 generation. Following the usual SKU nomenclature, Xeon E7-48xx v3 and E7-88xx v3 series allow multi-socket operation, supporting up to quad- and eight-socket configurations, respectively.<sup id="cite_ref-cpu-world-2015050701_45-0" class="reference"><a href="#cite_note-cpu-world-2015050701-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-anandtech-9193_46-0" class="reference"><a href="#cite_note-anandtech-9193-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> These processors use the LGA 2011 (R1) socket.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>Xeon E7-48xx v3 and E7-88xx v3 series contain a quad-channel <a href="/wiki/Integrated_memory_controller" class="mw-redirect" title="Integrated memory controller">integrated memory controller</a> (IMC), supporting both DDR3 and DDR4 <a href="/wiki/LRDIMM" class="mw-redirect" title="LRDIMM">LRDIMM</a> or <a href="/wiki/RDIMM" class="mw-redirect" title="RDIMM">RDIMM</a> memory modules through the use of <i>Jordan Creek</i> (DDR3) or <i>Jordan Creek 2</i> (DDR4) memory buffer chips. Both versions of the memory buffer chip connect to the processor using version 2.0 of the Intel <a href="/wiki/Scalable_Memory_Interconnect" class="mw-redirect" title="Scalable Memory Interconnect">Scalable Memory Interconnect</a> (SMI) interface, while supporting <a href="/wiki/Lockstep_memory" class="mw-redirect" title="Lockstep memory">lockstep memory</a> layouts for improved reliability. Up to four memory buffer chips can be connected to a processor, with up to six DIMM slots supported per each memory buffer chip.<sup id="cite_ref-cpu-world-2015050701_45-1" class="reference"><a href="#cite_note-cpu-world-2015050701-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-anandtech-9193_46-1" class="reference"><a href="#cite_note-anandtech-9193-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </p><p>Xeon E7-48xx v3 and E7-88xx v3 series also contain functional bug-free support for <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">Transactional Synchronization Extensions</a> (TSX), which was disabled via a <a href="/wiki/Microcode" title="Microcode">microcode</a> update in August 2014 for Haswell-E, Haswell-WS (E3-12xx v3) and Haswell-EP (E5-16xx/26xx v3) models, due to a bug that was discovered in the TSX implementation.<sup id="cite_ref-cpu-world-2015050701_45-2" class="reference"><a href="#cite_note-cpu-world-2015050701-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-anandtech-9193_46-2" class="reference"><a href="#cite_note-anandtech-9193-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Broadwell-based_Xeon">Broadwell-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=58" title="Edit section: Broadwell-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Broadwell_(microarchitecture)#Server_processors" title="Broadwell (microarchitecture)">Broadwell (microarchitecture) § Server processors</a></div> <div class="mw-heading mw-heading3"><h3 id="E3-12xx_v4_series_"Broadwell-H""><span id="E3-12xx_v4_series_.22Broadwell-H.22"></span><span class="anchor" id="E3-V4"></span>E3-12xx v4 series "Broadwell-H"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=59" title="Edit section: E3-12xx v4 series "Broadwell-H""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Introduced in June 2015, <b>Xeon E3-12xx v4</b> is the first Xeon series based on the Broadwell microarchitecture. It uses <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a> socket, which was introduced with the desktop Core i5/i7 Haswell processors. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. The main benefit of the new microarchitecture is the new lithography process, which results in better power efficiency. </p> <div class="mw-heading mw-heading2"><h2 id="Skylake-based_Xeon">Skylake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=60" title="Edit section: Skylake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Skylake_(microarchitecture)#Server_processors" title="Skylake (microarchitecture)">Skylake (microarchitecture) § Server processors</a></div> <div class="mw-heading mw-heading3"><h3 id="E3-12xx_v5_series_"Skylake-S""><span id="E3-12xx_v5_series_.22Skylake-S.22"></span><span class="anchor" id="E3-V5"></span>E3-12xx v5 series "Skylake-S"</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=61" title="Edit section: E3-12xx v5 series "Skylake-S""><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Introduced in October 2015, <b>Xeon E3-12xx v5</b> is the first Xeon series based on the Skylake microarchitecture. It uses new <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a> socket, which was introduced with the desktop Core i5/i7 Skylake processors. Although it uses the same socket as consumer processors, it is limited to the C200 server chipset series and will not work with consumer chipsets like Z170. As before, the main difference between the desktop and server versions is added support for ECC memory in the Xeon-branded parts. </p> <div class="mw-heading mw-heading2"><h2 id="Kaby_Lake-based_Xeon">Kaby Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=62" title="Edit section: Kaby Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a></div> <div class="mw-heading mw-heading3"><h3 id="E3-12xx_v6_series"><span class="anchor" id="E3-V5"></span>E3-12xx v6 series</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=63" title="Edit section: E3-12xx v6 series"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Introduced in January 2017, <b>Xeon E3-12xx v6</b> is the first Xeon series based on the Kaby Lake microarchitecture. It uses the same <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a> socket, which was introduced with the desktop Core i5/i7 Kaby Lake processors. As before, the main difference between the desktop and server versions is added support for ECC memory and improved energy efficiency in the Xeon-branded parts. </p> <div class="mw-heading mw-heading2"><h2 id="Coffee_Lake-based_Xeon">Coffee Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=64" title="Edit section: Coffee Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a></div> <div class="mw-heading mw-heading3"><h3 id="Coffee_Lake-E_(Server/Workstation)"><span id="Coffee_Lake-E_.28Server.2FWorkstation.29"></span>Coffee Lake-E (Server/Workstation)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=65" title="Edit section: Coffee Lake-E (Server/Workstation)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align: center;"> <tbody><tr> <th>Processor<br />branding </th> <th>Model </th> <th><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th>Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th>Max. <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> <p>clock rate </p> </th> <th><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th>max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th>L3<br />cache <sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>note 1<span class="cite-bracket">]</span></a></sup> </th> <th>TDP </th> <th>Memory<br />support </th> <th>Price<br />(USD) </th></tr> <tr> <td rowspan="11">Xeon E </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134855/intel-xeon-e2186g-processor-12m-cache-up-to-4-70-ghz.html">2186G</a> </td> <td rowspan="2">6 (12) </td> <td>3.8 GHz </td> <td rowspan="3">4.7 GHz </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD P630</a> </td> <td rowspan="5">1.20 GHz </td> <td rowspan="2">12 MB </td> <td>95 W </td> <td rowspan="11">Up to 64 GB<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>note 2<span class="cite-bracket">]</span></a></sup><br />DDR4 2666<br /><a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a><br />supported </td> <td>$506 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134860/intel-xeon-e2176g-processor-12m-cache-up-to-4-70-ghz.html">2176G</a> </td> <td>3.7 GHz </td> <td>80 W </td> <td>$406 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134864/intel-xeon-e2174g-processor-8m-cache-up-to-4-70-ghz.html">2174G</a> </td> <td>4 (8) </td> <td>3.8 GHz </td> <td>8 MB </td> <td>71 W </td> <td>$370 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134866/intel-xeon-e2146g-processor-12m-cache-up-to-4-50-ghz.html">2146G</a> </td> <td>6 (12) </td> <td>3.5 GHz </td> <td rowspan="6">4.5 GHz </td> <td>12 MB </td> <td>80 W </td> <td>$350 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134862/intel-xeon-e2144g-processor-8m-cache-up-to-4-50-ghz.html">2144G</a> </td> <td>4 (8) </td> <td>3.6 GHz </td> <td>8 MB </td> <td>71 W </td> <td>$306 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134857/intel-xeon-e2136-processor-12m-cache-up-to-4-50-ghz.html">2136</a> </td> <td>6 (12) </td> <td>3.3 GHz </td> <td colspan="2" rowspan="2">N/A </td> <td>12 MB </td> <td>80 W </td> <td>$319 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134858/intel-xeon-e2134-processor-8m-cache-up-to-4-50-ghz.html">2134</a> </td> <td>4 (8) </td> <td>3.5 GHz </td> <td>8 MB </td> <td>71 W </td> <td>$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134863/intel-xeon-e2126g-processor-12m-cache-up-to-4-50-ghz.html">2126G</a> </td> <td>6 (6) </td> <td>3.3 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD P630</a> </td> <td rowspan="2">1.20 GHz </td> <td>12 MB </td> <td>80 W </td> <td>$286 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134854/intel-xeon-e2124g-processor-8m-cache-up-to-4-50-ghz.html">2124G</a> </td> <td rowspan="3">4 (4) </td> <td>3.4 GHz </td> <td rowspan="3">8 MB </td> <td rowspan="2">71 W </td> <td>$245 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134856/intel-xeon-e2124-processor-8m-cache-up-to-4-30-ghz.html">2124</a> </td> <td>3.3 GHz </td> <td>4.3 GHz </td> <td colspan="2">N/A </td> <td>$217 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134929/intel-xeon-e2104g-processor-8m-cache-3-20-ghz.html">2104G</a> </td> <td>3.2 GHz </td> <td>N/A </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD P630</a> </td> <td>1.20 GHz </td> <td>65 W </td> <td>$193 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Coffee_Lake-E_Refresh_(Server/Workstation)"><span id="Coffee_Lake-E_Refresh_.28Server.2FWorkstation.29"></span>Coffee Lake-E Refresh (Server/Workstation)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=66" title="Edit section: Coffee Lake-E Refresh (Server/Workstation)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align: center;"> <tbody><tr> <th>Processor<br />branding </th> <th>Model </th> <th><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th>Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th>Max. <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> <p>clock rate </p> </th> <th><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th>max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th>L3<br />cache <sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>note 3<span class="cite-bracket">]</span></a></sup> </th> <th>TDP </th> <th>Memory<br />support </th> <th>Price<br />(USD) </th></tr> <tr> <td rowspan="12">Xeon E </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193743/intel-xeon-e-2288g-processor-16m-cache-3-70-ghz.html">2288G</a> </td> <td>8 (16) </td> <td>3.7 GHz </td> <td>5.0 GHz </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD P630</a> </td> <td rowspan="7">1.20 GHz </td> <td>16 MiB </td> <td rowspan="2">95 W </td> <td rowspan="12">Up to 128 GB<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>note 4<span class="cite-bracket">]</span></a></sup><br />DDR4 2666<br /><a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a><br />supported </td> <td>$539 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191033/intel-xeon-e-2286g-processor-12m-cache-4-00-ghz.html">2286G</a> </td> <td>6 (12) </td> <td>4.0 GHz </td> <td>4.9 GHz </td> <td>12 MiB </td> <td>$450 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193745/intel-xeon-e-2278g-processor-16m-cache-3-40-ghz.html">2278G</a> </td> <td>8 (16) </td> <td>3.4 GHz </td> <td>5.0 GHz </td> <td>16 MiB </td> <td rowspan="2">80 W </td> <td>$494 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191035/intel-xeon-e-2276g-processor-12m-cache-3-80-ghz.html">2276G</a> </td> <td>6 (12) </td> <td>3.8 GHz </td> <td rowspan="2">4.9 GHz </td> <td>12 MiB </td> <td>$362 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191042/intel-xeon-e-2274g-processor-8m-cache-4-00-ghz.html">2274G</a> </td> <td>4 (8) </td> <td>4.0 GHz </td> <td>8 MiB </td> <td>83 W </td> <td>$328 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191043/intel-xeon-e-2246g-processor-12m-cache-3-60-ghz.html">2246G</a> </td> <td>6 (12) </td> <td>3.6 GHz </td> <td rowspan="4">4.8 GHz </td> <td>12 MiB </td> <td>80 W </td> <td>$311 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191041/intel-xeon-e-2244g-processor-8m-cache-3-80-ghz.html">2244G</a> </td> <td>4 (8) </td> <td>3.8 GHz </td> <td>8 MiB </td> <td>71 W </td> <td>$272 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191040/intel-xeon-e-2236-processor-12m-cache-3-40-ghz.html">2236</a> </td> <td>6 (12) </td> <td>3.4 GHz </td> <td colspan="2" rowspan="2">N/A </td> <td>12 MiB </td> <td>80 W </td> <td>$284 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191039/intel-xeon-e-2234-processor-8m-cache-3-60-ghz.html">2234</a> </td> <td>4 (8) </td> <td>3.6 GHz </td> <td>8 MiB </td> <td>71 W </td> <td>$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191038/intel-xeon-e-2226g-processor-12m-cache-3-40-ghz.html">2226G</a> </td> <td>6 (6) </td> <td>3.4 GHz </td> <td rowspan="2">4.7 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD P630</a> </td> <td rowspan="2">1.20 GHz </td> <td>12 MiB </td> <td>80 W </td> <td>$255 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191037/intel-xeon-e-2224g-processor-8m-cache-3-50-ghz.html">2224G</a> </td> <td rowspan="2">4 (4) </td> <td>3.5 GHz </td> <td rowspan="2">8 MiB </td> <td rowspan="2">71 W </td> <td>$213 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191036/intel-xeon-e-2224-processor-8m-cache-3-40-ghz.html">2224</a> </td> <td>3.4 GHz </td> <td>4.6 GHz </td> <td colspan="2">N/A </td> <td>$193 </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Comet_Lake-based_Xeon">Comet Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=67" title="Edit section: Comet Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a></div> <div class="mw-heading mw-heading2"><h2 id="Cascade_Lake-based_Xeon">Cascade Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=68" title="Edit section: Cascade Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_Intel_Cascade_Lake-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Cascade Lake-based Xeon microprocessors">List of Intel Cascade Lake-based Xeon microprocessors</a></div> <div class="mw-heading mw-heading3"><h3 id="Variants">Variants</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=69" title="Edit section: Variants"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Server: Cascade Lake-SP (Scalable Performance; meaning multi physical processors configuration), Cascade Lake-AP (Advanced Performance)</li> <li>Workstation: Cascade Lake-W</li> <li>Enthusiast: Cascade Lake-X</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cooper_Lake-based_Xeon">Cooper Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=70" title="Edit section: Cooper Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cooper_Lake_(microprocessor)" title="Cooper Lake (microprocessor)">Cooper Lake (microprocessor)</a></div><p>The 3rd generation Xeon SP processors for 4S and 8S. </p><div class="mw-heading mw-heading2"><h2 id="Ice_Lake-based_Xeon">Ice Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=71" title="Edit section: Ice Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake (microprocessor)</a></div><p>The 3rd generation Xeon SP processors for WS, 1S and 2S. </p><div class="mw-heading mw-heading2"><h2 id="Rocket_Lake-based_Xeon">Rocket Lake-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=72" title="Edit section: Rocket Lake-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a></div> <div class="mw-heading mw-heading2"><h2 id="Sapphire_Rapids-based_Xeon">Sapphire Rapids-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=73" title="Edit section: Sapphire Rapids-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids (microprocessor)</a></div><p>Introduced in 2023, the <b>4th generation Xeon Scalable</b> processors (<b>Sapphire Rapids-SP</b> and <b>Sapphire Rapids-HBM</b>) and <b>Xeon W-2400</b> and <b>W-3400</b> series (<b>Sapphire Rapids-WS</b>) provide large performance enhancements over the prior generation. </p><div class="mw-heading mw-heading3"><h3 id="Features">Features</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=74" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="CPU">CPU</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=75" title="Edit section: CPU"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/Golden_Cove_(microarchitecture)" class="mw-redirect" title="Golden Cove (microarchitecture)">Golden Cove (microarchitecture)</a></div> <ul><li>Up to 60 <a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a> CPU cores per package</li> <li><a href="/wiki/AVX-512#FP16" title="AVX-512">AVX512-FP16</a></li> <li><a href="/wiki/Transactional_Synchronization_Extensions#TSX_Suspend_Load_Address_Tracking" title="Transactional Synchronization Extensions">TSX Suspend Load Address Tracking (<code>TSXLDTRK</code>)</a></li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">Advanced Matrix Extensions</a> (AMX)</li> <li>Trust Domain Extensions (TDX), a collection of technologies to help deploy hardware-isolated virtual machines (VMs) called trust domains (TDs)</li> <li>In-Field Scan (IFS), a technology that allows for testing the processor for potential hardware faults without taking it completely offline</li> <li>Data Streaming Accelerator (DSA), allows for speeding up data copy and transformation between different kinds of storage</li> <li>QuickAssist Technology (QAT), allows for improved performance of compression and encryption tasks</li> <li>Dynamic Load Balancer (DLB), allows for offloading tasks of load balancing, packet prioritization and queue management</li> <li>In-Memory Analytics Accelerator (IAA), allows accelerating in-memory databases and big data analytics</li></ul> <p>Not all accelerators are available in all processor models. Some accelerators are available under the Intel On Demand program, also known as Software Defined Silicon (SDSi), where a license is required to activate a given accelerator that is physically present in the processor. The license can be obtained as a one-time purchase or as a paid subscription. Activating the license requires support in the operating system. A driver with the necessary support was added in Linux kernel version 6.2. </p> <div class="mw-heading mw-heading4"><h4 id="I/O"><span id="I.2FO"></span>I/O</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=76" title="Edit section: I/O"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/PCI_Express#PCI_Express_5.0" title="PCI Express">PCI Express 5.0</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface 4.0</a></li> <li>8-channel <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> memory support up to DDR5-4800, up to 2 DIMMs per channel</li> <li>On-package <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory 2e</a> memory as L4 cache on Xeon Max models</li> <li><a href="/wiki/Compute_Express_Link" title="Compute Express Link">Compute Express Link</a> 1.1</li></ul> <div class="mw-heading mw-heading2"><h2 id="Emerald_Rapids-based_Xeon">Emerald Rapids-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=77" title="Edit section: Emerald Rapids-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Emerald_Rapids" title="Emerald Rapids">Emerald Rapids</a></div> <div class="mw-heading mw-heading2"><h2 id="Granite_Rapids-based_Xeon">Granite Rapids-based Xeon</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=78" title="Edit section: Granite Rapids-based Xeon"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Granite_Rapids" title="Granite Rapids">Granite Rapids</a></div> <div class="mw-heading mw-heading2"><h2 id="Supercomputers">Supercomputers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=79" title="Edit section: Supercomputers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>By 2013 Xeon processors were ubiquitous in supercomputers—more than 80% of the <a href="/wiki/TOP500" title="TOP500">TOP500</a> machines in 2013 used them. For the fastest machines, much of the performance comes from compute accelerators; Intel's entry into that market was the <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a>, the first machines using it appeared in June 2012 and by June 2013 it was used in the fastest computer in the world. </p> <ul><li>The first Xeon-based machines in the top-10 appeared in November 2002, two clusters at <a href="/wiki/Lawrence_Livermore_National_Laboratory" title="Lawrence Livermore National Laboratory">Lawrence Livermore National Laboratory</a> and at <a href="/wiki/National_Oceanic_and_Atmospheric_Administration" title="National Oceanic and Atmospheric Administration">NOAA</a>.</li> <li>The first Xeon-based machine to be in the first place of the TOP500 was the Chinese <a href="/wiki/Tianhe-I" class="mw-redirect" title="Tianhe-I">Tianhe-I</a>A in November 2010, which used a mixed Xeon-Nvidia GPU configuration; it was overtaken by the Japanese <a href="/wiki/K_computer" title="K computer">K computer</a> in 2012, but the <a href="/wiki/Tianhe-2" title="Tianhe-2">Tianhe-2</a> system using 12-core Xeon E5-2692 processors and <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> cards occupied the first place in both TOP500 lists of 2013.</li> <li>The <a href="/wiki/SuperMUC" title="SuperMUC">SuperMUC</a> system, using eight-core Xeon E5-2680 processors but no accelerator cards, managed fourth place in June 2012 and had dropped to tenth by November 2013</li> <li>Xeon processor-based systems are among the top 20 fastest systems by memory bandwidth as measured by the STREAM benchmark.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup></li> <li>An Intel Xeon virtual SMP system using ScaleMP's Versatile SMP (vSMP) architecture with 128 cores and 1 <a href="/wiki/Tebibyte" class="mw-redirect" title="Tebibyte">TiB</a> RAM.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> This system aggregates 16 Stoakley platform (Seaburg chipset) systems with total of 32 <a href="#5400-series_"Harpertown"">Harpertown</a> processors.</li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=80" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Epyc" title="Epyc">AMD Epyc</a></li> <li><a href="/wiki/Opteron" title="Opteron">AMD Opteron</a></li> <li><a href="/wiki/Itanium" title="Itanium">Intel Itanium</a></li> <li>Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a>, brand name for family of products using the <a href="/wiki/Intel_MIC" class="mw-redirect" title="Intel MIC">Intel MIC</a> architecture</li> <li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">List of Intel processors</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">List of Intel Xeon processors</a></li></ul></li> <li><a href="/wiki/List_of_Macintosh_models_grouped_by_CPU_type" class="mw-redirect" title="List of Macintosh models grouped by CPU type">List of Macintosh models grouped by CPU type</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=81" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text">MiB = MB = 1024 kB</span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text">128 GB after BIOS update</span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text">MiB = MB = 1024 kB</span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text">GB = 1024 MB = 1024^2 kB = 1024^3 B</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=82" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFCutress2021" class="citation web cs1">Cutress, Ian (November 15, 2021). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/17067/intel-sapphire-rapids-with-64-gb-of-hbm2e-ponte-vecchio-with-408-mb-l2-cache">"Intel: Sapphire Rapids With 64 GB of HBM2e, Ponte Vecchio with 408 MB L2 Cache"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">December 11,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Intel%3A+Sapphire+Rapids+With+64+GB+of+HBM2e%2C+Ponte+Vecchio+with+408+MB+L2+Cache&rft.date=2021-11-15&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F17067%2Fintel-sapphire-rapids-with-64-gb-of-hbm2e-ponte-vecchio-with-408-mb-l2-cache&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXeon" class="Z3988"></span></span> </li> <li id="cite_note-Xeon_W_series-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-Xeon_W_series_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Xeon_W_series_2-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Xeon_W_series_2-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Xeon_W_series_2-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-new-xeon-workstation-processors.html#gs.qeb2cq">"Intel Launches New Xeon Workstation Processors – the Ultimate Solution for Professionals"</a>. <i>Intel</i><span class="reference-accessdate">. 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Retrieved <span class="nowrap">December 10,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=University+of+Virginia&rft.atitle=STREAM+benchmark&rft.aulast=McCalpin&rft.aufirst=John+D.&rft_id=http%3A%2F%2Fwww.cs.virginia.edu%2Fstream%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXeon" class="Z3988"></span></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cs.virginia.edu/stream/top20/Bandwidth.html">"STREAM "Top20" results"</a>. <i>University of Virginia</i><span class="reference-accessdate">. Retrieved <span class="nowrap">December 10,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=University+of+Virginia&rft.atitle=STREAM+%22Top20%22+results&rft_id=http%3A%2F%2Fwww.cs.virginia.edu%2Fstream%2Ftop20%2FBandwidth.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AXeon" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Xeon&action=edit&section=83" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid 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href="/wiki/Template:Intel_processors" title="Template:Intel processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel_processors" title="Template talk:Intel processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel_processors" title="Special:EditPage/Template:Intel processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel_processors144" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Intel_Core#Core_and_Core_Ultra_3/5/7/9" title="Intel Core">Core Ultra</a> <ul><li><a href="/wiki/Intel_Core#Series_1" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#Series_2" title="Intel Core">2nd gen</a></li></ul></li> <li><a class="mw-selflink selflink">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a class="mw-selflink selflink">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a class="mw-selflink selflink">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table></div>    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