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class="vector-toc-list"> <li id="toc-Hardware_Lock_Elision" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Hardware_Lock_Elision"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Hardware Lock Elision</span> </div> </a> <ul id="toc-Hardware_Lock_Elision-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Restricted_Transactional_Memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Restricted_Transactional_Memory"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Restricted Transactional Memory</span> </div> </a> <ul id="toc-Restricted_Transactional_Memory-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-XTEST_instruction" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#XTEST_instruction"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>XTEST instruction</span> </div> </a> <ul id="toc-XTEST_instruction-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-TSX_Suspend_Load_Address_Tracking" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#TSX_Suspend_Load_Address_Tracking"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>TSX Suspend Load Address Tracking</span> </div> </a> <ul id="toc-TSX_Suspend_Load_Address_Tracking-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Implementation" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Implementation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Implementation</span> </div> </a> <ul id="toc-Implementation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-History_and_bugs" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#History_and_bugs"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>History and bugs</span> </div> </a> <ul id="toc-History_and_bugs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Extension to the x86 instruction set architecture that adds hardware transactional memory support</div> <p><b>Transactional Synchronization Extensions</b> (<b>TSX</b>), also called <b>Transactional Synchronization Extensions New Instructions</b> (<b>TSX-NI</b>), is an extension to the <a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA) that adds hardware <a href="/wiki/Transactional_memory" title="Transactional memory">transactional memory</a> support, speeding up execution of multi-threaded software through lock elision. According to different benchmarks, TSX/TSX-NI can provide around 40% faster applications execution in specific workloads, and 4–5 times more database <a href="/wiki/Transactions_per_second" title="Transactions per second">transactions per second</a> (TPS).<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>TSX/TSX-NI was documented by <a href="/wiki/Intel" title="Intel">Intel</a> in February 2012, and debuted in June 2013 on selected Intel <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> based on the <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> microarchitecture.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Haswell processors below 45xx as well as R-series and K-series (with unlocked multiplier) <a href="/wiki/Stock_keeping_unit" title="Stock keeping unit">SKUs</a> do not support TSX/TSX-NI.<sup id="cite_ref-comparison_8-0" class="reference"><a href="#cite_note-comparison-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> In August 2014, Intel announced a bug in the TSX/TSX-NI implementation on current steppings of Haswell, Haswell-E, Haswell-EP and early <a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a> CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a <a href="/wiki/Microcode" title="Microcode">microcode</a> update.<sup id="cite_ref-techreport-26911_9-0" class="reference"><a href="#cite_note-techreport-26911-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-intel-spec-update_10-0" class="reference"><a href="#cite_note-intel-spec-update-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p>In 2016, a <a href="/wiki/Side-channel_attack" title="Side-channel attack">side-channel</a> <a href="/wiki/Timing_attack" title="Timing attack">timing attack</a> was found by abusing the way TSX/TSX-NI handles transactional faults (i.e. <a href="/wiki/Page_fault" title="Page fault">page faults</a>) in order to break <a href="/wiki/KASLR" class="mw-redirect" title="KASLR">kernel address space layout randomization</a> (KASLR) on all major operating systems.<sup id="cite_ref-Breaking_Kernel_Address_Space_Layout_Randomization_with_Intel_TSX_11-0" class="reference"><a href="#cite_note-Breaking_Kernel_Address_Space_Layout_Randomization_with_Intel_TSX-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> In 2021, Intel released a microcode update that disabled the TSX/TSX-NI feature on CPU generations from <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> to <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a>, as a mitigation for discovered security issues.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>Support for TSX/TSX-NI emulation is provided as part of the Intel Software Development Emulator.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> There is also experimental support for TSX/TSX-NI emulation in a <a href="/wiki/QEMU" title="QEMU">QEMU</a> fork.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Features">Features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=1" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TSX/TSX-NI provides two software interfaces for designating code regions for transactional execution. <b>Hardware Lock Elision</b> (HLE) is an instruction prefix-based interface designed to be backward compatible with processors without TSX/TSX-NI support. <b>Restricted Transactional Memory</b> (RTM) is a new instruction set interface that provides greater flexibility for programmers.<sup id="cite_ref-anandtech-tsx_15-0" class="reference"><a href="#cite_note-anandtech-tsx-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p>TSX/TSX-NI enables <a href="/wiki/Speculative_execution" title="Speculative execution">optimistic execution</a> of transactional code regions. The hardware monitors multiple threads for conflicting memory accesses, while aborting and rolling back transactions that cannot be successfully completed. Mechanisms are provided for software to detect and handle failed transactions.<sup id="cite_ref-anandtech-tsx_15-1" class="reference"><a href="#cite_note-anandtech-tsx-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p>In other words, lock elision through transactional execution uses memory transactions as a fast path where possible, while the slow (fallback) path is still a normal lock. </p> <div class="mw-heading mw-heading3"><h3 id="Hardware_Lock_Elision"><span class="anchor" id="HLE"></span>Hardware Lock Elision</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=2" title="Edit section: Hardware Lock Elision"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Hardware Lock Elision (HLE) adds two new instruction prefixes, <code>XACQUIRE</code> and <code>XRELEASE</code>. These two prefixes reuse the <a href="/wiki/Opcodes" class="mw-redirect" title="Opcodes">opcodes</a> of the existing <code>REPNE</code> / <code>REPE</code> prefixes (<code>F2H</code> / <code>F3H</code>). On processors that do not support HLE, <code>REPNE</code> / <code>REPE</code> prefixes are ignored on instructions for which the <code>XACQUIRE</code> / <code>XRELEASE</code> are valid, thus enabling backward compatibility.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>The <code>XACQUIRE</code> prefix hint can only be used with the following instructions with an explicit <code>LOCK</code> prefix: <code>ADD</code>, <code>ADC</code>, <code>AND</code>, <code>BTC</code>, <code>BTR</code>, <code>BTS</code>, <code>CMPXCHG</code>, <code>CMPXCHG8B</code>, <code>DEC</code>, <code>INC</code>, <code>NEG</code>, <code>NOT</code>, <code>OR</code>, <code>SBB</code>, <code>SUB</code>, <code>XOR</code>, <code>XADD</code>, and <code>XCHG</code>. The <code>XCHG</code> instruction can be used without the <code>LOCK</code> prefix as well. </p><p>The <code>XRELEASE</code> prefix hint can be used both with the instructions listed above, and with the <code>MOV mem, reg</code> and <code>MOV mem, imm</code> instructions. </p><p>HLE allows optimistic execution of a critical section by skipping the write to a lock, so that the lock appears to be free to other threads. A failed transaction results in execution restarting from the <code>XACQUIRE</code>-prefixed instruction, but treating the instruction as if the <code>XACQUIRE</code> prefix were not present. </p> <div class="mw-heading mw-heading3"><h3 id="Restricted_Transactional_Memory"><span class="anchor" id="RTM"></span>Restricted Transactional Memory</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=3" title="Edit section: Restricted Transactional Memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Restricted Transactional Memory (RTM) is an alternative implementation to HLE which gives the programmer the flexibility to specify a fallback code path that is executed when a transaction cannot be successfully executed. Unlike HLE, RTM is not backward compatible with processors that do not support it. For backward compatibility, programs are required to detect support for RTM in the CPU before using the new instructions. </p><p>RTM adds three new instructions: <code>XBEGIN</code>, <code>XEND</code> and <code>XABORT</code>. The <code>XBEGIN</code> and <code>XEND</code> instructions mark the start and the end of a transactional code region; the <code>XABORT</code> instruction explicitly aborts a transaction. Transaction failure redirects the processor to the fallback code path specified by the <code>XBEGIN</code> instruction, with the abort status returned in the <code>EAX</code> register. </p> <table class="wikitable"> <tbody><tr> <th>EAX register<br />bit position</th> <th>Meaning </th></tr> <tr> <td style="text-align:center;">0</td> <td>Set if abort caused by <code>XABORT</code> instruction. </td></tr> <tr> <td style="text-align:center;">1</td> <td>If set, the transaction may succeed on a retry. This bit is always clear if bit 0 is set. </td></tr> <tr> <td style="text-align:center;">2</td> <td>Set if another logical processor conflicted with a memory address that was part of the transaction that aborted. </td></tr> <tr> <td style="text-align:center;">3</td> <td>Set if an internal buffer overflowed. </td></tr> <tr> <td style="text-align:center;">4</td> <td>Set if debug breakpoint was hit. </td></tr> <tr> <td style="text-align:center;">5</td> <td>Set if an abort occurred during execution of a nested transaction. </td></tr> <tr> <td style="text-align:center;">23:6</td> <td>Reserved. </td></tr> <tr> <td style="text-align:center;">31:24</td> <td><code>XABORT</code> argument (only valid if bit 0 set, otherwise reserved). </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="XTEST_instruction"><code>XTEST</code> instruction</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=4" title="Edit section: XTEST instruction"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TSX/TSX-NI provides a new <code>XTEST</code> instruction that returns whether the processor is executing a transactional region. This instruction is supported by the processor if it supports HLE or RTM or both. </p> <div class="mw-heading mw-heading3"><h3 id="TSX_Suspend_Load_Address_Tracking"><span class="anchor" id="TSXLDTRK"></span>TSX Suspend Load Address Tracking</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=5" title="Edit section: TSX Suspend Load Address Tracking"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>TSX/TSX-NI Suspend Load Address Tracking (TSXLDTRK) is an instruction set extension that allows to temporarily disable tracking loads from memory in a section of code within a transactional region. This feature extends HLE and RTM, and its support in the processor must be detected separately. </p><p>TSXLDTRK introduces two new instructions, <code>XSUSLDTRK</code> and <code>XRESLDTRK</code>, for suspending and resuming load address tracking, respectively. While the tracking is suspended, any loads from memory will not be added to the transaction read set. This means that, unless these memory locations were added to the transaction read or write sets outside the suspend region, writes at these locations by other threads will not cause transaction abort. Suspending load address tracking for a portion of code within a transactional region allows to reduce the amount of memory that needs to be tracked for read-write conflicts and therefore increase the probability of successful commit of the transaction. </p> <div class="mw-heading mw-heading2"><h2 id="Implementation">Implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=6" title="Edit section: Implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Transactional_memory#Available_implementations" title="Transactional memory">Transactional memory § Available implementations</a></div> <p>Intel's TSX/TSX-NI specification describes how the transactional memory is exposed to programmers, but withholds details on the actual transactional memory implementation.<sup id="cite_ref-haswell-tm_17-0" class="reference"><a href="#cite_note-haswell-tm-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> Intel specifies in its developer's and optimization manuals that Haswell maintains both read-sets and write-sets at the granularity of a cache line, tracking addresses in the L1 data cache of the processor.<sup id="cite_ref-intel-arch-sdm_18-0" class="reference"><a href="#cite_note-intel-arch-sdm-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-intel-arch-optimization_19-0" class="reference"><a href="#cite_note-intel-arch-optimization-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Intel also states that data conflicts are detected through the <a href="/wiki/Cache_coherence" title="Cache coherence">cache coherence</a> protocol.<sup id="cite_ref-intel-arch-optimization_19-1" class="reference"><a href="#cite_note-intel-arch-optimization-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>Haswell's L1 data cache has an associativity of eight. This means that in this implementation, a transactional execution that writes to nine distinct locations mapping to the same cache set will abort. However, due to micro-architectural implementations, this does not mean that fewer accesses to the same set are guaranteed to never abort. Additionally, in CPU configurations with <a href="/wiki/Hyper-Threading_Technology" class="mw-redirect" title="Hyper-Threading Technology">Hyper-Threading Technology</a>, the L1 cache is shared between the two threads on the same core, so operations in a sibling logical processor of the same core can cause evictions.<sup id="cite_ref-intel-arch-optimization_19-2" class="reference"><a href="#cite_note-intel-arch-optimization-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>Independent research points into Haswell’s transactional memory most likely being a deferred update system using the per-core caches for transactional data and register checkpoints.<sup id="cite_ref-haswell-tm_17-1" class="reference"><a href="#cite_note-haswell-tm-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> In other words, Haswell is more likely to use the cache-based transactional memory system, as it is a much less risky implementation choice. On the other hand, Intel's <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> or later may combine this cache-based approach with <i>memory ordering buffer</i> (MOB) for the same purpose, possibly also providing multi-versioned transactional memory that is more amenable to <a href="/wiki/Speculative_multithreading" title="Speculative multithreading">speculative multithreading</a>.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="History_and_bugs">History and bugs</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=7" title="Edit section: History and bugs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In August 2014, Intel announced that a bug exists in the TSX/TSX-NI implementation on Haswell, Haswell-E, Haswell-EP and early Broadwell CPUs, which resulted in disabling the TSX/TSX-NI feature on affected CPUs via a microcode update.<sup id="cite_ref-techreport-26911_9-1" class="reference"><a href="#cite_note-techreport-26911-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-intel-spec-update_10-1" class="reference"><a href="#cite_note-intel-spec-update-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> The bug was fixed in F-0 steppings of the vPro-enabled Core M-5Y70 Broadwell CPU in November 2014.<sup id="cite_ref-intel-330836-003_24-0" class="reference"><a href="#cite_note-intel-330836-003-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p><p>The bug was found and then reported during a diploma thesis in the School of Electrical and Computer Engineering of the <a href="/wiki/National_Technical_University_of_Athens" title="National Technical University of Athens">National Technical University of Athens</a>.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>In October 2018, Intel disclosed a TSX/TSX-NI memory ordering issue found in some <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> processors.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> As a result of a microcode update, HLE support was disabled in the affected CPUs, and RTM was mitigated by sacrificing one performance counter when used outside of Intel <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> mode or System Management Mode (<a href="/wiki/System_Management_Mode" title="System Management Mode">SMM</a>). System software would have to either effectively disable RTM or update performance monitoring tools not to use the affected performance counter. </p><p>In June 2021, Intel published a microcode update that further disables TSX/TSX-NI on various Xeon and Core processor models from <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> through <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a> and <a href="/wiki/Whiskey_Lake_(microprocessor)" class="mw-redirect" title="Whiskey Lake (microprocessor)">Whiskey Lake</a> as a mitigation for TSX Asynchronous Abort (TAA) vulnerability. Earlier mitigation for memory ordering issue was removed.<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> By default, with the updated microcode, the processor would still indicate support for RTM but would always abort the transaction. System software is able to detect this mode of operation and mask support for TSX/TSX-NI from the <a href="/wiki/CPUID#EAX=7,_ECX=0:_Extended_Features" title="CPUID"><code>CPUID</code></a> instruction, preventing detection of TSX/TSX-NI by applications. System software may also enable the "Unsupported Software Development Mode", where RTM is fully active, but in this case RTM usage may be subject to the issues described earlier, and therefore this mode should not be enabled on production systems. On some systems RTM can't be re-enabled when SGX is active. HLE is always disabled. </p><p>According to Intel 64 and IA-32 Architectures Software Developer's Manual from May 2020, Volume 1, Chapter 2.5 Intel Instruction Set Architecture And Features Removed,<sup id="cite_ref-intel-arch-sdm_18-1" class="reference"><a href="#cite_note-intel-arch-sdm-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> HLE has been removed from Intel products released in 2019 and later. RTM is not documented as removed. However, Intel 10th generation <a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a> and <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a> client processors, which were released in 2020, do not support TSX/TSX-NI,<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> including both HLE and RTM. Engineering versions of Comet Lake processors were still retaining TSX/TSX-NI support. </p><p>In Intel Architecture Instruction Set Extensions Programming Reference revision 41 from October 2020,<sup id="cite_ref-intel-arch-extensions_33-0" class="reference"><a href="#cite_note-intel-arch-extensions-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> a new TSXLDTRK instruction set extension was documented. It was first included in <a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a> processors released in January 2023. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=8" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">Advanced Synchronization Facility</a> – AMD's competing technology</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=9" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFRichard_M._YooChristopher_J._HughesKonrad_LaiRavi_Rajwar2013" class="citation web cs1">Richard M. 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Intel. 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-11-14</span></span>. <q>The processor tracks both the read-set addresses and the write-set addresses in the first level data cache (L1 cache) of the processor.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+TSX+implementation+properties&rft.pub=Intel&rft.date=2013&rft_id=http%3A%2F%2Fsoftware.intel.com%2Fen-us%2Fforums%2Ftopic%2F402412&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDe_Gelas2012" class="citation web cs1">De Gelas, Johan (September 20, 2012). <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/6290/making-sense-of-intel-haswell-transactional-synchronization-extensions/4">"Making Sense of the Intel Haswell Transactional Synchronization eXtensions"</a>. AnandTech<span class="reference-accessdate">. Retrieved <span class="nowrap">23 December</span> 2013</span>. <q>The whole "CPU does the fine grained locks" is based upon tagging the L1 (64 B) cachelines and there are 512 of them to be specific (64 x 512 = 32 KB). There is only one "lock tag" per cacheline.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Making+Sense+of+the+Intel+Haswell+Transactional+Synchronization+eXtensions&rft.pub=AnandTech&rft.date=2012-09-20&rft.aulast=De+Gelas&rft.aufirst=Johan&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fshow%2F6290%2Fmaking-sense-of-intel-haswell-transactional-synchronization-extensions%2F4&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDavid_Kanter2012" class="citation web cs1">David Kanter (2012-08-21). <a rel="nofollow" class="external text" href="http://www.realworldtech.com/haswell-tm-alt/">"Haswell Transactional Memory Alternatives"</a>. Real World Technologies<span class="reference-accessdate">. Retrieved <span class="nowrap">2013-11-14</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Haswell+Transactional+Memory+Alternatives&rft.pub=Real+World+Technologies&rft.date=2012-08-21&rft.au=David+Kanter&rft_id=http%3A%2F%2Fwww.realworldtech.com%2Fhaswell-tm-alt%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIan_Cutress2014" class="citation web cs1">Ian Cutress (2014-08-12). <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/8376/intel-disables-tsx-instructions-erratum-found-in-haswell-haswelleep-broadwelly">"Intel Disables TSX Instructions: Erratum Found in Haswell, Haswell-E/EP, Broadwell-Y"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a><span class="reference-accessdate">. Retrieved <span class="nowrap">2014-08-30</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Disables+TSX+Instructions%3A+Erratum+Found+in+Haswell%2C+Haswell-E%2FEP%2C+Broadwell-Y&rft.pub=AnandTech&rft.date=2014-08-12&rft.au=Ian+Cutress&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fshow%2F8376%2Fintel-disables-tsx-instructions-erratum-found-in-haswell-haswelleep-broadwelly&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-intel-330836-003-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-intel-330836-003_24-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf">"Intel Core M Processor Family. Specification Update. December 2014. Revision 003. 330836-003"</a> <span class="cs1-format">(PDF)</span>. <a href="/wiki/Intel" title="Intel">Intel</a>. December 2014. p. 10<span class="reference-accessdate">. Retrieved <span class="nowrap">2014-12-28</span></span>. <q>BDM53 <sup>1</sup> E-0: X, F-0:, Status: Fixed ERRATA: Intel TSX Instructions Not Available. 1. Applies to Intel Core M-5Y70 processor. Intel TSX is supported on Intel Core M-5Y70 processor with Intel vPro Technology. Intel TSX is not supported on other processor SKUs.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core+M+Processor+Family.+Specification+Update.+December+2014.+Revision+003.+330836-003&rft.pages=10&rft.pub=Intel&rft.date=2014-12&rft_id=http%3A%2F%2Fwww.intel.com%2Fcontent%2Fdam%2Fwww%2Fpublic%2Fus%2Fen%2Fdocuments%2Fspecification-updates%2Fcore-m-processor-family-spec-update.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170305013511/https://www.hipeac.net/assets/public/publications/newsletter/hipeacinfo45.pdf">"HiPEAC info"</a> <span class="cs1-format">(PDF)</span>. p. 12. Archived from <a rel="nofollow" class="external text" href="https://www.hipeac.net/assets/public/publications/newsletter/hipeacinfo45.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2017-03-05.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=HiPEAC+info&rft.pages=12&rft_id=https%3A%2F%2Fwww.hipeac.net%2Fassets%2Fpublic%2Fpublications%2Fnewsletter%2Fhipeacinfo45.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/support/us/en/documents/processors/Performance-Monitoring-Impact-of-TSX-Memory-Ordering-Issue-604224.pdf">"Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue White Paper, June 2021, Revision 1.4"</a> <span class="cs1-format">(PDF)</span>. Intel. 2021-06-12. p. 5. <q>The October 2018 microcode update also disabled the HLE instruction prefix of Intel TSX and force all RTM transactions to abort when operating in Intel SGX mode or System Management Mode (SMM).</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Performance+Monitoring+Impact+of+Intel%C2%AE+Transactional+Synchronization+Extension+Memory+Ordering+Issue+White+Paper%2C+June+2021%2C+Revision+1.4&rft.pages=5&rft.pub=Intel&rft.date=2021-06-12&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fdam%2Fsupport%2Fus%2Fen%2Fdocuments%2Fprocessors%2FPerformance-Monitoring-Impact-of-TSX-Memory-Ordering-Issue-604224.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html">"Intel® Transactional Synchronization Extensions (Intel® TSX) Memory and Performance Monitoring Update for Intel® Processors"</a>. Intel. 2021-06-12.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Transactional+Synchronization+Extensions+%28Intel%C2%AE+TSX%29+Memory+and+Performance+Monitoring+Update+for+Intel%C2%AE+Processors&rft.pub=Intel&rft.date=2021-06-12&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fsupport%2Farticles%2F000059422%2Fprocessors.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199332/intel-core-i9-10900k-processor-20m-cache-up-to-5-30-ghz.html">"Intel® Core™ i9-10900K Processor specifications"</a>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A2+i9-10900K+Processor+specifications&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2F199332%2Fintel-core-i9-10900k-processor-20m-cache-up-to-5-30-ghz.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201838/intel-core-i9-10980hk-processor-16m-cache-up-to-5-30-ghz.html">"Intel® Core™ i9-10980HK Processor specifications"</a>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A2+i9-10980HK+Processor+specifications&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2F201838%2Fintel-core-i9-10980hk-processor-16m-cache-up-to-5-30-ghz.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201888/intel-core-i7-10810u-processor-12m-cache-up-to-4-90-ghz.html">"Intel® Core™ i7-10810U Processor specifications"</a>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A2+i7-10810U+Processor+specifications&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2F201888%2Fintel-core-i7-10810u-processor-12m-cache-up-to-4-90-ghz.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199336/intel-xeon-w-1290p-processor-20m-cache-3-70-ghz.html">"Intel® Xeon® W-1290P Processor specifications"</a>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Xeon%C2%AE+W-1290P+Processor+specifications&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2F199336%2Fintel-xeon-w-1290p-processor-20m-cache-3-70-ghz.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196593/intel-core-i7-1068ng7-processor-8m-cache-up-to-4-10-ghz.html">"Intel® Core™ i7-1068NG7 Processor specifications"</a>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A2+i7-1068NG7+Processor+specifications&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2F196593%2Fintel-core-i7-1068ng7-processor-8m-cache-up-to-4-10-ghz.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> <li id="cite_note-intel-arch-extensions-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-intel-arch-extensions_33-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://software.intel.com/content/dam/develop/external/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf">"Intel® Architecture Instruction Set Extensions Programming Reference"</a> <span class="cs1-format">(PDF)</span>. Intel. 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-10-21</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Architecture+Instruction+Set+Extensions+Programming+Reference&rft.pub=Intel&rft.date=2020&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fcontent%2Fdam%2Fdevelop%2Fexternal%2Fus%2Fen%2Fdocuments%2Farchitecture-instruction-set-extensions-programming-reference.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=10" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAfekLevyMorrison2014" class="citation book cs1">Afek, Y.; Levy, A.; Morrison, A. (2014). <i>Proceedings of the 2014 ACM symposium on Principles of distributed computing - PODC '14</i>. Software-improved hardware lock elision, p. 212. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F2611462.2611482">10.1145/2611462.2611482</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9781450329446" title="Special:BookSources/9781450329446"><bdi>9781450329446</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:16645370">16645370</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Proceedings+of+the+2014+ACM+symposium+on+Principles+of+distributed+computing+-+PODC+%2714&rft.pages=Software-improved+hardware+lock+elision%2C+p.+212&rft.date=2014&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A16645370%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1145%2F2611462.2611482&rft.isbn=9781450329446&rft.aulast=Afek&rft.aufirst=Y.&rft.au=Levy%2C+A.&rft.au=Morrison%2C+A.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ATransactional+Synchronization+Extensions" class="Z3988"></span>. Software-based improvements to hardware lock-elision in Intel TSX.</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Transactional_Synchronization_Extensions&action=edit&section=11" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://software.intel.com/sites/default/files/blog/393551/sf12-arcs004-100.pdf">Presentation from IDF 2012</a> (PDF)</li> <li><a rel="nofollow" class="external text" href="http://halobates.de/adding-lock-elision-to-linux.pdf">Adding lock elision to Linux</a>, Linux Plumbers Conference 2012 (PDF)</li> <li><a rel="nofollow" class="external text" href="https://lwn.net/Articles/534758/">Lock elision in the GNU C library</a>, <a href="/wiki/LWN.net" title="LWN.net">LWN.net</a>, January 30, 2013, by Andi Kleen</li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf">TSX Optimization Guide</a>, Chapter 12 (PDF)</li> <li><a rel="nofollow" class="external text" href="https://software.intel.com/content/dam/develop/public/us/en/documents/325462-sdm-vol-1-2abcd-3abcd.pdf">Software Developers Manual</a>, Volume 1, Chapter 2.5 (PDF)</li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/software/tsx">Web Resources about Intel Transactional Synchronization Extensions</a></li> <li><a rel="nofollow" class="external text" href="https://lkml.org/lkml/2014/9/18/218">x86, microcode: BUG: microcode update that changes x86_capability</a>, <a href="/wiki/LKML" class="mw-redirect" title="LKML">LKML</a>, September 2014 (there is also another <a rel="nofollow" class="external text" href="https://bugs.gentoo.org/show_bug.cgi?id=528712">similar bug report</a>)</li> <li><a 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<li><a href="/wiki/Omni-Path" title="Omni-Path">Omni-Path</a></li> <li><a href="/wiki/Platform_Environment_Control_Interface" title="Platform Environment Control Interface">Platform Environment Control Interface</a></li> <li><a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">QuickPath Interconnect</a></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">Platform Controller Hub</a></li> <li><a href="/wiki/System_Management_Bus" title="System Management Bus">System Management Bus</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li> <li><a href="/wiki/Intel_Ultra_Path_Interconnect" title="Intel Ultra Path Interconnect">Ultra Path Interconnect</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Upcoming</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a 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navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <ul><li><a href="/wiki/DEC_Alpha#Motion_Video_Instructions_(MVI)" title="DEC Alpha">MVI</a></li></ul></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> <ul><li><a href="/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)" title="ARM architecture family">NEON</a></li> <li><a href="/wiki/AArch64#Scalable_Vector_Extension_(SVE)" title="AArch64">SVE</a></li></ul></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <ul><li><a href="/wiki/MDMX" title="MDMX">MDMX</a></li> <li><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></li> <li><a href="/wiki/Media_Extension_Unit" class="mw-redirect" title="Media Extension Unit">MXU</a></li> <li><a href="/wiki/MIPS_architecture#MIPS_SIMD_architecture" title="MIPS architecture">MIPS SIMD</a></li></ul></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> <ul><li><a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">MAX</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/AltiVec" title="AltiVec">VMX</a></li></ul></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a> <ul><li><a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">VIS</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/X86" title="X86">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (1996)</li> <li><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> (1998)</li> <li><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> (1999)</li> <li><a href="/wiki/SSE2" title="SSE2">SSE2</a> (2001)</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a> (2004)</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (2006)</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a> (2006)</li> <li><a href="/wiki/SSE5" title="SSE5">SSE5</a> <s>(2007)</s></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> (2008)</li> <li><a href="/wiki/F16C" title="F16C">F16C</a> (2009)</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a> (2009)</li> <li><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> (FMA4: 2011, FMA3: 2012)</li> <li><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> (2013)</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (2015)</li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> (2022)</li> <li><a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bit_manipulation" title="Bit manipulation">Bit manipulation</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a> (2014)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS16e ASE</a></li> <li><a href="/wiki/RISC-V#Compressed_subset" title="RISC-V">RVC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li> <li><a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li> <li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> (2012)</li> <li><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA</a> (2013)</li> <li><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> (2015)</li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> (2015)</li> <li><a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> (2021)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">TSX</a> (2013)</li> <li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/X86_virtualization#Intel_virtualization_(VT-x)" title="X86 virtualization">VT-x</a> (2005)</li> <li><a href="/wiki/X86_virtualization#AMD_virtualization_(AMD-V)" title="X86 virtualization">AMD-V</a> (2006)</li> <li><a href="/wiki/X86_virtualization#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" title="X86 virtualization">VT-d</a> (AMD-Vi)</li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck through</s>.</div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" 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