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vector-toc-level-2"> <a class="vector-toc-link" href="#From_16-bit_and_32-bit_to_64-bit_architecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>From 16-bit and 32-bit to 64-bit architecture</span> </div> </a> <ul id="toc-From_16-bit_and_32-bit_to_64-bit_architecture-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Basic_properties_of_the_architecture" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Basic_properties_of_the_architecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Basic properties of the architecture</span> </div> </a> <button aria-controls="toc-Basic_properties_of_the_architecture-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Basic properties of the architecture subsection</span> </button> <ul id="toc-Basic_properties_of_the_architecture-sublist" class="vector-toc-list"> <li id="toc-Floating_point_and_SIMD" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Floating_point_and_SIMD"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Floating point and SIMD</span> </div> </a> <ul id="toc-Floating_point_and_SIMD-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Current_implementations" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Current_implementations"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Current implementations</span> </div> </a> <ul id="toc-Current_implementations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Addressing_modes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Addressing_modes"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Addressing modes</span> </div> </a> <ul id="toc-Addressing_modes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-x86_registers" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#x86_registers"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>x86 registers</span> </div> </a> <button aria-controls="toc-x86_registers-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle x86 registers subsection</span> </button> <ul id="toc-x86_registers-sublist" class="vector-toc-list"> <li id="toc-16-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#16-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>16-bit</span> </div> </a> <ul id="toc-16-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-32-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#32-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>32-bit</span> </div> </a> <ul id="toc-32-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-64-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#64-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.3</span> <span>64-bit</span> </div> </a> <ul id="toc-64-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-128-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#128-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.4</span> <span>128-bit</span> </div> </a> <ul id="toc-128-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-256-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#256-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.5</span> <span>256-bit</span> </div> </a> <ul id="toc-256-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-512-bit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#512-bit"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.6</span> <span>512-bit</span> </div> </a> <ul id="toc-512-bit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Miscellaneous/special_purpose" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Miscellaneous/special_purpose"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.7</span> <span>Miscellaneous/special purpose</span> </div> </a> <ul id="toc-Miscellaneous/special_purpose-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Purpose" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Purpose"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.8</span> <span>Purpose</span> </div> </a> <ul id="toc-Purpose-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Structure" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Structure"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.9</span> <span>Structure</span> </div> </a> <ul id="toc-Structure-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Operating_modes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Operating_modes"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Operating modes</span> </div> </a> <button aria-controls="toc-Operating_modes-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Operating modes subsection</span> </button> <ul id="toc-Operating_modes-sublist" class="vector-toc-list"> <li id="toc-Real_mode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Real_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Real mode</span> </div> </a> <ul id="toc-Real_mode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Unreal_mode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Unreal_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2</span> <span>Unreal mode</span> </div> </a> <ul id="toc-Unreal_mode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-System_Management_Mode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#System_Management_Mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3</span> <span>System Management Mode</span> </div> </a> <ul id="toc-System_Management_Mode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Protected_mode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Protected_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4</span> <span>Protected mode</span> </div> </a> <ul id="toc-Protected_mode-sublist" class="vector-toc-list"> <li id="toc-Virtual_8086_mode" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Virtual_8086_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4.1</span> <span>Virtual 8086 mode</span> </div> </a> <ul id="toc-Virtual_8086_mode-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Long_mode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Long_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.5</span> <span>Long mode</span> </div> </a> <ul id="toc-Long_mode-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Extensions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Extensions"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Extensions</span> </div> </a> <button aria-controls="toc-Extensions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Extensions subsection</span> </button> <ul id="toc-Extensions-sublist" class="vector-toc-list"> <li id="toc-Floating-point_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Floating-point_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1</span> <span>Floating-point unit</span> </div> </a> <ul id="toc-Floating-point_unit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MMX" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MMX"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.2</span> <span>MMX</span> </div> </a> <ul id="toc-MMX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-3DNow!" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#3DNow!"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.3</span> <span>3DNow!</span> </div> </a> <ul id="toc-3DNow!-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SSE_and_AVX" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SSE_and_AVX"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.4</span> <span><span><span>SSE</span></span> and AVX</span> </div> </a> <ul id="toc-SSE_and_AVX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Physical_Address_Extension_(PAE)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Physical_Address_Extension_(PAE)"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.5</span> <span>Physical Address Extension (PAE)</span> </div> </a> <ul id="toc-Physical_Address_Extension_(PAE)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-x86-64" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#x86-64"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.6</span> <span>x86-64</span> </div> </a> <ul id="toc-x86-64-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Virtualization" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Virtualization"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.7</span> <span>Virtualization</span> </div> </a> <ul id="toc-Virtualization-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-AES" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#AES"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.8</span> <span>AES</span> </div> </a> <ul id="toc-AES-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-APX_(Advanced_Performance_Extensions)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#APX_(Advanced_Performance_Extensions)"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.9</span> <span>APX (Advanced Performance Extensions)</span> </div> </a> <ul id="toc-APX_(Advanced_Performance_Extensions)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading">x86</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 51 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-51" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">51 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%A5%D9%83%D8%B3_86" title="إكس 86 – Arabic" lang="ar" hreflang="ar" data-title="إكس 86" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/X86" title="X86 – Azerbaijani" lang="az" hreflang="az" data-title="X86" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target"><span>Azərbaycanca</span></a></li><li class="interlanguage-link interwiki-be mw-list-item"><a href="https://be.wikipedia.org/wiki/X86" title="X86 – Belarusian" lang="be" hreflang="be" data-title="X86" data-language-autonym="Беларуская" data-language-local-name="Belarusian" class="interlanguage-link-target"><span>Беларуская</span></a></li><li class="interlanguage-link interwiki-be-x-old mw-list-item"><a href="https://be-tarask.wikipedia.org/wiki/X86" title="X86 – Belarusian (Taraškievica orthography)" lang="be-tarask" hreflang="be-tarask" data-title="X86" data-language-autonym="Беларуская (тарашкевіца)" data-language-local-name="Belarusian (Taraškievica orthography)" class="interlanguage-link-target"><span>Беларуская (тарашкевіца)</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/X86" title="X86 – Bulgarian" lang="bg" hreflang="bg" data-title="X86" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/X86" title="X86 – Bosnian" lang="bs" hreflang="bs" data-title="X86" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target"><span>Bosanski</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/X86" title="X86 – Catalan" lang="ca" hreflang="ca" data-title="X86" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/X86" title="X86 – Czech" lang="cs" hreflang="cs" data-title="X86" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/X86" title="X86 – Danish" lang="da" hreflang="da" data-title="X86" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/X86-Architektur" title="X86-Architektur – German" lang="de" hreflang="de" data-title="X86-Architektur" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/X86" title="X86 – Estonian" lang="et" hreflang="et" data-title="X86" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/X86" title="X86 – Greek" lang="el" hreflang="el" data-title="X86" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/X86" title="X86 – Spanish" lang="es" hreflang="es" data-title="X86" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/X86-arkitekturo" title="X86-arkitekturo – Esperanto" lang="eo" hreflang="eo" data-title="X86-arkitekturo" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%A7%DA%A9%D8%B3%DB%B8%DB%B6" title="اکس۸۶ – Persian" lang="fa" hreflang="fa" data-title="اکس۸۶" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/X86" title="X86 – French" lang="fr" hreflang="fr" data-title="X86" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ga mw-list-item"><a href="https://ga.wikipedia.org/wiki/Ailtireacht_x86" title="Ailtireacht x86 – Irish" lang="ga" hreflang="ga" data-title="Ailtireacht x86" data-language-autonym="Gaeilge" data-language-local-name="Irish" class="interlanguage-link-target"><span>Gaeilge</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/X86" title="X86 – Korean" lang="ko" hreflang="ko" data-title="X86" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hy mw-list-item"><a href="https://hy.wikipedia.org/wiki/X86" title="X86 – Armenian" lang="hy" hreflang="hy" data-title="X86" data-language-autonym="Հայերեն" data-language-local-name="Armenian" class="interlanguage-link-target"><span>Հայերեն</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/X86" title="X86 – Croatian" lang="hr" hreflang="hr" data-title="X86" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/X86" title="X86 – Indonesian" lang="id" hreflang="id" data-title="X86" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-is mw-list-item"><a href="https://is.wikipedia.org/wiki/X86-h%C3%B6nnun" title="X86-hönnun – Icelandic" lang="is" hreflang="is" data-title="X86-hönnun" data-language-autonym="Íslenska" data-language-local-name="Icelandic" class="interlanguage-link-target"><span>Íslenska</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Architettura_x86" title="Architettura x86 – Italian" lang="it" hreflang="it" data-title="Architettura x86" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/X86" title="X86 – Hebrew" lang="he" hreflang="he" data-title="X86" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-jv mw-list-item"><a href="https://jv.wikipedia.org/wiki/X86" title="X86 – Javanese" lang="jv" hreflang="jv" data-title="X86" data-language-autonym="Jawa" data-language-local-name="Javanese" class="interlanguage-link-target"><span>Jawa</span></a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/X86" title="X86 – Latvian" lang="lv" hreflang="lv" data-title="X86" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target"><span>Latviešu</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/X86" title="X86 – Lithuanian" lang="lt" hreflang="lt" data-title="X86" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/X86" title="X86 – Hungarian" lang="hu" hreflang="hu" data-title="X86" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/X86" title="X86 – Malayalam" lang="ml" hreflang="ml" data-title="X86" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/X86-instructieset" title="X86-instructieset – Dutch" lang="nl" hreflang="nl" data-title="X86-instructieset" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/X86" title="X86 – Japanese" lang="ja" hreflang="ja" data-title="X86" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/X86-arkitektur" title="X86-arkitektur – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="X86-arkitektur" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/X86" title="X86 – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="X86" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/X86" title="X86 – Polish" lang="pl" hreflang="pl" data-title="X86" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/X86" title="X86 – Portuguese" lang="pt" hreflang="pt" data-title="X86" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/X86" title="X86 – Romanian" lang="ro" hreflang="ro" data-title="X86" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/X86" title="X86 – Russian" lang="ru" hreflang="ru" data-title="X86" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sco mw-list-item"><a href="https://sco.wikipedia.org/wiki/X86" title="X86 – Scots" lang="sco" hreflang="sco" data-title="X86" data-language-autonym="Scots" data-language-local-name="Scots" class="interlanguage-link-target"><span>Scots</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/X86" title="X86 – Simple English" lang="en-simple" hreflang="en-simple" data-title="X86" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/X86" title="X86 – Slovak" lang="sk" hreflang="sk" data-title="X86" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-ckb mw-list-item"><a href="https://ckb.wikipedia.org/wiki/%D8%A6%DB%8E%DA%A9%D8%B3%D9%A8%D9%A6" title="ئێکس٨٦ – Central Kurdish" lang="ckb" hreflang="ckb" data-title="ئێکس٨٦" data-language-autonym="کوردی" data-language-local-name="Central Kurdish" class="interlanguage-link-target"><span>کوردی</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/X86" title="X86 – Serbian" lang="sr" hreflang="sr" data-title="X86" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/X86" title="X86 – Finnish" lang="fi" hreflang="fi" data-title="X86" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/X86" title="X86 – Swedish" lang="sv" hreflang="sv" data-title="X86" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B9%80%E0%B8%AD%E0%B8%81%E0%B8%8B%E0%B9%8C86" title="เอกซ์86 – Thai" lang="th" hreflang="th" data-title="เอกซ์86" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/X86" title="X86 – Turkish" lang="tr" hreflang="tr" data-title="X86" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/X86" title="X86 – Ukrainian" lang="uk" hreflang="uk" data-title="X86" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/X86" title="X86 – Vietnamese" lang="vi" hreflang="vi" data-title="X86" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/X86" title="X86 – Wu" lang="wuu" hreflang="wuu" data-title="X86" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/X86" 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i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">This article is about the Intel microprocessor architecture in general. For the 32-bit generation of this architecture that is also referred to as "x86", see <a href="/wiki/IA-32" title="IA-32">IA-32</a>.</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">x86</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a>, <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a></td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data"><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>, <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> and <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">1978 (16-bit), 1985 (32-bit), 2003 (64-bit)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register–memory</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Variable (1 to 15 bytes)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data"><a href="/wiki/Status_register" title="Status register">Condition code</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Little</td></tr><tr><th scope="row" class="infobox-label">Page size</th><td class="infobox-data"><a href="/wiki/8086" class="mw-redirect" title="8086">8086</a>–<a href="/wiki/I286" class="mw-redirect" title="I286">i286</a>: None<br /><a href="/wiki/Intel_386" class="mw-redirect" title="Intel 386">i386</a>, <a href="/wiki/Intel_486" class="mw-redirect" title="Intel 486">i486</a>: 4 KB pages<br /><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a> <a href="/wiki/Pentium" title="Pentium">Pentium</a>: added 4 MB pages<br />(Legacy <a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>: 4 KB→2 MB)<br /><a href="/wiki/Long_mode" title="Long mode">x86-64</a>: added 1 GB pages</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><a href="/wiki/X87" title="X87">x87</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a>, <a href="/wiki/X86S" class="mw-redirect" title="X86S">X86S</a>, <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/Machine_Check_Architecture" title="Machine Check Architecture">MCA</a>, <a href="/wiki/Advanced_Configuration_and_Power_Interface" class="mw-redirect" title="Advanced Configuration and Power Interface">ACPI</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/AES-NI" class="mw-redirect" title="AES-NI">AES-NI</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/SM3_(hash_function)" title="SM3 (hash function)">SM3</a>, <a href="/wiki/SM4_(cipher)" title="SM4 (cipher)">SM4</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA</a>, <a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a>, <a href="/wiki/Secure_Memory_Encryption" class="mw-redirect" title="Secure Memory Encryption">SME</a>, <a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a>, <a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a>, <a href="/wiki/AVX-VNNI" class="mw-redirect" title="AVX-VNNI">AVX-VNNI</a>, <a href="/wiki/AVX512" class="mw-redirect" title="AVX512">AVX512</a>, <a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a>, <a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a>, <a href="/wiki/VT-x" class="mw-redirect" title="VT-x">VT-x</a>, <a href="/wiki/VT-d" class="mw-redirect" title="VT-d">VT-d</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AMD-Vi" class="mw-redirect" title="AMD-Vi">AMD-Vi</a>, <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a>, <a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">TXT</a>, <a href="/wiki/Advanced_Performance_Extensions" class="mw-redirect" title="Advanced Performance Extensions">APX</a></td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Partly. For some advanced features, x86 may require license from Intel; x86-64 may require an additional license from AMD. The <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> processor (and <a href="/wiki/NetBurst" title="NetBurst">NetBurst</a>) has been on the market for more than 21 years<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> and so cannot be subject to patent claims. The <a href="/wiki/I686" class="mw-redirect" title="I686">i686</a> subset of the x86 architecture is therefore fully open. The <a href="/wiki/Opteron" title="Opteron">Opteron</a> 1000 series processors have been on the market for more than 21 years<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> and so cannot be subject to patent claims. The <a href="/wiki/AMD_K8" title="AMD K8">AMD K8</a> subset of the x86 architecture is therefore fully open.</td></tr><tr><th colspan="2" class="infobox-header"><a href="/wiki/Processor_register" title="Processor register">Registers</a></th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/General-purpose_register" class="mw-redirect" title="General-purpose register">General-purpose</a></th><td class="infobox-data"><div><ul><li>16-bit: 6 semi-dedicated registers, BP and SP are not general-purpose</li><li>32-bit: 8 GPRs, including EBP and ESP</li><li>64-bit: 16 GPRs, including RBP and RSP</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Floating_point" class="mw-redirect" title="Floating point">Floating point</a></th><td class="infobox-data"><div><ul><li>16-bit: optional separate <a href="/wiki/X87" title="X87">x87</a> FPU</li><li>32-bit: optional separate or integrated <a href="/wiki/X87" title="X87">x87</a> FPU, integrated <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> units in later processors</li><li>64-bit: integrated <a href="/wiki/X87" title="X87">x87</a> and <a href="/wiki/SSE2" title="SSE2">SSE2</a> units, later implementations extended to <a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> and <a href="/wiki/AVX512" class="mw-redirect" title="AVX512">AVX512</a></li></ul></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Intel_D8086.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e1/KL_Intel_D8086.jpg/220px-KL_Intel_D8086.jpg" decoding="async" width="220" height="113" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e1/KL_Intel_D8086.jpg/330px-KL_Intel_D8086.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e1/KL_Intel_D8086.jpg/440px-KL_Intel_D8086.jpg 2x" data-file-width="1512" data-file-height="774" /></a><figcaption>The x86 architectures were based on the Intel 8086 microprocessor chip, initially released in 1978.</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Core_2_Duo_E6300.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/Core_2_Duo_E6300.jpg/220px-Core_2_Duo_E6300.jpg" decoding="async" width="220" height="219" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/23/Core_2_Duo_E6300.jpg/330px-Core_2_Duo_E6300.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/23/Core_2_Duo_E6300.jpg/440px-Core_2_Duo_E6300.jpg 2x" data-file-width="1710" data-file-height="1700" /></a><figcaption>Intel Core 2 Duo, an example of an x86-compatible, 64-bit multicore processor</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Slot-A_Athlon.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e7/Slot-A_Athlon.jpg/220px-Slot-A_Athlon.jpg" decoding="async" width="220" height="101" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e7/Slot-A_Athlon.jpg/330px-Slot-A_Athlon.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e7/Slot-A_Athlon.jpg/440px-Slot-A_Athlon.jpg 2x" data-file-width="1286" data-file-height="592" /></a><figcaption>AMD Athlon (early version), a technically different but fully compatible x86 implementation</figcaption></figure> <p><b>x86</b> (also known as <b>80x86</b><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> or the <b>8086 family</b><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup>) is a family of <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">complex instruction set computer</a> (CISC) <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architectures</a><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> initially developed by <a href="/wiki/Intel" title="Intel">Intel</a> based on the <a href="/wiki/Intel_8086" title="Intel 8086">8086</a> microprocessor and its 8-bit-external-bus variant, the <a href="/wiki/Intel_8088" title="Intel 8088">8088</a>. The 8086 was introduced in 1978 as a fully <a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a> extension of <a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a> Intel's <a href="/wiki/Intel_8080" title="Intel 8080">8080</a> microprocessor, with <a href="/wiki/X86_memory_segmentation" title="X86 memory segmentation">memory segmentation</a> as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including the <a href="/wiki/Intel_80186" title="Intel 80186">80186</a>, <a href="/wiki/Intel_80286" title="Intel 80286">80286</a>, <a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">80386</a> and <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">80486</a>. Colloquially, their names were "186", "286", "386" and "486". </p><p>The term is not synonymous with <a href="/wiki/IBM_PC_compatible" class="mw-redirect" title="IBM PC compatible">IBM PC compatibility</a>, as this implies a multitude of other <a href="/wiki/Computer_hardware" title="Computer hardware">computer hardware</a>. <a href="/wiki/Embedded_system" title="Embedded system">Embedded systems</a> and general-purpose computers used x86 chips <a href="/wiki/Influence_of_the_IBM_PC_on_the_personal_computer_market#Before_the_IBM_PC's_introduction" title="Influence of the IBM PC on the personal computer market">before the PC-compatible market started</a>,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> some of them before the <a href="/wiki/IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a> (1981) debut. </p><p>As of June 2022<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=X86&action=edit">[update]</a></sup>, most <a href="/wiki/Desktop_computer" title="Desktop computer">desktop</a> and <a href="/wiki/Laptop" title="Laptop">laptop</a> computers sold are based on the x86 architecture family,<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> while mobile categories such as <a href="/wiki/Smartphone" title="Smartphone">smartphones</a> or <a href="/wiki/Tablet_computer" title="Tablet computer">tablets</a> are dominated by <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a>. At the high end, x86 continues to dominate computation-intensive <a href="/wiki/Workstation" title="Workstation">workstation</a> and <a href="/wiki/Cloud_computing" title="Cloud computing">cloud computing</a> segments.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In the 1980s and early 1990s, when the <a href="/wiki/8088" class="mw-redirect" title="8088">8088</a> and <a href="/wiki/80286" class="mw-redirect" title="80286">80286</a> were still in common use, the term x86 usually represented any 8086-compatible CPU. Today, however, x86 usually implies binary compatibility with the <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> of the <a href="/wiki/I386" title="I386">80386</a>. This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and also probably because the term became common after the introduction of the 80386 in 1985. </p><p>A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as the "iAPX" of the ambitious but ill-fated <a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">Intel iAPX 432</a> processor was tried on the more successful 8086 family of chips,<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> applied as a kind of system-level prefix. An 8086 system, including <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a> such as <a href="/wiki/8087" class="mw-redirect" title="8087">8087</a> and <a href="/wiki/8089" class="mw-redirect" title="8089">8089</a>, and simpler Intel-specific system chips,<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> was thereby described as an iAPX 86 system.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup> There were also terms <i>iRMX</i> (for operating systems), <i>iSBC</i> (for single-board computers), and <i>iSBX</i> (for multimodule boards based on the 8086-architecture), all together under the heading <i>Microsystem 80</i>.<sup id="cite_ref-i286_13-0" class="reference"><a href="#cite_note-i286-13"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-i86_14-0" class="reference"><a href="#cite_note-i86-14"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> However, this naming scheme was quite temporary, lasting for a few years during the early 1980s.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup> </p><p>Although the 8086 was primarily developed for <a href="/wiki/Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a> and small multi-user or single-user computers, largely as a response to the successful 8080-compatible <a href="/wiki/Zilog_Z80" title="Zilog Z80">Zilog Z80</a>,<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> the x86 line soon grew in features and processing power. Today, x86 is ubiquitous in both stationary and portable personal computers, and is also used in <a href="/wiki/Midrange_computer" title="Midrange computer">midrange computers</a>, <a href="/wiki/Workstation" title="Workstation">workstations</a>, servers, and most new <a href="/wiki/Supercomputer" title="Supercomputer">supercomputer</a> <a href="/wiki/Computer_cluster" title="Computer cluster">clusters</a> of the <a href="/wiki/TOP500" title="TOP500">TOP500</a> list. A large amount of <a href="/wiki/Software" title="Software">software</a>, including a large list of <a href="/wiki/Category:X86_operating_systems" title="Category:X86 operating systems">x86 operating systems</a> are using x86-based hardware. </p><p>Modern x86 is relatively uncommon in <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>, however, and small <a href="/wiki/Low-power_electronics" title="Low-power electronics">low power</a> applications (using tiny batteries), and low-cost microprocessor markets, such as <a href="/wiki/Home_appliance" title="Home appliance">home appliances</a> and toys, lack significant x86 presence.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup> Simple 8- and 16-bit based architectures are common here, as well as simpler RISC architectures like <a href="/wiki/RISC-V" title="RISC-V">RISC-V</a>, although the x86-compatible <a href="/wiki/VIA_C7" title="VIA C7">VIA C7</a>, <a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a>, <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a>'s <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode</a>, <a href="/wiki/Athlon_Neo" class="mw-redirect" title="Athlon Neo">Athlon Neo</a> and <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a> are examples of 32- and <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> designs used in some relatively low-power and low-cost segments. </p><p>There have been several attempts, including by Intel, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the <a href="/wiki/IAPX_432" class="mw-redirect" title="IAPX 432">iAPX 432</a> (a project originally named the <i>Intel 8800</i><sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup>), the <a href="/wiki/Intel_960" class="mw-redirect" title="Intel 960">Intel 960</a>, <a href="/wiki/Intel_860" class="mw-redirect" title="Intel 860">Intel 860</a> and the Intel/Hewlett-Packard <a href="/wiki/Itanium" title="Itanium">Itanium</a> architecture. However, the continuous refinement of x86 <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitectures</a>, <a href="/wiki/Electronic_circuit" title="Electronic circuit">circuitry</a> and <a href="/wiki/Semiconductor_manufacturing" class="mw-redirect" title="Semiconductor manufacturing">semiconductor manufacturing</a> would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design)<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> and the scalability of x86 chips in the form of modern multi-core CPUs, is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Chronology">Chronology</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=2" title="Edit section: Chronology"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/X86" title="Special:EditPage/X86">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a> in this section. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">March 2020</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs. <style data-mw-deduplicate="TemplateStyles:r1232966811">.mw-parser-output .hover-highlight tr:hover,.mw-parser-output .mw-datatable tr:hover{background-color:var(--background-color-progressive-subtle,#eaf3ff);color:var(--color-base,#333)}.mw-parser-output .mw-datatable{background-color:var(--background-color-base,#fff);color:var(--color-base,#333)}</style> </p> <table class="wikitable mw-datatable" style="text-align:center"> <caption>Chronology of x86 processors </caption> <tbody><tr> <th colspan="2" rowspan="2">Era </th> <th rowspan="2">Introduction </th> <th rowspan="2">Prominent CPU models </th> <th colspan="3"><a href="/wiki/Address_space" title="Address space">Address space</a> </th> <th rowspan="2">Notable features </th></tr> <tr> <th><a href="/wiki/Linear_address_space" class="mw-redirect" title="Linear address space">Linear</a> </th> <th><a href="/wiki/Virtual_address_space" title="Virtual address space">Virtual</a> </th> <th><a href="/wiki/Physical_address" title="Physical address">Physical</a> </th></tr> <tr> <td rowspan="3" style="vertical-align: middle; font-size: smaller;">x86-16</td> <td rowspan="2" style="width:80px"><b>1st</b></td> <td>1978</td> <td><a href="/wiki/Intel_8086" title="Intel 8086">Intel 8086</a>, <a href="/wiki/Intel_8088" title="Intel 8088">Intel 8088</a> (1979)</td> <td rowspan="3" style="background: #FAECC8;">16-bit</td> <td rowspan="2" style="background: #FAECC8;">NA</td> <td rowspan="2" style="background: #FAECC8;">20-bit</td> <td><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">ISA</a>, <a href="/wiki/IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a> (8088), <a href="/wiki/IBM_PC/XT" class="mw-redirect" title="IBM PC/XT">IBM PC/XT</a> (8088) </td></tr> <tr> <td rowspan="2">1982</td> <td><a href="/wiki/Intel_80186" title="Intel 80186">Intel 80186</a>, <a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">Intel 80188</a><br /><a href="/wiki/NEC_V20" title="NEC V20">NEC V20</a>/V30 (1983)</td> <td>8086-2 ISA, embedded (80186/80188) </td></tr> <tr> <td><b>2nd</b></td> <td><a href="/wiki/Intel_80286" title="Intel 80286">Intel 80286</a> and clones</td> <td style="background: #FAECC8;">30-bit</td> <td style="background: #FAECC8;">24-bit</td> <td><a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>, <a href="/wiki/IBM_Personal_Computer_XT" title="IBM Personal Computer XT">IBM PC/XT 286</a>, <a href="/wiki/IBM_Personal_Computer/AT" class="mw-redirect" title="IBM Personal Computer/AT">IBM PC/AT</a> </td></tr> <tr> <td rowspan="13" style="vertical-align: middle; font-size: smaller;"><a href="/wiki/IA-32" title="IA-32">IA-32</a></td> <td rowspan="1" style="width:80px"><b>3rd</b></td> <td>1985</td> <td><a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">Intel 80386</a>, <a href="/wiki/AMD_Am386" class="mw-redirect" title="AMD Am386">AMD Am386</a> (1991)</td> <td rowspan="13" style="background: #CEE0F2;">32-bit</td> <td rowspan="13" style="background: #CEE0F2;">46-bit</td> <td rowspan="5" style="background: #CEE0F2;">32-bit</td> <td><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">ISA</a>, paging, <a href="/wiki/IBM_Personal_System/2" class="mw-redirect" title="IBM Personal System/2">IBM PS/2</a> </td></tr> <tr> <td><b>4th</b> (pipelining, cache)</td> <td>1989</td> <td><a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">Intel 80486</a><br /><a href="/wiki/Cyrix" title="Cyrix">Cyrix</a> <a href="/wiki/Cyrix_Cx486SLC" title="Cyrix Cx486SLC">Cx486S</a>, <a href="/wiki/Cyrix_Cx486DLC" title="Cyrix Cx486DLC">DLC</a> (1992)<br /><a href="/wiki/AMD_Am486" class="mw-redirect" title="AMD Am486">AMD Am486</a> (1993), <a href="/wiki/AMD_Am5x86" class="mw-redirect" title="AMD Am5x86">Am5x86</a> (1995)</td> <td><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelining</a>, on-die <a href="/wiki/X87" title="X87">x87</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPU</a> (486DX), on-die <a href="/wiki/CPU_cache" title="CPU cache">cache</a> </td></tr> <tr> <td rowspan="3"><b>5th</b><br />(<a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">Superscalar</a>)</td> <td>1993</td> <td>Intel <a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">Pentium</a>, <a href="/wiki/Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a> (1996)</td> <td><a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">Superscalar</a>, <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">databus</a>, faster FPU, <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (Pentium MMX), <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">APIC</a>, <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a> </td></tr> <tr> <td>1994</td> <td><a href="/wiki/NexGen" title="NexGen">NexGen</a> Nx586<br />AMD <a href="/wiki/AMD_K5" title="AMD K5">5k86</a>/<a href="/wiki/AMD_K5" title="AMD K5">K5</a> (1996)</td> <td>Discrete microarchitecture (<a href="/wiki/Micro-operation" title="Micro-operation">μ-op</a> translation) </td></tr> <tr> <td>1995</td> <td><a href="/wiki/Cyrix_Cx5x86" class="mw-redirect" title="Cyrix Cx5x86">Cyrix Cx5x86</a><br /><a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a>/MX (1997)/<a href="/wiki/Cyrix_MII" class="mw-redirect" title="Cyrix MII">MII</a> (1998)</td> <td><a href="/wiki/Dynamic_execution" class="mw-redirect" title="Dynamic execution">dynamic execution</a> </td></tr> <tr> <td rowspan="3"><b>6th</b><br />(<a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>, μ-op translation)</td> <td>1995</td> <td>Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a></td> <td rowspan="2" style="background: #CEE0F2;">36-bit (<a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>)</td> <td>μ-op translation, conditional move instructions, <a href="/wiki/Dynamic_execution" class="mw-redirect" title="Dynamic execution">dynamic execution</a>, <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>, 3-way x86 superscalar, superscalar FPU, <a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>, on-chip <a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2 cache</a> </td></tr> <tr> <td>1997</td> <td>Intel <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>, <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a> (1999)<br /><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998), <a href="/wiki/Xeon" title="Xeon">Xeon</a> (1998)</td> <td>on-package (Pentium II) or on-die (Celeron) L2 Cache, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> (Pentium III), <a href="/wiki/Slot_1" title="Slot 1">Slot 1</a>, <a href="/wiki/Socket_370" title="Socket 370">Socket 370</a> or <a href="/wiki/Slot_2" title="Slot 2">Slot 2</a> (Xeon) </td></tr> <tr> <td>1997</td> <td><a href="/wiki/AMD_K6" title="AMD K6">AMD K6</a>/<a href="/wiki/AMD_K6-2" title="AMD K6-2">K6-2</a> (1998)/<a href="/wiki/AMD_K6-III" title="AMD K6-III">K6-III</a> (1999)</td> <td style="background: #CEE0F2;">32-bit</td> <td><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a>, 3-level cache system (K6-III) </td></tr> <tr> <td rowspan="5">Enhanced Platform</td> <td>1999</td> <td>AMD <a href="/wiki/Athlon" title="Athlon">Athlon</a><br /><a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon XP</a>/<a href="/wiki/Athlon_MP" class="mw-redirect" title="Athlon MP">MP</a> (2001)<br /><a href="/wiki/Duron" title="Duron">Duron</a> (2000)<br /><a href="/wiki/Sempron" title="Sempron">Sempron</a> (2004)</td> <td style="background: #CEE0F2;">36-bit</td> <td>MMX+, 3DNow!+, double-pumped bus, <a href="/wiki/Slot_A" title="Slot A">Slot A</a> or <a href="/wiki/Socket_A" title="Socket A">Socket A</a> </td></tr> <tr> <td rowspan="2">2000</td> <td><a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Transmeta Crusoe</a></td> <td style="background: #CEE0F2;">32-bit</td> <td><a href="/wiki/Code_Morphing_Software" class="mw-redirect" title="Code Morphing Software">CMS</a> powered x86 platform processor, <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a>-128 core, on-die memory controller, on-die PCI bridge logic </td></tr> <tr> <td>Intel <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a></td> <td rowspan="3" style="background: #CEE0F2;">36-bit</td> <td><a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/Hyper-Threading" class="mw-redirect" title="Hyper-Threading">HTT</a> (Northwood), NetBurst, quad-pumped bus, Trace Cache, <a href="/wiki/Socket_478" title="Socket 478">Socket 478</a> </td></tr> <tr> <td rowspan="2">2003</td> <td>Intel <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a><br /><a href="/wiki/Intel_Core#Core" title="Intel Core">Intel Core</a> (2006)<br /><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> (2007)</td> <td><a href="/wiki/Micro-op_fusion" class="mw-redirect" title="Micro-op fusion">μ-op fusion</a>, <a href="/wiki/XD_bit" class="mw-redirect" title="XD bit">XD bit</a> (Dothan) (Intel Core "Yonah") </td></tr> <tr> <td><a href="/wiki/Transmeta_Efficeon" title="Transmeta Efficeon">Transmeta Efficeon</a></td> <td><a href="/wiki/Code_Morphing_Software" class="mw-redirect" title="Code Morphing Software">CMS</a> 6.0.4, <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a>-256, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/Hyper_Transport" class="mw-redirect" title="Hyper Transport">HT</a> </td></tr> <tr> <td style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;"><a href="/wiki/IA-64" title="IA-64">IA-64</a></td> <td style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;">64-bit Transition<br />1999–2005</td> <td>2001</td> <td>Intel <a href="/wiki/Itanium" title="Itanium">Itanium</a> (2001–2017)</td> <td colspan="3" style="background: #ececec;">52-bit</td> <td>64-bit <a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a> architecture, 128-bit VLIW instruction bundle, on-die hardware IA-32 H/W enabling x86 OSes & x86 applications (early generations), software IA-32 EL enabling x86 applications (Itanium 2), Itanium register files are remapped to x86 registers </td></tr> <tr> <td rowspan="30" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;"><a href="/wiki/X86-64" title="X86-64">x86-64</a></td> <td rowspan="30" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;">64-bit Extended<br />since 2001</td> <td colspan="6" style="background: #ececec; color: grey; vertical-align: middle; font-size: smaller;">x86-64 is the 64-bit extended architecture of x86, its Legacy Mode preserves the entire and unaltered x86 architecture. The native architecture of x86-64 processors: residing in the 64-bit Mode, lacks of access mode in segmentation, presenting 64-bit architectural-permit linear address space; an adapted IA-32 architecture residing in the Compatibility Mode alongside 64-bit Mode is provided to support most x86 applications </td></tr> <tr> <td>2003</td> <td><a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a>/<a href="/wiki/Athlon_64_FX" class="mw-redirect" title="Athlon 64 FX">FX</a>/<a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">X2</a> (2005), <a href="/wiki/Opteron" title="Opteron">Opteron</a><br /><a href="/wiki/Sempron" title="Sempron">Sempron</a> (2004)/<a href="/wiki/Turion_64_X2" class="mw-redirect" title="Turion 64 X2">X2</a> (2008)<br /><a href="/wiki/Turion_64" class="mw-redirect" title="Turion 64">Turion 64</a> (2005)/<a href="/wiki/Turion_64_X2" class="mw-redirect" title="Turion 64 X2">X2</a> (2006)</td> <td colspan="3" style="background: #ececec;">40-bit</td> <td><a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a> (except some Sempron processors presented as purely x86 processors), on-die memory controller, <a href="/wiki/HyperTransport" title="HyperTransport">HyperTransport</a>, on-die dual-core (X2), <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> (Athlon 64 Orleans), <a href="/wiki/Socket_754" title="Socket 754">Socket 754</a>/<a href="/wiki/Socket_939" title="Socket 939">939</a>/<a href="/wiki/Socket_940" title="Socket 940">940</a> or <a href="/wiki/Socket_AM2" title="Socket AM2">AM2</a> </td></tr> <tr> <td>2004</td> <td><a href="/wiki/Pentium4#Prescott" class="mw-redirect" title="Pentium4">Pentium 4</a> (Prescott)<br /><a href="/wiki/Celeron_D" class="mw-redirect" title="Celeron D">Celeron D</a>, <a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a> (2005)</td> <td rowspan="2" colspan="3" style="background: #ececec;">36-bit</td> <td><a href="/wiki/EM64T" class="mw-redirect" title="EM64T">EM64T</a> (enabled on selected models of Pentium 4 and Celeron D), <a href="/wiki/SSE3" title="SSE3">SSE3</a>, 2nd gen. NetBurst pipelining, dual-core (on-die: Pentium D 8xx, on-chip: Pentium D 9xx), <a href="/wiki/Intel_VT" class="mw-redirect" title="Intel VT">Intel VT</a> (Pentium 4 6x2), socket <a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td></tr> <tr> <td>2006</td> <td><a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a><br /><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> (2007)<br /><a href="/wiki/Celeron_Dual-Core" class="mw-redirect" title="Celeron Dual-Core">Celeron Dual-Core</a> (2008)</td> <td><a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a> (<<== EM64T), <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (65 nm), wide dynamic execution, μ-op fusion, macro-op fusion in 16-bit and 32-bit mode,<sup id="cite_ref-intel-optimization-for-macro-fusion_21-0" class="reference"><a href="#cite_note-intel-optimization-for-macro-fusion-21"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-agner-fog-microarchitecture_22-0" class="reference"><a href="#cite_note-agner-fog-microarchitecture-22"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> on-chip quad-core(Core 2 Quad), Smart Shared L2 Cache (Intel Core 2 "Merom") </td></tr> <tr> <td>2007</td> <td><a href="/wiki/AMD_Phenom" title="AMD Phenom">AMD Phenom</a>/<a href="/wiki/AMD_Phenom_II" class="mw-redirect" title="AMD Phenom II">II</a> (2008)<br /><a href="/wiki/AMD_Athlon_II" class="mw-redirect" title="AMD Athlon II">Athlon II</a> (2009)<br /><a href="/wiki/AMD_Turion#Turion_II" title="AMD Turion">Turion II</a> (2009)</td> <td colspan="3" style="background: #ececec;">48-bit</td> <td>Monolithic quad-core (X4)/triple-core (X3), <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Rapid_Virtualization_Indexing" class="mw-redirect" title="Rapid Virtualization Indexing">Rapid Virtualization Indexing</a> (RVI), HyperTransport 3, <a href="/wiki/AM2%2B" class="mw-redirect" title="AM2+">AM2+</a> or <a href="/wiki/AM3" class="mw-redirect" title="AM3">AM3</a> </td></tr> <tr> <td rowspan="4">2008</td> <td><a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a> (45 nm)</td> <td rowspan="4" colspan="3" style="background: #ececec;">40-bit</td> <td><a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a> </td></tr> <tr> <td><a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a></td> <td>netbook or low power smart device processor, P54C core reused </td></tr> <tr> <td>Intel <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a><br /><a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> (2009)<br /><a href="/wiki/Intel_Core_i3" class="mw-redirect" title="Intel Core i3">Core i3</a> (2010)</td> <td>QuickPath, on-chip GMCH (<a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a>), <a href="/wiki/SSE4" title="SSE4">SSE4.2</a>, <a href="/wiki/Second_Level_Address_Translation#Extended_Page_Tables" title="Second Level Address Translation">Extended Page Tables</a> (EPT) for virtualization, macro-op fusion in 64-bit mode,<sup id="cite_ref-intel-optimization-for-macro-fusion_21-1" class="reference"><a href="#cite_note-intel-optimization-for-macro-fusion-21"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-agner-fog-microarchitecture_22-1" class="reference"><a href="#cite_note-agner-fog-microarchitecture-22"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> (Intel Xeon "Bloomfield" with Nehalem microarchitecture) </td></tr> <tr> <td><a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a></td> <td><a href="/wiki/Hardware-based_encryption" title="Hardware-based encryption">hardware-based encryption</a>; adaptive <a href="/wiki/Power_management" title="Power management">power management</a> </td></tr> <tr> <td>2010</td> <td><a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">AMD FX</a></td> <td colspan="3" style="background: #ececec;">48-bit</td> <td>octa-core, CMT(Clustered Multi-Thread), FMA, OpenCL, AM3+ </td></tr> <tr> <td rowspan="3">2011</td> <td>AMD APU A and E Series (<a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">Llano</a>)</td> <td colspan="3" style="background: #ececec;">40-bit</td> <td>on-die GPGPU, PCI Express 2.0, <a href="/wiki/Socket_FM1" title="Socket FM1">Socket FM1</a> </td></tr> <tr> <td>AMD APU C, E and Z Series (<a href="/wiki/Bobcat_(processor)" class="mw-redirect" title="Bobcat (processor)">Bobcat</a>)</td> <td rowspan="2" colspan="3" style="background: #ececec;">36-bit</td> <td>low power smart device APU </td></tr> <tr> <td><a href="/wiki/Intel_Core_i3" class="mw-redirect" title="Intel Core i3">Intel Core i3</a>, <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> and <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a><br />(<a href="/wiki/Sandy_Bridge_(microarchitecture)" class="mw-redirect" title="Sandy Bridge (microarchitecture)">Sandy Bridge</a>/<a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a>)</td> <td>Internal Ring connection, decoded μ-op cache, <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a> socket </td></tr> <tr> <td rowspan="2">2012</td> <td>AMD APU A Series (<a href="/wiki/Bulldozer_(processor)" class="mw-redirect" title="Bulldozer (processor)">Bulldozer, Trinity</a> and later)</td> <td rowspan="3" colspan="3" style="background: #ececec;">48-bit</td> <td><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, Bulldozer based APU, <a href="/wiki/Socket_FM2" title="Socket FM2">Socket FM2</a> or <a href="/wiki/Socket_FM2%2B" title="Socket FM2+">Socket FM2+</a> </td></tr> <tr> <td>Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> (<a href="/wiki/Knights_Corner" class="mw-redirect" title="Knights Corner">Knights Corner</a>)</td> <td>PCI-E add-on card coprocessor for XEON based system, Manycore Chip, In-order <a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P54C</a>, very wide VPU (512-bit SSE), LRBni instructions (8× 64-bit) </td></tr> <tr> <td rowspan="3">2013</td> <td>AMD <a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a><br />(Athlon, Sempron)</td> <td><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>, game console and low power smart device processor </td></tr> <tr> <td>Intel <a href="/wiki/Silvermont" title="Silvermont">Silvermont</a><br />(Atom, Celeron, Pentium)</td> <td colspan="3" style="background: #ececec;">36-bit</td> <td><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>, low/ultra-low power smart device processor </td></tr> <tr> <td><a href="/wiki/Intel_Core_i3" class="mw-redirect" title="Intel Core i3">Intel Core i3</a>, <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> and <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a> (<a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>/<a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a>)</td> <td rowspan="2" colspan="3" style="background: #ececec;">39-bit</td> <td><a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1, and BMI2</a> instructions, <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a> socket </td></tr> <tr> <td>2015</td> <td>Intel <a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell-U</a><br />(<a href="/wiki/Intel_Core_i3" class="mw-redirect" title="Intel Core i3">Intel Core i3</a>, <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a>, <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a>, <a href="/wiki/List_of_Intel_Core_M_microprocessors" class="mw-redirect" title="List of Intel Core M microprocessors">Core M</a>, <a href="/wiki/Pentium" title="Pentium">Pentium</a>, <a href="/wiki/Celeron" title="Celeron">Celeron</a>)</td> <td>SoC, on-chip Broadwell-U PCH-LP (Multi-chip module) </td></tr> <tr> <td>2015–2020</td> <td>Intel <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>/<a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a>/<a href="/wiki/Cannon_Lake_(microarchitecture)" class="mw-redirect" title="Cannon Lake (microarchitecture)">Cannon Lake</a>/<a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a>/<a href="/wiki/Rocket_Lake_(microarchitecture)" class="mw-redirect" title="Rocket Lake (microarchitecture)">Rocket Lake</a><br />(Intel Pentium/Celeron Gold, <a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a>, <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a>, <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a>, <a href="/wiki/Core_i9" class="mw-redirect" title="Core i9">Core i9</a>)</td> <td colspan="3" style="background: #ececec;">46-bit</td> <td>AVX-512 (restricted to Cannon Lake-U and workstation/server variants of Skylake) </td></tr> <tr> <td>2016</td> <td>Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> (<a href="/wiki/Knights_Landing_(microarchitecture)" class="mw-redirect" title="Knights Landing (microarchitecture)">Knights Landing</a>)</td> <td colspan="3" rowspan="4" style="background: #ececec">48-bit</td> <td>Manycore CPU and coprocessor for Xeon systems, Airmont (Atom) based core </td></tr> <tr> <td>2016</td> <td>AMD <a href="/wiki/Bristol_Ridge" class="mw-redirect" title="Bristol Ridge">Bristol Ridge</a><br />(AMD (Pro) A6/A8/A10/A12)</td> <td>Integrated FCH on die, SoC, AM4 socket </td></tr> <tr> <td>2017</td> <td>AMD <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a> Series/AMD <a href="/wiki/Epyc" title="Epyc">Epyc</a> Series</td> <td>AMD's implementation of SMT, on-chip multiple dies </td></tr> <tr> <td>2017</td> <td>Zhaoxin WuDaoKou (KX-5000, KH-20000)</td> <td><a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a>'s first brand new x86-64 architecture </td></tr> <tr> <td>2018–2021</td> <td>Intel <a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> (<a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a>-U and Y), <a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a> (<a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a>)</td> <td colspan="3" style="background: #ececec;">57-bit</td> <td>Intel's first implementation of AVX-512 for the consumer segment. Addition of Vector Neural Network Instructions (VNNI) </td></tr> <tr> <td>2019 </td> <td>AMD <a href="/wiki/AMD_Matisse" class="mw-redirect" title="AMD Matisse">Matisse</a> </td> <td colspan="3" style="background: #ececec">48-bit </td> <td>Multiple Chip Module design with I/O die separate from CPU die(s), Support for PCIe Gen4 </td></tr> <tr> <td>2020</td> <td>Intel <a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a> (<a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>-Y/U/H) </td> <td colspan="3" rowspan="2" style="background: #ececec">57-bit</td> <td>Dual ring interconnect architecture, updated Gaussian Neural Accelerator (GNA2), new AVX-512 Vector Intersection Instructions, addition of Control-Flow Enforcement Technology (CET) </td></tr> <tr> <td>2021</td> <td>Intel <a href="/wiki/Alder_Lake_(microarchitecture)" class="mw-redirect" title="Alder Lake (microarchitecture)">Alder Lake</a></td> <td>Hybrid design with performance (Golden Cove) and efficiency cores (Gracemont), support for PCIe Gen5 and DDR5, updated Gaussian Neural Accelerator (GNA3). AVX-512 not officially supported </td></tr> <tr> <td>2022 </td> <td>AMD <a href="/wiki/AMD_Vermeer" class="mw-redirect" title="AMD Vermeer">Vermeer</a> (5800X3D) </td> <td colspan="3" rowspan="2" style="background: #ececec">48-bit </td> <td>X3D chips have an additional 64MB 3D vertically stacked L3 cache (3D V-Cache) for up to 96MB L3 Cache </td></tr> <tr> <td>2022 </td> <td>AMD <a href="/wiki/AMD_Raphael" class="mw-redirect" title="AMD Raphael">Raphael</a> </td> <td>AMD's first implementation of AVX-512 for the consumer segment, iGPU now standard on Ryzen CPU's with 2 <a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> compute cores </td></tr> <tr> <th colspan="2">Era </th> <th rowspan="2">Introduction </th> <th rowspan="2">Prominent CPU models </th> <th colspan="3"><a href="/wiki/Address_space" title="Address space">Address space</a> </th> <th rowspan="2">Notable features </th></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=3" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Designers_and_manufacturers">Designers and manufacturers</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=4" title="Edit section: Designers and manufacturers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Am386SXL-25cropped.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f5/Am386SXL-25cropped.jpg/220px-Am386SXL-25cropped.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f5/Am386SXL-25cropped.jpg/330px-Am386SXL-25cropped.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f5/Am386SXL-25cropped.jpg/440px-Am386SXL-25cropped.jpg 2x" data-file-width="1440" data-file-height="1440" /></a><figcaption><a href="/wiki/Am386" title="Am386">Am386</a>, released by AMD in 1991</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/List_of_former_IA-32_compatible_processor_manufacturers" title="List of former IA-32 compatible processor manufacturers">List of former IA-32 compatible processor manufacturers</a></div> <p>At various times, companies such as <a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA</a>, <a href="/wiki/NEC" title="NEC">NEC</a>,<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>h<span class="cite-bracket">]</span></a></sup> <a href="/wiki/AMD" title="AMD">AMD</a>, <a href="/wiki/Texas_Instruments" title="Texas Instruments">TI</a>, <a href="/wiki/STMicroelectronics" title="STMicroelectronics">STM</a>, <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu</a>, <a href="/wiki/Oki_Electric_Industry" title="Oki Electric Industry">OKI</a>, <a href="/wiki/Siemens" title="Siemens">Siemens</a>, <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a>, <a href="/wiki/Intersil" title="Intersil">Intersil</a>, <a href="/wiki/Chips_and_Technologies" title="Chips and Technologies">C&T</a>, <a href="/wiki/NexGen" title="NexGen">NexGen</a>, <a href="/wiki/United_Microelectronics_Corporation" title="United Microelectronics Corporation">UMC</a>, and <a href="/wiki/Vortex86" title="Vortex86">DM&P</a> started to design or manufacture<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>i<span class="cite-bracket">]</span></a></sup> x86 <a href="/wiki/Central_processing_unit" title="Central processing unit">processors</a> (CPUs) intended for personal computers and embedded systems. Other companies that designed or manufactured x86 or <a href="/wiki/X87" title="X87">x87</a> processors include <a href="/wiki/ITT_Corporation" class="mw-redirect" title="ITT Corporation">ITT Corporation</a>, <a href="/wiki/National_Semiconductor" title="National Semiconductor">National Semiconductor</a>, ULSI System Technology, and <a href="/wiki/Weitek" title="Weitek">Weitek</a>. </p><p>Such x86 implementations were seldom simple copies but often employed different internal <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitectures</a> and different solutions at the electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the <a href="/wiki/Personal_computer" title="Personal computer">personal computer</a> market, real quantities started to appear around 1990 with <a href="/wiki/I386" title="I386">i386</a> and <a href="/wiki/I486" title="I486">i486</a> compatible processors, often named similarly to Intel's original chips. </p><p>After the fully <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelined</a> <a href="/wiki/I486" title="I486">i486</a>, in 1993 <a href="/wiki/Intel" title="Intel">Intel</a> introduced the <a href="/wiki/Pentium" title="Pentium">Pentium</a> brand name (which, unlike numbers, could be <a href="/wiki/Trademark" title="Trademark">trademarked</a>) for their new set of <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> x86 designs. With the x86 naming scheme now legally cleared, other x86 vendors had to choose different names for their x86-compatible products, and initially some chose to continue with variations of the numbering scheme: <a href="/wiki/IBM" title="IBM">IBM</a> partnered with <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a> to produce the <a href="/wiki/Cyrix_Cx5x86" class="mw-redirect" title="Cyrix Cx5x86">5x86</a> and then the very efficient <a href="/wiki/6x86" class="mw-redirect" title="6x86">6x86</a> (M1) and <a href="/wiki/6x86" class="mw-redirect" title="6x86">6x86</a>MX (<a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">MII</a>) lines of Cyrix designs, which were the first x86 microprocessors implementing <a href="/wiki/Register_renaming" title="Register renaming">register renaming</a> to enable <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>. </p><p>AMD meanwhile designed and manufactured the advanced but delayed <a href="/wiki/5k86" class="mw-redirect" title="5k86">5k86</a> (<a href="/wiki/AMD_K5" title="AMD K5">K5</a>), which, internally, was closely based on AMD's earlier <a href="/wiki/29K" class="mw-redirect" title="29K">29K</a> <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a> design; similar to <a href="/wiki/NexGen" title="NexGen">NexGen</a>'s <a href="/wiki/Nx586" class="mw-redirect" title="Nx586">Nx586</a>, it used a strategy such that dedicated pipeline stages decode x86 instructions into uniform and easily handled <a href="/wiki/Micro-operation" title="Micro-operation">micro-operations</a>, a method that has remained the basis for most x86 designs to this day. </p><p>Some early versions of these microprocessors had heat dissipation problems. The 6x86 was also affected by a few minor compatibility problems, the <a href="/wiki/Nx586" class="mw-redirect" title="Nx586">Nx586</a> lacked a <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU) and (the then crucial) pin-compatibility, while the <a href="/wiki/AMD_K5" title="AMD K5">K5</a> had somewhat disappointing performance when it was (eventually) introduced. </p><p>Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the <a href="/wiki/AMD_K5" title="AMD K5">K5</a> had very good Pentium compatibility and the <a href="/wiki/6x86" class="mw-redirect" title="6x86">6x86</a> was significantly faster than the Pentium on integer code.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>j<span class="cite-bracket">]</span></a></sup> <a href="/wiki/AMD" title="AMD">AMD</a> later managed to grow into a serious contender with the <a href="/wiki/AMD_K6" title="AMD K6">K6</a> set of processors, which gave way to the very successful <a href="/wiki/Athlon" title="Athlon">Athlon</a> and <a href="/wiki/Opteron" title="Opteron">Opteron</a>. </p><p>There were also other contenders, such as <a href="/wiki/Centaur_Technology" title="Centaur Technology">Centaur Technology</a> (formerly <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">IDT</a>), <a href="/wiki/Rise_Technology" title="Rise Technology">Rise Technology</a>, and <a href="/wiki/Transmeta" title="Transmeta">Transmeta</a>. <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA Technologies</a>' energy efficient <a href="/wiki/VIA_C3" title="VIA C3">C3</a> and <a href="/wiki/VIA_C7" title="VIA C7">C7</a> processors, which were designed by the <a href="/wiki/Centaur_Technology" title="Centaur Technology">Centaur</a> company, were sold for many years following their release in 2005. Centaur's 2008 design, the <a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a>, was their first processor with <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> and <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>. It was introduced at about the same time (in 2008) as Intel introduced the <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a>, its first "in-order" processor after the <a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a> <a href="/wiki/Pentium" title="Pentium">Pentium</a>. </p><p>Many additions and extensions have been added to the original x86 instruction set over the years, almost consistently with full <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a>.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>k<span class="cite-bracket">]</span></a></sup> The architecture family has been implemented in processors from Intel, <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a>, <a href="/wiki/AMD" title="AMD">AMD</a>, <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA Technologies</a> and many other companies; there are also open implementations, such as the <a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet SoC</a> platform (currently inactive).<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> Nevertheless, of those, only Intel, AMD, VIA Technologies, and <a href="/wiki/Vortex86" title="Vortex86">DM&P Electronics</a> hold x86 architectural licenses, and from these, only the first two actively produce modern 64-bit designs, leading to what has been called a "duopoly" of Intel and AMD in x86 processors. </p><p>However, in 2014 the Shanghai-based Chinese company <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a>, a joint venture between a Chinese company and VIA Technologies, began designing VIA based x86 processors for desktops and laptops. The release of its newest "7" family<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> of x86 processors (e.g. KX-7000), which are not quite as fast as AMD or Intel chips but are still state of the art,<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> had been planned for 2021; as of March 2022 the release had not taken place, however.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="From_16-bit_and_32-bit_to_64-bit_architecture">From 16-bit and 32-bit to 64-bit architecture</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=5" title="Edit section: From 16-bit and 32-bit to 64-bit architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> has twice been extended to a larger <a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">word</a> size. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>) during the following years; this extended programming model was originally referred to as <i>the i386 architecture</i> (like its first implementation) but Intel later dubbed it <a href="/wiki/IA-32" title="IA-32">IA-32</a> when introducing its (unrelated) <a href="/wiki/IA-64" title="IA-64">IA-64</a> architecture. </p><p>In 1999–2003, <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> extended this 32-bit architecture to 64 bits and referred to it as <a href="/wiki/X86-64" title="X86-64">x86-64</a> in early documents and later as <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>. Intel soon adopted AMD's architectural extensions under the name IA-32e, later using the name EM64T and finally using Intel 64. <a href="/wiki/Microsoft" title="Microsoft">Microsoft</a> and <a href="/wiki/Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a>/<a href="/wiki/Oracle_Corporation" title="Oracle Corporation">Oracle</a> also use term "x64", while many <a href="/wiki/Linux_distribution" title="Linux distribution">Linux distributions</a>, and the <a href="/wiki/BSD" class="mw-redirect" title="BSD">BSDs</a> also use the "amd64" term. Microsoft Windows, for example, designates its 32-bit versions as "x86" and 64-bit versions as "x64", while installation files of 64-bit Windows versions are required to be placed into a directory called "AMD64".<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p><p>In 2023, Intel proposed a major change to the architecture referred to as <a href="/wiki/X86-64#X86S" title="X86-64">X86S</a> (formerly known as X86-S). The S in X86S stands for "simplification", which aims to remove support for legacy execution modes and instructions. A processor implementing this proposal would start execution directly in <a href="/wiki/Long_mode" title="Long mode">long mode</a> and would only support 64-bit operating systems. 32-bit code would only be supported for user applications running in ring 3, and would use the same simplified segmentation as long mode.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Basic_properties_of_the_architecture">Basic properties of the architecture</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=6" title="Edit section: Basic properties of the architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The x86 architecture is a variable instruction length, primarily "<a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a>" design with emphasis on <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a>. The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit <a href="/wiki/Intel_8008" title="Intel 8008">8008</a> and <a href="/wiki/Intel_8080" title="Intel 8080">8080</a> architectures. Byte-addressing is enabled and words are stored in memory with <a href="/wiki/Endianness" title="Endianness">little-endian</a> byte order. Memory access to unaligned addresses is allowed for almost all instructions. The largest native size for <a href="/wiki/Integer_(computing)" class="mw-redirect" title="Integer (computing)">integer</a> arithmetic and memory addresses (or <a href="/wiki/Offset_(computer_science)" title="Offset (computer science)">offsets</a>) is 16, 32 or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well). Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>l<span class="cite-bracket">]</span></a></sup> Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for the frequently occurring cases or contexts where a −128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte). </p><p>To further conserve encoding space, most registers are expressed in <a href="/wiki/Opcode" title="Opcode">opcodes</a> using three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand to an instruction can be a memory location.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>m<span class="cite-bracket">]</span></a></sup> However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on the stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache. </p> <div class="mw-heading mw-heading3"><h3 id="Floating_point_and_SIMD">Floating point and SIMD</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=7" title="Edit section: Floating point and SIMD"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A dedicated <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point processor</a> with 80-bit internal registers, the <a href="/wiki/Intel_8087" title="Intel 8087">8087</a>, was developed for the original <a href="/wiki/8086" class="mw-redirect" title="8086">8086</a>. This microprocessor subsequently developed into the extended <a href="/wiki/80387" class="mw-redirect" title="80387">80387</a>, and later processors incorporated a <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> version of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain a <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a>-unit (see <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> below) where instructions can work in parallel on (one or two) 128-bit words, each containing two or four <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point numbers</a> (each 64 or 32 bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8 bits wide respectively). </p><p>The presence of wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in a single instruction and also perform bitwise operations (although not integer arithmetic<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>n<span class="cite-bracket">]</span></a></sup>) on full 128-bits quantities in parallel. Intel's <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> processors added the <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights Corner <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> processors, and the <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> instructions implemented by the Knights Landing Xeon Phi processors and by <a href="/wiki/Skylake_(microarchitecture)#High-end_desktop_processors_(Skylake-X)" title="Skylake (microarchitecture)">Skylake-X</a> processors, use 512-bit wide SIMD registers. </p> <div class="mw-heading mw-heading2"><h2 id="Current_implementations">Current implementations</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=8" title="Edit section: Current implementations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>During <a href="/wiki/Execution_(computers)" class="mw-redirect" title="Execution (computers)">execution</a>, current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces called micro-operations. These are then handed to a <a href="/wiki/Control_unit" title="Control unit">control unit</a> that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) <a href="/wiki/Execution_units" class="mw-redirect" title="Execution units">execution units</a>. These modern x86 designs are thus <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelined</a>, <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a>, and also capable of <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out of order</a> and <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a> (via <a href="/wiki/Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a>, <a href="/wiki/Register_renaming" title="Register renaming">register renaming</a>, and <a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">memory dependence prediction</a>), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in the same order as given in the instruction stream.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> Some Intel CPUs (<a href="/wiki/Xeon#Foster" title="Xeon">Xeon Foster MP</a>, some <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>, and some <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> and later <a href="/wiki/Intel_Core" title="Intel Core">Intel Core</a> processors) and AMD CPUs (starting from <a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a>) are also capable of <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> with two <a href="/wiki/Thread_(computer_science)" class="mw-redirect" title="Thread (computer science)">threads</a> per <a href="/wiki/Multi-core_processor" title="Multi-core processor">core</a> (<a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> has four threads per core). Some Intel CPUs support <a href="/wiki/Transactional_memory" title="Transactional memory">transactional memory</a> (<a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a>). </p><p>When introduced, in the mid-1990s, this method was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, traditional <a href="/wiki/Microcode" title="Microcode">microcode</a> (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize the execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit. </p><p>The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into a more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved. </p><p>Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their <a href="/wiki/NetBurst" title="NetBurst">NetBurst</a> microarchitecture (for Pentium 4 processors) and later in the Decoded Stream Buffer (for Core-branded processors since Sandy Bridge).<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Transmeta" title="Transmeta">Transmeta</a> used a completely different method in their <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a> x86 compatible CPUs. They used <a href="/wiki/Just-in-time_compilation" title="Just-in-time compilation">just-in-time</a> translation to convert x86 instructions to the CPU's native <a href="/wiki/VLIW" class="mw-redirect" title="VLIW">VLIW</a> instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations. </p> <div class="mw-heading mw-heading2"><h2 id="Addressing_modes">Addressing modes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=9" title="Edit section: Addressing modes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a> for 16-bit processor modes can be summarized by the formula:<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\end{matrix}}\ \ {\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {BX}}\\{\mathtt {BP}}\end{bmatrix}}+{\begin{bmatrix}{\mathtt {SI}}\\{\mathtt {DI}}\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">C</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> </mtable> </mrow> <mtext> </mtext> <mtext> </mtext> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>(</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd /> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">P</mi> </mrow> </mrow> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd /> </mtr> </mtable> <mo>)</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="normal">d</mi> <mi mathvariant="normal">i</mi> <mi mathvariant="normal">s</mi> <mi mathvariant="normal">p</mi> <mi mathvariant="normal">l</mi> <mi mathvariant="normal">a</mi> <mi mathvariant="normal">c</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">m</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">n</mi> <mi mathvariant="normal">t</mi> </mrow> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\end{matrix}}\ \ {\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {BX}}\\{\mathtt {BP}}\end{bmatrix}}+{\begin{bmatrix}{\mathtt {SI}}\\{\mathtt {DI}}\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/405d0baf770d62b897802f29e1a682724d4db108" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -5.671ex; width:40.628ex; height:12.509ex;" alt="{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\end{matrix}}\ \ {\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {BX}}\\{\mathtt {BP}}\end{bmatrix}}+{\begin{bmatrix}{\mathtt {SI}}\\{\mathtt {DI}}\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}"></span></dd></dl> <p>Addressing modes for 32-bit x86 processor modes<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> can be summarized by the formula:<sup id="cite_ref-addrmodes_42-0" class="reference"><a href="#cite_note-addrmodes-42"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\\{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {ESP}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">C</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">F</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">G</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> </mtable> </mrow> <mtext> </mtext> <mtext> </mtext> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">A</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">C</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">P</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">P</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>(</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd /> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">A</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">C</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">X</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">B</mi> <mi mathvariant="monospace">P</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">S</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">E</mi> <mi mathvariant="monospace">D</mi> <mi mathvariant="monospace">I</mi> </mrow> </mrow> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> <mo>∗</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mn>2</mn> </mtd> </mtr> <mtr> <mtd> <mn>4</mn> </mtd> </mtr> <mtr> <mtd> <mn>8</mn> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd /> </mtr> </mtable> <mo>)</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="normal">d</mi> <mi mathvariant="normal">i</mi> <mi mathvariant="normal">s</mi> <mi mathvariant="normal">p</mi> <mi mathvariant="normal">l</mi> <mi mathvariant="normal">a</mi> <mi mathvariant="normal">c</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">m</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">n</mi> <mi mathvariant="normal">t</mi> </mrow> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\\{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {ESP}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a8f86b5ea0949d4bad74de4b167fcc9628515993" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -13.838ex; width:51.569ex; height:28.843ex;" alt="{\displaystyle {\begin{matrix}{\mathtt {CS}}:\\{\mathtt {DS}}:\\{\mathtt {SS}}:\\{\mathtt {ES}}:\\{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {ESP}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}{\mathtt {EAX}}\\{\mathtt {EBX}}\\{\mathtt {ECX}}\\{\mathtt {EDX}}\\{\mathtt {EBP}}\\{\mathtt {ESI}}\\{\mathtt {EDI}}\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}+{\rm {displacement}}}"></span></dd></dl> <p>Addressing modes for the 64-bit processor mode can be summarized by the formula:<sup id="cite_ref-addrmodes_42-1" class="reference"><a href="#cite_note-addrmodes-42"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\begin{Bmatrix}\\{\begin{matrix}{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \\\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}\\\\\hline \\{\begin{matrix}{\mathtt {RIP}}\end{matrix}}\\\\\end{Bmatrix}}+{\rm {displacement}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>{</mo> <mtable rowspacing="4pt" columnspacing="1em" rowlines="none none solid none"> <mtr> <mtd /> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">F</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">G</mi> <mi mathvariant="monospace">S</mi> </mrow> </mrow> <mo>:</mo> </mtd> </mtr> </mtable> </mrow> <mtext> </mtext> <mtext> </mtext> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mo>⋮</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">G</mi> <mi mathvariant="monospace">P</mi> <mi mathvariant="monospace">R</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mo>⋮</mo> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>(</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd /> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mo>⋮</mo> </mtd> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">G</mi> <mi mathvariant="monospace">P</mi> <mi mathvariant="monospace">R</mi> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd> <mo>⋮</mo> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> <mo>∗</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow> <mo>[</mo> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mn>1</mn> </mtd> </mtr> <mtr> <mtd> <mn>2</mn> </mtd> </mtr> <mtr> <mtd> <mn>4</mn> </mtd> </mtr> <mtr> <mtd> <mn>8</mn> </mtd> </mtr> </mtable> <mo>]</mo> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd /> </mtr> </mtable> <mo>)</mo> </mrow> </mrow> </mtd> </mtr> <mtr> <mtd /> </mtr> <mtr> <mtd /> </mtr> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mtable rowspacing="4pt" columnspacing="1em"> <mtr> <mtd> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">R</mi> <mi mathvariant="monospace">I</mi> <mi mathvariant="monospace">P</mi> </mrow> </mrow> </mtd> </mtr> </mtable> </mrow> </mtd> </mtr> <mtr> <mtd /> </mtr> </mtable> <mo>}</mo> </mrow> </mrow> <mo>+</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="normal">d</mi> <mi mathvariant="normal">i</mi> <mi mathvariant="normal">s</mi> <mi mathvariant="normal">p</mi> <mi mathvariant="normal">l</mi> <mi mathvariant="normal">a</mi> <mi mathvariant="normal">c</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">m</mi> <mi mathvariant="normal">e</mi> <mi mathvariant="normal">n</mi> <mi mathvariant="normal">t</mi> </mrow> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\begin{Bmatrix}\\{\begin{matrix}{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \\\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}\\\\\hline \\{\begin{matrix}{\mathtt {RIP}}\end{matrix}}\\\\\end{Bmatrix}}+{\rm {displacement}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/74a19e80c5e175febface72d51393386270c5b5b" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -17.671ex; width:58.311ex; height:36.509ex;" alt="{\displaystyle {\begin{Bmatrix}\\{\begin{matrix}{\mathtt {FS}}:\\{\mathtt {GS}}:\end{matrix}}\ \ {\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \end{bmatrix}}+{\begin{pmatrix}\\{\begin{bmatrix}\vdots \\{\mathtt {GPR}}\\\vdots \\\end{bmatrix}}*{\begin{bmatrix}1\\2\\4\\8\end{bmatrix}}\\\\\end{pmatrix}}\\\\\hline \\{\begin{matrix}{\mathtt {RIP}}\end{matrix}}\\\\\end{Bmatrix}}+{\rm {displacement}}}"></span></dd></dl> <p>Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the <a href="/wiki/Instruction_pointer" class="mw-redirect" title="Instruction pointer">instruction pointer register</a>) simplifies the implementation of <a href="/wiki/Position-independent_code" title="Position-independent code">position-independent code</a> (as used in <a href="/wiki/Shared_libraries" class="mw-redirect" title="Shared libraries">shared libraries</a> in some operating systems).<sup id="cite_ref-Andriesse_2019_43-0" class="reference"><a href="#cite_note-Andriesse_2019-43"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> </p><p>The 8086 had <span class="nowrap"><span data-sort-value="7005512000000000000♠"></span>64 KB</span> of eight-bit (or alternatively <span class="nowrap"><span data-sort-value="7001320000000000000♠"></span>32 K-word of 16-bit</span>) <a href="/wiki/I/O" class="mw-redirect" title="I/O">I/O</a> space, and a <span class="nowrap"><span data-sort-value="7005512000000000000♠"></span>64 KB</span> (one segment) <a href="/wiki/Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a> in memory supported by <a href="/wiki/Computer_hardware" title="Computer hardware">computer hardware</a>. Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, with <style data-mw-deduplicate="TemplateStyles:r886049734">.mw-parser-output .monospaced{font-family:monospace,monospace}</style><span class="monospaced">SS:SP</span> pointing to the most recently pushed item. There are 256 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the <a href="/wiki/Return_statement" title="Return statement">return address</a>. </p> <div class="mw-heading mw-heading2"><h2 id="x86_registers">x86 registers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=10" title="Edit section: x86 registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For a description of the general notion of a CPU register, see <a href="/wiki/Processor_register" title="Processor register">Processor register</a>.</div> <div class="mw-heading mw-heading3"><h3 id="16-bit">16-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=11" title="Edit section: 16-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The original <a href="/wiki/Intel_8086" title="Intel 8086">Intel 8086</a> and <a href="/wiki/Intel_8088" title="Intel 8088">8088</a> have fourteen 16-<a href="/wiki/Bit" title="Bit">bit</a> registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as a counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of the <a href="/wiki/Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a>, and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see <a href="/wiki/Frame_pointer" class="mw-redirect" title="Frame pointer">frame pointer</a>). The registers SI, DI, BX and BP are <a href="/wiki/Address_register" class="mw-redirect" title="Address register">address registers</a>, and may also be used for array indexing. </p><p>One of four possible 'segment registers' (CS, DS, SS and ES) is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported. </p><p>The <a href="/wiki/FLAGS_register_(computing)" class="mw-redirect" title="FLAGS register (computing)">FLAGS register</a> contains <a href="/wiki/Flag_(computing)" class="mw-redirect" title="Flag (computing)">flags</a> such as <a href="/wiki/Carry_flag" title="Carry flag">carry flag</a>, <a href="/wiki/Overflow_flag" title="Overflow flag">overflow flag</a> and <a href="/wiki/Zero_flag" title="Zero flag">zero flag</a>. Finally, the instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </p><p>The <a href="/wiki/Intel_80186" title="Intel 80186">Intel 80186</a> and <a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for the peripherals). </p><p>The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the <a href="/wiki/Intel_8087" title="Intel 8087">8087</a>. The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer.<sup id="cite_ref-i86_14-1" class="reference"><a href="#cite_note-i86-14"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: S-6, S-13..S-15">: S-6, S-13..S-15 </span></sup> It also has its own 16-bit status register accessible through the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">fstsw</span> instruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p>In the <a href="/wiki/Intel_80286" title="Intel 80286">Intel 80286</a>, to support <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>, three special registers hold descriptor table addresses (GDTR, LDTR, <a href="/wiki/Interrupt_descriptor_table" title="Interrupt descriptor table">IDTR</a>), and a fourth task register (TR) is used for task switching. The <a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a> is the floating-point coprocessor for the 80286 and has the same registers as the 8087 with the same data formats. </p> <div class="mw-heading mw-heading3"><h3 id="32-bit">32-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=12" title="Edit section: 32-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Table_of_x86_Registers_svg.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/15/Table_of_x86_Registers_svg.svg/480px-Table_of_x86_Registers_svg.svg.png" decoding="async" width="480" height="169" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/15/Table_of_x86_Registers_svg.svg/720px-Table_of_x86_Registers_svg.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/15/Table_of_x86_Registers_svg.svg/960px-Table_of_x86_Registers_svg.svg.png 2x" data-file-width="3055" data-file-height="1075" /></a><figcaption>Registers available in the x86-64 instruction set</figcaption></figure> <p>With the advent of the 32-bit <a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">80386</a> processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and <a href="/wiki/FLAGS_register" title="FLAGS register">FLAGS register</a>, but not the segment registers, were expanded to 32 bits. The nomenclature represented this by prefixing an "<b>E</b>" (for "extended") to the register names in <a href="/wiki/X86_assembly_language" title="X86 assembly language">x86 assembly language</a>. Thus, the AX register corresponds to the lower 16 bits of the new 32-bit EAX register, SI corresponds to the lower 16 bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes. </p><p>Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands, the <a href="/wiki/Machine_code" title="Machine code">machine code</a> format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa. </p><p>The 80386 had an optional floating-point coprocessor, the <a href="/wiki/80387" class="mw-redirect" title="80387">80387</a>; it had eight 80-bit wide registers: st(0) to st(7),<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> like the 8087 and 80287. The 80386 could also use an 80287 coprocessor.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> With the <a href="/wiki/80486" class="mw-redirect" title="80486">80486</a> and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip. </p><p>The <a href="/wiki/Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a> added eight 64-bit <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> integer vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack).<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> With the <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a>, Intel added a 32-bit <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7).<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="64-bit">64-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=13" title="Edit section: 64-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/X86-64" title="X86-64">x86-64</a></div> <p>Starting with the <a href="/wiki/AMD_Opteron" class="mw-redirect" title="AMD Opteron">AMD Opteron</a> processor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. An <b>R</b>-prefix (for "register") identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8–R15) were also introduced in the creation of <a href="/wiki/X86-64" title="X86-64">x86-64</a>. Also, eight more SSE vector registers (XMM8–XMM15) were added. However, these extensions are only usable in 64-bit mode, which is one of the two modes only available in <a href="/wiki/Long_mode" title="Long mode">long mode</a>. The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, virtual addresses are now sign extended to 64 bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (the <a href="/wiki/Instruction_pointer" class="mw-redirect" title="Instruction pointer">instruction pointer</a>), to ease the implementation of <a href="/wiki/Position-independent_code" title="Position-independent code">position-independent code</a>, used in shared libraries in some operating systems. </p> <div class="mw-heading mw-heading3"><h3 id="128-bit">128-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=14" title="Edit section: 128-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Streaming_SIMD_Extensions#Registers" title="Streaming SIMD Extensions">Streaming SIMD Extensions § Registers</a></div> <p>SIMD registers XMM0–XMM15 (XMM0–XMM31 when <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> is supported). </p> <div class="mw-heading mw-heading3"><h3 id="256-bit">256-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=15" title="Edit section: 256-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Advanced_Vector_Extensions#New_features" title="Advanced Vector Extensions">Advanced Vector Extensions § New features</a></div> <p>SIMD registers YMM0–YMM15 (YMM0–YMM31 when <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register. </p> <div class="mw-heading mw-heading3"><h3 id="512-bit">512-bit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=16" title="Edit section: 512-bit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Advanced_Vector_Extensions#AVX-512" title="Advanced Vector Extensions">Advanced Vector Extensions § AVX-512</a></div> <p>SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto the corresponding YMM register. </p> <div class="mw-heading mw-heading3"><h3 id="Miscellaneous/special_purpose"><span id="Miscellaneous.2Fspecial_purpose"></span>Miscellaneous/special purpose</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=17" title="Edit section: Miscellaneous/special purpose"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>x86 processors that have a <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>, i.e. the 80286 and later processors, also have three descriptor registers (GDTR, LDTR, <a href="/wiki/Interrupt_descriptor_table" title="Interrupt descriptor table">IDTR</a>) and a task register (TR). </p><p>32-bit x86 processors (starting with the 80386) also include various special/miscellaneous registers such as <a href="/wiki/Control_register" title="Control register">control registers</a> (CR0 through 4, CR8 for 64-bit only), <a href="/wiki/Debug_register" class="mw-redirect" title="Debug register">debug registers</a> (DR0 through 3, plus 6 and 7), <a href="/wiki/Test_register" title="Test register">test registers</a> (TR3 through 7; 80486 only), and <a href="/wiki/Model-specific_register" title="Model-specific register">model-specific registers</a> (MSRs, appearing with the Pentium<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>o<span class="cite-bracket">]</span></a></sup>). </p><p><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> has eight extra 64-bit mask registers K0–K7 for selecting elements in a vector register. Depending on the vector register and element widths, only a subset of bits of the mask register may be used by a given instruction. </p> <div class="mw-heading mw-heading3"><h3 id="Purpose">Purpose</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=18" title="Edit section: Purpose"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Although the main registers (with the exception of the instruction pointer) are "general-purpose" in the 32-bit and 64-bit versions of the instruction set and can be used for anything, it was originally envisioned that they be used for the following purposes: </p> <ul><li>AL/AH/AX/EAX/RAX: Accumulator</li> <li>CL/CH/CX/ECX/RCX: Counter (for use with loops and strings)</li> <li>DL/DH/DX/EDX/RDX: Extend the precision of the accumulator (e.g. combine 32-bit EAX and EDX for 64-bit integer operations in 32-bit code)</li> <li>BL/BH/BX/EBX/RBX: Base index (for use with arrays)</li> <li>SP/ESP/RSP: Stack pointer for top address of the stack.</li> <li>BP/EBP/RBP: Stack base pointer for holding the address of the current <a href="/wiki/Stack_frame" class="mw-redirect" title="Stack frame">stack frame</a>.</li> <li>SI/ESI/RSI: <i>Source index</i> for <a href="/wiki/String_(computer_science)" title="String (computer science)">string</a> operations.</li> <li>DI/EDI/RDI: <i>Destination index</i> for string operations.</li> <li>IP/EIP/RIP: Instruction pointer. Holds the <a href="/wiki/Program_counter" title="Program counter">program counter</a>, the address of next instruction.</li></ul> <p>Segment registers: </p> <ul><li>CS: Code</li> <li>DS: Data</li> <li>SS: Stack</li> <li>ES: Extra data</li> <li>FS: Extra data #2</li> <li>GS: Extra data #3</li></ul> <p>No particular purposes were envisioned for the other 8 registers available only in 64-bit mode. </p><p>Some instructions compile and execute more efficiently when using these registers for their designed purpose. For example, using AL as an <a href="/wiki/Accumulator_(computing)" title="Accumulator (computing)">accumulator</a> and adding an immediate byte value to it produces the efficient <i>add to AL</i> <a href="/wiki/Opcode" title="Opcode">opcode</a> of 04h, whilst using the BL register produces the generic and longer <i>add to register</i> opcode of 80C3h. Another example is double precision division and multiplication that works specifically with the AX and DX registers. </p><p>Modern compilers benefited from the introduction of the <i>sib</i> byte (<i>scale-index-base byte</i>) that allows registers to be treated uniformly (<a href="/wiki/Minicomputer" title="Minicomputer">minicomputer</a>-like). However, using the sib byte universally is non-optimal, as it produces longer encodings than only using it selectively when necessary. (The main benefit of the sib byte is the orthogonality and more powerful addressing modes it provides, which make it possible to save instructions and the use of registers for address calculations such as scaling an index.) Some special instructions lost priority in the hardware design and became slower than equivalent small code sequences. A notable example is the LODSW instruction. </p> <div class="mw-heading mw-heading3"><h3 id="Structure">Structure</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=19" title="Edit section: Structure"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <caption>General Purpose Registers (A, B, C and D) </caption> <tbody><tr> <th style="width:50pt;">64 </th> <th style="width:50pt;">56 </th> <th style="width:50pt;">48 </th> <th style="width:50pt;">40 </th> <th style="width:50pt;">32 </th> <th style="width:50pt;">24 </th> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="8" style="text-align:center;">R?X </td></tr> <tr> <td colspan="4" style="background:lightgrey"> </td> <td colspan="4" style="text-align:center;">E?X </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td colspan="2" style="text-align:center;">?X </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td style="text-align:center;">?H </td> <td style="text-align:center;">?L </td></tr></tbody></table> <table class="wikitable"> <caption>64-bit mode-only General Purpose Registers (R8, R9, R10, R11, R12, R13, R14, R15) </caption> <tbody><tr> <th style="width:50pt;">64 </th> <th style="width:50pt;">56 </th> <th style="width:50pt;">48 </th> <th style="width:50pt;">40 </th> <th style="width:50pt;">32 </th> <th style="width:50pt;">24 </th> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="8" style="text-align:center;">? </td></tr> <tr> <td colspan="4" style="background:lightgrey"> </td> <td colspan="4" style="text-align:center;">?D </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td colspan="2" style="text-align:center;">?W </td></tr> <tr> <td colspan="7" style="background:lightgrey"> </td> <td style="text-align:center;">?B </td></tr></tbody></table> <table class="wikitable"> <caption>Segment Registers (C, D, S, E, F and G) </caption> <tbody><tr> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="2" style="text-align:center;">?S </td></tr></tbody></table> <table class="wikitable"> <caption>Pointer Registers (S and B) </caption> <tbody><tr> <th style="width:50pt;">64 </th> <th style="width:50pt;">56 </th> <th style="width:50pt;">48 </th> <th style="width:50pt;">40 </th> <th style="width:50pt;">32 </th> <th style="width:50pt;">24 </th> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="8" style="text-align:center;">R?P </td></tr> <tr> <td colspan="4" style="background:lightgrey"> </td> <td colspan="4" style="text-align:center;">E?P </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td colspan="2" style="text-align:center;">?P </td></tr> <tr> <td colspan="7" style="background:lightgrey"> </td> <td style="text-align:center;">?PL </td></tr></tbody></table> <p>Note: The ?PL registers are only available in 64-bit mode. </p> <table class="wikitable"> <caption>Index Registers (S and D) </caption> <tbody><tr> <th style="width:50pt;">64 </th> <th style="width:50pt;">56 </th> <th style="width:50pt;">48 </th> <th style="width:50pt;">40 </th> <th style="width:50pt;">32 </th> <th style="width:50pt;">24 </th> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="8" style="text-align:center;">R?I </td></tr> <tr> <td colspan="4" style="background:lightgrey"> </td> <td colspan="4" style="text-align:center;">E?I </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td colspan="2" style="text-align:center;">?I </td></tr> <tr> <td colspan="7" style="background:lightgrey"> </td> <td style="text-align:center;">?IL </td></tr></tbody></table> <p>Note: The ?IL registers are only available in 64-bit mode. </p> <table class="wikitable"> <caption>Instruction Pointer Register (I) </caption> <tbody><tr> <th style="width:50pt;">64 </th> <th style="width:50pt;">56 </th> <th style="width:50pt;">48 </th> <th style="width:50pt;">40 </th> <th style="width:50pt;">32 </th> <th style="width:50pt;">24 </th> <th style="width:50pt;">16 </th> <th style="width:50pt;">8 </th></tr> <tr> <td colspan="8" style="text-align:center;">RIP </td></tr> <tr> <td colspan="4" style="background:lightgrey"> </td> <td colspan="4" style="text-align:center;">EIP </td></tr> <tr> <td colspan="6" style="background:lightgrey"> </td> <td colspan="2" style="text-align:center;">IP </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Operating_modes">Operating modes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=20" title="Edit section: Operating modes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Real_mode">Real mode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=21" title="Edit section: Real mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Real_mode" title="Real mode">Real mode</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/X86" title="Special:EditPage/X86">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a> in this section. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">January 2014</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>Real Address mode,<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> commonly called Real mode, is an operating mode of <a href="/wiki/8086" class="mw-redirect" title="8086">8086</a> and later x86-compatible <a href="/wiki/Central_processing_unit" title="Central processing unit">CPUs</a>. Real mode is characterized by a 20-bit segmented memory address space (meaning that only slightly more than 1 <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> of memory can be addressed<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>p<span class="cite-bracket">]</span></a></sup>), direct software access to peripheral hardware, and no concept of <a href="/wiki/Memory_protection" title="Memory protection">memory protection</a> or <a href="/wiki/Computer_multitasking" title="Computer multitasking">multitasking</a> at the hardware level. All x86 CPUs in the <a href="/wiki/Intel_80286" title="Intel 80286">80286</a> series and later start up in real mode at power-on; <a href="/wiki/Intel_80186" title="Intel 80186">80186</a> CPUs and earlier had only one operational mode, which is equivalent to real mode in later chips. (On the IBM PC platform, direct software access to the IBM <a href="/wiki/BIOS" title="BIOS">BIOS</a> routines is available only in real mode, since BIOS is written for real mode. However, this is not a property of the x86 CPU but of the IBM BIOS design.) </p><p>In order to use more than 64 KB of memory, the segment registers must be used. This created great complications for compiler implementors who introduced odd pointer modes such as "near", "far" and "huge" to leverage the implicit nature of segmented architecture to different degrees, with some pointers containing 16-bit offsets within implied segments and other pointers containing segment addresses and offsets within segments. It is technically possible to use up to 256 KB of memory for code and data, with up to 64 KB for code, by setting all four segment registers once and then only using 16-bit offsets (optionally with default-segment override prefixes) to address memory, but this puts substantial restrictions on the way data can be addressed and memory operands can be combined, and it violates the architectural intent of the Intel designers, which is for separate data items (e.g. arrays, structures, code units) to be contained in separate segments and addressed by their own segment addresses, in new programs that are not ported from earlier 8-bit processors with 16-bit address spaces. </p> <div class="mw-heading mw-heading3"><h3 id="Unreal_mode">Unreal mode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=22" title="Edit section: Unreal mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Unreal_mode" title="Unreal mode">Unreal mode</a></div> <p>Unreal mode is used by some 16-bit <a href="/wiki/Operating_system" title="Operating system">operating systems</a> and some 32-bit <a href="/wiki/Boot_loader" class="mw-redirect" title="Boot loader">boot loaders</a>. </p> <div class="mw-heading mw-heading3"><h3 id="System_Management_Mode">System Management Mode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=23" title="Edit section: System Management Mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/System_Management_Mode" title="System Management Mode">System Management Mode</a></div> <p>The System Management Mode (SMM) is only used by the system firmware (<a href="/wiki/BIOS" title="BIOS">BIOS</a>/<a href="/wiki/UEFI" title="UEFI">UEFI</a>), not by <a href="/wiki/Operating_system" title="Operating system">operating systems</a> and applications software. The SMM code is running in SMRAM. </p> <div class="mw-heading mw-heading3"><h3 id="Protected_mode">Protected mode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=24" title="Edit section: Protected mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Protected_mode" title="Protected mode">Protected mode</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/X86" title="Special:EditPage/X86">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a> in this section. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">January 2014</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>In addition to real mode, the Intel 80286 supports protected mode, expanding addressable <a href="/wiki/Physical_memory" class="mw-redirect" title="Physical memory">physical memory</a> to 16 <a href="/wiki/Megabyte" title="Megabyte">MB</a> and addressable <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a> to 1 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a>, and providing <a href="/wiki/Protected_memory" class="mw-redirect" title="Protected memory">protected memory</a>, which prevents programs from corrupting one another. This is done by using the segment registers only for storing an index into a descriptor table that is stored in memory. There are two such tables, the <a href="/wiki/Global_Descriptor_Table" title="Global Descriptor Table">Global Descriptor Table</a> (GDT) and the <a href="/wiki/Local_Descriptor_Table" class="mw-redirect" title="Local Descriptor Table">Local Descriptor Table</a> (LDT), each holding up to 8192 segment descriptors, each segment giving access to 64 KB of memory. In the 80286, a segment descriptor provides a 24-bit <a href="/wiki/Base_address" title="Base address">base address</a>, and this base address is added to a 16-bit offset to create an absolute address. The base address from the table fulfills the same role that the literal value of the segment register fulfills in real mode; the segment registers have been converted from direct registers to indirect registers. Each segment can be assigned one of four <a href="/wiki/Ring_(computer_security)" class="mw-redirect" title="Ring (computer security)">ring</a> levels used for hardware-based <a href="/wiki/Computer_security" title="Computer security">computer security</a>. Each segment descriptor also contains a segment limit field which specifies the maximum offset that may be used with the segment. Because offsets are 16 bits, segments are still limited to 64 KB each in 80286 protected mode.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>Each time a segment register is loaded in protected mode, the 80286 must read a 6-byte segment descriptor from memory into a set of hidden internal registers. Thus, loading segment registers is much slower in protected mode than in real mode, and changing segments very frequently is to be avoided. Actual memory operations using protected mode segments are not slowed much because the 80286 and later have hardware to check the offset against the segment limit in parallel with instruction execution. </p><p>The <a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">Intel 80386</a> extended offsets and also the segment limit field in each segment descriptor to 32 bits, enabling a segment to span the entire memory space. It also introduced support in protected mode for <a href="/wiki/Paging" class="mw-redirect" title="Paging">paging</a>, a mechanism making it possible to use paged <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a> (with 4 KB page size). Paging allows the CPU to map any page of the virtual memory space to any page of the physical memory space. To do this, it uses additional mapping tables in memory called page tables. Protected mode on the 80386 can operate with paging either enabled or disabled; the segmentation mechanism is always active and generates virtual addresses that are then mapped by the paging mechanism if it is enabled. The segmentation mechanism can also be effectively disabled by setting all segments to have a base address of 0 and size limit equal to the whole address space; this also requires a minimally-sized segment descriptor table of only four descriptors (since the FS and GS segments need not be used).<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>q<span class="cite-bracket">]</span></a></sup> </p><p>Paging is used extensively by modern multitasking operating systems. <a href="/wiki/Linux" title="Linux">Linux</a>, <a href="/wiki/386BSD" title="386BSD">386BSD</a> and <a href="/wiki/Windows_NT" title="Windows NT">Windows NT</a> were developed for the 386 because it was the first Intel architecture CPU to support paging and 32-bit segment offsets. The 386 architecture became the basis of all further development in the x86 series. </p><p>x86 processors that support protected mode boot into <a href="/wiki/Real_mode" title="Real mode">real mode</a> for backward compatibility with the older 8086 class of processors. Upon power-on (a.k.a. <a href="/wiki/Booting" title="Booting">booting</a>), the processor initializes in real mode, and then begins executing instructions. Operating system boot code, which might be stored in <a href="/wiki/Read-only_memory" title="Read-only memory">read-only memory</a>, may place the processor into the <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a> to enable paging and other features. Conversely, segment arithmetic, a common practice in real mode code, is not allowed in protected mode. </p> <div class="mw-heading mw-heading4"><h4 id="Virtual_8086_mode">Virtual 8086 mode</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=25" title="Edit section: Virtual 8086 mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a></div> <p>There is also a sub-mode of operation in 32-bit protected mode (a.k.a. 80386 protected mode) called <i><a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">virtual 8086 mode</a></i>, also known as <i>V86 mode</i>. This is basically a special hybrid operating mode that allows real mode programs and operating systems to run while under the control of a protected mode supervisor operating system. This allows for a great deal of flexibility in running both protected mode programs and real mode programs simultaneously. This mode is exclusively available for the 32-bit version of protected mode; it does not exist in the 16-bit version of protected mode, or in long mode. </p> <div class="mw-heading mw-heading3"><h3 id="Long_mode">Long mode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=26" title="Edit section: Long mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Long_mode" title="Long mode">Long mode</a></div> <p>In the mid 1990s, it was obvious that the 32-bit address space of the x86 architecture was limiting its performance in applications requiring large data sets. A 32-bit address space would allow the processor to directly address only 4 GB of data, a size surpassed by applications such as <a href="/wiki/Video_editing_software" title="Video editing software">video processing</a> and <a href="/wiki/Database_engine" title="Database engine">database engines</a>. Using 64-bit addresses, it is possible to directly address 16 <a href="/wiki/Exbibyte" class="mw-redirect" title="Exbibyte">EiB</a> of data, although most 64-bit architectures do not support access to the full 64-bit address space; for example, AMD64 supports only 48 bits from a 64-bit address, split into four paging levels. </p><p>In 1999, <a href="/wiki/AMD" title="AMD">AMD</a> published a (nearly) complete specification for a <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> extension of the x86 architecture which they called <i>x86-64</i> with claimed intentions to produce. That design is currently used in almost all x86 processors, with some exceptions intended for <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>. </p><p>Mass-produced <i>x86-64</i> chips for the general market were available four years later, in 2003, after the time was spent for working prototypes to be tested and refined; about the same time, the initial name <i>x86-64</i> was changed to <i>AMD64</i>. The success of the AMD64 line of processors coupled with lukewarm reception of the IA-64 architecture forced Intel to release its own implementation of the AMD64 instruction set. Intel had previously implemented support for AMD64<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> but opted not to enable it in hopes that AMD would not bring AMD64 to market before Itanium's new IA-64 instruction set was widely adopted. It branded its implementation of AMD64 as <i>EM64T</i>, and later rebranded it <i>Intel 64</i>. </p><p>In its literature and product version names, Microsoft and Sun refer to AMD64/Intel 64 collectively as <i>x64</i> in the Windows and <a href="/wiki/Solaris_(operating_system)" class="mw-redirect" title="Solaris (operating system)">Solaris</a> operating systems. <a href="/wiki/Linux_distribution" title="Linux distribution">Linux distributions</a> refer to it either as "x86-64", its variant "x86_64", or "amd64". <a href="/wiki/Berkeley_Software_Distribution" title="Berkeley Software Distribution">BSD</a> systems use "amd64" while <a href="/wiki/MacOS" title="MacOS">macOS</a> uses "x86_64". </p><p>Long mode is mostly an extension of the 32-bit instruction set, but unlike the 16–to–32-bit transition, many instructions were dropped in the 64-bit mode. This does not affect actual binary backward compatibility (which would execute legacy code in other modes that retain support for those instructions), but it changes the way assembler and compilers for new code have to work. </p><p>This was the first time that a major extension of the x86 architecture was initiated and originated by a manufacturer other than Intel. It was also the first time that Intel accepted technology of this nature from an outside source. </p> <div class="mw-heading mw-heading2"><h2 id="Extensions">Extensions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=27" title="Edit section: Extensions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Floating-point_unit">Floating-point unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=28" title="Edit section: Floating-point unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X87" title="X87">x87</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a></div> <p>Early x86 processors could be extended with <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> hardware in the form of a series of floating-point <a href="/wiki/Numerical_analysis" title="Numerical analysis">numerical</a> <a href="/wiki/Co-processor" class="mw-redirect" title="Co-processor">co-processors</a> with names like <a href="/wiki/Intel_8087" title="Intel 8087">8087</a>, 80287 and 80387, abbreviated x87. This was also known as the NPX (<i>Numeric Processor eXtension</i>), an apt name since the coprocessors, while used mainly for floating-point calculations, also performed integer operations on both binary and decimal formats. With very few exceptions, the 80486 and subsequent x86 processors then integrated this x87 functionality on chip which made the x87 instructions a <a href="/wiki/De_facto" title="De facto">de facto</a> integral part of the x86 instruction set. </p><p>Each x87 register, known as ST(0) through ST(7), is 80 bits wide and stores numbers in the <a href="/wiki/IEEE_floating-point_standard" class="mw-redirect" title="IEEE floating-point standard">IEEE floating-point standard</a> double extended precision format. These registers are organized as a stack with ST(0) as the top. This was done in order to conserve opcode space, and the registers are therefore randomly accessible only for either operand in a register-to-register instruction; ST0 must always be one of the two operands, either the source or the destination, regardless of whether the other operand is ST(x) or a memory operand. However, random access to the stack registers can be obtained through an instruction which exchanges any specified ST(x) with ST(0). </p><p>The operations include arithmetic and transcendental functions, including trigonometric and exponential functions, and instructions that load common constants (such as 0; 1; e, the base of the natural logarithm; log2(10); and log10(2)) into one of the stack registers. While the integer ability is often overlooked, the x87 can operate on larger integers with a single instruction than the 8086, 80286, 80386, or any x86 CPU without to 64-bit extensions can, and repeated integer calculations even on small values (e.g., 16-bit) can be accelerated by executing integer instructions on the x86 CPU and the x87 in parallel. (The x86 CPU keeps running while the x87 coprocessor calculates, and the x87 sets a signal to the x86 when it is finished or interrupts the x86 if it needs attention because of an error.) </p> <div class="mw-heading mw-heading3"><h3 id="MMX">MMX</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=29" title="Edit section: MMX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX (instruction set)</a></div> <p>MMX is a <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> instruction set designed by Intel and introduced in 1997 for the <a href="/wiki/Pentium_MMX" class="mw-redirect" title="Pentium MMX">Pentium MMX</a> microprocessor.<sup id="cite_ref-intel_56-0" class="reference"><a href="#cite_note-intel-56"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> The MMX instruction set was developed from a similar concept first used on the <a href="/wiki/Intel_i860" title="Intel i860">Intel i860</a>. It is supported on most subsequent IA-32 processors by Intel and other vendors. MMX is typically used for video processing (in multimedia applications, for instance).<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p><p>MMX added 8 new registers to the architecture, known as MM0 through MM7 (henceforth referred to as <i>MMn</i>). In reality, these new registers were just aliases for the existing x87 FPU stack registers. Hence, anything that was done to the floating-point stack would also affect the MMX registers. Unlike the FP stack, these MMn registers were fixed, not relative, and therefore they were randomly accessible. The instruction set did not adopt the stack-like semantics so that existing operating systems could still correctly save and restore the register state when multitasking without modifications.<sup id="cite_ref-intel_56-1" class="reference"><a href="#cite_note-intel-56"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p><p>Each of the MMn registers are 64-bit integers. However, one of the main concepts of the MMX instruction set is the concept of <i>packed data types</i>, which means instead of using the whole register for a single 64-bit integer (<a href="/wiki/Quadword" class="mw-redirect" title="Quadword">quadword</a>), one may use it to contain two 32-bit integers (<a href="/wiki/Integer_(computer_science)" title="Integer (computer science)">doubleword</a>), four 16-bit integers (<a href="/wiki/Integer_(computer_science)" title="Integer (computer science)">word</a>) or eight 8-bit integers (<a href="/wiki/Integer_(computer_science)" title="Integer (computer science)">byte</a>). Given that the MMX's 64-bit MMn registers are aliased to the FPU stack and each of the floating-point registers are 80 bits wide, the upper 16 bits of the floating-point registers are unused in MMX. These bits are set to all ones by any MMX instruction, which correspond to the floating-point representation of <a href="/wiki/NaN" title="NaN">NaNs</a> or infinities.<sup id="cite_ref-intel_56-2" class="reference"><a href="#cite_note-intel-56"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="3DNow!"><span id="3DNow.21"></span>3DNow!</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=30" title="Edit section: 3DNow!"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a></div> <p>In 1997, AMD introduced 3DNow!.<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> The introduction of this technology coincided with the rise of <a href="/wiki/3D_computer_graphics" title="3D computer graphics">3D</a> entertainment applications and was designed to improve the CPU's <a href="/wiki/Vector_processing" class="mw-redirect" title="Vector processing">vector processing</a> performance of graphic-intensive applications. 3D video game developers and 3D graphics hardware vendors use 3DNow! to enhance their performance on AMD's <a href="/wiki/AMD_K6" title="AMD K6">K6</a> and <a href="/wiki/Athlon" title="Athlon">Athlon</a> series of processors.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p><p>3DNow! was designed to be the natural evolution of MMX from integers to floating point. As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> The only difference is that instead of packing integers into these registers, two <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">single-precision floating-point</a> numbers are packed into each register. The advantage of aliasing the FPU registers is that the same instruction and data structures used to save the state of the FPU registers can also be used to save 3DNow! register states. Thus no special modifications are required to be made to operating systems which would otherwise not know about them.<sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="SSE_and_AVX"><style data-mw-deduplicate="TemplateStyles:r1238216509">.mw-parser-output .vanchor>:target~.vanchor-text{background-color:#b1d2ff}@media screen{html.skin-theme-clientpref-night .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}</style><span class="vanchor"><span id="SSE"></span><span class="vanchor-text">SSE</span></span> and AVX</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=31" title="Edit section: SSE and AVX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>, and <a href="/wiki/SSE5" title="SSE5">SSE5</a></div> <p>In 1999, Intel introduced the Streaming SIMD Extensions (SSE) <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a>, following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the <a href="/wiki/Intel_Prescott" class="mw-redirect" title="Intel Prescott"><i>Prescott</i></a> revision of the <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> processor, SSE3 added specific memory and <a href="/wiki/Thread_(computing)" title="Thread (computing)">thread</a>-handling instructions to boost the performance of Intel's <a href="/wiki/HyperThreading" class="mw-redirect" title="HyperThreading">HyperThreading</a> technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.<sup id="cite_ref-tomshardware_62-0" class="reference"><a href="#cite_note-tomshardware-62"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p><p>SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (In <a href="/wiki/X86-64" title="X86-64">AMD64</a>, the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode. </p><p>SSE is a SIMD instruction set that works only on floating-point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of <a href="/wiki/Single_precision" class="mw-redirect" title="Single precision">single precision</a> floats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack <a href="/wiki/Double_precision" class="mw-redirect" title="Double precision">double precision</a> numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128 bits, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.<sup id="cite_ref-tomshardware_62-1" class="reference"><a href="#cite_note-tomshardware-62"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> and <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a></div> <p>The Advanced Vector Extensions (AVX) doubled the size of SSE registers to 256-bit YMM registers. It also introduced the VEX coding scheme to accommodate the larger registers, plus a few instructions to permute elements. AVX2 did not introduce extra registers, but was notable for the addition for masking, <a href="/wiki/Gather-scatter_(vector_addressing)" class="mw-redirect" title="Gather-scatter (vector addressing)">gather</a>, and shuffle instructions. </p><p>AVX-512 features yet another expansion to 32 512-bit ZMM registers and a new EVEX scheme. Unlike its predecessors featuring a monolithic extension, it is divided into many subsets that specific models of CPUs can choose to implement. </p> <div class="mw-heading mw-heading3"><h3 id="Physical_Address_Extension_(PAE)"><span id="Physical_Address_Extension_.28PAE.29"></span>Physical Address Extension (PAE)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=32" title="Edit section: Physical Address Extension (PAE)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">Physical Address Extension</a></div> <p><a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">Physical Address Extension</a> or PAE was first added in the Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, and later by <a href="/wiki/AMD" title="AMD">AMD</a> in the Athlon processors,<sup id="cite_ref-Athlon_PAE_63-0" class="reference"><a href="#cite_note-Athlon_PAE-63"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> to allow up to 64 GB of RAM to be addressed. Without PAE, physical RAM in 32-bit protected mode is usually limited to 4 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a>. PAE defines a different page table structure with wider page table entries and a third level of page table, allowing additional bits of physical address. Although the initial implementations on 32-bit processors theoretically supported up to 64 GB of RAM, chipset and other platform limitations often restricted what could actually be used. <a href="/wiki/X86-64" title="X86-64">x86-64</a> processors define page table structures that theoretically allow up to 52 bits of physical address, although again, chipset and other platform concerns (like the number of DIMM slots available, and the maximum RAM possible per DIMM) prevent such a large physical address space to be realized. On x86-64 processors PAE mode must be active before the switch to <a href="/wiki/Long_mode" title="Long mode">long mode</a>, and must remain active while <a href="/wiki/Long_mode" title="Long mode">long mode</a> is active, so while in long mode there is no "non-PAE" mode. PAE mode does not affect the width of linear or virtual addresses. </p> <div class="mw-heading mw-heading3"><h3 id="x86-64">x86-64</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=33" title="Edit section: x86-64"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/X86" title="Special:EditPage/X86">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a> in this section. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">March 2016</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X86-64" title="X86-64">x86-64</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Processor_families_in_TOP500_supercomputers.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ef/Processor_families_in_TOP500_supercomputers.svg/280px-Processor_families_in_TOP500_supercomputers.svg.png" decoding="async" width="280" height="198" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ef/Processor_families_in_TOP500_supercomputers.svg/420px-Processor_families_in_TOP500_supercomputers.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ef/Processor_families_in_TOP500_supercomputers.svg/560px-Processor_families_in_TOP500_supercomputers.svg.png 2x" data-file-width="1232" data-file-height="873" /></a><figcaption>In <a href="/wiki/Supercomputer" title="Supercomputer">supercomputer</a> <a href="/wiki/Computer_cluster" title="Computer cluster">clusters</a> (as tracked by <a href="/wiki/TOP_500" class="mw-redirect" title="TOP 500">TOP 500</a> data and visualized on the diagram above, last updated 2013), the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel (teal hatched and blue hatched, in the diagram, respectively) to replace most RISC processor architectures previously used in such systems (including <a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a>, <a href="/wiki/SPARC" title="SPARC">SPARC</a>, <a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a>, and others), and 32-bit x86 (green on the diagram), even though Intel initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the <a href="/wiki/Itanium" title="Itanium">Itanium</a> processor. The main non-x86 architecture which is still used, as of 2014, in supercomputing clusters is the <a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> used by <a href="/wiki/IBM_Power_microprocessors" title="IBM Power microprocessors">IBM Power microprocessors</a> (blue with diamond tiling in the diagram), with SPARC as a distant second.</figcaption></figure> <p>By the 2000s, 32-bit x86 processors' limits in memory addressing were an obstacle to their use in high-performance computing clusters and powerful desktop workstations. The aged 32-bit x86 was competing with much more advanced 64-bit RISC architectures which could address much more memory. Intel and the whole x86 ecosystem needed 64-bit memory addressing if x86 was to survive the 64-bit computing era, as workstation and desktop software applications were soon to start hitting the limits of 32-bit memory addressing. However, Intel felt that it was the right time to make a bold step and use the transition to 64-bit desktop computers for a transition away from the x86 architecture in general, an experiment which ultimately failed. </p><p>In 2001, Intel attempted to introduce a non-x86 64-bit architecture named <a href="/wiki/IA-64" title="IA-64">IA-64</a> in its <a href="/wiki/Itanium" title="Itanium">Itanium</a> processor, initially aiming for the <a href="/wiki/High-performance_computing" title="High-performance computing">high-performance computing</a> market, hoping that it would eventually replace the 32-bit x86.<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> While IA-64 was incompatible with x86, the Itanium processor did provide <a href="/wiki/Emulator" title="Emulator">emulation</a> abilities for translating x86 instructions into IA-64, but this affected the performance of x86 programs so badly that it was rarely, if ever, actually useful to the users: programmers should rewrite x86 programs for the IA-64 architecture or their performance on Itanium would be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it broke <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> and preferred to continue using x86 chips, and very few programs were rewritten for IA-64. </p><p>AMD decided to take another path toward 64-bit memory addressing, making sure backward compatibility would not suffer. In April 2003, AMD released the first x86 processor with 64-bit general-purpose registers, the <a href="/wiki/Opteron" title="Opteron">Opteron</a>, capable of addressing much more than 4 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a> of virtual memory using the new <a href="/wiki/X86-64" title="X86-64">x86-64</a> extension (also known as AMD64 or x64). The 64-bit extensions to the x86 architecture were enabled only in the newly introduced <a href="/wiki/Long_mode" title="Long mode">long mode</a>, therefore 32-bit and 16-bit applications and operating systems could simply continue using an AMD64 processor in protected or other modes, without even the slightest sacrifice of performance<sup id="cite_ref-x86-compat-perf_65-0" class="reference"><a href="#cite_note-x86-compat-perf-65"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> and with full compatibility back to the original instructions of the 16-bit Intel 8086.<sup id="cite_ref-amd-24593_66-0" class="reference"><a href="#cite_note-amd-24593-66"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: 13–14">: 13–14 </span></sup> The market responded positively, adopting the 64-bit AMD processors for both high-performance applications and business or home computers. </p><p>Seeing the market rejecting the incompatible Itanium processor and Microsoft supporting AMD64, Intel had to respond and introduced its own x86-64 processor, the <i><a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Prescott</a></i> Pentium 4, in July 2004.<sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> As a result, the Itanium processor with its IA-64 instruction set is rarely used and x86, through its x86-64 incarnation, is still the dominant CPU architecture in non-embedded computers. </p><p>x86-64 also introduced the <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, which offers some protection against security bugs caused by <a href="/wiki/Buffer_overrun" class="mw-redirect" title="Buffer overrun">buffer overruns</a>. </p><p>As a result of AMD's 64-bit contribution to the x86 lineage and its subsequent acceptance by Intel, the 64-bit RISC architectures ceased to be a threat to the x86 ecosystem and almost disappeared from the workstation market. x86-64 began to be utilized in powerful <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> (in its <a href="/wiki/AMD_Opteron" class="mw-redirect" title="AMD Opteron">AMD Opteron</a> and <a href="/wiki/Intel_Xeon" class="mw-redirect" title="Intel Xeon">Intel Xeon</a> incarnations), a market which was previously the natural habitat for 64-bit RISC designs (such as the <a href="/wiki/IBM_Power_microprocessors" title="IBM Power microprocessors">IBM Power microprocessors</a> or <a href="/wiki/SPARC" title="SPARC">SPARC</a> processors). The great leap toward 64-bit computing and the maintenance of backward compatibility with 32-bit and 16-bit software enabled the x86 architecture to become an extremely flexible platform today, with x86 chips being utilized from small low-power systems (for example, <a href="/wiki/Intel_Quark" title="Intel Quark">Intel Quark</a> and <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a>) to fast gaming desktop computers (for example, <a href="/wiki/Intel_Core_i7" class="mw-redirect" title="Intel Core i7">Intel Core i7</a> and <a href="/wiki/AMD_FX" title="AMD FX">AMD FX</a>/<a href="/wiki/Ryzen" title="Ryzen">Ryzen</a>), and even dominate large supercomputing <a href="/wiki/Computer_cluster" title="Computer cluster">clusters</a>, effectively leaving only the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> 32-bit and 64-bit RISC architecture as a competitor in the <a href="/wiki/Smartphone" title="Smartphone">smartphone</a> and <a href="/wiki/Tablet_computer" title="Tablet computer">tablet</a> market. </p> <div class="mw-heading mw-heading3"><h3 id="Virtualization">Virtualization</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=34" title="Edit section: Virtualization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X86_virtualization" title="X86 virtualization">x86 virtualization</a></div> <p>Prior to 2005, x86 architecture processors were unable to meet the <a href="/wiki/Popek_and_Goldberg_virtualization_requirements" title="Popek and Goldberg virtualization requirements">Popek and Goldberg requirements</a> – a specification for virtualization created in 1974 by <a href="/wiki/Gerald_J._Popek" title="Gerald J. Popek">Gerald J. Popek</a> and <a href="/wiki/Robert_P._Goldberg" title="Robert P. Goldberg">Robert P. Goldberg</a>. However, both proprietary and open-source <a href="/wiki/X86_virtualization" title="X86 virtualization">x86 virtualization</a> hypervisor products were developed using <a href="/wiki/Shadow_page_tables" class="mw-redirect" title="Shadow page tables">software-based virtualization</a>. Proprietary systems include <a href="/wiki/Hyper-V" title="Hyper-V">Hyper-V</a>, <a href="/wiki/Parallels_Workstation" title="Parallels Workstation">Parallels Workstation</a>, <a href="/wiki/VMware_ESX" class="mw-redirect" title="VMware ESX">VMware ESX</a>, <a href="/wiki/VMware_Workstation" title="VMware Workstation">VMware Workstation</a>, <a href="/wiki/VMware_Workstation_Player" title="VMware Workstation Player">VMware Workstation Player</a> and <a href="/wiki/Windows_Virtual_PC" class="mw-redirect" title="Windows Virtual PC">Windows Virtual PC</a>, while <a href="/wiki/Free_and_open-source" class="mw-redirect" title="Free and open-source">free and open-source</a> systems include <a href="/wiki/QEMU" title="QEMU">QEMU</a>, <a href="/wiki/Kernel-based_Virtual_Machine" title="Kernel-based Virtual Machine">Kernel-based Virtual Machine</a>, <a href="/wiki/VirtualBox" title="VirtualBox">VirtualBox</a>, and <a href="/wiki/Xen" title="Xen">Xen</a>. </p><p>The introduction of the AMD-V and Intel VT-x instruction sets in 2005 allowed x86 processors to meet the Popek and Goldberg virtualization requirements.<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="AES">AES</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=35" title="Edit section: AES"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/AES_instruction_set" title="AES instruction set">AES instruction set</a></div> <div class="mw-heading mw-heading3"><h3 id="APX_(Advanced_Performance_Extensions)"><span id="APX_.28Advanced_Performance_Extensions.29"></span>APX (Advanced Performance Extensions)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=36" title="Edit section: APX (Advanced Performance Extensions)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>APX (Advanced Performance Extensions) are extensions to double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.<sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-70" class="reference"><a href="#cite_note-70"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> These extensions have been called "generational"<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> and "the biggest x86 addition since 64 bits".<sup id="cite_ref-74" class="reference"><a href="#cite_note-74"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> Intel contributed APX support to <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a> (GCC) 14.<sup id="cite_ref-75" class="reference"><a href="#cite_note-75"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </p><p>According to the architecture specification,<sup id="cite_ref-76" class="reference"><a href="#cite_note-76"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> the main features of APX are: </p> <ul><li>16 additional general-purpose registers, called the Extended GPRs (EGPRs)</li> <li>Three-operand instruction formats for many integer instructions</li> <li>New conditional instructions for loads, stores, and comparisons with common instructions that do not modify flags</li> <li>Optimized register save/restore operations</li> <li>A 64-bit absolute direct jump instruction</li></ul> <p>Extended GPRs for general purpose instructions are encoded using 2-byte <a href="/wiki/REX_prefix" class="mw-redirect" title="REX prefix">REX2</a> prefix, while new instructions and extended operands for existing <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>/<a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a>/<a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> instructions are encoded with <a href="/wiki/EVEX_prefix#Extended_EVEX_prefix" title="EVEX prefix">extended EVEX</a> prefix which has four variants used for different groups of instructions. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=37" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 25em;"> <ul><li><a href="/wiki/X86_assembly_language" title="X86 assembly language">x86 assembly language</a></li> <li><a href="/wiki/X86_calling_conventions" title="X86 calling conventions">x86 calling conventions</a></li> <li><a href="/wiki/X86_instruction_listings" title="X86 instruction listings">x86 instruction listings</a></li> <li><a href="/wiki/X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a></li> <li><a href="/wiki/CPUID" title="CPUID">CPUID</a></li> <li><a href="/wiki/Itanium" title="Itanium">Itanium</a></li> <li><a href="/wiki/X86-64" title="X86-64">x86-64</a></li> <li><a href="/wiki/680x0" class="mw-redirect" title="680x0">680x0</a>, a competing architecture in the 16 & early 32bit eras</li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a>, a competing architecture in the later 32-bit and 64-bit eras</li> <li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/List_of_AMD_processors" title="List of AMD processors">List of AMD processors</a></li> <li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">List of Intel processors</a></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">List of Intel CPU microarchitectures</a></li> <li><a href="/wiki/List_of_VIA_microprocessor_cores" title="List of VIA microprocessor cores">List of VIA microprocessor cores</a></li> <li><a href="/wiki/List_of_x86_manufacturers" title="List of x86 manufacturers">List of x86 manufacturers</a></li> <li><a href="/wiki/Interrupt_request" title="Interrupt request">Interrupt request</a></li> <li><a href="/wiki/IAPX" title="IAPX">iAPX</a></li> <li><a href="/wiki/Speculative_execution_CPU_vulnerabilities" class="mw-redirect" title="Speculative execution CPU vulnerabilities">Speculative execution CPU vulnerabilities</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Virtual_legacy_wires" title="Virtual legacy wires">Virtual legacy wires</a></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=38" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width reflist-lower-alpha" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text">Unlike the <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> (and specific electronic and physical implementation) used for a specific microprocessor design.</span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text">The <a href="/wiki/GRID_Compass" class="mw-redirect" title="GRID Compass">GRID Compass</a> laptop, for instance.</span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text">Including the <a href="/wiki/8088" class="mw-redirect" title="8088">8088</a>, <a href="/wiki/80186" class="mw-redirect" title="80186">80186</a>, <a href="/wiki/80188" class="mw-redirect" title="80188">80188</a> and <a href="/wiki/80286" class="mw-redirect" title="80286">80286</a> processors.</span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text">Such a system also contained the usual mix of standard <a href="/wiki/7400_series" class="mw-redirect" title="7400 series">7400 series</a> support components, including <a href="/wiki/Multiplexer" title="Multiplexer">multiplexers</a>, buffers, and <a href="/wiki/Glue_logic" title="Glue logic">glue logic</a>.</span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text">The actual meaning of <a href="/wiki/IAPX" title="IAPX">iAPX</a> was <i>Intel Advanced Performance Architecture</i>, or sometimes <i>Intel Advanced Processor Architecture</i>.</span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text">late 1981 to early 1984, approximately</span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text">The embedded processor market is populated by more than 25 different <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">architectures</a>, which, due to the price sensitivity, low power, and hardware simplicity requirements, outnumber the x86.</span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text">The NEC V20 and V30 also provided the older 8080 instruction set, allowing PCs equipped with these microprocessors to operate CP/M applications at full speed (i.e., without the need to simulate an 8080 by software).</span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><a href="/wiki/Fabless" class="mw-redirect" title="Fabless">Fabless</a> companies designed the chip and contracted another company to manufacture it, while fabbed companies would do both the design and the manufacturing themselves. Some companies started as fabbed manufacturers and later became fabless designers, one such example being AMD.</span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text">It had a slower FPU however, which is slightly ironic as Cyrix started out as a designer of fast floating-point units for x86 processors.</span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text">Intel abandoned its "x86" naming scheme with the <i><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a> <a href="/wiki/Pentium" title="Pentium">Pentium</a></i> during 1993 (as numbers could not be trademarked). However, the term x86 was already established among technicians, compiler writers etc.</span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text">16-bit and 32-bit microprocessors were introduced during 1978 and 1985 respectively; plans for 64-bit was announced during 1999 and gradually introduced from 2003 and onwards.</span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text">Some "CISC" designs, such as the <a href="/wiki/PDP-11" title="PDP-11">PDP-11</a>, may use two.</span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text">That is because integer arithmetic generates carry between subsequent bits (unlike simple bitwise operations).</span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-50">^</a></b></span> <span class="reference-text">Two MSRs of particular interest are SYSENTER_EIP_MSR and SYSENTER_ESP_MSR, introduced on the Pentium® II processor, which store the address of the kernel mode system service handler and corresponding kernel stack pointer. Initialized during system startup, SYSENTER_EIP_MSR and SYSENTER_ESP_MSR are used by the SYSENTER (Intel) or SYSCALL (AMD) instructions to achieve Fast System Calls, about three times faster than the software interrupt method used previously.</span> </li> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text">Because a segmented address is the sum of a 16-bit segment multiplied by 16 and a 16-bit offset, the maximum address is 1,114,095 (10FFEF hex), for an addressability of 1,114,096 bytes = 1 MB + 65,520 bytes. Before the 80286, x86 CPUs had only 20 physical address lines (address bit signals), so the 21st bit of the address, bit 20, was dropped and addresses past 1 MB were mirrors of the low end of the address space (starting from address zero). Since the 80286, all x86 CPUs have at least 24 physical address lines, and bit 20 of the computed address is brought out onto the address bus in real mode, allowing the CPU to address the full 1,114,096 bytes reachable with an x86 segmented address. On the popular IBM PC platform, switchable hardware to disable the 21st address bit was added to machines with an 80286 or later so that all programs designed for 8088/8086-based models could run, while newer software could take advantage of the "high" memory in real mode and the full 16 MB or larger address space in protected mode—see A20 gate.</span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text">An extra descriptor record at the top of the table is also required, because the table starts at zero but the minimum descriptor index that can be loaded into a segment register is 1; the value 0 is reserved to represent a segment register that points to no segment.</span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=39" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFPryce1989" class="citation pressrelease cs1">Pryce, Dave (May 11, 1989). "80486 32-bit CPU breaks new ground in chip density and operating performance. (Intel Corp.) (product announcement) EDN" (Press release).</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=80486+32-bit+CPU+breaks+new+ground+in+chip+density+and+operating+performance.+%28Intel+Corp.%29+%28product+announcement%29+EDN&rft.date=1989-05-11&rft.aulast=Pryce&rft.aufirst=Dave&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSwoyer2003" class="citation web cs1">Swoyer, Stephen (April 24, 2003). <a rel="nofollow" class="external text" href="https://www.hpcwire.com/2003/09/12/amd-announces-new-amd-opteron-processors/">"AMD introduces 64-bit Opteron Chip (ESJ) (news article)"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+introduces+64-bit+Opteron+Chip+%28ESJ%29+%28news+article%29&rft.date=2003-04-24&rft.aulast=Swoyer&rft.aufirst=Stephen&rft_id=https%3A%2F%2Fwww.hpcwire.com%2F2003%2F09%2F12%2Famd-announces-new-amd-opteron-processors%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRao2009" class="citation book cs1">Rao, P.V.S. (2009). <i>Computer System Architecture</i>. Prentice-Hall of India. p. 402 (Section 19.1, <i>The x86 family of processors</i>). <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-81-203-3594-3" title="Special:BookSources/978-81-203-3594-3"><bdi>978-81-203-3594-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+System+Architecture&rft.pages=402+%28Section+19.1%2C+%27%27The+x86+family+of+processors%27%27%29&rft.pub=Prentice-Hall+of+India&rft.date=2009&rft.isbn=978-81-203-3594-3&rft.aulast=Rao&rft.aufirst=P.V.S.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMhatre2012" class="citation book cs1">Mhatre, Swapneel Chandrakant (2012). <i>Microprocessors and Interfacing Techniques: For S. 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Jaico Publishing House. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-81-8495-325-1" title="Special:BookSources/978-81-8495-325-1"><bdi>978-81-8495-325-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Microprocessors+and+Interfacing+Techniques%3A+For+S.+E.+%28Computer+Engineering%29+Semester+II+of+University+of+Pune&rft.pub=Jaico+Publishing+House&rft.date=2012&rft.isbn=978-81-8495-325-1&rft.aulast=Mhatre&rft.aufirst=Swapneel+Chandrakant&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2022" class="citation web cs1">Alcorn, Paul (February 9, 2022). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-amd-4q-2021-2022-market-share-desktop-notebook-server-x86">"AMD Sets All-Time CPU Market Share Record as Intel Gains in Desktop and Notebook PCs"</a>. <i><a href="/wiki/Tom%27s_Hardware" title="Tom's Hardware">Tom's Hardware</a></i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=AMD+Sets+All-Time+CPU+Market+Share+Record+as+Intel+Gains+in+Desktop+and+Notebook+PCs&rft.date=2022-02-09&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-amd-4q-2021-2022-market-share-desktop-notebook-server-x86&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBrandon2015" class="citation web cs1">Brandon, Jonathan (April 15, 2015). <a rel="nofollow" class="external text" href="https://icloud.pe/blog/the-cloud-beyond-x86-how-old-architectures-are-making-a-comeback/">"The cloud beyond x86: How old architectures are making a comeback"</a>. <i>ICloud PE</i>. Business Cloud News. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210819235820/https://icloud.pe/blog/the-cloud-beyond-x86-how-old-architectures-are-making-a-comeback/">Archived</a> from the original on August 19, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">November 23,</span> 2020</span>. <q>Despite the dominance of x86 in the datacentre it is difficult to ignore the noise vendors have been making over the past couple of years around non-x86 architectures like ARM...</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ICloud+PE&rft.atitle=The+cloud+beyond+x86%3A+How+old+architectures+are+making+a+comeback&rft.date=2015-04-15&rft.aulast=Brandon&rft.aufirst=Jonathan&rft_id=https%3A%2F%2Ficloud.pe%2Fblog%2Fthe-cloud-beyond-x86-how-old-architectures-are-making-a-comeback%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDvorak" class="citation web cs1">Dvorak, John C. <a rel="nofollow" class="external text" href="http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/">"Whatever Happened to the Intel iAPX432?"</a>. Dvorak.org. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171125031112/http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/">Archived</a> from the original on November 25, 2017<span class="reference-accessdate">. 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Retrieved <span class="nowrap">October 22,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Phoronix&rft.atitle=Intel+APX+Code+Begins+Landing+Within+The+GCC+Compiler&rft.aulast=Larabel&rft.aufirst=Michael&rft_id=https%3A%2F%2Fwww.phoronix.com%2Fnews%2FGCC-Intel-APX-Starts-Landing&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> <li id="cite_note-76"><span class="mw-cite-backlink"><b><a href="#cite_ref-76">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/content-details/784266/intel-advanced-performance-extensions-intel-apx-architecture-specification.html">"Intel® Advanced Performance Extensions (Intel® APX) Architecture Specification"</a>. <i>Intel</i>. July 21, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">October 22,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel%C2%AE+Advanced+Performance+Extensions+%28Intel%C2%AE+APX%29+Architecture+Specification&rft.date=2023-07-21&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fcontent-details%2F784266%2Fintel-advanced-performance-extensions-intel-apx-architecture-specification.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=40" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRosenblumGarfinkel2005" class="citation journal cs1">Rosenblum, Mendel; Garfinkel, Tal (May 2005). "Virtual machine monitors: current technology and future trends". <i>IEEE Computer</i>. <b>38</b> (5): 39–47. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.614.9870">10.1.1.614.9870</a></span>. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMC.2005.176">10.1109/MC.2005.176</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:10385623">10385623</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Computer&rft.atitle=Virtual+machine+monitors%3A+current+technology+and+future+trends&rft.volume=38&rft.issue=5&rft.pages=39-47&rft.date=2005-05&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.614.9870%23id-name%3DCiteSeerX&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A10385623%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FMC.2005.176&rft.aulast=Rosenblum&rft.aufirst=Mendel&rft.au=Garfinkel%2C+Tal&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86&action=edit&section=41" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style 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src="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/40px-Wikibooks-logo-en-noslogan.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/60px-Wikibooks-logo-en-noslogan.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/80px-Wikibooks-logo-en-noslogan.svg.png 2x" data-file-width="400" data-file-height="400" /></span></span></div> <div class="side-box-text plainlist">Wikibooks has a book on the topic of: <i><b><a href="https://en.wikibooks.org/wiki/X86_Assembly/X86_Architecture" class="extiw" title="wikibooks:X86 Assembly/X86 Architecture">X86 Assembly/X86 Architecture</a></b></i></div></div> </div> <ul><li><a rel="nofollow" class="external text" href="https://www.computerworld.com/article/2827767/why-intel-can-t-seem-to-retire-the-x86.html">Why Intel can't seem to retire the x86</a></li> <li><a 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Assembler</a> (FASM)</li> <li><a href="/wiki/GNU_Assembler" title="GNU Assembler">GNU Assembler</a> (GAS)</li> <li><a href="/wiki/High_Level_Assembly" title="High Level Assembly">High Level Assembly</a> (HLA)</li> <li><a href="/wiki/Microsoft_Macro_Assembler" title="Microsoft Macro Assembler">Microsoft Macro Assembler</a> (MASM)</li> <li><a href="/wiki/Netwide_Assembler" title="Netwide Assembler">Netwide Assembler</a> (NASM)</li> <li><a href="/wiki/Turbo_Assembler" title="Turbo Assembler">Turbo Assembler</a> (TASM)</li> <li><a href="/wiki/Open_Watcom_Assembler" title="Open Watcom Assembler">Open Watcom Assembler</a> (WASM)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Programming<br />issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Call_stack" title="Call stack">Call stack</a></li> <li><a href="/wiki/FLAGS_register" title="FLAGS register">Flags</a> <ul><li><a href="/wiki/Carry_flag" title="Carry flag">Carry flag</a></li> <li><a href="/wiki/Direction_flag" title="Direction flag">Direction flag</a></li> <li><a href="/wiki/Interrupt_flag" title="Interrupt flag">Interrupt flag</a></li> <li><a href="/wiki/Overflow_flag" title="Overflow flag">Overflow flag</a></li> <li><a href="/wiki/Zero_flag" title="Zero flag">Zero flag</a></li></ul></li> <li><a href="/wiki/Memory_address" title="Memory address">Memory address</a></li> <li><a href="/wiki/Opcode" title="Opcode">Opcode</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li> <li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/X86_calling_conventions" title="X86 calling conventions">Calling conventions</a></li> <li><a href="/wiki/X86_instruction_listings" title="X86 instruction listings">Instruction listings</a></li> <li><a class="mw-selflink-fragment" href="#x86_registers">Registers</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Instruction_set_extensions" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Multimedia_extensions" title="Template:Multimedia extensions"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Multimedia_extensions" title="Template talk:Multimedia extensions"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Multimedia_extensions" title="Special:EditPage/Template:Multimedia extensions"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Instruction_set_extensions" style="font-size:114%;margin:0 4em"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Instruction set</a> <a href="/wiki/Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <ul><li><a href="/wiki/DEC_Alpha#Motion_Video_Instructions_(MVI)" title="DEC Alpha">MVI</a></li></ul></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> <ul><li><a href="/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)" title="ARM architecture family">NEON</a></li> <li><a href="/wiki/AArch64#Scalable_Vector_Extension_(SVE)" title="AArch64">SVE</a></li></ul></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <ul><li><a href="/wiki/MDMX" title="MDMX">MDMX</a></li> <li><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></li> <li><a href="/wiki/Media_Extension_Unit" class="mw-redirect" title="Media Extension Unit">MXU</a></li> <li><a href="/wiki/MIPS_architecture#MIPS_SIMD_architecture" title="MIPS architecture">MIPS SIMD</a></li></ul></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> <ul><li><a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">MAX</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/AltiVec" title="AltiVec">VMX</a></li></ul></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a> <ul><li><a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">VIS</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a class="mw-selflink selflink">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (1996)</li> <li><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> (1998)</li> <li><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> (1999)</li> <li><a href="/wiki/SSE2" title="SSE2">SSE2</a> (2001)</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a> (2004)</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (2006)</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a> (2006)</li> <li><a href="/wiki/SSE5" title="SSE5">SSE5</a> <s>(2007)</s></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> (2008)</li> <li><a href="/wiki/F16C" title="F16C">F16C</a> (2009)</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a> (2009)</li> <li><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> (FMA4: 2011, FMA3: 2012)</li> <li><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> (2013)</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (2015)</li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> (2022)</li> <li><a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bit_manipulation" title="Bit manipulation">Bit manipulation</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a> (2014)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS16e ASE</a></li> <li><a href="/wiki/RISC-V#Compressed_subset" title="RISC-V">RVC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li> <li><a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li> <li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> (2012)</li> <li><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">SHA</a> (2013)</li> <li><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> (2015)</li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> (2015)</li> <li><a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> (2021)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> (2013)</li> <li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/X86_virtualization#Intel_virtualization_(VT-x)" title="X86 virtualization">VT-x</a> (2005)</li> <li><a href="/wiki/X86_virtualization#AMD_virtualization_(AMD-V)" title="X86 virtualization">AMD-V</a> (2006)</li> <li><a href="/wiki/X86_virtualization#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" title="X86 virtualization">VT-d</a> (AMD-Vi)</li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck through</s>.</div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"></div><div role="navigation" class="navbox" aria-labelledby="Intel" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Intel" title="Template:Intel"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel" title="Template talk:Intel"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel" title="Special:EditPage/Template:Intel"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel" style="font-size:114%;margin:0 4em"><a href="/wiki/Intel" title="Intel">Intel</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Subsidiaries</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><i><a href="/wiki/3Dlabs" title="3Dlabs">3Dlabs</a></i></li> <li><a href="/wiki/Altera" title="Altera">Altera</a></li> <li><i><a href="/wiki/Intel_Security" class="mw-redirect" title="Intel Security">Intel Security</a></i></li> <li><a href="/wiki/Mobileye" title="Mobileye">Mobileye</a></li> <li><a href="/wiki/Recon_Instruments" title="Recon Instruments">Recon Instruments</a></li> <li><a href="/wiki/Virtutech" title="Virtutech">Virtutech</a></li> <li><a href="/wiki/Wind_River_Systems" title="Wind River Systems">Wind River Systems</a></li> <li><a href="/wiki/Xircom" title="Xircom">Xircom</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Joint venture</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">4Group Holdings (50% owned by <a href="/wiki/Vantiva" title="Vantiva">Vantiva</a>)</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/3D_XPoint" title="3D XPoint">3D XPoint</a></li> <li><a href="/wiki/Accounts_%26_SSO" title="Accounts & SSO">Accounts & SSO</a></li> <li><a href="/wiki/Amplify_Tablet" title="Amplify Tablet">Amplify Tablet</a></li> <li><a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">Advanced Programmable Interrupt Controller</a></li> <li><a href="/wiki/Cache_Acceleration_Software" title="Cache Acceleration Software">Cache Acceleration Software</a></li> <li><a href="/wiki/Client_Initiated_Remote_Access" title="Client Initiated Remote Access">Client Initiated Remote Access</a></li> <li><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a></li> <li><a href="/wiki/Flexible_Display_Interface" title="Flexible Display Interface">Flexible Display Interface</a></li> <li><a href="/wiki/Hella_Zippy" title="Hella Zippy">Hella Zippy</a></li> <li><a href="/wiki/Intel_1103" title="Intel 1103">Intel 1103</a></li> <li><a href="/wiki/Intel_AZ210" title="Intel AZ210">Intel AZ210</a></li> <li><a href="/wiki/Intel_Clear_Video" title="Intel Clear Video">Intel Clear Video</a></li> <li><a href="/wiki/Intel_Display_Power_Saving_Technology" title="Intel Display Power Saving Technology">Intel Display Power Saving Technology</a></li> <li><a href="/wiki/Intel_Modular_Server_System" title="Intel Modular Server System">Intel Modular Server System</a></li> <li><a href="/wiki/Intel_Quick_Sync_Video" title="Intel Quick Sync Video">Intel Quick Sync Video</a></li> <li><a href="/wiki/Intel_Reader" title="Intel Reader">Intel Reader</a></li> <li><a href="/wiki/Intel_system_development_kit" title="Intel system development kit">Intel system development kit</a></li> <li><a href="/wiki/Intel_Upgrade_Service" title="Intel Upgrade Service">Intel Upgrade Service</a></li> <li><a href="/wiki/Intel740" title="Intel740">Intel740</a></li> <li><a href="/wiki/InTru3D" title="InTru3D">InTru3D</a></li> <li><a href="/wiki/IXP1200" title="IXP1200">IXP1200</a></li> <li><a href="/wiki/OFono" title="OFono">OFono</a></li> <li><a href="/wiki/Omni-Path" title="Omni-Path">Omni-Path</a></li> <li><a href="/wiki/Performance_acceleration_technology" title="Performance acceleration technology">Performance acceleration technology</a></li> <li><a href="/wiki/Shooting_Star_(drone)" title="Shooting Star (drone)">Shooting Star</a></li> <li><a href="/wiki/List_of_Intel_SSDs" title="List of Intel SSDs">SSDs</a> (<a href="/wiki/X25-M" title="X25-M">X25-M</a>)</li> <li><a href="/wiki/Stable_Image_Platform_Program" title="Stable Image Platform Program">Stable Image Platform Program</a></li> <li><a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a></li> <li><a href="/wiki/WiDi" title="WiDi">WiDi</a></li> <li><a class="mw-selflink selflink">x86</a></li></ul> </div><table class="nowraplinks mw-collapsible autocollapse navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Intel_processors" title="Template:Intel processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel_processors" title="Template talk:Intel processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel_processors" title="Special:EditPage/Template:Intel processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel_processors" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a class="mw-selflink selflink">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Litigation</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Advanced_Micro_Devices,_Inc._v._Intel_Corp." title="Advanced Micro Devices, Inc. v. Intel Corp.">Advanced Micro Devices, Inc. v. Intel Corp.</a></li> <li><a href="/wiki/High-Tech_Employee_Antitrust_Litigation" title="High-Tech Employee Antitrust Litigation">High-Tech Employee Antitrust Litigation</a></li> <li><a href="/wiki/Intel_Corp._v._Advanced_Micro_Devices,_Inc." title="Intel Corp. v. Advanced Micro Devices, Inc.">Intel Corp. v. Advanced Micro Devices, Inc.</a></li> <li><a href="/wiki/Intel_Corp._v._Hamidi" title="Intel Corp. v. Hamidi">Intel Corp. v. Hamidi</a></li> <li><a href="/wiki/Intel_Corporation_Inc._v_CPM_United_Kingdom_Ltd" class="mw-redirect" title="Intel Corporation Inc. v CPM United Kingdom Ltd">Intel Corporation Inc. v CPM United Kingdom Ltd</a></li> <li><a href="/wiki/Silvaco_Data_Systems_v._Intel_Corp." title="Silvaco Data Systems v. Intel Corp.">Silvaco Data Systems v. Intel Corp.</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">People</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Founders</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Gordon_Moore" title="Gordon Moore">Gordon Moore</a></li> <li><a href="/wiki/Robert_Noyce" title="Robert Noyce">Robert Noyce</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">CEOs</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Robert Noyce</li> <li>Gordon Moore</li> <li><a href="/wiki/Andrew_Grove" title="Andrew Grove">Andrew Grove</a></li> <li><a href="/wiki/Craig_Barrett_(chief_executive)" title="Craig Barrett (chief executive)">Craig Barrett</a></li> <li><a href="/wiki/Paul_Otellini" title="Paul Otellini">Paul Otellini</a></li> <li><a href="/wiki/Brian_Krzanich" title="Brian Krzanich">Brian Krzanich</a></li> <li><a href="/wiki/Bob_Swan" title="Bob Swan">Bob Swan</a></li> <li><a href="/wiki/Pat_Gelsinger" title="Pat Gelsinger">Pat Gelsinger</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Foundation_Achievement_Award" title="Intel Foundation Achievement Award">Intel Foundation Achievement Award</a></li> <li><a href="/wiki/Mac_transition_to_Intel_processors" title="Mac transition to Intel processors">Mac transition to Intel processors</a></li> <li><a href="/wiki/Intel_Architecture_Labs" title="Intel Architecture Labs">Intel Architecture Labs</a></li> <li><a href="/wiki/ASCI_Red" title="ASCI Red">ASCI Red</a></li> <li><a href="/wiki/BiiN" title="BiiN">BiiN</a></li> <li><a href="/wiki/Classmate_PC" title="Classmate PC">Classmate PC</a></li> <li><a href="/wiki/Convera_Corporation" title="Convera Corporation">Convera Corporation</a></li> <li><a href="/wiki/Copy_Exactly!" title="Copy Exactly!">Copy Exactly!</a></li> <li><a href="/wiki/Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a></li> <li><a href="/wiki/Dynamic_video_memory_technology" title="Dynamic video memory technology">Dynamic video memory technology</a></li> <li><a href="/wiki/Intel_Extreme_Masters" title="Intel Extreme Masters">Intel Extreme Masters</a></li> <li><a href="/wiki/List_of_Intel_microprocessors" class="mw-redirect" title="List of Intel microprocessors">List of Intel microprocessors</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units_(2013_or_earlier)" class="mw-redirect" title="List of Intel graphics processing units (2013 or earlier)">List of Intel graphics processing units (2013 or earlier)</a></li> <li><a href="/wiki/I/O_Acceleration_Technology" title="I/O Acceleration Technology">I/O Acceleration Technology</a></li> <li><a href="/wiki/IA-32_Execution_Layer" title="IA-32 Execution Layer">IA-32 Execution Layer</a></li> <li><a href="/wiki/IM_Flash_Technologies" title="IM Flash Technologies">IM Flash Technologies</a></li> <li><i><a href="/wiki/The_Innovators_(book)" title="The Innovators (book)">The Innovators</a></i></li> <li><a href="/wiki/Inside_Films" title="Inside Films">Inside Films</a> <ul><li><i><a href="/wiki/Inside_(2011_film)" title="Inside (2011 film)">Inside</a></i></li> <li><i><a href="/wiki/The_Beauty_Inside_(web_series)" title="The Beauty Inside (web series)">The Beauty Inside</a></i></li> <li><i><a href="/wiki/The_Power_Inside" title="The Power Inside">The Power Inside</a></i></li></ul></li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">Intel ADX</a></li> <li><a href="/wiki/Intel_Capital" title="Intel Capital">Intel Capital</a></li> <li><a href="/wiki/Intel_Cluster_Ready" title="Intel Cluster Ready">Intel Cluster Ready</a></li> <li><a href="/wiki/Intel_Compute_Stick" title="Intel Compute Stick">Intel Compute Stick</a></li> <li><a href="/wiki/Intel_Ireland" title="Intel Ireland">Intel Ireland</a></li> <li><a href="/wiki/Intel_Mobile_Communications" title="Intel Mobile Communications">Intel Mobile Communications</a></li> <li><a href="/wiki/Intel_Outstanding_Researcher_Award" title="Intel Outstanding Researcher Award">Intel Outstanding Researcher Award</a></li> <li><a href="/wiki/Intel_SHA_extensions" title="Intel SHA extensions">Intel SHA extensions</a></li> <li><a href="/wiki/Intel_Teach" title="Intel Teach">Intel Teach</a></li> <li><a href="/wiki/List_of_semiconductor_fabrication_plants" title="List of semiconductor fabrication plants">List of semiconductor fabrication plants</a></li> <li><a href="/wiki/List_of_Intel_manufacturing_sites" title="List of Intel manufacturing sites">List of Intel manufacturing sites</a></li> <li><a href="/wiki/List_of_mergers_and_acquisitions_by_Intel" title="List of mergers and acquisitions by Intel">List of mergers and acquisitions by Intel</a></li> <li><a href="/wiki/Intel_Museum" title="Intel Museum">Intel Museum</a></li> <li><a href="/wiki/OnCue" class="mw-redirect" title="OnCue">OnCue</a></li> <li><a href="/wiki/Intel_PRO/Wireless" title="Intel PRO/Wireless">Intel PRO/Wireless</a></li> <li><a href="/wiki/Intel_International_Science_and_Engineering_Fair" class="mw-redirect" title="Intel International Science and Engineering Fair">Intel International Science and Engineering Fair</a></li> <li><a href="/wiki/Regeneron_Science_Talent_Search" title="Regeneron Science Talent Search">Regeneron Science Talent Search</a></li> <li><a href="/wiki/Simple_Firmware_Interface" title="Simple Firmware Interface">Simple Firmware Interface</a></li> <li><a href="/wiki/Single-chip_Cloud_Computer" title="Single-chip Cloud Computer">Single-chip Cloud Computer</a></li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">Software Guard Extensions</a></li> <li><a href="/wiki/Supervisor_Mode_Access_Prevention" title="Supervisor Mode Access Prevention">Supervisor Mode Access Prevention</a></li> <li><a href="/wiki/Tarari_(company)" class="mw-redirect" title="Tarari (company)">Tarari</a></li> <li><a href="/wiki/Intel_Tera-Scale" title="Intel Tera-Scale">Intel Tera-Scale</a></li> <li><a href="/wiki/Timeline_of_Intel" title="Timeline of Intel">Timeline of Intel</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a class="mw-selflink selflink">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox authority-control" aria-labelledby="Authority_control_databases_frameless&#124;text-top&#124;10px&#124;alt=Edit_this_at_Wikidata&#124;link=https&#58;//www.wikidata.org/wiki/Q182933#identifiers&#124;class=noprint&#124;Edit_this_at_Wikidata" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th 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