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class="vector-main-menu-container"> <div id="mw-navigation"> <nav id="mw-panel" class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-pinned-container" class="vector-pinned-container"> </div> </nav> </div> </div> <div class="vector-sticky-pinned-container"> <nav id="mw-panel-toc" aria-label="Contents" data-event-name="ui.sidebar-toc" class="mw-table-of-contents-container vector-toc-landmark"> <div id="vector-toc-pinned-container" class="vector-pinned-container"> <div id="vector-toc" class="vector-toc vector-pinnable-element"> <div class="vector-pinnable-header vector-toc-pinnable-header vector-pinnable-header-pinned" data-feature-name="toc-pinned" data-pinnable-element-id="vector-toc" > <h2 class="vector-pinnable-header-label">Contents</h2> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-x86_integer_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#x86_integer_instructions"> <div class="vector-toc-text"> 1 x86 integer instructions </div> </a> <button aria-controls="toc-x86_integer_instructions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle x86 integer instructions subsection </button> <ul id="toc-x86_integer_instructions-sublist" class="vector-toc-list"> <li id="toc-Original_8086/8088_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Original_8086/8088_instructions"> <div class="vector-toc-text"> 1.1 Original 8086/8088 instructions </div> </a> <ul id="toc-Original_8086/8088_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_in_specific_processors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Added_in_specific_processors"> <div class="vector-toc-text"> 1.2 Added in specific processors </div> </a> <ul id="toc-Added_in_specific_processors-sublist" class="vector-toc-list"> <li id="toc-Added_with_80186/80188" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_80186/80188"> <div class="vector-toc-text"> 1.2.1 Added with 80186/80188 </div> </a> <ul id="toc-Added_with_80186/80188-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_80286" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_80286"> <div class="vector-toc-text"> 1.2.2 Added with 80286 </div> </a> <ul id="toc-Added_with_80286-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_80386" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_80386"> <div class="vector-toc-text"> 1.2.3 Added with 80386 </div> </a> <ul id="toc-Added_with_80386-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_80486" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_80486"> <div class="vector-toc-text"> 1.2.4 Added with 80486 </div> </a> <ul id="toc-Added_with_80486-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_in_P5/P6-class_processors" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_in_P5/P6-class_processors"> <div class="vector-toc-text"> 1.2.5 Added in P5/P6-class processors </div> </a> <ul id="toc-Added_in_P5/P6-class_processors-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Added_as_instruction_set_extensions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Added_as_instruction_set_extensions"> <div class="vector-toc-text"> 1.3 Added as instruction set extensions </div> </a> <ul id="toc-Added_as_instruction_set_extensions-sublist" class="vector-toc-list"> <li id="toc-Added_with_x86-64" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_x86-64"> <div class="vector-toc-text"> 1.3.1 Added with x86-64 </div> </a> <ul id="toc-Added_with_x86-64-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bit_manipulation_extensions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Bit_manipulation_extensions"> <div class="vector-toc-text"> 1.3.2 Bit manipulation extensions </div> </a> <ul id="toc-Bit_manipulation_extensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_Intel_TSX" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_Intel_TSX"> <div class="vector-toc-text"> 1.3.3 Added with Intel TSX </div> </a> <ul id="toc-Added_with_Intel_TSX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_Intel_CET" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_Intel_CET"> <div class="vector-toc-text"> 1.3.4 Added with Intel CET </div> </a> <ul id="toc-Added_with_Intel_CET-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_XSAVE" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_XSAVE"> <div class="vector-toc-text"> 1.3.5 Added with XSAVE </div> </a> <ul id="toc-Added_with_XSAVE-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_other_cross-vendor_extensions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_other_cross-vendor_extensions"> <div class="vector-toc-text"> 1.3.6 Added with other cross-vendor extensions </div> </a> <ul id="toc-Added_with_other_cross-vendor_extensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_other_Intel-specific_extensions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_other_Intel-specific_extensions"> <div class="vector-toc-text"> 1.3.7 Added with other Intel-specific extensions </div> </a> <ul id="toc-Added_with_other_Intel-specific_extensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Added_with_other_AMD-specific_extensions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Added_with_other_AMD-specific_extensions"> <div class="vector-toc-text"> 1.3.8 Added with other AMD-specific extensions </div> </a> <ul id="toc-Added_with_other_AMD-specific_extensions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-x87_floating-point_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#x87_floating-point_instructions"> <div class="vector-toc-text"> 2 x87 floating-point instructions </div> </a> <button aria-controls="toc-x87_floating-point_instructions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle x87 floating-point instructions subsection </button> <ul id="toc-x87_floating-point_instructions-sublist" class="vector-toc-list"> <li id="toc-Original_8087_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Original_8087_instructions"> <div class="vector-toc-text"> 2.1 Original 8087 instructions </div> </a> <ul id="toc-Original_8087_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-x87_instructions_added_in_later_processors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#x87_instructions_added_in_later_processors"> <div class="vector-toc-text"> 2.2 x87 instructions added in later processors </div> </a> <ul id="toc-x87_instructions_added_in_later_processors-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-SIMD_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#SIMD_instructions"> <div class="vector-toc-text"> 3 SIMD instructions </div> </a> <ul id="toc-SIMD_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cryptographic_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cryptographic_instructions"> <div class="vector-toc-text"> 4 Cryptographic instructions </div> </a> <ul id="toc-Cryptographic_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Virtualization_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Virtualization_instructions"> <div class="vector-toc-text"> 5 Virtualization instructions </div> </a> <ul id="toc-Virtualization_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Other_instructions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Other_instructions"> <div class="vector-toc-text"> 6 Other instructions </div> </a> <button aria-controls="toc-Other_instructions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Other instructions subsection </button> <ul id="toc-Other_instructions-sublist" class="vector-toc-list"> <li id="toc-Undocumented_x86_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Undocumented_x86_instructions"> <div class="vector-toc-text"> 6.1 Undocumented x86 instructions </div> </a> <ul id="toc-Undocumented_x86_instructions-sublist" class="vector-toc-list"> <li id="toc-Undocumented_instructions_that_are_widely_available_across_many_x86_CPUs_include" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Undocumented_instructions_that_are_widely_available_across_many_x86_CPUs_include"> <div class="vector-toc-text"> 6.1.1 Undocumented instructions that are widely available across many x86 CPUs include </div> </a> <ul id="toc-Undocumented_instructions_that_are_widely_available_across_many_x86_CPUs_include-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Undocumented_instructions_that_appear_only_in_a_limited_subset_of_x86_CPUs_include" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Undocumented_instructions_that_appear_only_in_a_limited_subset_of_x86_CPUs_include"> <div class="vector-toc-text"> 6.1.2 Undocumented instructions that appear only in a limited subset of x86 CPUs include </div> </a> <ul id="toc-Undocumented_instructions_that_appear_only_in_a_limited_subset_of_x86_CPUs_include-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Undocumented_x87_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Undocumented_x87_instructions"> <div class="vector-toc-text"> 6.2 Undocumented x87 instructions </div> </a> <ul id="toc-Undocumented_x87_instructions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 7 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 8 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 9 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> 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</div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">List of x86 microprocessor instructions</div> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline 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.mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar nomobile nowraplinks" style="width:auto"><tbody><tr><td class="sidebar-pretitle">Part of a series on</td></tr><tr><th class="sidebar-title-with-pretitle" style="background:lavender"><a class="mw-selflink selflink">x86 instruction listings</a></th></tr><tr><td class="sidebar-content" style="text-align:left"> <ul><li><a class="mw-selflink selflink">Main</a> (integer, system, x87)</li> <li><a href="/wiki/X86_SIMD_instruction_listings" title="X86 SIMD instruction listings">SIMD</a> (MMX, SSE, AVX, FMA, AMX)</li> <li><a href="/wiki/List_of_x86_virtualization_instructions" title="List of x86 virtualization instructions">Virtualization</a> (VT-x, AMD-V, TDX)</li> <li><a href="/wiki/List_of_x86_cryptographic_instructions" title="List of x86 cryptographic instructions">Cryptographic</a> (e.g. RDRAND, AES-NI)</li> <li><a href="/wiki/List_of_discontinued_x86_instructions" title="List of discontinued x86 instructions">Discontinued</a> (e.g. 3DNow!, MPX, XOP)</li></ul></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:X86_instruction_listings" title="Template:X86 instruction listings"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/w/index.php?title=Template_talk:X86_instruction_listings&action=edit&redlink=1" class="new" title="Template talk:X86 instruction listings (page does not exist)"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:X86_instruction_listings" title="Special:EditPage/Template:X86 instruction listings"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> The <a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> refers to the set of instructions that <a href="/wiki/X86" title="X86">x86</a>-compatible <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> support. The instructions are usually part of an <a href="/wiki/Executable" title="Executable">executable</a> program, often stored as a <a href="/wiki/Computer_file" title="Computer file">computer file</a> and executed on the processor. The x86 instruction set has been extended several times, introducing wider <a href="/wiki/Register_(computing)" class="mw-redirect" title="Register (computing)">registers</a> and datatypes as well as new functionality.<a href="#cite_note-:0-1">[1]</a> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="x86_integer_instructions">x86 integer instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=1" title="Edit section: x86 integer instructions">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X86_assembly_language" title="X86 assembly language">x86 assembly language</a></div> Below is the full <a href="/wiki/8086" class="mw-redirect" title="8086">8086</a>/<a href="/wiki/8088" class="mw-redirect" title="8088">8088</a> instruction set of Intel (81 instructions total).<a href="#cite_note-2">[2]</a> These instructions are also available in 32-bit mode, they operate instead on 32-bit registers (eax, ebx, etc.) and values instead of their 16-bit (ax, bx, etc.) counterparts. The updated instruction set is grouped according to architecture (<a href="/wiki/Intel_80186" title="Intel 80186">i186</a>, <a href="/wiki/Intel_80286" title="Intel 80286">i286</a>, <a href="/wiki/I386" title="I386">i386</a>, <a href="/wiki/I486" title="I486">i486</a>, <a href="/wiki/Pentium_(original)" title="Pentium (original)">i586</a>/<a href="/wiki/I686" class="mw-redirect" title="I686">i686</a>) and is referred to as (32-bit) <a href="/wiki/X86" title="X86">x86</a> and (64-bit) <a href="/wiki/X86-64" title="X86-64">x86-64</a> (also known as <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>). <div class="mw-heading mw-heading3"><h3 id="Original_8086/8088_instructions">Original 8086/8088 instructions</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=2" title="Edit section: Original 8086/8088 instructions">edit</a>]</div> This is the original instruction set. In the 'Notes' column, r means register, m means memory address and imm means immediate (i.e. a value). <table class="wikitable sortable"> <caption>Original 8086/8088 instruction set </caption> <tbody><tr> <th style="line-height:120%; text-align:left">In- struc- tion</th> <th>Meaning</th> <th>Notes</th> <th>Opcode </th></tr> <tr id="mnem-aaa"> <td><style data-mw-deduplicate="TemplateStyles:r886049734">.mw-parser-output .monospaced{font-family:monospace,monospace}</style><a href="/wiki/Intel_BCD_opcodes" title="Intel BCD opcodes">AAA</a></td> <td>ASCII adjust AL after addition</td> <td>used with unpacked <a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">binary-coded decimal</a></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x37 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">AAD</td> <td>ASCII adjust AX before division</td> <td>8086/8088 datasheet documents only base 10 version of the AAD instruction (<a href="/wiki/Opcode" title="Opcode">opcode</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD5 <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x0A), but any other base will work. Later Intel's documentation has the generic form too. <a href="/wiki/NEC_V20" title="NEC V20">NEC V20</a> and V30 (and possibly other NEC V-series CPUs) always use base 10, and ignore the argument, causing a number of incompatibilities</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">AAM</td> <td>ASCII adjust AX after multiplication</td> <td>Only base 10 version (Operand is 0xA) is documented, see notes for AAD</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">AAS</td> <td>ASCII adjust AL after subtraction</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x3F </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ADC</td> <td>Add with carry</td> <td>(1) <code> r += (r/m/imm+CF);</code> (2) <code>m += (r/imm+CF);</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x10...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x15, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/2, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/2 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ADD</td> <td>Add</td> <td>(1) <code> r += r/m/imm;</code> (2) <code>m += r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x00...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x05, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80/0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/0, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">AND</td> <td><a href="/wiki/Logical_conjunction" title="Logical conjunction">Logical AND</a></td> <td>(1) <code> r &= r/m/imm;</code> (2) <code>m &= r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x20...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x25, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/4, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CALL</td> <td><a href="/wiki/Function_(computer_programming)" title="Function (computer programming)">Call procedure</a></td> <td><code class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" style="" dir="ltr">push eip; eip points to the instruction directly after the call</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9A, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE8, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/2, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CBW</td> <td>Convert byte to word</td> <td><code>AX = AL ; sign extended</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x98 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CLC</td> <td>Clear <a href="/wiki/Carry_flag" title="Carry flag">carry flag</a></td> <td><code>CF = 0;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF8 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CLD</td> <td>Clear <a href="/wiki/Direction_flag" title="Direction flag">direction flag</a></td> <td><code>DF = 0;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFC </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/CLI_(x86_instruction)" class="mw-redirect" title="CLI (x86 instruction)">CLI</a></td> <td>Clear <a href="/wiki/IF_(x86_flag)" class="mw-redirect" title="IF (x86 flag)">interrupt flag</a></td> <td><code>IF = 0;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFA </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CMC</td> <td>Complement carry flag</td> <td><code>CF = !CF;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CMP</td> <td>Compare operands</td> <td>(1) <code> r - r/m/imm;</code> (2) <code>m - r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x38...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x3D, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/7, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/7 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CMPSB</td> <td>Compare bytes in memory. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPE or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPNE prefix to test and repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>if (DF==0) *(byte*)SI++ - *(byte*)ES:DI++; else *(byte*)SI-- - *(byte*)ES:DI--; </pre></div></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA6 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CMPSW</td> <td>Compare words. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPE or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPNE prefix to test and repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>if (DF==0) *(word*)SI++ - *(word*)ES:DI++; else *(word*)SI-- - *(word*)ES:DI--; </pre></div></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA7 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CWD</td> <td>Convert word to doubleword</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x99 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/Intel_BCD_opcodes" title="Intel BCD opcodes">DAA</a></td> <td>Decimal adjust AL after addition</td> <td>(used with packed <a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">binary-coded decimal</a>)</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x27 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/Intel_BCD_opcodes" title="Intel BCD opcodes">DAS</a></td> <td>Decimal adjust AL after subtraction</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x2F </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DEC</td> <td>Decrement by 1</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x48...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x4F, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFE/1, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/1 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DIV</td> <td><a href="/wiki/Signed_number_representations" title="Signed number representations">Unsigned</a> divide</td> <td>(1) <code>AX = DX:AX / r/m;</code> resulting <code>DX = remainder</code> (2) <code>AL = AX / r/m;</code> resulting <code>AH = remainder</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/6, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/6 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ESC</td> <td>Used with <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a></td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD8..<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xDF </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/HLT_(x86_instruction)" title="HLT (x86 instruction)">HLT</a></td> <td>Enter halt state</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IDIV</td> <td>Signed divide</td> <td>(1) <code>AX = DX:AX / r/m;</code> resulting <code>DX = remainder</code> (2) <code>AL = AX / r/m;</code> resulting <code>AH = remainder</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/7, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/7 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IMUL</td> <td>Signed multiply in One-operand form</td> <td>(1) <code>DX:AX = AX * r/m;</code> (2) <code>AX = AL * r/m</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/5, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IN</td> <td>Input from port</td> <td>(1) <code>AL = port[imm];</code> (2) <code>AL = port[DX];</code> (3) <code>AX = port[imm];</code> (4) <code>AX = port[DX];</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE4, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE5, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xEC, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xED </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">INC</td> <td>Increment by 1</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x40...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x47, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFE/0, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/INT_(x86_instruction)" title="INT (x86 instruction)">INT</a></td> <td>Call to <a href="/wiki/Interrupt" title="Interrupt">interrupt</a></td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCC, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCD </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">INTO</td> <td>Call to interrupt if overflow</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCE </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IRET</td> <td>Return from interrupt</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCF </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">Jcc</td> <td><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Jump if condition</a></td> <td>(<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">JA, JAE, JB, JBE, JC, JE, JG, JGE, JL, JLE, JNA, JNAE, JNB, JNBE, JNC, JNE, JNG, JNGE, JNL, JNLE, JNO, JNP, JNS, JNZ, JO, JP, JPE, JPO, JS, JZ)</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x70...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x7F </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">JCXZ</td> <td>Jump if CX is zero</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/JMP_(x86_instruction)" title="JMP (x86 instruction)">JMP</a></td> <td>Jump</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE9...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xEB, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/4, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LAHF</td> <td>Load FLAGS into AH register</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9F </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LDS</td> <td>Load DS:r with far pointer</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LEA</td> <td><a href="/wiki/Load_Effective_Address" class="mw-redirect" title="Load Effective Address">Load Effective Address</a></td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x8D </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LES</td> <td>Load ES:r with far pointer</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LOCK</td> <td>Assert BUS LOCK# signal</td> <td>(for multiprocessing)</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LODSB</td> <td>Load string byte. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) AL = *SI++; else AL = *SI--;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAC </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LODSW</td> <td>Load string word. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) AX = *SI++; else AX = *SI--;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAD </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LOOP/ <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LOOPx</td> <td>Loop control</td> <td>(<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LOOPE, LOOPNE, LOOPNZ, LOOPZ) <code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (x && --CX) goto lbl;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE2 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">MOV</td> <td>Move</td> <td>(1) <code> r = r/m/imm;</code> (2) <code>m = r/imm</code> (3) <code> r/m = sreg;</code> (4) <code> sreg = r/m;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA3, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x8C, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x8E </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">MOVSB</td> <td>Move byte from string to string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>if (DF==0) *(byte*)ES:DI++ = *(byte*)SI++; else *(byte*)ES:DI-- = *(byte*)SI--; </pre></div>.</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">MOVSW</td> <td>Move word from string to string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre>if (DF==0) *(word*)ES:DI++ = *(word*)SI++; else *(word*)ES:DI-- = *(word*)SI--; </pre></div></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">MUL</td> <td>Unsigned multiply</td> <td>(1) <code>DX:AX = AX * r/m;</code> (2) <code>AX = AL * r/m;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/4, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">NEG</td> <td><a href="/wiki/Two%27s_complement" title="Two's complement">Two's complement</a> negation</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">r/m = 0 – r/m;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/3...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/NOP_(code)" title="NOP (code)">NOP</a></td> <td>No operation</td> <td>opcode equivalent to <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">XCHG EAX, EAX</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x90 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">NOT</td> <td>Negate the operand, <a href="/wiki/Bitwise_operation#NOT" title="Bitwise operation">logical NOT</a></td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">r/m ^= -1;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/2...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/2 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">OR</td> <td><a href="/wiki/Logical_disjunction" title="Logical disjunction">Logical OR</a></td> <td>(1) <code> r ∣= r/m/imm;</code> (2) <code>m ∣= r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x08...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x0D, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/1, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/1 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">OUT</td> <td>Output to port</td> <td>(1) <code>port[imm] = AL;</code> (2) <code>port[DX] = AL;</code> (3) <code>port[imm] = AX;</code> (4) <code>port[DX] = AX;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE6, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xE7, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xEE, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xEF </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">POP</td> <td>Pop data from <a href="/wiki/Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a></td> <td><code>r/m/sreg = *SP++;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x07, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x17, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x1F, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x58...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x5F, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x8F/0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">POPF</td> <td>Pop <a href="/wiki/FLAGS_register_(computing)" class="mw-redirect" title="FLAGS register (computing)">FLAGS register</a> from stack</td> <td><code>FLAGS = *SP++;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9D </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">PUSH</td> <td>Push data onto stack</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">*--SP = r/m/sreg;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x06, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x0E, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x16, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x1E, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x50...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x57, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFF/6 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">PUSHF</td> <td>Push FLAGS onto stack</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">*--SP = FLAGS;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9C </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RCL</td> <td>Rotate left (with carry)</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/2 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/2 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RCR</td> <td>Rotate right (with carry)</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/3 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPxx</td> <td>Repeat MOVS/STOS/CMPS/LODS/SCAS</td> <td>(<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP, REPE, REPNE, REPNZ, REPZ)</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF2, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RET</td> <td>Return from procedure</td> <td>Not a real instruction. The assembler will translate these to a RETN or a RETF depending on the memory model of the target system.</td> <td> </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RETN</td> <td>Return from near procedure</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC2, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RETF</td> <td>Return from far procedure</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCA, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xCB </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ROL</td> <td>Rotate left</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/0 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ROR</td> <td>Rotate right</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/1 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/1 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SAHF</td> <td>Store AH into FLAGS</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9E </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SAL</td> <td><a href="/wiki/Arithmetic_shift" title="Arithmetic shift">Shift Arithmetically</a> left (signed shift left)</td> <td>(1) <code>r/m <<= 1;</code> (2) <code>r/m <<= CL;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/4 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SAR</td> <td>Shift Arithmetically right (signed shift right)</td> <td>(1) <code>(signed) r/m >>= 1;</code> (2) <code>(signed) r/m >>= CL;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/7 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/7 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SBB</td> <td>Subtraction with borrow</td> <td>(1) <code> r -= (r/m/imm+CF);</code> (2) <code>m -= (r/imm+CF);</code> alternative 1-byte encoding of <code>SBB AL, AL</code> is available via <a href="#Undocumented_instructions">undocumented</a> SALC instruction</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x18...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x1D, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/3, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/3 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SCASB</td> <td>Compare byte string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPE or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPNE prefix to test and repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) AL - *ES:DI++; else AL - *ES:DI--;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAE </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SCASW</td> <td>Compare word string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPE or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REPNE prefix to test and repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) AX - *ES:DI++; else AX - *ES:DI--;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAF </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SHL</td> <td><a href="/wiki/Logical_shift" title="Logical shift">Shift</a> left (unsigned shift left)</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/4 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/4 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SHR</td> <td>Shift right (unsigned shift right)</td> <td></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xC1/5 (186+), <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD0...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD3/5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">STC</td> <td>Set carry flag</td> <td><code>CF = 1;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF9 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">STD</td> <td>Set direction flag</td> <td><code>DF = 1;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFD </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/STI_(x86_instruction)" class="mw-redirect" title="STI (x86 instruction)">STI</a></td> <td>Set interrupt flag</td> <td><code>IF = 1;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xFB </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">STOSB</td> <td>Store byte in string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) *ES:DI++ = AL; else *ES:DI-- = AL;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAA </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">STOSW</td> <td>Store word in string. May be used with a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">REP prefix to repeat the instruction <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">CX times.</td> <td><code class="mw-highlight mw-highlight-lang-c mw-content-ltr" style="" dir="ltr">if (DF==0) *ES:DI++ = AX; else *ES:DI-- = AX;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xAB </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SUB</td> <td>Subtraction</td> <td>(1) <code> r -= r/m/imm;</code> (2) <code>m -= r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x28...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x2D, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/5, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/5 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><a href="/wiki/TEST_(x86_instruction)" title="TEST (x86 instruction)">TEST</a></td> <td>Logical compare (AND)</td> <td>(1) <code> r & r/m/imm;</code> (2) <code>m & r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x84, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x85, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA8, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xA9, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF6/0, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xF7/0 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">WAIT</td> <td>Wait until not busy</td> <td>Waits until BUSY# pin is inactive (used with <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a>)</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x9B </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">XCHG</td> <td>Exchange data</td> <td><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" style="" dir="ltr">r :=: r/m;</code> A <a href="/wiki/Spinlock" title="Spinlock">spinlock</a> typically uses xchg as an <a href="/wiki/Atomic_operation" class="mw-redirect" title="Atomic operation">atomic operation</a>. (<a href="/wiki/Coma_bug" class="mw-redirect" title="Coma bug">coma bug</a>).</td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x86, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x87, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x91...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x97 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">XLAT</td> <td>Table look-up translation</td> <td>behaves like <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">MOV AL, [BX+AL]</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0xD7 </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">XOR</td> <td><a href="/wiki/Exclusive_or" title="Exclusive or">Exclusive OR</a></td> <td>(1) <code> r ^+= r/m/imm;</code> (2) <code>m ^= r/imm;</code></td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x30...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x35, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x80...<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x81/6, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">0x83/6 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Added_in_specific_processors">Added in specific processors</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=3" title="Edit section: Added in specific processors">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Added_with_80186/80188">Added with <a href="/wiki/Intel_80186" title="Intel 80186">80186</a>/<a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=4" title="Edit section: Added with 80186/80188">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction</th> <th>Opcode</th> <th>Meaning</th> <th>Notes </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">BOUND</td> <td>62 /r</td> <td>Check array index against bounds</td> <td>raises software interrupt 5 if test fails </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">ENTER</td> <td>C8 iw ib</td> <td>Enter stack frame</td> <td>Modifies stack for entry to procedure for high level language. Takes two operands: the amount of storage to be allocated on the stack and the nesting level of the procedure. </td></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">INSB/INSW </td> <td>6C </td> <td rowspan="2">Input from port to string. May be used with a REP prefix to repeat the instruction CX times. </td> <td rowspan="2">equivalent to: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>IN AL, DX MOV ES:[DI], AL INC DI ; adjust DI according to operand size and DF </pre></div> </td></tr> <tr> <td>6D </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">LEAVE</td> <td>C9</td> <td>Leave stack frame</td> <td>Releases the local stack storage created by the previous ENTER instruction. </td></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">OUTSB/OUTSW </td> <td>6E </td> <td rowspan="2">Output string to port. May be used with a REP prefix to repeat the instruction CX times. </td> <td rowspan="2">equivalent to: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>MOV AL, DS:[SI] OUT DX, AL INC SI ; adjust SI according to operand size and DF </pre></div> </td></tr> <tr> <td>6F </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">POPA</td> <td>61</td> <td>Pop all general purpose registers from stack</td> <td>equivalent to: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>POP DI POP SI POP BP POP AX ; no POP SP here, all it does is ADD SP, 2 (since AX will be overwritten later) POP BX POP DX POP CX POP AX </pre></div> </td></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">PUSHA</td> <td>60</td> <td>Push all general purpose registers onto stack</td> <td>equivalent to: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>PUSH AX PUSH CX PUSH DX PUSH BX PUSH SP ; The value stored is the initial SP value PUSH BP PUSH SI PUSH DI </pre></div> </td></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">PUSH immediate </td> <td>6A ib </td> <td rowspan="2">Push an immediate byte/word value onto the stack </td> <td rowspan="2">example: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>PUSH 12h PUSH 1200h </pre></div> </td></tr> <tr> <td>68 iw </td></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IMUL immediate </td> <td>6B /r ib </td> <td rowspan="2">Signed and unsigned multiplication of immediate byte/word value </td> <td rowspan="2">example: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>IMUL BX,12h IMUL DX,1200h IMUL CX, DX, 12h IMUL BX, SI, 1200h IMUL DI, word ptr [BX+SI], 12h IMUL SI, word ptr [BP-4], 1200h </pre></div> Note that since the lower half is the same for unsigned and signed multiplication, this version of the instruction can be used for unsigned multiplication as well. </td></tr> <tr> <td>69 /r iw </td></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">SHL/SHR/SAL/SAR/ROL/ROR/RCL/RCR immediate </td> <td>C0 </td> <td rowspan="2">Rotate/shift bits with an immediate value greater than 1 </td> <td rowspan="2">example: <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>ROL AX,3 SHR BL,3 </pre></div> </td></tr> <tr> <td>C1 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Added_with_80286">Added with <a href="/wiki/80286" class="mw-redirect" title="80286">80286</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=5" title="Edit section: Added with 80286">edit</a>]</div> The new instructions added in 80286 add support for x86 <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>. Some but not all of the instructions are available in <a href="/wiki/Real_mode" title="Real mode">real mode</a> as well. <table class="wikitable sortable"> <tbody><tr> <th>Instruction</th> <th>Opcode</th> <th>Instruction description</th> <th>Real mode</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a> </th></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>LGDT m16&32</code><a href="#cite_note-gdt_idt_descriptor-4">[a]</a> </td> <td><code>0F 01 /2</code> </td> <td>Load GDTR (<a href="/wiki/Global_Descriptor_Table" title="Global Descriptor Table">Global Descriptor Table</a> Register) from memory.<a href="#cite_note-i286_serialize-5">[b]</a> </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="6" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <td><code>LIDT m16&32</code><a href="#cite_note-gdt_idt_descriptor-4">[a]</a> </td> <td><code>0F 01 /3</code> </td> <td>Load IDTR (Interrupt Descriptor Table Register) from memory.<a href="#cite_note-i286_serialize-5">[b]</a> The IDTR controls not just the address/size of the IDT (<a href="/wiki/Interrupt_Descriptor_Table" class="mw-redirect" title="Interrupt Descriptor Table">interrupt Descriptor Table</a>) in <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>, but the IVT (Interrupt Vector Table) in <a href="/wiki/Real_mode" title="Real mode">real mode</a> as well. </td></tr> <tr> <td><code>LMSW r/m16</code> </td> <td><code>0F 01 /6</code> </td> <td>Load MSW (Machine Status Word) from 16-bit register or memory.<a href="#cite_note-6">[c]</a><a href="#cite_note-8">[d]</a> </td></tr> <tr> <td><code>CLTS</code> </td> <td><code>0F 06</code> </td> <td>Clear task-switched flag in the MSW. </td></tr> <tr> <td><code>LLDT r/m16</code> </td> <td><code>0F 00 /2</code> </td> <td>Load LDTR (Local Descriptor Table Register) from 16-bit register or memory.<a href="#cite_note-i286_serialize-5">[b]</a> </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">#UD </td></tr> <tr> <td><code><a href="/wiki/Load_Task_Register" class="mw-redirect" title="Load Task Register">LTR</a> r/m16</code> </td> <td><code>0F 00 /3</code> </td> <td>Load TR (Task Register) from 16-bit register or memory.<a href="#cite_note-i286_serialize-5">[b]</a> The TSS (<a href="/wiki/Task_State_Segment" class="mw-redirect" title="Task State Segment">Task State Segment</a>) specified by the 16-bit argument is marked busy, but a task switch is not done. </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>SGDT m16&32</code><a href="#cite_note-gdt_idt_descriptor-4">[a]</a> </td> <td><code>0F 01 /0</code> </td> <td>Store GDTR to memory. </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="5" style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-12">[e]</a> </td></tr> <tr> <td><code>SIDT m16&32</code><a href="#cite_note-gdt_idt_descriptor-4">[a]</a> </td> <td><code>0F 01 /1</code> </td> <td>Store IDTR to memory. </td></tr> <tr> <td><code>SMSW r/m16</code> </td> <td><code>0F 01 /4</code> </td> <td>Store MSW to register or 16-bit memory.<a href="#cite_note-i286_extend16-13">[f]</a> </td></tr> <tr> <td><code>SLDT r/m16</code> </td> <td><code>0F 00 /0</code> </td> <td>Store LDTR to register or 16-bit memory.<a href="#cite_note-i286_extend16-13">[f]</a> </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">#UD </td></tr> <tr> <td><code>STR r/m16</code> </td> <td><code>0F 00 /1</code> </td> <td>Store TR to register or 16-bit memory.<a href="#cite_note-i286_extend16-13">[f]</a> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>ARPL r/m16,r16</code> </td> <td><code>63 /r</code><a href="#cite_note-14">[g]</a> </td> <td>Adjust RPL (Requested <a href="/wiki/Protection_ring#Privilege_level" title="Protection ring">Privilege Level</a>) field of selector. The operation performed is:<pre>if (dst & 3) < (src & 3) then dst = (dst & 0xFFFC) | (src & 3) eflags.zf = 1 else eflags.zf = 0</pre> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">#UD<a href="#cite_note-17">[h]</a> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>LAR r,r/m16</code> </td> <td><code>0F 02 /r</code> </td> <td>Load access rights byte from the specified <a href="/wiki/Segment_descriptor" title="Segment descriptor">segment descriptor</a>. Reads bytes 4-7 of segment descriptor, bitwise-ANDs it with <code>0x00FxFF00</code>,<a href="#cite_note-19">[i]</a> then stores the bottom 16/32 bits of the result in destination register. Sets <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>.ZF=1 if the descriptor could be loaded, ZF=0 otherwise. </td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">#UD </td></tr> <tr> <td><code>LSL r,r/m16</code> </td> <td><code>0F 03 /r</code> </td> <td>Load segment limit from the specified segment descriptor. Sets ZF=1 if the descriptor could be loaded, ZF=0 otherwise. </td></tr> <tr> <td><code>VERR r/m16</code> </td> <td><code>0F 00 /4</code> </td> <td>Verify a segment for reading. Sets ZF=1 if segment can be read, ZF=0 otherwise. </td></tr> <tr> <td><code>VERW r/m16</code> </td> <td><code>0F 00 /5</code> </td> <td>Verify a segment for writing. Sets ZF=1 if segment can be written, ZF=0 otherwise.<a href="#cite_note-22">[j]</a> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> <a href="/wiki/LOADALL" title="LOADALL">LOADALL</a><a href="#cite_note-i286_undoc-25">[k]</a> </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 05 </td> <td>Load all CPU registers from a 102-byte data structure starting at physical address <code>800h</code>, including "hidden" part of segment descriptor registers. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> STOREALL<a href="#cite_note-i286_undoc-25">[k]</a> </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> F1 0F 04 </td> <td>Store all CPU registers to a 102-byte data structure starting at physical address <code>800h</code>, then shut down CPU. </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-gdt_idt_descriptor-4">^ <a href="#cite_ref-gdt_idt_descriptor_4-0">a</a> <a href="#cite_ref-gdt_idt_descriptor_4-1">b</a> <a href="#cite_ref-gdt_idt_descriptor_4-2">c</a> <a href="#cite_ref-gdt_idt_descriptor_4-3">d</a> The descriptors used by the <code>LGDT</code>, <code>LIDT</code>, <code>SGDT</code> and <code>SIDT</code> instructions consist of a 2-part data structure. The first part is a 16-bit value, specifying table size in bytes minus 1. The second part is a 32-bit value (64-bit value in 64-bit mode), specifying the linear start address of the table. For <code>LGDT</code> and <code>LIDT</code> with a 16-bit operand size, the address is ANDed with 00FFFFFFh. On Intel (but not AMD) CPUs, the <code>SGDT</code> and <code>SIDT</code> instructions with a 16-bit operand size is – as of <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/325462-079.pdf">Intel SDM revision 079, March 2023</a> – documented to write a descriptor to memory with the last byte being set to 0. However, observed behavior is that bits 31:24 of the descriptor table address are written instead.<a href="#cite_note-3">[3]</a> </li> <li id="cite_note-i286_serialize-5">^ <a href="#cite_ref-i286_serialize_5-0">a</a> <a href="#cite_ref-i286_serialize_5-1">b</a> <a href="#cite_ref-i286_serialize_5-2">c</a> <a href="#cite_ref-i286_serialize_5-3">d</a> The <code>LGDT</code>, <code>LIDT</code>, <code>LLDT</code> and <code>LTR</code> instructions are serializing on <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> and later processors. </li> <li id="cite_note-6"><a href="#cite_ref-6">^</a> The <code>LMSW</code> instruction is serializing on Intel processors from <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> onwards, but not on AMD processors. </li> <li id="cite_note-8"><a href="#cite_ref-8">^</a> On 80386 and later, the "Machine Status Word" is the same as the <a href="/wiki/Control_register#CR0" title="Control register">CR0 control register</a> – however, the <code>LMSW</code> instruction can only modify the bottom 4 bits of this register and cannot clear bit 0. The inability to clear bit 0 means that <code>LMSW</code> can be used to enter but not leave x86 <a href="/wiki/Protected_Mode" class="mw-redirect" title="Protected Mode">Protected Mode</a>. On 80286, it is not possible to leave Protected Mode at all (neither with <code>LMSW</code> nor with <code>LOADALL</code><a href="#cite_note-loadall286_doc-7">[4]</a>) without a <a href="/wiki/Hardware_reset" class="mw-redirect" title="Hardware reset">CPU reset</a> – on 80386 and later, it is possible to leave Protected Mode, but this requires the use of the 80386-and-later <code>MOV</code> to <code>CR0</code> instruction. </li> <li id="cite_note-12"><a href="#cite_ref-12">^</a> If <code><a href="/wiki/Control_register#CR4" title="Control register">CR4</a>.UMIP=1</code> is set, then the <code>SGDT</code>, <code>SIDT</code>, <code>SLDT</code>, <code>SMSW</code> and <code>STR</code> instructions can only run in Ring 0. These instructions were unprivileged on all x86 CPUs from 80286 onwards until the introduction of UMIP in 2017.<a href="#cite_note-9">[5]</a> This has been a significant security problem for software-based virtualization, since it enables these instructions to be used by a VM guest to detect that it is running inside a VM.<a href="#cite_note-10">[6]</a><a href="#cite_note-11">[7]</a> </li> <li id="cite_note-i286_extend16-13">^ <a href="#cite_ref-i286_extend16_13-0">a</a> <a href="#cite_ref-i286_extend16_13-1">b</a> <a href="#cite_ref-i286_extend16_13-2">c</a> The <code>SMSW</code>, <code>SLDT</code> and <code>STR</code> instructions always use an operand size of 16 bits when used with a memory argument. With a register argument on 80386 or later processors, wider destination operand sizes are available and behave as follows: <ul><li><code>SMSW</code>: Stores full <a href="/wiki/Control_register#CR0" title="Control register">CR0</a> in x86-64 <a href="/wiki/Long_mode" title="Long mode">long mode</a>, undefined otherwise.</li> <li><code>SLDT</code>: Zero-extends 16-bit argument on <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> and later processors, undefined on earlier processors.</li> <li><code>STR</code>: Zero-extends 16-bit argument.</li></ul> </li> <li id="cite_note-14"><a href="#cite_ref-14">^</a> In 64-bit <a href="/wiki/Long_mode" title="Long mode">long mode</a>, the <code>ARPL</code> instruction is not available – the <code>63 /r</code> opcode has been reassigned to the 64-bit-mode-only <code>MOVSXD</code> instruction. </li> <li id="cite_note-17"><a href="#cite_ref-17">^</a> The <code>ARPL</code> instruction causes #UD in <a href="/wiki/Real_mode" title="Real mode">Real mode</a> and <a href="/wiki/Virtual_8086_Mode" class="mw-redirect" title="Virtual 8086 Mode">Virtual 8086 Mode</a> – Windows 95 and OS/2 2.x are known to make extensive use of this #UD to use the <code>63</code> opcode as a one-byte breakpoint to transition from Virtual 8086 Mode to kernel mode.<a href="#cite_note-15">[8]</a><a href="#cite_note-16">[9]</a> </li> <li id="cite_note-19"><a href="#cite_ref-19">^</a> Bits 19:16 of this mask are documented as "undefined" on Intel CPUs.<a href="#cite_note-18">[10]</a> On AMD CPUs, the mask is documented as <code>0x00FFFF00</code>. </li> <li id="cite_note-22"><a href="#cite_ref-22">^</a> On some Intel CPU/microcode combinations from 2019 onwards, the <code>VERW</code> instruction also flushes microarchitectural data buffers. This enables it to be used as part of workarounds for <a href="/wiki/Microarchitectural_Data_Sampling" title="Microarchitectural Data Sampling">Microarchitectural Data Sampling</a> security vulnerabilities.<a href="#cite_note-20">[11]</a><a href="#cite_note-21">[12]</a> </li> <li id="cite_note-i286_undoc-25">^ <a href="#cite_ref-i286_undoc_25-0">a</a> <a href="#cite_ref-i286_undoc_25-1">b</a> Undocumented, 80286 only.<a href="#cite_note-loadall286_doc-7">[4]</a><a href="#cite_note-23">[13]</a><a href="#cite_note-24">[14]</a> (A different variant of <code>LOADALL</code> with a different opcode and memory layout exists on 80386.) </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_80386">Added with <a href="/wiki/80386" class="mw-redirect" title="80386">80386</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=6" title="Edit section: Added with 80386">edit</a>]</div> The 80386 added support for 32-bit operation to the x86 instruction set. This was done by widening the general-purpose registers to 32 bits and introducing the concepts of OperandSize and AddressSize – most instruction forms that would previously take 16-bit data arguments were given the ability to take 32-bit arguments by setting their OperandSize to 32 bits, and instructions that could take 16-bit address arguments were given the ability to take 32-bit address arguments by setting their AddressSize to 32 bits. (Instruction forms that work on 8-bit data continue to be 8-bit regardless of OperandSize. Using a data size of 16 bits will cause only the bottom 16 bits of the 32-bit general-purpose registers to be modified – the top 16 bits are left unchanged.) The default OperandSize and AddressSize to use for each instruction is given by the D bit of the <a href="/wiki/Segment_descriptor" title="Segment descriptor">segment descriptor</a> of the current code segment - <code>D=0</code> makes both 16-bit, <code>D=1</code> makes both 32-bit. Additionally, they can be overridden on a per-instruction basis with two new instruction prefixes that were introduced in the 80386: <ul><li><code>66h</code>: OperandSize override. Will change OperandSize from 16-bit to 32-bit if <code>CS.D=0</code>, or from 32-bit to 16-bit if <code>CS.D=1</code>.</li> <li><code>67h</code>: AddressSize override. Will change AddressSize from 16-bit to 32-bit if <code>CS.D=0</code>, or from 32-bit to 16-bit if <code>CS.D=1</code>.</li></ul> The 80386 also introduced the two new segment registers <code>FS</code> and <code>GS</code> as well as the x86 <a href="/wiki/Control_register" title="Control register">control</a>, <a href="/wiki/X86_debug_register" title="X86 debug register">debug</a> and <a href="/wiki/Test_register" title="Test register">test registers</a>. The new instructions introduced in the 80386 can broadly be subdivided into two classes: <ul><li>Pre-existing opcodes that needed new mnemonics for their 32-bit OperandSize variants (e.g. <code>CWDE</code>, <code>LODSD</code>)</li> <li>New opcodes that introduced new functionality (e.g. <code>SHLD</code>, <code>SETcc</code>)</li></ul> For instruction forms where the operand size can be inferred from the instruction's arguments (e.g. <code>ADD EAX,EBX</code> can be inferred to have a 32-bit OperandSize due to its use of EAX as an argument), new instruction mnemonics are not needed and not provided. <table class="wikitable sortable"> <caption>80386: new instruction mnemonics for 32-bit variants of older opcodes </caption> <tbody><tr> <th>Type</th> <th>Instruction mnemonic</th> <th>Opcode</th> <th>Description</th> <th>Mnemonic for older 16-bit variant</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a> </th></tr> <tr> <td rowspan="7">String instructions<a href="#cite_note-26">[a]</a><a href="#cite_note-27">[b]</a> </td> <td><code>LODSD</code></td> <td><code>AD</code></td> <td>Load string doubleword: <code>EAX := DS:[rSI±±]</code></td> <td><code>LODSW</code> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>STOSD</code></td> <td><code>AB</code></td> <td>Store string doubleword: <code>ES:[rDI±±] := EAX</code></td> <td><code>STOSW</code> </td></tr> <tr> <td><code>MOVSD</code></td> <td><code>A5</code></td> <td>Move string doubleword: <code>ES:[rDI±±] := DS:[rSI±±]</code></td> <td><code>MOVSW</code> </td></tr> <tr> <td><code>CMPSD</code></td> <td><code>A7</code></td> <td>Compare string doubleword: <pre>temp1 := DS:[rSI±±] temp2 := ES:[rDI±±] CMP temp1, temp2 /* 32-bit compare and set EFLAGS */</pre></td> <td><code>CMPSW</code> </td></tr> <tr> <td><code>SCASD</code></td> <td><code>AF</code></td> <td>Scan string doubleword: <pre>temp1 := ES:[rDI±±] CMP EAX, temp1 /* 32-bit compare and set EFLAGS */</pre></td> <td><code>SCASW</code> </td></tr> <tr> <td><code>INSD</code></td> <td><code>6D</code></td> <td>Input string from doubleword I/O port:<code>ES:[rDI±±] := port[DX]</code><a href="#cite_note-28">[c]</a></td> <td><code>INSW</code></td> <td rowspan="2" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">Usually 0<a href="#cite_note-29">[d]</a> </td></tr> <tr> <td><code>OUTSD</code></td> <td><code>6F</code></td> <td>Output string to doubleword I/O port:<code>port[DX] := DS:[rSI±±]</code></td> <td><code>OUTSW</code> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="8">Other </td> <td><code>CWDE</code></td> <td><code>98</code></td> <td><a href="/wiki/Sign_extension" title="Sign extension">Sign-extend</a> 16-bit value in AX to 32-bit value in EAX<a href="#cite_note-30">[e]</a></td> <td><code>CBW</code> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>CDQ</code></td> <td><code>99</code></td> <td>Sign-extend 32-bit value in EAX to 64-bit value in EDX:EAX. Mainly used to prepare a dividend for the 32-bit <code>IDIV</code> (signed divide) instruction. </td> <td><code>CWD</code> </td></tr> <tr> <td><code>JECXZ rel8</code></td> <td><code>E3 cb</code><a href="#cite_note-31">[f]</a></td> <td>Jump if ECX is zero</td> <td><code>JCXZ</code> </td></tr> <tr> <td><code>PUSHAD</code></td> <td><code>60</code></td> <td>Push all 32-bit registers onto stack<a href="#cite_note-32">[g]</a></td> <td><code>PUSHA</code> </td></tr> <tr> <td><code>POPAD</code></td> <td><code>61</code></td> <td>Pop all 32-bit general-purpose registers off stack<a href="#cite_note-33">[h]</a></td> <td><code>POPA</code> </td></tr> <tr> <td><code>PUSHFD</code></td> <td><code>9C</code></td> <td>Push 32-bit E<a href="/wiki/FLAGS_register" title="FLAGS register">FLAGS register</a> onto stack</td> <td><code>PUSHF</code> </td> <td rowspan="3" style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-34">[i]</a> </td></tr> <tr> <td><code>POPFD</code></td> <td><code>9D</code></td> <td>Pop 32-bit EFLAGS register off stack</td> <td><code>POPF</code> </td></tr> <tr> <td><code>IRETD</code></td> <td><code>CF</code></td> <td>32-bit interrupt return. Differs from the older 16-bit <code>IRET</code> instruction in that it will pop interrupt return items (EIP,CS,EFLAGS; also ESP<a href="#cite_note-37">[j]</a> and SS if there is a <a href="/wiki/Privilege_level" class="mw-redirect" title="Privilege level">CPL</a> change; and also ES,DS,FS,GS if returning to <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">virtual 8086 mode</a>) off the stack as 32-bit items instead of 16-bit items. Should be used to return from interrupts when the interrupt handler was entered through a 32-bit <a href="/wiki/Interrupt_descriptor_table" title="Interrupt descriptor table">IDT</a> interrupt/trap gate. Instruction is serializing. </td> <td><code>IRET</code> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-26"><a href="#cite_ref-26">^</a> For the 32-bit string instructions, the ±± notation is used to indicate that the indicated register is post-decremented by 4 if <code>EFLAGS.DF=1</code> and post-incremented by 4 otherwise. For the operands where the DS segment is indicated, the DS segment can be overridden by a segment-override prefix – where the ES segment is indicated, the segment is always ES and cannot be overridden. The choice of whether to use the 16-bit SI/DI registers or the 32-bit ESI/EDI registers as the address registers to use is made by AddressSize, overridable with the <code>67</code> prefix. </li> <li id="cite_note-27"><a href="#cite_ref-27">^</a> The 32-bit string instructions accept repeat-prefixes in the same way as older 8/16-bit string instructions. For <code>LODSD</code>, <code>STOSD</code>, <code>MOVSD</code>, <code>INSD</code> and <code>OUTSD</code>, the <code>REP</code> prefix (<code>F3</code>) will repeat the instruction the number of times specified in rCX (CX or ECX, decided by AddressSize), decrementing rCX for each iteration (with rCX=0 resulting in no-op and proceeding to the next instruction). For <code>CMPSD</code> and <code>SCASD</code>, the <code>REPE</code> (<code>F3</code>) and <code>REPNE</code> (<code>F2</code>) prefixes are available, which will repeat the instruction, decrementing rCX for each iteration, but only as long as the flag condition (ZF=1 for <code>REPE</code>, ZF=0 for <code>REPNE</code>) holds true AND rCX ≠ 0. </li> <li id="cite_note-28"><a href="#cite_ref-28">^</a> For the <code>INSB/W/D</code> instructions, the memory access rights for the <code>ES:[rDI]</code> memory address might not be checked until after the port access has been performed – if this check fails (e.g. page fault or other memory exception), then the data item read from the port is lost. As such, it is not recommended to use this instruction to access an I/O port that performs any kind of side effect upon read. </li> <li id="cite_note-29"><a href="#cite_ref-29">^</a> I/O port access is only allowed when <a href="/wiki/Protection_ring#Privilege_level" title="Protection ring">CPL≤IOPL</a> or the <a href="/wiki/Task_state_segment#I/O_port_permissions" title="Task state segment">I/O port permission bitmap</a> bits for the port to access are all set to 0. </li> <li id="cite_note-30"><a href="#cite_ref-30">^</a> The <code>CWDE</code> instruction differs from the older <code>CWD</code> instruction in that <code>CWD</code> would sign-extend the 16-bit value in AX into a 32-bit value in the DX:AX register pair. </li> <li id="cite_note-31"><a href="#cite_ref-31">^</a> For the <code>E3</code> opcode (<code>JCXZ</code>/<code>JECXZ</code>), the choice of whether the instruction will use <code>CX</code> or <code>ECX</code> for its comparison (and consequently which mnemonic to use) is based on the AddressSize, not OperandSize. (OperandSize instead controls whether the jump destination should be truncated to 16 bits or not). This also applies to the loop instructions <code>LOOP</code>,<code>LOOPE</code>,<code>LOOPNE</code> (opcodes <code>E0</code>,<code>E1</code>,<code>E2</code>), however, unlike <code>JCXZ</code>/<code>JECXZ</code>, these instructions have not been given new mnemonics for their ECX-using variants. </li> <li id="cite_note-32"><a href="#cite_ref-32">^</a> For <code>PUSHA(D)</code>, the value of SP/ESP pushed onto the stack is the value it had just before the <code>PUSHA(D)</code> instruction started executing. </li> <li id="cite_note-33"><a href="#cite_ref-33">^</a> For <code>POPA</code>/<code>POPAD</code>, the stack item corresponding to SP/ESP is popped off the stack (performing a memory read), but not placed into SP/ESP. </li> <li id="cite_note-34"><a href="#cite_ref-34">^</a> The <code>PUSHFD</code> and <code>POPFD</code> instructions will cause a #GP exception if executed in <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">virtual 8086 mode</a> if IOPL is not 3. The <code>PUSHF</code>, <code>POPF</code>, <code>IRET</code> and <code>IRETD</code> instructions will cause a #GP exception if executed in Virtual-8086 mode if IOPL is not 3 and VME is not enabled. </li> <li id="cite_note-37"><a href="#cite_ref-37">^</a> If <code>IRETD</code> is used to return from kernel mode to user mode (which will entail a CPL change) and the user-mode stack <a href="/wiki/X86_memory_segmentation" title="X86 memory segmentation">segment</a> indicated by SS is a 16-bit segment, then the <code>IRETD</code> instruction will only restore the low 16 bits of the stack pointer (ESP/RSP), with the remaining bits keeping whatever value they had in kernel code before the <code>IRETD</code>. This has necessitated complex workarounds on both Linux ("ESPFIX")<a href="#cite_note-35">[15]</a> and Windows.<a href="#cite_note-36">[16]</a> This issue also affects the later 64-bit <code>IRETQ</code> instruction. </li> </ol></div></div> <table class="wikitable sortable"> <caption>80386: new opcodes introduced </caption> <tbody><tr> <th>Instruction mnemonics</th> <th>Opcode</th> <th>Description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a> </th></tr> <tr> <td><code>BT r/m, r</code></td> <td><code>0F A3 /r</code></td> <td rowspan="2"><a href="/wiki/Bit_Test" title="Bit Test">Bit Test</a>.<a href="#cite_note-bt_offsetting-38">[a]</a> Second operand specifies which bit of the first operand to test. The bit to test is copied to <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>.<a href="/wiki/Carry_flag" title="Carry flag">CF</a>. </td> <td rowspan="8" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>BT r/m, imm8</code></td> <td><code>0F BA /4 ib</code> </td></tr> <tr> <td><code>BTS r/m, r</code></td> <td><code>0F AB /r</code></td> <td rowspan="2">Bit <a href="/wiki/Test-and-set" title="Test-and-set">Test-and-set</a>.<a href="#cite_note-bt_offsetting-38">[a]</a><a href="#cite_note-bt_atomic-39">[b]</a> Second operand specifies which bit of the first operand to test and set. </td></tr> <tr> <td><code>BTS r/m, imm8</code></td> <td><code>0F BA /5 ib</code> </td></tr> <tr> <td><code>BTR r/m, r</code></td> <td><code>0F B3 /r</code></td> <td rowspan="2">Bit Test and Reset.<a href="#cite_note-bt_offsetting-38">[a]</a><a href="#cite_note-bt_atomic-39">[b]</a> Second operand specifies which bit of the first operand to test and clear. </td></tr> <tr> <td><code>BTR r/m, imm8</code></td> <td><code>0F BA /6 ib</code> </td></tr> <tr> <td><code>BTC r/m, r</code></td> <td><code>0F BB /r</code></td> <td rowspan="2">Bit Test and Complement.<a href="#cite_note-bt_offsetting-38">[a]</a><a href="#cite_note-bt_atomic-39">[b]</a> Second operand specifies which bit of the first operand to test and toggle. </td></tr> <tr> <td><code>BTC r/m, imm8</code></td> <td><code>0F BA /7 ib</code> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>BSF r, r/m</code></td> <td><code>NFx 0F BC /r</code><a href="#cite_note-40">[c]</a></td> <td><a href="/wiki/Find_first_set" title="Find first set">Bit scan</a> forward. Returns bit index of lowest set bit in input.<a href="#cite_note-bsf_bsr_zero-41">[d]</a> </td> <td rowspan="6" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>BSR r, r/m</code></td> <td><code>NFx 0F BD /r</code><a href="#cite_note-42">[e]</a></td> <td><a href="/wiki/Find_first_set" title="Find first set">Bit scan</a> reverse. Returns bit index of highest set bit in input.<a href="#cite_note-bsf_bsr_zero-41">[d]</a> </td></tr> <tr> <td><code>SHLD r/m, r, imm8</code></td> <td><code>0F A4 /r ib</code></td> <td rowspan="2">Shift Left Double. The operation of <code>SHLD arg1,arg2,shamt</code> is: <code>arg1 := (arg1<<shamt) | (arg2>>(operand_size - shamt))</code><a href="#cite_note-shld_shamt-44">[f]</a> </td></tr> <tr> <td><code>SHLD r/m, r, CL</code></td> <td><code>0F A5 /r</code> </td></tr> <tr> <td><code>SHRD r/m, r, imm8</code></td> <td><code>0F AC /r ib</code></td> <td rowspan="2">Shift Right Double. The operation of <code>SHRD arg1,arg2,shamt</code> is: <code>arg1 := (arg1>>shamt) | (arg2<<(operand_size - shamt))</code><a href="#cite_note-shld_shamt-44">[f]</a> </td></tr> <tr> <td><code>SHRD r/m, r, CL</code></td> <td><code>0F AD /r</code> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>MOVZX reg, r/m8</code></td> <td><code>0F B6 /r</code></td> <td rowspan="2">Move from 8/16-bit source to 16/32-bit register with zero-extension. </td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>MOVZX reg, r/m16</code></td> <td><code>0F B7 /r</code> </td></tr> <tr> <td><code>MOVSX reg, r/m8</code></td> <td><code>0F BE /r</code></td> <td rowspan="2">Move from 8/16-bit source to 16/32/64-bit register with <a href="/wiki/Sign-extension" class="mw-redirect" title="Sign-extension">sign-extension</a>. </td></tr> <tr> <td><code>MOVSX reg, r/m16</code></td> <td><code>0F BF /r</code> </td></tr> <tr> <td><code>SETcc r/m8</code> </td> <td><code>0F 9x /0</code><a href="#cite_note-setcc_conds-45">[g]</a><a href="#cite_note-46">[h]</a> </td> <td>Set byte to 1 if condition is satisfied, 0 otherwise. </td></tr> <tr> <td><code>Jcc rel16</code> <code>Jcc rel32</code> </td> <td><code>0F 8x cw</code> <code>0F 8x cd</code><a href="#cite_note-setcc_conds-45">[g]</a> </td> <td>Conditional jump near. Differs from older variants of conditional jumps in that they accept a 16/32-bit offset rather than just an 8-bit offset. </td></tr> <tr> <td><code>IMUL r, r/m</code></td> <td><code>0F AF /r</code></td> <td>Two-operand non-widening integer multiply. </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>FS:</code></td> <td><code>64</code></td> <td rowspan="2">Segment-override prefixes for FS and GS segment registers. </td> <td rowspan="9" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>GS:</code></td> <td><code>65</code> </td></tr> <tr> <td><code>PUSH FS</code></td> <td><code>0F A0</code></td> <td rowspan="4">Push/pop FS and GS segment registers. </td></tr> <tr> <td><code>POP FS</code></td> <td><code>0F A1</code> </td></tr> <tr> <td><code>PUSH GS</code></td> <td><code>0F A8</code> </td></tr> <tr> <td><code>POP GS</code></td> <td><code>0F A9</code> </td></tr> <tr> <td><code>LFS r16, m16&16</code> <code>LFS r32, m32&16</code></td> <td><code>0F B4 /r</code></td> <td rowspan="3">Load <a href="/wiki/Far_pointer" title="Far pointer">far pointer</a> from memory. Offset part is stored in destination register argument, segment part in FS/GS/SS segment register as indicated by the instruction mnemonic.<a href="#cite_note-47">[i]</a> </td></tr> <tr> <td><code>LGS r16, m16&16</code> <code>LGS r32, m32&16</code></td> <td><code>0F B5 /r</code> </td></tr> <tr> <td><code>LSS r16, m16&16</code> <code>LSS r32, m32&16</code></td> <td><code>0F B2 /r</code> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>MOV reg,CRx</code></td> <td><code>0F 20 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from <a href="/wiki/Control_register" title="Control register">control register</a> to general register.<a href="#cite_note-movcr_opsiz-49">[k]</a> </td> <td rowspan="6" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <td><code>MOV CRx,reg</code></td> <td><code>0F 22 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from general register to control register.<a href="#cite_note-movcr_opsiz-49">[k]</a> Moves to the <code>CR3</code> control register are serializing and will flush the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a>.<a href="#cite_note-50">[l]</a> On Pentium and later processors, moves to the <code>CR0</code> and <code>CR4</code> control registers are also serializing.<a href="#cite_note-53">[m]</a> </td></tr> <tr> <td><code>MOV reg,DRx</code></td> <td><code>0F 21 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from <a href="/wiki/X86_debug_register" title="X86 debug register">x86 debug register</a> to general register.<a href="#cite_note-movcr_opsiz-49">[k]</a> </td></tr> <tr> <td><code>MOV DRx,reg</code></td> <td><code>0F 23 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from general register to x86 debug register.<a href="#cite_note-movcr_opsiz-49">[k]</a> On Pentium and later processors, moves to the DR0-DR7 debug registers are serializing. </td></tr> <tr> <td><code>MOV reg,TRx</code></td> <td><code>0F 24 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from x86 <a href="/wiki/Test_register" title="Test register">test register</a> to general register.<a href="#cite_note-movtr_pent-54">[n]</a> </td></tr> <tr> <td><code>MOV TRx,reg</code></td> <td><code>0F 26 /r</code><a href="#cite_note-movcr_modrm-48">[j]</a></td> <td>Move from general register to x86 test register.<a href="#cite_note-movtr_pent-54">[n]</a> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> ICEBP,  INT01,  INT1<a href="#cite_note-59">[o]</a> </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> F1 </td> <td><a href="/wiki/In-circuit_emulation" title="In-circuit emulation">In-circuit emulation</a> breakpoint. Performs software interrupt #1 if executed when not using in-circuit emulation.<a href="#cite_note-60">[p]</a> </td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> UMOV r/m, r8 </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 10 /r </td> <td rowspan="4">User Move – perform data moves that can access user memory while in In-circuit emulation HALT mode. Performs same operation as <code>MOV</code> if executed when not doing in-circuit emulation.<a href="#cite_note-61">[q]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> UMOV r/m, r16/32 </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 11 /r </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> UMOV r8, r/m </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 12 /r </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> UMOV r16/32, r/m </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 13 /r </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> XBTS reg,r/m </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F A6 /r </td> <td>Bitfield extract (early 386 only).<a href="#cite_note-xbts_discon-64">[r]</a><a href="#cite_note-xbts_op-66">[s]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> IBTS r/m,reg </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F A7 /r </td> <td>Bitfield insert (early 386 only).<a href="#cite_note-xbts_discon-64">[r]</a><a href="#cite_note-xbts_op-66">[s]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> <a href="/wiki/LOADALL" title="LOADALL">LOADALL</a>D,  LOADALL386<a href="#cite_note-i386_loadall-68">[t]</a> </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"> 0F 07 </td> <td>Load all CPU registers from a 296-byte data structure starting at ES:EDI, including "hidden" part of segment descriptor registers. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-bt_offsetting-38">^ <a href="#cite_ref-bt_offsetting_38-0">a</a> <a href="#cite_ref-bt_offsetting_38-1">b</a> <a href="#cite_ref-bt_offsetting_38-2">c</a> <a href="#cite_ref-bt_offsetting_38-3">d</a> For the <code>BT</code>, <code>BTS</code>, <code>BTR</code> and <code>BTC</code> instructions: <ul><li>If the first argument to the instruction is a register operand and/or the second argument is an immediate, then the bit-index in the second argument is taken modulo operand size (16/32/64, in effect using only the bottom 4, 5 or 6 bits of the index.)</li> <li>If the first argument is a memory operand and the second argument is a register operand, then the bit-index in the second argument is used in full – it is interpreted as a signed bit-index that is used to offset the memory address to use for the bit test.</li></ul> </li> <li id="cite_note-bt_atomic-39">^ <a href="#cite_ref-bt_atomic_39-0">a</a> <a href="#cite_ref-bt_atomic_39-1">b</a> <a href="#cite_ref-bt_atomic_39-2">c</a> The <code>BTS</code>, <code>BTC</code> and <code>BTR</code> instructions accept the <code>LOCK</code> (<code>F0</code>) prefix when used with a memory argument – this results in the instruction executing atomically. </li> <li id="cite_note-40"><a href="#cite_ref-40">^</a> If the <code>F3</code> prefix is used with the <code>0F BC /r</code> opcode, then the instruction will execute as <code>TZCNT</code> on systems that support the BMI1 extension. <code>TZCNT</code> differs from <code>BSF</code> in that <code>TZCNT</code> but not <code>BSR</code> is defined to return operand size if the source operand is zero – for other source operand values, they produce the same result (except for flags). </li> <li id="cite_note-bsf_bsr_zero-41">^ <a href="#cite_ref-bsf_bsr_zero_41-0">a</a> <a href="#cite_ref-bsf_bsr_zero_41-1">b</a> <code>BSF</code> and <code>BSR</code> set the EFLAGS.ZF flag to 1 if the source argument was all-0s and 0 otherwise. If the source argument was all-0s, then the destination register is documented as being left unchanged on AMD processors, but set to an undefined value on Intel processors. </li> <li id="cite_note-42"><a href="#cite_ref-42">^</a> If the <code>F3</code> prefix is used with the <code>0F BD /r</code> opcode, then the instruction will execute as <code>LZCNT</code> on systems that support the ABM or LZCNT extensions. <code>LZCNT</code> produces a different result from <code>BSR</code> for most input values. </li> <li id="cite_note-shld_shamt-44">^ <a href="#cite_ref-shld_shamt_44-0">a</a> <a href="#cite_ref-shld_shamt_44-1">b</a> For <code>SHLD</code> and <code>SHRD</code>, the shift-amount is masked – the bottom 5 bits are used for 16/32-bit operand size and 6 bits for 64-bit operand size. <code>SHLD</code> and <code>SHRD</code> with 16-bit arguments and a shift-amount greater than 16 produce undefined results. (Actual results differ between different Intel CPUs, with at least three different behaviors known.<a href="#cite_note-43">[17]</a>) </li> <li id="cite_note-setcc_conds-45">^ <a href="#cite_ref-setcc_conds_45-0">a</a> <a href="#cite_ref-setcc_conds_45-1">b</a> The condition codes supported for the <code>SETcc</code> and <code>Jcc near</code> instructions (opcodes <code>0F 9x /0</code> and <code>0F 8x</code> respectively, with the x nibble specifying the condition) are: <table class="wikitable sortable"> <tbody><tr> <th>x</th> <th>cc</th> <th>Condition (<a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>) </th></tr> <tr> <td>0</td> <td>O</td> <td>OF=1: "Overflow" </td></tr> <tr> <td>1</td> <td>NO</td> <td>OF=0: "Not Overflow" </td></tr> <tr> <td>2</td> <td>C,B,NAE</td> <td>CF=1: "Carry", "Below", "Not Above or Equal" </td></tr> <tr> <td>3</td> <td>NC,NB,AE</td> <td>CF=0: "Not Carry", "Not Below", "Above or Equal" </td></tr> <tr> <td>4</td> <td>Z,E</td> <td>ZF=1: "Zero", "Equal" </td></tr> <tr> <td>5</td> <td>NZ,NE</td> <td>ZF=0: "Not Zero", "Not Equal" </td></tr> <tr> <td>6</td> <td>NA,BE</td> <td>(CF=1 or ZF=1): "Not Above", "Below or Equal" </td></tr> <tr> <td>7</td> <td>A,NBE</td> <td>(CF=0 and ZF=0): "Above", "Not Below or Equal" </td></tr> <tr> <td>8</td> <td>S</td> <td>SF=1: "Sign" </td></tr> <tr> <td>9</td> <td>NS</td> <td>SF=0: "Not Sign" </td></tr> <tr> <td>A</td> <td>P,PE</td> <td>PF=1: "Parity", "Parity Even" </td></tr> <tr> <td>B</td> <td>NP,PO</td> <td>PF=0: "Not Parity", "Parity Odd" </td></tr> <tr> <td>C</td> <td>L,NGE</td> <td>SF≠OF: "Less", "Not Greater Or Equal" </td></tr> <tr> <td>D</td> <td>NL,GE</td> <td>SF=OF: "Not Less", "Greater Or Equal" </td></tr> <tr> <td>E</td> <td>LE,NG</td> <td>(ZF=1 or SF≠OF): "Less or Equal", "Not Greater" </td></tr> <tr> <td>F</td> <td>NLE,G</td> <td>(ZF=0 and SF=OF): "Not Less or Equal", "Greater" </td></tr></tbody></table> </li> <li id="cite_note-46"><a href="#cite_ref-46">^</a> For <code>SETcc</code>, while the opcode is commonly specified as /0 – implying that bits 5:3 of the instruction's <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte should be 000 – modern x86 processors (Pentium and later) ignore bits 5:3 and will execute the instruction as <code>SETcc</code> regardless of the contents of these bits. </li> <li id="cite_note-47"><a href="#cite_ref-47">^</a> For <code>LFS</code>, <code>LGS</code> and <code>LSS</code>, the size of the offset part of the far pointer is given by operand size – the size of the segment part is always 16 bits. In 64-bit mode, using the <code>REX.W</code> prefix with these instructions will cause them to load a <a href="/wiki/Far_pointer" title="Far pointer">far pointer</a> with a 64-bit offset on Intel but not AMD processors. </li> <li id="cite_note-movcr_modrm-48">^ <a href="#cite_ref-movcr_modrm_48-0">a</a> <a href="#cite_ref-movcr_modrm_48-1">b</a> <a href="#cite_ref-movcr_modrm_48-2">c</a> <a href="#cite_ref-movcr_modrm_48-3">d</a> <a href="#cite_ref-movcr_modrm_48-4">e</a> <a href="#cite_ref-movcr_modrm_48-5">f</a> For <code>MOV</code> to/from the <code>CRx</code>, <code>DRx</code> and <code>TRx</code> registers, the reg part of the <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte is used to indicate <code>CRx/DRx/TRx</code> register and r/m part the general-register. Uniquely for the <code>MOV CRx/DRx/TRx</code> opcodes, the top two bits of the <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte is ignored – these opcodes are decoded and executed as if the top two bits of the ModR/M byte are <code>11b</code>. </li> <li id="cite_note-movcr_opsiz-49">^ <a href="#cite_ref-movcr_opsiz_49-0">a</a> <a href="#cite_ref-movcr_opsiz_49-1">b</a> <a href="#cite_ref-movcr_opsiz_49-2">c</a> <a href="#cite_ref-movcr_opsiz_49-3">d</a> For moves to/from the <code>CRx</code> and <code>DRx</code> registers, the operand size is always 64 bits in 64-bit mode and 32 bits otherwise. </li> <li id="cite_note-50"><a href="#cite_ref-50">^</a> On processors that support global pages (Pentium and later), global page table entries will not be flushed by a <code>MOV</code> to <code>CR3</code> − instead, these entries can be flushed by toggling the CR4.PGE bit. On processors that support <a href="/wiki/Process-context_identifier" class="mw-redirect" title="Process-context identifier">PCIDs</a>, writing to CR3 while PCIDs are enabled will only flush TLB entries belonging to the PCID specified in bits 11:0 of the value written to CR3 (this flush can be suppressed by setting bit 63 of the written value to 1). Flushing pages belonging to other PCIDs can instead be done by toggling the CR4.PGE bit, clearing the CR4.PCIDE bit, or using the <code>INVPCID</code> instruction. </li> <li id="cite_note-53"><a href="#cite_ref-53">^</a> On processors prior to <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, moves to <code>CR0</code> would not serialize the instruction stream – in part for this reason, it is usually required to perform a far jump<a href="#cite_note-51">[18]</a> immediately after a <code>MOV</code> to <code>CR0</code> if such a <code>MOV</code> is used to enable/disable <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a> and/or <a href="/wiki/Memory_paging" title="Memory paging">memory paging</a>. <code>MOV</code> to <code>CR2</code> is architecturally listed as serializing, but has been reported to be non-serializing on at least some Intel Core-i7 processors.<a href="#cite_note-52">[19]</a> <code>MOV</code> to <code>CR8</code> (introduced with x86-64) is serializing on AMD but not Intel processors. </li> <li id="cite_note-movtr_pent-54">^ <a href="#cite_ref-movtr_pent_54-0">a</a> <a href="#cite_ref-movtr_pent_54-1">b</a> The <code>MOV TRx</code> instructions were discontinued from Pentium onwards. </li> <li id="cite_note-59"><a href="#cite_ref-59">^</a> The <code>INT1</code>/<code>ICEBP</code> (<code>F1</code>) instruction is present on all known Intel x86 processors from the 80386 onwards,<a href="#cite_note-rcollins_undoc-55">[20]</a> but only fully documented for Intel processors from the May 2018 release of the Intel SDM (rev 067) onwards.<a href="#cite_note-56">[21]</a> Before this release, mention of the instruction in Intel material was sporadic, e.g. AP-526 rev 001.<a href="#cite_note-intel_ap526_001-57">[22]</a> For AMD processors, the instruction has been documented since 2002.<a href="#cite_note-58">[23]</a> </li> <li id="cite_note-60"><a href="#cite_ref-60">^</a> The operation of the <code>F1</code>(<code>ICEBP</code>) opcode differs from the operation of the regular software interrupt opcode <code>CD 01</code> in several ways:<ul>In protected mode, <code>CD 01</code> will check CPL against the interrupt descriptor's DPL field as an access-rights check, while <code>F1</code> will not.<li>In virtual-8086 mode, <code>CD 01</code> will also check CPL against IOPL as an access-rights check, while <code>F1</code> will not.</li><li>In virtual-8086 mode with VME enabled, interrupt redirection is supported for <code>CD 01</code> but not <code>F1</code>.</li></ul> </li> <li id="cite_note-61"><a href="#cite_ref-61">^</a> The UMOV instruction is present on 386 and 486 processors only.<a href="#cite_note-rcollins_undoc-55">[20]</a> </li> <li id="cite_note-xbts_discon-64">^ <a href="#cite_ref-xbts_discon_64-0">a</a> <a href="#cite_ref-xbts_discon_64-1">b</a> The <code>XBTS</code> and <code>IBTS</code> instructions were discontinued with the B1 stepping of 80386. They have been used by software mainly for detection of the buggy<a href="#cite_note-62">[24]</a> B0 stepping of the 80386. Microsoft Windows (v2.01 and later) will attempt to run the <code>XBTS</code> instruction as part of its CPU detection if <code>CPUID</code> is not present, and will refuse to boot if <code>XBTS</code> is found to be working.<a href="#cite_note-63">[25]</a> </li> <li id="cite_note-xbts_op-66">^ <a href="#cite_ref-xbts_op_66-0">a</a> <a href="#cite_ref-xbts_op_66-1">b</a> For <code>XBTS</code> and <code>IBTS</code>, the r/m argument represents the data to extract/insert a bitfield from/to, the reg argument the bitfield to be inserted/extracted, AX/EAX a bit-offset and CL a bitfield length.<a href="#cite_note-65">[26]</a> </li> <li id="cite_note-i386_loadall-68"><a href="#cite_ref-i386_loadall_68-0">^</a> Undocumented, 80386 only.<a href="#cite_note-67">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_80486">Added with <a href="/wiki/80486" class="mw-redirect" title="80486">80486</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=7" title="Edit section: Added with 80486">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction</th> <th>Opcode</th> <th>Description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a> </th></tr> <tr> <td><code>BSWAP r32</code> </td> <td><code>0F C8+r</code> </td> <td>Byte Order Swap. Usually used to convert between big-endian and little-endian data representations. For 32-bit registers, the operation performed is:<pre>r = (r << 24) | ((r << 8) & 0x00FF0000) | ((r >> 8) & 0x0000FF00) | (r >> 24);</pre> Using <code>BSWAP</code> with a 16-bit register argument produces an undefined result.<a href="#cite_note-71">[a]</a> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>CMPXCHG r/m8,r8</code> </td> <td><code>0F B0 /r</code><a href="#cite_note-i486_cmpxchg-75">[b]</a> </td> <td rowspan="2"><a href="/wiki/Compare-and-swap" title="Compare-and-swap">Compare and Exchange</a>. If accumulator (AL/AX/EAX/RAX) compares equal to first operand,<a href="#cite_note-76">[c]</a> then <code>EFLAGS.ZF</code> is set to 1 and the first operand is overwritten with the second operand. Otherwise, <code>EFLAGS.ZF</code> is set to 0, and first operand is copied into the accumulator. Instruction atomic only if used with <code>LOCK</code> prefix. </td></tr> <tr> <td><code>CMPXCHG r/m,r16</code> <code>CMPXCHG r/m,r32</code> </td> <td><code>0F B1 /r</code><a href="#cite_note-i486_cmpxchg-75">[b]</a> </td></tr> <tr> <td><code>XADD r/m,r8</code> </td> <td><code>0F C0 /r</code> </td> <td rowspan="2"><a href="/wiki/Fetch-and-add" title="Fetch-and-add">eXchange and ADD</a>. Exchanges the first operand with the second operand, then stores the sum of the two values into the destination operand. Instruction atomic only if used with <code>LOCK</code> prefix. </td></tr> <tr> <td><code>XADD r/m,r16</code> <code>XADD r/m,r32</code> </td> <td><code>0F C1 /r</code> </td></tr> <tr> <td><code>INVLPG m8</code> </td> <td><code>0F 01 /7</code> </td> <td>Invalidate the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a> entries that would be used for the 1-byte memory operand.<a href="#cite_note-77">[d]</a> Instruction is serializing. </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <td><code>INVD</code> </td> <td><code>0F 08</code> </td> <td>Invalidate Internal Caches.<a href="#cite_note-invd_scope-78">[e]</a> Modified data in the cache are not written back to memory, potentially causing data loss.<a href="#cite_note-80">[f]</a> </td></tr> <tr> <td><code>WBINVD</code> </td> <td><code>NFx 0F 09</code><a href="#cite_note-81">[g]</a> </td> <td>Write Back and Invalidate Cache.<a href="#cite_note-invd_scope-78">[e]</a> Writes back all modified cache lines in the processor's internal cache to main memory and invalidates the internal caches. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-71"><a href="#cite_ref-71">^</a> Using <code>BSWAP</code> with 16-bit registers is not disallowed per se (it will execute without producing an #UD or other exceptions) but is documented to produce undefined results – it is reported to produce various different results on 486,<a href="#cite_note-toth-19980316-69">[28]</a> 586, and <a href="/wiki/Bochs" title="Bochs">Bochs</a>/<a href="/wiki/QEMU" title="QEMU">QEMU</a>.<a href="#cite_note-coldwin-20091229-70">[29]</a> </li> <li id="cite_note-i486_cmpxchg-75">^ <a href="#cite_ref-i486_cmpxchg_75-0">a</a> <a href="#cite_ref-i486_cmpxchg_75-1">b</a> On Intel 80486 stepping A,<a href="#cite_note-72">[30]</a> the <code>CMPXCHG</code> instruction uses a different encoding - <code>0F A6 /r</code> for 8-bit variant, <code>0F A7 /r</code> for 16/32-bit variant. The <code>0F B0/B1</code> encodings are used on 80486 stepping B and later.<a href="#cite_note-73">[31]</a><a href="#cite_note-74">[32]</a> </li> <li id="cite_note-76"><a href="#cite_ref-76">^</a> The <code>CMPXCHG</code> instruction sets <code>EFLAGS</code> in the same way as a <code>CMP</code> instruction that uses the accumulator (AL/AX/EAX/RAX) as its first argument would do. </li> <li id="cite_note-77"><a href="#cite_ref-77">^</a> <code>INVLPG</code> executes as no-operation if the m8 argument is invalid (e.g. unmapped page or non-canonical address). <code>INVLPG</code> can be used to invalidate TLB entries for individual global pages. </li> <li id="cite_note-invd_scope-78">^ <a href="#cite_ref-invd_scope_78-0">a</a> <a href="#cite_ref-invd_scope_78-1">b</a> The <code>INVD</code> and <code>WBINVD</code> instructions will invalidate all cache lines in the CPU's L1 caches. It is implementation-defined whether they will invalidate L2/L3 caches as well. These instructions are serializing – on some processors, they may block interrupts until completion as well. </li> <li id="cite_note-80"><a href="#cite_ref-80">^</a> Under <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> virtualization, the <code>INVD</code> instruction will cause a mandatory #VMEXIT. Also, on processors that support <a href="/wiki/Intel_SGX" class="mw-redirect" title="Intel SGX">Intel SGX</a>, if the PRM (Processor Reserved Memory) has been set up by using the PRMRRs (PRM range registers), then the <code>INVD</code> instruction is not permitted and will cause a #GP(0) exception.<a href="#cite_note-79">[33]</a> </li> <li id="cite_note-81"><a href="#cite_ref-81">^</a> If the <code>F3</code> prefix is used with the <code>0F 09</code> opcode, then the instruction will execute as <code>WBNOINVD</code> on processors that support the WBNOINVD extension – this will not invalidate the cache. </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_in_P5/P6-class_processors">Added in <a href="/wiki/Pentium_(original)" title="Pentium (original)">P5</a>/<a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a>-class processors</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=8" title="Edit section: Added in P5/P6-class processors">edit</a>]</div> Integer/system instructions that were not present in the basic 80486 instruction set, but were added in various x86 processors prior to the introduction of SSE. (<a href="/wiki/List_of_discontinued_x86_instructions" title="List of discontinued x86 instructions">Discontinued instructions</a> are not included.) <table class="wikitable sortable"> <tbody><tr> <th>Instruction</th> <th>Opcode</th> <th>Description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>RDMSR</code> </td> <td><code>0F 32</code> </td> <td>Read <a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific register</a>. The MSR to read is specified in ECX. The value of the MSR is then returned as a 64-bit value in EDX:EAX. </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2">IBM <a href="/wiki/IBM_386SLC" title="IBM 386SLC">386SLC</a>,<a href="#cite_note-82">[34]</a> Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, AMD <a href="/wiki/AMD_K5" title="AMD K5">K5</a>, Cyrix <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">6x86MX</a>,<a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>, IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6, Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>, DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a>DX3 </td></tr> <tr> <td><code>WRMSR</code> </td> <td><code>0F 30</code> </td> <td>Write <a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific register</a>. The MSR to write is specified in ECX, and the data to write is given in EDX:EAX.<a href="#cite_note-84">[a]</a> Instruction is, with some exceptions, serializing.<a href="#cite_note-88">[b]</a> </td></tr> <tr> <td><code>RSM</code><a href="#cite_note-89">[39]</a> </td> <td><code>0F AA</code> </td> <td>Resume from <a href="/wiki/System_Management_Mode" title="System Management Mode">System Management Mode</a>. Instruction is serializing. </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">-2 (SMM) </td> <td>Intel 386SL,<a href="#cite_note-90">[40]</a><a href="#cite_note-91">[41]</a> <a href="/wiki/Intel_80486SL" class="mw-redirect" title="Intel 80486SL">486SL</a>,<a href="#cite_note-92">[c]</a> Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, AMD <a href="/wiki/AMD_5x86" class="mw-redirect" title="AMD 5x86">5x86</a>, Cyrix <a href="/wiki/Cyrix_Cx486SLC" title="Cyrix Cx486SLC">486SLC</a>/e,<a href="#cite_note-cx486slce-93">[42]</a> IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6, Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>, Rise <a href="/wiki/MP6" title="MP6">mP6</a> </td></tr> <tr> <td><code><a href="/wiki/CPUID" title="CPUID">CPUID</a></code> </td> <td><code>0F A2</code> </td> <td>CPU Identification and feature information. Takes as input a CPUID leaf index in EAX and, depending on leaf, a sub-index in ECX. Result is returned in EAX,EBX,ECX,EDX.<a href="#cite_note-96">[d]</a> Instruction is serializing, and causes a mandatory #VMEXIT under virtualization. Support for <code>CPUID</code> can be checked by toggling bit 21 of <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a> (EFLAGS.ID) – if this bit can be toggled, <code>CPUID</code> is present. </td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-100">[e]</a> </td> <td>Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>,<a href="#cite_note-cpuid_backported-101">[f]</a> AMD <a href="/wiki/AMD_5x86" class="mw-redirect" title="AMD 5x86">5x86</a>,<a href="#cite_note-cpuid_backported-101">[f]</a> Cyrix <a href="/wiki/Cyrix_5x86" title="Cyrix 5x86">5x86</a>,<a href="#cite_note-102">[g]</a> IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6, Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>, Rise <a href="/wiki/MP6" title="MP6">mP6</a>, NexGen <a href="/wiki/NexGen" title="NexGen">Nx586</a>,<a href="#cite_note-104">[h]</a> UMC <a href="/wiki/UMC_Green_CPU" title="UMC Green CPU">Green CPU</a> </td></tr> <tr> <td><code>CMPXCHG8B m64</code> </td> <td><code>0F C7 /1</code> </td> <td><a href="/wiki/Compare-and-swap" title="Compare-and-swap">Compare and Exchange</a> 8 bytes. Compares EDX:EAX with m64. If equal, set ZF<a href="#cite_note-105">[i]</a> and store ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX. Instruction atomic only if used with <code>LOCK</code> prefix.<a href="#cite_note-106">[j]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td>Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, AMD <a href="/wiki/AMD_K5" title="AMD K5">K5</a>, Cyrix <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">6x86L</a>,<a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>, IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6,<a href="#cite_note-cmpxchg8b_ntbug-108">[k]</a> Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>,<a href="#cite_note-cmpxchg8b_ntbug-108">[k]</a> Rise <a href="/wiki/MP6" title="MP6">mP6</a><a href="#cite_note-cmpxchg8b_ntbug-108">[k]</a> </td></tr> <tr> <td><code>RDTSC</code> </td> <td><code>0F 31</code> </td> <td>Read 64-bit <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> (TSC) into EDX:EAX.<a href="#cite_note-rdtsc_pmc_unordered-110">[l]</a> In early processors, the TSC was a cycle counter, incrementing by 1 for each clock cycle (which could cause its rate to vary on processors that could change clock speed at runtime) – in later processors, it increments at a fixed rate that doesn't necessarily match the CPU clock speed.<a href="#cite_note-114">[m]</a> </td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-116">[n]</a> </td> <td>Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a>, AMD <a href="/wiki/AMD_K5" title="AMD K5">K5</a>, Cyrix <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">6x86MX</a>,<a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>, IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6, Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>, Rise <a href="/wiki/MP6" title="MP6">mP6</a> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>RDPMC</code> </td> <td><code>0F 33</code> </td> <td>Read <a href="/wiki/Performance_Monitoring_Counter" class="mw-redirect" title="Performance Monitoring Counter">Performance Monitoring Counter</a>. The counter to read is specified by ECX and its value is returned in EDX:EAX.<a href="#cite_note-rdtsc_pmc_unordered-110">[l]</a> </td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-117">[o]</a> </td> <td>Intel <a href="/wiki/Pentium_(original)#MMX" title="Pentium (original)">Pentium MMX</a>, Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, AMD <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">K7</a>, Cyrix <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">6x86MX</a>, IDT <a href="/wiki/WinChip" title="WinChip">WinChip</a> C6, AMD <a href="/wiki/Geode_(processor)#Geode_LX" title="Geode (processor)">Geode LX</a>, VIA <a href="/wiki/VIA_Nano" title="VIA Nano">Nano</a><a href="#cite_note-118">[p]</a> </td></tr> <tr> <td><code>CMOVcc reg,r/m</code> </td> <td><code>0F 4x /r</code><a href="#cite_note-119">[q]</a> </td> <td>Conditional move to register. The source operand may be either register or memory.<a href="#cite_note-120">[r]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td>Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, AMD <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">K7</a>, Cyrix <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">6x86MX</a>,<a href="/wiki/MediaGX" title="MediaGX">MediaGXm</a>, Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>, VIA <a href="/wiki/VIA_C3#Nehemiah_cores" title="VIA C3">C3 "Nehemiah"</a>,<a href="#cite_note-122">[s]</a> DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a>DX3 </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>NOP r/m</code>, <code>NOPL r/m</code> </td> <td><code>NFx 0F 1F /0</code><a href="#cite_note-124">[t]</a> </td> <td>Official long <a href="/wiki/NOP_(code)" title="NOP (code)">NOP</a>. Other than AMD K7/K8, broadly unsupported in non-Intel processors released before 2005.<a href="#cite_note-125">[u]</a><a href="#cite_note-126">[57]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td>Intel <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>,<a href="#cite_note-129">[v]</a> AMD <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">K7</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a>,<a href="#cite_note-131">[w]</a> VIA <a href="/wiki/VIA_C7" title="VIA C7">C7</a><a href="#cite_note-132">[61]</a> </td></tr> <tr> <td><code>UD2</code>,<a href="#cite_note-134">[x]</a> <code>UD2A</code><a href="#cite_note-ud2_binutils-137">[y]</a> </td> <td><code>0F 0B</code> </td> <td rowspan="3">Undefined Instructions – will generate an <a href="/wiki/Illegal_opcode" title="Illegal opcode">invalid opcode</a> (#UD) exception in all operating modes.<a href="#cite_note-139">[z]</a> These instructions are provided for software testing to explicitly generate invalid opcodes. The opcodes for these instructions are reserved for this purpose. </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">(3) </td> <td rowspan="2">(<a href="/wiki/Intel_80186" title="Intel 80186">80186</a>),<a href="#cite_note-ud_186-140">[aa]</a> Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a><a href="#cite_note-141">[66]</a> </td></tr> <tr> <td><code>UD1 reg,r/m</code>,<a href="#cite_note-144">[ab]</a> <code>UD2B reg,r/m</code><a href="#cite_note-ud2_binutils-137">[y]</a> </td> <td><code>0F B9 /r</code><a href="#cite_note-ud01_modrm-147">[ac]</a> </td></tr> <tr> <td><code>OIO</code>, <code>UD0</code>, <code>UD0 reg,r/m</code><a href="#cite_note-150">[ad]</a> </td> <td><code>0F FF</code>, <code>0F FF /r</code><a href="#cite_note-ud01_modrm-147">[ac]</a> </td> <td>(<a href="/wiki/Intel_80186" title="Intel 80186">80186</a>),<a href="#cite_note-ud_186-140">[aa]</a> <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a>,<a href="#cite_note-cyrix_oio-148">[71]</a> <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a><a href="#cite_note-151">[73]</a> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>SYSCALL</code> </td> <td><code>0F 05</code> </td> <td>Fast <a href="/wiki/System_call" title="System call">System call</a>. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2">AMD <a href="/wiki/AMD_K6" title="AMD K6">K6</a>,<a href="#cite_note-153">[ae]</a> <a href="/wiki/X86-64" title="X86-64">x86-64</a><a href="#cite_note-154">[af]</a><a href="#cite_note-156">[ag]</a> </td></tr> <tr> <td><code>SYSRET</code> </td> <td><code>0F 07</code><a href="#cite_note-sysret_64bit-157">[ah]</a> </td> <td>Fast Return from System Call. Designed to be used together with <code>SYSCALL</code>. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0<a href="#cite_note-syscall_realmode-158">[ai]</a> </td></tr> <tr> <td><code>SYSENTER</code> </td> <td><code>0F 34</code> </td> <td>Fast <a href="/wiki/System_call" title="System call">System call</a>. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3<a href="#cite_note-syscall_realmode-158">[ai]</a> </td> <td rowspan="2">Intel <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>,<a href="#cite_note-161">[aj]</a> AMD <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">K7</a>,<a href="#cite_note-162">[78]</a><a href="#cite_note-163">[ak]</a> Transmeta <a href="/wiki/Transmeta_Crusoe" title="Transmeta Crusoe">Crusoe</a>,<a href="#cite_note-165">[al]</a> NatSemi <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode GX2</a>, VIA <a href="/wiki/VIA_C3#Nehemiah_cores" title="VIA C3">C3 "Nehemiah"</a>,<a href="#cite_note-167">[am]</a> DM&P <a href="/wiki/Vortex86" title="Vortex86">Vortex86</a>DX3 </td></tr> <tr> <td><code>SYSEXIT</code> </td> <td><code>0F 35</code><a href="#cite_note-sysret_64bit-157">[ah]</a> </td> <td>Fast Return from System Call. Designed to be used together with <code>SYSENTER</code>. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0<a href="#cite_note-syscall_realmode-158">[ai]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-84"><a href="#cite_ref-84">^</a> On Intel and AMD CPUs, the <code>WRMSR</code> instruction is also used to update the <a href="/wiki/Intel_Microcode#Update_facility" class="mw-redirect" title="Intel Microcode">CPU microcode</a>. This is done by writing the virtual address of the new microcode to upload to MSR <code>79h</code> on Intel CPUs and MSR <code>C001_0020h</code><a href="#cite_note-83">[35]</a> on AMD CPUs. </li> <li id="cite_note-88"><a href="#cite_ref-88">^</a> Writes to the following MSRs are not serializing:<a href="#cite_note-85">[36]</a><a href="#cite_note-86">[37]</a> <table class="wikitable sortable"> <tbody><tr> <th>Number</th> <th>Name </th></tr> <tr> <td><code>48h</code></td> <td>SPEC_CTRL </td></tr> <tr> <td><code>49h</code></td> <td>PRED_CMD </td></tr> <tr> <td><code>10Bh</code></td> <td>FLUSH_CMD </td></tr> <tr> <td><code>122h</code></td> <td>TSX_CTRL </td></tr> <tr> <td><code>6E0h</code></td> <td>TSC_DEADLINE </td></tr> <tr> <td><code>6E1h</code></td> <td>PKRS </td></tr> <tr> <td><code>774h</code></td> <td>HWP_REQUEST (non-serializing only if the FAST_IA32_HWP_REQUEST bit it set) </td></tr> <tr> <td><code>802h</code> to <code>83Fh</code></td> <td>(x2APIC MSRs) </td></tr> <tr> <td><code>1B01h</code></td> <td>UARCH_MISC_CTL </td></tr> <tr> <td><code>C001_0100h</code></td> <td>FS_BASE (non-serializing on AMD <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> and later)<a href="#cite_note-amd_56713_p116-87">[38]</a> </td></tr> <tr> <td><code>C001_0101h</code></td> <td>GS_BASE (<a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> and later) </td></tr> <tr> <td><code>C001_0102h</code></td> <td>KernelGSbase (<a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> and later) </td></tr> <tr> <td><code>C001_011Bh</code></td> <td>Doorbell Register (AMD-specific) </td></tr></tbody></table> </li> <li id="cite_note-92"><a href="#cite_ref-92">^</a> <a href="/wiki/System_Management_Mode" title="System Management Mode">System Management Mode</a> and the <code>RSM</code> instruction were made available on non-SL variants of the Intel 486 only after the initial release of the Intel Pentium in 1993. </li> <li id="cite_note-96"><a href="#cite_ref-96">^</a> On some older 32-bit processors, executing <code>CPUID</code> with a leaf index (EAX) greater than 0 may leave EBX and ECX unmodified, keeping their old values. For this reason, it is recommended to zero out EBX and ECX before executing <code>CPUID</code>. Processors noted to exhibit this behavior include Cyrix MII<a href="#cite_note-94">[43]</a> and IDT WinChip 2.<a href="#cite_note-95">[44]</a> In 64-bit mode, <code>CPUID</code> will set the top 32 bits of RAX, RBX, RCX and RDX to zero. </li> <li id="cite_note-100"><a href="#cite_ref-100">^</a> On some Intel processors starting from <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a>, there exists MSRs that can be used to restrict <code>CPUID</code> to ring 0. Such MSRs are documented for at least Ivy Bridge<a href="#cite_note-97">[45]</a> and Denverton.<a href="#cite_note-98">[46]</a> The ability to restrict <code>CPUID</code> to ring 0 also exists on AMD processors supporting the "CpuidUserDis" feature (<a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> "Raphael" and later).<a href="#cite_note-99">[47]</a> </li> <li id="cite_note-cpuid_backported-101">^ <a href="#cite_ref-cpuid_backported_101-0">a</a> <a href="#cite_ref-cpuid_backported_101-1">b</a> <code>CPUID</code> is also available on some Intel and AMD 486 processor variants that were released after the initial release of the Intel Pentium. </li> <li id="cite_note-102"><a href="#cite_ref-102">^</a> On the Cyrix 5x86 and 6x86 CPUs, <code>CPUID</code> is not enabled by default and must be enabled through a Cyrix configuration register. </li> <li id="cite_note-104"><a href="#cite_ref-104">^</a> On NexGen CPUs, <code>CPUID</code> is only supported with some system BIOSes. On some NexGen CPUs that do support <code>CPUID</code>, EFLAGS.ID is not supported but EFLAGS.AC is, complicating CPU detection.<a href="#cite_note-103">[48]</a> </li> <li id="cite_note-105"><a href="#cite_ref-105">^</a> Unlike the older <code>CMPXCHG</code> instruction, the <code>CMPXCHG8B</code> instruction does not modify any <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a> bits other than ZF. </li> <li id="cite_note-106"><a href="#cite_ref-106">^</a> <code>LOCK CMPXCHG8B</code> with a register operand (which is an invalid encoding) will, on some Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> CPUs, cause a <a href="/wiki/Halt_and_Catch_Fire_(computing)" title="Halt and Catch Fire (computing)">hang</a> rather than the expected #UD exception - this is known as the <a href="/wiki/Pentium_F00F_bug" title="Pentium F00F bug">Pentium F00F bug</a>. </li> <li id="cite_note-cmpxchg8b_ntbug-108">^ <a href="#cite_ref-cmpxchg8b_ntbug_108-0">a</a> <a href="#cite_ref-cmpxchg8b_ntbug_108-1">b</a> <a href="#cite_ref-cmpxchg8b_ntbug_108-2">c</a> On IDT WinChip, Transmeta Crusoe and Rise mP6 processors, the <code>CMPXCHG8B</code> instruction is always supported, however its CPUID bit may be missing. This is a workaround for a bug in Windows NT.<a href="#cite_note-107">[49]</a> </li> <li id="cite_note-rdtsc_pmc_unordered-110">^ <a href="#cite_ref-rdtsc_pmc_unordered_110-0">a</a> <a href="#cite_ref-rdtsc_pmc_unordered_110-1">b</a> The <code>RDTSC</code> and <code>RDPMC</code> instructions are not ordered with respect to other instructions, and may sample their respective counters before earlier instructions are executed or after later instructions have executed. Invocations of <code>RDPMC</code> (but not <code>RDTSC</code>) may be reordered relative to each other even for reads of the same counter. In order to impose ordering with respect to other instructions, <code>LFENCE</code> or serializing instructions (e.g. <code>CPUID</code>) are needed.<a href="#cite_note-rdtsc_ordering-109">[50]</a> </li> <li id="cite_note-114"><a href="#cite_ref-114">^</a> Fixed-rate TSC was introduced in two stages:<style data-mw-deduplicate="TemplateStyles:r1228772891">.mw-parser-output .glossary dt{margin-top:0.4em}.mw-parser-output .glossary dt+dt{margin-top:-0.2em}.mw-parser-output .glossary .templatequote{margin-top:0;margin-bottom:-0.5em}</style> <dl class="glossary"><dt id="constant_tsc"><dfn>Constant TSC</dfn></dt><dd>TSC running at a fixed rate as long as the processor core is not in a deep-sleep (<a href="/wiki/ACPI#Power_states" title="ACPI">C2</a> or deeper) mode, but not synchronized between CPU cores. Introduced in Intel <a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Prescott</a>, <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a> and <a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>. Also present in all <a href="/wiki/Transmeta" title="Transmeta">Transmeta</a> and <a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a><a href="#cite_note-111">[51]</a> CPUs. Does not have a CPUID bit.</dd><dt id="invariant_tsc"><dfn>Invariant TSC</dfn></dt><dd>TSC running at a fixed rate, and remaining synchronized between CPU cores in all <a href="/wiki/ACPI#Power_states" title="ACPI">P-,C- and T-states</a> (but not necessarily S-states). Present in <a href="/wiki/AMD_K10" class="mw-redirect" title="AMD K10">AMD K10</a> and later; Intel <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>/<a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a><a href="#cite_note-112">[52]</a> and later; <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> WuDaoKou<a href="#cite_note-113">[53]</a> and later. Indicated with a CPUID bit (leaf <code>8000_0007:EDX[8]</code>).</dd> </dl></li> <li id="cite_note-116"><a href="#cite_ref-116">^</a> <code>RDTSC</code> can be run outside Ring 0 only if <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.TSD</a>=0</code>. On Intel Pentium and AMD K5, <code>RDTSC</code> cannot be run in Virtual-8086 mode.<a href="#cite_note-115">[54]</a> Later processors removed this restriction. </li> <li id="cite_note-117"><a href="#cite_ref-117">^</a> <code>RDPMC</code> can be run outside Ring 0 only if <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.PCE</a>=1</code>. </li> <li id="cite_note-118"><a href="#cite_ref-118">^</a> The <code>RDPMC</code> instruction is not present in VIA processors prior to the Nano. </li> <li id="cite_note-119"><a href="#cite_ref-119">^</a> The condition codes supported for <code>CMOVcc</code> instruction (opcode <code>0F 4x /r</code>, with the x nibble specifying the condition) are: <table class="wikitable sortable"> <tbody><tr> <th>x</th> <th>cc</th> <th>Condition (<a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>) </th></tr> <tr> <td>0</td> <td>O</td> <td>OF=1: "Overflow" </td></tr> <tr> <td>1</td> <td>NO</td> <td>OF=0: "Not Overflow" </td></tr> <tr> <td>2</td> <td>C,B,NAE</td> <td>CF=1: "Carry", "Below", "Not Above or Equal" </td></tr> <tr> <td>3</td> <td>NC,NB,AE</td> <td>CF=0: "Not Carry", "Not Below", "Above or Equal" </td></tr> <tr> <td>4</td> <td>Z,E</td> <td>ZF=1: "Zero", "Equal" </td></tr> <tr> <td>5</td> <td>NZ,NE</td> <td>ZF=0: "Not Zero", "Not Equal" </td></tr> <tr> <td>6</td> <td>NA,BE</td> <td>(CF=1 or ZF=1): "Not Above", "Below or Equal" </td></tr> <tr> <td>7</td> <td>A,NBE</td> <td>(CF=0 and ZF=0): "Above", "Not Below or Equal" </td></tr> <tr> <td>8</td> <td>S</td> <td>SF=1: "Sign" </td></tr> <tr> <td>9</td> <td>NS</td> <td>SF=0: "Not Sign" </td></tr> <tr> <td>A</td> <td>P,PE</td> <td>PF=1: "Parity", "Parity Even" </td></tr> <tr> <td>B</td> <td>NP,PO</td> <td>PF=0: "Not Parity", "Parity Odd" </td></tr> <tr> <td>C</td> <td>L,NGE</td> <td>SF≠OF: "Less", "Not Greater Or Equal" </td></tr> <tr> <td>D</td> <td>NL,GE</td> <td>SF=OF: "Not Less", "Greater Or Equal" </td></tr> <tr> <td>E</td> <td>LE,NG</td> <td>(ZF=1 or SF≠OF): "Less or Equal", "Not Greater" </td></tr> <tr> <td>F</td> <td>NLE,G</td> <td>(ZF=0 and SF=OF): "Not Less or Equal", "Greater" </td></tr></tbody></table> </li> <li id="cite_note-120"><a href="#cite_ref-120">^</a> In 64-bit mode, <code>CMOVcc</code> with a 32-bit operand size will clear the upper 32 bits of the destination register even if the condition is false. For <code>CMOVcc</code> with a memory source operand, the CPU will always read the operand from memory – potentially causing memory exceptions and cache line-fills – even if the condition for the move is not satisfied. (The Intel <a href="/wiki/X86#APX_(Advanced_Performance_Extensions)" title="X86">APX</a> extension defines a set of new <a href="/wiki/EVEX_prefix" title="EVEX prefix">EVEX</a>-encoded variants of <code>CMOVcc</code> that will suppress memory exceptions if the condition is false.) </li> <li id="cite_note-122"><a href="#cite_ref-122">^</a> On pre-Nehemiah VIA C3 variants ("Samuel"/"Ezra"), the <code>reg,reg</code> but not <code>reg,[mem]</code> forms of the <code>CMOVcc</code> instructions have been reported to be present as undocumented instructions.<a href="#cite_note-121">[55]</a> </li> <li id="cite_note-124"><a href="#cite_ref-124">^</a> Intel's recommended byte encodings for multi-byte NOPs of lengths 2 to 9 bytes in 32/64-bit mode are (in hex):<a href="#cite_note-123">[56]</a> <table class="wikitable sortable"> <tbody><tr> <th>Length</th> <th>Byte Sequence </th></tr> <tr> <td>2</td> <td><code>66 90</code> </td></tr> <tr> <td>3</td> <td><code>0F 1F 00</code> </td></tr> <tr> <td>4</td> <td><code>0F 1F 40 00</code> </td></tr> <tr> <td>5</td> <td><code>0F 1F 44 00 00</code> </td></tr> <tr> <td>6</td> <td><code>66 0F 1F 44 00 00</code> </td></tr> <tr> <td>7</td> <td><code>0F 1F 80 00 00 00 00</code> </td></tr> <tr> <td>8</td> <td><code>0F 1F 84 00 00 00 00 00</code> </td></tr> <tr> <td>9</td> <td><code>66 0F 1F 84 00 00 00 00 00</code> </td></tr></tbody></table> For cases where there is a need to use more than 9 bytes of NOP padding, it is recommended to use multiple NOPs. </li> <li id="cite_note-125"><a href="#cite_ref-125">^</a> Unlike other instructions added in <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, long NOP does not have a <a href="/wiki/CPUID" title="CPUID">CPUID</a> feature bit. </li> <li id="cite_note-129"><a href="#cite_ref-129">^</a> <code>0F 1F /0</code> as long-NOP was introduced in the Pentium Pro, but remained undocumented until 2006.<a href="#cite_note-longnop2006-127">[58]</a> The whole <code>0F 18..1F</code> opcode range was <code>NOP</code> in Pentium Pro. However, except for <code>0F 1F /0</code>, Intel does not guarantee that these opcodes will remain <code>NOP</code> in future processors, and have indeed assigned some of these opcodes to other instructions in at least some processors.<a href="#cite_note-128">[59]</a> </li> <li id="cite_note-131"><a href="#cite_ref-131">^</a> Documented for AMD x86-64 since 2002.<a href="#cite_note-130">[60]</a> </li> <li id="cite_note-134"><a href="#cite_ref-134">^</a> While the <code>0F 0B</code> opcode was officially reserved as an invalid opcode from Pentium onwards, it only got assigned the mnemonic <code>UD2</code> from <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> onwards.<a href="#cite_note-133">[62]</a> </li> <li id="cite_note-ud2_binutils-137">^ <a href="#cite_ref-ud2_binutils_137-0">a</a> <a href="#cite_ref-ud2_binutils_137-1">b</a> <a href="/wiki/GNU_Binutils" title="GNU Binutils">GNU Binutils</a> have used the <code>UD2A</code> and <code>UD2B</code> mnemonics for the <code>0F 0B</code> and <code>0F B9</code> opcodes since version 2.7.<a href="#cite_note-135">[63]</a> Neither <code>UD2A</code> nor <code>UD2B</code> originally took any arguments - <code>UD2B</code> was later modified to accept a <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte, in Binutils version 2.30.<a href="#cite_note-136">[64]</a> </li> <li id="cite_note-139"><a href="#cite_ref-139">^</a> The <code>UD2</code> (<code>0F 0B</code>) instruction will additionally stop subsequent bytes from being decoded as instructions, even speculatively. For this reason, if an indirect branch instruction is followed by something that is not code, it is recommended to place an <code>UD2</code> instruction after the indirect branch.<a href="#cite_note-138">[65]</a> </li> <li id="cite_note-ud_186-140">^ <a href="#cite_ref-ud_186_140-0">a</a> <a href="#cite_ref-ud_186_140-1">b</a> The UD0/1/2 opcodes - <code>0F 0B</code>, <code>0F B9</code> and <code>0F FF</code> - will cause an #UD exception on all x86 processors from the <a href="/wiki/Intel_80186" title="Intel 80186">80186</a> onwards (except <a href="/wiki/NEC_V20" title="NEC V20">NEC V-series</a> processors), but did not get explicitly reserved for this purpose until P5-class processors. </li> <li id="cite_note-144"><a href="#cite_ref-144">^</a> While the <code>0F B9</code> opcode was officially reserved as an invalid opcode from Pentium onwards, it only got assigned its mnemonic <code>UD1</code> much later – AMD APM started listing <code>UD1</code> in its opcode maps from rev 3.17 onwards,<a href="#cite_note-amd_ud0_ud1-142">[67]</a> while Intel SDM started listing it from rev 061 onwards.<a href="#cite_note-intel_ud0_ud1-143">[68]</a> </li> <li id="cite_note-ud01_modrm-147">^ <a href="#cite_ref-ud01_modrm_147-0">a</a> <a href="#cite_ref-ud01_modrm_147-1">b</a> For both the <code>0F B9</code> and <code>0F FF</code> opcodes, different x86 implementations are known to differ regarding whether the opcodes accept a <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte.<a href="#cite_note-145">[69]</a><a href="#cite_note-146">[70]</a> </li> <li id="cite_note-150"><a href="#cite_ref-150">^</a> For the <code>0F FF</code> opcode, the <code>OIO</code> mnemonic was introduced by Cyrix,<a href="#cite_note-cyrix_oio-148">[71]</a> while the <code>UD0</code> menmonic (without arguments) was introduced by AMD and Intel at the same time as the <code>UD1</code> mnemonic for <code>0F B9</code>.<a href="#cite_note-amd_ud0_ud1-142">[67]</a><a href="#cite_note-intel_ud0_ud1-143">[68]</a> Later Intel (but not AMD) documentation modified its description of <code>UD0</code> to add a <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte and take two arguments.<a href="#cite_note-149">[72]</a> </li> <li id="cite_note-153"><a href="#cite_ref-153">^</a> On K6, the <code>SYSCALL</code>/<code>SYSRET</code> instructions were available on Model 7 (250nm "Little Foot") and later, not on the earlier Model 6.<a href="#cite_note-152">[74]</a> </li> <li id="cite_note-154"><a href="#cite_ref-154">^</a> <code>SYSCALL</code> and <code>SYSRET</code> were made an integral part of x86-64 – as a result, the instructions are available in 64-bit mode on all x86-64 processors from AMD, Intel, VIA and Zhaoxin. Outside 64-bit mode, the instructions are available on AMD processors only. </li> <li id="cite_note-156"><a href="#cite_ref-156">^</a> The exact semantics of <code>SYSRET</code> differs slightly between AMD and Intel processors: non-canonical return addresses cause a #GP exception to be thrown in Ring 3 on AMD CPUs but Ring 0 on Intel CPUs. This has been known to cause security issues.<a href="#cite_note-155">[75]</a> </li> <li id="cite_note-sysret_64bit-157">^ <a href="#cite_ref-sysret_64bit_157-0">a</a> <a href="#cite_ref-sysret_64bit_157-1">b</a> For the <code>SYSRET</code> and <code>SYSEXIT</code> instructions under x86-64, it is necessary to add the <code>REX.W</code> prefix for variants that will return to 64-bit user-mode code. Encodings of these instructions without the <code>REX.W</code> prefix are used to return to 32-bit user-mode code. (Neither of these instructions can be used to return to 16-bit user-mode code.) </li> <li id="cite_note-syscall_realmode-158">^ <a href="#cite_ref-syscall_realmode_158-0">a</a> <a href="#cite_ref-syscall_realmode_158-1">b</a> <a href="#cite_ref-syscall_realmode_158-2">c</a> The <code>SYSRET</code>, <code>SYSENTER</code> and <code>SYSEXIT</code> instructions are unavailable in <a href="/wiki/Real_mode" title="Real mode">Real mode</a>. (<code>SYSENTER</code> is, however, available in <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a>.) </li> <li id="cite_note-161"><a href="#cite_ref-161">^</a> The <code>CPUID</code> flags that indicate support for <code>SYSENTER</code>/<code>SYSEXIT</code> are set on the Pentium Pro, even though the processor does not officially support these instructions.<a href="#cite_note-159">[76]</a> Third party testing indicates that the opcodes are present on the Pentium Pro but too buggy to be usable.<a href="#cite_note-160">[77]</a> </li> <li id="cite_note-163"><a href="#cite_ref-163">^</a> On AMD CPUs, the <code>SYSENTER</code> and <code>SYSEXIT</code> instructions are not available in x86-64 <a href="/wiki/Long_mode" title="Long mode">long mode</a> (#UD). </li> <li id="cite_note-165"><a href="#cite_ref-165">^</a> On Transmeta CPUs, the <code>SYSENTER</code> and <code>SYSEXIT</code> instructions are only available with version 4.2 or higher of the Transmeta Code Morphing software.<a href="#cite_note-164">[79]</a> </li> <li id="cite_note-167"><a href="#cite_ref-167">^</a> On Nehemiah, <code>SYSENTER</code> and <code>SYSEXIT</code> are available only on stepping 8 and later.<a href="#cite_note-166">[80]</a> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Added_as_instruction_set_extensions">Added as instruction set extensions</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=9" title="Edit section: Added as instruction set extensions">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Added_with_x86-64">Added with <a href="/wiki/X86-64" title="X86-64">x86-64</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=10" title="Edit section: Added with x86-64">edit</a>]</div> These instructions can only be encoded in 64 bit mode. They fall in four groups: <ul><li>original instructions that reuse existing opcodes for a different purpose (<code>MOVSXD</code> replacing <code>ARPL</code>)</li> <li>original instructions with new opcodes (<code>SWAPGS</code>)</li> <li>existing instructions extended to a 64 bit address size (<code>JRCXZ</code>)</li> <li>existing instructions extended to a 64 bit operand size (remaining instructions)</li></ul> Most instructions with a 64 bit operand size encode this using a <code>REX.W</code> prefix; in the absence of the <code>REX.W</code> prefix, the corresponding instruction with 32 bit operand size is encoded. This mechanism also applies to most other instructions with 32 bit operand size. These are not listed here as they do not gain a new mnemonic in Intel syntax when used with a 64 bit operand size. <table class="wikitable sortable"> <tbody><tr> <th>Instruction</th> <th>Encoding</th> <th>Meaning</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a> </th></tr> <tr> <td><code>CDQE</code> </td> <td><code>REX.W 98</code> </td> <td>Sign extend EAX into RAX </td> <td rowspan="13" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td></tr> <tr> <td><code>CQO</code> </td> <td><code>REX.W 99</code> </td> <td>Sign extend RAX into RDX:RAX </td></tr> <tr> <td><code>CMPSQ</code> </td> <td><code>REX.W A7</code> </td> <td>CoMPare String Quadword </td></tr> <tr> <td><code>CMPXCHG16B m128</code><a href="#cite_note-168">[a]</a><a href="#cite_note-172">[b]</a> </td> <td><code>REX.W 0F C7 /1</code> </td> <td>CoMPare and eXCHanGe 16 Bytes. Atomic only if used with LOCK prefix. </td></tr> <tr> <td><code>IRETQ</code> </td> <td><code>REX.W CF</code> </td> <td>64-bit Return from Interrupt </td></tr> <tr> <td><code>JRCXZ rel8</code> </td> <td><code>E3 cb</code> </td> <td>Jump if RCX is zero </td></tr> <tr> <td><code>LODSQ</code> </td> <td><code>REX.W AD</code> </td> <td>LoaD String Quadword </td></tr> <tr> <td><code>MOVSXD r64,r/m32</code> </td> <td><code>REX.W 63 /r</code><a href="#cite_note-174">[c]</a> </td> <td>MOV with Sign Extend 32-bit to 64-bit </td></tr> <tr> <td><code>MOVSQ</code> </td> <td><code>REX.W A5</code> </td> <td>Move String Quadword </td></tr> <tr> <td><code>POPFQ</code> </td> <td><code>9D</code> </td> <td>POP RFLAGS Register </td></tr> <tr> <td><code>PUSHFQ</code> </td> <td><code>9C</code> </td> <td>PUSH RFLAGS Register </td></tr> <tr> <td><code>SCASQ</code> </td> <td><code>REX.W AF</code> </td> <td>SCAn String Quadword </td></tr> <tr> <td><code>STOSQ</code> </td> <td><code>REX.W AB</code> </td> <td>STOre String Quadword </td></tr> <tr> <td><code>SWAPGS</code> </td> <td><code>0F 01 F8</code> </td> <td>Exchange GS base with KernelGSBase MSR </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-168"><a href="#cite_ref-168">^</a> The memory operand to <code>CMPXCHG16B</code> must be 16-byte aligned. </li> <li id="cite_note-172"><a href="#cite_ref-172">^</a> The <code>CMPXCHG16B</code> instruction was absent from a few of the earliest Intel/AMD x86-64 processors. On Intel processors, the instruction was missing from <a href="/wiki/List_of_Intel_Xeon_processors_(NetBurst-based)#"Nocona"_(90_nm)" title="List of Intel Xeon processors (NetBurst-based)">Xeon "Nocona"</a> stepping D,<a href="#cite_note-169">[81]</a> but added in stepping E.<a href="#cite_note-170">[82]</a> On <a href="/wiki/AMD_K8" title="AMD K8">AMD K8</a> family processors, it was added in stepping F, at the same time as DDR2 support was introduced.<a href="#cite_note-171">[83]</a> For this reason, <code>CMPXCHG16B</code> has its own CPUID flag, separate from the rest of x86-64. </li> <li id="cite_note-174"><a href="#cite_ref-174">^</a> Encodings of <code>MOVSXD</code> without REX.W prefix are permitted but discouraged<a href="#cite_note-173">[84]</a> – such encodings behave identically to 16/32-bit <code>MOV</code> (<code>8B /r</code>). </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Bit_manipulation_extensions">Bit manipulation extensions</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=11" title="Edit section: Bit manipulation extensions">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X86_Bit_manipulation_instruction_set" title="X86 Bit manipulation instruction set">X86 Bit manipulation instruction set</a></div> Bit manipulation instructions. For all of the <a href="/wiki/VEX_prefix" title="VEX prefix">VEX-encoded</a> instructions defined by BMI1 and BMI2, the operand size may be 32 or 64 bits, controlled by the VEX.W bit – none of these instructions are available in 16-bit variants. <table class="wikitable sortable"> <tbody><tr> <th>Bit Manipulation Extension</th> <th>Instruction mnemonics</th> <th>Opcode</th> <th>Instruction description</th> <th>Added in </th></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="abm_(lzcnt)'`UNIQ--ref-00000268-QINU`'"><dfn><a href="/wiki/Advanced_Bit_Manipulation" class="mw-redirect" title="Advanced Bit Manipulation">ABM</a> (LZCNT)<a href="#cite_note-175">[a]</a></dfn></dt><dd>Advanced Bit Manipulation</dd></dl> </td> <td><code>POPCNT r16,r/m16</code> <code>POPCNT r32,r/m32</code> </td> <td><code>F3 0F B8 /r</code> </td> <td rowspan="2"><a href="/wiki/Hamming_weight" title="Hamming weight">Population Count</a>. Counts the number of bits that are set to 1 in its source argument. </td> <td rowspan="4"><a href="/wiki/AMD_K10" class="mw-redirect" title="AMD K10">K10</a>, <a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat</a>, <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> </td></tr> <tr> <td><code>POPCNT r64,r/m64</code> </td> <td><code>F3 REX.W 0F B8 /r</code> </td></tr> <tr> <td><code>LZCNT r16,r/m16</code> <code>LZCNT r32,r/m32</code> </td> <td><code>F3 0F BD /r</code> </td> <td rowspan="2">Count Leading zeroes.<a href="#cite_note-176">[b]</a> If source operand is all-0s, then <code>LZCNT</code> will return operand size in bits (16/32/64) and set CF=1. </td></tr> <tr> <td><code>LZCNT r64,r/m64</code> </td> <td><code>F3 REX.W 0F BD /r</code> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="7"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="bmi1"><dfn>BMI1</dfn></dt><dd>Bit Manipulation Instruction Set 1</dd></dl> </td> <td><code>TZCNT r16,r/m16</code> <code>TZCNT r32,r/m32</code> </td> <td><code>F3 0F BC /r</code> </td> <td rowspan="2">Count Trailing zeroes.<a href="#cite_note-177">[c]</a> If source operand is all-0s, then <code>TZCNT</code> will return operand size in bits (16/32/64) and set CF=1. </td> <td rowspan="7"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a>, <a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> </td></tr> <tr> <td><code>TZCNT r64,r/m64</code> </td> <td><code>F3 REX.W 0F BC /r</code> </td></tr> <tr> <td><code>ANDN ra,rb,r/m</code> </td> <td><code>VEX.LZ.0F38 F2 /r</code> </td> <td>Bitwise AND-NOT: <code>ra = r/m AND NOT(rb)</code> </td></tr> <tr> <td><code>BEXTR ra,r/m,rb</code> </td> <td><code>VEX.LZ.0F38 F7 /r</code> </td> <td>Bitfield extract. Bitfield start position is specified in bits [7:0] of <code>rb</code>, length in bits[15:8] of <code>rb</code>. The bitfield is then extracted from the <code>r/m</code> value with zero-extension, then stored in <code>ra</code>. Equivalent to<a href="#cite_note-178">[d]</a><pre>mask = (1 << rb[15:8]) - 1 ra = (r/m >> rb[7:0]) AND mask</pre> </td></tr> <tr> <td><code>BLSI reg,r/m</code> </td> <td><code>VEX.LZ.0F38 F3 /3</code> </td> <td>Extract lowest set bit in source argument. Returns 0 if source argument is 0. Equivalent to <code>dst = (-src) AND src</code> </td></tr> <tr> <td><code>BLSMSK reg,r/m</code> </td> <td><code>VEX.LZ.0F38 F3 /2</code> </td> <td>Generate a bitmask of all-1s bits up to the lowest bit position with a 1 in the source argument. Returns all-1s if source argument is 0. Equivalent to <code>dst = (src-1) XOR src</code> </td></tr> <tr> <td><code>BLSR reg,r/m</code> </td> <td><code>VEX.LZ.0F38 F3 /1</code> </td> <td>Copy all bits of the source argument, then clear the lowest set bit. Equivalent to <code>dst = (src-1) AND src</code> </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="8"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="bmi2"><dfn>BMI2</dfn></dt><dd>Bit Manipulation Instruction Set 2</dd></dl> </td> <td><code>BZHI ra,r/m,rb</code> </td> <td><code>VEX.LZ.0F38 F5 /r</code> </td> <td>Zero out high-order bits in <code>r/m</code> starting from the bit position specified in <code>rb</code>, then write result to <code>rd</code>. Equivalent to <code>ra = r/m AND NOT(-1 << rb[7:0])</code> </td> <td rowspan="8"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a>,<a href="#cite_note-182">[e]</a> <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> </td></tr> <tr> <td><code>MULX ra,rb,r/m</code> </td> <td><code>VEX.LZ.F2.0F38 F6 /r</code> </td> <td>Widening unsigned integer multiply without setting flags. Multiplies EDX/RDX with <code>r/m</code>, then stores the low half of the multiplication result in <code>ra</code> and the high half in <code>rb</code>. If <code>ra</code> and <code>rb</code> specify the same register, only the high half of the result is stored. </td></tr> <tr> <td><code>PDEP ra,rb,r/m</code> </td> <td><code>VEX.LZ.F2.0F38 F5 /r</code> </td> <td>Parallel Bit Deposit. Scatters contiguous bits from <code>rb</code> to the bit positions set in <code>r/m</code>, then stores result to <code>ra</code>. Operation performed is:<pre>ra=0; k=0; mask=r/m for i=0 to opsize-1 do if (mask[i] == 1) then ra[i]=rb[k]; k=k+1</pre> </td></tr> <tr> <td><code>PEXT ra,rb,r/m</code> </td> <td><code>VEX.LZ.F3.0F38 F5 /r</code> </td> <td>Parallel Bit Extract. Uses <code>r/m</code> argument as a bit mask to select bits in <code>rb</code>, then compacts the selected bits into a contiguous bit-vector. Operation performed is:<pre>ra=0; k=0; mask=r/m for i=0 to opsize-1 do if (mask[i] == 1) then ra[k]=rb[i]; k=k+1</pre> </td></tr> <tr> <td><code>RORX reg,r/m,imm8</code> </td> <td><code>VEX.LZ.F2.0F3A F0 /r ib</code> </td> <td>Rotate right by immediate without affecting flags. </td></tr> <tr> <td><code>SARX ra,r/m,rb</code> </td> <td><code>VEX.LZ.F3.0F38 F7 /r</code> </td> <td>Arithmetic shift right without updating flags. For <code>SARX</code>, <code>SHRX</code> and <code>SHLX</code>, the shift-amount specified in <code>rb</code> is masked to 5 bits for 32-bit operand size and 6 bits for 64-bit operand size. </td></tr> <tr> <td><code>SHRX ra,r/m,rb</code> </td> <td><code>VEX.LZ.F2.0F38 F7 /r</code> </td> <td>Logical shift right without updating flags. </td></tr> <tr> <td><code>SHLX ra,r/m,rb</code> </td> <td><code>VEX.LZ.66.0F38 F7 /r</code> </td> <td>Shift left without updating flags. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-175"><a href="#cite_ref-175">^</a> On AMD CPUs, the "ABM" extension provides both <code>POPCNT</code> and <code>LZCNT</code>. On Intel CPUs, however, the CPUID bit for "ABM" is only documented to indicate the presence of the <code>LZCNT</code> instruction and is listed as "LZCNT", while <code>POPCNT</code> has its own separate CPUID feature bit. However, all known processors that implement the "ABM"/"LZCNT" extensions also implement <code>POPCNT</code> and set the CPUID feature bit for POPCNT, so the distinction is theoretical only. (The converse is not true – there exist processors that support <code>POPCNT</code> but not ABM, such as Intel <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> and <a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a> 3000.) </li> <li id="cite_note-176"><a href="#cite_ref-176">^</a> The <code>LZCNT</code> instruction will execute as <code>BSR</code> on systems that do not support the LZCNT or ABM extensions. <code>BSR</code> computes the index of the highest set bit in the source operand, producing a different result from <code>LZCNT</code> for most input values. </li> <li id="cite_note-177"><a href="#cite_ref-177">^</a> The <code>TZCNT</code> instruction will execute as <code>BSF</code> on systems that do not support the BMI1 extension. <code>BSF</code> produces the same result as <code>TZCNT</code> for all input operand values except zero – for which <code>TZCNT</code> returns input operand size, but <code>BSF</code> produces undefined behavior (leaves destination unmodified on most modern CPUs). </li> <li id="cite_note-178"><a href="#cite_ref-178">^</a> For <code>BEXTR</code>, the start position and length are not masked and can take values from 0 to 255. If the selected bits extend beyond the end of the <code>r/m</code> argument (which has the usual 32/64-bit operand size), then the excess bits are read out as 0. </li> <li id="cite_note-182"><a href="#cite_ref-182">^</a> On AMD processors before Zen 3, the <code>PEXT</code> and <code>PDEP</code> instructions are quite slow<a href="#cite_note-179">[85]</a> and exhibit data-dependent timing due to the use of a microcoded implementation (about 18 to 300 cycles, depending on the number of bits set in the mask argument). As a result, it is often faster to use other instruction sequences on these processors.<a href="#cite_note-180">[86]</a><a href="#cite_note-181">[87]</a> </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_Intel_TSX">Added with Intel TSX</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=12" title="Edit section: Added with Intel TSX">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">Transactional Synchronization Extensions</a></div> <table class="wikitable sortable"> <tbody><tr> <th>TSX Subset</th> <th>Instruction</th> <th>Opcode</th> <th>Description</th> <th>Added in </th></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="rtm"><dfn>RTM</dfn></dt><dd>Restricted <a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></dd></dl> </td> <td><code>XBEGIN rel16</code> <code>XBEGIN rel32</code> </td> <td><code>C7 F8 cw</code> <code>C7 F8 cd</code> </td> <td>Start transaction. If transaction fails, perform a branch to the given relative offset. </td> <td rowspan="4"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> (Deprecated on desktop/laptop CPUs from 10th generation (<a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a>, <a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a>) onwards, but continues to be available on <a href="/wiki/Xeon" title="Xeon">Xeon</a>-branded server parts (e.g. <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake-SP</a>, <a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a>)) </td></tr> <tr> <td><code>XABORT imm8</code> </td> <td><code>C6 F8 ib</code> </td> <td>Abort transaction with 8-bit immediate as error code. </td></tr> <tr> <td><code>XEND</code> </td> <td><code>NP 0F 01 D5</code> </td> <td>End transaction. </td></tr> <tr> <td><code>XTEST</code> </td> <td><code>NP 0F 01 D6</code> </td> <td>Test if in transactional execution. Sets <code><a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>.ZF</code> to 0 if executed inside a transaction (RTM or HLE), 1 otherwise. </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="hle"><dfn>HLE</dfn></dt><dd>Hardware Lock Elision</dd></dl> </td> <td><code>XACQUIRE</code> </td> <td><code>F2</code> </td> <td>Instruction prefix to indicate start of hardware lock elision, used with memory atomic instructions only (for other instructions, the <code>F2</code> prefix may have other meanings). When used with such instructions, may start a transaction instead of performing the memory atomic operation. </td> <td rowspan="2"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> (Discontinued – the last processors to support HLE were <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a> and <a href="/wiki/Cascade_Lake_(microprocessor)" class="mw-redirect" title="Cascade Lake (microprocessor)">Cascade Lake</a>) </td></tr> <tr> <td><code>XRELEASE</code> </td> <td><code>F3</code> </td> <td>Instruction prefix to indicate end of hardware lock elision, used with memory atomic/store instructions only (for other instructions, the <code>F3</code> prefix may have other meanings). When used with such instructions during hardware lock elision, will end the associated transaction instead of performing the store/atomic. </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="tsxldtrk"><dfn>TSXLDTRK</dfn></dt><dd>Load Address Tracking suspend/resume</dd></dl> </td> <td><code>XSUSLDTRK</code> </td> <td><code>F2 0F 01 E8</code> </td> <td>Suspend Tracking Load Addresses </td> <td rowspan="2"><a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a> </td></tr> <tr> <td><code>XRESLDTRK</code> </td> <td><code>F2 0F 01 E9</code> </td> <td>Resume Tracking Load Addresses </td></tr></tbody></table> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_Intel_CET">Added with <a href="/wiki/Control-flow_integrity#Intel_Control-flow_Enforcement_Technology" title="Control-flow integrity">Intel CET</a></h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=13" title="Edit section: Added with Intel CET">edit</a>]</div> Intel CET (Control-Flow Enforcement Technology) adds two distinct features to help protect against security exploits such as <a href="/wiki/Return-oriented_programming" title="Return-oriented programming">return-oriented programming</a>: a <a href="/wiki/Shadow_stack" title="Shadow stack">shadow stack</a> (CET_SS), and <a href="/wiki/Indirect_branch_tracking" title="Indirect branch tracking">indirect branch tracking</a> (CET_IBT). <table class="wikitable sortable"> <tbody><tr> <th>CET Subset</th> <th>Instruction</th> <th>Opcode</th> <th>Description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="12"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="cet_ss"><dfn>CET_SS</dfn></dt><dd><a href="/wiki/Shadow_stack" title="Shadow stack">Shadow stack</a>. When shadow stacks are enabled, return addresses are pushed on both the regular stack and the shadow stack when a function call is made. They are then both popped on return from the function call – if they do not match, then the stack is assumed to be corrupted, and a #CP exception is issued. The shadow stack is additionally required to be stored in specially marked memory pages which cannot be modified by normal memory store instructions.</dd></dl> </td> <td><code>INCSSPD r32</code> </td> <td><code>F3 0F AE /5</code> </td> <td rowspan="2">Increment shadow stack pointer </td> <td rowspan="8" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="12"><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>, <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> </td></tr> <tr> <td><code>INCSSPQ r64</code> </td> <td><code>F3 REX.W 0F AE /5</code> </td></tr> <tr> <td><code>RDSSPD r32</code> </td> <td><code>F3 0F 1E /1</code> </td> <td>Read shadow stack pointer into register (low 32 bits)<a href="#cite_note-rdssp_nop-183">[a]</a> </td></tr> <tr> <td><code>RDSSPQ r64</code> </td> <td><code>F3 REX.W 0F 1E /1</code> </td> <td>Read shadow stack pointer into register (full 64 bits)<a href="#cite_note-rdssp_nop-183">[a]</a> </td></tr> <tr> <td><code>SAVEPREVSSP</code> </td> <td><code>F3 0F 01 EA</code> </td> <td>Save previous shadow stack pointer </td></tr> <tr> <td><code>RSTORSSP m64</code> </td> <td><code>F3 0F 01 /5</code> </td> <td>Restore saved shadow stack pointer </td></tr> <tr> <td><code>WRSSD m32,r32</code> </td> <td><code>NP 0F 38 F6 /r</code> </td> <td>Write 4 bytes to shadow stack </td></tr> <tr> <td><code>WRSSQ m64,r64</code> </td> <td><code>NP REX.W 0F 38 F6 /r</code> </td> <td>Write 8 bytes to shadow stack </td></tr> <tr> <td><code>WRUSSD m32,r32</code> </td> <td><code>66 0F 38 F5 /r</code> </td> <td>Write 4 bytes to user shadow stack </td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <td><code>WRUSSQ m64,r64</code> </td> <td><code>66 REX.W 0F 38 F5 /r</code> </td> <td>Write 8 bytes to user shadow stack </td></tr> <tr> <td><code>SETSSBSY</code> </td> <td><code>F3 0F 01 E8</code> </td> <td>Mark shadow stack busy </td></tr> <tr> <td><code>CLRSSBSY m64</code> </td> <td><code>F3 0F AE /6</code> </td> <td>Clear shadow stack busy flag </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="cet_ibt"><dfn>CET_IBT</dfn></dt><dd><a href="/wiki/Indirect_Branch_Tracking" class="mw-redirect" title="Indirect Branch Tracking">Indirect Branch Tracking</a>. When IBT is enabled, an indirect branch (jump, call, return) to any instruction that is not an <code>ENDBR32/64</code> instruction will cause a #CP exception.</dd></dl> </td> <td><code>ENDBR32</code> </td> <td><code>F3 0F 1E FB</code> </td> <td>Terminate indirect branch in 32-bit mode<a href="#cite_note-endbr_nop-184">[b]</a> </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="3"><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a> </td></tr> <tr> <td><code>ENDBR64</code> </td> <td><code>F3 0F 1E FA</code> </td> <td>Terminate indirect branch in 64-bit mode<a href="#cite_note-endbr_nop-184">[b]</a> </td></tr> <tr> <td><code>NOTRACK</code> </td> <td><code>3E</code><a href="#cite_note-188">[c]</a> </td> <td>Prefix used with indirect <code>CALL</code>/<code>JMP</code> near instructions (opcodes <code>FF /2</code> and <code>FF /4</code>) to indicate that the branch target is not required to start with an <code>ENDBR32/64</code> instruction. Prefix only honored when NO_TRACK_EN flag is set. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-rdssp_nop-183">^ <a href="#cite_ref-rdssp_nop_183-0">a</a> <a href="#cite_ref-rdssp_nop_183-1">b</a> The <code>RDSSPD</code> and <code>RDSSPQ</code> instructions act as NOPs on processors where shadow stacks are disabled or CET is not supported. </li> <li id="cite_note-endbr_nop-184">^ <a href="#cite_ref-endbr_nop_184-0">a</a> <a href="#cite_ref-endbr_nop_184-1">b</a> <code>ENDBR32</code> and <code>ENDBR64</code> act as NOPs on processors that don't support CET_IBT or where IBT is disabled. </li> <li id="cite_note-188"><a href="#cite_ref-188">^</a> This prefix has the same encoding as the DS: segment override prefix – as of April 2022, Intel documentation does not appear to specify whether this prefix also retains its old segment-override function when used as a no-track prefix, nor does it provide an official mnemonic for this prefix.<a href="#cite_note-185">[88]</a><a href="#cite_note-186">[89]</a> (GNU binutils use "notrack"<a href="#cite_note-187">[90]</a>) </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_XSAVE">Added with XSAVE</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=14" title="Edit section: Added with XSAVE">edit</a>]</div> The XSAVE instruction set extensions are designed to save/restore CPU extended state (typically for the purpose of <a href="/wiki/Context_switch" title="Context switch">context switching</a>) in a manner that can be extended to cover new instruction set extensions without the OS context-switching code needing to understand the specifics of the new extensions. This is done by defining a series of state-components, each with a size and offset within a given save area, and each corresponding to a subset of the state needed for one CPU extension or another. The <code>EAX=0Dh</code> <a href="/wiki/CPUID#EAX=0Dh:_XSAVE_features_and_state-components" title="CPUID">CPUID</a> leaf is used to provide information about which state-components the CPU supports and what their sizes/offsets are, so that the OS can reserve the proper amount of space and set the associated enable-bits. <table class="wikitable sortable"> <tbody><tr> <th>XSAVE Extension</th> <th>Instruction mnemonics</th> <th>Opcode<a href="#cite_note-189">[a]</a></th> <th>Instruction description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="xsave"><dfn>XSAVE</dfn></dt><dd>Processor Extended State Save/Restore.</dd></dl> </td> <td><code>XSAVE mem</code> <code>XSAVE64 mem</code> </td> <td><code>NP 0F AE /4</code> <code>NP REX.W 0F AE /4</code> </td> <td>Save state components specified by bitmap in EDX:EAX to memory. </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="4"><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a>,<a href="#cite_note-190">[b]</a> <a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a>, <a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <td><code>XRSTOR mem</code> <code>XRSTOR64 mem</code> </td> <td><code>NP 0F AE /5</code> <code>NP REX.W 0F AE /5</code> </td> <td>Restore state components specified by EDX:EAX from memory. </td></tr> <tr> <td><code>XGETBV</code> </td> <td><code>NP 0F 01 D0</code> </td> <td>Get value of Extended Control Register. Reads an XCR specified by ECX into EDX:EAX.<a href="#cite_note-191">[c]</a> </td></tr> <tr> <td><code>XSETBV</code> </td> <td><code>NP 0F 01 D1</code> </td> <td>Set Extended Control Register.<a href="#cite_note-192">[d]</a> Write the value in EDX:EAX to the XCR specified by ECX. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="xsaveopt"><dfn>XSAVEOPT</dfn></dt><dd>Processor Extended State Save/Restore Optimized</dd></dl> </td> <td><code>XSAVEOPT mem</code> <code>XSAVEOPT64 mem</code> </td> <td><code>NP 0F AE /6</code> <code>NP REX.W 0F AE /6</code> </td> <td>Save state components specified by EDX:EAX to memory. Unlike the older <code>XSAVE</code> instruction, <code>XSAVEOPT</code> may abstain from writing processor state items to memory when the CPU can determine that they haven't been modified since the most recent corresponding <code>XRSTOR</code>. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>, <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a>, <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="xsavec"><dfn>XSAVEC</dfn></dt><dd>Processor Extended State save/restore with compaction.</dd></dl> </td> <td><code>XSAVEC mem</code> <code>XSAVEC64 mem</code> </td> <td><code>NP 0F C7 /4</code> <code>NP REX.W 0F C7 /4</code> </td> <td>Save processor extended state components specified by EDX:EAX to memory with compaction. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="xss"><dfn>XSS</dfn></dt><dd>Processor Extended State save/restore, including supervisor state.</dd></dl> </td> <td><code>XSAVES mem</code> <code>XSAVES64 mem</code> </td> <td><code>NP 0F C7 /5</code> <code>NP REX.W 0F C7 /5</code> </td> <td>Save processor extended state components specified by EDX:EAX to memory with compaction and optimization if possible. </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2"><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a> </td></tr> <tr> <td><code>XRSTORS mem</code> <code>XRSTORS64 mem</code> </td> <td><code>NP 0F C7 /3</code> <code>NP REX.W 0F C7 /3</code> </td> <td>Restore state components specified by EDX:EAX from memory. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-189"><a href="#cite_ref-189">^</a> Under Intel APX, the <code>XSAVE*</code> and <code>XRSTOR*</code> instructions cannot be encoded with the REX2 prefix. </li> <li id="cite_note-190"><a href="#cite_ref-190">^</a> XSAVE was added in steppings E0/R0 of Penryn and is not available in earlier steppings. </li> <li id="cite_note-191"><a href="#cite_ref-191">^</a> On some processors (starting with <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> and <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a>), executing <code>XGETBV</code> with ECX=1 is permitted – this will not return <code>XCR1</code> (no such register exists) but instead return <code>XCR0</code> bitwise-ANDed with the current value of the "XINUSE" state-component bitmap (a bitmap of XSAVE state-components that are not known to be in their initial state). The presence of this functionality of <code>XGETBV</code> is indicated by <a href="/wiki/CPUID" title="CPUID">CPUID</a>.(EAX=0Dh,ECX=1):EAX[bit 2]. </li> <li id="cite_note-192"><a href="#cite_ref-192">^</a> The <code>XSETBV</code> instruction will cause a mandatory #VMEXIT if executed under <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> virtualization. </li> </ol></div></div> <div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_other_cross-vendor_extensions">Added with other cross-vendor extensions</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=15" title="Edit section: Added with other cross-vendor extensions">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction Set Extension</th> <th>Instruction mnemonics</th> <th>Opcode</th> <th>Instruction description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="5"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sse'`UNIQ--ref-00000286-QINU`'"><dfn><a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a><a href="#cite_note-k7_mmxext-193">[a]</a></dfn></dt><dd>(non-SIMD)</dd></dl> </td> <td><code>PREFETCHNTA m8</code> </td> <td><code>0F 18 /0</code> </td> <td>Prefetch with Non-Temporal Access. Prefetch data under the assumption that the data will be used only once, and attempt to minimize cache pollution from said data. The methods used to minimize cache pollution are implementation-dependent.<a href="#cite_note-prefetch_hint-194">[b]</a> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="5"><a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a>, (<a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">K7</a>),<a href="#cite_note-k7_mmxext-193">[a]</a> (<a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode GX2</a>),<a href="#cite_note-k7_mmxext-193">[a]</a> <a href="/wiki/VIA_C3#Nehemiah_cores" title="VIA C3">Nehemiah</a>, <a href="/wiki/Transmeta_Efficeon" title="Transmeta Efficeon">Efficeon</a> </td></tr> <tr> <td><code>PREFETCHT0 m8</code> </td> <td><code>0F 18 /1</code> </td> <td>Prefetch data to all levels of the cache hierarchy.<a href="#cite_note-prefetch_hint-194">[b]</a> </td></tr> <tr> <td><code>PREFETCHT1 m8</code> </td> <td><code>0F 18 /2</code> </td> <td>Prefetch data to all levels of the cache hierarchy except L1 cache.<a href="#cite_note-prefetch_hint-194">[b]</a> </td></tr> <tr> <td><code>PREFETCHT2 m8</code> </td> <td><code>0F 18 /3</code> </td> <td>Prefetch data to all levels of the cache hierarchy except L1 and L2 caches.<a href="#cite_note-prefetch_hint-194">[b]</a> </td></tr> <tr> <td><code>SFENCE</code> </td> <td><code>NP 0F AE F8+x</code><a href="#cite_note-sse_partial_decode-196">[c]</a> </td> <td>Store Fence.<a href="#cite_note-199">[d]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sse2"><dfn><a href="/wiki/SSE2" title="SSE2">SSE2</a></dfn></dt><dd>(non-SIMD)</dd></dl> </td> <td><code>LFENCE</code> </td> <td><code>NP 0F AE E8+x</code><a href="#cite_note-sse_partial_decode-196">[c]</a> </td> <td>Load Fence and Dispatch Serialization.<a href="#cite_note-202">[e]</a> </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="4"><a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>, <a href="/wiki/AMD_K8" title="AMD K8">K8</a>, <a href="/wiki/Transmeta_Efficeon" title="Transmeta Efficeon">Efficeon</a>, <a href="/wiki/VIA_C7" title="VIA C7">C7 Esther</a> </td></tr> <tr> <td><code>MFENCE</code> </td> <td><code>NP 0F AE F0+x</code><a href="#cite_note-sse_partial_decode-196">[c]</a> </td> <td>Memory Fence.<a href="#cite_note-204">[f]</a> </td></tr> <tr> <td><code>MOVNTI m32,r32</code> <code>MOVNTI m64,r64</code> </td> <td><code>NP 0F C3 /r</code> <code>NP REX.W 0F C3 /r</code> </td> <td>Non-Temporal Memory Store. </td></tr> <tr> <td><code>PAUSE</code> </td> <td><code>F3 90</code><a href="#cite_note-205">[g]</a> </td> <td>Pauses CPU thread for a short time period.<a href="#cite_note-206">[h]</a> Intended for use in spinlocks.<a href="#cite_note-207">[i]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="clfsh'`UNIQ--ref-0000029D-QINU`'"><dfn>CLFSH<a href="#cite_note-208">[j]</a></dfn></dt><dd>Cache Line Flush.</dd></dl> </td> <td><code>CLFLUSH m8</code> </td> <td><code>NP 0F AE /7</code> </td> <td>Flush one cache line to memory. In a system with multiple <a href="/wiki/Cache_hierarchy" title="Cache hierarchy">cache hierarchy</a> levels and/or multiple processors each with their own caches, the line is flushed from all of them. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td>(SSE2), <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode LX</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="monitor'`UNIQ--ref-0000029E-QINU`'"><dfn>MONITOR<a href="#cite_note-209">[k]</a></dfn></dt><dd>Monitor a memory location for memory writes.</dd></dl> </td> <td><code>MONITOR</code><a href="#cite_note-monitor_explicit_op-212">[l]</a> <code>MONITOR EAX,ECX,EDX</code> </td> <td><code>NP 0F 01 C8</code> </td> <td>Start monitoring a memory location for memory writes. The memory address to monitor is given by DS:AX/EAX/RAX.<a href="#cite_note-213">[m]</a> ECX and EDX are reserved for extra extension and hint flags, respectively.<a href="#cite_note-214">[n]</a> </td> <td rowspan="2" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">Usually 0<a href="#cite_note-monitor_ring3-217">[o]</a> </td> <td rowspan="2"><a href="/wiki/Pentium_4#Prescott" title="Pentium 4">Prescott</a>, <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a>, <a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>, <a href="/wiki/AMD_K10" class="mw-redirect" title="AMD K10">K10</a>, <a href="/wiki/VIA_Nano" title="VIA Nano">Nano</a> </td></tr> <tr> <td><code>MWAIT</code><a href="#cite_note-monitor_explicit_op-212">[l]</a> <code>MWAIT EAX,ECX</code> </td> <td><code>NP 0F 01 C9</code> </td> <td>Wait for a write to a monitored memory location previously specified with <code>MONITOR</code>.<a href="#cite_note-218">[p]</a> ECX and EAX are used to provide extra extension<a href="#cite_note-221">[q]</a> and hint<a href="#cite_note-222">[r]</a> flags, respectively. <code>MWAIT</code> hints are commonly used for CPU power management. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="smx"><dfn>SMX</dfn></dt><dd>Safer Mode Extensions. Load, authenticate and execute a digitally signed "Authenticated Code Module" as part of Intel <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a>.</dd></dl> </td> <td><code>GETSEC</code> </td> <td><code>NP 0F 37</code><a href="#cite_note-223">[s]</a> </td> <td>Perform an SMX function. The leaf function to perform is given in EAX.<a href="#cite_note-224">[t]</a> Depending on leaf function, the instruction may take additional arguments in RBX, ECX and EDX. </td> <td style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">Usually 0<a href="#cite_note-225">[u]</a> </td> <td><a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe</a>/<a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">WuDaoKou</a>,<a href="#cite_note-226">[103]</a> <a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="rdtscp"><dfn>RDTSCP</dfn></dt><dd>Read <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> and Processor ID.</dd></dl> </td> <td><code>RDTSCP</code> </td> <td><code>0F 01 F9</code> </td> <td>Read Time Stamp Counter and processor core ID.<a href="#cite_note-rdtscp_rdpid-227">[v]</a> The TSC value is placed in EDX:EAX and the core ID in ECX.<a href="#cite_note-228">[w]</a> </td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-229">[x]</a> </td> <td><a href="/wiki/AMD_K8" title="AMD K8">K8</a>,<a href="#cite_note-230">[y]</a> <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>, <a href="/wiki/Silvermont" title="Silvermont">Silvermont</a>, <a href="/wiki/VIA_Nano" title="VIA Nano">Nano</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="popcnt'`UNIQ--ref-000002B5-QINU`'"><dfn>POPCNT<a href="#cite_note-231">[z]</a></dfn></dt><dd><a href="/wiki/Hamming_weight" title="Hamming weight">Population Count</a>.</dd></dl> </td> <td><code>POPCNT r16,r/m16</code> <code>POPCNT r32,r/m32</code> </td> <td><code>F3 0F B8 /r</code> </td> <td rowspan="2">Count the number of bits that are set to 1 in its source argument. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/AMD_K10" class="mw-redirect" title="AMD K10">K10</a>, <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>, <a href="/wiki/VIA_Nano" title="VIA Nano">Nano 3000</a> </td></tr> <tr> <td><code>POPCNT r64,r/m64</code> </td> <td><code>F3 REX.W 0F B8 /r</code> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sse4.2"><dfn><a href="/wiki/SSE4#SSE4.2" title="SSE4">SSE4.2</a></dfn></dt><dd>(non-SIMD)</dd></dl> </td> <td><code>CRC32 r32,r/m8</code> </td> <td><code>F2 0F 38 F0 /r</code> </td> <td rowspan="3">Accumulate <a href="/wiki/Cyclic_redundancy_check" title="Cyclic redundancy check">CRC</a> value using the CRC-32C (Castagnoli) polynomial 0x11EDC6F41 (normal form 0x1EDC6F41). This is the polynomial used in iSCSI. In contrast to the more popular one used in Ethernet, its parity is even, and it can thus detect any error with an odd number of changed bits. </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="3"><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>, <a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <td><code>CRC32 r32,r/m16</code> <code>CRC32 r32,r/m32</code> </td> <td><code>F2 0F 38 F1 /r</code> </td></tr> <tr> <td><code>CRC32 r64,r/m64</code> </td> <td><code>F2 REX.W 0F 38 F1 /r</code> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="fsgsbase"><dfn>FSGSBASE</dfn></dt><dd>Read/write base address of FS and GS segments from user-mode. Available in 64-bit mode only.</dd></dl> </td> <td><code>RDFSBASE r32</code> <code>RDFSBASE r64</code> </td> <td><code>F3 0F AE /0</code> <code>F3 REX.W 0F AE /0</code> </td> <td>Read base address of FS: segment. </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="4"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a>, <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <td><code>RDGSBASE r32</code> <code>RDGSBASE r64</code> </td> <td><code>F3 0F AE /1</code> <code>F3 REX.W 0F AE /1</code> </td> <td>Read base address of GS: segment. </td></tr> <tr> <td><code>WRFSBASE r32</code> <code>WRFSBASE r64</code> </td> <td><code>F3 0F AE /2</code> <code>F3 REX.W 0F AE /2</code> </td> <td>Write base address of FS: segment. </td></tr> <tr> <td><code>WRGSBASE r32</code> <code>WRGSBASE r64</code> </td> <td><code>F3 0F AE /3</code> <code>F3 REX.W 0F AE /3</code> </td> <td>Write base address of GS: segment. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="4"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="movbe"><dfn>MOVBE</dfn></dt><dd>Move to/from memory with <a href="/wiki/Endianness#Byte_swapping" title="Endianness">byte order swap</a>.</dd></dl> </td> <td><code>MOVBE r16,m16</code> <code>MOVBE r32,m32</code> </td> <td><code>NFx 0F 38 F0 /r</code> </td> <td rowspan="2">Load from memory to register with byte-order swap. </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="4"><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>, <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a>, <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <td><code>MOVBE r64,m64</code> </td> <td><code>NFx REX.W 0F 38 F0 /r</code> </td></tr> <tr> <td><code>MOVBE m16,r16</code> <code>MOVBE m32,r32</code> </td> <td><code>NFx 0F 38 F1 /r</code> </td> <td rowspan="2">Store to memory from register with byte-order swap. </td></tr> <tr> <td><code>MOVBE m64,r64</code> </td> <td><code>NFx REX.W 0F 38 F1 /r</code> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="invpcid"><dfn>INVPCID</dfn></dt><dd>Invalidate <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a> entries by <a href="/wiki/Process-context_identifier" class="mw-redirect" title="Process-context identifier">Process-context identifier</a>.</dd></dl> </td> <td><code>INVPCID reg,m128</code> </td> <td><code>66 0F 38 82 /r</code> </td> <td>Invalidate entries in TLB and paging-structure caches based on invalidation type in register<a href="#cite_note-232">[aa]</a> and descriptor in m128. The descriptor contains a memory address and a PCID.<a href="#cite_note-234">[ab]</a> Instruction is serializing on AMD but not Intel CPUs. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a>, <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="prefetchw'`UNIQ--ref-000002B9-QINU`'"><dfn>PREFETCHW<a href="#cite_note-235">[ac]</a></dfn></dt><dd>Cache-line prefetch with intent to write.</dd></dl> </td> <td><code>PREFETCHW m8</code> </td> <td><code>0F 0D /1</code> </td> <td>Prefetch cache line with intent to write.<a href="#cite_note-prefetch_hint-194">[b]</a> </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/AMD_K6-2" title="AMD K6-2">K6-2</a>, (<a href="/wiki/Pentium_4#Cedar_Mill" title="Pentium 4">Cedar Mill</a>),<a href="#cite_note-236">[ad]</a> <a href="/wiki/Silvermont" title="Silvermont">Silvermont</a>, <a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a> </td></tr> <tr> <td><code>PREFETCH m8</code><a href="#cite_note-239">[ae]</a> </td> <td><code>0F 0D /0</code> </td> <td>Prefetch cache line.<a href="#cite_note-prefetch_hint-194">[b]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="adx"><dfn><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a></dfn></dt><dd>Enhanced variants of add-with-carry.</dd></dl> </td> <td><code>ADCX r32,r/m32</code> <code>ADCX r64,r/m64</code> </td> <td><code>66 0F 38 F6 /r</code> <code>66 REX.W 0F 38 F6 /r</code> </td> <td>Add-with-carry. Differs from the older <code>ADC</code> instruction in that it leaves flags other than <code>EFLAGS.CF</code> unchanged. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a>, <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">ZhangJiang</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> </td></tr> <tr> <td><code>ADOX r32,r/m32</code> <code>ADOX r64,r/m64</code> </td> <td><code>F3 0F 38 F6 /r</code> <code>F3 REX.W 0F 38 F6 /r</code> </td> <td>Add-with-carry, with the overflow-flag <code>EFLAGS.OF</code> serving as carry input and output, with other flags left unchanged. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="smap"><dfn>SMAP</dfn></dt><dd><a href="/wiki/Supervisor_Mode_Access_Prevention" title="Supervisor Mode Access Prevention">Supervisor Mode Access Prevention</a>. Repurposes the <code>EFLAGS.AC</code> (alignment check) flag to a flag that prevents access to user-mode memory while in ring 0, 1 or 2.</dd></dl> </td> <td><code>CLAC</code> </td> <td><code>NP 0F 01 CA</code> </td> <td>Clear <code>EFLAGS.AC</code>. </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2"><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">LuJiaZui</a><a href="#cite_note-lujiazui_step2-241">[af]</a> </td></tr> <tr> <td><code>STAC</code> </td> <td><code>NP 0F 01 CB</code> </td> <td>Set <code>EFLAGS.AC</code>. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="clflushopt"><dfn>CLFLUSHOPT</dfn></dt><dd>Optimized Cache Line Flush.</dd></dl> </td> <td><code>CLFLUSHOPT m8</code> </td> <td><code>NFx 66 0F AE /7</code> </td> <td>Flush cache line. Differs from the older <code>CLFLUSH</code> instruction in that it has more relaxed ordering rules with respect to memory stores and other cache line flushes, enabling improved performance. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>, <a href="/wiki/Goldmont" title="Goldmont">Goldmont</a>, <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="prefetchwt1"><dfn>PREFETCHWT1</dfn></dt><dd>Cache-line prefetch into L2 cache with intent to write.</dd></dl> </td> <td><code>PREFETCHWT1 m8</code> </td> <td><code>0F 0D /2</code> </td> <td>Prefetch data with T1 locality hint (fetch into L2 cache, but not L1 cache) and intent-to-write hint.<a href="#cite_note-prefetch_hint-194">[b]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Xeon_Phi#Knights_Landing" title="Xeon Phi">Knights Landing</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">YongFeng</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="pku"><dfn>PKU</dfn></dt><dd>Protection Keys for user pages.</dd></dl> </td> <td><code>RDPKRU</code> </td> <td><code>NP 0F 01 EE</code> </td> <td>Read User Page Key register into EAX. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake-X</a>, <a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a>, <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a>, <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">LuJiaZui</a><a href="#cite_note-lujiazui_step2-241">[af]</a> </td></tr> <tr> <td><code>WRPKRU</code> </td> <td><code>NP 0F 01 EF</code> </td> <td>Write data from EAX into User Page Key Register, and perform a Memory Fence. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="clwb"><dfn>CLWB</dfn></dt><dd>Cache Line Writeback to memory.</dd></dl> </td> <td><code>CLWB m8</code> </td> <td><code>NFx 66 0F AE /6</code> </td> <td>Write one cache line back to memory without invalidating the cache line. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake-X</a>, <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a>, <a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>, <a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="rdpid"><dfn>RDPID</dfn></dt><dd>Read processor core ID.</dd></dl> </td> <td><code>RDPID r32</code> </td> <td><code>F3 0F C7 /7</code> </td> <td>Read processor core ID into register.<a href="#cite_note-rdtscp_rdpid-227">[v]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3<a href="#cite_note-242">[ag]</a> </td> <td><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a>, <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a>, <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a>, <a href="/wiki/Zhaoxin" title="Zhaoxin">LuJiaZui</a><a href="#cite_note-lujiazui_step2-241">[af]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="movdiri"><dfn>MOVDIRI</dfn></dt><dd>Move to memory as Direct Store.</dd></dl> </td> <td><code>MOVDIRI m32,r32</code> <code>MOVDIRI m64,r64</code> </td> <td><code>NP 0F 38 F9 /r</code> <code>NP REX.W 0F 38 F9 /r</code> </td> <td>Store to memory using Direct Store (memory store that is not cached or write-combined with other stores). </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>, <a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>, <a href="/wiki/Zen_5" title="Zen 5">Zen 5</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="movdir64b"><dfn>MOVDIR64B</dfn></dt><dd>Move 64 bytes as Direct Store.</dd></dl> </td> <td><code>MOVDIR64B reg,m512</code> </td> <td><code>66 0F 38 F8 /r</code> </td> <td>Move 64 bytes of data from m512 to address given by ES:reg. The 64-byte write is done atomically with Direct Store.<a href="#cite_note-243">[ah]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>, <a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>, <a href="/wiki/Zen_5" title="Zen 5">Zen 5</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="wbnoinvd"><dfn>WBNOINVD</dfn></dt><dd>Whole Cache Writeback without invalidate.</dd></dl> </td> <td><code>WBNOINVD</code> </td> <td><code>F3 0F 09</code> </td> <td>Write back all dirty cache lines to memory without invalidation.<a href="#cite_note-244">[ai]</a> Instruction is serializing. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a>, <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake-SP</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="prefetchi"><dfn>PREFETCHI</dfn></dt><dd>Instruction prefetch.</dd></dl> </td> <td><code>PREFETCHIT0 m8</code> </td> <td><code>0F 18 /7</code> </td> <td>Prefetch code to all levels of the cache hierarchy.<a href="#cite_note-prefetchi_note-245">[aj]</a> </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Zen_5" title="Zen 5">Zen 5</a>, <a href="/wiki/Granite_Rapids" title="Granite Rapids">Granite Rapids</a> </td></tr> <tr> <td><code>PREFETCHIT1 m8</code> </td> <td><code>0F 18 /6</code> </td> <td>Prefetch code to all levels of the cache hierarchy except first-level cache.<a href="#cite_note-prefetchi_note-245">[aj]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-k7_mmxext-193">^ <a href="#cite_ref-k7_mmxext_193-0">a</a> <a href="#cite_ref-k7_mmxext_193-1">b</a> <a href="#cite_ref-k7_mmxext_193-2">c</a> AMD <a href="/wiki/Athlon" title="Athlon">Athlon</a> processors prior to the Athlon XP did not support full SSE, but did introduce the non-SIMD instructions of SSE as part of <a href="/wiki/Extended_MMX" title="Extended MMX">"MMX Extensions"</a>.<a href="#cite_note-195">[91]</a> These extensions (without full SSE) are also present on <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode GX2</a> and later Geode processors. </li> <li id="cite_note-prefetch_hint-194">^ <a href="#cite_ref-prefetch_hint_194-0">a</a> <a href="#cite_ref-prefetch_hint_194-1">b</a> <a href="#cite_ref-prefetch_hint_194-2">c</a> <a href="#cite_ref-prefetch_hint_194-3">d</a> <a href="#cite_ref-prefetch_hint_194-4">e</a> <a href="#cite_ref-prefetch_hint_194-5">f</a> <a href="#cite_ref-prefetch_hint_194-6">g</a> All of the <code>PREFETCH*</code> instructions are hint instructions with effects only on performance, not program semantics. Providing an invalid address (e.g. address of an unmapped page or a non-canonical address) will cause the instruction to act as a NOP without any exceptions generated. </li> <li id="cite_note-sse_partial_decode-196">^ <a href="#cite_ref-sse_partial_decode_196-0">a</a> <a href="#cite_ref-sse_partial_decode_196-1">b</a> <a href="#cite_ref-sse_partial_decode_196-2">c</a> For the <code>SFENCE</code>, <code>LFENCE</code> and <code>MFENCE</code> instructions, the bottom 3 bits of the ModR/M byte are ignored, and any value of x in the range 0..7 will result in a valid instruction. </li> <li id="cite_note-199"><a href="#cite_ref-199">^</a> The <code>SFENCE</code> instruction ensures that all memory stores after the <code>SFENCE</code> instruction are made globally observable after all memory stores before the <code>SFENCE</code>. This imposes ordering on stores that can otherwise be reordered, such as non-temporal stores and stores to WC (Write-Combining) memory regions.<a href="#cite_note-197">[92]</a> On Intel CPUs, as well as AMD CPUs from Zen1 onwards (but not older AMD CPUs), <code>SFENCE</code> also acts as a reordering barrier on cache flushes/writebacks performed with the <code>CLFLUSH</code>, <code>CLFLUSHOPT</code> and <code>CLWB</code> instructions. (Older AMD CPUs require <code>MFENCE</code> to order <code>CLFLUSH</code>.) <code>SFENCE</code> is not ordered with respect to <code>LFENCE</code>, and an <code>SFENCE+LFENCE</code> sequence is not sufficient to prevent a load from being reordered past a previous store.<a href="#cite_note-198">[93]</a> To prevent such reordering, it is necessary to execute an <code>MFENCE</code>, <code>LOCK</code> or a serializing instruction. </li> <li id="cite_note-202"><a href="#cite_ref-202">^</a> The <code>LFENCE</code> instruction ensures that all memory loads after the <code>LFENCE</code> instruction are made globally observable after all memory loads before the <code>LFENCE</code>. On all Intel CPUs that support SSE2, the <code>LFENCE</code> instruction provides a stronger ordering guarantee:<a href="#cite_note-200">[94]</a> it is dispatch-serializing, meaning that instructions after the <code>LFENCE</code> instruction are allowed to start executing only after all instructions before it have retired (which will ensure that all preceding loads but not necessarily stores have completed). The effect of dispatch-serialization is that <code>LFENCE</code> also acts as a <a href="/wiki/Speculative_execution" title="Speculative execution">speculation</a> barrier and a reordering barrier for accesses to non-memory resources such as performance counters (accessed through e.g. <code>RDTSC</code> or <code>RDPMC</code>) and <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">x2apic</a> MSRs. On AMD CPUs, <code>LFENCE</code> is not necessarily dispatch-serializing by default – however, on all AMD CPUs that support any form of non-dispatch-serializing <code>LFENCE</code>, it can be made dispatch-serializing by setting bit 1 of MSR <code>C001_1029</code>.<a href="#cite_note-201">[95]</a> </li> <li id="cite_note-204"><a href="#cite_ref-204">^</a> The <code>MFENCE</code> instruction ensures that all memory loads, stores and cacheline-flushes after the <code>MFENCE</code> instruction are made globally observable after all memory loads, stores and cacheline-flushes before the <code>MFENCE</code>. On Intel CPUs, <code>MFENCE</code> is not dispatch-serializing, and therefore cannot be used on its own to enforce ordering on accesses to non-memory resources such as performance counters and x2apic MSRs. <code>MFENCE</code> is still ordered with respect to <code>LFENCE</code>, so if there is a need to enforce ordering between memory stores and subsequent non-memory accesses, then such an ordering can be obtained by issuing an <code>MFENCE</code> followed by an <code>LFENCE</code>.<a href="#cite_note-rdtsc_ordering-109">[50]</a><a href="#cite_note-203">[96]</a> On AMD CPUs, <code>MFENCE</code> is serializing. </li> <li id="cite_note-205"><a href="#cite_ref-205">^</a> The operation of the <code>PAUSE</code> instruction in 64-bit mode is, unlike <code>NOP</code>, unaffected by the presence of the <code>REX.R</code> prefix. Neither <code>NOP</code> nor <code>PAUSE</code> are affected by the other bits of the <code>REX</code> prefix. A few examples of how opcode <code>90</code> interacts with various prefixes in 64-bit mode are:<ul><li><code>90</code> is <code>NOP</code></li><li><code>41 90</code> is <code>XCHG R8D,EAX</code></li><li><code>4E 90</code> is <code>NOP</code></li><li><code>49 90</code> is <code>XCHG R8,RAX</code></li><li><code>F3 90</code> is <code>PAUSE</code></li><li><code>F3 41 90</code> is <code>PAUSE</code></li><li><code>F3 4F 90</code> is <code>PAUSE</code></li></ul> </li> <li id="cite_note-206"><a href="#cite_ref-206">^</a> The actual length of the pause performed by the <code>PAUSE</code> instruction is implementation-dependent. On systems without SSE2, <code>PAUSE</code> will execute as NOP. </li> <li id="cite_note-207"><a href="#cite_ref-207">^</a> Under VT-x or AMD-V virtualization, executing <code>PAUSE</code> many times in a short time interval may cause a #VMEXIT. The number of <code>PAUSE</code> executions and interval length that can trigger #VMEXIT are platform-specific. </li> <li id="cite_note-208"><a href="#cite_ref-208">^</a> While the <code>CLFLUSH</code> instruction was introduced together with SSE2, it has its own CPUID flag and may be present on processors not otherwise implementing SSE2 and/or absent from processors that otherwise implement SSE2. (E.g. AMD <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode LX</a> supports <code>CLFLUSH</code> but not SSE2.) </li> <li id="cite_note-209"><a href="#cite_ref-209">^</a> While the <code>MONITOR</code> and <code>MWAIT</code> instructions were introduced at the same time as SSE3, they have their own CPUID flag that needs to be checked separately from the SSE3 CPUID flag (e.g. <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a> and <a href="/wiki/VIA_C7" title="VIA C7">VIA C7</a> supported SSE3 but not MONITOR.) </li> <li id="cite_note-monitor_explicit_op-212">^ <a href="#cite_ref-monitor_explicit_op_212-0">a</a> <a href="#cite_ref-monitor_explicit_op_212-1">b</a> For the <code>MONITOR</code> and <code>MWAIT</code> instructions, older Intel documentation<a href="#cite_note-210">[97]</a> lists instruction mnemonics with explicit operands (<code>MONITOR EAX,ECX,EDX</code> and <code>MWAIT EAX,ECX</code>), while newer documentation omits these operands. Assemblers/disassemblers may support one or both of these variants.<a href="#cite_note-211">[98]</a> </li> <li id="cite_note-213"><a href="#cite_ref-213">^</a> For <code>MONITOR</code>, the DS: segment can be overridden with a segment prefix. The memory area that will be monitored will be not just the single byte specified by DS:rAX, but a linear memory region containing the byte – the size and alignment of this memory region is implementation-dependent and can be queried through CPUID. The memory location to monitor should have memory type WB (write-back cacheable), or else monitoring may fail. </li> <li id="cite_note-214"><a href="#cite_ref-214">^</a> As of April 2024, no extensions or hints have been defined for the <code>MONITOR</code> instruction. As such, the instruction requires ECX=0 and ignores EDX. </li> <li id="cite_note-monitor_ring3-217"><a href="#cite_ref-monitor_ring3_217-0">^</a> On some processors, such as Intel <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> x200<a href="#cite_note-215">[99]</a> and AMD K10<a href="#cite_note-216">[100]</a> and later, there exist documented MSRs that can be used to enable <code>MONITOR</code> and <code>MWAIT</code> to run in Ring 3. </li> <li id="cite_note-218"><a href="#cite_ref-218">^</a> The wait performed by <code>MWAIT</code>may be ended by system events other than a memory write (e.g. cacheline evictions, interrupts) – the exact set of events that can cause the wait to end is implementation-specific. Regardless of whether the wait was ended by a memory write or some other event, monitoring will have ended and it will be necessary to set up monitoring again with <code>MONITOR</code> before using <code>MWAIT</code> to wait for memory writes again. </li> <li id="cite_note-221"><a href="#cite_ref-221">^</a> The extension flags available for <code>MWAIT</code> in the ECX register are: <table class="wikitable sortable"> <tbody><tr> <th>Bits</th> <th>MWAIT Extension </th></tr> <tr> <td>0</td> <td>Treat interrupts as break events, even when masked (<a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>.IF=0). (Available on all non-<a href="/wiki/NetBurst" title="NetBurst">NetBurst</a> implementations of <code>MWAIT</code>.) </td></tr> <tr> <td>1</td> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial">Timed MWAIT: end the wait when the <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">TSC</a> reaches or exceeds the value in EDX:EBX. (Undocumented, reportedly present in Intel <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> and later Intel processors)<a href="#cite_note-219">[101]</a> </td></tr> <tr> <td>2</td> <td>Monitorless MWAIT<a href="#cite_note-220">[102]</a> </td></tr> <tr> <td>31:3</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align:" class="table-na">Not used, must be set to zero. </td></tr></tbody></table> </li> <li id="cite_note-222"><a href="#cite_ref-222">^</a> The hint flags available for <code>MWAIT</code> in the EAX register are: <table class="wikitable sortable"> <tbody><tr> <th>Bits</th> <th>MWAIT Hint </th></tr> <tr> <td>3:0</td> <td>Sub-state within a C-state (see bits 7:4) (Intel processors only) </td></tr> <tr> <td>7:4</td> <td>Target <a href="/wiki/ACPI#Processor_states" title="ACPI">CPU power C-state</a> during wait, minus 1. (E.g. 0000b for C1, 0001b for C2, 1111b for C0) </td></tr> <tr> <td>31:8</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align:" class="table-na">Not used. </td></tr></tbody></table> The C-states are processor-specific power states, which do not necessarily correspond 1:1 to <a href="/wiki/ACPI#Processor_states" title="ACPI">ACPI C-states</a>. </li> <li id="cite_note-223"><a href="#cite_ref-223">^</a> For the <code>GETSEC</code> instruction, the <code>REX.W</code> prefix enables 64-bit addresses for the EXITAC leaf function only - REX prefixes are otherwise permitted but ignored for the instruction. </li> <li id="cite_note-224"><a href="#cite_ref-224">^</a> The leaf functions defined for <code>GETSEC</code> (selected by EAX) are: <table class="wikitable sortable"> <tbody><tr> <th>EAX</th> <th>Function </th></tr> <tr> <td>0 (CAPABILITIES)</td> <td>Report SMX capabilities </td></tr> <tr> <td>2 (ENTERACCES)</td> <td>Enter execution of authenticated code module </td></tr> <tr> <td>3 (EXITAC)</td> <td>Exit execution of authenticated code module </td></tr> <tr> <td>4 (SENTER)</td> <td>Enter measured environment </td></tr> <tr> <td>5 (SEXIT)</td> <td>Exit measured environment </td></tr> <tr> <td>6 (PARAMETERS)</td> <td>Report SMX parameters </td></tr> <tr> <td>7 (SMCTRL)</td> <td>SMX Mode Control </td></tr> <tr> <td>8 (WAKEUP)</td> <td>Wake up sleeping processors in measured environment </td></tr></tbody></table> Any unsupported value in EAX causes an #UD exception. </li> <li id="cite_note-225"><a href="#cite_ref-225">^</a> For <code>GETSEC</code>, most leaf functions are restricted to Ring 0, but the CAPABILITIES (EAX=0) and PARAMETERS (EAX=6) leaf functions are available in Ring 3. </li> <li id="cite_note-rdtscp_rdpid-227">^ <a href="#cite_ref-rdtscp_rdpid_227-0">a</a> <a href="#cite_ref-rdtscp_rdpid_227-1">b</a> The "core ID" value read by <code>RDTSCP</code> and <code>RDPID</code> is actually the <code>TSC_AUX</code> MSR (MSR <code>C000_0103h</code>). Whether this value actually corresponds to a processor ID is a matter of operating system convention. </li> <li id="cite_note-228"><a href="#cite_ref-228">^</a> Unlike the older <code>RDTSC</code> instruction, <code>RDTSCP</code> will delay the TSC read until all previous instructions have retired, guaranteeing ordering with respect to preceding memory loads (but not stores). <code>RDTSCP</code> is not ordered with respect to subsequent instructions, though. </li> <li id="cite_note-229"><a href="#cite_ref-229">^</a> <code>RDTSCP</code> can be run outside Ring 0 only if <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.TSD</a>=0</code>. </li> <li id="cite_note-230"><a href="#cite_ref-230">^</a> Support for <code>RDTSCP</code> was added in stepping F of the AMD K8, and is not available on earlier steppings. </li> <li id="cite_note-231"><a href="#cite_ref-231">^</a> While the <code>POPCNT</code> instruction was introduced at the same time as SSE4.2, it is not considered to be a part of SSE4.2, but instead a separate extension with its own CPUID flag. On AMD processors, it is considered to be a part of the ABM extension, but still has its own CPUID flag. </li> <li id="cite_note-232"><a href="#cite_ref-232">^</a> The invalidation types defined for <code>INVPCID</code> (selected by register argument) are: <table class="wikitable sortable"> <tbody><tr> <th>Value</th> <th>Function </th></tr> <tr> <td>0</td> <td>Invalidate TLB entries matching PCID and virtual memory address in descriptor, excluding global entries </td></tr> <tr> <td>1</td> <td>Invalidate TLB entries matching PCID in descriptor, excluding global entries </td></tr> <tr> <td>2</td> <td>Invalidate all TLB entries, including global entries </td></tr> <tr> <td>3</td> <td>Invalidate all TLB entries, excluding global entries </td></tr></tbody></table> Any unsupported value in the register argument causes a #GP exception. </li> <li id="cite_note-234"><a href="#cite_ref-234">^</a> Unlike the older <code>INVLPG</code> instruction, <code>INVPCID</code> will cause a #GP exception if the provided memory address is non-canonical. This discrepancy has been known to cause security issues.<a href="#cite_note-233">[104]</a> </li> <li id="cite_note-235"><a href="#cite_ref-235">^</a> The <code>PREFETCH</code> and <code>PREFETCHW</code> instructions are mandatory parts of the <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> instruction set extension, but are also available as a standalone extension on systems that do not support 3DNow! </li> <li id="cite_note-236"><a href="#cite_ref-236">^</a> The opcodes for <code>PREFETCH</code> and <code>PREFETCHW</code> (<code>0F 0D /r</code>) execute as NOPs on Intel CPUs from Cedar Mill (65nm <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>) onwards, with <code>PREFETCHW</code> gaining prefetch functionality from Broadwell onwards. </li> <li id="cite_note-239"><a href="#cite_ref-239">^</a> The <code>PREFETCH</code> (<code>0F 0D /0</code>) instruction is a <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> instruction, present on all processors with 3DNow! but not necessarily on processors with the PREFETCHW extension. On AMD CPUs with PREFETCHW, opcode <code>0F 0D /0</code> as well as opcodes <code>0F 0D /2../7</code> are all documented to be performing prefetch. On Intel processors with PREFETCHW, these opcodes are documented as performing reserved-NOPs<a href="#cite_note-237">[105]</a> (except <code>0F 0D /2</code> being <code>PREFETCHWT1 m8</code> on <a href="/wiki/Xeon_Phi" title="Xeon Phi">Xeon Phi</a> only) – third party testing<a href="#cite_note-cattius_0f0d-238">[106]</a> indicates that some or all of these opcodes may be performing prefetch on at least some Intel Core CPUs. </li> <li id="cite_note-lujiazui_step2-241">^ <a href="#cite_ref-lujiazui_step2_241-0">a</a> <a href="#cite_ref-lujiazui_step2_241-1">b</a> <a href="#cite_ref-lujiazui_step2_241-2">c</a> The SMAP, PKU and RDPID instruction set extensions are supported on stepping 2<a href="#cite_note-240">[107]</a> and later of <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> LuJiaZui, but not on earlier steppings. </li> <li id="cite_note-242"><a href="#cite_ref-242">^</a> Unlike the older <code>RDTSCP</code> instruction which can also be used to read the processor ID, user-mode <code>RDPID</code> is not disabled by <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.TSD</a>=1</code>. </li> <li id="cite_note-243"><a href="#cite_ref-243">^</a> For <code>MOVDIR64</code>, the destination address given by ES:reg must be 64-byte aligned. The operand size for the register argument is given by the address size, which may be overridden by the <code>67h</code> prefix. The 64-byte memory source argument does not need to be 64-byte aligned, and is not guaranteed to be read atomically. </li> <li id="cite_note-244"><a href="#cite_ref-244">^</a> The <code>WBNOINVD</code> instruction will execute as <code>WBINVD</code> if run on a system that doesn't support the WBNOINVD extension. <code>WBINVD</code> differs from <code>WBNOINVD</code> in that <code>WBINVD</code> will invalidate all cache lines after writeback. </li> <li id="cite_note-prefetchi_note-245">^ <a href="#cite_ref-prefetchi_note_245-0">a</a> <a href="#cite_ref-prefetchi_note_245-1">b</a> In initial implementations, the <code>PREFETCHIT0</code> and <code>PREFETCHIT1</code> instructions will perform code prefetch only when using the RIP-relative addressing mode and act as NOPs otherwise. The PREFETCHI instructions are hint instructions only - if an attempt is made to prefetch an invalid address, the instructions will act as NOPs with no exceptions generated. On processors that support Long-NOP but do not support the PREFETCHI instructions, these instructions will always act as NOPs. </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_other_Intel-specific_extensions">Added with other Intel-specific extensions</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=16" title="Edit section: Added with other Intel-specific extensions">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction Set Extension</th> <th>Instruction mnemonics</th> <th>Opcode</th> <th>Instruction description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sse2_branch_hints"><dfn>SSE2 <a href="/wiki/Branch_(computer_science)#Branch_prediction_hints" title="Branch (computer science)">branch hints</a></dfn></dt><dd>Instruction prefixes that can be used with the <code>Jcc</code> instructions to provide branch taken/not-taken hints.</dd></dl> </td> <td>(<code>HWNT</code>)<a href="#cite_note-wmt_hint-248">[a]</a> </td> <td><code>2E</code><a href="#cite_note-wmt_prefix-249">[b]</a> </td> <td>Instruction prefix: branch hint weakly not taken. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>,<a href="#cite_note-250">[c]</a> <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a><a href="#cite_note-251">[110]</a> </td></tr> <tr> <td>(<code>HST</code>)<a href="#cite_note-wmt_hint-248">[a]</a> </td> <td><code>3E</code><a href="#cite_note-wmt_prefix-249">[b]</a> </td> <td>Instruction prefix: branch hint strongly taken. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sgx"><dfn>SGX</dfn></dt><dd><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">Software Guard Extensions</a>. Set up an encrypted enclave in which a guest can execute code that a compromised or malicious host cannot inspect or tamper with.</dd></dl> </td> <td><code>ENCLS</code> </td> <td><code>NP 0F 01 CF</code> </td> <td>Perform an SGX Supervisor function. The function to perform is given in EAX<a href="#cite_note-254">[d]</a> - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Depending on function, the instruction may return data in RBX and/or an error code in EAX. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="sgx1"><dfn>SGX1</dfn></dt><dd><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>,<a href="#cite_note-256">[e]</a> <a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></dd><dt id="sgx2"><dfn>SGX2</dfn></dt><dd><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a>, <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake-SP</a><a href="#cite_note-257">[114]</a></dd><dt id="oversub'`UNIQ--ref-000002DB-QINU`'"><dfn>OVERSUB<a href="#cite_note-sgx_oversub-252">[111]</a></dfn></dt><dd><a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake-SP</a>, <a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a></dd></dl> </td></tr> <tr> <td><code>ENCLU</code> </td> <td><code>NP 0F 01 D7</code> </td> <td>Perform an SGX User function. The function to perform is given in EAX<a href="#cite_note-259">[f]</a> - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Depending on function, the instruction may return data/status information in EAX and/or RCX. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3<a href="#cite_note-260">[g]</a> </td></tr> <tr> <td><code>ENCLV</code> </td> <td><code>NP 0F 01 C0</code> </td> <td>Perform an SGX Virtualization function. The function to perform is given in EAX<a href="#cite_note-261">[h]</a> - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. Instruction returns status information in EAX. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0<a href="#cite_note-262">[i]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="ptwrite"><dfn>PTWRITE</dfn></dt><dd>Write data to a Processor Trace Packet.</dd></dl> </td> <td><code>PTWRITE r/m32</code> <code>PTWRITE r/m64</code> </td> <td><code>F3 0F AE /4</code> <code>F3 REX.W 0F AE /4</code> </td> <td>Read data from register or memory to encode into a PTW packet.<a href="#cite_note-263">[j]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a>, <a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="pconfig"><dfn>PCONFIG</dfn></dt><dd>Platform Configuration, including TME-MK ("Total Memory Encryption – Multi-Key") and TSE ("Total Storage Encryption").</dd></dl> </td> <td><code>PCONFIG</code> </td> <td><code>NP 0F 01 C5</code> </td> <td>Perform a platform feature configuration function. The function to perform is specified in EAX<a href="#cite_note-264">[k]</a> - depending on function, the instruction may take additional input operands in RBX, RCX and RDX. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake-SP</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="cldemote"><dfn>CLDEMOTE</dfn></dt><dd>Cache Line Demotion Hint.</dd></dl> </td> <td><code>CLDEMOTE m8</code> </td> <td><code>NP 0F 1C /0</code> </td> <td>Move cache line containing m8 from CPU L1 cache to a more distant level of the cache hierarchy.<a href="#cite_note-265">[l]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td>(<a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>), (<a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a>), <a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a><a href="#cite_note-268">[m]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="3"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="waitpkg"><dfn>WAITPKG</dfn></dt><dd>User-mode memory monitoring and waiting.</dd></dl> </td> <td><code>UMONITOR r16/32/64</code> </td> <td><code>F3 0F AE /6</code> </td> <td>Start monitoring a memory location for memory writes. The memory address to monitor is given by the register argument.<a href="#cite_note-269">[n]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="3"><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>, <a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a> </td></tr> <tr> <td><code>UMWAIT r32</code> <code>UMWAIT r32,EDX,EAX</code> </td> <td><code>F2 0F AE /6</code> </td> <td>Timed wait for a write to a monitored memory location previously specified with <code>UMONITOR</code>. In the absence of a memory write, the wait will end when either the TSC reaches the value specified by EDX:EAX or the wait has been going on for an OS-controlled maximum amount of time.<a href="#cite_note-umwait_ctrl-270">[o]</a> </td> <td rowspan="2" style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-waitpkg_cr4tsd-271">[p]</a> </td></tr> <tr> <td><code>TPAUSE r32</code> <code>TPAUSE r32,EDX,EAX</code> </td> <td><code>66 0F AE /6</code> </td> <td>Wait until the <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> reaches the value specified in EDX:EAX.<a href="#cite_note-umwait_ctrl-270">[o]</a> The register argument to the <code>UMWAIT</code> and <code>TPAUSE</code> instructions specifies extra flags to control the operation of the instruction.<a href="#cite_note-umwait_flags-272">[q]</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="serialize"><dfn>SERIALIZE</dfn></dt><dd>Instruction Execution Serialization.</dd></dl> </td> <td><code>SERIALIZE</code> </td> <td><code>NP 0F 01 E8</code> </td> <td>Serialize instruction fetch and execution.<a href="#cite_note-273">[r]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="hreset"><dfn>HRESET</dfn></dt><dd>Processor History Reset.</dd></dl> </td> <td><code>HRESET imm8</code> </td> <td><code>F3 0F 3A F0 C0 ib</code> </td> <td>Request that the processor reset selected components of hardware-maintained prediction history. A bitmap of which components of the CPU's prediction history to reset is given in EAX (the imm8 argument is ignored).<a href="#cite_note-274">[s]</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="5"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="uintr"><dfn>UINTR</dfn></dt><dd>User Interprocessor interrupt. Available in 64-bit mode only.</dd></dl> </td> <td><code>SENDUIPI reg</code> </td> <td><code>F3 0F C7 /6</code> </td> <td>Send Interprocessor User Interrupt.<a href="#cite_note-275">[t]</a> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="5"><a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a> </td></tr> <tr> <td><code>UIRET</code> </td> <td><code>F3 0F 01 EC</code> </td> <td>User Interrupt Return. Pops <a href="/wiki/Program_counter" title="Program counter">RIP</a>, <a href="/wiki/FLAGS_register" title="FLAGS register">RFLAGS</a> and <a href="/wiki/Stack_register" title="Stack register">RSP</a> off the stack, in that order.<a href="#cite_note-276">[u]</a> </td></tr> <tr> <td><code>TESTUI</code> </td> <td><code>F3 0F 01 ED</code> </td> <td>Test User Interrupt Flag. Copies UIF to <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>.CF . </td></tr> <tr> <td><code>CLUI</code> </td> <td><code>F3 0F 01 EE</code> </td> <td>Clear User Interrupt Flag. </td></tr> <tr> <td><code>STUI</code> </td> <td><code>F3 0F 01 EF</code> </td> <td>Set User Interrupt Flag. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="enqcmd"><dfn>ENQCMD</dfn></dt><dd>Enqueue Store.Part of Intel DSA (<a href="/wiki/Sapphire_Rapids#Accelerators" title="Sapphire Rapids">Data Streaming Accelerator</a> Architecture).<a href="#cite_note-277">[118]</a></dd></dl> </td> <td><code>ENQCMD r32/64,m512</code> </td> <td><code>F2 0F 38 F8 /r</code> </td> <td>Enqueue Command. Reads a 64-byte "command data" structure from memory (m512 argument) and writes atomically to a memory-mapped Enqueue Store device (register argument provides the memory address of this device, using ES segment and requiring 64-byte alignment.) Sets ZF=0 to indicate that device accepted the command, or ZF=1 to indicate that command was not accepted (e.g. queue full or the memory location was not an Enqueue Store device.) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a> </td></tr> <tr> <td><code>ENQCMDS r32/64,m512</code> </td> <td><code>F3 0F 38 F8 /r</code> </td> <td>Enqueue Command Supervisor. Differs from <code>ENQCMD</code> in that it can place an arbitrary PASID (process address-space identifier) and a privilege-bit in the "command data" to enqueue. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="wrmsrns"><dfn>WRMSRNS</dfn></dt><dd>Non-serializing Write to <a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific register</a>.</dd></dl> </td> <td><code>WRMSRNS</code> </td> <td><code>NP 0F 01 C6</code> </td> <td>Write Model-specific register. The MSR to write is specified in ECX, and the data to write is given in EDX:EAX. The instruction differs from the older <code>WRMSR</code> instruction in that it is not serializing. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="msrlist"><dfn>MSRLIST</dfn></dt><dd>Read/write multiple <a href="/wiki/Model-specific_register" title="Model-specific register">Model-specific registers</a>. Available in 64-bit mode only.</dd></dl> </td> <td><code>RDMSRLIST</code> </td> <td><code>F2 0F 01 C6</code> </td> <td>Read multiple MSRs. RSI points to a table of up to 64 MSR indexes to read (64 bits each), RDI points to a table of up to 64 data items that the MSR read-results will be written to (also 64 bits each), and RCX provides a 64-entry bitmap of which of the table entries to actually perform an MSR read for.<a href="#cite_note-msrlist_align-278">[v]</a> </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2"><a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a> </td></tr> <tr> <td><code>WRMSRLIST</code> </td> <td><code>F3 0F 01 C6</code> </td> <td>Write multiple MSRs. RSI points to a table of up to 64 MSR indexes to write (64 bits each), RDI points to a table of up to 64 data items to write into the MSRs (also 64 bits each), and RCX provides a 64-entry bitmap of which of the table entries to actually perform an MSR write for.<a href="#cite_note-msrlist_align-278">[v]</a>The instruction is not serializing. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="cmpccxadd"><dfn>CMPCCXADD</dfn></dt><dd>Atomically perform a compare - and a <a href="/wiki/Fetch-and-add" title="Fetch-and-add">fetch-and-add</a> if the condition is met. Available in 64-bit mode only.</dd></dl> </td> <td><code>CMPccXADD m32,r32,r32</code> <code>CMPccXADD m64,r64,r64</code>   </td> <td><code>VEX.128.66.0F38.W0 Ex /r</code> <code>VEX.128.66.0F38.W1 Ex /r</code> <a href="#cite_note-setcc_conds-279">[w]</a><a href="#cite_note-280">[x]</a>  </td> <td>Read value from memory, then compare to first register operand. If the comparison passes, then add the second register operand to the memory value. The instruction as a whole is performed atomically. The operation of <code>CMPccXADD [mem],reg1,reg2</code> is:<pre>temp1 := [mem] EFLAGS := CMP temp1, reg1 // sets EFLAGS like regular compare reg1 := temp1 if( condition ) [mem] := temp1 + reg2</pre> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a>, <a href="/wiki/Lunar_Lake" title="Lunar Lake">Lunar Lake</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="pbndkb"><dfn>PBNDKB</dfn></dt><dd>Platform Bind Key to Binary Large Object.Part of Intel TSE (Total Storage Encryption), and available in 64-bit mode only.</dd></dl> </td> <td><code>PBNDKB</code> </td> <td><code>NP 0F 01 C7</code> </td> <td>Bind information to a platform by encrypting it with a platform-specific wrapping key. The instruction takes as input the addresses to two 256-byte-aligned "bind structures" in RBX and RCX, reads the structure pointed to by RBX and writes a modified structure to the address given in RCX. If the instruction fails, it will set EFLAGS.ZF=1 and return an error code in EAX. If it is successful, it sets EFLAGS.ZF=0 and EAX=0. </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td><a href="/wiki/Lunar_Lake" title="Lunar Lake">Lunar Lake</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-wmt_hint-248">^ <a href="#cite_ref-wmt_hint_248-0">a</a> <a href="#cite_ref-wmt_hint_248-1">b</a> The branch hint mnemonics <code>HWNT</code> and <code>HST</code> are listed in early <a href="/wiki/Pentium_4#Willamette" title="Pentium 4">Willamette</a> documentation only<a href="#cite_note-246">[108]</a> - later Intel documentation lists the branch hint prefixes without assigning them a mnemonic.<a href="#cite_note-247">[109]</a> </li> <li id="cite_note-wmt_prefix-249">^ <a href="#cite_ref-wmt_prefix_249-0">a</a> <a href="#cite_ref-wmt_prefix_249-1">b</a> The <code>2E</code> and <code>3E</code> prefixes are interpreted as branch hints only when used with the <code>Jcc</code> conditional branch instructions (opcodes <code>70..7F</code> and <code>0F 80..8F</code>) - when used with other opcodes, they may take other meanings (e.g. for instructions with memory operands outside 64-bit mode, they will work as segment-override prefixes <code>CS:</code> and <code>DS:</code>, respectively). On processors that don't support branch hints, these prefixes are accepted but ignored when used with <code>Jcc</code>. </li> <li id="cite_note-250"><a href="#cite_ref-250">^</a> Branch hints are supported on all <a href="/wiki/NetBurst" title="NetBurst">NetBurst</a> (Pentium 4 family) processors - but not supported on any other known processor prior to their re-introduction in "Redwood Cove" CPUs, starting with "Meteor Lake" in 2023. </li> <li id="cite_note-254"><a href="#cite_ref-254">^</a> The leaf functions defined for <code>ENCLS</code> (selected by EAX) are: <table class="wikitable sortable"> <tbody><tr> <th>EAX</th> <th>Function </th></tr> <tr> <td>0 (ECREATE)</td> <td>Create an enclave </td></tr> <tr> <td>1 (EADD)</td> <td>Add a page </td></tr> <tr> <td>2 (EINIT)</td> <td>Initialize an enclave </td></tr> <tr> <td>3 (EREMOVE)</td> <td>Remove a page from EPC (Enclave Page Cache) </td></tr> <tr> <td>4 (EDBGRD)</td> <td>Read data by debugger </td></tr> <tr> <td>5 (EDBGWR)</td> <td>Write data by debugger </td></tr> <tr> <td>6 (EEXTEND)</td> <td>Extend EPC page measurement </td></tr> <tr> <td>7 (ELDB)</td> <td>Load an EPC page as blocked </td></tr> <tr> <td>8 (ELDU)</td> <td>Load an EPC page as unblocked </td></tr> <tr> <td>9 (EBLOCK)</td> <td>Block an EPC page </td></tr> <tr> <td>A (EPA)</td> <td>Add version array </td></tr> <tr> <td>B (EWB)</td> <td>Writeback/invalidate EPC page </td></tr> <tr> <td>C (ETRACK)</td> <td>Activate EBLOCK checks </td></tr> <tr> <th colspan="2">Added with SGX2 </th></tr> <tr> <td>D (EAUG)</td> <td>Add page to initialized enclave </td></tr> <tr> <td>E (EMODPTR)</td> <td>Restrict permissions of EPC page </td></tr> <tr> <td>F (EMODT)</td> <td>Change type of EPC page </td></tr> <tr> <th colspan="2">Added with OVERSUB<a href="#cite_note-sgx_oversub-252">[111]</a> </th></tr> <tr> <td>10 (ERDINFO)</td> <td>Read EPC page type/status info </td></tr> <tr> <td>11 (ETRACKC)</td> <td>Activate EBLOCK checks </td></tr> <tr> <td>12 (ELDBC)</td> <td>Load EPC page as blocked with enhanced error reporting </td></tr> <tr> <td>13 (ELDUC)</td> <td>Load EPC page as unblocked with enhanced error reporting </td></tr> <tr> <th colspan="2">Other </th></tr> <tr> <td>18 (EUPDATESVN)</td> <td>Update SVN (Security Version Number) after live microcode update<a href="#cite_note-253">[112]</a> </td></tr></tbody></table> Any unsupported value in EAX causes a #GP exception. </li> <li id="cite_note-256"><a href="#cite_ref-256">^</a> SGX is deprecated on desktop/laptop processors from 11th generation (<a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a>, <a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a>) onwards, but continues to be available on <a href="/wiki/Xeon" title="Xeon">Xeon</a>-branded server parts.<a href="#cite_note-255">[113]</a> </li> <li id="cite_note-259"><a href="#cite_ref-259">^</a> The leaf functions defined for <code>ENCLU</code> (selected by EAX) are: <table class="wikitable sortable"> <tbody><tr> <th>EAX</th> <th>Function </th></tr> <tr> <td>0 (EREPORT)</td> <td>Create a cryptographic report </td></tr> <tr> <td>1 (EGETKEY)</td> <td>Create a cryptographic key </td></tr> <tr> <td>2 (EENTER)</td> <td>Enter an Enclave </td></tr> <tr> <td>3 (ERESUME)</td> <td>Re-enter an Enclave </td></tr> <tr> <td>4 (EEXIT)</td> <td>Exit an Enclave </td></tr> <tr> <th colspan="2">Added with SGX2 </th></tr> <tr> <td>5 (EACCEPT)</td> <td>Accept changes to EPC page </td></tr> <tr> <td>6 (EMODPE)</td> <td>Extend EPC page permissions </td></tr> <tr> <td>7 (EACCEPTCOPY)</td> <td>Initialize pending page </td></tr> <tr> <th colspan="2">Added with TDX<a href="#cite_note-intel_tdx-258">[115]</a> </th></tr> <tr> <td>8 (EVERIFYREPORT2)</td> <td>Verify a cryptographic report of a trust domain </td></tr> <tr> <th colspan="2">Added with AEX-Notify </th></tr> <tr> <td>9 (EDECCSSA)</td> <td>Decrement TCS.CSSA </td></tr></tbody></table> Any unsupported value in EAX causes a #GP exception. The EENTER and ERESUME functions cannot be executed inside an SGX enclave – the other functions can only be executed inside an enclave. </li> <li id="cite_note-260"><a href="#cite_ref-260">^</a> <code>ENCLU</code> can only be executed in ring 3, not rings 0/1/2. </li> <li id="cite_note-261"><a href="#cite_ref-261">^</a> The leaf functions defined for <code>ENCLV</code> (selected by EAX) are: <table class="wikitable sortable"> <tbody><tr> <th>EAX</th> <th>Function </th></tr> <tr> <th colspan="2">Added with OVERSUB<a href="#cite_note-sgx_oversub-252">[111]</a> </th></tr> <tr> <td>0 (EDECVIRTCHILD)</td> <td>Decrement VIRTCHILDCNT in SECS </td></tr> <tr> <td>1 (EINCVIRTCHILD)</td> <td>Increment VIRTCHILDCNT in SECS </td></tr> <tr> <td>2 (ESETCONTEXT)</td> <td>Set ENCLAVECONTEXT field in SECS </td></tr></tbody></table> Any unsupported value in EAX causes a #GP exception. The <code>ENCLV</code> instruction is only present on systems that support the EPC Oversubscription Extensions to SGX ("OVERSUB"). </li> <li id="cite_note-262"><a href="#cite_ref-262">^</a> <code>ENCLV</code> is only available if Intel VMX operation is enabled with <code>VMXON</code>, and will produce #UD otherwise. </li> <li id="cite_note-263"><a href="#cite_ref-263">^</a> For <code>PTWRITE</code>, the write to the Processor Trace Packet will only happen if a set of enable-bits (the "TriggerEn", "ContextEn", "FilterEn" bits of the <code>RTIT_STATUS</code> MSR and the "PTWEn" bit of the <code>RTIT_CTL</code> MSR) are all set to 1. The <code>PTWRITE</code> instruction is indicated in the SDM to cause an #UD exception if the 66h instruction prefix is used, regardless of other prefixes. </li> <li id="cite_note-264"><a href="#cite_ref-264">^</a> The leaf functions defined for <code>PCONFIG</code> (selected by EAX) are: <table class="wikitable sortable"> <tbody><tr> <th>EAX</th> <th>Function </th></tr> <tr> <td>0</td> <td>MKTME_KEY_PROGRAM: Program key and encryption mode to use with an TME-MK Key ID. </td></tr> <tr> <th colspan="2">Added with TSE </th></tr> <tr> <td>1</td> <td>TSE_KEY_PROGRAM: Direct key programming for TSE. </td></tr> <tr> <td>2</td> <td>TSE_KEY_PROGRAM_WRAPPED: Wrapped key programming for TSE. </td></tr></tbody></table> Any unsupported value in EAX causes a #GP(0) exception. </li> <li id="cite_note-265"><a href="#cite_ref-265">^</a> For <code>CLDEMOTE</code>, the cache level that it will demote a cache line to is implementation-dependent. Since the instruction is considered a hint, it will execute as a NOP without any exceptions if the provided memory address is invalid or not in the L1 cache. It may also execute as a NOP under other implementation-dependent circumstances as well. On systems that do not support the CLDEMOTE extension, it executes as a NOP. </li> <li id="cite_note-268"><a href="#cite_ref-268">^</a> Intel documentation lists Tremont and Alder Lake as the processors in which CLDEMOTE was introduced. However, as of May 2022, no Tremont or Alder Lake models have been observed to have the CPUID feature bit for CLDEMOTE set, while several of them have the CPUID bit cleared.<a href="#cite_note-266">[116]</a> As of April 2023, the CPUID feature bit for CLDEMOTE has been observed to be set for Sapphire Rapids.<a href="#cite_note-267">[117]</a> </li> <li id="cite_note-269"><a href="#cite_ref-269">^</a> For <code>UMONITOR</code>, the operand size of the address argument is given by the address size, which may be overridden by the <code>67h</code> prefix. The default segment used is DS:, which can be overridden with a segment prefix. </li> <li id="cite_note-umwait_ctrl-270">^ <a href="#cite_ref-umwait_ctrl_270-0">a</a> <a href="#cite_ref-umwait_ctrl_270-1">b</a> For the <code>UMWAIT</code> and <code>TPAUSE</code> instructions, the operating system can use the <code>IA32_UMWAIT_CONTROL</code> MSR to limit the maximum amount of time that a single <code>UMWAIT</code>/<code>TPAUSE</code> invocation is permitted to wait. The <code>UMWAIT</code> and <code>TPAUSE</code> instructions will set <code>RFLAGS.CF</code> to 1 if they reached the <code>IA32_UMWAIT_CONTROL</code>-defined time limit and 0 otherwise. </li> <li id="cite_note-waitpkg_cr4tsd-271"><a href="#cite_ref-waitpkg_cr4tsd_271-0">^</a> <code>TPAUSE</code> and <code>UMWAIT</code> can be run outside Ring 0 only if <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.TSD</a>=0</code>. </li> <li id="cite_note-umwait_flags-272"><a href="#cite_ref-umwait_flags_272-0">^</a> For the register argument to the <code>UMWAIT</code> and <code>TPAUSE</code> instructions, the following flag bits are supported: <table class="wikitable sortable"> <tbody><tr> <th>Bits</th> <th>Usage </th></tr> <tr> <td>0</td> <td>Preferred optimization state. <ul><li>0 = C0.2 (slower wakeup, improves performance of other SMT threads on same core)</li> <li>1 = C0.1 (faster wakeup)</li></ul> </td></tr> <tr> <td>31:1</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">(Reserved) </td></tr></tbody></table> </li> <li id="cite_note-273"><a href="#cite_ref-273">^</a> While serialization can be performed with older instructions such as e.g. <code>CPUID</code> and <code>IRET</code>, these instructions perform additional functions, causing side-effects and reduced performance when stand-alone instruction serialization is needed. (<code>CPUID</code> additionally has the issue that it causes a mandatory #VMEXIT when executed under virtualization, which causes a very large overhead.) The <code>SERIALIZE</code> instruction performs serialization only, avoiding these added costs. </li> <li id="cite_note-274"><a href="#cite_ref-274">^</a> A bitmap of CPU history components that can be reset through <code>HRESET</code> is provided by CPUID.(EAX=20h,ECX=0):EBX. As of July 2023, the following bits are defined: <table class="wikitable sortable"> <tbody><tr> <th>Bit</th> <th>Usage </th></tr> <tr> <td>0</td> <td>Intel Thread Director history </td></tr> <tr> <td>31:1</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">(Reserved) </td></tr></tbody></table> </li> <li id="cite_note-275"><a href="#cite_ref-275">^</a> The register argument to <code>SENDUIPI</code> is an index to pick an entry from the UITT (User-Interrupt Target Table, a table specified by the new <code>UINTR_TT</code> and <code>UINT_MISC</code> <a href="/wiki/Model-specific_register" title="Model-specific register">MSRs.</a>) </li> <li id="cite_note-276"><a href="#cite_ref-276">^</a> On <a href="/wiki/Sapphire_Rapids_(microprocessor)" class="mw-redirect" title="Sapphire Rapids (microprocessor)">Sapphire Rapids</a> processors, the <code>UIRET</code> instruction always sets UIF (User Interrupt Flag) to 1. On <a href="/wiki/Sierra_Forest" title="Sierra Forest">Sierra Forest</a> and later processors, <code>UIRET</code> will set UIF to the value of bit 1 of the value popped off the stack for RFLAGS - this functionality is indicated by <code>CPUID.(EAX=7,ECX=1):EDX[17]</code>. </li> <li id="cite_note-msrlist_align-278">^ <a href="#cite_ref-msrlist_align_278-0">a</a> <a href="#cite_ref-msrlist_align_278-1">b</a> For the <code>RDMSRLIST</code> and <code>WRMSRLIST</code> instructions, the addresses specified in the RSI and RDI registers must be 8-byte aligned. </li> <li id="cite_note-setcc_conds-279"><a href="#cite_ref-setcc_conds_279-0">^</a> The condition codes supported for the <code>CMPccXADD</code> instructions (opcode <code>VEX.128.66.0F38 Ex /r</code> with the x nibble specifying the condition) are: <table class="wikitable sortable"> <tbody><tr> <th>x</th> <th>cc</th> <th>Condition (<a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a>) </th></tr> <tr> <td>0</td> <td>O</td> <td>OF=1: "Overflow" </td></tr> <tr> <td>1</td> <td>NO</td> <td>OF=0: "Not Overflow" </td></tr> <tr> <td>2</td> <td>B</td> <td>CF=1: "Below" </td></tr> <tr> <td>3</td> <td>NB</td> <td>CF=0: "Not Below" </td></tr> <tr> <td>4</td> <td>Z</td> <td>ZF=1: "Zero" </td></tr> <tr> <td>5</td> <td>NZ</td> <td>ZF=0: "Not Zero" </td></tr> <tr> <td>6</td> <td>BE</td> <td>(CF=1 or ZF=1): "Below or Equal" </td></tr> <tr> <td>7</td> <td>NBE</td> <td>(CF=0 and ZF=0): "Not Below or Equal" </td></tr> <tr> <td>8</td> <td>S</td> <td>SF=1: "Sign" </td></tr> <tr> <td>9</td> <td>NS</td> <td>SF=0: "Not Sign" </td></tr> <tr> <td>A</td> <td>P</td> <td>PF=1: "Parity" </td></tr> <tr> <td>B</td> <td>NP</td> <td>PF=0: "Not Parity" </td></tr> <tr> <td>C</td> <td>L</td> <td>SF≠OF: "Less" </td></tr> <tr> <td>D</td> <td>NL</td> <td>SF=OF: "Not Less" </td></tr> <tr> <td>E</td> <td>LE</td> <td>(ZF=1 or SF≠OF): "Less or Equal" </td></tr> <tr> <td>F</td> <td>NLE</td> <td>(ZF=0 and SF=OF): "Not Less or Equal" </td></tr></tbody></table> </li> <li id="cite_note-280"><a href="#cite_ref-280">^</a> Even though the <code>CMPccXADD</code> instructions perform a locked memory operation, they do not require or accept the <code>LOCK</code> (<code>F0h</code>) prefix - attempting to use this prefix results in #UD. </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading4"><h4 id="Added_with_other_AMD-specific_extensions">Added with other AMD-specific extensions</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=17" title="Edit section: Added with other AMD-specific extensions">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction Set Extension</th> <th>Instruction mnemonics</th> <th>Opcode</th> <th>Instruction description</th> <th><a href="/wiki/Protection_ring" title="Protection ring">Ring</a></th> <th>Added in </th></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="altmovcr8"><dfn>AltMovCr8</dfn></dt><dd>Alternative mechanism to access the CR8 <a href="/wiki/Control_register" title="Control register">control register</a>.<a href="#cite_note-281">[a]</a></dd></dl> </td> <td><code>MOV reg,CR8</code> </td> <td><code>F0 0F 20 /0</code><a href="#cite_note-altmovcr8_encoding-282">[b]</a> </td> <td>Read the CR8 register. </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2"><a href="/wiki/AMD_K8" title="AMD K8">K8</a><a href="#cite_note-283">[c]</a> </td></tr> <tr> <td><code>MOV CR8,reg</code> </td> <td><code>F0 0F 22 /0</code><a href="#cite_note-altmovcr8_encoding-282">[b]</a> </td> <td>Write to the CR8 register. </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="monitorx"><dfn>MONITORX</dfn></dt><dd>Monitor a memory location for writes in user mode.</dd></dl> </td> <td><code>MONITORX</code> </td> <td><code>NP 0F 01 FA</code> </td> <td>Start monitoring a memory location for memory writes. Similar to older <code>MONITOR</code>, except available in user mode. </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td rowspan="2"><a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> </td></tr> <tr> <td><code>MWAITX</code> </td> <td><code>NP 0F 01 FB</code> </td> <td>Wait for a write to a monitored memory location previously specified with <code>MONITORX</code>. <code>MWAITX</code> differs from the older <code>MWAIT</code> instruction mainly in that it runs in user mode and that it can accept an optional timeout argument (given in TSC time units) in EBX (enabled by setting bit[1] of ECX to 1.) </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="clzero"><dfn>CLZERO</dfn></dt><dd>Zero out full cache line.</dd></dl> </td> <td><code>CLZERO rAX</code> </td> <td><code>NP 0F 01 FC</code> </td> <td>Write zeroes to all bytes in a memory region that has the size and alignment of a CPU cache line and contains the byte addressed by DS:rAX.<a href="#cite_note-285">[d]</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen 1</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="rdpru"><dfn>RDPRU</dfn></dt><dd>Read processor register in user mode.</dd></dl> </td> <td><code>RDPRU</code> </td> <td><code>NP 0F 01 FD</code> </td> <td>Read selected <a href="/wiki/Model-specific_register" title="Model-specific register">MSRs</a> (mainly performance counters) in user mode. ECX specifies which register to read.<a href="#cite_note-286">[e]</a> The value of the MSR is returned in EDX:EAX. </td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">Usually 3<a href="#cite_note-287">[f]</a> </td> <td><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="mcommit"><dfn>MCOMMIT</dfn></dt><dd>Commit Stores To Memory.</dd></dl> </td> <td><code>MCOMMIT</code> </td> <td><code>F3 0F 01 FA</code> </td> <td>Ensure that all preceding stores in thread have been committed to memory, and that any errors encountered by these stores have been signalled to any associated error logging resources. The set of errors that can be reported and the logging mechanism are platform-specific. Sets <code>EFLAGS.CF</code> to 0 if any errors occurred, 1 otherwise. </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3 </td> <td><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> </td></tr> <tr> <th colspan="6"> </th></tr> <tr> <td rowspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1228772891"> <dl class="glossary"><dt id="invlpgb"><dfn>INVLPGB</dfn></dt><dd>Invalidate TLB Entries with broadcast.</dd></dl> </td> <td><code>INVLPGB</code> </td> <td><code>NP 0F 01 FE</code> </td> <td>Invalidate TLB Entries for a range of pages, with broadcast. The invalidation is performed on the processor executing the instruction, and also broadcast to all other processors in the system. rAX takes the virtual address to invalidate and some additional flags, ECX takes the number of pages to invalidate, and EDX specifies ASID and PCID to perform TLB invalidation for. </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">0 </td> <td rowspan="2"><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> </td></tr> <tr> <td><code>TLBSYNC</code> </td> <td><code>NP 0F 01 FF</code> </td> <td>Synchronize TLB invalidations. Wait until all TLB invalidations signalled by preceding invocations of the <code>INVLPGB</code> instruction on the same logical processor have been responded to by all processors in the system. Instruction is serializing. </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-281"><a href="#cite_ref-281">^</a> The standard way to access the CR8 register is to use an encoding that makes use of the <code>REX.R</code> prefix, e.g. <code>44 0F 20 07</code> (<code>MOV RDI,CR8</code>). However, the <code>REX.R</code> prefix is only available in 64-bit mode. The AltMovCr8 extension adds an additional method to access CR8, using the <code>F0</code> (<code>LOCK</code>) prefix instead of <code>REX.R</code> – this provides access to CR8 outside 64-bit mode. </li> <li id="cite_note-altmovcr8_encoding-282">^ <a href="#cite_ref-altmovcr8_encoding_282-0">a</a> <a href="#cite_ref-altmovcr8_encoding_282-1">b</a> Like other variants of MOV to/from the CRx registers, the AltMovCr8 encodings ignore the top 2 bits of the instruction's ModR/M byte, and always execute as if these two bits are set to <code>11b</code>. The AltMovCr8 encodings are available in 64-bit mode. However, combining the <code>LOCK</code> prefix with the <code>REX.R</code> prefix is not permitted and will cause an #UD exception. </li> <li id="cite_note-283"><a href="#cite_ref-283">^</a> Support for AltMovCR8 was added in stepping F of the AMD K8, and is not available on earlier steppings. </li> <li id="cite_note-285"><a href="#cite_ref-285">^</a> For <code>CLZERO</code>, the address size and 67h prefix control whether to use AX, EAX or RAX as address. The default segment DS: can be overridden by a segment-override prefix. The provided address does not need to be aligned – hardware will align it as necessary. The <code>CLZERO</code> instruction is intended for recovery from otherwise-fatal Machine Check errors. It is non-cacheable, cannot be used to allocate a cache line without a memory access, and should not be used for fast memory clears.<a href="#cite_note-284">[119]</a> </li> <li id="cite_note-286"><a href="#cite_ref-286">^</a> The register numbering used by <code>RDPRU</code> does not necessarily match that of <code>RDMSR</code>/<code>WRMSR</code>. The registers supported by <code>RDPRU</code> as of December 2022 are: <table class="wikitable sortable"> <tbody><tr> <th>ECX</th> <th>Register </th></tr> <tr> <td>0</td> <td>MPERF (MSR 0E7h: Maximum Performance Frequency Clock Count) </td></tr> <tr> <td>1</td> <td>APERF (MSR 0E8h: Actual Performance Frequency Clock Count) </td></tr></tbody></table> Unsupported values in ECX return 0. </li> <li id="cite_note-287"><a href="#cite_ref-287">^</a> If <code><a href="/wiki/Control_register#CR4" title="Control register">CR4.TSD</a>=1</code>, then the <code>RDPRU</code> instruction can only run in ring 0. </li> </ol></div></div><div style="width:100%; height:1em; clear:both;"></div> <div class="mw-heading mw-heading2"><h2 id="x87_floating-point_instructions">x87 floating-point instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=18" title="Edit section: x87 floating-point instructions">edit</a>]</div> The <a href="/wiki/X87" title="X87">x87</a> coprocessor, if present, provides support for floating-point arithmetic. The coprocessor provides eight data registers, each holding one 80-bit floating-point value (1 sign bit, 15 exponent bits, 64 mantissa bits) – these registers are organized as a stack, with the top-of-stack register referred to as "st" or "st(0)", and the other registers referred to as st(1),st(2),...st(7). It additionally provides a number of control and status registers, including "PC" (precision control, to control whether floating-point operations should be rounded to 24, 53 or 64 mantissa bits) and "RC" (rounding control, to pick rounding-mode: round-to-zero, round-to-positive-infinity, round-to-negative-infinity, round-to-nearest-even) and a 4-bit condition code register "CC", whose four bits are individually referred to as C0,C1,C2 and C3). Not all of the arithmetic instructions provided by x87 obey PC and RC. <div class="mw-heading mw-heading3"><h3 id="Original_8087_instructions">Original <a href="/wiki/8087" class="mw-redirect" title="8087">8087</a> instructions</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=19" title="Edit section: Original 8087 instructions">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction description </th> <th>Mnemonic </th> <th>Opcode </th> <th colspan="2">Additional items </th></tr> <tr> <th colspan="3"></th> <th colspan="2"> </th></tr> <tr> <th colspan="3">x87 Non-Waiting<a href="#cite_note-289">[a]</a> FPU Control Instructions</th> <th colspan="2">Waiting mnemonic<a href="#cite_note-290">[b]</a> </th></tr> <tr> <td>Initialize x87 FPU </td> <td><code>FNINIT</code> </td> <td><code>DB E3</code></td> <td colspan="2"><code>FINIT</code> </td></tr> <tr> <td>Load x87 Control Word </td> <td><code>FLDCW m16</code></td> <td><code>D9 /5</code></td> <td colspan="2" style="background: #EEE; color:black; vertical-align: middle; text-align: center;" class="table-cast">(none) </td></tr> <tr> <td>Store x87 Control Word </td> <td><code>FNSTCW m16</code></td> <td><code>D9 /7</code></td> <td colspan="2"><code>FSTCW</code> </td></tr> <tr> <td>Store x87 Status Word </td> <td><code>FNSTSW m16</code> </td> <td><code>DD /7</code></td> <td colspan="2"><code>FSTSW</code> </td></tr> <tr> <td>Clear x87 Exception Flags </td> <td><code>FNCLEX</code> </td> <td><code>DB E2</code></td> <td colspan="2"><code>FCLEX</code> </td></tr> <tr> <td>Load x87 FPU Environment </td> <td><code>FLDENV m112/m224</code><a href="#cite_note-x87_environment_size-291">[c]</a> </td> <td><code>D9 /4</code></td> <td colspan="2" style="background: #EEE; color:black; vertical-align: middle; text-align: center;" class="table-cast">(none) </td></tr> <tr> <td>Store x87 FPU Environment </td> <td><code>FNSTENV m112/m224</code><a href="#cite_note-x87_environment_size-291">[c]</a> </td> <td><code>D9 /6</code></td> <td colspan="2"><code>FSTENV</code> </td></tr> <tr> <td>Save x87 FPU State, then initialize x87 FPU </td> <td><code>FNSAVE m752/m864</code><a href="#cite_note-x87_environment_size-291">[c]</a> </td> <td><code>DD /6</code></td> <td colspan="2"><code>FSAVE</code> </td></tr> <tr> <td>Restore x87 FPU State </td> <td><code>FRSTOR m752/m864</code><a href="#cite_note-x87_environment_size-291">[c]</a> </td> <td><code>DD /4</code></td> <td colspan="2" style="background: #EEE; color:black; vertical-align: middle; text-align: center;" class="table-cast">(none) </td></tr> <tr> <td>Enable Interrupts (8087 only)<a href="#cite_note-feni_8087_only-295">[d]</a> </td> <td><code>FNENI</code></td> <td><code>DB E0</code></td> <td colspan="2"><code>FENI</code> </td></tr> <tr> <td>Disable Interrupts (8087 only)<a href="#cite_note-feni_8087_only-295">[d]</a> </td> <td><code>FNDISI</code></td> <td><code>DB E1</code></td> <td colspan="2"><code>FDISI</code> </td></tr> <tr> <th colspan="3"></th> <th colspan="2"> </th></tr> <tr> <th colspan="3">x87 Floating-point Load/Store/Move Instructions</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td rowspan="4">Load floating-point value onto stack </td> <td><code>FLD m32</code></td> <td><code>D9 /0</code></td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FLD m64</code></td> <td><code>DD /0</code> </td></tr> <tr> <td><code>FLD m80</code></td> <td><code>DB /5</code> </td></tr> <tr> <td><code>FLD st(i)</code></td> <td><code>D9 C0+i</code> </td></tr> <tr> <td rowspan="3">Store top-of-stack floating-point value to memory or stack register </td> <td><code>FST m32</code></td> <td><code>D9 /2</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FST m64</code></td> <td><code>DD /2</code> </td></tr> <tr> <td><code>FST st(i)</code><a href="#cite_note-x87_amd_fstp-296">[e]</a> </td> <td><code>DD D0+i</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="6">Store top-of-stack floating-point value to memory or stack register, then pop </td> <td><code>FSTP m32</code></td> <td><code>D9 /3</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FSTP m64</code></td> <td><code>DD /3</code> </td></tr> <tr> <td><code>FSTP m80</code><a href="#cite_note-x87_amd_fstp-296">[e]</a> </td> <td><code>DB /7</code></td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="3"><code>FSTP st(i)</code><a href="#cite_note-x87_amd_fstp-296">[e]</a><a href="#cite_note-297">[f]</a> </td> <td><code>DD D8+i</code> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DF D0+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DF D8+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td>Push +0.0 onto stack </td> <td><code>FLDZ</code></td> <td><code>D9 EE</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Push +1.0 onto stack </td> <td><code>FLD1</code></td> <td><code>D9 E8</code> </td></tr> <tr> <td>Push <a href="/wiki/Pi" title="Pi">π</a> (approximately 3.14159) onto stack </td> <td><code>FLDPI</code></td> <td><code>D9 EB</code></td> <td rowspan="5" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="5" style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">387<a href="#cite_note-x87_rounding_387-304">[h]</a> </td></tr> <tr> <td>Push <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \log _{2}\left(10\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mrow> <mo>(</mo> <mn>10</mn> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \log _{2}\left(10\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/ac0f01f6c6a3684cbd7194eb79c062db36f73bf3" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:8.16ex; height:2.843ex;" alt="{\displaystyle \log _{2}\left(10\right)}"> (approximately 3.32193) onto stack </td> <td><code>FLDL2T</code></td> <td><code>D9 E9</code> </td></tr> <tr> <td>Push <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \log _{2}\left(e\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mrow> <mo>(</mo> <mi>e</mi> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \log _{2}\left(e\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a10eb00a2ba6f57a2aa48001c65a5b0728d0540c" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:6.919ex; height:2.843ex;" alt="{\displaystyle \log _{2}\left(e\right)}"> (approximately 1.44269) onto stack </td> <td><code>FLDL2E</code></td> <td><code>D9 EA</code> </td></tr> <tr> <td>Push <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \log _{10}\left(2\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>10</mn> </mrow> </msub> <mo>⁡</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \log _{10}\left(2\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a11ac9b1e50fe6c9dac93d3a9f78401a47a0b826" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:7.82ex; height:2.843ex;" alt="{\displaystyle \log _{10}\left(2\right)}"> (approximately 0.30103) onto stack </td> <td><code>FLDLG2</code></td> <td><code>D9 EC</code> </td></tr> <tr> <td>Push <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \ln \left(2\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>ln</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mn>2</mn> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \ln \left(2\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/f638f7cc21a997e58b02fc8f7b2cfe29dee4faac" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:4.911ex; height:2.843ex;" alt="{\displaystyle \ln \left(2\right)}"> (approximately 0.69315) onto stack </td> <td><code>FLDLN2</code></td> <td><code>D9 ED</code> </td></tr> <tr> <td rowspan="3">Exchange top-of-stack register with other stack register </td> <td rowspan="3"><code>FXCH st(i)</code><a href="#cite_note-x87_optarg-305">[i]</a><a href="#cite_note-306">[j]</a> </td> <td><code>D9 C8+i</code> </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DD C8+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DF C8+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <th colspan="3">x87 Integer Load/Store Instructions</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td rowspan="3">Load signed integer value onto stack from memory, with conversion to floating-point </td> <td><code>FILD m16</code></td> <td><code>DF /0</code></td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FILD m32</code></td> <td><code>DB /0</code> </td></tr> <tr> <td><code>FILD m64</code></td> <td><code>DF /5</code> </td></tr> <tr> <td rowspan="2">Store top-of-stack value to memory, with conversion to signed integer </td> <td><code>FIST m16</code></td> <td><code>DF /2</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FIST m32</code></td> <td><code>DB /2</code> </td></tr> <tr> <td rowspan="3">Store top-of-stack value to memory, with conversion to signed integer, then pop stack </td> <td><code>FISTP m16</code></td> <td><code>DF /3</code></td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FISTP m32</code></td> <td><code>DB /3</code> </td></tr> <tr> <td><code>FISTP m64</code></td> <td><code>DF /7</code> </td></tr> <tr> <td>Load 18-digit Binary-Coded-Decimal integer value onto stack from memory, with conversion to floating-point </td> <td><code>FBLD m80</code><a href="#cite_note-307">[k]</a> </td> <td><code>DF /4</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Store top-of-stack value to memory, with conversion to 18-digit Binary-Coded-Decimal integer, then pop stack </td> <td><code>FBSTP m80</code></td> <td><code>DF /6</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#bfd; color:black; vertical-align:middle; text-align:center;" class="table-yes2">387<a href="#cite_note-x87_rounding_387-304">[h]</a> </td></tr> <tr> <th colspan="3">x87 Basic Arithmetic Instructions</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td rowspan="4">Floating-point add <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- dst + src</code></dd></dl> </td> <td><code>FADD m32</code></td> <td><code>D8 /0</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FADD m64</code></td> <td><code>DC /0</code> </td></tr> <tr> <td><code>FADD st,st(i)</code></td> <td><code>D8 C0+i</code> </td></tr> <tr> <td><code>FADD st(i),st</code></td> <td><code>DC C0+i</code> </td></tr> <tr> <td rowspan="4">Floating-point multiply <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- dst * src</code></dd></dl> </td> <td><code>FMUL m32</code></td> <td><code>D8 /1</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FMUL m64</code></td> <td><code>DC /1</code> </td></tr> <tr> <td><code>FMUL st,st(i)</code></td> <td><code>D8 C8+i</code> </td></tr> <tr> <td><code>FMUL st(i),st</code></td> <td><code>DC C8+i</code> </td></tr> <tr> <td rowspan="4">Floating-point subtract <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- dst – src</code></dd></dl> </td> <td><code>FSUB m32</code></td> <td><code>D8 /4</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FSUB m64</code></td> <td><code>DC /4</code> </td></tr> <tr> <td><code>FSUB st,st(i)</code></td> <td><code>D8 E0+i</code> </td></tr> <tr> <td><code>FSUB st(i),st</code></td> <td><code>DC E8+i</code> </td></tr> <tr> <td rowspan="4">Floating-point reverse subtract <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- src – dst</code></dd></dl> </td> <td><code>FSUBR m32</code></td> <td><code>D8 /5</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FSUBR m64</code></td> <td><code>DC /5</code> </td></tr> <tr> <td><code>FSUBR st,st(i)</code></td> <td><code>D8 E8+i</code> </td></tr> <tr> <td><code>FSUBR st(i),st</code></td> <td><code>DC E0+i</code> </td></tr> <tr> <td rowspan="4">Floating-point divide<a href="#cite_note-pentium_fdiv-309">[l]</a> <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- dst / src</code></dd></dl> </td> <td><code>FDIV m32</code></td> <td><code>D8 /6</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FDIV m64</code></td> <td><code>DC /6</code> </td></tr> <tr> <td><code>FDIV st,st(i)</code></td> <td><code>D8 F0+i</code> </td></tr> <tr> <td><code>FDIV st(i),st</code></td> <td><code>DC F8+i</code> </td></tr> <tr> <td rowspan="4">Floating-point reverse divide <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">dst <- src / dst</code></dd></dl> </td> <td><code>FDIVR m32</code></td> <td><code>D8 /7</code></td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FDIVR m64</code></td> <td><code>DC /7</code> </td></tr> <tr> <td><code>FDIVR st,st(i)</code></td> <td><code>D8 F8+i</code> </td></tr> <tr> <td><code>FDIVR st(i),st</code></td> <td><code>DC F0+i</code> </td></tr> <tr> <td rowspan="4">Floating-point compare <dl><dd><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">CC <- result_of( st(0) – src )</code> Same operation as subtract, except that it updates the x87 CC status register instead of any of the FPU stack registers</dd></dl> </td> <td><code>FCOM m32</code></td> <td><code>D8 /2</code></td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FCOM m64</code></td> <td><code>DC /2</code> </td></tr> <tr> <td rowspan="2"><code>FCOM st(i)</code><a href="#cite_note-x87_optarg-305">[i]</a> </td> <td><code>D8 D0+i</code> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DC D0+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <th colspan="3">x87 Basic Arithmetic Instructions with Stack Pop</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td>Floating-point add and pop </td> <td><code>FADDP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE C0+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point multiply and pop </td> <td><code>FMULP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE C8+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point subtract and pop </td> <td><code>FSUBP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE E8+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point reverse-subtract and pop </td> <td><code>FSUBRP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE E0+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point divide and pop </td> <td><code>FDIVP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE F8+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point reverse-divide and pop </td> <td><code>FDIVRP st(i),st</code><a href="#cite_note-x87_optarg-305">[i]</a></td> <td><code>DE F0+i</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td rowspan="5">Floating-point compare and pop </td> <td><code>FCOMP m32</code></td> <td><code>D8 /3</code></td> <td rowspan="5" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FCOMP m64</code></td> <td><code>DC /3</code> </td></tr> <tr> <td rowspan="3"><code>FCOMP st(i)</code><a href="#cite_note-x87_optarg-305">[i]</a> </td> <td><code>D8 D8+i</code> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DC D8+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td style="background: #BFE; color:black; vertical-align: middle; text-align:" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DE D0+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td>Floating-point compare to st(1), then pop twice </td> <td><code>FCOMPP</code></td> <td><code>DE D9</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th colspan="3">x87 Basic Arithmetic Instructions with Integer Source Argument</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td rowspan="2">Floating-point add by integer </td> <td><code>FIADD m16</code></td> <td><code>DA /0</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FIADD m32</code></td> <td><code>DE /0</code> </td></tr> <tr> <td rowspan="2">Floating-point multiply by integer </td> <td><code>FIMUL m16</code></td> <td><code>DA /1</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FIMUL m32</code></td> <td><code>DE /1</code> </td></tr> <tr> <td rowspan="2">Floating-point subtract by integer </td> <td><code>FISUB m16</code></td> <td><code>DA /4</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FISUB m32</code></td> <td><code>DE /4</code> </td></tr> <tr> <td rowspan="2">Floating-point reverse-subtract by integer </td> <td><code>FISUBR m16</code></td> <td><code>DA /5</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FISUBR m32</code></td> <td><code>DE /5</code> </td></tr> <tr> <td rowspan="2">Floating-point divide by integer </td> <td><code>FIDIV m16</code></td> <td><code>DA /6</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FIDIV m32</code></td> <td><code>DE /6</code> </td></tr> <tr> <td rowspan="2">Floating-point reverse-divide by integer </td> <td><code>FIDIVR m16</code></td> <td><code>DA /7</code></td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><code>FIDIVR m32</code></td> <td><code>DE /7</code> </td></tr> <tr> <td rowspan="2">Floating-point compare to integer </td> <td><code>FICOM m16</code></td> <td><code>DA /2</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FICOM m32</code></td> <td><code>DE /2</code> </td></tr> <tr> <td rowspan="2">Floating-point compare to integer, and stack pop </td> <td><code>FICOMP m16</code> </td> <td><code>DA /3</code></td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><code>FICOMP m32</code> </td> <td><code>DE /3</code> </td></tr> <tr> <th colspan="3">x87 Additional Arithmetic Instructions</th> <th>precision control</th> <th>rounding control </th></tr> <tr> <td>Floating-point change sign </td> <td><code>FCHS</code></td> <td><code>D9 E0</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Floating-point absolute value </td> <td><code>FABS</code></td> <td><code>D9 E1</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Floating-point compare top-of-stack value to 0 </td> <td><code>FTST</code></td> <td><code>D9 E4</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Classify top-of-stack st(0) register value. The classification result is stored in the x87 CC register.<a href="#cite_note-310">[m]</a> </td> <td><code>FXAM</code></td> <td><code>D9 E5</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Split the st(0) value into two values E and M representing the exponent and mantissa of st(0). The split is done such that <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle M*2^{E}=st(0)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>M</mi> <mo>∗</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mi>E</mi> </mrow> </msup> <mo>=</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle M*2^{E}=st(0)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/1e7732085a9d17db9e278cf7a224aea9557dca6f" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:15.287ex; height:3.176ex;" alt="{\displaystyle M*2^{E}=st(0)}">, where E is an integer and M is a number whose absolute value is within the range <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 1\leq \left|M\right|<2}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mn>1</mn> <mo>≤</mo> <mrow> <mo>|</mo> <mi>M</mi> <mo>|</mo> </mrow> <mo><</mo> <mn>2</mn> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 1\leq \left|M\right|<2}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/c1c9cbe74d5f35b2e880dfa119e82ba154a0bdce" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:12.258ex; height:2.843ex;" alt="{\displaystyle 1\leq \left|M\right|<2}">.  <a href="#cite_note-311">[n]</a> st(0) is then replaced with E, after which M is pushed onto the stack. </td> <td><code>FXTRACT</code></td> <td><code>D9 F4</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td>Floating-point partial<a href="#cite_note-312">[o]</a> remainder (not <a href="/wiki/IEEE_754" title="IEEE 754">IEEE 754</a> compliant):<math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle Q\leftarrow {\mathtt {IntegerRoundToZero}}\left({\frac {st(0)}{st(1)}}\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>Q</mi> <mo stretchy="false">←</mo> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">I</mi> <mi mathvariant="monospace">n</mi> <mi mathvariant="monospace">t</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">g</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">r</mi> <mi mathvariant="monospace">R</mi> <mi mathvariant="monospace">o</mi> <mi mathvariant="monospace">u</mi> <mi mathvariant="monospace">n</mi> <mi mathvariant="monospace">d</mi> <mi mathvariant="monospace">T</mi> <mi mathvariant="monospace">o</mi> <mi mathvariant="monospace">Z</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">r</mi> <mi mathvariant="monospace">o</mi> </mrow> </mrow> <mrow> <mo>(</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> </mrow> </mfrac> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle Q\leftarrow {\mathtt {IntegerRoundToZero}}\left({\frac {st(0)}{st(1)}}\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/26200d81648fb4327f04968587950dc5483cea51" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.671ex; width:36.968ex; height:6.509ex;" alt="{\displaystyle Q\leftarrow {\mathtt {IntegerRoundToZero}}\left({\frac {st(0)}{st(1)}}\right)}"><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(0)\leftarrow st(0)-st(1)*Q}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo>−</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo>∗</mo> <mi>Q</mi> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(0)\leftarrow st(0)-st(1)*Q}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/6f95f390a2f7e71b3b67381b36e150edc3c84cb7" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:25.193ex; height:2.843ex;" alt="{\displaystyle st(0)\leftarrow st(0)-st(1)*Q}"> </td> <td><code>FPREM</code></td> <td><code>D9 F8</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—<a href="#cite_note-313">[p]</a> </td></tr> <tr> <td>Floating-point <a href="/wiki/Square_root" title="Square root">square root</a> </td> <td><code>FSQRT</code></td> <td><code>D9 FA</code></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point round to integer </td> <td><code>FRNDINT</code></td> <td><code>D9 FC</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Floating-point power-of-2 scaling. Rounds the value of st(1) to integer with round-to-zero, then uses it as a scale factor for st(0):<a href="#cite_note-314">[q]</a><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(0)\leftarrow st(0)*2^{{\mathtt {IntegerRoundToZero}}\left(st(1)\right)}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo>∗</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mi mathvariant="monospace">I</mi> <mi mathvariant="monospace">n</mi> <mi mathvariant="monospace">t</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">g</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">r</mi> <mi mathvariant="monospace">R</mi> <mi mathvariant="monospace">o</mi> <mi mathvariant="monospace">u</mi> <mi mathvariant="monospace">n</mi> <mi mathvariant="monospace">d</mi> <mi mathvariant="monospace">T</mi> <mi mathvariant="monospace">o</mi> <mi mathvariant="monospace">Z</mi> <mi mathvariant="monospace">e</mi> <mi mathvariant="monospace">r</mi> <mi mathvariant="monospace">o</mi> </mrow> </mrow> <mrow> <mo>(</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(0)\leftarrow st(0)*2^{{\mathtt {IntegerRoundToZero}}\left(st(1)\right)}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/992e95f3f49f3258cd2d43c58fdad86f627d4628" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:37.287ex; height:3.343ex;" alt="{\displaystyle st(0)\leftarrow st(0)*2^{{\mathtt {IntegerRoundToZero}}\left(st(1)\right)}}"> </td> <td><code>FSCALE</code></td> <td><code>D9 FD</code></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<a href="#cite_note-315">[r]</a> </td></tr> <tr> <th colspan="3"></th> <th colspan="2"> </th></tr> <tr> <th colspan="3">x87 Transcendental Instructions<a href="#cite_note-316">[s]</a></th> <th colspan="2">Source operand range restriction </th></tr> <tr> <td>Base-2 exponential minus 1, with extra precision for st(0) close to 0:<math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(0)\leftarrow 2^{st(0)}-1}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> </msup> <mo>−</mo> <mn>1</mn> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(0)\leftarrow 2^{st(0)}-1}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/e8809e32510ed6c0a62730f34c13cc43fac3b06e" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:17.38ex; height:3.343ex;" alt="{\displaystyle st(0)\leftarrow 2^{st(0)}-1}"> </td> <td><code>F2XM1</code></td> <td><code>D9 F0</code> </td> <td colspan="2">8087: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 0\leq st(0)\leq {\frac {1}{2}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mn>0</mn> <mo>≤</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo>≤</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 0\leq st(0)\leq {\frac {1}{2}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a0b9d7deeb36881e65675399d3a4906e554b88c1" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:14.26ex; height:5.176ex;" alt="{\displaystyle 0\leq st(0)\leq {\frac {1}{2}}}"> 80387: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle -1\leq st(0)\leq 1}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo>−</mo> <mn>1</mn> <mo>≤</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo>≤</mo> <mn>1</mn> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle -1\leq st(0)\leq 1}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/5b80f0c3fac446a39566d253e9666a587a871f7b" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:15.232ex; height:2.843ex;" alt="{\displaystyle -1\leq st(0)\leq 1}"> </td></tr> <tr> <td>Base-2 <a href="/wiki/Logarithm" title="Logarithm">Logarithm</a>:<math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo>∗</mo> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/1663c680eaef2ff782bb4a499b9c6854896f0d1f" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:26.35ex; height:2.843ex;" alt="{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)\right)}">followed by stack pop </td> <td><code>FYL2X</code><a href="#cite_note-x87_fyl2x_error-317">[t]</a> </td> <td><code>D9 F1</code></td> <td colspan="2">no restrictions </td></tr> <tr> <td>Partial Tangent: Computes from st(0) a pair of values X and Y, such that<math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \tan \left(st(0)\right)={\frac {Y}{X}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>tan</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> <mo>=</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mi>Y</mi> <mi>X</mi> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \tan \left(st(0)\right)={\frac {Y}{X}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/624cad8017d87cf49596d16a064e1b562477fb2d" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:15.985ex; height:5.176ex;" alt="{\displaystyle \tan \left(st(0)\right)={\frac {Y}{X}}}">The Y value replaces the top-of-stack value, and then X is pushed onto the stack. On 80387 and later x87, but not original 8087, X is always 1.0 </td> <td><code>FPTAN</code></td> <td><code>D9 F2</code> </td> <td colspan="2">8087: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 0\leq \left|st(0)\right|\leq {\frac {\pi }{4}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mn>0</mn> <mo>≤</mo> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo>≤</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mi>π</mi> <mn>4</mn> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 0\leq \left|st(0)\right|\leq {\frac {\pi }{4}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/f1da0b9d36e6e8fd4f5341b3480b75b72737e8db" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:15.723ex; height:4.676ex;" alt="{\displaystyle 0\leq \left|st(0)\right|\leq {\frac {\pi }{4}}}"> 80387: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 0\leq \left|st(0)\right|<2^{63}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mn>0</mn> <mo>≤</mo> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo><</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>63</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 0\leq \left|st(0)\right|<2^{63}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/04365abaeff237bcbdb108d439f63cffe8fb1eca" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:16.594ex; height:3.176ex;" alt="{\displaystyle 0\leq \left|st(0)\right|<2^{63}}"> </td></tr> <tr> <td><a href="/wiki/Atan2" title="Atan2">Two-argument arctangent</a> with quadrant adjustment:<a href="#cite_note-318">[u]</a><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(1)\leftarrow \arctan \left({\frac {st(1)}{st(0)}}\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>arctan</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> </mrow> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> </mfrac> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(1)\leftarrow \arctan \left({\frac {st(1)}{st(0)}}\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/8ab64bc830bc9cd057d33a4f26a9e7f75b96c5e0" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.671ex; width:24.141ex; height:6.509ex;" alt="{\displaystyle st(1)\leftarrow \arctan \left({\frac {st(1)}{st(0)}}\right)}"> followed by stack pop </td> <td><code>FPATAN</code></td> <td><code>D9 F3</code> </td> <td colspan="2">8087: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \left|st(1)\right|\leq \left|st(0)\right|<\infty }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo>≤</mo> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo><</mo> <mi mathvariant="normal">∞</mi> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \left|st(1)\right|\leq \left|st(0)\right|<\infty }</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/b0860583d901040ee9341ba6d33d7511ff630692" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:20.912ex; height:2.843ex;" alt="{\displaystyle \left|st(1)\right|\leq \left|st(0)\right|<\infty }"> 80387: no restrictions </td></tr> <tr> <td>Base-2 Logarithm plus 1, with extra precision for st(0) close to 0:<math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)+1\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo>∗</mo> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo>+</mo> <mn>1</mn> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)+1\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/30274421798a5d9044ec9813f4c814a3c0cca97a" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:30.352ex; height:2.843ex;" alt="{\displaystyle st(1)\leftarrow st(1)*\log _{2}\left(st(0)+1\right)}">followed by stack pop </td> <td><code>FYL2XP1</code><a href="#cite_note-x87_fyl2x_error-317">[t]</a></td> <td><code>D9 F9</code> </td> <td colspan="2">Intel: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \left|st(0)\right|<\left(1-{\sqrt {\frac {1}{2}}}\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo><</mo> <mrow> <mo>(</mo> <mrow> <mn>1</mn> <mo>−</mo> <mrow class="MJX-TeXAtom-ORD"> <msqrt> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> </msqrt> </mrow> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \left|st(0)\right|<\left(1-{\sqrt {\frac {1}{2}}}\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/2bc520bbcd7d8b47895c89f4c4dbcea5ab99244a" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.505ex; width:21.04ex; height:6.343ex;" alt="{\displaystyle \left|st(0)\right|<\left(1-{\sqrt {\frac {1}{2}}}\right)}"> AMD: <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \left({\sqrt {\frac {1}{2}}}-1\right)<st(0)<\left({\sqrt {2}}-1\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow> <mo>(</mo> <mrow> <mrow class="MJX-TeXAtom-ORD"> <msqrt> <mfrac> <mn>1</mn> <mn>2</mn> </mfrac> </msqrt> </mrow> <mo>−</mo> <mn>1</mn> </mrow> <mo>)</mo> </mrow> <mo><</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo><</mo> <mrow> <mo>(</mo> <mrow> <mrow class="MJX-TeXAtom-ORD"> <msqrt> <mn>2</mn> </msqrt> </mrow> <mo>−</mo> <mn>1</mn> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \left({\sqrt {\frac {1}{2}}}-1\right)<st(0)<\left({\sqrt {2}}-1\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a3c3b96f6ad54217d2eeeecf7f6d712d875fb57f" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.505ex; width:32.076ex; height:6.343ex;" alt="{\displaystyle \left({\sqrt {\frac {1}{2}}}-1\right)<st(0)<\left({\sqrt {2}}-1\right)}"> </td></tr> <tr> <th colspan="3"></th> <th colspan="2"> </th></tr> <tr> <th colspan="3">Other x87 Instructions</th> <th colspan="2"> </th></tr> <tr> <td>No operation<a href="#cite_note-319">[v]</a> </td> <td><code>FNOP</code></td> <td><code>D9 D0</code> </td></tr> <tr> <td>Decrement x87 FPU Register Stack Pointer </td> <td><code>FDECSTP</code></td> <td><code>D9 F6</code> </td></tr> <tr> <td>Increment x87 FPU Register Stack Pointer </td> <td><code>FINCSTP</code></td> <td><code>D9 F7</code> </td></tr> <tr> <td>Free x87 FPU Register </td> <td><code>FFREE st(i)</code> </td> <td><code>DD C0+i</code> </td></tr> <tr> <td>Check and handle pending unmasked x87 FPU exceptions </td> <td><code>WAIT</code>, <code>FWAIT</code></td> <td><code>9B</code> </td></tr> <tr> <td>Floating-point store and pop, without stack underflow exception </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">FSTPNCE st(i) </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">D9 D8+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr> <tr> <td>Free x87 register, then stack pop </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">FFREEP st(i) </td> <td style="background: #BFE; color:black; vertical-align: middle; text-align: left;" class="partial table-partial"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">DF C0+i<a href="#cite_note-x87_alias-303">[g]</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-289"><a href="#cite_ref-289">^</a> x87 coprocessors (other than the 8087) handle exceptions in a fairly unusual way. When an x87 instruction generates an unmasked arithmetic exception, it will still complete without causing a CPU fault – instead of causing a fault, it will record within the coprocessor information needed to handle the exception (instruction pointer, opcode, data pointer if the instruction had a memory operand) and set FPU status-word flag to indicate that a pending exception is present. This pending exception will then cause a CPU fault when the next x87, MMX or <code>WAIT</code> instruction is executed. The exception to this is x87's "Non-Waiting" instructions, which will execute without causing such a fault even if a pending exception is present (with some caveats, see application note AP-578<a href="#cite_note-288">[120]</a>). These instructions are mostly control instructions that can inspect and/or modify the pending-exception state of the x87 FPU. </li> <li id="cite_note-290"><a href="#cite_ref-290">^</a> For each non-waiting x87 instruction whose mnemonic begins with <code>FN</code>, there exists a pseudo-instruction that has the same mnemonic except without the N. These pseudo-instructions consist of a <code>WAIT</code> instruction (opcode <code>9B</code>) followed by the corresponding non-waiting x87 instruction. For example:<ul><li><code>FNCLEX</code> is an instruction with the opcode <code>DB E2</code>. The corresponding pseudo-instruction <code>FCLEX</code> is then encoded as <code>9B DB E2</code>.</li><li><code>FNSAVE ES:[BX+6]</code> is an instruction with the opcode <code>26 DD 77 06</code>. The corresponding pseudo-instruction <code>FSAVE ES:[BX+6]</code> is then encoded as <code>9B 26 DD 77 06</code></li></ul>These pseudo-instructions are commonly recognized by x86 assemblers and disassemblers and treated as single instructions, even though all x86 CPUs with x87 coprocessors execute them as a sequence of two instructions. </li> <li id="cite_note-x87_environment_size-291">^ <a href="#cite_ref-x87_environment_size_291-0">a</a> <a href="#cite_ref-x87_environment_size_291-1">b</a> <a href="#cite_ref-x87_environment_size_291-2">c</a> <a href="#cite_ref-x87_environment_size_291-3">d</a> On 80387 and later x87 FPUs, <code>FLDENV</code>, <code>F(N)STENV</code>, <code>FRSTOR</code> and <code>F(N)SAVE</code> exist in 16-bit and 32-bit variants. The 16-bit variants will load/store a 14-byte floating-point environment data structure to/from memory – the 32-bit variants will load/store a 28-byte data structure instead. (<code>F(N)SAVE</code>/<code>FRSTOR</code> will additionally load/store an additional 80 bytes of FPU data register content after the FPU environment, for a total of 94 or 108 bytes). The choice between the 16-bit and 32-bit variants is based on the <code>CS.D</code> bit and the presence of the <code>66h</code> instruction prefix. On 8087 and 80287, only the 16-bit variants are available. 64-bit variants of these instructions do not exist – using <code>REX.W</code> under x86-64 will cause the 32-bit variants to be used. Since these can only load/store the bottom 32 bits of FIP and FDP, it is recommended to use <code>FXSAVE64</code>/<code>FXRSTOR64</code> instead if 64-bit operation is desired. </li> <li id="cite_note-feni_8087_only-295">^ <a href="#cite_ref-feni_8087_only_295-0">a</a> <a href="#cite_ref-feni_8087_only_295-1">b</a> In the case of an x87 instruction producing an unmasked FPU exception, the 8087 FPU will signal an <a href="/wiki/Interrupt_Request" class="mw-redirect" title="Interrupt Request">IRQ</a> some indeterminate time after the instruction was issued. This may not always be possible to handle,<a href="#cite_note-292">[121]</a> and so the FPU offers the <code>F(N)DISI</code> and <code>F(N)ENI</code> instructions to set/clear the Interrupt Mask bit (bit 7) of the x87 Control Word,<a href="#cite_note-293">[122]</a> to control the interrupt. Later x87 FPUs, from 80287 onwards, changed the FPU exception mechanism to instead produce a CPU exception on the next x87 instruction. This made the Interrupt Mask bit unnecessary, so it was removed.<a href="#cite_note-294">[123]</a> In later Intel x87 FPUs, the <code>F(N)ENI</code> and <code>F(N)DISI</code> instructions were kept for backwards compatibility, executing as NOPs that do not modify any x87 state. </li> <li id="cite_note-x87_amd_fstp-296">^ <a href="#cite_ref-x87_amd_fstp_296-0">a</a> <a href="#cite_ref-x87_amd_fstp_296-1">b</a> <a href="#cite_ref-x87_amd_fstp_296-2">c</a> <code>FST</code>/<code>FSTP</code> with an 80-bit destination (m80 or st(i)) and an sNaN source value will produce exceptions on AMD but not Intel FPUs. </li> <li id="cite_note-297"><a href="#cite_ref-297">^</a> <code>FSTP ST(0)</code> is a commonly used idiom for popping a single register off the x87 register stack. </li> <li id="cite_note-x87_alias-303">^ <a href="#cite_ref-x87_alias_303-0">a</a> <a href="#cite_ref-x87_alias_303-1">b</a> <a href="#cite_ref-x87_alias_303-2">c</a> <a href="#cite_ref-x87_alias_303-3">d</a> <a href="#cite_ref-x87_alias_303-4">e</a> <a href="#cite_ref-x87_alias_303-5">f</a> <a href="#cite_ref-x87_alias_303-6">g</a> <a href="#cite_ref-x87_alias_303-7">h</a> <a href="#cite_ref-x87_alias_303-8">i</a> Intel x87 alias opcode. Use of this opcode is not recommended. On the Intel 8087 coprocessor, several reserved opcodes would perform operations behaving similarly to existing defined x87 instructions. These opcodes were documented for the 8087<a href="#cite_note-298">[124]</a> and 80287,<a href="#cite_note-i80287-299">[125]</a> but then omitted from later manuals until the October 2017 update of the Intel SDM.<a href="#cite_note-300">[126]</a> They are present on all known Intel x87 FPUs but unavailable on some older non-Intel FPUs, such as AMD Geode GX/LX, DM&P Vortex86<a href="#cite_note-301">[127]</a> and NexGen 586PF.<a href="#cite_note-302">[128]</a> </li> <li id="cite_note-x87_rounding_387-304">^ <a href="#cite_ref-x87_rounding_387_304-0">a</a> <a href="#cite_ref-x87_rounding_387_304-1">b</a> On the 8087 and 80287, <code>FBSTP</code> and the load-constant instructions always use the round-to-nearest rounding mode. On the 80387 and later x87 FPUs, these instructions will use the rounding mode specified in the x87 RC register. </li> <li id="cite_note-x87_optarg-305">^ <a href="#cite_ref-x87_optarg_305-0">a</a> <a href="#cite_ref-x87_optarg_305-1">b</a> <a href="#cite_ref-x87_optarg_305-2">c</a> <a href="#cite_ref-x87_optarg_305-3">d</a> <a href="#cite_ref-x87_optarg_305-4">e</a> <a href="#cite_ref-x87_optarg_305-5">f</a> <a href="#cite_ref-x87_optarg_305-6">g</a> <a href="#cite_ref-x87_optarg_305-7">h</a> <a href="#cite_ref-x87_optarg_305-8">i</a> For the <code>FADDP</code>, <code>FSUBP</code>, <code>FSUBRP</code>, <code>FMULP</code>, <code>FDIVP</code>, <code>FDIVRP</code>, <code>FCOM</code>, <code>FCOMP</code> and <code>FXCH</code> instructions, x86 assemblers/disassemblers may recognize variants of the instructions with no arguments. Such variants are equivalent to variants using st(1) as their first argument. </li> <li id="cite_note-306"><a href="#cite_ref-306">^</a> On Intel Pentium and later processors, <code>FXCH</code> is implemented as a register renaming rather than a true data move. This has no semantic effect, but enables zero-cycle-latency operation. It also allows the instruction to break data dependencies for the x87 top-of-stack value, improving attainable performance for code optimized for these processors. </li> <li id="cite_note-307"><a href="#cite_ref-307">^</a> The result of executing the <code>FBLD</code> instruction on non-BCD data is undefined. </li> <li id="cite_note-pentium_fdiv-309"><a href="#cite_ref-pentium_fdiv_309-0">^</a> On early Intel <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> processors, floating-point divide was subject to the <a href="/wiki/Pentium_FDIV_bug" title="Pentium FDIV bug">Pentium FDIV bug</a>. This also affected instructions that perform divide as part of their operations, such as <code>FPREM</code> and <code>FPATAN</code>.<a href="#cite_note-308">[129]</a> </li> <li id="cite_note-310"><a href="#cite_ref-310">^</a> The <code>FXAM</code> instruction will set C0, C2 and C3 based on value type in st(0) as follows: <table class="wikitable sortable"> <tbody><tr> <th>C3</th> <th>C2</th> <th>C0</th> <th>Classification </th></tr> <tr> <td>0</td> <td>0</td> <td>0</td> <td>Unsupported (unnormal or pseudo-NaN) </td></tr> <tr> <td>0</td> <td>0</td> <td>1</td> <td><a href="/wiki/NaN" title="NaN">NaN</a> </td></tr> <tr> <td>0</td> <td>1</td> <td>0</td> <td>Normal finite number </td></tr> <tr> <td>0</td> <td>1</td> <td>1</td> <td>Infinity </td></tr> <tr> <td>1</td> <td>0</td> <td>0</td> <td>Zero </td></tr> <tr> <td>1</td> <td>0</td> <td>1</td> <td>Empty </td></tr> <tr> <td>1</td> <td>1</td> <td>0</td> <td><a href="/wiki/Subnormal_number" title="Subnormal number">Denormal</a> number </td></tr> <tr> <td>1</td> <td>1</td> <td>1</td> <td>Empty (may occur on 8087/80287 only) </td></tr></tbody></table> C1 is set to the sign-bit of st(0), regardless of whether st(0) is Empty or not. </li> <li id="cite_note-311"><a href="#cite_ref-311">^</a> For <code>FXTRACT</code>, if st(0) is zero or ±∞, then M is set equal to st(0). If st(0) is zero, E is set to 0 on 8087/80287 but -∞ on 80387 and later. If st(0) is ±∞, then E is set to +∞. </li> <li id="cite_note-312"><a href="#cite_ref-312">^</a> For <code>FPREM</code>, if the quotient Q is larger than <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 2^{63}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>63</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 2^{63}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/b39e86ff89473195ea369e15878afc044b87bb06" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:3.039ex; height:2.676ex;" alt="{\displaystyle 2^{63}}">, then the remainder calculation may have been done only partially – in this case, the <code>FPREM</code> instruction will need to be run again in order to complete the remainder calculation. This is indicated by the instruction setting <code>C2</code> to 1. If the instruction did complete the remainder calculation, it will set <code>C2</code> to 0 and set the three bits <code>{C0,C3,C1}</code> to the bottom three bits of the quotient Q. On 80387 and later, if the instruction didn't complete the remainder calculation, then the computed remainder Q used for argument reduction will have been rounded to a multiple of 8 (or larger power-of-2), so that the bottom 3 bits of the quotient can still be correctly retrieved in a later pass that does complete the remainder calculation. </li> <li id="cite_note-313"><a href="#cite_ref-313">^</a> The remainder computation done by the <code>FPREM</code> instruction is always exact with no roundoff errors. </li> <li id="cite_note-314"><a href="#cite_ref-314">^</a> For the <code>FSCALE</code> instruction on 8087 and 80287, st(1) is required to be in the range <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle -2^{15}\leq st(1)<2^{15}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo>−</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>15</mn> </mrow> </msup> <mo>≤</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> <mo><</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>15</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle -2^{15}\leq st(1)<2^{15}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/3f4908bdccae794356788497bc908a2cd417074f" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:18.984ex; height:3.176ex;" alt="{\displaystyle -2^{15}\leq st(1)<2^{15}}">. Also, its absolute value must be either 0 or at least 1. If these requirements are not satisfied, the result is undefined. These restrictions were removed in the 80387. </li> <li id="cite_note-315"><a href="#cite_ref-315">^</a> For <code>FSCALE</code>, rounding is only applied in the case of overflow, underflow or subnormal result. </li> <li id="cite_note-316"><a href="#cite_ref-316">^</a> The x87 transcendental instructions do not obey PC or RC, but instead compute full 80-bit results. These results are not necessarily correctly rounded (see <a href="/wiki/Table-maker%27s_dilemma" class="mw-redirect" title="Table-maker's dilemma">Table-maker's dilemma</a>) – they may have an error of up to ±1 <a href="/wiki/Unit_in_the_last_place" title="Unit in the last place">ulp</a> on <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> or later, or up to ±1.5 ulps on earlier x87 coprocessors. </li> <li id="cite_note-x87_fyl2x_error-317">^ <a href="#cite_ref-x87_fyl2x_error_317-0">a</a> <a href="#cite_ref-x87_fyl2x_error_317-1">b</a> For the <code>FYL2X</code> and <code>FYL2XP1</code> instructions, the maximum error bound of ±1 ulp only holds for st(1)=1.0 – for other values of st(1), the error bound is increased to ±1.35 ulps. </li> <li id="cite_note-318"><a href="#cite_ref-318">^</a> For <code>FPATAN</code>, the following adjustments are done as compared to just computing a one-argument arctangent of the ratio <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\frac {st(1)}{st(0)}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>1</mn> <mo stretchy="false">)</mo> </mrow> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\frac {st(1)}{st(0)}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/685ac81d3c516d0116b524e0c5ed4723e58b6df8" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.671ex; width:5.738ex; height:6.509ex;" alt="{\displaystyle {\frac {st(1)}{st(0)}}}">:<ul><li>If both st(0) and st(1) are ±∞, then the arctangent is computed as if each of st(0) and st(1) had been replaced with ±1 of the same sign. This produces a result that is an odd multiple of <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle {\frac {\pi }{4}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mi>π</mi> <mn>4</mn> </mfrac> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle {\frac {\pi }{4}}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/1f89d7c88c1c93dce69a46052a8e276e231063de" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:2.168ex; height:4.676ex;" alt="{\displaystyle {\frac {\pi }{4}}}">.</li><li>If both st(0) and st(1) are ±0, then the arctangent is computed as if st(0) but not st(1) had been replaced with ±1 of the same sign, producing a result of ±0 or <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \pm \pi }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo>±</mo> <mi>π</mi> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \pm \pi }</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/526d4dfa032be40e7af5c8e7e27132397765fb36" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:3.14ex; height:2.176ex;" alt="{\displaystyle \pm \pi }">.</li><li>If st(0) is negative (has sign bit set), then an addend of <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \pm \pi }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo>±</mo> <mi>π</mi> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \pm \pi }</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/526d4dfa032be40e7af5c8e7e27132397765fb36" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:3.14ex; height:2.176ex;" alt="{\displaystyle \pm \pi }"> with the same sign as st(1) is added to the result.</li></ul> </li> <li id="cite_note-319"><a href="#cite_ref-319">^</a> While <code>FNOP</code> is a no-op in the sense that will leave the x87 FPU register stack unmodified, it may still modify FIP and CC, and it may fault if a pending x87 FPU exception is present. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="x87_instructions_added_in_later_processors">x87 instructions added in later processors</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=20" title="Edit section: x87 instructions added in later processors">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Instruction description </th> <th>Mnemonic </th> <th>Opcode </th> <th>Additional items </th></tr> <tr> <th colspan="3"></th> <th> </th></tr> <tr> <th colspan="3">x87 Non-Waiting Control Instructions added in <a href="/wiki/80287" class="mw-redirect" title="80287">80287</a></th> <th>Waiting mnemonic </th></tr> <tr> <td>Notify FPU of entry into <a href="/wiki/Protected_Mode" class="mw-redirect" title="Protected Mode">Protected Mode</a><a href="#cite_note-320">[a]</a></td> <td><code>FNSETPM</code></td> <td><code>DB E4</code></td> <td><code>FSETPM</code> </td></tr> <tr> <td>Store x87 Status Word to AX</td> <td><code>FNSTSW AX</code></td> <td><code>DF E0</code></td> <td><code>FSTSW AX</code> </td></tr> <tr> <th colspan="3"></th> <th> </th></tr> <tr> <th colspan="3">x87 Instructions added in <a href="/wiki/80387" class="mw-redirect" title="80387">80387</a><a href="#cite_note-321">[b]</a></th> <th>Source operand range restriction </th></tr> <tr> <td>Floating-point unordered compare. Similar to the regular floating-point compare instruction <code>FCOM</code>, except will not produce an exception in response to any <a href="/wiki/NaN#Quiet_NaN" title="NaN">qNaN</a> operands.</td> <td><code>FUCOM st(i)</code><a href="#cite_note-387_optarg-322">[c]</a></td> <td><code>DD E0+i</code></td> <td rowspan="4">no restrictions </td></tr> <tr> <td>Floating-point unordered compare and pop</td> <td><code>FUCOMP st(i)</code><a href="#cite_note-387_optarg-322">[c]</a></td> <td><code>DD E8+i</code> </td></tr> <tr> <td>Floating-point unordered compare to st(1), then pop twice</td> <td><code>FUCOMPP</code></td> <td><code>DA E9</code> </td></tr> <tr> <td><a href="/wiki/IEEE_754" title="IEEE 754">IEEE 754</a> compliant floating-point partial remainder.<a href="#cite_note-323">[d]</a></td> <td><code>FPREM1</code></td> <td><code>D9 F5</code> </td></tr> <tr> <td>Floating-point sine and cosine. Computes two values <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle S=\sin \left(k*st(0)\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>S</mi> <mo>=</mo> <mi>sin</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>k</mi> <mo>∗</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle S=\sin \left(k*st(0)\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/5197cb9ad0d7d5578751a770905fe433a3ed6ae7" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:17.57ex; height:2.843ex;" alt="{\displaystyle S=\sin \left(k*st(0)\right)}"> and <math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle C=\cos \left(k*st(0)\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>C</mi> <mo>=</mo> <mi>cos</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>k</mi> <mo>∗</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle C=\cos \left(k*st(0)\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/1982e0a9d5fd4c676f95a7e6c57f5b2d5de7f75b" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:18.093ex; height:2.843ex;" alt="{\displaystyle C=\cos \left(k*st(0)\right)}"> <a href="#cite_note-x87_inaccurate_sincos-324">[e]</a> Top-of-stack st(0) is replaced with S, after which C is pushed onto the stack.</td> <td><code>FSINCOS</code></td> <td><code>D9 FB</code></td> <td rowspan="3"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \left|st(0)\right|<2^{63}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mrow> <mo>|</mo> <mrow> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>|</mo> </mrow> <mo><</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>63</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \left|st(0)\right|<2^{63}}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/e75dec6323882be93ad2984d60c0661de1d84961" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:12.333ex; height:3.176ex;" alt="{\displaystyle \left|st(0)\right|<2^{63}}"> </td></tr> <tr> <td>Floating-point sine.<a href="#cite_note-x87_inaccurate_sincos-324">[e]</a><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(0)\leftarrow \sin \left(k*st(0)\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>sin</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>k</mi> <mo>∗</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(0)\leftarrow \sin \left(k*st(0)\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/7372201f231a01c595be645ed8091aa78a7c7608" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:21.489ex; height:2.843ex;" alt="{\displaystyle st(0)\leftarrow \sin \left(k*st(0)\right)}"></td> <td><code>FSIN</code></td> <td><code>D9 FE</code> </td></tr> <tr> <td>Floating-point cosine.<a href="#cite_note-x87_inaccurate_sincos-324">[e]</a><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle st(0)\leftarrow \cos \left(k*st(0)\right)}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> <mo stretchy="false">←</mo> <mi>cos</mi> <mo>⁡</mo> <mrow> <mo>(</mo> <mrow> <mi>k</mi> <mo>∗</mo> <mi>s</mi> <mi>t</mi> <mo stretchy="false">(</mo> <mn>0</mn> <mo stretchy="false">)</mo> </mrow> <mo>)</mo> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle st(0)\leftarrow \cos \left(k*st(0)\right)}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/4f362995ef02cba8ea1d468eb3925a98bb13a139" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:21.744ex; height:2.843ex;" alt="{\displaystyle st(0)\leftarrow \cos \left(k*st(0)\right)}"></td> <td><code>FCOS</code></td> <td><code>D9 FF</code> </td></tr> <tr> <th colspan="3"></th> <th> </th></tr> <tr> <th colspan="3">x87 Instructions added in <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a></th> <th>Condition for conditional moves </th></tr> <tr> <td rowspan="8">Floating-point conditional move to st(0) based on <a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a></td> <td><code><a href="/wiki/FCMOV" title="FCMOV">FCMOV</a>B st(0),st(i)</code></td> <td><code>DA C0+i</code></td> <td>below (CF=1) </td></tr> <tr> <td><code>FCMOVE st(0),st(i)</code></td> <td><code>DA C8+i</code></td> <td>equal (ZF=1) </td></tr> <tr> <td><code>FCMOVBE st(0),st(i)</code></td> <td><code>DA D0+i</code></td> <td>below or equal (CF=1 or ZF=1) </td></tr> <tr> <td><code>FCMOVU st(0),st(i)</code></td> <td><code>DA D8+i</code></td> <td>unordered (PF=1) </td></tr> <tr> <td><code>FCMOVNB st(0),st(i)</code></td> <td><code>DB C0+i</code></td> <td>not below (CF=0) </td></tr> <tr> <td><code>FCMOVNE st(0),st(i)</code></td> <td><code>DB C8+i</code></td> <td>not equal (ZF=0) </td></tr> <tr> <td><code>FCMOVNBE st(0),st(i)</code></td> <td><code>DB D0+i</code></td> <td>not below or equal (CF=0 and ZF=0) </td></tr> <tr> <td><code>FCMOVNU st(0),st(i)</code></td> <td><code>DB D8+i</code></td> <td>not unordered (PF=0) </td></tr> <tr> <td>Floating-point compare and set <code>EFLAGS</code>. Differs from the older <code>FCOM</code> floating-point compare instruction in that it puts its result in the integer <code><a href="/wiki/FLAGS_register" title="FLAGS register">EFLAGS</a></code> register rather than the x87 CC register.<a href="#cite_note-327">[f]</a></td> <td><code>FCOMI st(0),st(i)</code></td> <td><code>DB F0+i</code> </td></tr> <tr> <td>Floating-point compare and set <code>EFLAGS</code>, then pop</td> <td><code>FCOMIP st(0),st(i)</code></td> <td><code>DF F0+i</code> </td></tr> <tr> <td>Floating-point unordered compare and set <code>EFLAGS</code></td> <td><code>FUCOMI st(0),st(i)</code></td> <td><code>DB E8+i</code> </td></tr> <tr> <td>Floating-point unordered compare and set <code>EFLAGS</code>, then pop</td> <td><code>FUCOMIP st(0),st(i)</code></td> <td><code>DF E8+i</code> </td></tr> <tr> <th colspan="3"></th> <th> </th></tr> <tr> <th colspan="3">x87 Non-Waiting Instructions added in <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>, <a href="/wiki/AMD_K7" class="mw-redirect" title="AMD K7">AMD K7</a> and <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a><a href="#cite_note-328">[g]</a> </th> <th>64-bit mnemonic (<code>REX.W</code> prefix) </th></tr> <tr> <td>Save x87, MMX and SSE state to 512-byte data structure<a href="#cite_note-fxsave_sse-329">[h]</a><a href="#cite_note-fxsave_cr0em-330">[i]</a><a href="#cite_note-331">[j]</a></td> <td><code>FXSAVE m512byte</code></td> <td><code>NP 0F AE /0</code></td> <td><code>FXSAVE64 m512byte</code> </td></tr> <tr> <td>Restore x87, MMX and SSE state from 512-byte data structure<a href="#cite_note-fxsave_sse-329">[h]</a><a href="#cite_note-fxsave_cr0em-330">[i]</a></td> <td><code>FXRSTOR m512byte</code></td> <td><code>NP 0F AE /1</code></td> <td><code>FXRSTOR64 m512byte</code> </td></tr> <tr> <th colspan="3"></th> <th> </th></tr> <tr> <th colspan="3">x87 Instructions added as part of <a href="/wiki/SSE3" title="SSE3">SSE3</a></th> <th> </th></tr> <tr> <td rowspan="3">Floating-point store integer and pop, with round-to-zero</td> <td><code>FISTTP m16</code></td> <td><code>DF /1</code> </td></tr> <tr> <td><code>FISTTP m32</code></td> <td><code>DB /1</code> </td></tr> <tr> <td><code>FISTTP m64</code></td> <td><code>DD /1</code> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-320"><a href="#cite_ref-320">^</a> The x87 FPU needs to know whether it is operating in <a href="/wiki/Real_Mode" class="mw-redirect" title="Real Mode">Real Mode</a> or <a href="/wiki/Protected_Mode" class="mw-redirect" title="Protected Mode">Protected Mode</a> because the floating-point environment accessed by the <code>F(N)SAVE</code>, <code>FRSTOR</code>, <code>FLDENV</code> and <code>F(N)STENV</code> instructions has different formats in Real Mode and Protected Mode. On 80287, the <code>F(N)SETPM</code> instruction is required to communicate the real-to-protected mode transition to the FPU. On 80387 and later x87 FPUs, real↔protected mode transitions are communicated automatically to the FPU without the need for any dedicated instructions – therefore, on these FPUs, <code>FNSETPM</code> executes as a NOP that does not modify any FPU state. </li> <li id="cite_note-321"><a href="#cite_ref-321">^</a> Not including <a href="/wiki/List_of_discontinued_x86_instructions#Instructions_present_in_specific_80387_clones" title="List of discontinued x86 instructions">discontinued instructions specific to particular 80387-compatible FPU models.</a> </li> <li id="cite_note-387_optarg-322">^ <a href="#cite_ref-387_optarg_322-0">a</a> <a href="#cite_ref-387_optarg_322-1">b</a> For the <code>FUCOM</code> and <code>FUCOMP</code> instructions, x86 assemblers/disassemblers may recognize variants of the instructions with no arguments. Such variants are equivalent to variants using st(1) as their first argument. </li> <li id="cite_note-323"><a href="#cite_ref-323">^</a> The 80387 <code>FPREM1</code> instruction differs from the older <code>FPREM</code> (<code>D9 F8</code>) instruction in that the quotient Q is rounded to integer with round-to-nearest-even rounding rather than the round-to-zero rounding used by <code>FPREM</code>. Like <code>FPREM</code>, <code>FPREM1</code> always computes an exact result with no roundoff errors. Like <code>FPREM</code>, it may also perform a partial computation if the quotient is too large, in which case it must be run again. </li> <li id="cite_note-x87_inaccurate_sincos-324">^ <a href="#cite_ref-x87_inaccurate_sincos_324-0">a</a> <a href="#cite_ref-x87_inaccurate_sincos_324-1">b</a> <a href="#cite_ref-x87_inaccurate_sincos_324-2">c</a> Due to the x87 FPU performing argument reduction for sin/cos with only about 68 bits of precision, the value of k used in the calculation of <code>FSIN</code>, <code>FCOS</code> and <code>FSINCOS</code> is not precisely 1.0, but instead given by<a href="#cite_note-325">[130]</a><a href="#cite_note-326">[131]</a><math display="block" xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle k{=}{\frac {2^{66}*\pi }{\lfloor 2^{66}*\pi \rfloor }}\approx 1.0000000000000000000012874}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>k</mi> <mrow class="MJX-TeXAtom-ORD"> <mo>=</mo> </mrow> <mrow class="MJX-TeXAtom-ORD"> <mfrac> <mrow> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>66</mn> </mrow> </msup> <mo>∗</mo> <mi>π</mi> </mrow> <mrow> <mo fence="false" stretchy="false">⌊</mo> <msup> <mn>2</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>66</mn> </mrow> </msup> <mo>∗</mo> <mi>π</mi> <mo fence="false" stretchy="false">⌋</mo> </mrow> </mfrac> </mrow> <mo>≈</mo> <mn>1.0000000000000000000012874</mn> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle k{=}{\frac {2^{66}*\pi }{\lfloor 2^{66}*\pi \rfloor }}\approx 1.0000000000000000000012874}</annotation> </semantics> </math><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/7e1161484e9a9dbdcda7c5ae64689225f8318434" class="mwe-math-fallback-image-display mw-invert skin-invert" aria-hidden="true" style="vertical-align: -2.838ex; width:46.455ex; height:6.676ex;" alt="{\displaystyle k{=}{\frac {2^{66}*\pi }{\lfloor 2^{66}*\pi \rfloor }}\approx 1.0000000000000000000012874}">This argument reduction inaccuracy also affects the <code>FPTAN</code> instruction. </li> <li id="cite_note-327"><a href="#cite_ref-327">^</a> The <code>FCOMI</code>, <code>FCOMIP</code>, <code>FUCOMI</code> and <code>FUCOMIP</code> instructions write their results to the <code>ZF</code>, <code>CF</code> and <code>PF</code> bits of the <code>EFLAGS</code> register. On Intel but not AMD processors, the <code>SF</code>, <code>AF</code> and <code>OF</code> bits of <code>EFLAGS</code> are also zeroed out by these instructions. </li> <li id="cite_note-328"><a href="#cite_ref-328">^</a> The <code>FXSAVE</code> and <code>FXRSTOR</code> instructions were added in the "Deschutes" revision of Pentium II, and are not present in earlier "Klamath" revision. They are also present in AMD K7. They are also considered an integral part of SSE and are therefore present in all processors with SSE. </li> <li id="cite_note-fxsave_sse-329">^ <a href="#cite_ref-fxsave_sse_329-0">a</a> <a href="#cite_ref-fxsave_sse_329-1">b</a> The <code>FXSAVE</code> and <code>FXRSTOR</code> instructions will save/restore SSE state only on processors that support SSE. Otherwise, they will only save/restore x87 and MMX state. The x87 section of the state saved/restored by <code>FXSAVE</code>/<code>FXRSTOR</code> has a completely different layout than the data structure of the older <code>F(N)SAVE</code>/<code>FRSTOR</code> instructions, enabling faster save/restore by avoiding misaligned loads and stores. </li> <li id="cite_note-fxsave_cr0em-330">^ <a href="#cite_ref-fxsave_cr0em_330-0">a</a> <a href="#cite_ref-fxsave_cr0em_330-1">b</a> When floating-point emulation is enabled with <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">CR0.EM=1</code>, <code>FXSAVE(64)</code> and <code>FXRSTOR(64)</code> are considered to be x87 instructions and will accordingly produce an <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">#NM (device-not-available) exception. Other than <code>WAIT</code>, these are the only opcodes outside the <code>D8..DF</code> ESC opcode space that exhibit this behavior. (All opcodes in <code>D8..DF</code> will produce <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">#NM if <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">CR0.EM=1</code>, even for undefined opcodes that would produce <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">#UD otherwise.) </li> <li id="cite_note-331"><a href="#cite_ref-331">^</a> Unlike the older <code>F(N)SAVE</code> instruction, <code>FXSAVE</code> will not initialize the FPU after saving its state to memory, but instead leave the x87 coprocessor state unmodified. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="SIMD_instructions"><a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=21" title="Edit section: SIMD instructions">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/X86_SIMD_instruction_listings" title="X86 SIMD instruction listings">x86 SIMD instruction listings</a></div> <div class="mw-heading mw-heading2"><h2 id="Cryptographic_instructions">Cryptographic instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=22" title="Edit section: Cryptographic instructions">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_x86_cryptographic_instructions" title="List of x86 cryptographic instructions">List of x86 cryptographic instructions</a></div> <div class="mw-heading mw-heading2"><h2 id="Virtualization_instructions">Virtualization instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=23" title="Edit section: Virtualization instructions">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_x86_virtualization_instructions" title="List of x86 virtualization instructions">List of x86 virtualization instructions</a></div> <div class="mw-heading mw-heading2"><h2 id="Other_instructions">Other instructions</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=24" title="Edit section: Other instructions">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/List_of_discontinued_x86_instructions" title="List of discontinued x86 instructions">List of discontinued x86 instructions</a></div> x86 also includes discontinued instruction sets which are no longer supported by Intel and AMD, and undocumented instructions which execute but are not officially documented. <div class="mw-heading mw-heading3"><h3 id="Undocumented_x86_instructions">Undocumented x86 instructions</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=25" title="Edit section: Undocumented x86 instructions">edit</a>]</div> The x86 CPUs contain <a href="/wiki/Undocumented_instruction" class="mw-redirect" title="Undocumented instruction">undocumented instructions</a> which are implemented on the chips but not listed in some official documents. They can be found in various sources across the Internet, such as <a href="/wiki/Ralf_Brown%27s_Interrupt_List" title="Ralf Brown's Interrupt List">Ralf Brown's Interrupt List</a> and at <a rel="nofollow" class="external text" href="https://www.sandpile.org/">sandpile.org</a> Some of these instructions are widely available across many/most x86 CPUs, while others are specific to a narrow range of CPUs. <div class="mw-heading mw-heading4"><h4 id="Undocumented_instructions_that_are_widely_available_across_many_x86_CPUs_include">Undocumented instructions that are widely available across many x86 CPUs include</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=26" title="Edit section: Undocumented instructions that are widely available across many x86 CPUs include">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Mnemonics </th> <th>Opcodes </th> <th>Description </th> <th>Status </th></tr> <tr> <td><code>AAM imm8</code> </td> <td><code>D4 ib</code> </td> <td>ASCII-Adjust-after-Multiply. On the 8086, documented for imm8=0Ah only, which is used to convert a binary multiplication result to BCD. The actual operation is <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">AH ← AL/imm8; AL ← AL mod imm8</code> for any imm8 value (except zero, which produces a divide-by-zero exception).<a href="#cite_note-332">[132]</a> </td> <td rowspan="2">Available beginning with 8086, documented for imm8 values other than <code>0Ah</code> since Pentium (earlier documentation lists no arguments). </td></tr> <tr> <td><code>AAD imm8</code> </td> <td><code>D5 ib</code> </td> <td>ASCII-Adjust-Before-Division. On the 8086, documented for imm8=0Ah only, which is used to convert a BCD value to binary for a following division instruction. The actual operation is <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">AL ← (AL+(AH*imm8)) & 0FFh; AH ← 0</code> for any imm8 value. </td></tr> <tr> <td><code>SALC</code>, <code>SETALC</code> </td> <td><code>D6</code> </td> <td>Set AL depending on the value of the Carry Flag (a 1-byte alternative of <code>SBB AL, AL</code>) </td> <td>Available beginning with 8086, but only documented since Pentium Pro. </td></tr> <tr> <td><code>ICEBP</code>, <code>INT1</code> </td> <td><code>F1</code> </td> <td>Single byte single-step exception / Invoke <a href="/wiki/In-circuit_emulator" class="mw-redirect" title="In-circuit emulator">ICE</a> </td> <td>Available beginning with 80386, documented (as <code>INT1</code>) since Pentium Pro. Executes as undocumented instruction prefix on 8086 and 80286.<a href="#cite_note-333">[133]</a> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>TEST r/m8,imm8</code> </td> <td><code>F6 /1 ib</code> </td> <td rowspan="2">Undocumented variants of the <code>TEST</code> instruction.<a href="#cite_note-test_and_sal-334">[134]</a> Performs the same operation as the documented <code>F6 /0</code> and <code>F7 /0</code> variants, respectively. </td> <td rowspan="2">Available since the 8086. Unavailable on some 80486 steppings.<a href="#cite_note-335">[135]</a><a href="#cite_note-hummel-336">[136]</a> </td></tr> <tr> <td><code>TEST r/m16,imm16</code>, <code>TEST r/m32,imm32</code> </td> <td><code>F7 /1 iw</code>, <code>F7 /1 id</code> </td></tr> <tr> <td><code>SHL</code>, <code>SAL</code> </td> <td><code>(D0..D3) /6</code>, <code>(C0..C1) /6 ib</code> </td> <td>Undocumented variants of the <code>SHL</code> instruction.<a href="#cite_note-test_and_sal-334">[134]</a> Performs the same operation as the documented <code>(D0..D3) /4</code> and <code>(C0..C1) /4 ib</code> variants, respectively. </td> <td>Available since the 80186 (performs different operation on the 8086)<a href="#cite_note-337">[137]</a> </td></tr> <tr> <td>(multiple) </td> <td><code>82 /(0..7) ib</code> </td> <td>Alias of opcode <code>80h</code>, which provides variants of 8-bit integer instructions (<code>ADD</code>, <code>OR</code>, <code>ADC</code>, <code>SBB</code>, <code>AND</code>, <code>SUB</code>, <code>XOR</code>, <code>CMP</code>) with an 8-bit immediate argument.<a href="#cite_note-asm-opcode-82h-338">[138]</a> </td> <td>Available since the 8086.<a href="#cite_note-asm-opcode-82h-338">[138]</a> Explicitly unavailable in 64-bit mode but kept and reserved for compatibility.<a href="#cite_note-FOOTNOTEIntel_Corporation20223698-339">[139]</a> </td></tr> <tr> <td><code>OR/AND/XOR r/m16,imm8</code> </td> <td><code>83 /(1,4,6) ib</code> </td> <td>16-bit <code>OR</code>/<code>AND</code>/<code>XOR</code> with a sign-extended 8-bit immediate. </td> <td>Available on 8086, but only documented from 80386 onwards.<a href="#cite_note-340">[140]</a><a href="#cite_note-341">[141]</a> </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>REPNZ MOVS</code> </td> <td><code>F2 (A4..A5)</code> </td> <td rowspan="2">The behavior of the <code>F2</code> prefix (<code>REPNZ</code>, <code>REPNE</code>) when used with string instructions other than <code>CMPS</code>/<code>SCAS</code> is officially undefined, but there exists commercial software (e.g. the version of FDISK distributed with MS-DOS versions 3.30 to 6.22<a href="#cite_note-342">[142]</a>) that rely on it to behave in the same way as the documented <code>F3</code> (<code>REP</code>) prefix. </td> <td rowspan="2">Available since the 8086. </td></tr> <tr> <td><code>REPNZ STOS</code> </td> <td><code>F2 (AA..AB)</code> </td></tr> <tr> <td><code>REP RET</code> </td> <td><code>F3 C3</code> </td> <td>The use of the <code>REP</code> prefix with the <code>RET</code> instruction is not listed as supported in either the Intel SDM or the AMD APM. However, AMD's optimization guide for the AMD-K8 describes the <code>F3 C3</code> encoding as a way to encode a two-byte <code>RET</code> instruction – this is the recommended workaround for an issue in the AMD-K8's branch predictor that can cause branch prediction to fail for some 1-byte <code>RET</code> instructions.<a href="#cite_note-343">[143]</a> At least some versions of gcc are known to use this encoding.<a href="#cite_note-344">[144]</a> </td> <td>Executes as <code>RET</code> on all known x86 CPUs. </td></tr> <tr> <td><code>NOP</code> </td> <td><code>67 90</code> </td> <td><code>NOP</code> with address-size override prefix. The use of the <code>67h</code> prefix for instructions without memory operands is listed by the Intel SDM (vol 2, section 2.1.1) as "reserved", but it is used in Microsoft Windows 95 as a workaround for a bug in the B1 stepping of Intel 80386.<a href="#cite_note-345">[145]</a><a href="#cite_note-346">[146]</a> </td> <td>Executes as <code>NOP</code> on 80386 and later. </td></tr> <tr> <th colspan="4"> </th></tr> <tr> <td><code>NOP r/m</code> </td> <td><code>0F 1F /0</code> </td> <td>Official long NOP. Introduced in the Pentium Pro in 1995, but remained undocumented until March 2006.<a href="#cite_note-longnop2006-127">[58]</a><a href="#cite_note-347">[147]</a><a href="#cite_note-348">[148]</a> </td> <td>Available on Pentium Pro and AMD K7<a href="#cite_note-349">[149]</a> and later. Unavailable on AMD K6, AMD Geode LX, VIA Nehemiah.<a href="#cite_note-350">[150]</a> </td></tr> <tr> <td><code>NOP r/m</code> </td> <td><code>0F 0D /r</code> </td> <td>Reserved-NOP. Introduced in 65 nm Pentium 4. Intel documentation lists this opcode as <code>NOP</code> in opcode tables but not instruction listings since June 2005.<a href="#cite_note-351">[151]</a><a href="#cite_note-352">[152]</a> From Broadwell onwards, <code>0F 0D /1</code> has been documented as <code>PREFETCHW</code>, while <code>0F 0D /0</code> and <code>/2../7</code> have been reported to exhibit undocumented prefetch functionality.<a href="#cite_note-cattius_0f0d-238">[106]</a> On AMD CPUs, <code>0F 0D /r</code> with a memory argument is documented as <code>PREFETCH</code>/<code>PREFETCHW</code> since K6-2 – originally as part of 3Dnow!, but has been kept in later AMD CPUs even after the rest of 3Dnow! was dropped. </td> <td> Available on Intel CPUs since 65 nm Pentium 4. </td></tr> <tr> <td><code>UD1</code> </td> <td><code>0F B9 /r</code> </td> <td rowspan="2">Intentionally undefined instructions, but unlike <code>UD2</code> (<code>0F 0B</code>) these instructions were left unpublished until December 2016.<a href="#cite_note-353">[153]</a><a href="#cite_note-intel_ud0_ud1-143">[68]</a> Microsoft Windows 95 Setup is known to depend on <code>0F FF</code> being invalid<a href="#cite_note-354">[154]</a><a href="#cite_note-355">[155]</a> – it is used as a self check to test that its #UD exception handler is working properly. Other invalid opcodes that are being relied on by commercial software to produce #UD exceptions include <code>FF FF</code> (DIF-2,<a href="#cite_note-356">[156]</a> LaserLok<a href="#cite_note-357">[157]</a>) and <code>C4 C4</code> (<code>"BOP"</code><a href="#cite_note-358">[158]</a><a href="#cite_note-359">[159]</a>), however as of January 2022 they are not published as intentionally invalid opcodes. </td> <td rowspan="2">All of these opcodes produce #UD exceptions on 80186 and later (except on NEC V20/V30, which assign at least <code>0F FF</code> to the NEC-specific <code>BRKEM</code> instruction.) </td></tr> <tr> <td><code>UD0</code> </td> <td><code>0F FF</code> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Undocumented_instructions_that_appear_only_in_a_limited_subset_of_x86_CPUs_include">Undocumented instructions that appear only in a limited subset of x86 CPUs include</h4>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=27" title="Edit section: Undocumented instructions that appear only in a limited subset of x86 CPUs include">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Mnemonics </th> <th>Opcodes </th> <th>Description </th> <th>Status </th></tr> <tr> <td><code>REP MUL</code> </td> <td><code>F3 F6 /4</code>, <code>F3 F7 /4</code> </td> <td rowspan="2">On 8086/8088, a <code>REP</code> or <code>REPNZ</code> prefix on a <code>MUL</code> or <code>IMUL</code> instruction causes the result to be negated. This is due to the microcode using the “REP prefix present” bit to store the sign of the result. </td> <td rowspan="2">8086/8088 only.<a href="#cite_note-rep_imul-360">[160]</a> </td></tr> <tr> <td><code>REP IMUL</code> </td> <td><code>F3 F6 /5</code>, <code>F3 F7 /5</code> </td></tr> <tr> <td><code>REP IDIV</code> </td> <td><code>F3 F6 /7</code>, <code>F3 F7 /7</code> </td> <td>On 8086/8088, a <code>REP</code> or <code>REPNZ</code> prefix on an <code>IDIV</code> (but not <code>DIV</code>) instruction causes the quotient to be negated. This is due to the microcode using the “REP prefix present” bit to store the sign of the quotient. </td> <td>8086/8088 only.<a href="#cite_note-rep_imul-360">[160]</a> </td></tr> <tr> <td><code>SAVEALL</code>, <code>STOREALL</code> </td> <td><code>(F1) 0F 04</code> </td> <td>Exact purpose unknown, causes CPU hang (<a href="/wiki/Halt_and_Catch_Fire_(computing)" title="Halt and Catch Fire (computing)">HCF</a>). The only way out is CPU reset.<a href="#cite_note-361">[161]</a> In some implementations, emulated through <a href="/wiki/BIOS" title="BIOS">BIOS</a> as a <a href="/wiki/HLT_(x86_instruction)" title="HLT (x86 instruction)">halting</a> sequence.<a href="#cite_note-362">[162]</a> In <a rel="nofollow" class="external text" href="https://forum.vcfed.org/index.php?threads/i-found-the-saveall-opcode.71519/">a forum post at the Vintage Computing Federation</a>, this instruction (with <code>F1</code> prefix) is explained as <code>SAVEALL</code>. It interacts with ICE mode. </td> <td>Only available on 80286. </td></tr> <tr> <td><code><a href="/wiki/LOADALL" title="LOADALL">LOADALL</a></code> </td> <td><code>0F 05</code> </td> <td>Loads All Registers from Memory Address 0x000800H </td> <td>Only available on 80286. Opcode reused for <code>SYSCALL</code> in AMD K6 and later CPUs. </td></tr> <tr> <td><code><a href="/wiki/LOADALLD" class="mw-redirect" title="LOADALLD">LOADALLD</a></code> </td> <td><code>0F 07</code> </td> <td>Loads All Registers from Memory Address ES:EDI </td> <td>Only available on 80386. Opcode reused for <code>SYSRET</code> in AMD K6 and later CPUs. </td></tr> <tr> <td><code>CL1INVMB</code> </td> <td><code>0F 0A</code><a href="#cite_note-363">[163]</a> </td> <td>On the Intel SCC (<a href="/wiki/Single-chip_Cloud_Computer" title="Single-chip Cloud Computer">Single-chip Cloud Computer</a>), invalidate all message buffers. The mnemonic and operation of the instruction, but not its opcode, are described in Intel's SCC architecture specification.<a href="#cite_note-364">[164]</a> </td> <td>Available on the SCC only. </td></tr> <tr> <td><code>PATCH2</code> </td> <td><code>0F 0E</code> </td> <td>On AMD K6 and later maps to <code>FEMMS</code> operation (fast clear of MMX state) but on Intel identified as <a href="/wiki/Intel_Microcode" class="mw-redirect" title="Intel Microcode">uarch</a> data read on Intel<a href="#cite_note-365">[165]</a> </td> <td>Only available in Red unlock state (<code>0F 0F</code> too) </td></tr> <tr> <td><code>PATCH3</code> </td> <td><code>0F 0F</code> </td> <td>Write uarch </td> <td>Can change RAM part of microcode on Intel </td></tr> <tr> <td><code>UMOV r,r/m</code>, <code>UMOV r/m,r</code> </td> <td><code>0F (10..13) /r</code> </td> <td>Moves data to/from user memory when operating in <a href="/wiki/In-circuit_emulation" title="In-circuit emulation">ICE</a> HALT mode.<a href="#cite_note-366">[166]</a> Acts as regular <code>MOV</code> otherwise. </td> <td>Available on some 386 and 486 processors only. Opcodes reused for SSE instructions in later CPUs. </td></tr> <tr> <td><code>NXOP</code> </td> <td><code>0F 55</code> </td> <td>NexGen hypercode interface.<a href="#cite_note-367">[167]</a> </td> <td>Available on <a href="/wiki/NexGen" title="NexGen">NexGen</a> Nx586 only. </td></tr> <tr> <td>(multiple) </td> <td><code>0F (E0..FB)</code><a href="#cite_note-368">[168]</a> </td> <td>NexGen Nx586 "hyper mode" instructions. The NexGen Nx586 CPU uses "hyper code"<a href="#cite_note-369">[169]</a> (x86 code sequences unpacked at boot time and only accessible in a special "hyper mode" operation mode, similar to DEC Alpha's <a href="/wiki/PALcode" title="PALcode">PALcode</a> and Intel's XuCode<a href="#cite_note-370">[170]</a>) for many complicated operations that are implemented with microcode in most other x86 CPUs. The Nx586 provides a large number of undocumented instructions to assist hyper mode operation. </td> <td>Available in Nx586 hyper mode only. </td></tr> <tr> <td><code>PSWAPW mm,mm/m64</code> </td> <td><code>0F 0F /r BB</code> </td> <td>Undocumented AMD 3DNow! instruction on K6-2 and K6-3. Swaps 16-bit words within 64-bit MMX register.<a href="#cite_note-371">[171]</a><a href="#cite_note-mazur_3dnow-372">[172]</a> Instruction known to be recognized by <a href="/wiki/Microsoft_Macro_Assembler" title="Microsoft Macro Assembler">MASM</a> 6.13 and 6.14. </td> <td>Available on K6-2 and K6-3 only. Opcode reused for documented <code>PSWAPD</code> instruction from AMD K7 onwards. </td></tr> <tr> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown mnemonic </td> <td><code>64 D6</code> </td> <td>Using the <code>64</code> (FS: segment) prefix with the undocumented <code>D6</code> (<code>SALC</code>/<code>SETALC</code>) instruction will, on UMC CPUs only, cause EAX to be set to <code>0xAB6B1B07</code>.<a href="#cite_note-potemkin-373">[173]</a><a href="#cite_note-374">[174]</a> </td> <td>Available on the <a href="/wiki/UMC_Green_CPU" title="UMC Green CPU">UMC Green CPU</a> only. Executes as <code>SALC</code> on non-UMC CPUs. </td></tr> <tr> <td><code>FS: Jcc</code> </td> <td><code>64 (70..7F) rel8</code>, <code>64 0F (80..8F) rel16/32</code> </td> <td>On Intel <a href="/wiki/NetBurst" title="NetBurst">NetBurst</a> (Pentium 4) CPUs, the 64h (FS: segment) instruction prefix will, when used with conditional branch instructions, act as a branch hint to indicate that the branch will be alternating between taken and not-taken.<a href="#cite_note-375">[175]</a> Unlike other NetBurst branch hints (CS: and DS: segment prefixes), this hint is not documented. </td> <td>Available on NetBurst CPUs only. Segment prefixes on conditional branches are accepted but ignored by non-NetBurst CPUs. </td></tr> <tr> <td><code>JMPAI</code> </td> <td><code>0F 3F</code> </td> <td>Jump and execute instructions in the undocumented <a href="/wiki/Alternate_Instruction_Set" title="Alternate Instruction Set">Alternate Instruction Set</a>. </td> <td>Only available on some x86 processors made by <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA Technologies</a>. </td></tr> <tr> <td>(<a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA4</a>) </td> <td><code>VEX.66.0F38 (5C..5F,68..6F,78..7F) /r imm8</code> </td> <td>On AMD Zen1, FMA4 instructions are present but undocumented (missing CPUID flag). The reason for leaving the feature undocumented may or may not have been due to a buggy implementation.<a href="#cite_note-376">[176]</a> </td> <td>Removed from Zen2 onwards. </td></tr> <tr> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">(unknown, multiple) </td> <td><code>0F 0F /r ??</code> </td> <td>The whitepapers for SandSifter<a href="#cite_note-sandsifter-377">[177]</a> and UISFuzz<a href="#cite_note-uisfuzz-378">[178]</a> report the detection of large numbers of undocumented instructions in the 3DNow! opcode range on several different AMD CPUs (at least <a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode NX</a> and <a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">C-50</a>). Their operation is not known. On at least AMD K6-2, all of the unassigned 3DNow! opcodes (other than the undocumented <code>PF2IW</code>, <code>PI2FW</code> and <code>PSWAPW</code> instructions) are reported to execute as equivalents of <code>POR</code> (MMX bitwise-OR instruction).<a href="#cite_note-mazur_3dnow-372">[172]</a> </td> <td>Present on some AMD CPUs with 3DNow!. </td></tr> <tr> <td><code>MOVDB</code>, <code>GP2MEM</code> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a>'s article "MediaGX Targets Low-Cost PCs" from 1997, covering the introduction of the Cyrix <a href="/wiki/MediaGX" title="MediaGX">MediaGX</a> processor, lists several new instructions that are said to have been added to this processor in order to support its new "Virtual System Architecture" features, including <code>MOVDB</code> and <code>GP2MEM</code> – and also mentions that Cyrix did not intend to publish specifications for these instructions.<a href="#cite_note-379">[179]</a> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown. No specification known to have been published. </td></tr> <tr> <th colspan="5"> </th></tr> <tr> <td><code>REP XSHA512</code> </td> <td><code>F3 0F A6 E0</code> </td> <td>Perform <a href="/wiki/SHA-2" title="SHA-2">SHA-512</a> hashing. Supported by OpenSSL<a href="#cite_note-380">[180]</a> as part of its <a href="/wiki/VIA_PadLock" title="VIA PadLock">VIA PadLock</a> support, and listed in a Zhaoxin-supplied Linux kernel patch,<a href="#cite_note-381">[181]</a> but not documented by the <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100526054140/http://linux.via.com.tw/support/beginDownload.action?eleid=181&fid=261">VIA PadLock Programming Guide</a>. </td> <td rowspan="4">Only available on some x86 processors made by <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA Technologies</a> and <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a>. </td></tr> <tr> <td><code>REP XMODEXP</code> </td> <td><code>F3 0F A6 F8</code> </td> <td rowspan="2">Instructions to perform <a href="/wiki/Modular_exponentiation" title="Modular exponentiation">modular exponentiation</a> and <a href="/wiki/Hardware_random_number_generator" title="Hardware random number generator">random number generation</a>, respectively. Listed in a VIA-supplied patch to add support for VIA Nano-specific PadLock instructions to OpenSSL,<a href="#cite_note-382">[182]</a> but not documented by the VIA PadLock Programming Guide. </td></tr> <tr> <td><code>XRNG2</code> </td> <td><code>F3 0F A7 F8</code> </td></tr> <tr> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown mnemonic </td> <td><code>0F A7 (C1..C7)</code> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Detected by CPU fuzzing tools such as SandSifter<a href="#cite_note-sandsifter-377">[177]</a> and UISFuzz<a href="#cite_note-uisfuzz-378">[178]</a> as executing without causing #UD on several different VIA and Zhaoxin CPUs. Unknown operation, may be related to the documented <code>XSTORE</code> (<code>0F A7 C0</code>) instruction. </td></tr> <tr> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown mnemonic </td> <td><code>F2 0F A6 C0</code> </td> <td><a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> <a href="/wiki/SM9_(cryptography_standard)" title="SM9 (cryptography standard)">SM2</a> instruction. <a href="/wiki/CPUID" title="CPUID">CPUID</a> flags listed in a Linux kernel patch for OpenEuler,<a href="#cite_note-openeuler_zx_cpuid-383">[183]</a> description and opcode (but no instruction mnemonic) provided in a Zhaoxin patent application<a href="#cite_note-384">[184]</a> and a Zhaoxin-provided Linux kernel patch.<a href="#cite_note-385">[185]</a> </td> <td>Present in Zhaoxin KX-6000G.<a href="#cite_note-zx6000g_cpuid-386">[186]</a> </td></tr> <tr> <td><code>ZXPAUSE</code> </td> <td><code>F2 0F A6 D0</code> </td> <td>Pause the processor until the <a href="/wiki/Time_Stamp_Counter" title="Time Stamp Counter">Time Stamp Counter</a> reaches or exceeds the value specified in EDX:EAX. Low-power processor C-state can be requested in ECX. Listed in OpenEuler kernel patch.<a href="#cite_note-387">[187]</a> </td> <td>Present in Zhaoxin KX-7000. </td></tr> <tr> <td><code>MONTMUL2</code> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td>Zhaoxin RSA/"xmodx" instructions. Mnemonics and CPUID flags are listed in a Linux kernel patch for OpenEuler,<a href="#cite_note-openeuler_zx_cpuid-383">[183]</a> but opcodes and instruction descriptions are not available. </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown. Some Zhaoxin CPUs<a href="#cite_note-zx6000g_cpuid-386">[186]</a> have the CPUID flags for these instructions set. </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Undocumented_x87_instructions">Undocumented x87 instructions</h3>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=28" title="Edit section: Undocumented x87 instructions">edit</a>]</div> <table class="wikitable sortable"> <tbody><tr> <th>Mnemonics </th> <th>Opcodes </th> <th>Description </th> <th>Status </th></tr> <tr> <td><code>FENI</code>, <code>FENI8087_NOP</code> </td> <td><code>DB E0</code> </td> <td>FPU Enable Interrupts (8087) </td> <td rowspan="3">Documented for the Intel 80287.<a href="#cite_note-i80287-299">[125]</a> Present on all Intel x87 FPUs from 80287 onwards. For FPUs other than the ones where they were introduced on (8087 for <code>FENI</code>/<code>FDISI</code> and 80287 for <code>FSETPM</code>), they act as <code>NOP</code>s. These instructions and their operation on modern CPUs are commonly mentioned in later Intel documentation, but with opcodes omitted and opcode table entries left blank (e.g. <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/671200/325462-sdm-vol-1-2abcd-3abcd.pdf">Intel SDM 325462-077, April 2022</a> mentions them twice without opcodes). The opcodes are, however, recognized by Intel XED.<a href="#cite_note-388">[188]</a> </td></tr> <tr> <td><code>FDISI</code>, <code>FDISI8087_NOP</code> </td> <td><code>DB E1</code> </td> <td>FPU Disable Interrupts (8087) </td></tr> <tr> <td><code>FSETPM</code>, <code>FSETPM287_NOP</code> </td> <td><code>DB E4</code> </td> <td>FPU Set Protected Mode (80287) </td></tr> <tr> <td>(no mnemonic) </td> <td><code>D9 D7</code>,  <code>D9 E2</code>, <code>D9 E7</code>,  <code>DD FC</code>, <code>DE D8</code>,  <code>DE DA</code>, <code>DE DC</code>,  <code>DE DD</code>, <code>DE DE</code>,  <code>DF FC</code> </td> <td>"Reserved by Cyrix" opcodes </td> <td>These opcodes are listed as reserved opcodes that will produce "unpredictable results" without generating exceptions on at least Cyrix 6x86,<a href="#cite_note-389">[189]</a> 6x86MX, MII, MediaGX, and AMD Geode GX/LX.<a href="#cite_note-390">[190]</a> (The documentation for these CPUs all list the same ten opcodes.) Their actual operation is not known, nor is it known whether their operation is the same on all of these CPUs. </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=29" title="Edit section: See also">edit</a>]</div> <ul><li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a></li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></li> <li><a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">Advanced Vector Extensions 2</a></li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a></li> <li><a href="/wiki/X86_Bit_manipulation_instruction_set" title="X86 Bit manipulation instruction set">x86 Bit manipulation instruction set</a></li> <li><a href="/wiki/CPUID" title="CPUID">CPUID</a></li> <li><a href="/wiki/List_of_discontinued_x86_instructions" title="List of discontinued x86 instructions">List of discontinued x86 instructions</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=30" title="Edit section: References">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-:0-1"><a href="#cite_ref-:0_1-0">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html?wapkw=processor-identification-cpuid-instruction">"Re: Intel Processor Identification and the CPUID Instruction"</a>. Retrieved 2013-04-21.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+Intel+Processor+Identification+and+the+CPUID+Instruction&rft_id=http%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fprocessors%2Fprocessor-identification-cpuid-instruction-note.html%3Fwapkw%3Dprocessor-identification-cpuid-instruction&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-2"><a href="#cite_ref-2">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://eecs.wsu.edu/~ee314/handouts/x86ref.pdf">"Intel 80x86 Instruction Set Summary"</a> (PDF). eecs.wsu.edu.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=eecs.wsu.edu&rft.atitle=Intel+80x86+Instruction+Set+Summary&rft_id=https%3A%2F%2Feecs.wsu.edu%2F~ee314%2Fhandouts%2Fx86ref.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-3"><a href="#cite_ref-3">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="https://www.os2museum.com/wp/sgdtsidt-fiction-and-reality/">SGDT/SIDT Fiction and Reality</a>, 4 May 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231129085923/https://www.os2museum.com/wp/sgdtsidt-fiction-and-reality/">Archived</a> on 29 Nov 2023. </li> <li id="cite_note-loadall286_doc-7">^ <a href="#cite_ref-loadall286_doc_7-0">a</a> <a href="#cite_ref-loadall286_doc_7-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://docs.pcjs.org/manuals/intel/80286/80286_LOADALL.pdf">Undocumented iAPX 286 Test Instruction</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231220173720/https://docs.pcjs.org/manuals/intel/80286/80286_LOADALL.pdf">Archived</a> on 20 Dec 2023. </li> <li id="cite_note-9"><a href="#cite_ref-9">^</a> WikiChip, <a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/x86/umip">UMIP – x86</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230316111706/https://en.wikichip.org/wiki/x86/umip">Archived</a> on 16 Mar 2023. </li> <li id="cite_note-10"><a href="#cite_ref-10">^</a> Oracle Corp, <a rel="nofollow" class="external text" href="https://docs.oracle.com/en/virtualization/virtualbox/6.0/admin/swvirt-details.html">Oracle® VM VirtualBox Administrator's Guide for Release 6.0, section 3.5: Details About Software Virtualization</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231208205121/https://docs.oracle.com/en/virtualization/virtualbox/6.0/admin/swvirt-details.html">Archived</a> on 8 Dec 2023. </li> <li id="cite_note-11"><a href="#cite_ref-11">^</a> MBC Project, <a rel="nofollow" class="external text" href="https://github.com/MBCProject/mbc-markdown/blob/7223fa76d69015ceb63cb094257e64c3cc6bf3b9/anti-behavioral-analysis/virtual-machine-detection.md">Virtual Machine Detection (permanent link)</a> or <a rel="nofollow" class="external text" href="https://github.com/MBCProject/mbc-markdown/blob/main/anti-behavioral-analysis/virtual-machine-detection.md">Virtual Machine Detection (non permanent link)</a> </li> <li id="cite_note-15"><a href="#cite_ref-15">^</a> Andrew Schulman, "Unauthorized Windows 95" (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-56884-169-8" title="Special:BookSources/1-56884-169-8">1-56884-169-8</a>), chapter 8, p.249,257. </li> <li id="cite_note-16"><a href="#cite_ref-16">^</a> <a rel="nofollow" class="external text" href="https://patents.google.com/patent/US4974159A/">US Patent 4974159</a>, "Method of transferring control in a multitasking computer system" mentions 63h/ARPL. </li> <li id="cite_note-18"><a href="#cite_ref-18">^</a> Intel, <a rel="nofollow" class="external text" href="https://ardent-tool.com/CPU/docs/Intel/Pentium/241430-004.pdf">Pentium® Processor Family Developer’s Manual, Volume 3</a>, 1995, order no. 241430-004, section 12.7, p. 323 </li> <li id="cite_note-20"><a href="#cite_ref-20">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/intel-analysis-microarchitectural-data-sampling.html">How Microarchitectural Data Sampling works</a>, see mitigations section. <a rel="nofollow" class="external text" href="https://archive.today/20220422211750/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/intel-analysis-microarchitectural-data-sampling.html">Archived</a> on Apr 22,2022 </li> <li id="cite_note-21"><a href="#cite_ref-21">^</a> Linux kernel documentation, <a rel="nofollow" class="external text" href="https://www.kernel.org/doc/html/latest/x86/mds.html">Microarchitectural Data Sampling (MDS) mitigation</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201021233511/https://www.kernel.org/doc/html/latest/x86/mds.html">Archived</a> 2020-10-21 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </li> <li id="cite_note-23"><a href="#cite_ref-23">^</a> VCF Forums, <a rel="nofollow" class="external text" href="https://forum.vcfed.org/index.php?threads/i-found-the-saveall-opcode.71519/">I found the SAVEALL opcode</a>, jun 21, 2019. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230413203921/https://forum.vcfed.org/index.php?threads/i-found-the-saveall-opcode.71519/">Archived</a> on 13 Apr 2023. </li> <li id="cite_note-24"><a href="#cite_ref-24">^</a> rep lodsb, <a rel="nofollow" class="external text" href="https://rep-lodsb.mataroa.blog/blog/intel-286-secrets-ice-mode-and-f1-0f-04/">Intel 286 secrets: ICE mode and F1 0F 04</a>, aug 12, 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231208175920/https://rep-lodsb.mataroa.blog/blog/intel-286-secrets-ice-mode-and-f1-0f-04/">Archived</a> on 8 Dec 2023. </li> <li id="cite_note-35"><a href="#cite_ref-35">^</a> LKML, <a rel="nofollow" class="external text" href="https://lkml.org/lkml/2014/4/29/626">(PATCH) x86-64, espfix: Don't leak bits 31:16 of %esp returning to 16-bit stack</a>, Apr 29, 2014. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180104155340/https://lkml.org/lkml/2014/4/29/626">Archived</a> on Jan 4, 2018 </li> <li id="cite_note-36"><a href="#cite_ref-36">^</a> Raymond Chen, <a rel="nofollow" class="external text" href="https://devblogs.microsoft.com/oldnewthing/20160404-00/?p=93261">Getting MS-DOS games to run on Windows 95: Working around the iretd problem</a>, Apr 4, 2016. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190315174141/https://devblogs.microsoft.com/oldnewthing/20160404-00/?p=93261">Archived</a> on Mar 15, 2019 </li> <li id="cite_note-43"><a href="#cite_ref-43">^</a> sandpile.org, <a rel="nofollow" class="external text" href="https://www.sandpile.org/x86/flags.htm">x86 architecture rFLAGS register</a>, see note #7. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20111103093624/https://www.sandpile.org/x86/flags.htm">Archived</a> on 3 Nov 2011. </li> <li id="cite_note-51"><a href="#cite_ref-51">^</a> iPXE, <a rel="nofollow" class="external text" href="https://github.com/ipxe/ipxe/commit/bc35b24e3ebd2996b2484b7f9ceb96a3cf25823a">Commit bc35b24: Fix use of writable code segment on 486 and earlier CPUs</a>, Github, Feb 2, 2022 − indicates that when leaving protected mode on 386/486 by writing to <code>CR0</code>, it is specifically necessary to do a far <code>JMP</code> (opcode <code>EA</code>) in order to restore proper real-mode access-rights for the CS segment, and that other far control transfers (e.g. <code>RETF</code>, <code>IRET</code>) will not do this. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20241104213948/https://github.com/ipxe/ipxe/commit/bc35b24e3ebd2996b2484b7f9ceb96a3cf25823a">Archived</a> on 4 Nov 2024. </li> <li id="cite_note-52"><a href="#cite_ref-52">^</a> Can Bölük, <a rel="nofollow" class="external text" href="https://blog.can.ac/2021/03/22/speculating-x86-64-isa-with-one-weird-trick/">Speculating the entire x86-64 Instruction Set In Seconds with This One Weird Trick</a>, Mar 22, 2021. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210323035913/https://blog.can.ac/2021/03/22/speculating-x86-64-isa-with-one-weird-trick/">Archived</a> on Mar 23, 2021. </li> <li id="cite_note-rcollins_undoc-55">^ <a href="#cite_ref-rcollins_undoc_55-0">a</a> <a href="#cite_ref-rcollins_undoc_55-1">b</a> Robert Collins, <a rel="nofollow" class="external text" href="http://www.rcollins.org/secrets/OpCodes.html">Undocumented OpCodes</a>, 29 july 1995. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010221221019/http://www.rcollins.org/secrets/OpCodes.html">Archived</a> on 21 feb 2001 </li> <li id="cite_note-56"><a href="#cite_ref-56">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="https://www.os2museum.com/wp/icebp-finally-documented/">ICEBP finally documented</a>, OS/2 Museum, May 25, 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180606211954/https://www.os2museum.com/wp/icebp-finally-documented/">Archived</a> on 6 June 2018 </li> <li id="cite_note-intel_ap526_001-57"><a href="#cite_ref-intel_ap526_001_57-0">^</a> Intel, <a rel="nofollow" class="external text" href="https://web.archive.org/web/19961222093646/http://www.intel.com/design/pro/applnots/24281601.pdf">AP-526: Optimization For Intel's 32-bit Processors</a>, order no. 242816-001, october 1995 – lists <code>SALC</code> on page 83, <code>INT1</code> on page 86 and <code>FFREEP</code> on page 114. Archived from the <a rel="nofollow" class="external text" href="http://www.intel.com/design/pro/applnots/24281601.pdf">original</a> on 22 Dec 1996. </li> <li id="cite_note-58"><a href="#cite_ref-58">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD64/24593_APM_v2-r3.06.pdf">AMD 64-bit Technology, vol 2: System Programming</a>, order no. 24593, rev 3.06, aug 2002, page 248 </li> <li id="cite_note-62"><a href="#cite_ref-62">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pcjs.org/documents/manuals/intel/80386/#b0-stepping">"Intel 80386 CPU Information | PCjs Machines"</a>. www.pcjs.org.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.pcjs.org&rft.atitle=Intel+80386+CPU+Information+%26%23124%3B+PCjs+Machines&rft_id=https%3A%2F%2Fwww.pcjs.org%2Fdocuments%2Fmanuals%2Fintel%2F80386%2F%23b0-stepping&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-63"><a href="#cite_ref-63">^</a> Geoff Chappell, <a rel="nofollow" class="external text" href="https://www.geoffchappell.com/studies/windows/km/cpu/precpuid.htm?tx=245">CPU Identification before CPUID</a>, 27 Jan 2020. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220407203913/https://www.geoffchappell.com/studies/windows/km/cpu/precpuid.htm?tx=245">Archived</a> on 7 Apr 2023. </li> <li id="cite_note-65"><a href="#cite_ref-65">^</a> Jeff Parsons, <a rel="nofollow" class="external text" href="https://www.pcjs.org/documents/manuals/intel/80386/ibts_xbts/">Obsolete 80386 Instructions: IBTS and XBTS</a>, PCjs Machines. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200919154722/https://www.pcjs.org/documents/manuals/intel/80386/ibts_xbts/">Archived</a> on Sep 19, 2020. </li> <li id="cite_note-67"><a href="#cite_ref-67">^</a> Robert Collins, <a rel="nofollow" class="external text" href="https://web.archive.org/web/19970605213204/http://www.x86.org/articles/loadall/tspec_a3_doc.html">The LOADALL Instruction</a>. Archived from the <a rel="nofollow" class="external text" href="http://www.x86.org/articles/loadall/tspec_a3_doc.html">original</a> on Jun 5, 1997. </li> <li id="cite_note-toth-19980316-69"><a href="#cite_ref-toth-19980316_69-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFToth1998" class="citation web cs1">Toth, Ervin (1998-03-16). <a rel="nofollow" class="external text" href="https://web.archive.org/web/19991103025640/http://www.df.lth.se/~john_e/gems/gem000c.html">"BSWAP with 16-bit registers"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.df.lth.se/~john_e/gems/gem000c.html">the original</a> on 1999-11-03. <q>The instruction brings down the upper word of the doubleword register without affecting its upper 16 bits.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=BSWAP+with+16-bit+registers&rft.date=1998-03-16&rft.aulast=Toth&rft.aufirst=Ervin&rft_id=http%3A%2F%2Fwww.df.lth.se%2F~john_e%2Fgems%2Fgem000c.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-coldwin-20091229-70"><a href="#cite_ref-coldwin-20091229_70-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFColdwin2009" class="citation web cs1">Coldwin, Gynvael (2009-12-29). <a rel="nofollow" class="external text" href="https://gynvael.coldwind.pl/?id=268">"BSWAP + 66h prefix"</a>. Retrieved 2018-10-03. <q>internal (zero-)extending the value of a smaller (16-bit) register … applying the bswap to a 32-bit value "00 00 AH AL", … truncated to lower 16-bits, which are "00 00". … Bochs … bswap reg16 acts just like the bswap reg32 … QEMU … ignores the 66h prefix</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=BSWAP+%2B+66h+prefix&rft.date=2009-12-29&rft.aulast=Coldwin&rft.aufirst=Gynvael&rft_id=https%3A%2F%2Fgynvael.coldwind.pl%2F%3Fid%3D268&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-72"><a href="#cite_ref-72">^</a> Intel <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Intel/486/datasheets/240440-001.pdf">"i486 Microprocessor"</a> (April 1989, order no. 240440-001) p.142 lists <code>CMPXCHG</code> with <code>0F A6/A7</code> encodings. </li> <li id="cite_note-73"><a href="#cite_ref-73">^</a> Intel <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Intel/486/datasheets/240440-002.pdf">"i486 Microprocessor"</a> (November 1989, order no. 240440-002) p.135 lists <code>CMPXCHG</code> with <code>0F B0/B1</code> encodings. </li> <li id="cite_note-74"><a href="#cite_ref-74">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/486/Intel486.htm">"Intel 486 & 486 POD CPUID, S-spec, & Steppings"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+486+%26+486+POD+CPUID%2C+S-spec%2C+%26+Steppings&rft_id=http%3A%2F%2Fdatasheets.chipdb.org%2FIntel%2Fx86%2F486%2FIntel486.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-79"><a href="#cite_ref-79">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/develop/external/us/en/documents/329298-002-629101.pdf">Software Guard Extensions Programming Reference</a>, order no. 329298-002, oct 2014, sections 3.5 and 3.6.5. </li> <li id="cite_note-82"><a href="#cite_ref-82">^</a> Frank van Gilluwe, "The Undocumented PC, second edition", 1997, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-201-47950-8" title="Special:BookSources/0-201-47950-8">0-201-47950-8</a>, page 55 </li> <li id="cite_note-83"><a href="#cite_ref-83">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/revision-guides/25759.pdf">Revision Guide for AMD Athlon 64 and AMD Opteron Processors</a> pub.no. 25759, rev 3.79, July 2009, page 34. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231220133454/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/revision-guides/25759.pdf">Archived</a> on 20 Dec 2023. </li> <li id="cite_note-85"><a href="#cite_ref-85">^</a> Intel, <a rel="nofollow" class="external text" href="http://kib.kiev.ua/x86docs/Intel/SDMs/253668-078.pdf">Software Developer’s Manual, vol 3A</a>, order no. 253668-078, Dec 2022, section 9.3, page 299. </li> <li id="cite_note-86"><a href="#cite_ref-86">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html">CPUID Enumeration and Architectural MSRs</a>, 8 Aug 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240523214955/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/cpuid-enumeration-and-architectural-msrs.html">Archived</a> on 23 May 2024. </li> <li id="cite_note-amd_56713_p116-87"><a href="#cite_ref-amd_56713_p116_87-0">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">PPR for AMD Family 19h Model 61h, Revision B1 processors</a>, document no. 56713, rev 3.05, mar 8 2023, page 116. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip">Archived</a> on Apr 25, 2023. </li> <li id="cite_note-89"><a href="#cite_ref-89">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120312224625/http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc279.htm">"RSM—Resume from System Management Mode"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.softeng.rl.ac.uk/st/archive/SoftEng/SESP/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc279.htm">the original</a> on 2012-03-12.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=RSM%E2%80%94Resume+from+System+Management+Mode&rft_id=http%3A%2F%2Fwww.softeng.rl.ac.uk%2Fst%2Farchive%2FSoftEng%2FSESP%2Fhtml%2FSoftwareTools%2Fvtune%2Fusers_guide%2FmergedProjects%2Fanalyzer_ec%2FmergedProjects%2Freference_olh%2FmergedProjects%2Finstructions%2Finstruct32_hh%2Fvc279.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-90"><a href="#cite_ref-90">^</a> Microprocessor Report, <a rel="nofollow" class="external text" href="http://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/060805.PDF">System Management Mode Explained</a> (vol 6, no. 8, june 17, 1992). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220629220530/https://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/060805.PDF">Archived</a> on Jun 29, 2022. </li> <li id="cite_note-91"><a href="#cite_ref-91">^</a> Ellis, Simson C., "The 386 SL Microprocessor in Notebook PCs", Intel Corporation, Microcomputer Solutions, March/April 1991, page 20 </li> <li id="cite_note-cx486slce-93"><a href="#cite_ref-cx486slce_93-0">^</a> <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/cyrix/Cyrix_Cx486SLCe_Data_Sheet_1992.pdf">Cyrix 486SLC/e Data Sheet (1992)</a>, section 2.6.4 </li> <li id="cite_note-94"><a href="#cite_ref-94">^</a> Linux 6.3 kernel sources, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v6.3/source/arch/x86/include/asm/cpuid.h">/arch/x86/include/asm/cpuid.h</a>, line 69 </li> <li id="cite_note-95"><a href="#cite_ref-95">^</a> gcc-patches mailing list, <a rel="nofollow" class="external text" href="https://gcc.gnu.org/pipermail/gcc-patches/2019-May/522177.html">CPUID Patch for IDT Winchip</a>, May 21, 2019. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230427201255/https://gcc.gnu.org/pipermail/gcc-patches/2019-May/522177.html">Archived</a> on Apr 27, 2023. </li> <li id="cite_note-97"><a href="#cite_ref-97">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf">Intel® Virtualization Technology FlexMigration Application Note</a> order no. 323850-004, oct 2012, section 2.3.2 on page 12. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20141013075554/https://www.intel.com/content/dam/www/public/us/en/documents/application-notes/virtualization-technology-flexmigration-application-note.pdf">Archived</a> on Oct 13, 2014. </li> <li id="cite_note-98"><a href="#cite_ref-98">^</a> Intel, <a rel="nofollow" class="external text" href="https://ru.mouser.com/datasheet/2/612/c3000-family-datasheet-1623704.pdf">Atom Processor C3000 Product Family Datasheet</a> order no. 337018-002, Feb 2018, pages 133, 3808 and 3814. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220209183514/https://ru.mouser.com/datasheet/2/612/c3000-family-datasheet-1623704.pdf">Archived</a> on Feb 9, 2022. </li> <li id="cite_note-99"><a href="#cite_ref-99">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.34.pdf">AMD64 Architecture Programmer’s Manual Volume 3</a> pub.no. 24594, rev 3.34, oct 2022, p. 165 (entry on <code>CPUID</code> instruction) </li> <li id="cite_note-103"><a href="#cite_ref-103">^</a> Robert Collins, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20001218003500/http://www.rcollins.org/ddj/Nov96/Nov96.html">CPUID Algorithm Wars</a>, nov 1996. Archived from the <a rel="nofollow" class="external text" href="http://www.rcollins.org/ddj/Nov96/Nov96.html">original</a> on dec 18, 2000. </li> <li id="cite_note-107"><a href="#cite_ref-107">^</a> Geoff Chappell, <a rel="nofollow" class="external text" href="https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm">CMPXCHG8B Support in the 32-Bit Windows Kernel</a>, 23 jan 2008. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231105001739/https://www.geoffchappell.com/studies/windows/km/cpu/cx8.htm">Archived</a> on 5 Nov 2023. </li> <li id="cite_note-rdtsc_ordering-109">^ <a href="#cite_ref-rdtsc_ordering_109-0">a</a> <a href="#cite_ref-rdtsc_ordering_109-1">b</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/325462-077.pdf">Software Developer's Manual</a>, order no. 325426-077, Nov 2022 – the entry on the <code>RDTSC</code> instruction on p.1739 describes the instruction sequences required to order the <code>RDTSC</code> instruction with respect to earlier and later instructions. </li> <li id="cite_note-111"><a href="#cite_ref-111">^</a> Linux kernel 5.4.12, <a rel="nofollow" class="external text" href="https://elixir.bootlin.com/linux/v5.4.12/source/arch/x86/kernel/cpu/centaur.c#L110">/arch/x86/kernel/cpu/centaur.c</a> </li> <li id="cite_note-112"><a href="#cite_ref-112">^</a> Stack Overflow, <a rel="nofollow" class="external text" href="https://stackoverflow.com/questions/62492053/can-constant-non-invariant-tsc-change-frequency-across-cpu-states">Can constant non-invariant tsc change frequency across cpu states?</a> Accessed 24 Jan 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230124204354/https://stackoverflow.com/questions/62492053/can-constant-non-invariant-tsc-change-frequency-across-cpu-states">Archived</a> on 24 Jan 2023. </li> <li id="cite_note-113"><a href="#cite_ref-113">^</a> CPU-World, <a rel="nofollow" class="external text" href="https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=81992">CPUID for Zhaoxin KaiXian KX-5000 KX-5650 (by timw4mail)</a>, 24 Apr 2024. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240426121032/https://www.cpu-world.com/cgi-bin/CPUID.pl?CPUID=81992">Archived</a> on 26 Apr 2024. </li> <li id="cite_note-115"><a href="#cite_ref-115">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/undocumented-rdtsc/">"Undocumented RDTSC"</a>, 27 Apr 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231216114233/http://www.os2museum.com/wp/undocumented-rdtsc/">Archived</a> on 16 Dec 2023. </li> <li id="cite_note-121"><a href="#cite_ref-121">^</a> Willy Tarreau, <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/20091110220652.GE26633@1wt.eu/">Re: i686 quirk for AMD Geode</a>, Linux Kernel Mailing List, 10 Nov 2009. </li> <li id="cite_note-123"><a href="#cite_ref-123">^</a> Intel, <a rel="nofollow" class="external text" href="https://cdrdv2-public.intel.com/821612/248966-Optimization-Reference-Manual-V1-050.pdf">Intel 64 and IA-32 Architectures Optimization Reference Manual: Volume 1</a>, order no. 248966-050US, April 2024, section 3.5.1.9, page 119. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240509192742/https://cdrdv2-public.intel.com/821612/248966-Optimization-Reference-Manual-V1-050.pdf">Archived</a> on 9 May 2024. </li> <li id="cite_note-126"><a href="#cite_ref-126">^</a> JookWiki, <a rel="nofollow" class="external text" href="https://www.jookia.org/wiki/Nopl">"nopl"</a>, sep 24, 2022 – provides a lengthy account of the history of the long NOP and the issues around it. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20221028233225/https://www.jookia.org/wiki/Nopl">Archived</a> on oct 28, 2022. </li> <li id="cite_note-longnop2006-127">^ <a href="#cite_ref-longnop2006_127-0">a</a> <a href="#cite_ref-longnop2006_127-1">b</a> Intel Community: <a rel="nofollow" class="external text" href="https://community.intel.com/t5/Software-Archive/Multi-byte-NOP-opcode-made-official/td-p/932580">Multibyte NOP Made Official</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220407203915/https://community.intel.com/t5/Software-Archive/Multi-byte-NOP-opcode-made-official/td-p/932580">Archived</a> on 7 Apr 2022. </li> <li id="cite_note-128"><a href="#cite_ref-128">^</a> Intel <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html">Software Developers Manual, vol 3B</a> (order no 253669-076us, December 2021), section 22.15 "Reserved NOP" </li> <li id="cite_note-130"><a href="#cite_ref-130">^</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.02.pdf">AMD 64-bit Technology – AMD x86-64 Architecture Programmer’s Manual Volume 3</a>, publication no. 24594, rev 3.02, aug 2002, page 379. </li> <li id="cite_note-132"><a href="#cite_ref-132">^</a> Debian bug report logs, <a rel="nofollow" class="external text" href="https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=464962#148">-686 build uses long noops, that are unsupported by Transmeta Crusoe, immediate crash on boot</a>, see messages 148 and 158 for NOPL on VIA C7. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190801174955/https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=464962#148">Archived</a> on 1 Aug 2019 </li> <li id="cite_note-133"><a href="#cite_ref-133">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Intel/IA/243191-001.pdf">Intel Architecture Software Developer’s Manual, Volume 2</a>, 1997, order no. 243191-001, pages 3-9 and A-7. </li> <li id="cite_note-135"><a href="#cite_ref-135">^</a> John Hassey, <a rel="nofollow" class="external text" href="https://sourceware.org/pipermail/gas2/1995/000421.html">Pentium Pro changes</a>, GAS2 mailing list, 28 dec 1995 – patch that added the <code>UD2A</code> and <code>UD2B</code> instruction mnemomics to GNU Binutils. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230725214633/https://sourceware.org/pipermail/gas2/1995/000421.html">Archived</a> on 25 Jul 2023. </li> <li id="cite_note-136"><a href="#cite_ref-136">^</a> Jan Beulich, <a rel="nofollow" class="external text" href="https://sourceware.org/pipermail/binutils-cvs/2017-November/046908.html">x86: correct UDn</a>, binutils-gdb mailing list, 23 nov 2017 – Binutils patch that added ModR/M byte to <code>UD1</code>/<code>UD2B</code> and added <code>UD0</code>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230725214642/https://sourceware.org/pipermail/binutils-cvs/2017-November/046908.html">Archived</a> on 25 Jul 2023. </li> <li id="cite_note-138"><a href="#cite_ref-138">^</a> Intel, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20030316105019/http://developer.intel.com/design/pentium4/manuals/24896607.pdf">Intel Pentium 4 and Intel Xeon Processor Optimization Reference Manual</a>, order no. 248966-007, see "Assembly/Compiler Coding Rule 13" on page 74. Archived from the <a rel="nofollow" class="external text" href="http://developer.intel.com/design/pentium4/manuals/24896607.pdf">original</a> on 16 Mar 2003. </li> <li id="cite_note-141"><a href="#cite_ref-141">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Intel/Pentium/241430-004.pdf">Pentium® Processor Family Developer's Manual Volume 3</a>, 1995. order no. 241430-004, appendix A, page 943 – reserves the opcodes <code>0F 0B</code> and <code>0F B9</code>. </li> <li id="cite_note-amd_ud0_ud1-142">^ <a href="#cite_ref-amd_ud0_ud1_142-0">a</a> <a href="#cite_ref-amd_ud0_ud1_142-1">b</a> AMD, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/AMD/AMD64/24594_APM_v3-r3.17.pdf">AMD64 Architecture Programmer’s Manual Volume 3</a>, publication no. 24594, rev 3.17, dec 2011 – see page 416 for <code>UD0</code> and page 415 and 419 for <code>UD1</code>. </li> <li id="cite_note-intel_ud0_ud1-143">^ <a href="#cite_ref-intel_ud0_ud1_143-0">a</a> <a href="#cite_ref-intel_ud0_ud1_143-1">b</a> <a href="#cite_ref-intel_ud0_ud1_143-2">c</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253667-061.pdf">Software Developer's Manual, vol 2B</a>, order no. 253667-061, dec 2016 – lists <code>UD1</code> (with <a href="/wiki/ModR/M" title="ModR/M">ModR/M</a> byte) and <code>UD0</code> (without ModR/M byte) on page 4-687. </li> <li id="cite_note-145"><a href="#cite_ref-145">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFStecklina2019" class="citation web cs1">Stecklina, Julian (2019-02-08). <a rel="nofollow" class="external text" href="https://x86.lol/generic/2019/02/08/fingerprint.html">"Fingerprinting x86 CPUs using Illegal Opcodes"</a>. x86.lol. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231215165112/https://x86.lol/generic/2019/02/08/fingerprint.html">Archived</a> from the original on 15 Dec 2023. Retrieved 2023-12-15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=x86.lol&rft.atitle=Fingerprinting+x86+CPUs+using+Illegal+Opcodes&rft.date=2019-02-08&rft.aulast=Stecklina&rft.aufirst=Julian&rft_id=https%3A%2F%2Fx86.lol%2Fgeneric%2F2019%2F02%2F08%2Ffingerprint.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-146"><a href="#cite_ref-146">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/intelxed/xed/commit/7561f549d787edc55949b671dee2255a8435741a">"ud0 length fix · intelxed/xed@7561f54"</a>. GitHub. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230601122641/https://github.com/intelxed/xed/commit/7561f549d787edc55949b671dee2255a8435741a">Archived</a> from the original on 1 Jun 2023. Retrieved 2023-12-15.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=ud0+length+fix+%C2%B7+intelxed%2Fxed%407561f54&rft_id=https%3A%2F%2Fgithub.com%2Fintelxed%2Fxed%2Fcommit%2F7561f549d787edc55949b671dee2255a8435741a&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-cyrix_oio-148">^ <a href="#cite_ref-cyrix_oio_148-0">a</a> <a href="#cite_ref-cyrix_oio_148-1">b</a> Cyrix, <a rel="nofollow" class="external text" href="https://ardent-tool.com/CPU/docs/Cyrix/6x86/94175.pdf">6x86 processor data book</a>, 1996, order no. 94175-01, table 6-20, page 209 – uses the mnemonic <code>OIO</code> ("Official invalid opcode") for the <code>0F FF</code> opcode. </li> <li id="cite_note-149"><a href="#cite_ref-149">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253667-064.pdf">Software Developer's Manual, vol 2B</a>, order no. 253667-064, oct 2017 – lists <code>UD0</code> (with ModR/M byte) on page 4-683. </li> <li id="cite_note-151"><a href="#cite_ref-151">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/AMD/K5/18524c.pdf">AMD-K5 Processor Technical Reference Manual</a>, Nov 1996, order no. 18524C/0, section 3.3.7, page 90 – reserves the <code>0F FF</code> opcode without assigning it a mnemonic. </li> <li id="cite_note-152"><a href="#cite_ref-152">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/AMD/K6/20695.pdf">AMD-K6 Processor Data Sheet</a>, order no. 20695H/0, March 1998, section 24.2, page 283. </li> <li id="cite_note-155"><a href="#cite_ref-155">^</a> George Dunlap, <a rel="nofollow" class="external text" href="https://xenproject.org/2012/06/13/the-intel-sysret-privilege-escalation/">The Intel SYSRET Privilege Escalation</a>, The Xen Project., 13 june 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190315121519/https://xenproject.org/2012/06/13/the-intel-sysret-privilege-escalation/">Archived</a> on Mar 15, 2019. </li> <li id="cite_note-159"><a href="#cite_ref-159">^</a> Intel, <a rel="nofollow" class="external text" href="http://kib.kiev.ua/x86docs/Intel/AppNote485/241618-039.pdf">AP-485: Intel® Processor Identification and the CPUID Instruction</a>, order no. 241618-039, may 2012, section 5.1.2.5, page 32 </li> <li id="cite_note-160"><a href="#cite_ref-160">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/sysenter-where-are-you/">"SYSENTER, Where Are You?"</a>, 20 Jul 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231129090510/http://www.os2museum.com/wp/sysenter-where-are-you/">Archived</a> on 29 Nov 2023. </li> <li id="cite_note-162"><a href="#cite_ref-162">^</a> AMD, <a rel="nofollow" class="external text" href="https://pdf.datasheetcatalog.com/datasheet/AdvancedMicroDevices/mXvyvs.pdf">Athlon Processor x86 Code Optimization Guide</a>, publication no. 22007, rev K, feb 2002, appendix F, page 284. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170413235648/https://pdf.datasheetcatalog.com/datasheet/AdvancedMicroDevices/mXvyvs.pdf">Archived</a> on 13 Apr 2017. </li> <li id="cite_note-164"><a href="#cite_ref-164">^</a> Transmeta, <a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Transmeta/Crusoe/Crusoe_CPUID_5-7-02.pdf">Processor Recognition</a>, May 7, 2002. </li> <li id="cite_note-166"><a href="#cite_ref-166">^</a> VIA, <a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/VIA/Nehemiah/VIA%20C3%20Nehemiah%20Datasheet%20R113.pdf">VIA C3 Nehemiah Processor Datasheet</a>, rev 1.13, sep 29, 2004, page 17 </li> <li id="cite_note-169"><a href="#cite_ref-169">^</a> CPU-World, <a rel="nofollow" class="external text" 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lists MOVSXD without REX.W as "discouraged" </li> <li id="cite_note-179"><a href="#cite_ref-179">^</a> Anandtech, <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested/6">AMD Zen 3 Ryzen Deep Dive Review</a>, nov 5, 2020, page 6 </li> <li id="cite_note-180"><a href="#cite_ref-180">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFinstlatx642020" class="citation web cs1">@instlatx64 (October 31, 2020). <a rel="nofollow" class="external text" href="https://x.com/instlatx64/status/1322503571288559617">"Saving Private Ryzen: PEXT/PDEP 32/64b replacement functions for #AMD CPUs (BR/#Zen/Zen+/#Zen2) based on @zwegner's zp7"</a> (<a href="/wiki/Tweet_(social_media)" title="Tweet (social media)">Tweet</a>). Retrieved 2023-01-20 – via <a href="/wiki/Twitter" title="Twitter">Twitter</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Saving+Private+Ryzen%3A+PEXT%2FPDEP+32%2F64b+replacement+functions+for+%23AMD+CPUs+%28BR%2F%23Zen%2FZen%2B%2F%23Zen2%29+based+on+%40zwegner%27s+zp7&rft.date=2020-10-31&rft.au=instlatx64&rft_id=https%3A%2F%2Fx.com%2Finstlatx64%2Fstatus%2F1322503571288559617&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-181"><a href="#cite_ref-181">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWegner2020" class="citation web cs1">Wegner, Zach (4 November 2020). <a rel="nofollow" class="external text" href="https://github.com/zwegner/zp7">"zwegner/zp7"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=zwegner%2Fzp7&rft.date=2020-11-04&rft.aulast=Wegner&rft.aufirst=Zach&rft_id=https%3A%2F%2Fgithub.com%2Fzwegner%2Fzp7&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-185"><a href="#cite_ref-185">^</a> Intel, <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/CET/334525-003.pdf">Control-flow Enforcement Technology Specification</a> (v3.0, order no. 334525-003, March 2019) </li> <li id="cite_note-186"><a href="#cite_ref-186">^</a> <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253665-076.pdf">Intel SDM, rev 076, December 2021</a>, volume 1, section 18.3.1 </li> <li id="cite_note-187"><a href="#cite_ref-187">^</a> Binutils mailing list: <a rel="nofollow" class="external text" href="https://sourceware.org/pipermail/binutils/2017-June/098516.html">x86: CET v2.0: Update NOTRACK prefix</a> </li> <li id="cite_note-195"><a href="#cite_ref-195">^</a> AMD, <a rel="nofollow" class="external text" href="https://refspecs.linuxfoundation.org/AMD-extensions.pdf">Extensions to the 3DNow! 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id="cite_note-284"><a href="#cite_ref-284">^</a> Wikichip, <a rel="nofollow" class="external text" href="https://en.wikichip.org/w/index.php?title=x86/clzero&oldid=94738">CLZERO – x86</a> </li> <li id="cite_note-288"><a href="#cite_ref-288">^</a> Intel, <a rel="nofollow" class="external text" href="https://ardent-tool.com/CPU/docs/Intel/IA/243291-002.pdf">Application note AP-578: Software and Hardware Considerations for FPU Exception Handlers for Intel Architecture Processors</a>, order no. 243291-002, February 1997 </li> <li id="cite_note-292"><a href="#cite_ref-292">^</a> Intel, <a rel="nofollow" class="external text" href="https://ardent-tool.com/CPU/docs/Intel/808x/8087/appnotes/AP-113.pdf">Application Note AP-113: Getting Started With The Numeric Data Processor</a>, feb 1981, pages 24-25 </li> <li id="cite_note-293"><a href="#cite_ref-293">^</a> Intel, <a rel="nofollow" class="external text" href="http://www.datasheetcatalog.com/datasheets_pdf/8/0/8/7/8087.shtml">8087 Math Coprocessor</a>, oct 1989, order no. 285385-007, page 3-100, fig 9 </li> <li id="cite_note-294"><a href="#cite_ref-294">^</a> Intel, <a rel="nofollow" class="external text" href="http://www.bitsavers.org/components/intel/_dataSheets/80287_Data_Sheet_Feb83.pdf">80287 80-bit HMOS Numeric Processor Extension</a>, feb 1983, order no. 201920-001, page 14 </li> <li id="cite_note-298"><a href="#cite_ref-298">^</a> Intel, <a rel="nofollow" class="external text" href="https://ardent-tool.com/CPU/docs/Intel/808x/manuals/210201-001.pdf">iAPX86, 88 User's Manual</a>, 1981 (order no. 210201-001), p. 797 </li> <li id="cite_note-i80287-299">^ <a href="#cite_ref-i80287_299-0">a</a> <a href="#cite_ref-i80287_299-1">b</a> Intel <a rel="nofollow" class="external text" href="http://bitsavers.trailing-edge.com/components/intel/80286/210498-005_80286_and_80287_Programmers_Reference_Manual_1987.pdf">80286 and 80287 Programmers Reference Manual</a>, 1987 (order no. 210498-005), p. 485 </li> <li id="cite_note-300"><a href="#cite_ref-300">^</a> Intel <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253669-064.pdf">Software Developer's Manual</a> volume 3B, revision 064, section 22.18.9 </li> <li id="cite_note-301"><a href="#cite_ref-301">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://gcc.gnu.org/bugzilla/show_bug.cgi?id=37179">"GCC Bugzilla – 37179 – GCC emits bad opcode 'ffreep'"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=GCC+Bugzilla+%E2%80%93+37179+%E2%80%93+GCC+emits+bad+opcode+%27ffreep%27&rft_id=https%3A%2F%2Fgcc.gnu.org%2Fbugzilla%2Fshow_bug.cgi%3Fid%3D37179&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-302"><a href="#cite_ref-302">^</a> Michael Steil, <a rel="nofollow" class="external text" href="https://www.pagetable.com/?p=16">FFREEP – the assembly instruction that never existed</a> </li> <li id="cite_note-308"><a href="#cite_ref-308">^</a> Dusko Koncaliev, <a rel="nofollow" class="external text" href="https://www.cs.earlham.edu/~dusko/cs63/fdiv.html">Pentium FDIV Bug</a> </li> <li id="cite_note-325"><a href="#cite_ref-325">^</a> Bruce Dawson, <a rel="nofollow" class="external text" href="https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/">Intel Underestimates Error Bounds by 1.3 quintillion</a> </li> <li id="cite_note-326"><a href="#cite_ref-326">^</a> <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253665-053.pdf">Intel SDM, rev 053</a> and later, describes the exact argument reduction procedure used for <code>FSIN</code>, <code>FCOS</code>, <code>FSINCOS</code> and <code>FPTAN</code> in volume 1, section 8.3.8 </li> <li id="cite_note-332"><a href="#cite_ref-332">^</a> Robert Collins, <a rel="nofollow" class="external text" href="http://www.rcollins.org/secrets/opcodes/AAM.html">Undocumented OpCodes: AAM</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010221212212/http://www.rcollins.org/secrets/opcodes/AAM.html">Archived on 21 Feb 2001</a> </li> <li id="cite_note-333"><a href="#cite_ref-333">^</a> Retrocomputing StackExchange, <a rel="nofollow" class="external text" href="https://retrocomputing.stackexchange.com/questions/12004/0f1h-opcode-prefix-on-i80286">0F1h opcode-prefix on i80286</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230413012532/https://retrocomputing.stackexchange.com/questions/12004/0f1h-opcode-prefix-on-i80286">Archived</a> on 13 Apr 2023. </li> <li id="cite_note-test_and_sal-334">^ <a href="#cite_ref-test_and_sal_334-0">a</a> <a href="#cite_ref-test_and_sal_334-1">b</a> Frank van Gilluwe, "The Undocumented PC – Second Edition", p. 93-95 </li> <li id="cite_note-335"><a href="#cite_ref-335">^</a> Michal Necasek, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/intel-486-errata/">Intel 486 Errata?</a>, 6 Dec 2015. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231129063912/http://www.os2museum.com/wp/intel-486-errata/">Archived</a> on 29 Nov 2023. </li> <li id="cite_note-hummel-336"><a href="#cite_ref-hummel_336-0">^</a> Robert Hummel, "PC Magazine Programmer's Technical Reference" (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-56276-016-5" title="Special:BookSources/1-56276-016-5">1-56276-016-5</a>) p.728 </li> <li id="cite_note-337"><a href="#cite_ref-337">^</a> Raúl Gutiérrez Sanz, <a rel="nofollow" class="external text" href="http://www.os2museum.com/wp/undocumented-8086-opcodes-part-i/">Undocumented 8086 Opcodes, Part I</a>, 27 Dec 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231129062730/http://www.os2museum.com/wp/undocumented-8086-opcodes-part-i/">Archived</a> on 29 Nov 2023. </li> <li id="cite_note-asm-opcode-82h-338">^ <a href="#cite_ref-asm-opcode-82h_338-0">a</a> <a href="#cite_ref-asm-opcode-82h_338-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://computer-programming-forum.com/46-asm/143edbd28ae1a091.htm">"Asm, opcode 82h"</a>. 24 Dec 1998. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230414000947/http://computer-programming-forum.com/46-asm/143edbd28ae1a091.htm">Archived</a> from the original on 14 Apr 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Asm%2C+opcode+82h&rft.date=1998-12-24&rft_id=http%3A%2F%2Fcomputer-programming-forum.com%2F46-asm%2F143edbd28ae1a091.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-FOOTNOTEIntel_Corporation20223698-339"><a href="#cite_ref-FOOTNOTEIntel_Corporation20223698_339-0">^</a> <a href="#CITEREFIntel_Corporation2022">Intel Corporation 2022</a>, p. 3698. </li> <li id="cite_note-340"><a href="#cite_ref-340">^</a> Intel, <a rel="nofollow" class="external text" href="http://bitsavers.org/components/intel/8086/9800722-03_The_8086_Family_Users_Manual_Oct79.pdf">The 8086 Family User's Manual, October 1979</a>, opcodes omitted on pages 4-25 and 4-31 </li> <li id="cite_note-341"><a href="#cite_ref-341">^</a> Retrocomputing StackExchange, <a rel="nofollow" class="external text" href="https://retrocomputing.stackexchange.com/questions/20031/undocumented-instructions-in-x86-cpu-prior-to-80386">Undocumented instructions in x86 CPU prior to 80386?</a>, 4 Jun 2021. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230718101651/https://retrocomputing.stackexchange.com/questions/20031/undocumented-instructions-in-x86-cpu-prior-to-80386">Archived</a> on 18 Jul 2023. </li> <li id="cite_note-342"><a href="#cite_ref-342">^</a> Daniel B. Sedory, <a rel="nofollow" class="external text" href="https://thestarman.pcministry.com/asm/mbr/STDMBR.htm#REP">An Examination of the Standard MBR</a>, 2000. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231006232036/https://thestarman.pcministry.com/asm/mbr/STDMBR.htm#REP">Archived</a> on 6 Oct 2023. </li> <li id="cite_note-343"><a href="#cite_ref-343">^</a> AMD, <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/25112.PDF">Software Optimization Guide for AMD64 Processors</a> (publication 25112, revision 3.06, sep 2005), section 6.2, p.128 </li> <li id="cite_note-344"><a href="#cite_ref-344">^</a> GCC bugzilla, <a rel="nofollow" class="external text" href="https://gcc.gnu.org/bugzilla/show_bug.cgi?id=48227">Bug 48227 – "rep ret" generated for -march=core2</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230409143117/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=48227">Archived</a> on 9 Apr 2023. </li> <li id="cite_note-345"><a href="#cite_ref-345">^</a> Raymond Chen, <a rel="nofollow" class="external text" href="https://devblogs.microsoft.com/oldnewthing/20110112-00/?p=11773">My, what strange NOPs you have!</a>, 12 Jan 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230520034608/https://devblogs.microsoft.com/oldnewthing/20110112-00/?p=11773">Archived</a> on 20 May 2023. </li> <li id="cite_note-346"><a href="#cite_ref-346">^</a> Jeff Parsons, <a rel="nofollow" class="external text" href="https://www.pcjs.org/documents/manuals/intel/80386/#b1-errata">Intel 80386 CPU information</a> (B1 errata section, item #7). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231113171132/https://www.pcjs.org/documents/manuals/intel/80386/#b1-errata">Archived</a> on 13 Nov 2023. </li> <li id="cite_note-347"><a href="#cite_ref-347">^</a> Intel <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253667-018.pdf">Software Developers Manual, volume 2B</a> (Jan 2006, order no 235667-018, does not have long NOP) </li> <li id="cite_note-348"><a href="#cite_ref-348">^</a> Intel <a rel="nofollow" class="external text" href="https://kib.kiev.ua/x86docs/Intel/SDMs/253667-019.pdf">Software Developers Manual, volume 2B</a> (March 2006, order no 235667-019, has long NOP) </li> <li id="cite_note-349"><a href="#cite_ref-349">^</a> Agner Fog, <a rel="nofollow" class="external text" href="https://www.agner.org/optimize/instruction_tables.pdf">Instruction Tables</a>, AMD K7 section. </li> <li id="cite_note-350"><a href="#cite_ref-350">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230730214505/https://bugzilla.redhat.com/show_bug.cgi?id=579838#c46">"579838 – glibc not compatible with AMD Geode LX"</a>. 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Ragestorm. 17 Sep 2005. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220409071159/https://www.ragestorm.net/tutorial?id=27">Archived</a> from the original on 9 April 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Ragestorm&rft.atitle=Tutorial+%E2%80%93+Calling+Win32+from+DOS&rft.date=2005-09-17&rft_id=https%3A%2F%2Fwww.ragestorm.net%2Ftutorial%3Fid%3D27&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-359"><a href="#cite_ref-359">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20111108011230/https://sta.c64.org/blog/dosvddaccess.html">"Accessing Windows device drivers from DOS programs"</a>. Archived from <a rel="nofollow" class="external text" href="https://sta.c64.org/blog/dosvddaccess.html">the original</a> on 8 Nov 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Accessing+Windows+device+drivers+from+DOS+programs&rft_id=https%3A%2F%2Fsta.c64.org%2Fblog%2Fdosvddaccess.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-rep_imul-360">^ <a href="#cite_ref-rep_imul_360-0">a</a> <a href="#cite_ref-rep_imul_360-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.reenigne.org/blog/8086-microcode-disassembled/">"8086 microcode disassembled"</a>. Reenigne blog. 2020-09-03. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231208191745/https://www.reenigne.org/blog/8086-microcode-disassembled/">Archived</a> from the original on 8 Dec 2023. Retrieved 2022-07-26. <q>Using the REP or REPNE prefix with a MUL or IMUL instruction negates the product. Using the REP or REPNE prefix with an IDIV instruction negates the quotient.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Reenigne+blog&rft.atitle=8086+microcode+disassembled&rft.date=2020-09-03&rft_id=https%3A%2F%2Fwww.reenigne.org%2Fblog%2F8086-microcode-disassembled%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-361"><a href="#cite_ref-361">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20041106070621/http://www.sandpile.org/post/msgs/20004129.htm">"Re: Undocumented opcodes (HINT_NOP)"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.sandpile.org/post/msgs/20004129.htm">the original</a> on 2004-11-06. Retrieved 2010-11-07.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+Undocumented+opcodes+%28HINT_NOP%29&rft_id=http%3A%2F%2Fwww.sandpile.org%2Fpost%2Fmsgs%2F20004129.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-362"><a href="#cite_ref-362">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030626044017/http://www.sandpile.org/post/msgs/20003986.htm">"Re: Also some undocumented 0Fh opcodes"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.sandpile.org/post/msgs/20003986.htm">the original</a> on 2003-06-26. Retrieved 2010-11-07.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+Also+some+undocumented+0Fh+opcodes&rft_id=http%3A%2F%2Fwww.sandpile.org%2Fpost%2Fmsgs%2F20003986.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-363"><a href="#cite_ref-363">^</a> Intel's <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220424231054/https://github.com/Intel-SCC/RCCE/blob/master/src/RCCE_admin.c#L87">RCCE library</a> for the SCC used opcode <code>0F 0A</code> for SCC's message invalidation instruction. </li> <li id="cite_note-364"><a href="#cite_ref-364">^</a> Intel Labs, <a rel="nofollow" class="external text" href="https://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-single-chip-cloud-architecture-brief.pdf">SCC External Architecture Specification (EAS), Revision 0.94</a>, p.29. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220522083931/https://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-single-chip-cloud-architecture-brief.pdf">Archived</a> on May 22, 2022. </li> <li id="cite_note-365"><a href="#cite_ref-365">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://raw.githubusercontent.com/chip-red-pill/udbgInstr/main/paper/undocumented_x86_insts_for_uarch_control.pdf">"Undocumented x86 instructions to control the CPU at the microarchitecture level in modern Intel processors"</a> (PDF). 9 July 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Undocumented+x86+instructions+to+control+the+CPU+at+the+microarchitecture+level+in+modern+Intel+processors&rft.date=2021-07-09&rft_id=https%3A%2F%2Fraw.githubusercontent.com%2Fchip-red-pill%2FudbgInstr%2Fmain%2Fpaper%2Fundocumented_x86_insts_for_uarch_control.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-366"><a href="#cite_ref-366">^</a> Robert R. Collins, <a rel="nofollow" class="external text" href="http://www.rcollins.org/secrets/opcodes/UMOV.html">Undocumented OpCodes: UMOV</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010221221425/http://www.rcollins.org/secrets/opcodes/UMOV.html">Archived</a> on Feb 21, 2001. </li> <li id="cite_note-367"><a href="#cite_ref-367">^</a> Herbert Oppmann, <a rel="nofollow" class="external text" href="https://www.memotech.franken.de/NexGen/Opcode0F55.html">NXOP (Opcode 0Fh 55h)</a> </li> <li id="cite_note-368"><a href="#cite_ref-368">^</a> Herbert Oppmann, <a rel="nofollow" class="external text" href="https://www.memotech.franken.de/NexGen/Source/index.html">NexGen Nx586 Hypercode Source</a>, see COMMON.INC. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230409144632/https://www.memotech.franken.de/NexGen/Source/index.html">Archived</a> on 9 Apr 2023. </li> <li id="cite_note-369"><a href="#cite_ref-369">^</a> Herbert Oppmann, <a rel="nofollow" class="external text" href="https://www.memotech.franken.de/NexGen/Bios.html">Inside the NexGen Nx586 System BIOS</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231229134905/https://www.memotech.franken.de/NexGen/Bios.html">Archived</a> on 29 Dec 2023. </li> <li id="cite_note-370"><a href="#cite_ref-370">^</a> Intel, <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/secure-coding/xucode-implementing-complex-instruction-flows.html">XuCode: An Innovative Technology for Implementing Complex Instruction Flows</a>, May 6, 2021. <a rel="nofollow" class="external text" href="https://archive.today/20220719155812/https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/secure-coding/xucode-implementing-complex-instruction-flows.html">Archived</a> on Jul 19, 2022. </li> <li id="cite_note-371"><a href="#cite_ref-371">^</a> Grzegorz Mazur, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20000121143428/http://x86.ddj.com/articles/3dnow/amd_3dnow.htm">AMD 3DNow! undocumented instructions</a> </li> <li id="cite_note-mazur_3dnow-372">^ <a href="#cite_ref-mazur_3dnow_372-0">a</a> <a href="#cite_ref-mazur_3dnow_372-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030130030723/http://grafi.ii.pw.edu.pl/gbm/x86/3dundoc.html">"Undocumented 3DNow! Instructions"</a>. grafi.ii.pw.edu.pl. Archived from <a rel="nofollow" class="external text" href="http://grafi.ii.pw.edu.pl/gbm/x86/3dundoc.html">the original</a> on 30 January 2003. Retrieved 22 February 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=grafi.ii.pw.edu.pl&rft.atitle=Undocumented+3DNow%21+Instructions&rft_id=http%3A%2F%2Fgrafi.ii.pw.edu.pl%2Fgbm%2Fx86%2F3dundoc.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-potemkin-373"><a href="#cite_ref-potemkin_373-0">^</a> <a rel="nofollow" class="external text" href="http://phg.chat.ru/opcode.txt">Potemkin's Hacker Group's OPCODE.LST, v4.51</a>, 15 Oct 1999. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20010521193749/http://phg.chat.ru/opcode.txt">Archived</a> on 21 May 2001. </li> <li id="cite_note-374"><a href="#cite_ref-374">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://x86.fr/uca-cpu-analysis-prototype-umc-green-cpu-u5s-super33">"[UCA CPU Analysis] Prototype UMC Green CPU U5S-SUPER33"</a>. 25 May 2020. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230609122255/https://x86.fr/uca-cpu-analysis-prototype-umc-green-cpu-u5s-super33/">Archived</a> from the original on 9 Jun 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%26%2391%3BUCA+CPU+Analysis%26%2393%3B+Prototype+UMC+Green+CPU+U5S-SUPER33&rft.date=2020-05-25&rft_id=https%3A%2F%2Fx86.fr%2Fuca-cpu-analysis-prototype-umc-green-cpu-u5s-super33&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-375"><a href="#cite_ref-375">^</a> Agner Fog, <a rel="nofollow" class="external text" href="https://www.agner.org/optimize/microarchitecture.pdf">The Microarchitecture of Intel, AMD and VIA CPUs</a>, section 3.4 "Branch Prediction in P4 and P4E". <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240107010216/https://www.agner.org/optimize/microarchitecture.pdf">Archived</a> on 7 Jan 2024. </li> <li id="cite_note-376"><a href="#cite_ref-376">^</a> Reddit /r/Amd discussion thread: <a rel="nofollow" class="external text" href="https://www.reddit.com/r/Amd/comments/68s4bj/ryzen_has_undocumented_support_for_fma4/dh0y353/">Ryzen has undocumented support for FMA4</a> </li> <li id="cite_note-sandsifter-377">^ <a href="#cite_ref-sandsifter_377-0">a</a> <a href="#cite_ref-sandsifter_377-1">b</a> Christopher Domas, <a rel="nofollow" class="external text" href="https://raw.githubusercontent.com/xoreaxeaxeax/sandsifter/dff63246fed84d90118441b8ba5b5d3bdd094427/references/domas_breaking_the_x86_isa_wp.pdf">Breaking the x86 ISA</a>, 27 July 2017. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231227000052/https://raw.githubusercontent.com/xoreaxeaxeax/sandsifter/dff63246fed84d90118441b8ba5b5d3bdd094427/references/domas_breaking_the_x86_isa_wp.pdf">Archived</a> on 27 Dec 2023. </li> <li id="cite_note-uisfuzz-378">^ <a href="#cite_ref-uisfuzz_378-0">a</a> <a href="#cite_ref-uisfuzz_378-1">b</a> Xixing Li et al, <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/abstract/document/8863327">UISFuzz: An Efficient Fuzzing Method for CPU Undocumented Instruction Searching</a>, 9 Oct 2019. <a rel="nofollow" class="external text" href="https://archive.today/20231227000943/https://ieeexplore.ieee.org/document/8863327">Archived</a> on 27 Dec 2023. </li> <li id="cite_note-379"><a href="#cite_ref-379">^</a> Microprocessor Report, <a rel="nofollow" class="external text" href="http://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/110301.PDF">MediaGX Targets Low-Cost PCs</a> (vol 11, no. 3, mar 10, 1997). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220606231124/https://www.cecs.uci.edu/~papers/mpr/MPR/ARTICLES/110301.PDF">Archived</a> on 6 Jun 2022. </li> <li id="cite_note-380"><a href="#cite_ref-380">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/openssl/openssl/blob/1aa89a7a3afb053d0c0b7fad8d3ea1b0a5447289/engines/asm/e_padlock-x86.pl#L597">"Welcome to the OpenSSL Project"</a>. <a href="/wiki/GitHub" title="GitHub">GitHub</a>. 21 April 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220104214039/https://github.com/openssl/openssl/blob/1aa89a7a3afb053d0c0b7fad8d3ea1b0a5447289/engines/asm/e_padlock-x86.pl#L597">Archived</a> from the original on 4 Jan 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=Welcome+to+the+OpenSSL+Project&rft.date=2022-04-21&rft_id=https%3A%2F%2Fgithub.com%2Fopenssl%2Fopenssl%2Fblob%2F1aa89a7a3afb053d0c0b7fad8d3ea1b0a5447289%2Fengines%2Fasm%2Fe_padlock-x86.pl%23L597&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"> </li> <li id="cite_note-381"><a href="#cite_ref-381">^</a> LKML, <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/20230802110741.4077-1-TonyWWang-oc@zhaoxin.com/">(PATCH) crypto: Zhaoxin: Hardware Engine Driver for SHA1/256/384/512</a>, 2 Aug 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240117024338/https://lore.kernel.org/lkml/20230802110741.4077-1-TonyWWang-oc@zhaoxin.com/">Archived</a> on 17 Jan 2024. </li> <li id="cite_note-382"><a href="#cite_ref-382">^</a> Kary Jin, <a rel="nofollow" class="external text" href="https://marc.info/?l=openssl-dev&m=130767391615291&w=2">PATCH: Update PadLock engine for VIA C7 and Nano CPUs</a>, openssl-dev mailing list, 10 Jun 2011. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220211130841/https://marc.info/?l=openssl-dev&m=130767391615291&w=2">Archived</a> on 11 Feb 2022. </li> <li id="cite_note-openeuler_zx_cpuid-383">^ <a href="#cite_ref-openeuler_zx_cpuid_383-0">a</a> <a href="#cite_ref-openeuler_zx_cpuid_383-1">b</a> OpenEuler mailing list, <a rel="nofollow" class="external text" href="https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/thread/W6GXBRRO6OKNHVJ3WDDUXSLQGI2GFU4X/">PATCH kernel-4.19 v2 5/6 : x86/cpufeatures: Add Zhaoxin feature bits</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220409071314/https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/thread/W6GXBRRO6OKNHVJ3WDDUXSLQGI2GFU4X/">Archived</a> on 9 Apr 2022. </li> <li id="cite_note-384"><a href="#cite_ref-384">^</a> USPTO/Zhaoxin, <a rel="nofollow" class="external text" href="https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20230066718">Patent application US2023/006718: Processor with a hash cryptographic algorithm and data processing thereof</a>, pages 13 and 45, Mar 2, 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230912063311/https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/20230066718">Archived</a> on Sep 12, 2023. </li> <li id="cite_note-385"><a href="#cite_ref-385">^</a> LKML, <a rel="nofollow" class="external text" href="https://lore.kernel.org/lkml/20231109094744.545887-1-LeoLiu-oc@zhaoxin.com/t/#u">(PATCH) crypto: x86/sm2 -add Zhaoxin SM2 algorithm implementation</a>, 11 Nov 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240117023414/https://lore.kernel.org/lkml/20231109094744.545887-1-LeoLiu-oc@zhaoxin.com/t/#u">Archived</a> on 17 Jan 2024. </li> <li id="cite_note-zx6000g_cpuid-386">^ <a href="#cite_ref-zx6000g_cpuid_386-0">a</a> <a href="#cite_ref-zx6000g_cpuid_386-1">b</a> InstLatx64, <a rel="nofollow" class="external text" href="http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00307B2_KX6000_01_CPUID.txt">CPUID dump for Zhaoxin KaiXian KX-6000G</a> – has the SM2 and xmodx feature bits set (<a href="/wiki/CPUID" title="CPUID">CPUID</a> leaf C0000001:EDX:bits 0 and 29). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230725214628/http://users.atw.hu/instlatx64/CentaurHauls/CentaurHauls00307B2_KX6000_01_CPUID.txt">Archived</a> on Jul 25, 2023. </li> <li id="cite_note-387"><a href="#cite_ref-387">^</a> OpenEuler kernel <a rel="nofollow" class="external text" href="https://gitee.com/openeuler/kernel/pulls/2602/files">pull request 2602: x86/delay: add support for Zhaoxin ZXPAUSE instruction</a>. Gitee. 26 Oct 2023. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240122224925/https://gitee.com/openeuler/kernel/pulls/2602/files">Archived</a> on 22 Jan 2024. </li> <li id="cite_note-388"><a href="#cite_ref-388">^</a> <a rel="nofollow" class="external text" href="https://github.com/intelxed/xed/blob/ef19f00de14a9c2c253c1c9b1119e1617280e3f2/datafiles/xed-isa.txt#L916">ISA datafile for Intel XED</a> (April 17, 2022), lines 916-944 </li> <li id="cite_note-389"><a href="#cite_ref-389">^</a> <a rel="nofollow" class="external text" href="https://www.ardent-tool.com/CPU/docs/Cyrix/6x86/94175.pdf">Cyrix 6x86 processor data book</a>, page 6-34 </li> <li id="cite_note-390"><a href="#cite_ref-390">^</a> <a rel="nofollow" class="external text" href="https://www.amd.com/system/files/TechDocs/33234H_LX_databook.pdf">AMD Geode LX Processors Data Book</a>, publication 33234H, p.670 </li> </ol></div></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIntel_Corporation2022" class="citation web cs1">Intel Corporation (April 2022). <a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/671200">"Intel 64 and IA-32 Architectures Software Developer's Manual, Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4"</a>. Intel. Retrieved 21 June 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+64+and+IA-32+Architectures+Software+Developer%27s+Manual%2C+Combined+Volumes%3A+1%2C+2A%2C+2B%2C+2C%2C+2D%2C+3A%2C+3B%2C+3C%2C+3D+and+4&rft.date=2022-04&rft.au=Intel+Corporation&rft_id=https%3A%2F%2Fcdrdv2.intel.com%2Fv1%2Fdl%2FgetContent%2F671200&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+instruction+listings" class="Z3988"></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=X86_instruction_listings&action=edit&section=31" title="Edit section: External links">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output 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class="side-box-text plainlist">The Wikibook <a href="https://en.wikibooks.org/wiki/x86_Assembly" class="extiw" title="wikibooks:x86 Assembly">x86 Assembly</a> has a page on the topic of: <a href="https://en.wikibooks.org/wiki/x86_Assembly/X86_Instructions" class="extiw" title="wikibooks:x86 Assembly/X86 Instructions">X86 Instructions</a></div></div> </div> <ul><li><a rel="nofollow" class="external text" href="https://software.intel.com/en-us/articles/intel-sdm">Free IA-32 and x86-64 documentation</a>, provided by Intel</li> <li><a rel="nofollow" class="external text" href="https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf">AMD64 Architecture Programmer's Manual, Volumes 1-5</a>, provided by AMD</li> <li><a rel="nofollow" class="external text" href="http://ref.x86asm.net/">x86 Opcode and Instruction Reference</a></li> <li><a rel="nofollow" class="external text" href="https://www.felixcloutier.com/x86/index.html">x86 and amd64 instruction reference</a></li> <li><a rel="nofollow" class="external text" href="https://www.agner.org/optimize/instruction_tables.pdf">Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs</a></li> <li><a rel="nofollow" class="external text" href="https://www.nasm.us/doc/nasmdocf.html">Netwide Assembler Instruction List</a> (from <a href="/wiki/Netwide_Assembler" title="Netwide Assembler">Netwide Assembler</a>)</li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="x86_assembly_topics" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:X86_assembly_topics" title="Template:X86 assembly topics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:X86_assembly_topics" title="Template talk:X86 assembly topics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:X86_assembly_topics" title="Special:EditPage/Template:X86 assembly topics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="x86_assembly_topics" style="font-size:114%;margin:0 4em">x86 assembly topics</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Topics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Assembly_language" title="Assembly language">Assembly language</a></li> <li><a href="/wiki/Comparison_of_assemblers" title="Comparison of assemblers">Comparison of assemblers</a></li> <li><a href="/wiki/Disassembler" title="Disassembler">Disassembler</a></li> <li><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Instruction set</a></li> <li><a href="/wiki/Low-level_programming_language" title="Low-level programming language">Low-level programming language</a></li> <li><a href="/wiki/Machine_code" title="Machine code">Machine code</a></li> <li><a href="/wiki/Microassembler" title="Microassembler">Microassembler</a></li> <li><a href="/wiki/X86_assembly_language" title="X86 assembly language">x86 assembly language</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Comparison_of_assemblers#x86_assemblers" title="Comparison of assemblers">Assemblers</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/A86_(software)" title="A86 (software)">A86/A386</a></li> <li><a href="/wiki/FASM" title="FASM">Flat Assembler</a> (FASM)</li> <li><a href="/wiki/GNU_Assembler" title="GNU Assembler">GNU Assembler</a> (GAS)</li> <li><a href="/wiki/High_Level_Assembly" title="High Level Assembly">High Level Assembly</a> (HLA)</li> <li><a href="/wiki/Microsoft_Macro_Assembler" title="Microsoft Macro Assembler">Microsoft Macro Assembler</a> (MASM)</li> <li><a href="/wiki/Netwide_Assembler" title="Netwide Assembler">Netwide Assembler</a> (NASM)</li> <li><a href="/wiki/Turbo_Assembler" title="Turbo Assembler">Turbo Assembler</a> (TASM)</li> <li><a href="/wiki/Open_Watcom_Assembler" title="Open Watcom Assembler">Open Watcom Assembler</a> (WASM)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Programming issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Call_stack" title="Call stack">Call stack</a></li> <li><a href="/wiki/FLAGS_register" title="FLAGS register">Flags</a> <ul><li><a href="/wiki/Carry_flag" title="Carry flag">Carry flag</a></li> <li><a href="/wiki/Direction_flag" title="Direction flag">Direction flag</a></li> <li><a href="/wiki/Interrupt_flag" title="Interrupt flag">Interrupt flag</a></li> <li><a href="/wiki/Overflow_flag" title="Overflow flag">Overflow flag</a></li> <li><a href="/wiki/Zero_flag" title="Zero flag">Zero flag</a></li></ul></li> <li><a href="/wiki/Memory_address" title="Memory address">Memory address</a></li> <li><a href="/wiki/Opcode" title="Opcode">Opcode</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li> <li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/X86_calling_conventions" title="X86 calling conventions">Calling conventions</a></li> <li><a class="mw-selflink selflink">Instruction listings</a></li> <li><a href="/wiki/X86#x86_registers" title="X86">Registers</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=X86_instruction_listings&oldid=1257873806">https://en.wikipedia.org/w/index.php?title=X86_instruction_listings&oldid=1257873806</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:X86_instructions" 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