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Search results for: FinFET

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method="get" action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="FinFET"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 8</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: FinFET</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">8</span> SOI-Multi-FinFET: Impact of Fins Number Multiplicity on Corner Effect</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.N.%20Moulay%20Khatir">A.N. Moulay Khatir</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Guen-Bouazza"> A. Guen-Bouazza</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Bouazza"> B. Bouazza</a> </p> <p class="card-text"><strong>Abstract:</strong></p> SOI-Multifin-FET shows excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency. In this work, we analyzed this combination by a three-dimensional numerical device simulator to investigate the influence of fins number on corner effect by analyzing its electrical characteristics and potential distribution in the oxide and the silicon in the section perpendicular to the flow of the current for SOI-single-fin FET, three-fin and five-fin, and we provide a comparison with a Trigate SOI Multi-FinFET structure. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SOI" title="SOI">SOI</a>, <a href="https://publications.waset.org/abstracts/search?q=FinFET" title=" FinFET"> FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=corner%20effect" title=" corner effect"> corner effect</a>, <a href="https://publications.waset.org/abstracts/search?q=dual-gate" title=" dual-gate"> dual-gate</a>, <a href="https://publications.waset.org/abstracts/search?q=tri-gate" title=" tri-gate"> tri-gate</a>, <a href="https://publications.waset.org/abstracts/search?q=Multi-Fin%20FET" title=" Multi-Fin FET"> Multi-Fin FET</a> </p> <a href="https://publications.waset.org/abstracts/7930/soi-multi-finfet-impact-of-fins-number-multiplicity-on-corner-effect" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7930.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">475</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7</span> Performance Improvement of SOI-Tri Gate FinFET Transistor Using High-K Dielectric with Metal Gate </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Fatima%20Zohra%20Rahou">Fatima Zohra Rahou</a>, <a href="https://publications.waset.org/abstracts/search?q=A.Guen%20Bouazza"> A.Guen Bouazza</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Bouazza"> B. Bouazza</a> </p> <p class="card-text"><strong>Abstract:</strong></p> SOI TRI GATE FinFET transistors have emerged as novel devices due to its simple architecture and better performance: better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. As the oxide thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the SiO2 gate oxide with a high-魏 material allows increased gate capacitance without the associated leakage effects. In this paper, SOI TRI-GATE FinFET structure with use of high K dielectric materials (HfO2) and SiO2 dielectric are simulated using the 3-D device simulator Devedit and Atlas of TCAD Silvaco. The simulated results exhibits significant improvements in the performances of SOI TRI GATE FinFET with gate oxide HfO2 compared with conventional gate oxide SiO2 for the same structure. SOI TRI-GATE FinFET structure with the use of high K materials (HfO2) in gate oxide results into the increase in saturation current, threshold voltage, on-state current and Ion/Ioff ratio while off-state current, subthreshold slope and DIBL effect are decreased. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=technology%20SOI" title="technology SOI">technology SOI</a>, <a href="https://publications.waset.org/abstracts/search?q=short-channel%20effects%20%28SCEs%29" title=" short-channel effects (SCEs)"> short-channel effects (SCEs)</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-gate%20SOI%20MOSFET" title=" multi-gate SOI MOSFET"> multi-gate SOI MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=SOI-TRI%20Gate%20FinFET" title=" SOI-TRI Gate FinFET"> SOI-TRI Gate FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=high-K%20dielectric" title=" high-K dielectric"> high-K dielectric</a>, <a href="https://publications.waset.org/abstracts/search?q=Silvaco%20software" title=" Silvaco software"> Silvaco software</a> </p> <a href="https://publications.waset.org/abstracts/31441/performance-improvement-of-soi-tri-gate-finfet-transistor-using-high-k-dielectric-with-metal-gate" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/31441.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">347</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">6</span> Assessment of Highly Sensitive Dielectric Modulated GaN-FinFET for Label-Free Biosensing Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ajay%20Kumar">Ajay Kumar</a>, <a href="https://publications.waset.org/abstracts/search?q=Neha%20Gupta"> Neha Gupta</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This work presents the sensitivity assessment of Gallium Nitride (GaN) material-based FinFET by dielectric modulation in the nanocavity gap for label-free biosensing applications. The significant deflection is observed in the electrical characteristics such as drain current (ID), transconductance (gm), surface potential, energy band profile, electric field, sub-threshold slope (SS), and threshold voltage (Vth) in the presence of biomolecules owing to GaN material. Further, the device sensitivity is evaluated to identify the effectiveness of the proposed biosensor and its capability to detect the biomolecules with high precision or accuracy. Higher sensitivity is observed for Gelatin (k=12) in terms of on-current (SION), threshold voltage (SVth), and switching ratio (SSR) by 104.88%, 82.12%, and 119.73%, respectively. This work is performed using a powerful tool 3D Sentaurus TCAD using a well-calibrated structure. All the results pave the way for GaN-FinFET as a viable candidate for label-free dielectric modulated biosensor applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=biosensor" title="biosensor">biosensor</a>, <a href="https://publications.waset.org/abstracts/search?q=biomolecules" title=" biomolecules"> biomolecules</a>, <a href="https://publications.waset.org/abstracts/search?q=FinFET" title=" FinFET"> FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=sensitivity" title=" sensitivity"> sensitivity</a> </p> <a href="https://publications.waset.org/abstracts/153336/assessment-of-highly-sensitive-dielectric-modulated-gan-finfet-for-label-free-biosensing-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/153336.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">205</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">5</span> Leakage Current Analysis of FinFET Based 7T SRAM at 32nm Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Chhavi%20Saxena">Chhavi Saxena</a> </p> <p class="card-text"><strong>Abstract:</strong></p> FinFETs can be a replacement for bulk-CMOS transistors in many different designs. Its low leakage/standby power property makes FinFETs a desirable option for memory sub-systems. Memory modules are widely used in most digital and computer systems. Leakage power is very important in memory cells since most memory applications access only one or very few memory rows at a given time. As technology scales down, the importance of leakage current and power analysis for memory design is increasing. In this paper, we discover an option for low power interconnect synthesis at the 32nm node and beyond, using Fin-type Field-Effect Transistors (FinFETs) which are a promising substitute for bulk CMOS at the considered gate lengths. We consider a mechanism for improving FinFETs efficiency, called variable supply voltage schemes. In this paper, we鈥檝e illustrated the design and implementation of FinFET based 4x4 SRAM cell array by means of one bit 7T SRAM. FinFET based 7T SRAM has been designed and analysis have been carried out for leakage current, dynamic power and delay. For the validation of our design approach, the output of FinFET SRAM array have been compared with standard CMOS SRAM and significant improvements are obtained in proposed model. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FinFET" title="FinFET">FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=7T%20SRAM%20cell" title=" 7T SRAM cell"> 7T SRAM cell</a>, <a href="https://publications.waset.org/abstracts/search?q=leakage%20current" title=" leakage current"> leakage current</a>, <a href="https://publications.waset.org/abstracts/search?q=delay" title=" delay "> delay </a> </p> <a href="https://publications.waset.org/abstracts/16196/leakage-current-analysis-of-finfet-based-7t-sram-at-32nm-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/16196.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">455</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">4</span> BOX Effect Sensitivity to Fin Width in SOI-Multi-FinFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.%20N.%20Moulai%20Khatir">A. N. Moulai Khatir</a> </p> <p class="card-text"><strong>Abstract:</strong></p> SOI-Multifin-FETs are placed to be the workhorse of the industry for the coming few generations, and thus, in a few years because their excellent transistor characteristics, ideal sub-threshold swing, low drain induced barrier lowering (DIBL) without pocket implantation, and negligible body bias dependency. The corner effect may also exist in the two lower corners; this effect is called the BOX effect, which can also occur in the direction X-Z. The electric field lines from the source and drain cross the bottom oxide and arrive in the silicon. This effect is also called DIVSB (Drain Induced Virtual Substrate Basing). The potential in the silicon film in particular near the drain is increased by the drain bias. It is similar to DIBL and result in a decrease of the threshold voltage. This work provides an understanding of the limitation of this effect by reducing the fin width for components with increased fin number. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SOI" title="SOI">SOI</a>, <a href="https://publications.waset.org/abstracts/search?q=finFET" title=" finFET"> finFET</a>, <a href="https://publications.waset.org/abstracts/search?q=corner%20effect" title=" corner effect"> corner effect</a>, <a href="https://publications.waset.org/abstracts/search?q=dual-gate" title=" dual-gate"> dual-gate</a>, <a href="https://publications.waset.org/abstracts/search?q=tri-gate" title=" tri-gate"> tri-gate</a>, <a href="https://publications.waset.org/abstracts/search?q=BOX" title=" BOX"> BOX</a>, <a href="https://publications.waset.org/abstracts/search?q=multi-finFET" title=" multi-finFET"> multi-finFET</a> </p> <a href="https://publications.waset.org/abstracts/32683/box-effect-sensitivity-to-fin-width-in-soi-multi-finfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32683.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">496</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">3</span> Performance Analysis of Double Gate FinFET at Sub-10NM Node</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Suruchi%20Saini">Suruchi Saini</a>, <a href="https://publications.waset.org/abstracts/search?q=Hitender%20Kumar%20Tyagi"> Hitender Kumar Tyagi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the rapid progress of the nanotechnology industry, it is becoming increasingly important to have compact semiconductor devices to function and offer the best results at various technology nodes. While performing the scaling of the device, several short-channel effects occur. To minimize these scaling limitations, some device architectures have been developed in the semiconductor industry. FinFET is one of the most promising structures. Also, the double-gate 2D Fin field effect transistor has the benefit of suppressing short channel effects (SCE) and functioning well for less than 14 nm technology nodes. In the present research, the MuGFET simulation tool is used to analyze and explain the electrical behaviour of a double-gate 2D Fin field effect transistor. The drift-diffusion and Poisson equations are solved self-consistently. Various models, such as Fermi-Dirac distribution, bandgap narrowing, carrier scattering, and concentration-dependent mobility models, are used for device simulation. The transfer and output characteristics of the double-gate 2D Fin field effect transistor are determined at 10 nm technology node. The performance parameters are extracted in terms of threshold voltage, trans-conductance, leakage current and current on-off ratio. In this paper, the device performance is analyzed at different structure parameters. The utilization of the Id-Vg curve is a robust technique that holds significant importance in the modeling of transistors, circuit design, optimization of performance, and quality control in electronic devices and integrated circuits for comprehending field-effect transistors. The FinFET structure is optimized to increase the current on-off ratio and transconductance. Through this analysis, the impact of different channel widths, source and drain lengths on the Id-Vg and transconductance is examined. Device performance was affected by the difficulty of maintaining effective gate control over the channel at decreasing feature sizes. For every set of simulations, the device's features are simulated at two different drain voltages, 50 mV and 0.7 V. In low-power and precision applications, the off-state current is a significant factor to consider. Therefore, it is crucial to minimize the off-state current to maximize circuit performance and efficiency. The findings demonstrate that the performance of the current on-off ratio is maximum with the channel width of 3 nm for a gate length of 10 nm, but there is no significant effect of source and drain length on the current on-off ratio. The transconductance value plays a pivotal role in various electronic applications and should be considered carefully. In this research, it is also concluded that the transconductance value of 340 S/m is achieved with the fin width of 3 nm at a gate length of 10 nm and 2380 S/m for the source and drain extension length of 5 nm, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=current%20on-off%20ratio" title="current on-off ratio">current on-off ratio</a>, <a href="https://publications.waset.org/abstracts/search?q=FinFET" title=" FinFET"> FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=short-channel%20effects" title=" short-channel effects"> short-channel effects</a>, <a href="https://publications.waset.org/abstracts/search?q=transconductance" title=" transconductance"> transconductance</a> </p> <a href="https://publications.waset.org/abstracts/172098/performance-analysis-of-double-gate-finfet-at-sub-10nm-node" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/172098.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">61</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">2</span> Impact of Fin Cross Section Shape on Potential Distribution of Nanoscale Trapezoidal FinFETs</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ahmed%20Nassim%20Moulai%20Khatir">Ahmed Nassim Moulai Khatir</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Fin field effect transistors (FinFETs) deliver superior levels of scalability than the classical structure of MOSFETs by offering the elimination of short channel effects. Modern FinFETs are 3D structures that rise above the planar substrate, but some of these structures have inclined surfaces, which results in trapezoidal cross sections instead of rectangular sections usually used. Fin cross section shape of FinFETs results in some device issues, like potential distribution performance. This work analyzes that impact with three-dimensional numeric simulation of several triple-gate FinFETs with various top and bottom widths of fin. Results of the simulation show that the potential distribution and the electrical field in the fin depend on the sidewall inclination angle. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=FinFET" title="FinFET">FinFET</a>, <a href="https://publications.waset.org/abstracts/search?q=cross%20section%20shape" title=" cross section shape"> cross section shape</a>, <a href="https://publications.waset.org/abstracts/search?q=SILVACO" title=" SILVACO"> SILVACO</a>, <a href="https://publications.waset.org/abstracts/search?q=trapezoidal%20FinFETs" title=" trapezoidal FinFETs"> trapezoidal FinFETs</a> </p> <a href="https://publications.waset.org/abstracts/186029/impact-of-fin-cross-section-shape-on-potential-distribution-of-nanoscale-trapezoidal-finfets" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/186029.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">47</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1</span> Low Power CNFET SRAM Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Pejman%20Hosseiniun">Pejman Hosseiniun</a>, <a href="https://publications.waset.org/abstracts/search?q=Rose%20Shayeghi"> Rose Shayeghi</a>, <a href="https://publications.waset.org/abstracts/search?q=Iman%20Rahbari"> Iman Rahbari</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohamad%20Reza%20Kalhor"> Mohamad Reza Kalhor</a> </p> <p class="card-text"><strong>Abstract:</strong></p> CNFET has emerged as an alternative material to silicon for high performance, high stability and low power SRAM design in recent years. SRAM functions as cache memory in computers and many portable devices. In this paper, a new SRAM cell design based on CNFET technology is proposed. The proposed SRAM cell design for CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell鈥檚 is reduced about 48% and the SNM is widened up to 56% compared to the conventional CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=SRAM%20cell" title="SRAM cell">SRAM cell</a>, <a href="https://publications.waset.org/abstracts/search?q=CNFET" title=" CNFET"> CNFET</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=HSPICE" title=" HSPICE "> HSPICE </a> </p> <a href="https://publications.waset.org/abstracts/7468/low-power-cnfet-sram-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7468.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">414</span> </span> </div> </div> </div> </main> <footer> <div id="infolinks" class="pt-3 pb-2"> <div class="container"> <div style="background-color:#f5f5f5;" class="p-3"> <div class="row"> <div class="col-md-2"> <ul class="list-unstyled"> About <li><a href="https://waset.org/page/support">About Us</a></li> <li><a href="https://waset.org/page/support#legal-information">Legal</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/WASET-16th-foundational-anniversary.pdf">WASET celebrates its 16th foundational anniversary</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Account <li><a href="https://waset.org/profile">My Account</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Explore <li><a href="https://waset.org/disciplines">Disciplines</a></li> <li><a href="https://waset.org/conferences">Conferences</a></li> <li><a href="https://waset.org/conference-programs">Conference Program</a></li> <li><a href="https://waset.org/committees">Committees</a></li> <li><a href="https://publications.waset.org">Publications</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Research <li><a href="https://publications.waset.org/abstracts">Abstracts</a></li> <li><a href="https://publications.waset.org">Periodicals</a></li> <li><a href="https://publications.waset.org/archive">Archive</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Open Science <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Science-Philosophy.pdf">Open Science Philosophy</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Science-Award.pdf">Open Science Award</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Society-Open-Science-and-Open-Innovation.pdf">Open Innovation</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Postdoctoral-Fellowship-Award.pdf">Postdoctoral Fellowship Award</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Scholarly-Research-Review.pdf">Scholarly Research Review</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Support <li><a href="https://waset.org/page/support">Support</a></li> <li><a href="https://waset.org/profile/messages/create">Contact Us</a></li> <li><a href="https://waset.org/profile/messages/create">Report Abuse</a></li> </ul> </div> </div> </div> </div> </div> <div class="container text-center"> <hr style="margin-top:0;margin-bottom:.3rem;"> <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank" class="text-muted small">Creative Commons Attribution 4.0 International License</a> <div id="copy" class="mt-2">&copy; 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