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instructions</span> </div> </a> <ul id="toc-Integer_instructions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Other_instructions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Other_instructions"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Other instructions</span> </div> </a> <ul id="toc-Other_instructions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Example" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Example"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Example</span> </div> </a> <ul id="toc-Example-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Later_versions" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Later_versions"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Later versions</span> </div> </a> <ul id="toc-Later_versions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Identifying" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Identifying"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Identifying</span> </div> </a> <ul id="toc-Identifying-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>References</span> 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Available in 24 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-24" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">24 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%AA%D8%B0%D9%81%D9%82_%D8%A7%D8%B3_%D8%A2%D9%8A_%D8%A7%D9%85_%D8%AF%D9%8A_%D8%A7%D9%84%D9%85%D8%B9%D8%B2%D8%B2%D8%A9_(%D8%A7%D8%B3_%D8%A7%D8%B3_%D8%A7%D9%8A)" title="تذفق اس آي ام دي المعززة (اس اس اي) – Arabic" lang="ar" hreflang="ar" data-title="تذفق اس آي ام دي المعززة (اس اس اي)" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/SSE" title="SSE – Bulgarian" lang="bg" hreflang="bg" data-title="SSE" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Catalan" lang="ca" hreflang="ca" data-title="Streaming SIMD Extensions" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Czech" lang="cs" hreflang="cs" data-title="Streaming SIMD Extensions" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – German" lang="de" hreflang="de" data-title="Streaming SIMD Extensions" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/SSE" title="SSE – Spanish" lang="es" hreflang="es" data-title="SSE" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/SSE_(instrukciaro)" title="SSE (instrukciaro) – Esperanto" lang="eo" hreflang="eo" data-title="SSE (instrukciaro)" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – French" lang="fr" hreflang="fr" data-title="Streaming SIMD Extensions" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%8A%A4%ED%8A%B8%EB%A6%AC%EB%B0%8D_SIMD_%ED%99%95%EC%9E%A5" title="스트리밍 SIMD 확장 – Korean" lang="ko" hreflang="ko" data-title="스트리밍 SIMD 확장" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/SSE" title="SSE – Indonesian" lang="id" hreflang="id" data-title="SSE" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Italian" lang="it" hreflang="it" data-title="Streaming SIMD Extensions" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Hungarian" lang="hu" hreflang="hu" data-title="Streaming SIMD Extensions" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/SSE" title="SSE – Dutch" lang="nl" hreflang="nl" data-title="SSE" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%82%B9%E3%83%88%E3%83%AA%E3%83%BC%E3%83%9F%E3%83%B3%E3%82%B0SIMD%E6%8B%A1%E5%BC%B5%E5%91%BD%E4%BB%A4" title="ストリーミングSIMD拡張命令 – Japanese" lang="ja" hreflang="ja" data-title="ストリーミングSIMD拡張命令" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Streaming SIMD Extensions" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Polish" lang="pl" hreflang="pl" data-title="Streaming SIMD Extensions" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Portuguese" lang="pt" hreflang="pt" data-title="Streaming SIMD Extensions" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/SSE" title="SSE – Russian" lang="ru" hreflang="ru" data-title="SSE" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Slovak" lang="sk" hreflang="sk" data-title="Streaming SIMD Extensions" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/SSE" title="SSE – Finnish" lang="fi" hreflang="fi" data-title="SSE" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions – Thai" lang="th" hreflang="th" data-title="Streaming SIMD Extensions" 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class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Computer chip instruction set extension</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-More_citations_needed plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/Streaming_SIMD_Extensions" title="Special:EditPage/Streaming SIMD Extensions">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and removed.<br /><small><span class="plainlinks"><i>Find sources:</i> <a rel="nofollow" class="external text" href="https://www.google.com/search?as_eq=wikipedia&q=%22Streaming+SIMD+Extensions%22">"Streaming SIMD Extensions"</a> – <a rel="nofollow" class="external text" href="https://www.google.com/search?tbm=nws&q=%22Streaming+SIMD+Extensions%22+-wikipedia&tbs=ar:1">news</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?&q=%22Streaming+SIMD+Extensions%22&tbs=bkt:s&tbm=bks">newspapers</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?tbs=bks:1&q=%22Streaming+SIMD+Extensions%22+-wikipedia">books</a> <b>·</b> <a rel="nofollow" class="external text" href="https://scholar.google.com/scholar?q=%22Streaming+SIMD+Extensions%22">scholar</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.jstor.org/action/doBasicSearch?Query=%22Streaming+SIMD+Extensions%22&acc=on&wc=on">JSTOR</a></span></small></span> <span class="date-container"><i>(<span class="date">June 2014</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>In <a href="/wiki/Computing" title="Computing">computing</a>, <b>Streaming SIMD Extensions</b> (<b>SSE</b>) is a single instruction, multiple data (<a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a>) <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> extension to the <a href="/wiki/X86" title="X86">x86</a> architecture, designed by <a href="/wiki/Intel" title="Intel">Intel</a> and introduced in 1999 in its <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a> series of <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) shortly after the appearance of <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">Advanced Micro Devices</a> (AMD's) <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a>. SSE contains 70 new instructions (65 unique mnemonics<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> using 70 encodings), most of which work on <a href="/wiki/Single_precision" class="mw-redirect" title="Single precision">single precision</a> <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> and <a href="/wiki/Graphics_processing" class="mw-redirect" title="Graphics processing">graphics processing</a>. </p><p>Intel's first <a href="/wiki/IA-32" title="IA-32">IA-32</a> SIMD effort was the <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> instruction set. MMX had two main problems: it re-used existing <a href="/wiki/X87" title="X87">x87</a> floating-point registers making the CPUs unable to work on both floating-point and SIMD data at the same time, and it only worked on <a href="/wiki/Integers" class="mw-redirect" title="Integers">integers</a>. SSE floating-point instructions operate on a new independent register set, the XMM registers, and adds a few integer instructions that work on MMX registers. </p><p>SSE was subsequently expanded by Intel to <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> and <a href="/wiki/SSE4" title="SSE4">SSE4</a>. Because it supports floating-point math, it had wider applications than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The time period mentioned near this tag is ambiguous. (November 2017)">when?</span></a></i>]</sup> by using MMX in parallel with SSE operations. </p><p>SSE was originally called <b>Katmai New Instructions</b> (<b>KNI</b>), <a href="/wiki/Katmai_(microprocessor)" class="mw-redirect" title="Katmai (microprocessor)">Katmai</a> being the code name for the first Pentium III core revision. During the Katmai project Intel sought to distinguish it from its earlier product line, particularly its flagship <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>. It was later renamed <b>Internet Streaming SIMD Extensions</b> (<b>ISSE</b><sup id="cite_ref-MPR=1999-03-08_2-0" class="reference"><a href="#cite_note-MPR=1999-03-08-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>), then SSE. </p><p>AMD added a subset of SSE, 19 of them, called new MMX instructions,<sup id="cite_ref-extman_3-0" class="reference"><a href="#cite_note-extman-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and known as several variants and combinations of SSE and MMX, shortly after with the release of the original <a href="/wiki/Athlon" title="Athlon">Athlon</a> in August 1999, see <a href="/wiki/3DNow!#3DNow!_extensions" title="3DNow!">3DNow! extensions</a>. AMD eventually added full support for SSE instructions, starting with its <a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">Athlon XP</a> and <a href="/wiki/Duron" title="Duron">Duron</a> (<a href="/wiki/Duron#Morgan_(Model_7,_180_nm)" title="Duron">Morgan core</a>) processors. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Registers">Registers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=1" title="Edit section: Registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SSE originally added eight new 128-bit registers known as <code>XMM0</code> through <code>XMM7</code>. The <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a> extensions from AMD (originally called <i>x86-64</i>) added a further eight registers <code>XMM8</code> through <code>XMM15</code>, and this extension is duplicated in the <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a> architecture. There is also a new 32-bit control/status register, <code>MXCSR</code>. The registers <code>XMM8</code> through <code>XMM15</code> are accessible only in 64-bit operating mode. </p> <figure class="mw-halign-right" typeof="mw:File"><a href="/wiki/File:XMM_registers.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/5a/XMM_registers.svg/220px-XMM_registers.svg.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/5a/XMM_registers.svg/330px-XMM_registers.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/5a/XMM_registers.svg/440px-XMM_registers.svg.png 2x" data-file-width="1024" data-file-height="1024" /></a><figcaption></figcaption></figure> <p>SSE used only a single data type for XMM registers: </p> <ul><li>four 32-bit <a href="/wiki/Single-precision" class="mw-redirect" title="Single-precision">single-precision</a> floating-point numbers</li></ul> <p><a href="/wiki/SSE2" title="SSE2">SSE2</a> would later expand the usage of the XMM registers to include: </p> <ul><li>two 64-bit <a href="/wiki/Double-precision" class="mw-redirect" title="Double-precision">double-precision</a> floating-point numbers or</li> <li>two 64-bit integers or</li> <li>four 32-bit integers or</li> <li>eight 16-bit short integers or</li> <li>sixteen 8-bit bytes or characters.</li></ul> <p>Because these 128-bit registers are additional machine states that the <a href="/wiki/Operating_system" title="Operating system">operating system</a> must preserve across <a href="/wiki/Context_switch" title="Context switch">task switches</a>, they are disabled by default until the operating system explicitly enables them. This means that the OS must know how to use the <code>FXSAVE</code> and <code>FXRSTOR</code> instructions, which is the extended pair of instructions that can save all <a href="/wiki/X86" title="X86">x86</a> and SSE register states at once. This support was quickly added to all major IA-32 operating systems. </p><p>The first CPU to support SSE, the <a href="/wiki/Pentium_III" title="Pentium III">Pentium III</a>, shared execution resources between SSE and the <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU).<sup id="cite_ref-MPR=1999-03-08_2-1" class="reference"><a href="#cite_note-MPR=1999-03-08-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> While a <a href="/wiki/Compiled" class="mw-redirect" title="Compiled">compiled</a> application can interleave FPU and SSE instructions side-by-side, the Pentium III will not issue an FPU and an SSE instruction in the same <a href="/wiki/Clock_cycle" class="mw-redirect" title="Clock cycle">clock cycle</a>. This limitation reduces the effectiveness of <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipelining</a>, but the separate XMM registers do allow SIMD and scalar floating-point operations to be mixed without the performance hit from explicit MMX/floating-point mode switching. </p> <div class="mw-heading mw-heading2"><h2 id="SSE_instructions">SSE instructions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=2" title="Edit section: SSE instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SSE introduced both <a href="/wiki/Scalar_(computing)" class="mw-redirect" title="Scalar (computing)">scalar</a> and <a href="/wiki/Data_structure_alignment" title="Data structure alignment">packed</a> floating-point instructions. </p> <div class="mw-heading mw-heading3"><h3 id="Floating-point_instructions">Floating-point instructions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=3" title="Edit section: Floating-point instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Memory-to-register/register-to-memory/register-to-register data movement <ul><li>Scalar – <code>MOVSS</code></li> <li>Packed – <code>MOVAPS, MOVUPS, MOVLPS, MOVHPS, MOVLHPS, MOVHLPS, MOVMSKPS</code></li></ul></li> <li>Arithmetic <ul><li>Scalar – <code>ADDSS, SUBSS, MULSS, DIVSS, RCPSS, SQRTSS, MAXSS, MINSS, RSQRTSS</code></li> <li>Packed – <code>ADDPS, SUBPS, MULPS, DIVPS, RCPPS, SQRTPS, MAXPS, MINPS, RSQRTPS</code></li></ul></li> <li><a href="/wiki/Comparison_(computer_programming)" class="mw-redirect" title="Comparison (computer programming)">Compare</a> <ul><li>Scalar – <code>CMPSS, COMISS, UCOMISS</code></li> <li>Packed – <code>CMPPS</code></li></ul></li> <li>Data shuffle and unpacking <ul><li>Packed – <code>SHUFPS, UNPCKHPS, UNPCKLPS</code></li></ul></li> <li><a href="/wiki/Type_conversion" title="Type conversion">Data-type conversion</a> <ul><li>Scalar – <code>CVTSI2SS, CVTSS2SI, CVTTSS2SI</code></li> <li>Packed – <code>CVTPI2PS, CVTPS2PI, CVTTPS2PI</code></li></ul></li> <li><a href="/wiki/Bitwise_operation" title="Bitwise operation">Bitwise</a> logical operations <ul><li>Packed – <code>ANDPS, ORPS, XORPS, ANDNPS</code></li></ul></li></ul> <div class="mw-heading mw-heading3"><h3 id="Integer_instructions">Integer instructions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=4" title="Edit section: Integer instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Arithmetic <ul><li><code>PMULHUW, PSADBW, PAVGB, PAVGW, PMAXUB, PMINUB, PMAXSW, PMINSW</code></li></ul></li> <li>Data movement <ul><li><code>PEXTRW, PINSRW</code></li></ul></li> <li>Other <ul><li><code>PMOVMSKB, PSHUFW</code></li></ul></li></ul> <div class="mw-heading mw-heading3"><h3 id="Other_instructions">Other instructions</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=5" title="Edit section: Other instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><code>MXCSR</code> management <ul><li><code>LDMXCSR, STMXCSR</code></li></ul></li> <li>Cache and Memory management <ul><li><code>MOVNTQ, MOVNTPS, MASKMOVQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE</code></li></ul></li></ul> <div class="mw-heading mw-heading2"><h2 id="Example">Example</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=6" title="Edit section: Example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following simple example demonstrates the advantage of using SSE. Consider an operation like vector addition, which is used very often in computer graphics applications. To add two single precision, four-component vectors together using x86 requires four floating-point addition instructions. </p> <div class="mw-highlight mw-highlight-lang-c mw-content-ltr" dir="ltr"><pre><span></span><span class="w"> </span><span class="n">vec_res</span><span class="p">.</span><span class="n">x</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">v1</span><span class="p">.</span><span class="n">x</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">v2</span><span class="p">.</span><span class="n">x</span><span class="p">;</span> <span class="w"> </span><span class="n">vec_res</span><span class="p">.</span><span class="n">y</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">v1</span><span class="p">.</span><span class="n">y</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">v2</span><span class="p">.</span><span class="n">y</span><span class="p">;</span> <span class="w"> </span><span class="n">vec_res</span><span class="p">.</span><span class="n">z</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">v1</span><span class="p">.</span><span class="n">z</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">v2</span><span class="p">.</span><span class="n">z</span><span class="p">;</span> <span class="w"> </span><span class="n">vec_res</span><span class="p">.</span><span class="n">w</span><span class="w"> </span><span class="o">=</span><span class="w"> </span><span class="n">v1</span><span class="p">.</span><span class="n">w</span><span class="w"> </span><span class="o">+</span><span class="w"> </span><span class="n">v2</span><span class="p">.</span><span class="n">w</span><span class="p">;</span> </pre></div> <p>This corresponds to four x86 FADD instructions in the object code. On the other hand, as the following pseudo-code shows, a single 128-bit 'packed-add' instruction can replace the four scalar addition instructions. </p> <div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre><span></span><span class="w"> </span><span class="nf">movaps</span><span class="w"> </span><span class="nb">xmm0</span><span class="p">,</span><span class="w"> </span><span class="p">[</span><span class="nv">v1</span><span class="p">]</span><span class="w"> </span><span class="c1">;xmm0 = v1.w | v1.z | v1.y | v1.x </span> <span class="w"> </span><span class="nf">addps</span><span class="w"> </span><span class="nb">xmm0</span><span class="p">,</span><span class="w"> </span><span class="p">[</span><span class="nv">v2</span><span class="p">]</span><span class="w"> </span><span class="c1">;xmm0 = v1.w+v2.w | v1.z+v2.z | v1.y+v2.y | v1.x+v2.x</span> <span class="w"> </span><span class="nf">movaps</span><span class="w"> </span><span class="p">[</span><span class="nv">vec_res</span><span class="p">],</span><span class="w"> </span><span class="nb">xmm0</span><span class="w"> </span><span class="c1">;xmm0</span> </pre></div> <div class="mw-heading mw-heading2"><h2 id="Later_versions">Later versions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=7" title="Edit section: Later versions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/SSE2" title="SSE2">SSE2</a>, Willamette New Instructions (WNI), introduced with the <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>, is a major enhancement to SSE. SSE2 adds two major features: <a href="/wiki/Double-precision" class="mw-redirect" title="Double-precision">double-precision</a> (64-bit) floating-point for all SSE operations, and MMX integer operations on 128-bit XMM registers. In the original SSE instruction set, conversion to and from integers placed the integer data in the 64-bit MMX registers. SSE2 enables the programmer to perform SIMD math on any data type (from 8-bit integer to 64-bit float) entirely with the XMM vector-register file, without the need to use the legacy MMX or FPU registers. It offers an <a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">orthogonal set of instructions</a> for dealing with common data types.</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a>, also called Prescott New Instructions (PNI), is an incremental upgrade to SSE2, adding a handful of DSP-oriented mathematics instructions and some process (thread) management instructions. It also allowed addition or multiplication of two numbers that are stored in the same register, which wasn't possible in SSE2 and earlier. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set. AMD's <a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> extension could do the latter too.</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Merom New Instructions (MNI), is an upgrade to SSE3, adding 16 new instructions which include permuting the bytes in a word, multiplying 16-bit fixed-point numbers with correct rounding, and within-word accumulate instructions. SSSE3 is often mistaken for SSE4 as this term was used during the development of the Core <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a>.</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a>, Penryn New Instructions (PNI), is another major enhancement, adding a <a href="/wiki/Dot_product" title="Dot product">dot product</a> instruction, additional integer instructions, a <a href="/wiki/SSE4#POPCNT_and_LZCNT" title="SSE4"><code class="mw-highlight mw-highlight-lang-asm mw-content-ltr" dir="ltr"><span class="nf">popcnt</span></code> instruction</a> (<a href="/wiki/Hamming_weight" title="Hamming weight">Population count</a>: count number of bits set to 1, used extensively e.g. in <a href="/wiki/Cryptography" title="Cryptography">cryptography</a>), and more.</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA4</a> and <a href="/wiki/CVT16_instruction_set" class="mw-redirect" title="CVT16 instruction set">CVT16</a> are new iterations announced by <a href="/wiki/AMD" title="AMD">AMD</a> in August 2007<sup id="cite_ref-:0_4-0" class="reference"><a href="#cite_note-:0-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> and revised in May 2009.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (AVX), Gesher New Instructions (GNI), is an advanced version of SSE announced by Intel featuring a widened data path from 128 bits to 256 bits and 3-operand instructions (up from 2). Intel released processors in early 2011 with AVX support.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a> is an expansion of the AVX instruction set.</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (3.1 and 3.2) are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Identifying">Identifying</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=8" title="Edit section: Identifying"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following programs can be used to determine which, if any, versions of SSE are supported on a system </p> <ul><li>Intel Processor Identification Utility<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/CPU-Z" title="CPU-Z">CPU-Z</a> – CPU, motherboard, and memory identification utility.</li> <li><a href="/wiki/Util-linux" title="Util-linux">lscpu</a> - provided by the util-linux package in most Linux distributions.</li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=9" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/AltiVec" title="AltiVec">AltiVec</a> - equivalent on <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> architecture</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Streaming_SIMD_Extensions&action=edit&section=10" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://cdrdv2.intel.com/v1/dl/getContent/671200">"Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture"</a>. 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href="/wiki/Processor_supplementary_capability" title="Processor supplementary capability">extensions</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a> <ul><li><a href="/wiki/DEC_Alpha#Motion_Video_Instructions_(MVI)" title="DEC Alpha">MVI</a></li></ul></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> <ul><li><a href="/wiki/ARM_architecture_family#Advanced_SIMD_(Neon)" title="ARM architecture family">NEON</a></li> <li><a href="/wiki/AArch64#Scalable_Vector_Extension_(SVE)" title="AArch64">SVE</a></li></ul></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <ul><li><a href="/wiki/MDMX" title="MDMX">MDMX</a></li> <li><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></li> <li><a href="/wiki/Media_Extension_Unit" class="mw-redirect" title="Media Extension Unit">MXU</a></li> <li><a href="/wiki/MIPS_architecture#MIPS_SIMD_architecture" title="MIPS architecture">MIPS SIMD</a></li></ul></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> <ul><li><a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">MAX</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/AltiVec" title="AltiVec">VMX</a></li></ul></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a> <ul><li><a href="/wiki/Visual_Instruction_Set" title="Visual Instruction Set">VIS</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> (<a href="/wiki/X86" title="X86">x86</a>)</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> (1996)</li> <li><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a> (1998)</li> <li><a class="mw-selflink selflink">SSE</a> (1999)</li> <li><a href="/wiki/SSE2" title="SSE2">SSE2</a> (2001)</li> <li><a href="/wiki/SSE3" title="SSE3">SSE3</a> (2004)</li> <li><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a> (2006)</li> <li><a href="/wiki/SSE4" title="SSE4">SSE4</a> (2006)</li> <li><a href="/wiki/SSE5" title="SSE5">SSE5</a> <s>(2007)</s></li> <li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> (2008)</li> <li><a href="/wiki/F16C" title="F16C">F16C</a> (2009)</li> <li><a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a> (2009)</li> <li><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> (FMA4: 2011, FMA3: 2012)</li> <li><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> (2013)</li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> (2015)</li> <li><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a> (2022)</li> <li><a href="/wiki/AVX10" class="mw-redirect" title="AVX10">AVX10</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Bit_manipulation" title="Bit manipulation">Bit manipulation</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit_Manipulation_Instruction_Sets" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI</a> (ABM: 2007, BMI1: 2012, BMI2: 2013, TBM: 2012)</li> <li><a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a> (2014)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture#Code_density" title="Instruction set architecture">Compressed instructions</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARM_architecture_family#Thumb" title="ARM architecture family">Thumb</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS16e ASE</a></li> <li><a href="/wiki/RISC-V#Compressed_subset" title="RISC-V">RVC</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Security and <a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">cryptography</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/VIA_PadLock" title="VIA PadLock">PadLock</a> (2003)</li> <li><a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a> (2008); ARMv8 also has AES instructions</li> <li><a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a> (2010)</li> <li><a href="/wiki/RDRAND" title="RDRAND">RDRAND</a> (2012)</li> <li><a href="/wiki/Intel_SHA_extensions" class="mw-redirect" title="Intel SHA extensions">SHA</a> (2013)</li> <li><a href="/wiki/Intel_MPX" title="Intel MPX">MPX</a> (2015)</li> <li><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a> (2015)</li> <li><a href="/wiki/Trust_Domain_Extensions" title="Trust Domain Extensions">TDX</a> (2021)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transactional_memory" title="Transactional memory">Transactional memory</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transactional_Synchronization_Extensions" title="Transactional Synchronization Extensions">TSX</a> (2013)</li> <li><a href="/wiki/Advanced_Synchronization_Facility" title="Advanced Synchronization Facility">ASF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Virtualization</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/X86_virtualization#Intel_virtualization_(VT-x)" title="X86 virtualization">VT-x</a> (2005)</li> <li><a href="/wiki/X86_virtualization#AMD_virtualization_(AMD-V)" title="X86 virtualization">AMD-V</a> (2006)</li> <li><a href="/wiki/X86_virtualization#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" title="X86 virtualization">VT-d</a> (AMD-Vi)</li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Suspended extensions' dates are <s>struck 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