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class="vector-toc-link" href="#Hardware-assisted_virtualization"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Hardware-assisted virtualization</span> </div> </a> <button aria-controls="toc-Hardware-assisted_virtualization-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Hardware-assisted virtualization subsection</span> </button> <ul id="toc-Hardware-assisted_virtualization-sublist" class="vector-toc-list"> <li id="toc-Central_processing_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Central_processing_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Central processing unit</span> </div> </a> <ul id="toc-Central_processing_unit-sublist" class="vector-toc-list"> <li id="toc-Virtual_8086_mode" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Virtual_8086_mode"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.1</span> <span>Virtual 8086 mode</span> </div> </a> <ul id="toc-Virtual_8086_mode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-AMD_virtualization_(AMD-V)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#AMD_virtualization_(AMD-V)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.2</span> <span>AMD virtualization (AMD-V)</span> </div> </a> <ul id="toc-AMD_virtualization_(AMD-V)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Intel_virtualization_(VT-x)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Intel_virtualization_(VT-x)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.3</span> <span>Intel virtualization (VT-x)</span> </div> </a> <ul id="toc-Intel_virtualization_(VT-x)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-VIA_virtualization_(VIA_VT)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#VIA_virtualization_(VIA_VT)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.4</span> <span>VIA virtualization (VIA VT)</span> </div> </a> <ul id="toc-VIA_virtualization_(VIA_VT)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.5</span> <span>Interrupt virtualization (AMD AVIC and Intel APICv)</span> </div> </a> <ul id="toc-Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Graphics_processing_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Graphics_processing_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Graphics processing unit</span> </div> </a> <ul id="toc-Graphics_processing_unit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Chipset" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chipset"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Chipset</span> </div> </a> <ul id="toc-Chipset-sublist" class="vector-toc-list"> <li id="toc-I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>I/O MMU virtualization (AMD-Vi and Intel VT-d)</span> </div> </a> <ul id="toc-I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Network_virtualization_(VT-c)" class="vector-toc-list-item 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also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div 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mw-first-heading">x86 virtualization</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. 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class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Virtualitzaci%C3%B3_x86" title="Virtualització x86 – Catalan" lang="ca" hreflang="ca" data-title="Virtualització x86" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/X86-Virtualisierung" title="X86-Virtualisierung – German" lang="de" hreflang="de" data-title="X86-Virtualisierung" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Virtualizaci%C3%B3n_x86" title="Virtualización x86 – Spanish" lang="es" hreflang="es" data-title="Virtualización x86" data-language-autonym="Español" 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class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Hardware-assisted virtualization on x86/x86-64 CPUs</div> <p><b>x86 virtualization</b> is the use of <a href="/wiki/Hardware_virtualization" title="Hardware virtualization">hardware-assisted virtualization</a> capabilities on an <a href="/wiki/X86" title="X86">x86</a>/<a href="/wiki/X86-64" title="X86-64">x86-64</a> <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a>. </p><p>In the late 1990s x86 virtualization was achieved by complex <a href="/wiki/Software" title="Software">software</a> techniques, necessary to compensate for the processor's lack of hardware-assisted virtualization capabilities while attaining reasonable <a href="/wiki/Computer_performance" title="Computer performance">performance</a>. In 2005 and 2006, both <a href="/wiki/Intel" title="Intel">Intel</a> (<a href="#Intel_virtualization_(VT-x)">VT-x</a>) and <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> (<a href="#AMD_virtualization_(AMD-V)">AMD-V</a>) introduced limited hardware virtualization support that allowed simpler virtualization software but offered very few speed benefits.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Greater hardware support, which allowed substantial speed improvements, came with later processor models. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Software-based_virtualization"><span class="anchor" id="SWBASED"></span>Software-based virtualization</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=1" title="Edit section: Software-based virtualization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following discussion focuses only on virtualization of the x86 architecture <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>. </p><p>In protected mode the operating system kernel runs at a higher privilege such as <a href="/wiki/Protection_ring" title="Protection ring">ring</a> 0, and applications at a lower privilege such as ring 3.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (January 2019)">citation needed</span></a></i>]</sup> In software-based virtualization, a host OS has direct access to hardware while the guest OSs have limited access to hardware, just like any other application of the host OS. One approach used in x86 software-based virtualization to overcome this limitation is called <i>ring deprivileging</i>, which involves running the guest OS at a ring higher (lesser privileged) than 0.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>Three techniques made virtualization of protected mode possible: </p> <ul><li><a href="/wiki/Binary_translation" title="Binary translation">Binary translation</a> is used to rewrite certain ring 0 instructions in terms of ring 3 instructions, such as <a href="/wiki/Interrupt_flag#Setting_and_clearing" title="Interrupt flag">POPF</a>, that would otherwise fail silently or behave differently when executed above ring 0,<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-asplos_4-0" class="reference"><a href="#cite_note-asplos-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 3">: 3 </span></sup> making the classic <a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">trap-and-emulate virtualization</a> impossible.<sup id="cite_ref-asplos_4-1" class="reference"><a href="#cite_note-asplos-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 1">: 1 </span></sup><sup id="cite_ref-pat242_5-0" class="reference"><a href="#cite_note-pat242-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> To improve performance, the translated <a href="/wiki/Basic_block" title="Basic block">basic blocks</a> need to be cached in a coherent way that detects <a href="/w/index.php?title=Code_patching&action=edit&redlink=1" class="new" title="Code patching (page does not exist)">code patching</a> (used in <a href="/wiki/VxD" title="VxD">VxDs</a> for instance), the reuse of pages by the guest OS, or even <a href="/wiki/Self-modifying_code" title="Self-modifying code">self-modifying code</a>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li> <li>A number of key data structures used by a processor need to be <a href="/wiki/Shadow_memory" title="Shadow memory">shadowed</a>. Because most operating systems use <a href="/wiki/Paged_virtual_memory" class="mw-redirect" title="Paged virtual memory">paged virtual memory</a>, and granting the guest OS direct access to the <a href="/wiki/Memory_management_unit" title="Memory management unit">MMU</a> would mean loss of control by the <a href="/wiki/Hypervisor" title="Hypervisor">virtualization manager</a>, some of the work of the x86 MMU needs to be duplicated in software for the guest OS using a technique known as <i>shadow page tables</i>.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 5">: 5 </span></sup><sup id="cite_ref-asplos_4-2" class="reference"><a href="#cite_note-asplos-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 2">: 2 </span></sup> This involves denying the guest OS any access to the actual page table entries by trapping access attempts and emulating them instead in software. The x86 architecture uses hidden state to store <a href="/wiki/Segment_descriptor" title="Segment descriptor">segment descriptors</a> in the processor, so once the segment descriptors have been loaded into the processor, the memory from which they have been loaded may be overwritten and there is no way to get the descriptors back from the processor. <i>Shadow descriptor tables</i> must therefore be used to track changes made to the descriptor tables by the guest OS.<sup id="cite_ref-pat242_5-1" class="reference"><a href="#cite_note-pat242-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup></li> <li>I/O device emulation: Unsupported devices on the guest OS must be emulated by a <a href="/wiki/Emulator" title="Emulator">device emulator</a> that runs in the host OS.<sup id="cite_ref-pat847_8-0" class="reference"><a href="#cite_note-pat847-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li></ul> <p>These techniques incur some performance overhead due to lack of MMU virtualization support, as compared to a VM running on a natively virtualizable architecture such as the <a href="/wiki/IBM_System/370" title="IBM System/370">IBM System/370</a>.<sup id="cite_ref-asplos_4-3" class="reference"><a href="#cite_note-asplos-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 10">: 10 </span></sup><sup id="cite_ref-tac9_9-0" class="reference"><a href="#cite_note-tac9-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 17 and 21">: 17 and 21 </span></sup> </p><p>On traditional mainframes, the classic <a href="/wiki/Hypervisor#Classification" title="Hypervisor">type 1</a> hypervisor was self-standing and did not depend on any operating system or run any user applications itself. In contrast, the first x86 virtualization products were aimed at workstation computers, and ran a guest OS inside a host OS by embedding the hypervisor in a kernel module that ran under the host OS (type 2 hypervisor).<sup id="cite_ref-pat847_8-1" class="reference"><a href="#cite_note-pat847-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>There has been some controversy whether the x86 architecture with no hardware assistance is virtualizable as described by <a href="/wiki/Popek_and_Goldberg_virtualization_requirements" title="Popek and Goldberg virtualization requirements">Popek and Goldberg</a>. <a href="/wiki/VMware" title="VMware">VMware</a> researchers pointed out in a 2006 <a href="/wiki/International_Conference_on_Architectural_Support_for_Programming_Languages_and_Operating_Systems" title="International Conference on Architectural Support for Programming Languages and Operating Systems">ASPLOS</a> paper that the above techniques made the x86 platform virtualizable in the sense of meeting the three criteria of Popek and Goldberg, albeit not by the classic trap-and-emulate technique.<sup id="cite_ref-asplos_4-4" class="reference"><a href="#cite_note-asplos-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 2–3">: 2–3 </span></sup> </p><p>A different route was taken by other systems like <a href="/wiki/Denali_(operating_system)" title="Denali (operating system)">Denali</a>, <a href="/wiki/L4_microkernel_family" title="L4 microkernel family">L4</a>, and <a href="/wiki/Xen" title="Xen">Xen</a>, known as <a href="/wiki/Paravirtualization" class="mw-redirect" title="Paravirtualization">paravirtualization</a>, which involves <a href="/wiki/Porting" title="Porting">porting</a> operating systems to run on the resulting virtual machine, which does not implement the parts of the actual x86 instruction set that are hard to virtualize. The paravirtualized I/O has significant performance benefits as demonstrated in the original <a href="/wiki/Symposium_on_Operating_Systems_Principles" title="Symposium on Operating Systems Principles">SOSP</a>'03 Xen paper.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p>The initial version of <a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/X86-64#AMD64" title="X86-64">AMD64</a>) did not allow for a software-only full virtualization due to the lack of segmentation support in <a href="/wiki/Long_mode" title="Long mode">long mode</a>, which made the protection of the hypervisor's memory impossible, in particular, the protection of the trap handler that runs in the guest kernel address space.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 11 and 20">: 11 and 20 </span></sup> Revision D and later 64-bit AMD processors (as a rule of thumb, those manufactured in 90 nm or less) added basic support for segmentation in long mode, making it possible to run 64-bit guests in 64-bit hosts via binary translation. Intel did not add segmentation support to its x86-64 implementation (<a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>), making 64-bit software-only virtualization impossible on Intel CPUs, but Intel VT-x support makes 64-bit hardware assisted virtualization possible on the Intel platform.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 4">: 4 </span></sup> </p><p>On some platforms, it is possible to run a 64-bit guest on a 32-bit host OS if the underlying processor is 64-bit and supports the necessary virtualization extensions. </p> <div class="mw-heading mw-heading2"><h2 id="Hardware-assisted_virtualization"><span class="anchor" id="Hardware_support"></span>Hardware-assisted virtualization</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=2" title="Edit section: Hardware-assisted virtualization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Hardware-assisted virtualization</a></div> <p>In 2005 and 2006, <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> (working independently) created new <a href="/wiki/X86#Extensions" title="X86">processor extensions</a> to the x86 architecture. The first generation of x86 hardware virtualization addressed the issue of privileged instructions. The issue of low performance of virtualized system memory was addressed with <a href="/wiki/Memory_management_unit" title="Memory management unit">MMU</a> virtualization that was added to the chipset later. </p> <div class="mw-heading mw-heading3"><h3 id="Central_processing_unit">Central processing unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=3" title="Edit section: Central processing unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Virtual_8086_mode">Virtual 8086 mode</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=4" title="Edit section: Virtual 8086 mode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">Virtual 8086 mode</a></div> <p>Because the <a href="/wiki/Intel_80286" title="Intel 80286">Intel 80286</a> could not run concurrent DOS applications well by itself in protected mode, Intel introduced the <a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">virtual 8086 mode</a> in their <a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">80386</a> chip, which offered virtualized 8086 processors on the 386 and later chips. Hardware support for virtualizing the protected mode itself, however, became available 20 years later.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="AMD_virtualization_(AMD-V)"><span id="AMD_virtualization_.28AMD-V.29"></span><span class="anchor" id="AMD-V"></span>AMD virtualization (AMD-V)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=5" title="Edit section: AMD virtualization (AMD-V)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_Phenom_die_equalized.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/AMD_Phenom_die_equalized.png/220px-AMD_Phenom_die_equalized.png" decoding="async" width="220" height="250" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/66/AMD_Phenom_die_equalized.png/330px-AMD_Phenom_die_equalized.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/66/AMD_Phenom_die_equalized.png/440px-AMD_Phenom_die_equalized.png 2x" data-file-width="1059" data-file-height="1202" /></a><figcaption><a href="/wiki/AMD_Phenom" title="AMD Phenom">AMD Phenom</a> die</figcaption></figure> <p>AMD developed its first generation virtualization extensions under the code name "Pacifica", and initially published them as AMD Secure Virtual Machine (SVM),<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> but later marketed them under the trademark <i>AMD Virtualization</i>, abbreviated <i>AMD-V</i>. </p><p>On May 23, 2006, AMD released the Athlon 64 (<a href="/wiki/List_of_AMD_Athlon_64_microprocessors#"Orleans"_(F2_&_F3,_90_nm)" class="mw-redirect" title="List of AMD Athlon 64 microprocessors">"Orleans"</a>), the Athlon 64 X2 (<a href="/wiki/List_of_AMD_Athlon_64_microprocessors#"Windsor"_(F2_&_F3,_90_nm)" class="mw-redirect" title="List of AMD Athlon 64 microprocessors">"Windsor"</a>) and the Athlon 64 FX (<a href="/wiki/List_of_AMD_Athlon_64_microprocessors#"Windsor"_(F2,_90_nm)" class="mw-redirect" title="List of AMD Athlon 64 microprocessors">"Windsor"</a>) as the first AMD processors to support this technology. </p><p>AMD-V capability also features on the <a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a> and <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a> family of processors with revisions "F" or "G" on <a href="/wiki/Socket_AM2" title="Socket AM2">socket AM2</a>, <a href="/wiki/AMD_Turion#Turion_64_X2" title="AMD Turion">Turion 64 X2</a>, and <a href="/wiki/Opteron" title="Opteron">Opteron</a> 2nd generation<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> and third-generation,<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> <a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a> and <a href="/wiki/Phenom_II" title="Phenom II">Phenom II</a> processors. The <a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">APU Fusion</a> processors support AMD-V. AMD-V is not supported by any Socket 939 processors. The only <a href="/wiki/Sempron" title="Sempron">Sempron</a> processors which support it are APUs and <a href="/wiki/List_of_AMD_Sempron_microprocessors#"Huron"_(65_nm,_Low_power)" class="mw-redirect" title="List of AMD Sempron microprocessors">Huron</a>, <a href="/wiki/List_of_AMD_Sempron_microprocessors#"Regor"_(Socket_AM3,_Dual-core,_C3,_45_nm)" class="mw-redirect" title="List of AMD Sempron microprocessors">Regor</a>, <a href="/wiki/List_of_AMD_Sempron_microprocessors#"Sargas"_(Socket_AM3,_Single-core,_C2_&_C3,_45_nm)" class="mw-redirect" title="List of AMD Sempron microprocessors">Sargas</a> desktop CPUs. </p><p>AMD Opteron CPUs beginning with the Family 0x10 Barcelona line, and Phenom II CPUs, support a second generation hardware virtualization technology called <a href="/wiki/Rapid_Virtualization_Indexing" class="mw-redirect" title="Rapid Virtualization Indexing">Rapid Virtualization Indexing</a> (formerly known as Nested Page Tables during its development), later adopted by Intel as <a href="/wiki/Extended_Page_Table" class="mw-redirect" title="Extended Page Table">Extended Page Tables</a> (EPT). </p><p>As of 2019, all <a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a>-based AMD processors support AMD-V. </p><p>The <a href="/wiki/CPU_flag_(x86)" class="mw-redirect" title="CPU flag (x86)">CPU flag</a> for AMD-V is "svm". This may be checked in <a href="/wiki/Comparison_of_BSD_operating_systems" title="Comparison of BSD operating systems">BSD derivatives</a> via <a href="/wiki/Dmesg" title="Dmesg">dmesg</a> or <a href="/wiki/Sysctl" title="Sysctl">sysctl</a> and in <a href="/wiki/Linux" title="Linux">Linux</a> via <code>/proc/<a href="/wiki/Cpuinfo" class="mw-redirect" title="Cpuinfo">cpuinfo</a></code>.<sup id="cite_ref-cpuflag_19-0" class="reference"><a href="#cite_note-cpuflag-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> Instructions in AMD-V include VMRUN, VMLOAD, VMSAVE, CLGI, VMMCALL, INVLPGA, SKINIT, and STGI. </p><p>With some <a href="/wiki/Motherboard" title="Motherboard">motherboards</a>, users must enable AMD SVM feature in the <a href="/wiki/BIOS" title="BIOS">BIOS</a> setup before applications can make use of it.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Intel_virtualization_(VT-x)"><span id="Intel_virtualization_.28VT-x.29"></span><span class="anchor" id="Intel-VT-x"></span><span class="anchor" id="VMCS-SHADOWING"></span>Intel virtualization (VT-x)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=6" title="Edit section: Intel virtualization (VT-x)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">"Intel VT-x" redirects here. For the Itanium virtualization extensions, see <a href="/wiki/Intel_VT-i" class="mw-redirect" title="Intel VT-i">Intel VT-i</a>.</div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Core_i7-940_bottom.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i7-940_bottom.jpg/220px-Intel_Core_i7-940_bottom.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i7-940_bottom.jpg/330px-Intel_Core_i7-940_bottom.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i7-940_bottom.jpg/440px-Intel_Core_i7-940_bottom.jpg 2x" data-file-width="4000" data-file-height="3000" /></a><figcaption><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Bloomfield"_(45_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Intel Core i7</a> (Bloomfield) CPU</figcaption></figure> <p>Previously codenamed "Vanderpool", VT-x represents Intel's technology for virtualization on the x86 platform. On November 14, 2005, Intel released two models of <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> (Model 662 and 672) as the first Intel processors to support VT-x. The CPU flag for VT-x capability is "vmx"; in Linux, this can be checked via <code>/proc/cpuinfo</code>, or in <a href="/wiki/MacOS" title="MacOS">macOS</a> via <code>sysctl machdep.cpu.features</code>.<sup id="cite_ref-cpuflag_19-1" class="reference"><a href="#cite_note-cpuflag-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p><p>"VMX" stands for Virtual Machine Extensions, which adds 13 new instructions: VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON, INVEPT, INVVPID, and VMFUNC.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> These instructions permit entering and exiting a virtual execution mode where the guest OS perceives itself as running with full privilege (ring 0), but the host OS remains protected. </p><p>As of 2015<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=X86_virtualization&action=edit">[update]</a></sup>, almost all newer server, desktop and mobile Intel processors support VT-x, with some of the <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a> processors as the primary exception.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> With some <a href="/wiki/Motherboard" title="Motherboard">motherboards</a>, users must enable Intel's VT-x feature in the <a href="/wiki/BIOS" title="BIOS">BIOS</a> setup before applications can make use of it.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>Intel started to include <a href="/wiki/Extended_Page_Table" class="mw-redirect" title="Extended Page Table">Extended Page Tables</a> (EPT),<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> a technology for page-table virtualization,<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> since the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> architecture,<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> released in 2008. In 2010, <a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a> added support for launching the logical processor directly in <a href="/wiki/Real_mode" title="Real mode">real mode</a> –  a feature called "unrestricted guest", which requires EPT to work.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p>Since the <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> microarchitecture (announced in 2013), Intel started to include <i>VMCS shadowing</i> as a technology that accelerates <a href="/wiki/Virtualization#Nested_virtualization" title="Virtualization">nested virtualization</a> of VMMs.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> The <i>virtual machine control structure</i> (VMCS) is a <a href="/wiki/Data_structure" title="Data structure">data structure</a> in memory that exists exactly once per VM, while it is managed by the VMM. With every change of the execution context between different VMs, the VMCS is restored for the current VM, defining the state of the VM's virtual processor.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> As soon as more than one VMM or nested VMMs are used, a problem appears in a way similar to what required shadow page table management to be invented, as described <a href="#SWBASED">above</a>. In such cases, VMCS needs to be shadowed multiple times (in case of nesting) and partially implemented in software in case there is no hardware support by the processor. To make shadow VMCS handling more efficient, Intel implemented hardware support for VMCS shadowing.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="VIA_virtualization_(VIA_VT)"><span id="VIA_virtualization_.28VIA_VT.29"></span>VIA virtualization (VIA VT)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=7" title="Edit section: VIA virtualization (VIA VT)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/VIA_Nano" title="VIA Nano">VIA Nano</a> 3000 Series Processors and higher support VIA VT virtualization technology compatible with Intel VT-x.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> EPT is present in <a href="/wiki/Zhaoxin" title="Zhaoxin">Zhaoxin</a> ZX-C, a descendant of <a href="/wiki/List_of_VIA_Nano_microprocessors#QuadCore-E" title="List of VIA Nano microprocessors">VIA QuadCore-E</a> & <a href="/wiki/List_of_VIA_Eden_microprocessors#Eden_C" title="List of VIA Eden microprocessors">Eden X4</a> similar to Nano <a href="/wiki/List_of_VIA_Nano_microprocessors#Nano_C" title="List of VIA Nano microprocessors">C4350AL</a>.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)"><span id="Interrupt_virtualization_.28AMD_AVIC_and_Intel_APICv.29"></span><span class="anchor" id="INTERRUPT"></span>Interrupt virtualization (AMD AVIC and Intel APICv)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=8" title="Edit section: Interrupt virtualization (AMD AVIC and Intel APICv)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 2012, AMD announced their <i>Advanced Virtual Interrupt Controller</i> (<i>AVIC</i>) targeting interrupt overhead reduction in virtualization environments.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> This technology, as announced, does not support <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">x2APIC</a>.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> In 2016, AVIC is available on the AMD family 15h models 6Xh (Carrizo) processors and newer.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p><p>Also in 2012, Intel announced a similar technology for interrupt and <a href="/wiki/Advanced_Programmable_Interrupt_Controller" title="Advanced Programmable Interrupt Controller">APIC</a> virtualization, which did not have a brand name at its announcement time.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> Later, it was branded as <i>APIC virtualization</i> (<i>APICv</i>)<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> and it became commercially available in the <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge EP</a> series of Intel CPUs, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Graphics_processing_unit"><span class="anchor" id="GPU"></span>Graphics processing unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=9" title="Edit section: Graphics processing unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Graphics virtualization is not part of the x86 architecture. Intel <a href="/wiki/Graphics_Virtualization_Technology" class="mw-redirect" title="Graphics Virtualization Technology">Graphics Virtualization Technology</a> (GVT) provides graphics virtualization as part of more recent Gen graphics architectures. Although <a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">AMD APUs</a> implement the <a href="/wiki/X86-64" title="X86-64">x86-64</a> instruction set, they implement AMD's own graphics architectures (<a href="/wiki/TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a>, <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">GCN</a> and <a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a>) which do not support graphics virtualization.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (October 2022)">citation needed</span></a></i>]</sup> <a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a> was the only graphics <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> based on x86, but it likely did not include support for graphics virtualization. </p> <div class="mw-heading mw-heading3"><h3 id="Chipset">Chipset</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=10" title="Edit section: Chipset"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/I/O_virtualization" title="I/O virtualization">I/O virtualization</a></div> <p>Memory and I/O virtualization is performed by the <a href="/wiki/Chipset" title="Chipset">chipset</a>.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> Typically these features must be enabled by the BIOS, which must be able to support them and also be set to use them. </p> <div class="mw-heading mw-heading4"><h4 id="I/O_MMU_virtualization_(AMD-Vi_and_Intel_VT-d)"><span id="I.2FO_MMU_virtualization_.28AMD-Vi_and_Intel_VT-d.29"></span><span class="anchor" id="Intel-VT-d"></span><span class="anchor" id="FLR"></span>I/O MMU virtualization (AMD-Vi and Intel VT-d)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=11" title="Edit section: I/O MMU virtualization (AMD-Vi and Intel VT-d)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Input%E2%80%93output_memory_management_unit#Virtualization" title="Input–output memory management unit">Input–output memory management unit § Virtualization</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD-Vi_boot_log_screenshot.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/AMD-Vi_boot_log_screenshot.png/330px-AMD-Vi_boot_log_screenshot.png" decoding="async" width="330" height="122" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/AMD-Vi_boot_log_screenshot.png/495px-AMD-Vi_boot_log_screenshot.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c4/AMD-Vi_boot_log_screenshot.png/660px-AMD-Vi_boot_log_screenshot.png 2x" data-file-width="859" data-file-height="318" /></a><figcaption>A <a href="/wiki/Linux_kernel" title="Linux kernel">Linux kernel</a> log showing AMD-Vi information</figcaption></figure> <p>An input/output memory management unit (IOMMU) allows guest <a href="/wiki/Virtual_machine" title="Virtual machine">virtual machines</a> to directly use <a href="/wiki/Peripheral" title="Peripheral">peripheral</a> devices, such as Ethernet, accelerated graphics cards, and hard-drive controllers, through <a href="/wiki/Direct_memory_access" title="Direct memory access">DMA</a> and <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> remapping. This is sometimes called <i>PCI passthrough</i>.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p><p>An IOMMU also allows operating systems to eliminate bounce buffers needed to allow themselves to communicate with peripheral devices whose memory address spaces are smaller than the operating system's memory address space, by using memory address translation. At the same time, an IOMMU also allows operating systems and hypervisors to prevent buggy or malicious hardware from <a href="/wiki/DMA_attack" title="DMA attack">compromising memory security</a>. </p><p>Both AMD and Intel have released their IOMMU specifications: </p> <ul><li>AMD's I/O Virtualization Technology, "AMD-Vi", originally called "IOMMU"<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup></li> <li>Intel's "Virtualization Technology for Directed I/O" (VT-d),<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> included in most high-end (but not all) newer Intel processors since the Core 2 architecture.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup></li></ul> <p>In addition to the CPU support, both <a href="/wiki/Motherboard" title="Motherboard">motherboard</a> <a href="/wiki/Chipset" title="Chipset">chipset</a> and system firmware (<a href="/wiki/BIOS" title="BIOS">BIOS</a> or <a href="/wiki/Unified_Extensible_Firmware_Interface" class="mw-redirect" title="Unified Extensible Firmware Interface">UEFI</a>) need to fully support the IOMMU I/O virtualization functionality for it to be usable. Only the <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">PCI</a> or <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> devices supporting <i>function level reset</i> (FLR) can be virtualized this way, as it is required for reassigning various <a href="/wiki/PCI_device_function" class="mw-redirect" title="PCI device function">device functions</a> between virtual machines.<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> If a device to be assigned does not support <a href="/wiki/Message_Signaled_Interrupts" title="Message Signaled Interrupts">Message Signaled Interrupts</a> (MSI), it must not share <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> lines with other devices for the assignment to be possible.<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> All <a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">conventional PCI</a> devices routed behind a PCI/<a href="/wiki/PCI-X" title="PCI-X">PCI-X</a>-to-PCI Express bridge can be assigned to a guest virtual machine only all at once; PCI Express devices have no such restriction. </p> <div class="mw-heading mw-heading4"><h4 id="Network_virtualization_(VT-c)"><span id="Network_virtualization_.28VT-c.29"></span>Network virtualization (VT-c)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=12" title="Edit section: Network virtualization (VT-c)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Intel's "Virtualization Technology for Connectivity" (VT-c).<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading5"><h5 id="PCI-SIG_Single_Root_I/O_Virtualization_(SR-IOV)"><span id="PCI-SIG_Single_Root_I.2FO_Virtualization_.28SR-IOV.29"></span><span class="anchor" id="PCI-SIG"></span><span class="anchor" id="SR-IOV"></span>PCI-SIG Single Root I/O Virtualization (SR-IOV)</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=13" title="Edit section: PCI-SIG Single Root I/O Virtualization (SR-IOV)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951" /><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Single-root_input/output_virtualization" title="Single-root input/output virtualization">Single-root input/output virtualization</a></div> <p><i>PCI-SIG Single Root I/O Virtualization (SR-IOV)</i> provides a set of general (non-x86 specific) I/O virtualization methods based on <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> (PCIe) native hardware, as standardized by PCI-SIG:<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> </p> <ul><li><i>Address translation services (ATS)</i> supports native IOV across PCI Express via address translation. It requires support for new transactions to configure such translations.</li> <li><i><a href="/wiki/Single-root_input/output_virtualization" title="Single-root input/output virtualization">Single-root IOV</a> (SR-IOV or SRIOV)</i> supports native IOV in existing single-root complex PCI Express topologies. It requires support for new device capabilities to configure multiple virtualized configuration spaces.<sup id="cite_ref-intel-grantley_53-0" class="reference"><a href="#cite_note-intel-grantley-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup></li> <li><i>Multi-root IOV (MR-IOV)</i> supports native IOV in new topologies (for example, blade servers) by building on SR-IOV to provide multiple root complexes which share a common PCI Express hierarchy.</li></ul> <p>In SR-IOV, the most common of these, a host VMM configures supported devices to create and allocate virtual "shadows" of their configuration spaces so that virtual machine guests can directly configure and access such "shadow" device resources.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> With SR-IOV enabled, virtualized network interfaces are directly accessible to the guests,<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> avoiding involvement of the VMM and resulting in high overall performance;<sup id="cite_ref-intel-grantley_53-1" class="reference"><a href="#cite_note-intel-grantley-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> for example, SR-IOV achieves over 95% of the <a href="/wiki/Bare_machine" title="Bare machine">bare metal</a> network bandwidth in <a href="/wiki/NASA" title="NASA">NASA</a>'s virtualized datacenter<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> and in the <a href="/wiki/Amazon_Web_Services" title="Amazon Web Services">Amazon Public Cloud</a>.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=14" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 25em;"> <ul><li><a href="/wiki/Comparison_of_application_virtualization_software" title="Comparison of application virtualization software">Comparison of application virtualization software</a></li> <li><a href="/wiki/Comparison_of_platform_virtualization_software" title="Comparison of platform virtualization software">Comparison of platform virtualization software</a></li> <li><a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Hardware-assisted virtualization</a></li> <li><a href="/wiki/Hypervisor" title="Hypervisor">Hypervisor</a></li> <li><a href="/wiki/I/O_virtualization" title="I/O virtualization">I/O virtualization</a></li> <li><a href="/wiki/Network_virtualization" title="Network virtualization">Network virtualization</a></li> <li><a href="/wiki/OS-level_virtualization" title="OS-level virtualization">OS-level virtualization</a></li> <li><a href="/wiki/Timeline_of_virtualization_development" class="mw-redirect" title="Timeline of virtualization development">Timeline of virtualization development</a></li> <li><a href="/wiki/Virtual_machine" title="Virtual machine">Virtual machine</a></li> <li><a href="/wiki/List_of_IOMMU-supporting_hardware" title="List of IOMMU-supporting hardware">List of IOMMU-supporting hardware</a></li> <li><a href="/wiki/Second_Level_Address_Translation" title="Second Level Address Translation">Second Level Address Translation</a> (SLAT)</li> <li><a href="/wiki/Message_Signaled_Interrupts" title="Message Signaled Interrupts">Message Signaled Interrupts</a> (MSI)</li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=15" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://web.stanford.edu/class/cs240/readings/hwsw.pdf">A Comparison of Software and Hardware Techniques for x86 Virtualization, Keith Adams and Ole Agesen, VMware, ASPLOS’06 October 21–25, 2006, San Jose, California, USA</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20221024045801/https://web.stanford.edu/class/cs240/readings/hwsw.pdf">Archived</a> 2022-10-24 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> "Surprisingly, we find that the first-generation hardware support rarely offers performance advantages over existing software techniques. We ascribe this situation to high VMM/guest transition costs and a rigid programming model that leaves little room for software flexibility in managing either the frequency or cost of these transitions."</span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://software.intel.com/sites/default/files/m/0/2/1/b/b/1024-Virtualization.pdf">"Intel Virtualization Technology Processor Virtualization Extensions and Intel Trusted execution Technology"</a> <span class="cs1-format">(PDF)</span>. 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Retrieved <span class="nowrap">2014-01-08</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Enhanced+Networking+in+the+AWS+Cloud+-+Part+2&rft.pub=Scalable+Logic&rft.date=2013-12-31&rft_id=http%3A%2F%2Fblogs.scalablelogic.com%2F2014%2F01%2Fenhanced-networking-in-aws-cloud-part-2.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AX86+virtualization" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=X86_virtualization&action=edit&section=16" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.hardwaresecrets.com/everything-you-need-to-know-about-the-intel-virtualization-technology/">Everything You Need to Know About the Intel Virtualization Technology</a> Archived at <a rel="nofollow" class="external text" href="https://ghostarchive.org/archive/7xRW3?kreymer=true">ghostarchive.org</a> at 10 May 2022</li> <li><a rel="nofollow" class="external text" href="http://www.cs.usfca.edu/~cruse/cs686s07/">A special course at the University of San Francisco on Intel EM64T and VT Extensions</a> (2007)</li> <li><a rel="nofollow" class="external text" href="http://opensecuritytraining.info/AdvancedX86-VTX.html">2 day open source & open access class on writing a VT-x VMM</a></li></ul>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=0" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=X86_virtualization&oldid=1275849428">https://en.wikipedia.org/w/index.php?title=X86_virtualization&oldid=1275849428</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:X86_architecture" title="Category:X86 architecture">X86 architecture</a></li><li><a href="/wiki/Category:Hardware_virtualization" title="Category:Hardware virtualization">Hardware virtualization</a></li></ul></div><div id="mw-hidden-catlinks" class="mw-hidden-catlinks mw-hidden-cats-hidden">Hidden categories: <ul><li><a href="/wiki/Category:Webarchive_template_wayback_links" title="Category:Webarchive template wayback links">Webarchive template wayback links</a></li><li><a href="/wiki/Category:Articles_with_short_description" title="Category:Articles with short description">Articles with short description</a></li><li><a href="/wiki/Category:Short_description_matches_Wikidata" title="Category:Short description matches Wikidata">Short description matches Wikidata</a></li><li><a href="/wiki/Category:All_articles_with_unsourced_statements" title="Category:All articles with unsourced statements">All articles with unsourced statements</a></li><li><a href="/wiki/Category:Articles_with_unsourced_statements_from_January_2019" title="Category:Articles with unsourced statements from January 2019">Articles with unsourced statements from January 2019</a></li><li><a href="/wiki/Category:Articles_containing_potentially_dated_statements_from_2015" title="Category:Articles containing potentially dated statements from 2015">Articles containing potentially dated statements from 2015</a></li><li><a href="/wiki/Category:All_articles_containing_potentially_dated_statements" title="Category:All articles containing potentially dated statements">All articles containing potentially dated statements</a></li><li><a href="/wiki/Category:Articles_with_unsourced_statements_from_October_2022" title="Category:Articles with unsourced statements from October 2022">Articles with unsourced statements from October 2022</a></li></ul></div></div> </div> </main> </div> <div class="mw-footer-container"> <footer id="footer" class="mw-footer" > <ul id="footer-info"> <li id="footer-info-lastmod"> This page was last edited on 15 February 2025, at 12:37<span class="anonymous-show"> (UTC)</span>.</li> <li id="footer-info-copyright">Text is available under the <a href="/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License" title="Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License">Creative Commons Attribution-ShareAlike 4.0 License</a>; additional terms may apply. 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