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dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Stage of electronic circuit design</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">This article is about designing integrated circuits, as part of <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a>. For other kinds of routing, see <a href="/wiki/Routing_(disambiguation)" class="mw-disambig" title="Routing (disambiguation)">routing (disambiguation)</a>.</div> <p> In <a href="/wiki/Electronic_design" class="mw-redirect" title="Electronic design">electronic design</a>, <b>wire routing</b>, commonly called simply <b>routing</b>, is a step in the design of <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit boards</a> (PCBs) and <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs). It builds on a preceding step, called <a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">placement</a>, which determines the location of each active element of an IC or component on a PCB. After placement, the routing step adds wires needed to properly connect the placed components while obeying all <a href="/wiki/Design_rules" class="mw-redirect" title="Design rules">design rules</a> for the IC. Together, the placement and routing steps of IC design are known as <a href="/wiki/Place_and_route" title="Place and route">place and route</a>. </p><p>The task of all routers is the same. They are given some pre-existing polygons consisting of <a href="/wiki/Pin_(electronics)" class="mw-redirect" title="Pin (electronics)">pins</a> (also called terminals) on cells, and optionally some pre-existing wiring called preroutes. Each of these polygons are associated with a <a href="/wiki/Net_(electronics)" class="mw-redirect" title="Net (electronics)">net</a>, usually by name or number. The primary task of the router is to create geometries such that all terminals assigned to the same net are connected, no terminals assigned to different nets are connected, and all design rules are obeyed. A router can fail by not connecting terminals that should be connected (an open), by mistakenly connecting two terminals that should not be connected (a short), or by creating a design rule violation. In addition, to correctly connect the nets, routers may also be expected to make sure the design meets timing, has no <a href="/wiki/Crosstalk" title="Crosstalk">crosstalk</a> problems, meets any metal density requirements, does not suffer from <a href="/wiki/Antenna_effect" title="Antenna effect">antenna effects</a>, and so on. This long list of often conflicting objectives is what makes routing extremely difficult. </p><p>Almost every problem associated with routing is known to be <a href="/wiki/Computational_complexity_theory" title="Computational complexity theory">intractable</a>. The simplest routing problem, called the <a href="/wiki/Steiner_tree" class="mw-redirect" title="Steiner tree">Steiner tree</a> problem, of finding the shortest route for one net in one layer with no obstacles and no design rules is known to be <a href="/wiki/NP-complete" class="mw-redirect" title="NP-complete">NP-complete</a>, both in the case where all angles are allowed or if routing is restricted to only horizontal and vertical wires.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Variants of <a href="/wiki/Channel_router" title="Channel router">channel routing</a> have also been shown to be NP-complete,<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> as well as routing which reduces <a href="/wiki/Crosstalk" title="Crosstalk">crosstalk</a>, number of <a href="/wiki/Via_(electronics)" title="Via (electronics)">vias</a>, and so on. Routers therefore seldom attempt to find an optimum result. Instead, almost all routing is based on <a href="/wiki/Heuristic_(computer_science)" title="Heuristic (computer science)">heuristics</a> which try to find a solution that is good enough. </p><p>Design rules sometimes vary considerably from layer to layer. For example, the allowed width and spacing on the lower layers may be four or more times smaller than the allowed widths and spacings on the upper layers. This introduces many additional complications not faced by routers for other applications such as <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a> or <a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a> design. Particular difficulties ensue if the rules are not simple multiples of each other, and when vias must traverse between layers with different rules. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Types_of_routers"><span class="anchor" id="Manual_router"></span><span class="anchor" id="Interactive_router"></span><span class="anchor" id="Autorouter"></span><span class="anchor" id="Push-and-shove_router"></span>Types of routers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=1" title="Edit section: Types of routers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PCB_design_and_realisation_smt_and_through_hole.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/67/PCB_design_and_realisation_smt_and_through_hole.png/220px-PCB_design_and_realisation_smt_and_through_hole.png" decoding="async" width="220" height="117" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/67/PCB_design_and_realisation_smt_and_through_hole.png/330px-PCB_design_and_realisation_smt_and_through_hole.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/67/PCB_design_and_realisation_smt_and_through_hole.png/440px-PCB_design_and_realisation_smt_and_through_hole.png 2x" data-file-width="3000" data-file-height="1600" /></a><figcaption>A PCB as a design on a computer (left) and realized as a board assembly populated with components (right). The board is double sided, with through-hole plating, green solder resist and a white legend. Both surface mount and through-hole components have been used.</figcaption></figure> <p>The earliest types of EDA routers were "manual routers"—the drafter clicked a mouse on the endpoint of each line segment of each net. Modern PCB design software typically provides "interactive routers"—the drafter selects a pad and clicks a few places to give the EDA tool an idea of where to go, and the EDA tool tries to place wires as close to that path as possible without violating <a href="/wiki/Design_rule_checking" title="Design rule checking">design rule checking</a> (DRC). Some more advanced interactive routers have "push and shove" (aka "shove-aside" or "automoving") features in an interactive router; the EDA tool pushes other nets out of the way, if possible, in order to place a new wire where the drafter wants it and still avoid violating DRC. Modern PCB design software also typically provides "autorouters" that route all remaining unrouted connections without human intervention. </p><p>The main types of autorouters are: </p> <ul><li><a href="/wiki/Maze_router" class="mw-redirect" title="Maze router">Maze router</a><sup id="cite_ref-Byers_1991_3-0" class="reference"><a href="#cite_note-Byers_1991-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Ritchey_1999_4-0" class="reference"><a href="#cite_note-Ritchey_1999-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> <ul><li>Lee router<sup id="cite_ref-Lee_1961_5-0" class="reference"><a href="#cite_note-Lee_1961-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Byers_1991_3-1" class="reference"><a href="#cite_note-Byers_1991-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Whitaker_2005_6-0" class="reference"><a href="#cite_note-Whitaker_2005-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li> <li>Hadlock router<sup id="cite_ref-Hadlock_1977_7-0" class="reference"><a href="#cite_note-Hadlock_1977-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li> <li>Flood router<sup id="cite_ref-Byers_1991_3-2" class="reference"><a href="#cite_note-Byers_1991-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></li></ul></li> <li><a href="/w/index.php?title=Line-probe_router&action=edit&redlink=1" class="new" title="Line-probe router (page does not exist)">Line-probe router</a> <ul><li>Mikami–Tahuchi router<sup id="cite_ref-Mikami_1968_8-0" class="reference"><a href="#cite_note-Mikami_1968-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li> <li>Hightower router<sup id="cite_ref-Hightower_1969_9-0" class="reference"><a href="#cite_note-Hightower_1969-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Whitaker_2005_6-1" class="reference"><a href="#cite_note-Whitaker_2005-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Minges_1989_10-0" class="reference"><a href="#cite_note-Minges_1989-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Byers_1991_3-3" class="reference"><a href="#cite_note-Byers_1991-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></li></ul></li> <li>Pattern router<sup id="cite_ref-Whitaker_2005_6-2" class="reference"><a href="#cite_note-Whitaker_2005-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Minges_1989_10-1" class="reference"><a href="#cite_note-Minges_1989-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Channel_router" title="Channel router">Channel router</a><sup id="cite_ref-Reed_1985_11-0" class="reference"><a href="#cite_note-Reed_1985-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Minges_1989_10-2" class="reference"><a href="#cite_note-Minges_1989-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Whitaker_2005_6-3" class="reference"><a href="#cite_note-Whitaker_2005-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Shankar_2014_12-0" class="reference"><a href="#cite_note-Shankar_2014-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> <ul><li><a href="/w/index.php?title=Switchbox_router&action=edit&redlink=1" class="new" title="Switchbox router (page does not exist)">Switchbox router</a><sup id="cite_ref-Shankar_2014_12-1" class="reference"><a href="#cite_note-Shankar_2014-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></li> <li>River router<sup id="cite_ref-Shankar_2014_12-2" class="reference"><a href="#cite_note-Shankar_2014-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></li> <li>Spine and stitch router<sup id="cite_ref-McLellan_2012_13-0" class="reference"><a href="#cite_note-McLellan_2012-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li></ul></li> <li>Gridless router<sup id="cite_ref-Finch_1985_14-0" class="reference"><a href="#cite_note-Finch_1985-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Minges_1989_10-3" class="reference"><a href="#cite_note-Minges_1989-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Whitaker_2005_6-4" class="reference"><a href="#cite_note-Whitaker_2005-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Webb_2012_15-0" class="reference"><a href="#cite_note-Webb_2012-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> <ul><li><a href="/w/index.php?title=Area_router&action=edit&redlink=1" class="new" title="Area router (page does not exist)">Area router</a></li> <li>Graph theory-based router<sup id="cite_ref-Wu_1992_Graph_16-0" class="reference"><a href="#cite_note-Wu_1992_Graph-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> <ul><li><a href="/w/index.php?title=Bloodhound_router&action=edit&redlink=1" class="new" title="Bloodhound router (page does not exist)">Bloodhound router</a><sup id="cite_ref-CW_1992_Bloodhound_17-0" class="reference"><a href="#cite_note-CW_1992_Bloodhound-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Pfeil_2017_Bloodhound_18-0" class="reference"><a href="#cite_note-Pfeil_2017_Bloodhound-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Redlich_2018_Routers_19-0" class="reference"><a href="#cite_note-Redlich_2018_Routers-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> (<a href="/wiki/CADSTAR" title="CADSTAR">CADSTAR</a> by <a href="/wiki/Racal-Redac" class="mw-redirect" title="Racal-Redac">Racal-Redac</a> / <a href="/wiki/Zuken" title="Zuken">Zuken</a>)</li> <li><a href="/wiki/Specctra" title="Specctra">Specctra</a><sup id="cite_ref-Redlich_2018_Routers_19-1" class="reference"><a href="#cite_note-Redlich_2018_Routers-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> (aka <a href="/wiki/Allegro_PCB_Router" class="mw-redirect" title="Allegro PCB Router">Allegro PCB Router</a>) (gridless since version 10)</li></ul></li> <li><span class="anchor" id="Topological_router"></span><span class="anchor" id="AnyAngle"></span>Topological router <ul><li><a href="/wiki/FreeStyle_Router" class="mw-redirect" title="FreeStyle Router">FreeStyle Router</a> (aka <i>SpeedWay</i>, a <a href="/wiki/DOS" title="DOS">DOS</a>-based autorouter for <a href="/wiki/P-CAD" title="P-CAD">P-CAD</a>)</li> <li><a href="/wiki/TopoR" title="TopoR">TopoR</a> (a <a href="/wiki/Microsoft_Windows" title="Microsoft Windows">Windows</a>-based autorouter, also used in <a href="/wiki/Eremex" class="mw-redirect" title="Eremex">Eremex</a>'s Delta Design)</li> <li><a href="/wiki/Toporouter" class="mw-redirect" title="Toporouter">Toporouter</a> (Anthony Blake's open-source router in <a href="/wiki/PCB_(software)" title="PCB (software)">PCB</a> of the <a href="/wiki/GEDA_suite" class="mw-redirect" title="GEDA suite">gEDA suite</a>)</li> <li><a href="/wiki/TopRouter" class="mw-redirect" title="TopRouter">TopRouter</a> (the topological pre-router in <a href="/wiki/CadSoft_Computer" class="mw-redirect" title="CadSoft Computer">CadSoft</a>/<a href="/wiki/Autodesk" title="Autodesk">Autodesk</a>'s <a href="/wiki/EAGLE_7.0" class="mw-redirect" title="EAGLE 7.0">EAGLE 7.0</a> and higher)</li> <li>SimplifyPCB (a topological router with a focus on bundle routing with hand-routing results)<sup id="cite_ref-SimplifyPCB_20-0" class="reference"><a href="#cite_note-SimplifyPCB-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></li></ul></li></ul></li></ul> <div class="mw-heading mw-heading2"><h2 id="How_routers_work"><span class="anchor" id="Ripup-router"></span>How routers work</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=2" title="Edit section: How routers work"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Many routers execute the following overall algorithm: </p> <ul><li>First, determine an approximate course for each net, often by routing on a coarse grid. This step is called <i>global routing</i>,<sup id="cite_ref-Soukup_1979_21-0" class="reference"><a href="#cite_note-Soukup_1979-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> and may optionally include layer assignment. Global routing limits the size and complexity of the following detailed routing steps, which can be done grid square by grid square.</li></ul> <p>For detailed routing, the most common technique is <b>rip-up and reroute</b> aka <b>rip-up and retry</b>:<sup id="cite_ref-Byers_1991_3-4" class="reference"><a href="#cite_note-Byers_1991-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Select a sequence in which the nets are to be routed.</li> <li>Route each net in sequence</li> <li>If not all nets can be successfully routed, apply any of a variety of "cleanup" methods, in which selected routings are removed, the order of the remaining nets to be routed is changed, and the remaining routings are attempted again.</li></ul> <p>This process repeats until all nets are routed or the program (or user) gives up. </p><p>An alternative approach is to treat shorts, design rule violations, obstructions, etc. on a similar footing as excess wire length—that is, as finite costs to be reduced (at first) rather than as absolutes to be avoided. This multi-pass "iterative-improvement" routing method<sup id="cite_ref-Rubin_1974_22-0" class="reference"><a href="#cite_note-Rubin_1974-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> is described by the following algorithm: </p> <ul><li>For each of several iterative passes:</li> <li>Prescribe or adjust the weight parameters of an "objective function" (having a weight parameter value for each unit of excess wire length, and for each type of violation). E.g., for the first pass, excess wire length may typically be given a high cost, while design violations such as shorts, adjacency, etc. are given a low cost. In later passes, the relative ordering of costs is changed so that violations are high-cost, or may be prohibited absolutely.</li> <li>Select (or randomly choose) a sequence in which nets are to be routed during this pass.</li> <li>"Rip up" (if previously routed) and reroute each net in turn, so as to minimize the value of the objective function for that net. (Some of the routings will in general have shorts or other design violations.)</li> <li>Proceed to the next iterative pass until routing is complete and correct, is not further improved, or some other termination criterion is satisfied.</li></ul> <p>Most routers assign wiring layers to carry predominantly "x" or "y" directional wiring, though there have been routers which avoid or reduce the need for such assignment.<sup id="cite_ref-Linsker_1984_23-0" class="reference"><a href="#cite_note-Linsker_1984-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> There are advantages and disadvantages to each approach. Restricted directions make power supply design and the control of inter-layer crosstalk easier, but allowing arbitrary routes can reduce the need for vias and decrease the number of required wiring layers. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=3" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a></li> <li><a href="/wiki/Design_flow_(EDA)" title="Design flow (EDA)">Design flow (EDA)</a></li> <li><a href="/wiki/Integrated_circuit_design" title="Integrated circuit design">Integrated circuit design</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a></li> <li><a href="/wiki/Auto_polarity_(differential_pairs)" class="mw-redirect" title="Auto polarity (differential pairs)">Auto polarity (differential pairs)</a></li> <li><a href="/wiki/Auto_crossover_(Ethernet)" class="mw-redirect" title="Auto crossover (Ethernet)">Auto crossover (Ethernet)</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=4" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFGareyJohnson1977" class="citation journal cs1">Garey, M. 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(1985). <a rel="nofollow" class="external text" href="https://ieeexplore.ieee.org/document/1270096">"Dogleg Channel Routing is NP-Complete"</a>. <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. <b>4</b> (1): 31–41. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2Ftcad.1985.1270096">10.1109/tcad.1985.1270096</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:17511882">17511882</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+and+Systems&rft.atitle=Dogleg+Channel+Routing+is+NP-Complete&rft.volume=4&rft.issue=1&rft.pages=31-41&rft.date=1985&rft_id=info%3Adoi%2F10.1109%2Ftcad.1985.1270096&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A17511882%23id-name%3DS2CID&rft.aulast=Szymanski&rft.aufirst=Thomas+G.&rft_id=https%3A%2F%2Fieeexplore.ieee.org%2Fdocument%2F1270096&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Byers_1991-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-Byers_1991_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Byers_1991_3-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Byers_1991_3-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Byers_1991_3-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-Byers_1991_3-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFByers1991" class="citation book cs1">Byers, T. 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New York, USA: <a href="/wiki/Intertext_Publications/Multiscience_Press,_Inc." class="mw-redirect" title="Intertext Publications/Multiscience Press, Inc.">Intertext Publications/Multiscience Press, Inc.</a>, <a href="/wiki/McGraw-Hill_Book_Company" class="mw-redirect" title="McGraw-Hill Book Company">McGraw-Hill Book Company</a>. pp. 99–101. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-07-009558-8" title="Special:BookSources/978-0-07-009558-8"><bdi>978-0-07-009558-8</bdi></a>. <a href="/wiki/LCCN_(identifier)" class="mw-redirect" title="LCCN (identifier)">LCCN</a> <a rel="nofollow" class="external text" href="https://lccn.loc.gov/91-72187">91-72187</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Printed+Circuit+Board+Design+with+Microcomputers&rft.place=New+York%2C+USA&rft.pages=99-101&rft.edition=1&rft.pub=Intertext+Publications%2FMultiscience+Press%2C+Inc.%2C+McGraw-Hill+Book+Company&rft.date=1991-08-01&rft_id=info%3Alccn%2F91-72187&rft.isbn=978-0-07-009558-8&rft.aulast=Byers&rft.aufirst=T.+J.&rft_id=https%3A%2F%2Fdl.acm.org%2Fcitation.cfm%3Fid%3D114661&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Ritchey_1999-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-Ritchey_1999_4-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRitchey1999" class="citation journal cs1">Ritchey, Lee W. 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Retrieved <span class="nowrap">2018-10-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=PC+Design+Magazine&rft.atitle=PCB+routers+and+routing+methods&rft.issue=February+1999&rft.date=1999-12&rft.aulast=Ritchey&rft.aufirst=Lee+W.&rft_id=http%3A%2F%2Fwww.speedingedge.com%2FPDF-Files%2Fpcbrouters.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Lee_1961-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-Lee_1961_5-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLee1961" class="citation journal cs1 cs1-prop-long-vol">Lee, Chester Y. (September 1961). "An algorithm for path connections and its applications". <i><a href="/wiki/IRE_Transactions_on_Electronic_Computers" class="mw-redirect" title="IRE Transactions on Electronic Computers">IRE Transactions on Electronic Computers</a></i>. EC-10 (3): 346–365. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTEC.1961.5219222">10.1109/TEC.1961.5219222</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:40700386">40700386</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IRE+Transactions+on+Electronic+Computers&rft.atitle=An+algorithm+for+path+connections+and+its+applications&rft.volume=EC-10&rft.issue=3&rft.pages=346-365&rft.date=1961-09&rft_id=info%3Adoi%2F10.1109%2FTEC.1961.5219222&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A40700386%23id-name%3DS2CID&rft.aulast=Lee&rft.aufirst=Chester+Y.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Whitaker_2005-6"><span class="mw-cite-backlink">^ <a href="#cite_ref-Whitaker_2005_6-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Whitaker_2005_6-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Whitaker_2005_6-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Whitaker_2005_6-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-Whitaker_2005_6-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKolliparaTripathiSergentBlackwell2005" class="citation book cs1">Kollipara, Ravindranath; Tripathi, Vijai K.; Sergent, Jerry E.; Blackwell, Glenn R.; White, Donald; Staszak, Zbigniew J. (2005). <a rel="nofollow" class="external text" href="http://s1.downloadmienphi.net/file/downloadfile6/192/1385077.pdf">"11.1.3 Packaging Electronic Systems - Design of Printed Wiring Boards"</a> <span class="cs1-format">(PDF)</span>. In Whitaker, Jerry C.; Dorf, Richard C. (eds.). <i>The Electronics Handbook</i> (2 ed.). <a href="/wiki/CRC_Press" title="CRC Press">CRC Press</a>, <a href="/wiki/Taylor_%26_Francis_Group,_LLC" class="mw-redirect" title="Taylor & Francis Group, LLC">Taylor & Francis Group, LLC</a>. p. 1266. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-8493-1889-4" title="Special:BookSources/978-0-8493-1889-4"><bdi>978-0-8493-1889-4</bdi></a>. <a href="/wiki/LCCN_(identifier)" class="mw-redirect" title="LCCN (identifier)">LCCN</a> <a rel="nofollow" class="external text" href="https://lccn.loc.gov/2004057106">2004057106</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170925235855/http://s1.downloadmienphi.net/file/downloadfile6/192/1385077.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2017-09-25<span class="reference-accessdate">. Retrieved <span class="nowrap">2017-09-25</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=11.1.3+Packaging+Electronic+Systems+-+Design+of+Printed+Wiring+Boards&rft.btitle=The+Electronics+Handbook&rft.pages=1266&rft.edition=2&rft.pub=CRC+Press%2C+Taylor+%26+Francis+Group%2C+LLC&rft.date=2005&rft_id=info%3Alccn%2F2004057106&rft.isbn=978-0-8493-1889-4&rft.aulast=Kollipara&rft.aufirst=Ravindranath&rft.au=Tripathi%2C+Vijai+K.&rft.au=Sergent%2C+Jerry+E.&rft.au=Blackwell%2C+Glenn+R.&rft.au=White%2C+Donald&rft.au=Staszak%2C+Zbigniew+J.&rft_id=http%3A%2F%2Fs1.downloadmienphi.net%2Ffile%2Fdownloadfile6%2F192%2F1385077.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Hadlock_1977-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-Hadlock_1977_7-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHadlock1977" class="citation journal cs1">Hadlock, Frank O. (1977-12-01). <a rel="nofollow" class="external text" href="https://www.researchgate.net/publication/227815552">"A shortest path algorithm for grid graphs"</a>. <i>Networks</i>. <b>7</b> (4): 323–334. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1002%2Fnet.3230070404">10.1002/net.3230070404</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Networks&rft.atitle=A+shortest+path+algorithm+for+grid+graphs&rft.volume=7&rft.issue=4&rft.pages=323-334&rft.date=1977-12-01&rft_id=info%3Adoi%2F10.1002%2Fnet.3230070404&rft.aulast=Hadlock&rft.aufirst=Frank+O.&rft_id=https%3A%2F%2Fwww.researchgate.net%2Fpublication%2F227815552&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Mikami_1968-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-Mikami_1968_8-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMikamiTabuchi1968" class="citation conference cs1">Mikami, Koichi; Tabuchi, Kinya (1968). <i>A computer program for optimal routing of printed circuit connectors</i>. <a href="/wiki/IFIPS" class="mw-redirect" title="IFIPS">IFIPS</a> Proceedings. Vol. H47. pp. 1745–1478.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+computer+program+for+optimal+routing+of+printed+circuit+connectors&rft.pages=1745-1478&rft.date=1968&rft.aulast=Mikami&rft.aufirst=Koichi&rft.au=Tabuchi%2C+Kinya&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Hightower_1969-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-Hightower_1969_9-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHightower1969" class="citation conference cs1">Hightower, David W. (1969). "A solution to line-routing problems on the continuous plane". <i>DAC'69: Proceedings of the 6th Annual Conference on Design Automation</i>. <a href="/wiki/ACM_Press" class="mw-redirect" title="ACM Press">ACM Press</a>. pp. 1–24. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1145%2F800260.809014">10.1145/800260.809014</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.atitle=A+solution+to+line-routing+problems+on+the+continuous+plane&rft.btitle=DAC%2769%3A+Proceedings+of+the+6th+Annual+Conference+on+Design+Automation&rft.pages=1-24&rft.pub=ACM+Press&rft.date=1969&rft_id=info%3Adoi%2F10.1145%2F800260.809014&rft.aulast=Hightower&rft.aufirst=David+W.&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span> (NB. This contains one of the first descriptions of a "line probe router".)</span> </li> <li id="cite_note-Minges_1989-10"><span class="mw-cite-backlink">^ <a href="#cite_ref-Minges_1989_10-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Minges_1989_10-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Minges_1989_10-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Minges_1989_10-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMinges1989" class="citation book cs1">Minges, Merrill L. (1989). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=c2YxCCaM9RIC&pg=PA758"><i>Electronic Materials Handbook: Packaging</i></a>. Vol. 1. <a href="/wiki/ASM_International" title="ASM International">ASM International</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-87170-285-2" title="Special:BookSources/978-0-87170-285-2"><bdi>978-0-87170-285-2</bdi></a><span class="reference-accessdate">. Retrieved <span class="nowrap">2017-09-27</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Electronic+Materials+Handbook%3A+Packaging&rft.pub=ASM+International&rft.date=1989&rft.isbn=978-0-87170-285-2&rft.aulast=Minges&rft.aufirst=Merrill+L.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3Dc2YxCCaM9RIC%26pg%3DPA758&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Reed_1985-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-Reed_1985_11-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFReedSangiovanni-VincentelliSantamauro1985" class="citation journal cs1">Reed, James B.; Sangiovanni-Vincentelli, Alberto; Santamauro, Mauro (1985). "A new symbolic channel router: YACR2". <i><a href="/wiki/IEEE_Transactions_on_Computer-Aided_Design_of_Integrated_Circuits_and_Systems" title="IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems">IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</a></i>. <b>4</b> (3): 203–219. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTCAD.1985.1270117">10.1109/TCAD.1985.1270117</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:17065773">17065773</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+and+Systems&rft.atitle=A+new+symbolic+channel+router%3A+YACR2&rft.volume=4&rft.issue=3&rft.pages=203-219&rft.date=1985&rft_id=info%3Adoi%2F10.1109%2FTCAD.1985.1270117&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A17065773%23id-name%3DS2CID&rft.aulast=Reed&rft.aufirst=James+B.&rft.au=Sangiovanni-Vincentelli%2C+Alberto&rft.au=Santamauro%2C+Mauro&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span> <a rel="nofollow" class="external autonumber" href="https://www.researchgate.net/publication/3225251_A_New_Symbolic_Channel_Router_YACR2">[1]</a></span> </li> <li id="cite_note-Shankar_2014-12"><span class="mw-cite-backlink">^ <a href="#cite_ref-Shankar_2014_12-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Shankar_2014_12-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Shankar_2014_12-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShankarFernandez2014" class="citation book cs1">Shankar, Ravi; Fernandez, Eduardo B. (2014-01-12). Einspruch, Norman G. (ed.). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=jDGoBQAAQBAJ&pg=PA232"><i>VLSI and Computer Architecture</i></a>. VLSI Electronics Microstructure Science. Vol. 20. <a href="/wiki/Academic_Press" title="Academic Press">Academic Press</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-48321784-0" title="Special:BookSources/978-1-48321784-0"><bdi>978-1-48321784-0</bdi></a><span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=VLSI+and+Computer+Architecture&rft.series=VLSI+Electronics+Microstructure+Science&rft.pub=Academic+Press&rft.date=2014-01-12&rft.isbn=978-1-48321784-0&rft.aulast=Shankar&rft.aufirst=Ravi&rft.au=Fernandez%2C+Eduardo+B.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DjDGoBQAAQBAJ%26pg%3DPA232&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-McLellan_2012-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-McLellan_2012_13-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMcLellan2012" class="citation web cs1">McLellan, Paul (2012-04-23). <a rel="nofollow" class="external text" href="https://www.semiwiki.com/forum/content/1208-channel-routing-memories.html">"Channel Routing Memories"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210518114742/https://semiwiki.com/uncategorized/1208-channel-routing-memories/">Archived</a> from the original on 2021-05-18<span class="reference-accessdate">. Retrieved <span class="nowrap">2022-01-01</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Channel+Routing+Memories&rft.date=2012-04-23&rft.aulast=McLellan&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.semiwiki.com%2Fforum%2Fcontent%2F1208-channel-routing-memories.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Finch_1985-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-Finch_1985_14-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFFinchMackenzieBalsdonSymonds1985" class="citation conference cs1">Finch, Alan C.; Mackenzie, Ken J.; Balsdon, G. J.; Symonds, G. (1985-06-23). <a rel="nofollow" class="external text" href="https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1985/DAC85_509.PDF"><i>A Method for Gridless Routing of Printed Circuit Boards</i></a> <span class="cs1-format">(PDF)</span>. 22nd ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA. <i>Design Automation Conference, 2009. Dac '09. 46th ACM/IEEE</i>. Newtown, Tewkesbury, Gloucestershire, UK: <a href="/wiki/Racal-Redac_Ltd." class="mw-redirect" title="Racal-Redac Ltd.">Racal-Redac Ltd.</a> pp. 509–515. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FDAC.1985.1585990">10.1109/DAC.1985.1585990</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-8186-0635-5" title="Special:BookSources/0-8186-0635-5"><bdi>0-8186-0635-5</bdi></a>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0738-100X">0738-100X</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181022030533/https://www.cs.york.ac.uk/rts/docs/DAC-1964-2006/PAPERS/1985/DAC85_509.PDF">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2018-10-22<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-22</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=conference&rft.jtitle=Design+Automation+Conference%2C+2009.+Dac+%2709.+46th+ACM%2FIEEE&rft.atitle=A+Method+for+Gridless+Routing+of+Printed+Circuit+Boards&rft.pages=509-515&rft.date=1985-06-23&rft.issn=0738-100X&rft_id=info%3Adoi%2F10.1109%2FDAC.1985.1585990&rft.isbn=0-8186-0635-5&rft.aulast=Finch&rft.aufirst=Alan+C.&rft.au=Mackenzie%2C+Ken+J.&rft.au=Balsdon%2C+G.+J.&rft.au=Symonds%2C+G.&rft_id=https%3A%2F%2Fwww.cs.york.ac.uk%2Frts%2Fdocs%2FDAC-1964-2006%2FPAPERS%2F1985%2FDAC85_509.PDF&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Webb_2012-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-Webb_2012_15-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWebb2012" class="citation web cs1">Webb, Darrell (2012-12-20). <a rel="nofollow" class="external text" href="https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/">"A Tribute to Alan Finch, the Father of Gridless Autorouting"</a>. <a rel="nofollow" class="external text" href="https://archive.today/20181022034218/https://blog.zuken.com/a-tribute-to-alan-finch-the-father-of-gridless-autorouting/">Archived</a> from the original on 2018-10-22<span class="reference-accessdate">. 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Archived from <a rel="nofollow" class="external text" href="https://pdfs.semanticscholar.org/d998/0976dc33c9bfe8b8a049ad8da696526872f7.pdf">the original</a> <span class="cs1-format">(PDF)</span> on 2018-10-22<span class="reference-accessdate">. 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Retrieved <span class="nowrap">2018-10-20</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Computerwoche&rft.atitle=Computer-Partner+Kiel+GmbH%3A+%22Bloodhound%22+entflechtet+Leiterplatten+auf+16+Lagen&rft.date=1992-03-13&rft_id=https%3A%2F%2Fwww.computerwoche.de%2Fa%2Fbloodhound-entflechtet-leiterplatten-auf-16-lagen%2C1133225&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Pfeil_2017_Bloodhound-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-Pfeil_2017_Bloodhound_18-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPfeil2017" class="citation journal cs1">Pfeil, Charles (2017-11-02). <a rel="nofollow" class="external text" href="https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software">"A lifetime designing PCBs: From design to software"</a>. <i><a href="/wiki/EDN_Network" class="mw-redirect" title="EDN Network">EDN Network</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181021225546/https://www.edn.com/electronics-blogs/all-aboard-/4459033/A-lifetime-designing-PCBs--From-design-to-software">Archived</a> from the original on 2018-10-21<span class="reference-accessdate">. Retrieved <span class="nowrap">2018-10-20</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EDN+Network&rft.atitle=A+lifetime+designing+PCBs%3A+From+design+to+software&rft.date=2017-11-02&rft.aulast=Pfeil&rft.aufirst=Charles&rft_id=https%3A%2F%2Fwww.edn.com%2Felectronics-blogs%2Fall-aboard-%2F4459033%2FA-lifetime-designing-PCBs--From-design-to-software&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Redlich_2018_Routers-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-Redlich_2018_Routers_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Redlich_2018_Routers_19-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRedlich" class="citation book cs1 cs1-prop-foreign-lang-source">Redlich, Detlef. <a rel="nofollow" class="external text" href="https://archive.today/20181021231530/http://web.eah-jena.de/fhj/etit/fb/homepage/home-redlich/lehre/design/Documents/Rechnergest_LP_Entwurf_Einf%C3%BChrung.pdf">"1.6. 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Retrieved <span class="nowrap">2018-10-20</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=1.6.+Rechnergest%C3%BCtzter+Leiterplattenentwurf+-+Entflechtung&rft.btitle=Schaltungsdesign&rft.pub=Ernst-Abbe-Hochschule+Jena+%28EAH%29&rft.aulast=Redlich&rft.aufirst=Detlef&rft_id=http%3A%2F%2Fweb.eah-jena.de%2Ffhj%2Fetit%2Ffb%2Fhomepage%2Fhome-redlich%2Flehre%2Fdesign%2FDocuments%2FRechnergest_LP_Entwurf_Einf%25C3%25BChrung.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-SimplifyPCB-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-SimplifyPCB_20-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.simplifyda.com">"Simplify Design Automation – the next generation in design methodology"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Simplify+Design+Automation+%E2%80%93+the+next+generation+in+design+methodology&rft_id=http%3A%2F%2Fwww.simplifyda.com&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Soukup_1979-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-Soukup_1979_21-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSoukup1979" class="citation conference cs1">Soukup, Jirí (1979). <a rel="nofollow" class="external text" href="http://portal.acm.org/citation.cfm?id=811756">"Global Router"</a>. <i>Proceedings of the 16th Design Automation Conference</i>. San Diego, CA, USA: <a href="/wiki/IEEE_Press" class="mw-redirect" title="IEEE Press">IEEE Press</a>. pp. 481–489.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.atitle=Global+Router&rft.btitle=Proceedings+of+the+16th+Design+Automation+Conference&rft.place=San+Diego%2C+CA%2C+USA&rft.pages=481-489&rft.pub=IEEE+Press&rft.date=1979&rft.aulast=Soukup&rft.aufirst=Jir%C3%AD&rft_id=http%3A%2F%2Fportal.acm.org%2Fcitation.cfm%3Fid%3D811756&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Rubin_1974-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-Rubin_1974_22-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRubin1974" class="citation conference cs1">Rubin, Frank (1974). <a rel="nofollow" class="external text" href="http://portal.acm.org/citation.cfm?id=811407">"An iterative technique for printed wire routing"</a>. <i>Proceedings 11th Design Automation Workshop</i>. pp. 308–13.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.atitle=An+iterative+technique+for+printed+wire+routing&rft.btitle=Proceedings+11th+Design+Automation+Workshop&rft.pages=308-13&rft.date=1974&rft.aulast=Rubin&rft.aufirst=Frank&rft_id=http%3A%2F%2Fportal.acm.org%2Fcitation.cfm%3Fid%3D811407&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> <li id="cite_note-Linsker_1984-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-Linsker_1984_23-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLinsker1984" class="citation journal cs1">Linsker, Ralph (1984). <a rel="nofollow" class="external text" href="http://www.research.ibm.com/journal/rd/285/ibmrd2805N.pdf">"An iterative-improvement penalty-function-driven wire routing system"</a> <span class="cs1-format">(PDF)</span>. <i><a href="/wiki/IBM_Journal_of_Research_and_Development" title="IBM Journal of Research and Development">IBM Journal of Research and Development</a></i>. <b>28</b> (5): 613–624. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1147%2Frd.285.0613">10.1147/rd.285.0613</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IBM+Journal+of+Research+and+Development&rft.atitle=An+iterative-improvement+penalty-function-driven+wire+routing+system&rft.volume=28&rft.issue=5&rft.pages=613-624&rft.date=1984&rft_id=info%3Adoi%2F10.1147%2Frd.285.0613&rft.aulast=Linsker&rft.aufirst=Ralph&rft_id=http%3A%2F%2Fwww.research.ibm.com%2Fjournal%2Frd%2F285%2Fibmrd2805N.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=5" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSchefferLavagnoMartin2006" class="citation book cs1">Scheffer, Louis K.; Lavagno, Luciano; Martin, Grant (2006). "Chapter 8: <i>Routing</i>". <i>Electronic Design Automation For Integrated Circuits Handbook</i>. Vol. II. Boca Raton, FL, USA: <a href="/wiki/CRC_Press" title="CRC Press">CRC Press</a> / <a href="/wiki/Taylor_%26_Francis" title="Taylor & Francis">Taylor & Francis</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-8493-3096-4" title="Special:BookSources/978-0-8493-3096-4"><bdi>978-0-8493-3096-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Chapter+8%3A+Routing&rft.btitle=Electronic+Design+Automation+For+Integrated+Circuits+Handbook&rft.place=Boca+Raton%2C+FL%2C+USA&rft.pub=CRC+Press+%2F+Taylor+%26+Francis&rft.date=2006&rft.isbn=978-0-8493-3096-4&rft.aulast=Scheffer&rft.aufirst=Louis+K.&rft.au=Lavagno%2C+Luciano&rft.au=Martin%2C+Grant&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARouting+%28electronic+design+automation%29" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Routing_(electronic_design_automation)&action=edit&section=6" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external free" href="http://www.eecs.northwestern.edu/~haizhou/357/lec6.pdf">http://www.eecs.northwestern.edu/~haizhou/357/lec6.pdf</a></li> <li><a rel="nofollow" class="external free" href="http://www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/10-grid-routing.pdf">http://www.facweb.iitkgp.ernet.in/~isg/CAD/SLIDES/10-grid-routing.pdf</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output 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title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a class="mw-selflink selflink">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div 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