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Logic synthesis - Wikipedia
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<span>Commercial tools</span> </div> </a> <ul id="toc-Commercial_tools-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Logic_elements" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Logic_elements"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Logic elements</span> </div> </a> <ul id="toc-Logic_elements-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-High-level_or_behavioral" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#High-level_or_behavioral"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>High-level or behavioral</span> </div> </a> <ul id="toc-High-level_or_behavioral-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multi-level_logic_minimization" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Multi-level_logic_minimization"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Multi-level logic minimization</span> </div> </a> <ul id="toc-Multi-level_logic_minimization-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" 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href="https://bn.wikipedia.org/wiki/%E0%A6%B2%E0%A6%9C%E0%A6%BF%E0%A6%95_%E0%A6%A1%E0%A6%BF%E0%A6%9C%E0%A6%BE%E0%A6%87%E0%A6%A8" title="লজিক ডিজাইন – Bangla" lang="bn" hreflang="bn" data-title="লজিক ডিজাইন" data-language-autonym="বাংলা" data-language-local-name="Bangla" class="interlanguage-link-target"><span>বাংলা</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Logiksynthese" title="Logiksynthese – German" lang="de" hreflang="de" data-title="Logiksynthese" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/%CE%9B%CE%BF%CE%B3%CE%B9%CE%BA%CE%AE_%CE%A3%CF%87%CE%B5%CE%B4%CE%AF%CE%B1%CF%83%CE%B7" title="Λογική Σχεδίαση – Greek" lang="el" hreflang="el" data-title="Λογική Σχεδίαση" data-language-autonym="Ελληνικά" data-language-local-name="Greek" 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href="https://fi.wikipedia.org/wiki/Logiikkasynteesi" title="Logiikkasynteesi – Finnish" lang="fi" hreflang="fi" data-title="Logiikkasynteesi" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%A1%D0%B8%D0%BD%D1%82%D0%B5%D0%B7_%D0%BB%D0%BE%D0%B3%D1%96%D0%BA%D0%B8" title="Синтез логіки – Ukrainian" lang="uk" hreflang="uk" data-title="Синтез логіки" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/%E9%80%BB%E8%BE%91%E7%BB%BC%E5%90%88" title="逻辑综合 – Wu" lang="wuu" hreflang="wuu" data-title="逻辑综合" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li 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</div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Process by which desired circuit behavior is turned into a schematic of logic gates</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div 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href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/Logic_synthesis" title="Special:EditPage/Logic synthesis">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and removed.<br /><small><span class="plainlinks"><i>Find sources:</i> <a rel="nofollow" class="external text" href="https://www.google.com/search?as_eq=wikipedia&q=%22Logic+synthesis%22">"Logic synthesis"</a> – <a rel="nofollow" class="external text" href="https://www.google.com/search?tbm=nws&q=%22Logic+synthesis%22+-wikipedia&tbs=ar:1">news</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?&q=%22Logic+synthesis%22&tbs=bkt:s&tbm=bks">newspapers</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?tbs=bks:1&q=%22Logic+synthesis%22+-wikipedia">books</a> <b>·</b> <a rel="nofollow" class="external text" href="https://scholar.google.com/scholar?q=%22Logic+synthesis%22">scholar</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.jstor.org/action/doBasicSearch?Query=%22Logic+synthesis%22&acc=on&wc=on">JSTOR</a></span></small></span> <span class="date-container"><i>(<span class="date">January 2013</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p> In <a href="/wiki/Computer_engineering" title="Computer engineering">computer engineering</a>, <b>logic synthesis</b> is a process by which an abstract specification of desired <a href="/wiki/Circuit_(electronics)" class="mw-redirect" title="Circuit (electronics)">circuit</a> behavior, typically at <a href="/wiki/Register_transfer_level" class="mw-redirect" title="Register transfer level">register transfer level</a> (RTL), is turned into a design implementation in terms of <a href="/wiki/Logic_gates" class="mw-redirect" title="Logic gates">logic gates</a>, typically by a <a href="/wiki/Computer_program" title="Computer program">computer program</a> called a <i>synthesis tool</i>. Common examples of this process include synthesis of designs specified in <a href="/wiki/Hardware_Description_Language" class="mw-redirect" title="Hardware Description Language">hardware description languages</a>, including <a href="/wiki/VHDL" title="VHDL">VHDL</a> and <a href="/wiki/Verilog" title="Verilog">Verilog</a>.<sup id="cite_ref-Verilog_2005_1-0" class="reference"><a href="#cite_note-Verilog_2005-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Some synthesis tools generate <a href="/wiki/Bitstream" title="Bitstream">bitstreams</a> for <a href="/wiki/Programmable_logic_device" title="Programmable logic device">programmable logic devices</a> such as <a href="/wiki/Programmable_array_logic" class="mw-redirect" title="Programmable array logic">PALs</a> or <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGAs</a>, while others target the creation of <a href="/wiki/ASIC" class="mw-redirect" title="ASIC">ASICs</a>. Logic synthesis is one step in circuit design in the <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a>, the others are <a href="/wiki/Place_and_route" title="Place and route">place and route</a> and <a href="/wiki/Verification_and_validation" title="Verification and validation">verification and validation</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The roots of logic synthesis can be traced to the treatment of logic by <a href="/wiki/George_Boole" title="George Boole">George Boole</a> (1815 to 1864), in what is now termed <a href="/wiki/Boolean_algebra_(logic)" class="mw-redirect" title="Boolean algebra (logic)">Boolean algebra</a>. In 1938, <a href="/wiki/Claude_Elwood_Shannon" class="mw-redirect" title="Claude Elwood Shannon">Claude Shannon</a> showed that the two-valued <a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a> can describe the operation of switching circuits. In the early days, <b>logic design</b> involved manipulating the <a href="/wiki/Truth_table" title="Truth table">truth table</a> representations as <a href="/wiki/Karnaugh_map" title="Karnaugh map">Karnaugh maps</a>. The Karnaugh map-based minimization of logic is guided by a set of rules on how entries in the maps can be combined. A human designer can typically only work with Karnaugh maps containing up to four to six variables. </p><p>The first step toward automation of <a href="/wiki/Logic_minimization" class="mw-redirect" title="Logic minimization">logic minimization</a> was the introduction of the <a href="/wiki/Quine%E2%80%93McCluskey_algorithm" title="Quine–McCluskey algorithm">Quine–McCluskey algorithm</a> that could be implemented on a computer. This exact minimization technique presented the notion of prime implicants and minimum cost covers that would become the cornerstone of <a href="/wiki/Two-level_minimization" class="mw-redirect" title="Two-level minimization">two-level minimization</a>. Nowadays, the much more efficient <a href="/wiki/Espresso_heuristic_logic_minimizer" title="Espresso heuristic logic minimizer">Espresso heuristic logic minimizer</a> has become the standard tool for this operation.<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="This correctly describes the situation around 1995. We need to expand this to include the changes of the past twenty years. (May 2017)">needs update</span></a></i>]</sup> Another area of early research was in state minimization and encoding of <a href="/wiki/Finite-state_machine" title="Finite-state machine">finite-state machines</a> (FSMs), a task that was the bane of designers. The applications for logic synthesis lay primarily in digital computer design. Hence, <a href="/wiki/IBM" title="IBM">IBM</a> and <a href="/wiki/Bell_Labs" title="Bell Labs">Bell Labs</a> played a pivotal role in the early automation of logic synthesis. The evolution from <a href="/wiki/Discrete_logic" class="mw-redirect" title="Discrete logic">discrete logic</a> components to <a href="/wiki/Programmable_logic_array" title="Programmable logic array">programmable logic arrays</a> (PLAs) hastened the need for efficient two-level minimization, since minimizing terms in a two-level representation reduces the area in a PLA. </p><p>Two-level logic circuits are of limited importance in a <a href="/wiki/Very-large-scale_integration" title="Very-large-scale integration">very-large-scale integration</a> (VLSI) design; most designs use multiple levels of logic. Almost any circuit representation in RTL or Behavioural Description is a multi-level representation. An early system that was used to design multilevel circuits was LSS from IBM. It used local transformations to simplify logic. Work on LSS and the Yorktown Silicon Compiler spurred rapid research progress in logic synthesis in the 1980s. Several universities contributed by making their research available to the public, most notably SIS from <a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a>, RASP from <a href="/wiki/University_of_California,_Los_Angeles" title="University of California, Los Angeles">University of California, Los Angeles</a> and BOLD from <a href="/wiki/University_of_Colorado,_Boulder" class="mw-redirect" title="University of Colorado, Boulder">University of Colorado, Boulder</a>. Within a decade, the technology migrated to commercial logic synthesis products offered by electronic design automation companies. </p> <div class="mw-heading mw-heading2"><h2 id="Commercial_tools">Commercial tools</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=2" title="Edit section: Commercial tools"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The leading developers and providers of logic synthesis software packages are <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a>, <a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a>, and <a href="/wiki/Siemens" title="Siemens">Siemens</a>. Their synthesis tools are Synopsys Design Compiler, Cadence First Encounter and Siemens Precision RTL. </p> <div class="mw-heading mw-heading2"><h2 id="Logic_elements">Logic elements</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=3" title="Edit section: Logic elements"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><i>Logic design</i> is a step in the standard design cycle in which the <a href="/wiki/Functional_design" title="Functional design">functional design</a> of an <a href="/wiki/Electronic_circuit" title="Electronic circuit">electronic circuit</a> is converted into the representation which captures <a href="/wiki/Boolean_algebra_(logic)" class="mw-redirect" title="Boolean algebra (logic)">logic operations</a>, <a href="/wiki/Arithmetic_operations" class="mw-redirect" title="Arithmetic operations">arithmetic operations</a>, <a href="/wiki/Control_flow" title="Control flow">control flow</a>, etc. A common output of this step is <a href="/wiki/RTL_description" class="mw-redirect" title="RTL description">RTL description</a>. Logic design is commonly followed by the <a href="/wiki/Circuit_design" title="Circuit design">circuit design</a> step. In modern <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a> parts of the logical design may be automated using <a href="/wiki/High-level_synthesis" title="High-level synthesis">high-level synthesis</a> tools based on the behavioral description of the circuit.<sup id="cite_ref-Sherwani_1999_2-0" class="reference"><a href="#cite_note-Sherwani_1999-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Baops.gif" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/43/Baops.gif/450px-Baops.gif" decoding="async" width="450" height="339" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/43/Baops.gif/675px-Baops.gif 1.5x, //upload.wikimedia.org/wikipedia/commons/4/43/Baops.gif 2x" data-file-width="787" data-file-height="593" /></a><figcaption>Various representations of Boolean operations</figcaption></figure> <p>Logic operations usually consist of Boolean AND, OR, XOR and NAND operations, and are the most basic forms of operations in an electronic circuit. Arithmetic operations are usually implemented with the use of logic operators. </p> <div class="mw-heading mw-heading2"><h2 id="High-level_or_behavioral">High-level or behavioral</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=4" title="Edit section: High-level or behavioral"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></div> <p>With a goal of increasing designer productivity, research efforts on the synthesis of circuits specified at the behavioral level have led to the emergence of commercial solutions in 2004,<sup id="cite_ref-EETimes_2017_3-0" class="reference"><a href="#cite_note-EETimes_2017-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> which are used for complex ASIC and FPGA design. These tools automatically synthesize circuits specified using high-level languages, like ANSI C/C++ or SystemC, to a register transfer level (RTL) specification, which can be used as input to a gate-level logic synthesis flow.<sup id="cite_ref-EETimes_2017_3-1" class="reference"><a href="#cite_note-EETimes_2017-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Using high-level synthesis, also known as ESL synthesis, the allocation of work to clock cycles and across structural components, such as floating-point ALUs, is done by the compiler using an optimisation procedure, whereas with RTL logic synthesis (even from behavioural Verilog or VHDL, where a thread of execution can make multiple reads and writes to a variable within a clock cycle) those allocation decisions have already been made. </p> <div class="mw-heading mw-heading2"><h2 id="Multi-level_logic_minimization">Multi-level logic minimization</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=5" title="Edit section: Multi-level logic minimization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Logic_optimization" title="Logic optimization">Logic optimization</a> and <a href="/wiki/Circuit_minimization" class="mw-redirect" title="Circuit minimization">Circuit minimization</a></div> <p>Typical practical implementations of a logic function utilize a multi-level network of logic elements. Starting from an RTL description of a design, the synthesis tool constructs a corresponding multilevel <a href="/wiki/Boolean_network" title="Boolean network">Boolean network</a>. </p><p>Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed. The typical cost function during technology-independent optimizations is total <a href="/wiki/Propositional_formula#Literal.2C_term_and_alterm" title="Propositional formula">literal</a> count of the factored representation of the logic function (which correlates quite well with circuit area). </p><p>Finally, technology-dependent optimization transforms the technology-independent circuit into a network of gates in a given technology. The simple cost estimates are replaced by more concrete, implementation-driven estimates during and after technology mapping. Mapping is constrained by factors such as the available gates (logic functions) in the technology library, the drive sizes for each gate, and the delay, <a href="/wiki/Electric_power" title="Electric power">power</a>, and area characteristics of each gate. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=6" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Silicon_compiler" title="Silicon compiler">Silicon compiler</a></li> <li><a href="/wiki/Binary_decision_diagram" title="Binary decision diagram">Binary decision diagram</a></li> <li><a href="/wiki/Functional_verification" title="Functional verification">Functional verification</a></li> <li><a href="/wiki/Boolean_differential_calculus" title="Boolean differential calculus">Boolean differential calculus</a></li> <li><a href="/wiki/Synthesis_of_Integral_Design" class="mw-redirect" title="Synthesis of Integral Design">Synthesis of Integral Design</a> by <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">DEC</a>, a 1980s tool used to design <a href="/wiki/VAX_9000" title="VAX 9000">VAX 9000</a> mainframe CPUs and others ICs</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=7" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-Verilog_2005-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-Verilog_2005_1-0">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-884-complex-digital-systems-spring-2005/lecture-notes/l05_synthesis.pdf">"Synthesis:Verilog to Gates"</a> <span class="cs1-format">(PDF)</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Synthesis%3AVerilog+to+Gates&rft_id=https%3A%2F%2Focw.mit.edu%2Fcourses%2Felectrical-engineering-and-computer-science%2F6-884-complex-digital-systems-spring-2005%2Flecture-notes%2Fl05_synthesis.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></span> </li> <li id="cite_note-Sherwani_1999-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Sherwani_1999_2-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNaveed_A._Sherwani1999" class="citation book cs1">Naveed A. Sherwani (1999). <i>Algorithms for VLSI physical design automation</i> (3rd ed.). Kluwer Academic Publishers. p. 4. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7923-8393-2" title="Special:BookSources/978-0-7923-8393-2"><bdi>978-0-7923-8393-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Algorithms+for+VLSI+physical+design+automation&rft.pages=4&rft.edition=3rd&rft.pub=Kluwer+Academic+Publishers&rft.date=1999&rft.isbn=978-0-7923-8393-2&rft.au=Naveed+A.+Sherwani&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></span> </li> <li id="cite_note-EETimes_2017-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-EETimes_2017_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-EETimes_2017_3-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">EETimes: <a rel="nofollow" class="external text" href="http://archives.eetimes.com/high-level-synthesis-rollouts-enable-esl/110436.html">High-level synthesis rollouts enable ESL</a><sup class="noprint Inline-Template"><span style="white-space: nowrap;">[<i><a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot"><span title=" Dead link tagged May 2017">permanent dead link</span></a></i><span style="visibility:hidden; color:transparent; padding-left:2px">‍</span>]</span></sup></span> </li> </ol></div></div> <ul><li><i>Electronic Design Automation For Integrated Circuits Handbook</i>, by Lavagno, Martin, and Scheffer, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-8493-3096-3" title="Special:BookSources/0-8493-3096-3">0-8493-3096-3</a> A survey of the field of <a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a>. The above summary was derived, with permission, from Volume 2, Chapter 2, <i>Logic Synthesis</i> by Sunil Khatri and Narendra Shenoy.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=8" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBurgunGreinerPrado_Lopes_Eudes1994" class="citation journal cs1">Burgun, Luc; Greiner, Alain; Prado Lopes Eudes (October 1994). "A Consistent Approach in Logic Synthesis for FPGA Architectures". <i>Proceedings of the International Conference on ASIC (ASICON)</i>. Pekin: 104–107.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Proceedings+of+the+International+Conference+on+ASIC+%28ASICON%29&rft.atitle=A+Consistent+Approach+in+Logic+Synthesis+for+FPGA+Architectures&rft.pages=104-107&rft.date=1994-10&rft.aulast=Burgun&rft.aufirst=Luc&rft.au=Greiner%2C+Alain&rft.au=Prado+Lopes+Eudes&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJiangDevadas2009" class="citation book cs1">Jiang, Jie-Hong "Roland"; Devadas, Srinivas (2009). "Chapter 6: Logic synthesis in a nutshell". In Wang, Laung-Terng; Chang, Yao-Wen; Cheng, Kwang-Ting (eds.). <i>Electronic design automation: synthesis, verification, and test</i>. Morgan Kaufmann. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-374364-0" title="Special:BookSources/978-0-12-374364-0"><bdi>978-0-12-374364-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Chapter+6%3A+Logic+synthesis+in+a+nutshell&rft.btitle=Electronic+design+automation%3A+synthesis%2C+verification%2C+and+test&rft.pub=Morgan+Kaufmann&rft.date=2009&rft.isbn=978-0-12-374364-0&rft.aulast=Jiang&rft.aufirst=Jie-Hong+%22Roland%22&rft.au=Devadas%2C+Srinivas&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHachtelSomenzi2006" class="citation book cs1">Hachtel, Gary D.; Somenzi, Fabio (2006) [1996]. <i>Logic Synthesis and Verification Algorithms</i>. <a href="/wiki/Springer_Science_%26_Business_Media" class="mw-redirect" title="Springer Science & Business Media">Springer Science & Business Media</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/0-7923-9746-0" title="Special:BookSources/0-7923-9746-0"><bdi>0-7923-9746-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Logic+Synthesis+and+Verification+Algorithms&rft.pub=Springer+Science+%26+Business+Media&rft.date=2006&rft.isbn=0-7923-9746-0&rft.aulast=Hachtel&rft.aufirst=Gary+D.&rft.au=Somenzi%2C+Fabio&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHassounSasao2002" class="citation book cs1"><a href="/wiki/Soha_Hassoun" title="Soha Hassoun">Hassoun, Soha</a>; Sasao, Tsutomu, eds. (2002). <i>Logic synthesis and verification</i>. Kluwer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7923-7606-4" title="Special:BookSources/978-0-7923-7606-4"><bdi>978-0-7923-7606-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Logic+synthesis+and+verification&rft.pub=Kluwer&rft.date=2002&rft.isbn=978-0-7923-7606-4&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPerkowskiGrygiel1995" class="citation book cs1">Perkowski, Marek A.; Grygiel, Stanislaw (1995-11-20). "6. Historical Overview of the Research on Decomposition". <a rel="nofollow" class="external text" href="http://web.cecs.pdx.edu/~mperkows/=PUBLICATIONS/PER/G1995/survey.pdf"><i>A Survey of Literature on Function Decomposition</i></a> <span class="cs1-format">(PDF)</span>. Version IV. Functional Decomposition Group, Department of Electrical Engineering, Portland University, Portland, Oregon, USA. <a href="/wiki/CiteSeerX_(identifier)" class="mw-redirect" title="CiteSeerX (identifier)">CiteSeerX</a> <span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.64.1129">10.1.1.64.1129</a></span>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210328181709/http://web.cecs.pdx.edu/~mperkows/=PUBLICATIONS/PER/G1995/survey.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2021-03-28<span class="reference-accessdate">. Retrieved <span class="nowrap">2021-03-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=6.+Historical+Overview+of+the+Research+on+Decomposition&rft.btitle=A+Survey+of+Literature+on+Function+Decomposition&rft.series=Version+IV&rft.pub=Functional+Decomposition+Group%2C+Department+of+Electrical+Engineering%2C+Portland+University%2C+Portland%2C+Oregon%2C+USA&rft.date=1995-11-20&rft_id=https%3A%2F%2Fciteseerx.ist.psu.edu%2Fviewdoc%2Fsummary%3Fdoi%3D10.1.1.64.1129%23id-name%3DCiteSeerX&rft.aulast=Perkowski&rft.aufirst=Marek+A.&rft.au=Grygiel%2C+Stanislaw&rft_id=http%3A%2F%2Fweb.cecs.pdx.edu%2F~mperkows%2F%3DPUBLICATIONS%2FPER%2FG1995%2Fsurvey.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span> (188 pages)</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFStankovićSasaoAstola2001" class="citation web cs1 cs1-prop-interwiki-linked-name"><a href="https://de.wikipedia.org/wiki/Radomir_S._Stankovi%C4%87" class="extiw" title="de:Radomir S. Stanković">Stanković, Radomir S.</a> <span class="cs1-format">[in German]</span>; Sasao, Tsutomu; <a href="https://fi.wikipedia.org/wiki/Jaakko_Tapio_Astola" class="extiw" title="fi:Jaakko Tapio Astola">Astola, Jaakko Tapio</a> <span class="cs1-format">[in Finnish]</span> (August 2001). <a rel="nofollow" class="external text" href="http://ticsp.cs.tut.fi/images/a/a5/Stari-radovi-report.pdf">"Publications in the First Twenty Years of Switching Theory and Logic Design"</a> <span class="cs1-format">(PDF)</span>. Tampere International Center for Signal Processing (TICSP) Series. Tampere University of Technology / TTKK, Monistamo, Finland. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1456-2774">1456-2774</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:62319288">62319288</a>. #14. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170809064702/http://ticsp.cs.tut.fi/images/a/a5/Stari-radovi-report.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on 2017-08-09<span class="reference-accessdate">. Retrieved <span class="nowrap">2021-03-28</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Publications+in+the+First+Twenty+Years+of+Switching+Theory+and+Logic+Design&rft.place=Tampere+University+of+Technology+%2F+TTKK%2C+Monistamo%2C+Finland&rft.series=Tampere+International+Center+for+Signal+Processing+%28TICSP%29+Series&rft.date=2001-08&rft.issn=1456-2774&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A62319288%23id-name%3DS2CID&rft.aulast=Stankovi%C4%87&rft.aufirst=Radomir+S.&rft.au=Sasao%2C+Tsutomu&rft.au=Astola%2C+Jaakko+Tapio&rft_id=http%3A%2F%2Fticsp.cs.tut.fi%2Fimages%2Fa%2Fa5%2FStari-radovi-report.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ALogic+synthesis" class="Z3988"></span> (4+60 pages)</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Logic_synthesis&action=edit&section=9" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Commons-logo.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/12px-Commons-logo.svg.png" decoding="async" width="12" height="16" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/18px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/24px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></a></span> Media related to <a href="https://commons.wikimedia.org/wiki/Category:Logic_design" class="extiw" title="commons:Category:Logic design">Logic design</a> at Wikimedia Commons</li></ul> <div class="navbox-styles"><style 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class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell 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href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a class="mw-selflink selflink">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> 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