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vector-toc-level-3"> <a class="vector-toc-link" href="#A-Link_Express"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.2</span> <span>A-Link Express</span> </div> </a> <ul id="toc-A-Link_Express-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Fusion_controller_hubs_(FCH)" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Fusion_controller_hubs_(FCH)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Fusion controller hubs (FCH)</span> </div> </a> <ul id="toc-Fusion_controller_hubs_(FCH)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-AM4_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#AM4_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>AM4 chipsets</span> </div> </a> <ul id="toc-AM4_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-TR4_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#TR4_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>TR4 chipsets</span> </div> </a> <ul id="toc-TR4_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-sTRX4_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#sTRX4_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>sTRX4 chipsets</span> </div> </a> <ul id="toc-sTRX4_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-sWRX8_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#sWRX8_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>sWRX8 chipsets</span> </div> </a> <ul id="toc-sWRX8_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-AM5_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#AM5_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>AM5 chipsets</span> </div> </a> <ul id="toc-AM5_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-sTR5_chipsets" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#sTR5_chipsets"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>sTR5 chipsets</span> </div> </a> <ul id="toc-sTR5_chipsets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown 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<div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=Fusion_controller_hub&redirect=no" class="mw-redirect" title="Fusion controller hub">Fusion controller hub</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><p class="mw-empty-elt"> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_Chipset_Logo_2011-2013.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/16/AMD_Chipset_Logo_2011-2013.png/220px-AMD_Chipset_Logo_2011-2013.png" decoding="async" width="220" height="186" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/16/AMD_Chipset_Logo_2011-2013.png/330px-AMD_Chipset_Logo_2011-2013.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/16/AMD_Chipset_Logo_2011-2013.png/440px-AMD_Chipset_Logo_2011-2013.png 2x" data-file-width="450" data-file-height="380" /></a><figcaption>AMD chipsets logo</figcaption></figure> <p>This is an overview of <a href="/wiki/Chipset" title="Chipset">chipsets</a> sold under the <a href="/wiki/AMD" title="AMD">AMD</a> brand, manufactured before May 2004 by the company itself, before the adoption of <a href="/wiki/AMD_mobile_platform#Open_platform_approach" title="AMD mobile platform">open platform approach</a> as well as chipsets manufactured by <a href="/wiki/ATI_Technologies" title="ATI Technologies">ATI Technologies</a> after October 2006 as the completion of the ATI acquisition. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="North-_and_Southbridges">North- and Southbridges</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=1" title="Edit section: North- and Southbridges"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_Chipset_Logo_2000.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_Chipset_Logo_2000.png/220px-AMD_Chipset_Logo_2000.png" decoding="async" width="220" height="118" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_Chipset_Logo_2000.png/330px-AMD_Chipset_Logo_2000.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_Chipset_Logo_2000.png/440px-AMD_Chipset_Logo_2000.png 2x" data-file-width="462" data-file-height="247" /></a><figcaption>AMD Chipset logo, in use from around 2000 till 2011</figcaption></figure> <div class="mw-heading mw-heading3"><h3 id="Northbridges">Northbridges</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=2" title="Edit section: Northbridges"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="AMD-xxx">AMD-xxx</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=3" title="Edit section: AMD-xxx"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Code name </th> <th>Released </th> <th>CPU support </th> <th><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fab</a> (<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>) </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a>/<a href="/wiki/HyperTransport" title="HyperTransport">HT</a> (MHz) </th> <th>Southbridge </th> <th>Features / Notes </th></tr> <tr> <th>AMD-640 chipset </th> <td>AMD-640 </td> <td>1997 </td> <td><a href="/wiki/AMD_K6" title="AMD K6">K6</a>, <p><a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a> </p> </td> <td rowspan="6">? </td> <td>66 <p>(FSB) </p> </td> <td>AMD-645 </td> <td align="left">AMD licensed <a href="/wiki/VIA_Technologies" title="VIA Technologies">VIA Technologies</a>' <a href="/wiki/VIA_chipsets" class="mw-redirect" title="VIA chipsets">Apollo VP2/97</a> </td></tr> <tr> <th>AMD-750 chipset </th> <td>AMD-751 </td> <td>1999 </td> <td><a href="/wiki/Athlon" title="Athlon">Athlon</a>, <a href="/wiki/Duron" title="Duron">Duron</a> <p>(<a href="/wiki/Slot_A" title="Slot A">Slot A</a>, <a href="/wiki/Socket_A" title="Socket A">Socket A</a>), <a href="/wiki/Alpha_21264" title="Alpha 21264">Alpha 21264</a> </p> </td> <td>100 <p>(FSB) </p> </td> <td>AMD-756, <p>VIA-VT82C686A </p> </td> <td align="left">AGP 2×, SDRAM<br /><i>Irongate</i> chipset family; early steppings had issues with AGP 2×; drivers often limited support to AGP 1×; later fixed with "super bypass" memory access adjustment.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>AMD-760 chipset </th> <td>AMD-761 </td> <td>Nov 2000 </td> <td>Athlon, Athlon XP, Duron <p>(<a href="/wiki/Socket_A" title="Socket A">Socket A</a>), <a href="/wiki/Alpha_21264" title="Alpha 21264">Alpha 21264</a> </p> </td> <td rowspan="3">133 <p>(FSB) </p> </td> <td>AMD-766, <p>VIA-T82C686B </p> </td> <td align="left">AGP 4×, DDR SDRAM </td></tr> <tr> <th>AMD-760MP chipset </th> <td rowspan="2">AMD-762 </td> <td rowspan="2">May 2001 </td> <td rowspan="2"><a href="/wiki/Athlon_MP" class="mw-redirect" title="Athlon MP">Athlon MP</a> </td> <td>AMD-766 </td> <td align="left">AGP 4× </td></tr> <tr> <th>AMD-760MPX chipset </th> <td>AMD-768 </td> <td align="left">AGP 4×, <a href="/wiki/Hardware_random_number_generator" title="Hardware random number generator">Hardware RNG</a><br />Most initial boards shipped without USB headers due to a fault with the integrated USB controller. Manufacturers included PCI USB cards to cover this shortcoming. A later refresh of the chipset had the USB problem remedied.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>AMD-8000 series chipset </th> <td>AMD-8111 </td> <td>Apr 2004 </td> <td><a href="/wiki/Opteron" title="Opteron">Opteron</a> </td> <td>800 <p>(HT 1.x) </p> </td> <td>AMD-8131 <p>AMD-8132 </p> </td> <td align="left">Hardware RNG </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="A-Link_Express_II">A-Link Express II</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=4" title="Edit section: A-Link Express II"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A-Link Express and A-Link Express II are essentially <a href="/wiki/PCI_Express#PCI_Express_1.1" title="PCI Express">PCIe 1.1</a> x4 lanes. </p><p>See <a href="/wiki/Comparison_of_ATI_Chipsets" class="mw-redirect" title="Comparison of ATI Chipsets">Comparison of ATI Chipsets</a> for the comparison of chipsets sold under the <a href="/wiki/ATI_Technologies" title="ATI Technologies">ATI</a> brand for AMD processors, before AMD's acquisition of ATI. </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Codename </th> <th>Released </th> <th>CPU support </th> <th><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fab</a> (<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>) </th> <th><a href="/wiki/HyperTransport" title="HyperTransport">HT</a> (MHz) </th> <th><a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">IGP</a> </th> <th><a href="/wiki/ATI_CrossFire" class="mw-redirect" title="ATI CrossFire">CrossFire</a> </th> <th>Southbridge </th> <th>Features / Notes </th></tr> <tr> <th>AMD <a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">480X</a> chipset<br />(originally CrossFire Xpress 1600) </th> <td>RD480 </td> <td>Oct 2006 </td> <td><a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a>,<br />Sempron </td> <td>110 </td> <td rowspan="3">1000 <p>(HT 2.0) </p> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x8 + x8 </td> <td>SB600,<br /><a href="/wiki/ULi" class="mw-redirect" title="ULi">ULi</a>-M1575</td> <td rowspan="3" align="left">? </td></tr> <tr> <th>AMD <a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">570X/550X</a> chipset<br />(originally CrossFire Xpress 3100) </th> <td>RD570 </td> <td>Jun 2007 </td> <td rowspan="2"><a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a>,<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Athlon 64,<br />Sempron </td> <td rowspan="2">? </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x8 </td> <td rowspan="2">SB600 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">580X</a> chipset<br />(originally CrossFire Xpress 3200) </th> <td>RD580 </td> <td>Oct 2006 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x16 </td></tr> <tr> <th colspan="10"> </th></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">690V</a> chipset </th> <td>RS690C </td> <td rowspan="6">Feb 2007 </td> <td>Athlon 64,<br />Sempron </td> <td rowspan="6">80 </td> <td rowspan="2">1000 <p>(HT 2.0) </p> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1200<br />(350MHz) </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="6">SB600 </td> <td align="left"><a href="/wiki/DirectX" title="DirectX">DirectX</a> 9.0, <a href="/wiki/AVIVO" class="mw-redirect" title="AVIVO">AVIVO</a>, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br />no <a href="/wiki/LVDS" class="mw-redirect" title="LVDS">LVDS</a> </td></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">690G</a> chipset </th> <td>RS690 </td> <td>Phenom, Athlon 64,<br /> Sempron </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1250<br />(400MHz) </td> <td align="left">DirectX 9.0, AVIVO, HDMI/HDCP </td></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">M690V</a> chipset </th> <td>RS690MC </td> <td rowspan="2"><a href="/wiki/Turion_64_X2" class="mw-redirect" title="Turion 64 X2">Turion 64 X2</a>,<br /><a href="/wiki/List_of_AMD_Turion_microprocessors#"Tyler"_(65_nm)" class="mw-redirect" title="List of AMD Turion microprocessors">Athlon 64 X2 mobile</a> </td> <td rowspan="4">800 <p>(HT 2.0) </p> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1200<br />(350 MHz) </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td align="left">DirectX 9.0, AVIVO, DVI, HDMI/HDCP,<br />no <a href="/wiki/LVDS" class="mw-redirect" title="LVDS">LVDS</a>, Powerplay 7.0 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">M690</a> chipset </th> <td>RS690M </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1250<br />(350 MHz) </td> <td align="left">DirectX 9.0, AVIVO, DVI/HDCP,<br />no HDMI, Powerplay 7.0 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">M690E</a> chipset </th> <td rowspan="2">RS690T </td> <td>Athlon Neo,<br />Mobile Sempron </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1250<br />(350Mhz) </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td align="left">DirectX 9.0, AVIVO, 2× <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br />Powerplay 7.0 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">M690T</a> chipset </th> <td><a href="/wiki/Turion_64_X2" class="mw-redirect" title="Turion 64 X2">Turion 64 X2</a>,<br /><a href="/wiki/List_of_AMD_Turion_microprocessors#"Tyler"_(65_nm)" class="mw-redirect" title="List of AMD Turion microprocessors">Athlon 64 X2 mobile</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon X1270<br />(400Mhz) </td> <td align="left">DirectX 9.0, AVIVO, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br />Powerplay 7.0 </td></tr> <tr> <th colspan="10"> </th></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#740" title="AMD 700 chipset series">740</a> chipset </th> <td>RX740 </td> <td rowspan="2">2008 </td> <td rowspan="6">Athlon 64,<br />Phenom,<br />Sempron </td> <td rowspan="3">55 </td> <td rowspan="2">1000 <p>(HT 2.0) </p> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2">SB600,<br />SB700,<br />SB750 </td> <td align="left">Single PCIe 1.1 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#740G" title="AMD 700 chipset series">740G</a> chipset </th> <td>RS740 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon 2100 </td> <td align="left">DirectX 9.0, AVIVO, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br />OR single PCIe 1.1 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#760G" title="AMD 700 chipset series">760G</a> chipset </th> <td>RS780L </td> <td>2009 </td> <td rowspan="7">2600 <p>(HT 3.0) </p> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon 3000 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid </td> <td>SB710 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10</a>, AVIVO HD, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br />OR single PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#770" title="AMD 700 chipset series">770</a> chipset </th> <td>RX780 </td> <td rowspan="5">2008 </td> <td>65 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>SB600,<br />SB700,<br />SB710,<br />SB750 </td> <td align="left">Single PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#780G/780V" title="AMD 700 chipset series">780V</a> chipset </th> <td>RS780C </td> <td rowspan="7">55 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon 3100 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2">SB700,<br />SB710,<br />SB750 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10</a>, AVIVO HD, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>,<br /><a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP,<br />OR single PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#780G/780V" title="AMD 700 chipset series">780G</a> chipset </th> <td>RS780I </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 3200 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10</a>, UVD+, <a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP, Side-port memory,<br />OR single PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#780G" title="AMD 700 chipset series">M780V</a> chipset </th> <td>RS780MC </td> <td rowspan="2">Mobile Turion,<br />Mobile Athlon,<br />Athlon Neo </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon 3100 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/AMD_700_chipset_series#PowerXpress" title="AMD 700 chipset series">PowerXpress</a><br /><a href="/w/index.php?title=Advanced_eXpress_I/O_Module&action=edit&redlink=1" class="new" title="Advanced eXpress I/O Module (page does not exist)">AXIOM</a>/<a href="/wiki/Mobile_PCI_Express_Module" title="Mobile PCI Express Module">MXM<br />module(s)</a> </td> <td rowspan="2">SB600,<br />SB700,<br />SB710 </td> <td rowspan="2" align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10</a>, UVD+,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>, <a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a>, <a href="/wiki/Video_Graphics_Array" title="Video Graphics Array">VGA</a>,<br />OR single PCIe 2.0 x16 <p><a href="/wiki/AMD_mobile_platform#Puma_platform_(2008)" title="AMD mobile platform">Puma Platform</a>, <a href="/wiki/AMD_700_chipset_series#PowerXpress" title="AMD 700 chipset series">PowerXpress</a> </p> </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#780G" title="AMD 700 chipset series">M780G</a> chipset </th> <td>RS780M </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 3200 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series#785G" title="AMD 700 chipset series">785G</a> chipset </th> <td>RS880 </td> <td>2009 </td> <td>Athlon 64,<br />Phenom,<br />Sempron </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4200 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid,<br />x16 + x4 </td> <td>SB710,<br />SB750,<br />SB810,<br />SB850 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br />Side-port memory,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP,<br />OR two PCIe 2.0 x16<br />TDP: 11 W (500 MHz), 3 W in PowerPlay </td></tr> <tr> <th>785E </th> <td>RS785E </td> <td colspan="2">? </td> <td>2200 <p>(HT 3.0) </p> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4200 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid </td> <td>SB810, SB850, SB820M </td> <td> </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">790GX</a> chipset </th> <td>RS780D </td> <td rowspan="2">2008 </td> <td rowspan="3">Athlon 64,<br />Phenom,<br />Sempron </td> <td rowspan="3">2600 <p>(HT 3.0) </p> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 3300 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid,<br />x8 + x8<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </td> <td>SB750 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10</a>, UVD+,<br />Side-port memory,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP,<br />OR two PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">790X</a> chipset </th> <td>RD780 </td> <td rowspan="2">65 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x8 + x8 </td> <td>SB600,<br />SB700,<br />SB750,<br />SB850 </td> <td align="left">Two PCIe 2.0 x16 </td></tr> <tr> <th>AMD <a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">790FX</a> chipset </th> <td>RD790 </td> <td>Nov 2007 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CrossFire X<br />(dual x16<br />or quad x8) </td> <td>SB600,<br />SB750,<br />SB850 </td> <td align="left">Up to four PCIe 2.0 x16<br />Support for <a href="/wiki/AMD_Quad_FX_platform" title="AMD Quad FX platform">AMD Quad FX platform</a> (<i>FASN8</i>),<br />Dual socket enthusiast platform with <a href="/wiki/Non-Uniform_Memory_Access" class="mw-redirect" title="Non-Uniform Memory Access">NUMA</a>,<br />optional single socket variant,<br />720-pin 1.1 <a href="/wiki/Volt" title="Volt">V</a> <a href="/wiki/Ball_Grid_Array" class="mw-redirect" title="Ball Grid Array">FC-BGA</a> </td></tr> <tr> <th>Model </th> <th>Codename </th> <th>Released </th> <th>CPU support </th> <th><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fab</a> (<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>) </th> <th><a href="/wiki/HyperTransport" title="HyperTransport">HT</a> (MHz) </th> <th><a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">IGP</a> </th> <th><a href="/wiki/ATI_CrossFire" class="mw-redirect" title="ATI CrossFire">CrossFire</a> </th> <th>Southbridge </th> <th>Features / Notes </th></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="A-Link_Express_III">A-Link Express III</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=5" title="Edit section: A-Link Express III"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A-Link Express III is essentially <a href="/wiki/PCI_Express#PCI_Express_2.0" title="PCI Express">PCIe 2.0</a> x4 lanes. </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Code<br />name </th> <th>Released </th> <th>CPU support </th> <th><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a><br />(<a href="/wiki/Nanometre" title="Nanometre">nm</a>) </th> <th><a href="/wiki/HyperTransport" title="HyperTransport">HT</a><br />(<a href="/wiki/Hertz" title="Hertz">MHz</a>) </th> <th><a href="/wiki/X86_virtualization#Hardware-assisted_virtualization" title="X86 virtualization">AMD-V</a><br />(<a href="/wiki/Hardware-assisted_virtualization" class="mw-redirect" title="Hardware-assisted virtualization">Hardware Virtualization</a>) </th> <th><a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">IGP</a> </th> <th><a href="/wiki/AMD_CrossFire" title="AMD CrossFire">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a><sup id="cite_ref-amd_sli_5-0" class="reference"><a href="#cite_note-amd_sli-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a><br />(<a href="/wiki/Watt" title="Watt">W</a>) </th> <th>Southbridge </th> <th>Features / Notes </th></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#870" title="AMD 800 chipset series">870</a> chipset </th> <td>RX880 </td> <td>2010 </td> <td>Phenom II,<br />Athlon 64,<br />Sempron </td> <td>65 </td> <td rowspan="7">2600<br />(HT 3.0) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid, x16 + x4 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="5">? </td> <td>SB850 </td> <td align="left">Single PCIe 2.0 x16 </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#880G" title="AMD 800 chipset series">880G</a> chipset </th> <td>RS880P </td> <td>Q4 2010 </td> <td>Phenom II,<br />Athlon II,<br />Sempron </td> <td rowspan="5">55 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4250 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>SB710,<br />SB750,<br />SB810,<br />SB850,<br />SB920,<br />SB950 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP,<br />OR single PCIe 2.0 x16<br />AM3+ socket support </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#880M" title="AMD 800 chipset series">880M</a> chipset </th> <td rowspan="3">RS880M </td> <td rowspan="5">Q2 2010 </td> <td>Mobile Turion II,<br />Mobile Athlon II,<br />Mobile Sempron </td> <td rowspan="3" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4200 </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/AMD_700_chipset_series#PowerXpress" title="AMD 700 chipset series">PowerXpress</a><br /><a href="/w/index.php?title=Advanced_eXpress_I/O_Module&action=edit&redlink=1" class="new" title="Advanced eXpress I/O Module (page does not exist)">AXIOM</a>/<a href="/wiki/Mobile_PCI_Express_Module" title="Mobile PCI Express Module">MXM<br />module(s)</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="3">SB820 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>, <a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a>, <a href="/wiki/Video_Graphics_Array" title="Video Graphics Array">VGA</a>,<br />sideport memory,<br />OR single PCI-E 2.0 x16 <p>Mobile Chipset, <a href="/wiki/AMD_mobile_platform#Tigris_platform_(2009)" title="AMD mobile platform"><i>Tigris</i></a> platform </p> </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#880M" title="AMD 800 chipset series">880M</a> chipset </th> <td>Athlon II Neo,<br />Turion II Neo </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4225 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>, <a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a>, <a href="/wiki/Video_Graphics_Array" title="Video Graphics Array">VGA</a>,<br />OR Single PCI-E 2.0 x16 <p>Mobile Chipset, <a href="/wiki/AMD_mobile_platform#Nile_platform_(2010)" title="AMD mobile platform"><i>Nile</i></a> platform </p> </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#880M" title="AMD 800 chipset series">880M</a> chipset </th> <td>Mobile Phenom II,<br />Mobile Turion II,<br />Mobile Athlon II,<br />Mobile Sempron<br />V-Series </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4250<br />Radeon HD 4270 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>, <a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a>, <a href="/wiki/Video_Graphics_Array" title="Video Graphics Array">VGA</a>,<br />OR single PCI-E 2.0 x16 <p>Mobile Chipset, <a href="/wiki/AMD_mobile_platform#Danube_platform_(2010)" title="AMD mobile platform"><i>Danube</i></a> platform </p> </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#890GX" title="AMD 800 chipset series">890GX</a> chipset </th> <td>RS880D </td> <td>Phenom II,<br />Athlon II,<br />Sempron </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Radeon HD 4290 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Hybrid,<br />x8 + x8 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>22 </td> <td>SB710,<br />SB750,<br />SB810,<br />SB850 </td> <td align="left"><a href="/wiki/Direct3D#Direct3D_10" title="Direct3D">DirectX 10.1</a>, UVD2,<br /><a href="/wiki/HDMI" title="HDMI">HDMI</a>/<a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a>, <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>/DPCP,<br /> Side-port memory,<br />OR two PCIe 2.0 x16 </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_800_chipset_series#890FX" title="AMD 800 chipset series">890FX</a> chipset </th> <td>RD890 </td> <td><i>Bulldozer</i>,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><br />Phenom II,<br />Athlon II,<br />Sempron </td> <td>65 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x16<br />or x8 quad </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>18 </td> <td>SB710,<br />SB750,<br />SB810,<br />SB850 </td> <td align="left">Four PCIe 2.0 x16 </td></tr> <tr> <th colspan="11"> </th></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_900_chipset_series#970" title="AMD 900 chipset series">970</a> chipset </th> <td>RX980 </td> <td rowspan="3">Q2 2011 </td> <td rowspan="3"><i>Bulldozer</i>, <i>Piledriver</i><br />Phenom II, Athlon II, Sempron, FX </td> <td rowspan="3">65 </td> <td>2400<br />(HT 3.0) </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x4 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>13.6 </td> <td rowspan="3">SB710,<br />SB750,<br />SB810,<br />SB850,<br />SB920,<br /> SB950 </td> <td align="left">Single PCIe 2.0 x16, <a href="/wiki/IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a> <p>AM3+ socket support </p> </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_900_chipset_series#990X" title="AMD 900 chipset series">990X</a> chipset </th> <td>RD980 </td> <td rowspan="2">2600<br />(HT 3.0) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x8 + x8 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x8 + x8 </td> <td>14 </td> <td align="left">Two PCIe 2.0 x16, <a href="/wiki/IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a> <p>AM3+ socket support </p> </td></tr> <tr> <th style="text-align: left">AMD <a href="/wiki/AMD_900_chipset_series#990FX" title="AMD 900 chipset series">990FX</a> chipset </th> <td>RD990 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x16<br />or x8 quad </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">x16 + x16<br />or x16 + x8 + x8<br />or x8 quad </td> <td>19.6 </td> <td align="left">Four PCIe 2.0 x16, <a href="/wiki/IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a> <p>AM3+ socket support </p> </td></tr> <tr> <th>Model </th> <th>Code<br />name </th> <th>Released </th> <th>CPU support </th> <th>Fab<br />(nm) </th> <th>HT<br />(MHz) </th> <th>AMD-V<br />(Hardware Virtualization) </th> <th>IGP </th> <th>CrossFire </th> <th>SLI </th> <th>TDP<br />(W) </th> <th>Southbridge </th> <th>Features / Notes </th></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Southbridges">Southbridges</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=6" title="Edit section: Southbridges"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="AMD-xxx_2">AMD-xxx</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=7" title="Edit section: AMD-xxx"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Codename </th> <th>Released </th> <th><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fab</a> (<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>) </th> <th><a href="/wiki/USB" title="USB">USB</a><br />2.0 + 1.1 </th> <th>Audio </th> <th><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA</a><sup>1</sup> </th> <th>Features / Notes </th></tr> <tr> <th>AMD 640 chipset </th> <td>AMD-645 </td> <td>1997 </td> <td> </td> <td> </td> <td> </td> <td>2 × ATA/33 </td> <td> </td></tr> <tr> <th>AMD 750 chipset </th> <td>AMD-756 </td> <td>1999 </td> <td> </td> <td rowspan="3">0 + 4 </td> <td> </td> <td>2 × ATA/66 </td> <td> </td></tr> <tr> <th>AMD 760 chipset </th> <td>AMD-766 </td> <td rowspan="2">2001 </td> <td> </td> <td> </td> <td rowspan="2">2 × ATA/100 </td> <td> </td></tr> <tr> <th>AMD 760MPX chipset </th> <td>AMD-768 </td> <td> </td> <td><a href="/wiki/AC%2797" title="AC'97">AC'97</a> </td> <td> </td></tr> <tr> <th colspan="8"> </th></tr> <tr> <th>Geode GX1 </th> <td>Geode CS5530 </td> <td> </td> <td> </td> <td> </td> <td rowspan="4">AC'97 </td> <td rowspan="2">2 × ATA/33 </td> <td rowspan="2" align="left"><a href="/wiki/Geode_(processor)#National_Semiconductor_Geode" title="Geode (processor)">National Semiconductor</a> release </td></tr> <tr> <th>Geode GXm<br />Geode GXLV </th> <td>Geode CS5530A </td> <td> </td> <td> </td> <td> </td></tr> <tr> <th>Geode GX </th> <td>Geode CS5535 </td> <td> </td> <td> </td> <td>0 + 4 </td> <td>2 × ATA/66 </td> <td> </td></tr> <tr> <th>Geode LX </th> <td>Geode CS5536 </td> <td> </td> <td> </td> <td>4 + 0 </td> <td>2 × ATA/100 </td> <td> </td></tr> <tr> <th colspan="8"> </th></tr> <tr> <th rowspan="2">AMD-8111<br /> nForce Professional<br /> ULi-1563 </th> <td>AMD-8131 </td> <td rowspan="3">2004 </td> <td rowspan="3"> </td> <td rowspan="3">4 + 2 </td> <td rowspan="3">AC'97 </td> <td rowspan="3">2 × ATA/133 </td> <td align="left"><a href="/wiki/PCI-X" title="PCI-X">PCI-X</a> </td></tr> <tr> <td>AMD-8132 </td> <td align="left"><a href="/wiki/PCI-X#PCI-X_2.0" title="PCI-X">PCI-X 2.0</a> </td></tr> <tr> <th>AMD-8151 </th> <td>AMD-8151 </td> <td align="left">AGP 8X </td></tr></tbody></table> <p><sup>1</sup> Parallel ATA, also known as Enhanced IDE supports up to 2 devices per channel. </p> <div class="mw-heading mw-heading4"><h4 id="A-Link_Express">A-Link Express</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=8" title="Edit section: A-Link Express"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support <a href="/wiki/ESATA" class="mw-redirect" title="ESATA">eSATA</a> implementations of available SATA channels.</li></ul> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Codename </th> <th>Released </th> <th><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fab</a> <p>(<a href="/wiki/Nanometer" class="mw-redirect" title="Nanometer">nm</a>) </p> </th> <th><a href="/wiki/SATA" title="SATA">SATA</a> </th> <th><a href="/wiki/USB" title="USB">USB</a><br />2.0 + 1.1 </th> <th><a href="/wiki/Parallel_ATA" title="Parallel ATA">Parallel ATA</a><sup>1</sup> </th> <th><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th><a href="/wiki/Network_interface_controller" title="Network interface controller">NIC</a> </th> <th><a href="/wiki/Integrated_circuit_packaging" title="Integrated circuit packaging">Package</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> <p>(<a href="/wiki/Watt" title="Watt">W</a>) </p> </th> <th>Features / Notes </th></tr> <tr> <th>AMD 480/570/580/690<br /> CrossFire Chipset </th> <td><b>SB600</b> </td> <td>2006 </td> <td rowspan="5">130 </td> <td>4 × 3 Gbit/s<br /> <a href="/wiki/AHCI" class="mw-redirect" title="AHCI">AHCI</a> 1.1 <a href="/wiki/SATA_Revision_2.0" class="mw-redirect" title="SATA Revision 2.0">SATA Revision 2.0</a> </td> <td>10 + 0 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">1 × ATA/133 </td> <td rowspan="4">0,1,10 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="5">548-pin<br /> <a href="/wiki/Ball_grid_array" title="Ball grid array">FC-BGA</a> </td> <td>4.0 </td> <td align="left"> </td></tr> <tr> <th rowspan="4"><a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">AMD 700 chipset series</a> </th> <td><b>SB700</b> </td> <td rowspan="2">Q1 2008 </td> <td rowspan="4">6 × 3 Gbit/s<br /> AHCI 1.1 <a href="/wiki/SATA_Revision_2.0" class="mw-redirect" title="SATA Revision 2.0">SATA Revision 2.0</a> </td> <td rowspan="4">12 + 2 </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">1 × ATA/133 </td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="4">4.5 </td> <td align="left"><a href="/wiki/Desktop_and_mobile_Architecture_for_System_Hardware" title="Desktop and mobile Architecture for System Hardware">DASH</a> 1.0 </td></tr> <tr> <td><b>SB700S</b> </td> <td align="left">DASH 1.0<br />Server southbridge </td></tr> <tr> <td><b>SB710</b> </td> <td rowspan="2">Q4 2008 </td> <td rowspan="2" align="left">DASH 1.0 </td></tr> <tr> <td><b>SB750</b> </td> <td>0,1,5,10 </td></tr> <tr> <th rowspan="3"><a href="/wiki/AMD_800_chipset_series" title="AMD 800 chipset series">AMD 800<br />chipset series</a> </th> <td><b>SB810</b> </td> <td rowspan="2">Q1 2010 </td> <td rowspan="5">65 </td> <td>6 × 3 Gbit/s<br /> AHCI 1.2 <a href="/wiki/SATA_Revision_2.0" class="mw-redirect" title="SATA Revision 2.0">SATA Revision 2.0</a> </td> <td rowspan="5">14 + 2 </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>0,1,10 </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td rowspan="5">605-pin<br />FC-BGA </td> <td rowspan="2">6.0 </td> <td rowspan="2" align="left"> </td></tr> <tr> <td><b>SB850</b> </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">6 × 6 Gbit/s<br />AHCI 1.2 <a href="/wiki/SATA_Revision_3.0" class="mw-redirect" title="SATA Revision 3.0">SATA Revision 3.0</a> </td> <td>0,1,5,10 </td></tr> <tr> <td><b>SB820M</b> </td> <td> </td> <td>0,1 </td> <td>3.4 - 5.3 </td> <td>mobile/embedded </td></tr> <tr> <th rowspan="2"><a href="/wiki/AMD_900_chipset_series" title="AMD 900 chipset series">AMD 900<br /> chipset series</a> </th> <td><b>SB920</b> </td> <td rowspan="2">May 30, 2011 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">6 × 6 Gbit/s<br /> AHCI 1.2 <a href="/wiki/SATA_Revision_3.0" class="mw-redirect" title="SATA Revision 3.0">SATA Revision 3.0</a> </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>0,1,10 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td rowspan="2">6.0 </td> <td rowspan="2" align="left"> </td></tr> <tr> <td><b>SB950</b></td> <td>0,1,5,10 </td></tr> <tr> <th>Model </th> <th>Codename </th> <th>Released </th> <th>Fab (nm) </th> <th>SATA </th> <th>USB<br />2.0 + 1.1 </th> <th>Parallel ATA<sup>1</sup> </th> <th>RAID </th> <th><a href="/wiki/Network_interface_controller" title="Network interface controller">NIC</a> </th> <th>Package </th> <th>TDP (W) </th> <th>Features / Notes </th></tr></tbody></table> <p><sup>1</sup> Parallel ATA, also known as Enhanced IDE supports up to 2 devices per channel. </p> <div class="mw-heading mw-heading2"><h2 id="Fusion_controller_hubs_(FCH)"><span id="Fusion_controller_hubs_.28FCH.29"></span><span class="anchor" id="FCH"></span> Fusion controller hubs (FCH)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=9" title="Edit section: Fusion controller hubs (FCH)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div><p> For AMD APU models from 2011 until 2016. AMD marketed their chipsets as Fusion Controller Hubs (FCH), implementing it across their product range in 2017 alongside the release of the Zen architecture. Before then, only APUs used FCHs, while their other CPUs still used a northbridge and southbridge. The Fusion Controller Hubs are similar in function to Intel's <a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">Platform Controller Hub</a>.</p><figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_FCH-A88X.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a4/AMD_FCH-A88X.jpg/220px-AMD_FCH-A88X.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a4/AMD_FCH-A88X.jpg/330px-AMD_FCH-A88X.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a4/AMD_FCH-A88X.jpg/440px-AMD_FCH-A88X.jpg 2x" data-file-width="1432" data-file-height="1432" /></a><figcaption>Fusion Controller Hub A88X</figcaption></figure> <p>AMD's FCH has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> However, since the release of the Zen architecture, there's still a component called a chipset which only handles relatively low speed I/O such as USB and SATA ports and connects to the CPU with a PCIe connection. In these systems all PCIe connections are routed directly to the CPU.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I/O. AMD server CPUs adopt a self contained <a href="/wiki/System_on_chip" class="mw-redirect" title="System on chip">system on chip</a> design instead which doesn't require a chipset.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th>Model </th> <th>Codename </th> <th><a href="/wiki/UMI_AMD" class="mw-redirect" title="UMI AMD">UMI</a> </th> <th><a href="/wiki/SATA" title="SATA">SATA</a> </th> <th><a href="/wiki/USB" title="USB">USB</a><br />3.0+2.0+1.1 </th> <th><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th><a href="/wiki/Network_interface_controller" title="Network interface controller">NIC</a> </th> <th><a href="/wiki/Conventional_PCI" class="mw-redirect" title="Conventional PCI">33 MHz PCI</a> </th> <th><a href="/wiki/Secure_Digital" class="mw-redirect" title="Secure Digital">SD</a><sup id="cite_ref-SDHC_15-0" class="reference"><a href="#cite_note-SDHC-15"><span class="cite-bracket">[</span>S 1<span class="cite-bracket">]</span></a></sup> </th> <th><a href="/wiki/RAMDAC" title="RAMDAC">VGA DAC</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> <p>(<a href="/wiki/Watt" title="Watt">W</a>) </p> </th> <th>Features / notes </th> <th>Part number </th></tr> <tr> <th colspan="13">Mobile </th></tr> <tr> <th>A55T </th> <td>Hudson-M2T<sup id="cite_ref-Mx_16-0" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td>×2 Gen 1 </td> <td>1× 3 Gbit/s<br /> AHCI 1.1 </td> <td>0 + 8 + 0 </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="5" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>SDIO </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td> </td> <td> </td></tr> <tr> <th>A50M </th> <td>Hudson-M1<sup id="cite_ref-Mx_16-1" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td>×4 Gen 1<sup id="cite_ref-B1_17-0" class="reference"><a href="#cite_note-B1-17"><span class="cite-bracket">[</span>M 1<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="2">6× 6 Gbit/s<br /><a href="/wiki/AHCI" class="mw-redirect" title="AHCI">AHCI</a> 1.2 </td> <td rowspan="2">0 + 14 + 2 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>5.9<sup id="cite_ref-embed_18-0" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td> <td align="left">~920 mW idle </td> <td>100-CG2198<sup id="cite_ref-embed_18-1" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>A60M </th> <td>Hudson-M2<sup id="cite_ref-Mx_16-2" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3">×4 Gen 1 +DP </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1 </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="3">4.7 </td> <td> </td> <td> </td></tr> <tr> <th>A68M </th> <td>Hudson-M3L<sup id="cite_ref-Mx_16-3" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td>2× 6 Gbit/s<br />AHCI 1.2 </td> <td>2 + 8 + 0 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td align="left">~750 mW idle </td> <td>218-0792006 </td></tr> <tr> <th>A70M </th> <td>Hudson-M3<sup id="cite_ref-Mx_16-4" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td>6× 6 Gbit/s<br />AHCI 1.2 </td> <td>4 + 10 + 2 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td align="left">First native<br />USB 3.0 controller<sup id="cite_ref-usb3chip_19-0" class="reference"><a href="#cite_note-usb3chip-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </td> <td>100-CG2389<sup id="cite_ref-embed_18-2" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>A76M </th> <td>Bolton-M3<sup id="cite_ref-Mx_16-5" class="reference"><a href="#cite_note-Mx-16"><span class="cite-bracket">[</span>N 1<span class="cite-bracket">]</span></a></sup> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td>218-0844012 </td></tr> <tr> <th colspan="13">Desktop </th></tr> <tr> <th>A45 </th> <td>Hudson-D1<sup id="cite_ref-Dx_20-0" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>×4 Gen. 2<sup id="cite_ref-B2_21-0" class="reference"><a href="#cite_note-B2-21"><span class="cite-bracket">[</span>M 2<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="2">6× 3 Gbit/s<br /> AHCI 1.1 </td> <td rowspan="3">0 + 14 + 2 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Up to 4 slots </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td> </td> <td>218-0792008 </td></tr> <tr> <th>A55 </th> <td>Hudson-D2<sup id="cite_ref-Dx_20-1" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>×4 Gen 2 +DP </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Up to 3 slots </td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="2">7.6 </td> <td> </td> <td> </td></tr> <tr> <th>A58 </th> <td>Bolton-D2<sup id="cite_ref-Dx_20-2" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="2">×4 Gen 2 </td> <td>6× 3 Gbit/s<br />AHCI 1.3 </td> <td> </td> <td> </td> <td>218-0844023 </td></tr> <tr> <th>A68H </th> <td>Bolton-D2H<sup id="cite_ref-Dx_20-3" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>4× 6 Gbit/s<br />AHCI 1.3 </td> <td>2 + 10 + 2 </td> <td> </td> <td> </td> <td>xHCI 1.0 </td> <td>218-0844029-00 </td></tr> <tr> <th>A75 </th> <td>Hudson-D3<sup id="cite_ref-Dx_20-4" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3">×4 Gen 2 +DP </td> <td>6× 6 Gbit/s<br />AHCI 1.2 </td> <td rowspan="4">4 + 10 + 2 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td>7.8<sup id="cite_ref-embed_18-3" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td> <td align="left">First native<br />USB 3.0 controller<sup id="cite_ref-usb3chip_19-1" class="reference"><a href="#cite_note-usb3chip-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </td> <td>100-CG2386<sup id="cite_ref-embed_18-4" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>A78 </th> <td>Bolton-D3<sup id="cite_ref-Dx_20-5" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>6× 6 Gbit/s<br />AHCI 1.3 </td> <td> </td> <td rowspan="3">7.8 </td> <td>xHCI 1.0 </td> <td>218-0844014 </td></tr> <tr> <th>A85X </th> <td>Hudson-D4<sup id="cite_ref-Dx_20-6" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>8× 6 Gbit/s<br />AHCI 1.2 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,5,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td>USB 3.0 (xHCI 0.96) </td> <td>218-0755117 </td></tr> <tr> <th>A88X </th> <td>Bolton-D4<sup id="cite_ref-Dx_20-7" class="reference"><a href="#cite_note-Dx-20"><span class="cite-bracket">[</span>N 2<span class="cite-bracket">]</span></a></sup> </td> <td>×4 Gen 2 </td> <td>8× 6 Gbit/s<br />AHCI 1.3 </td> <td> </td> <td>USB 3.0 (xHCI 1.0) </td> <td>218-0844016 </td></tr> <tr> <th colspan="13">Embedded </th></tr> <tr> <th>A55E </th> <td>Hudson-E1<sup id="cite_ref-Ex_22-0" class="reference"><a href="#cite_note-Ex-22"><span class="cite-bracket">[</span>N 3<span class="cite-bracket">]</span></a></sup> </td> <td>×4 Gen 2 </td> <td>6× 6 Gbit/s<br />AHCI 1.2 </td> <td>0 + 14 + 2 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,5,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Gigabit_Ethernet" title="Gigabit Ethernet">10/100/1000</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Up to 4 slots </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>5.9<sup id="cite_ref-embed_18-5" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td> <td> </td> <td>100-CG2293<sup id="cite_ref-embed_18-6" class="reference"><a href="#cite_note-embed-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>A77E<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </th> <td>Bolton-E4<sup id="cite_ref-Ex_22-1" class="reference"><a href="#cite_note-Ex-22"><span class="cite-bracket">[</span>N 3<span class="cite-bracket">]</span></a></sup> </td> <td>1-, 2-, or 4-lane<br />2 or 5 GB/s </td> <td>6× 6 Gbit/s<br />AHCI 1.3 </td> <td>4 + 10 + 2 </td> <td> </td> <td> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Up to 3 slots </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td>4-lane PCIe 2.0 </td> <td>218-0844020-00 </td></tr> <tr> <th>Model </th> <th>Codename </th> <th>UMI </th> <th>SATA </th> <th>USB<br />3.0+2.0+1.1 </th> <th>RAID </th> <th>NIC </th> <th>33 MHz PCI </th> <th>SD<sup id="cite_ref-SDHC_15-1" class="reference"><a href="#cite_note-SDHC-15"><span class="cite-bracket">[</span>S 1<span class="cite-bracket">]</span></a></sup> </th> <th>VGA DAC </th> <th>TDP (W) </th> <th>Features / notes </th> <th>Part number </th></tr></tbody></table> <p>Secure Digital: </p> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-SDHC-15"><span class="mw-cite-backlink">^ <a href="#cite_ref-SDHC_15-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-SDHC_15-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Supports <a href="/wiki/Secure_Digital#SDHC" class="mw-redirect" title="Secure Digital">SDHC</a> up to 32 GB, 4 pins @ 50 MHz.</span> </li> </ol></div></div> <p>Codename: </p> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-Mx-16"><span class="mw-cite-backlink">^ <a href="#cite_ref-Mx_16-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Mx_16-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Mx_16-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Mx_16-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-Mx_16-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-Mx_16-5"><sup><i><b>f</b></i></sup></a></span> <span class="reference-text"><b>M</b>: for notebook platform</span> </li> <li id="cite_note-Dx-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-Dx_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Dx_20-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Dx_20-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Dx_20-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-Dx_20-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-Dx_20-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-Dx_20-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-Dx_20-7"><sup><i><b>h</b></i></sup></a></span> <span class="reference-text"><b>D</b>: for desktop platform</span> </li> <li id="cite_note-Ex-22"><span class="mw-cite-backlink">^ <a href="#cite_ref-Ex_22-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Ex_22-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><b>E</b>: for embedded platform</span> </li> </ol></div></div> <p>UMI: </p> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-B1-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-B1_17-0">^</a></b></span> <span class="reference-text">UMI ×4 Gen. 1 is based on <a href="/wiki/PCI_Express#PCI_Express_1.1" title="PCI Express">PCIe 1.1</a> × 4 lanes, giving 1 GB/s bandwidth</span> </li> <li id="cite_note-B2-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-B2_21-0">^</a></b></span> <span class="reference-text">UMI ×4 Gen. 2 is based on <a href="/wiki/PCI_Express#PCI_Express_2.0" title="PCI Express">PCIe 2.0</a> × 4 lanes, giving 2 GB/s bandwidth</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="AM4_chipsets">AM4 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=10" title="Edit section: AM4 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_B350_Chipset.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/33/AMD_B350_Chipset.jpg/220px-AMD_B350_Chipset.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/33/AMD_B350_Chipset.jpg/330px-AMD_B350_Chipset.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/33/AMD_B350_Chipset.jpg/440px-AMD_B350_Chipset.jpg 2x" data-file-width="1050" data-file-height="1050" /></a><figcaption>AMD B350 Chipset</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_B450_Chipset.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/AMD_B450_Chipset.jpg/220px-AMD_B450_Chipset.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/AMD_B450_Chipset.jpg/330px-AMD_B450_Chipset.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c8/AMD_B450_Chipset.jpg/440px-AMD_B450_Chipset.jpg 2x" data-file-width="750" data-file-height="750" /></a><figcaption>AMD B450 Chipset</figcaption></figure> <p>There are currently 3 generations of AM4-based chipsets on the market. Models beginning with the numeral "3" are representatives of the first generation, those with "4" the second generation, etc. </p><p>In addition to their traditional chipsets, AMD offers chipsets with "processor-direct access", exclusively through OEM partners.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Enthusiast publication <a href="/wiki/Tom%27s_Hardware#Related_publications" title="Tom's Hardware">igor'sLAB</a> obtained leaked documents about an AMD "Knoll Activator" that enables "activating... processor I/O and processor features in the absence of an alternative AMD chipset." It is concluded that motherboards with the Knoll Activator would be built with I/O from the processor and low-cost I/O chips.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>Individual chipset models differ in the number of PCI Express lanes, USB ports, and SATA connectors, as well as supported technologies; the table below shows these differences.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align:center"> <tbody><tr> <th rowspan="2">Model </th> <th rowspan="2">Release date </th> <th rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support<sup id="cite_ref-pcie_28-0" class="reference"><a href="#cite_note-pcie-28"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th> <th colspan="2">Multi-GPU </th> <th rowspan="2"><a href="/wiki/USB" title="USB">USB</a> support<sup id="cite_ref-usb_29-0" class="reference"><a href="#cite_note-usb-29"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> </th> <th colspan="3">Storage features </th> <th rowspan="2">Processor<br /><a href="/wiki/Overclocking" title="Overclocking">overclocking</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th colspan="5">CPU support </th> <th rowspan="2">Architecture </th> <th rowspan="2">Part number </th></tr> <tr> <th><a href="/wiki/AMD_CrossFireX" class="mw-redirect" title="AMD CrossFireX">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th> <th><a href="/wiki/Serial_ATA" class="mw-redirect" title="Serial ATA">SATA</a> ports </th> <th><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/software/storemi.html">AMD StoreMI</a> </th> <th><a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> </th> <th><a href="/wiki/Zen_(first_generation_microarchitecture)" class="mw-redirect" title="Zen (first generation microarchitecture)">Zen</a> </th> <th><a href="/wiki/Zen%2B" title="Zen+">Zen+</a> </th> <th><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> </th> <th><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> </th></tr> <tr> <th>A300 </th> <td rowspan="2"><span data-sort-value="000000002017-02-01-0000" style="white-space:nowrap">Feb 2017</span> </td> <td rowspan="3" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td rowspan="3" colspan="2" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Untested </td> <td rowspan="3" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td rowspan="3" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="3">~120 μW<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td colspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3">Knoll Express<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="1">100-CG2978 218-0892000 KNOLL1 </td></tr> <tr> <th>X300 </th> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td colspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="1">unknown </td></tr> <tr> <th>Pro 500 </th> <td><span data-sort-value="000000002020-01-01-0000" style="white-space:nowrap">Jan 2020</span><sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td colspan="4" style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Partial<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="1">218-0891003 unreleased </td></tr> <tr> <th>A320 </th> <td rowspan="3"><span data-sort-value="000000002017-02-01-0000" style="white-space:nowrap">Feb 2017</span><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </td> <td>PCIe 2.0 ×4 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>1, 2, 6 </td> <td rowspan="2">4 </td> <td rowspan="8">0,<br />1,<br />10 </td> <td rowspan="3" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Limited<sup id="cite_ref-A320_OC_41-0" class="reference"><a href="#cite_note-A320_OC-41"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="6">~5.8 W<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="3" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="8" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="3" colspan="2" style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe"><small>Varies</small><sup id="cite_ref-zen2_43-0" class="reference"><a href="#cite_note-zen2-43"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="7">Promontory </td> <td rowspan="1">218-0891004 </td></tr> <tr> <th>B350 </th> <td>PCIe 2.0 ×6 </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>2, 2, 6 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="1">218-0891005 </td></tr> <tr> <th>X370 </th> <td>PCIe 2.0 ×8 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>2, 6, 6 </td> <td>8 </td> <td rowspan="1">218-0891006 </td></tr> <tr> <th>B450 </th> <td rowspan="2"><span data-sort-value="000000002018-03-01-0000" style="white-space:nowrap">Mar 2018</span><sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </td> <td>PCIe 2.0 ×6 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>2, 2, 6 </td> <td>4 </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes,<br />with <abbr title="Precision Boost Overdrive">PBO</abbr> </td> <td rowspan="4" style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe"><small>Varies</small><sup id="cite_ref-zen3_45-0" class="reference"><a href="#cite_note-zen3-45"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="5" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td rowspan="4" style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe"><small>Varies</small><sup id="cite_ref-zen3_45-1" class="reference"><a href="#cite_note-zen3-45"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Tom's_Hardware_Zen3_Update_46-0" class="reference"><a href="#cite_note-Tom's_Hardware_Zen3_Update-46"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </td> <td rowspan="1">218-0891011 </td></tr> <tr> <th>X470 </th> <td>PCIe 2.0 ×8 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>2, 6, 6 </td> <td>8 </td> <td rowspan="1">218-0891008 </td></tr> <tr> <th>A520 </th> <td><span data-sort-value="000000002020-08-01-0000" style="white-space:nowrap">Aug 2020</span><sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </td> <td>PCIe 3.0 ×6 </td> <td colspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>1, 2, 6 </td> <td>4 </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td rowspan="2" style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">Varies </td> <td rowspan="1">218-0891015 </td></tr> <tr> <th>B550<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>h<span class="cite-bracket">]</span></a></sup> </th> <td><span data-sort-value="000000002020-06-01-0000" style="white-space:nowrap">Jun 2020</span><sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </td> <td>PCIe 3.0 ×10 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background: #FF8; color:black; vertical-align: middle; text-align: center;" class="table-maybe">Varies </td> <td>2, 2, 6 </td> <td>6 </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes,<br />with <abbr title="Precision Boost Overdrive">PBO</abbr> </td> <td>~7W </td> <td rowspan="1">218-0891014 - b550, 218-0891009 - B550A </td></tr> <tr> <th>X570 </th> <td><span data-sort-value="000000002019-07-01-0000" style="white-space:nowrap">Jul 2019</span><sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </td> <td>PCIe 4.0 ×16 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>8, 0, 4 </td> <td>12 </td> <td>~15 W<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>i<span class="cite-bracket">]</span></a></sup> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Bixby </td> <td rowspan="1">100-CG3091 </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output 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.navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AM4_chipsets" title="Template:AM4 chipsets"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AM4_chipsets" title="Template talk:AM4 chipsets"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AM4_chipsets" title="Special:EditPage/Template:AM4 chipsets"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-pcie-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-pcie_28-0">^</a></b></span> <span class="reference-text"> PCIe lanes provided by the chipset. The CPU provides other PCIe 3.0 or 4.0 lanes.</span> </li> <li id="cite_note-usb-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-usb_29-0">^</a></b></span> <span class="reference-text"> USB 3.2 Gen 2x1, USB 3.2 Gen 1x1, USB 2.0</span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text">Knoll chipsets consume "insignificant power ...after [boot] in sleep mode", power figure based on a typical SPI controller</span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text">Limited to specific SKUs branded as Ryzen Pro and Athlon Pro</span> </li> <li id="cite_note-A320_OC-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-A320_OC_41-0">^</a></b></span> <span class="reference-text">Only pre-Zen CPUs can be overclocked.</span> </li> <li id="cite_note-zen2-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-zen2_43-0">^</a></b></span> <span class="reference-text"> BIOS update needed. Availability may depend on manufacturer.</span> </li> <li id="cite_note-zen3-45"><span class="mw-cite-backlink">^ <a href="#cite_ref-zen3_45-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-zen3_45-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"> Beta BIOS updates may be made available by motherboard manufacturers.</span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text">OEM-only B550A is a rebranded B450</span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text">7 watts on passive cooling (termed X570s).</span> </li> </ol></div></div> <p>The 300 series, 400 series, and the B550 chipsets are designed in collaboration with <a href="/wiki/ASMedia" title="ASMedia">ASMedia</a> and the family is codenamed Promontory.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> The X570 is designed by AMD with IP licensed from ASMedia and other companies and is codenamed Bixby.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Network_interface_controller" title="Network interface controller">Network interface controller</a>, <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a>, and <a href="/wiki/Bluetooth" title="Bluetooth">Bluetooth</a> are provided by external chips connected to the chipset through PCIe or USB. All 300 series chipsets are made using 55 <a href="/wiki/Nanometre" title="Nanometre">nm</a> lithography.<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> The X570 chipset is a repurposed Matisse/Vermeer IO die made using a 14 nm process.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="TR4_chipsets">TR4 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=11" title="Edit section: TR4 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Supports both 1st and 2nd generation AMD Ryzen Threadripper processors.<sup id="cite_ref-amd_socket_tr4_60-0" class="reference"><a href="#cite_note-amd_socket_tr4-60"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="2">Model </th> <th rowspan="2">CPU<br /><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> Link </th> <th rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th colspan="2">Multi-GPU support </th> <th rowspan="2"><a href="/wiki/SATA" title="SATA">SATA</a> + <a href="/wiki/SATA_Express" title="SATA Express">SATA Express</a> </th> <th rowspan="2"><a href="/wiki/USB" title="USB">USB</a><br />3.1 Gen 2 + 3.1 Gen 1 + 2.0 </th> <th rowspan="2"><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th rowspan="2"><a href="/wiki/Overclocking" title="Overclocking">Overclocking</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Chipset lithography </th></tr> <tr> <th><a href="/wiki/AMD_CrossFireX" class="mw-redirect" title="AMD CrossFireX">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th></tr> <tr> <th style="text-align: left">X399<sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-amd_socket_tr4_60-1" class="reference"><a href="#cite_note-amd_socket_tr4-60"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </th> <td>×4 </td> <td>PCIe 2.0 ×8 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>4 + 2 </td> <td>2 + 14 + 6 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>5 W<sup id="cite_ref-Anand_TRX40_62-0" class="reference"><a href="#cite_note-Anand_TRX40-62"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="sTRX4_chipsets">sTRX4 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=12" title="Edit section: sTRX4 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Supports 3rd generation AMD Ryzen Threadripper (3960X to 3990X) processors.<sup id="cite_ref-sTRX4_63-0" class="reference"><a href="#cite_note-sTRX4-63"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="2">Model </th> <th rowspan="2">CPU<br /><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> Link </th> <th rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th colspan="2">Multi-GPU support </th> <th rowspan="2"><a href="/wiki/SATA" title="SATA">SATA</a> </th> <th rowspan="2"><a href="/wiki/USB" title="USB">USB</a><br />3.1 Gen 2 + 2.0 </th> <th rowspan="2"><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th rowspan="2"><a href="/wiki/Overclocking" title="Overclocking">Overclocking</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Chipset lithography </th> <th rowspan="2">Notes </th></tr> <tr> <th><a href="/wiki/AMD_CrossFireX" class="mw-redirect" title="AMD CrossFireX">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th></tr> <tr> <th style="text-align: left">TRX40<sup id="cite_ref-sTRX4_63-1" class="reference"><a href="#cite_note-sTRX4-63"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> </th> <td>×8 </td> <td>PCIe 4.0 ×8 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>4 (+ up to 2 × 4 extra) </td> <td>8 + 4 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>15 W<sup id="cite_ref-Anand_TRX40_62-1" class="reference"><a href="#cite_note-Anand_TRX40-62"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </td> <td>14 nm </td> <td>HW-wise identical to X570<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (November 2021)">citation needed</span></a></i>]</sup> </td></tr></tbody></table> <p>Although the X399, TRX40 and WRX80 motherboards' CPU sockets use the same number of pins, the sockets are incompatible with each other due to ID pins and no-connects of some pins. Twelve TRX40 motherboards were released at launch in November 2019. The TRX40 chipset does not support the <a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">HD Audio</a> interface on its own, so motherboard vendors must include a USB audio device or a PCIe audio device on TRX40 motherboards to integrate audio codecs.<sup id="cite_ref-Anand_TRX40_62-2" class="reference"><a href="#cite_note-Anand_TRX40-62"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="sWRX8_chipsets">sWRX8 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=13" title="Edit section: sWRX8 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Supports 3rd (3900WX) and 4th generation (5900WX) AMD Ryzen Threadripper Pro processors.<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="2">Model </th> <th rowspan="2">CPU<br /><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> Link </th> <th rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th colspan="2">Multi-GPU support </th> <th rowspan="2"><a href="/wiki/SATA" title="SATA">SATA</a> </th> <th rowspan="2"><a href="/wiki/USB" title="USB">USB</a><br />3.1 Gen 2 + 2.0 </th> <th rowspan="2"><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th rowspan="2"><a href="/wiki/Overclocking" title="Overclocking">Overclocking</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Chipset lithography </th> <th rowspan="2">Notes </th></tr> <tr> <th><a href="/wiki/AMD_CrossFireX" class="mw-redirect" title="AMD CrossFireX">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th></tr> <tr> <th style="text-align: left">WRX80 </th> <td>×8 </td> <td>PCIe 4.0 ×16 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>4 </td> <td>8 + 4 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">0,1,10 </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>15 W </td> <td>14 nm </td> <td>HW-wise identical to EPYC/Threadripper IO die<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (November 2021)">citation needed</span></a></i>]</sup> </td></tr></tbody></table> <p>Although the X399, TRX40 and WRX80 motherboards' CPU sockets use the same number of pins, the sockets are incompatible with each other due to ID pins and no-connects of some pins.<sup id="cite_ref-Anand_TRX40_62-3" class="reference"><a href="#cite_note-Anand_TRX40-62"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> Three WRX80 motherboards were released at launch in March 2021. The WRX80 chipset does not support the <a href="/wiki/Intel_High_Definition_Audio" title="Intel High Definition Audio">HD Audio</a> interface on its own, so motherboard vendors must include a USB audio device or a PCIe audio device on WRX80 motherboards to integrate audio codecs. </p> <div class="mw-heading mw-heading2"><h2 id="AM5_chipsets">AM5 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=14" title="Edit section: AM5 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>AMD uses a single Promontory 21 chipset for all configurations that include a chipset. A single Promontory 21 chip provides four SATA III ports and twelve PCIe 4.0 lanes. Four lanes are reserved for the chipset uplink to the CPU while another four are used to connect to another Promontory 21 chip in a daisy-chained topology for X670, X670E and X870E chipsets.<sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="font-size: 100%; text-align: center;"> <tbody><tr> <th rowspan="2" colspan="3"> </th> <th colspan="9">Branding </th></tr> <tr> <th style="width:7em;">A620 </th> <th style="width:7em;">B650 </th> <th style="width:7em;">B650E </th> <th style="width:7em;">X670 </th> <th style="width:7em;">X670E </th> <th style="width:7em;">B840 </th> <th style="width:7em;">B850 </th> <th style="width:7em;">X870 </th> <th style="width:7em;">X870E </th></tr> <tr> <th rowspan="8" class="nowrap ts-vertical-header is-valign-middle" style=""><div style=""><style data-mw-deduplicate="TemplateStyles:r1221560606">@supports(writing-mode:vertical-rl){.mw-parser-output .ts-vertical-header{line-height:1;max-width:1em;padding:0.4em;vertical-align:bottom;width:1em}html.client-js .mw-parser-output .sortable:not(.jquery-tablesorter) .ts-vertical-header:not(.unsortable),html.client-js .mw-parser-output .ts-vertical-header.headerSort{background-position:50%.4em;padding-right:0.4em;padding-top:21px}.mw-parser-output .ts-vertical-header.is-valign-top{vertical-align:top}.mw-parser-output .ts-vertical-header.is-valign-middle{vertical-align:middle}.mw-parser-output .ts-vertical-header.is-normal{font-weight:normal}.mw-parser-output .ts-vertical-header>*{display:inline-block;transform:rotate(180deg);writing-mode:vertical-rl}@supports(writing-mode:sideways-lr){.mw-parser-output .ts-vertical-header>*{transform:none;writing-mode:sideways-lr}}}</style>Platform features</div> </th> <th style="text-align: left;" rowspan="2">PCIe 5.0<br />support<sup id="cite_ref-PCIeDirect_66-0" class="reference"><a href="#cite_note-PCIeDirect-66"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th> <th style="text-align: left;">x16 slot </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;">M.2 slot + 4× <abbr title="General-Purpose PCIe">GPP</abbr> </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">M.2 Optional </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;" colspan="2">x16 slot configurations </th> <td>1×16 </td> <td colspan="4">1×16 or 2×8 </td> <td>1×16 </td> <td colspan="5">1×16 or 2×8 </td></tr> <tr> <th style="text-align: left;" rowspan="2">Multi-GPU </th> <th style="text-align: left;"><a href="/wiki/AMD_CrossFire" title="AMD CrossFire">CrossFire</a> </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;"><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th style="text-align: left;" colspan="2"><a href="/wiki/USB4" title="USB4">USB4</a> Gen 3×2 <span style="font-size:90%;">(40 Gb/s)</span><sup id="cite_ref-3PController_67-0" class="reference"><a href="#cite_note-3PController-67"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> </th> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#FFB; color:black;vertical-align:middle;text-align:center;" class="table-partial">Optional </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;" colspan="2">Wi-Fi version<sup id="cite_ref-3PController_67-1" class="reference"><a href="#cite_note-3PController-67"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-OmitWiFi_68-0" class="reference"><a href="#cite_note-OmitWiFi-68"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </th> <td colspan="5"><a href="/wiki/Wi-Fi_6" title="Wi-Fi 6">6</a> </td> <td> </td> <td> </td> <td colspan="2"><a href="/wiki/IEEE_802.11be" class="mw-redirect" title="IEEE 802.11be">7</a> </td></tr> <tr> <th style="text-align: left;" colspan="2"><a href="/wiki/Overclocking" title="Overclocking">Processor overclocking</a> </th> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th rowspan="12" class="nowrap ts-vertical-header is-valign-middle" style=""><div style=""><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1221560606" />Chipset specifications</div> </th> <th style="text-align: left;" rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> lanes<sup id="cite_ref-pcie_69-0" class="reference"><a href="#cite_note-pcie-69"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </th> <th>Gen 4 </th> <td style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td colspan="2">×8 </td> <td colspan="2">×12 </td> <td>x10 </td> <td>x12 </td> <td>×8 </td> <td>×12 </td></tr> <tr> <th>Gen 3 </th> <td>Up to ×8 </td> <td colspan="2">Up to ×4 </td> <td colspan="2">Up to ×8 </td> <td>Up to x4 </td> <td>Up to ×4 </td> <td>Up to ×8 </td></tr> <tr> <th style="text-align: left;" rowspan="4">USB<br />support </th> <th style="text-align: left;"><a href="/wiki/USB_2.0" class="mw-redirect" title="USB 2.0">USB 2.0</a> </th> <td colspan="3">6 </td> <td colspan="2">12 </td> <td> </td> <td> </td> <td>6 </td> <td>12 </td></tr> <tr> <th style="text-align: left;"><a href="/wiki/USB_3.0#USB_3.2" title="USB 3.0">USB 3.2</a> Gen 1x1<br /><span style="font-size:90%;">(5 Gb/s)</span> </th> <td>2 </td> <td colspan="4" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td> </td> <td> </td> <td colspan="2" style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td></tr> <tr> <th style="text-align: left;">USB 3.2 Gen 2x1<br /><span style="font-size:90%;">(10 Gb/s)</span> </th> <td>2 </td> <td colspan="2">4 </td> <td colspan="2">8 </td> <td>2 </td> <td>6 </td> <td>4 </td> <td>8 </td></tr> <tr> <th style="text-align: left;">USB 3.2 Gen 2x2<br /><span style="font-size:90%;">(20 Gb/s)</span> </th> <td style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td colspan="2">1<sup id="cite_ref-usbshared1_70-0" class="reference"><a href="#cite_note-usbshared1-70"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2">2<sup id="cite_ref-usbshared2_71-0" class="reference"><a href="#cite_note-usbshared2-71"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup> </td> <td style="background: #FFE3E3; color: black; vertical-align: middle; text-align: center;" class="table-no2">None </td> <td colspan="2">1<sup id="cite_ref-usbshared1_70-1" class="reference"><a href="#cite_note-usbshared1-70"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup> </td> <td>2<sup id="cite_ref-usbshared2_71-1" class="reference"><a href="#cite_note-usbshared2-71"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th style="text-align: left;" rowspan="2">Storage<br />features </th> <th style="text-align: left;"><a href="/wiki/SATA_III" class="mw-redirect" title="SATA III">SATA III</a> ports </th> <td colspan="3">Up to 4 </td> <td colspan="2">Up to 8 </td> <td colspan="3">Up to 4 </td> <td>Up to 8 </td></tr> <tr> <th style="text-align: left;"><a href="/wiki/RAID" title="RAID">RAID</a> </th> <td colspan="9">0, 1, 10 </td></tr> <tr> <th style="text-align: left;" colspan="2">Chipset <a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <td>~4.5 W </td> <td colspan="2">~7 W </td> <td colspan="2">~14 W<sup id="cite_ref-TDPx2_72-0" class="reference"><a href="#cite_note-TDPx2-72"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup> </td> <td> </td> <td> </td> <td>~7 W </td> <td>~14 W<sup id="cite_ref-TDPx2_72-1" class="reference"><a href="#cite_note-TDPx2-72"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th style="text-align: left;" colspan="2">Architecture </th> <td colspan="3">Promontory 21<br />×1 </td> <td colspan="2">Promontory 21<br />×2 </td> <td> </td> <td> </td> <td>Promontory 21<br />×1 </td> <td>Promontory 21<br />×2 </td></tr> <tr> <th style="text-align: left;" rowspan="2">Chipset<br />links </th> <th style="text-align: left;">To CPU </th> <td colspan="9">PCIe 4.0 ×4 </td></tr> <tr> <th style="text-align: left;">Interchipset </th> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="2">PCIe 4.0 ×4 </td> <td> </td> <td> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>PCIe 4.0 ×4 </td></tr> <tr> <th style="text-align: left;" colspan="2" rowspan="2">CPU<br />support </th> <th style="text-align: left;"><a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> </th> <td colspan="9" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;"><a href="/wiki/Zen_5" title="Zen 5">Zen 5</a> </th> <td colspan="9" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th style="text-align: left;" colspan="3">Release date </th> <td><span data-sort-value="000000002023-03-31-0000" style="white-space:nowrap">Mar 31, 2023</span> </td> <td colspan="2"><span data-sort-value="000000002022-10-10-0000" style="white-space:nowrap">Oct 10, 2022</span> </td> <td colspan="2"><span data-sort-value="000000002022-09-27-0000" style="white-space:nowrap">Sep 27, 2022</span> </td> <td colspan="2"><span data-sort-value="000000002025-01-06-0000" style="white-space:nowrap">Jan 6, 2025</span> </td> <td colspan="2"><span data-sort-value="000000002024-09-01-0000" style="white-space:nowrap">Sep 2024</span> </td></tr> <tr> <th style="text-align: left;" colspan="3">Reference(s) </th> <td><sup id="cite_ref-AMD_AM5_Chipsets_73-0" class="reference"><a href="#cite_note-AMD_AM5_Chipsets-73"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-74" class="reference"><a href="#cite_note-74"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-75" class="reference"><a href="#cite_note-75"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> </td> <td colspan="4"><sup id="cite_ref-AMD_AM5_Chipsets_73-1" class="reference"><a href="#cite_note-AMD_AM5_Chipsets-73"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-76" class="reference"><a href="#cite_note-76"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-77" class="reference"><a href="#cite_note-77"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </td> <td> </td> <td> </td> <td colspan="2"><sup id="cite_ref-AMD_AM5_Chipsets_73-2" class="reference"><a href="#cite_note-AMD_AM5_Chipsets-73"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-78" class="reference"><a href="#cite_note-78"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-79" class="reference"><a href="#cite_note-79"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-80" class="reference"><a href="#cite_note-80"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AM5_chipsets" title="Template:AM5 chipsets"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AM5_chipsets" title="Template talk:AM5 chipsets"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AM5_chipsets" title="Special:EditPage/Template:AM5 chipsets"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-PCIeDirect-66"><span class="mw-cite-backlink"><b><a href="#cite_ref-PCIeDirect_66-0">^</a></b></span> <span class="reference-text">Support for Gen5 speeds on lanes directly from CPU to expansion and M.2 slots, and general-purpose lanes.</span> </li> <li id="cite_note-3PController-67"><span class="mw-cite-backlink">^ <a href="#cite_ref-3PController_67-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-3PController_67-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Provided by a third-party controller.</span> </li> <li id="cite_note-OmitWiFi-68"><span class="mw-cite-backlink"><b><a href="#cite_ref-OmitWiFi_68-0">^</a></b></span> <span class="reference-text">Motherboard makers may omit Wi-Fi on some models.</span> </li> <li id="cite_note-pcie-69"><span class="mw-cite-backlink"><b><a href="#cite_ref-pcie_69-0">^</a></b></span> <span class="reference-text"> PCIe lanes provided by the chipset. The CPU provides other PCIe 5.0 and/or 4.0 lanes.</span> </li> <li id="cite_note-usbshared1-70"><span class="mw-cite-backlink">^ <a href="#cite_ref-usbshared1_70-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-usbshared1_70-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"> The motherboard maker may configure the USB 3.2 provided by the chipset as 6× 3.2 Gen 2x1 and 0× 3.2 Gen 2x2 ports.</span> </li> <li id="cite_note-usbshared2-71"><span class="mw-cite-backlink">^ <a href="#cite_ref-usbshared2_71-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-usbshared2_71-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"> The motherboard maker may configure the USB 3.2 provided by the chipset as 10× 3.2 Gen 2x1 and 1× 3.2 Gen 2x2 ports, or 12× 3.2 Gen 2x1 and 0× 3.2 Gen 2x2 ports.</span> </li> <li id="cite_note-TDPx2-72"><span class="mw-cite-backlink">^ <a href="#cite_ref-TDPx2_72-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-TDPx2_72-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Two Promontory 21 chipsets are present, each having a TDP of ~7 W, giving a total TDP of ~14 W.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="sTR5_chipsets">sTR5 chipsets</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=15" title="Edit section: sTR5 chipsets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/Socket_sTR5" title="Socket sTR5">sTR5</a> socket has two chipset options available, TRX50 and WRX90: </p> <ul><li>TRX50 is an HEDT (High-End Desk-Top) platform which is intended to be paired with Threadripper (7000X) series processors, but is also compatible with Threadripper Pro models. When a Threadripper Pro CPU is paired with a TRX50 motherboard, extra features like enterprise management and security won't be available to the user, and PCIe lanes and memory channels will still be limited to that of non-Pro Threadripper.</li></ul> <ul><li>WRX90 is a workstation platform for Threadripper Pro (7000WX) series processors. It is not compatible with the Threadripper non-Pro 7000X series.<sup id="cite_ref-81" class="reference"><a href="#cite_note-81"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup></li></ul> <p>HD audio support is provided by the CPU, rather than by the chipset.<sup id="cite_ref-servethehome-wrx90_82-0" class="reference"><a href="#cite_note-servethehome-wrx90-82"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="2">Model </th> <th rowspan="2">CPU<br /><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> Link </th> <th rowspan="2"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th colspan="2">Multi-GPU support </th> <th rowspan="2"><a href="/wiki/SATA" title="SATA">SATA</a> </th> <th rowspan="2"><a href="/wiki/USB" title="USB">USB</a><br />3.2 Gen 2x2 + 3.1 Gen 2 + 2.0 </th> <th rowspan="2"><a href="/wiki/RAID" title="RAID">RAID</a> </th> <th rowspan="2"><a href="/wiki/Overclocking" title="Overclocking">Overclocking</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Chipset lithography </th> <th rowspan="2">Notes </th></tr> <tr> <th><a href="/wiki/AMD_CrossFireX" class="mw-redirect" title="AMD CrossFireX">CrossFire</a> </th> <th><a href="/wiki/Scalable_Link_Interface" title="Scalable Link Interface">SLI</a> </th></tr> <tr> <th style="text-align: left">TRX50<sup id="cite_ref-pugetsystems-str5_83-0" class="reference"><a href="#cite_note-pugetsystems-str5-83"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> </th> <td> </td> <td rowspan="4">PCIe 4.0 ×8 </td> <td> </td> <td> </td> <td rowspan="2">4 </td> <td rowspan="2">1 + 4 + 4 </td> <td> </td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td> </td> <td> </td></tr> <tr> <th style="text-align: left">WRX90<sup id="cite_ref-servethehome-wrx90_82-1" class="reference"><a href="#cite_note-servethehome-wrx90-82"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-pugetsystems-str5_83-1" class="reference"><a href="#cite_note-pugetsystems-str5-83"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> </th> <td>×4 </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=16" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_AMD_microprocessors" class="mw-redirect" title="List of AMD microprocessors">List of AMD microprocessors</a></li> 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Retrieved <span class="nowrap">8 October</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GamersNexus&rft.atitle=AMD+Chipset+Comparison%3A+B550+Specs+vs.+X570%2C+B450%2C+X370%2C+%26+Zen+3+Support+%282020%29&rft_id=https%3A%2F%2Fwww.gamersnexus.net%2Fguides%2F3582-amd-chipset-differences-b550-vs-x570-b450-x470-zen-3&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFCrimsonRayne2018" class="citation web cs1">CrimsonRayne (2018-12-01). <a rel="nofollow" class="external text" href="http://www.redgamingtech.com/amd-x570-launches-at-computex-supports-pcie-4-0-ryzen-3000-series-launch-date-leaked/">"AMD X570 Launches at Computex & Supports PCIE 4.0 | Ryzen 3000 Series Launch Date Leaked?"</a>. <i>redgamingtech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-07-10</span></span>. <q>the X570 platform is targeting a release of Computex 2019, which takes place between May 28th and June 1st.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=redgamingtech&rft.atitle=AMD+X570+Launches+at+Computex+%26+Supports+PCIE+4.0+%26%23124%3B+Ryzen+3000+Series+Launch+Date+Leaked%3F&rft.date=2018-12-01&rft.au=CrimsonRayne&rft_id=http%3A%2F%2Fwww.redgamingtech.com%2Famd-x570-launches-at-computex-supports-pcie-4-0-ryzen-3000-series-launch-date-leaked%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFHassan_Mujtaba2019" class="citation web cs1">Hassan Mujtaba (2019-05-27). <a rel="nofollow" class="external text" href="https://wccftech.com/amd-x570-motherboard-roundup-aorus-asus-asrock-msi-colorful-biostar/">"AMD X570 Motherboard Roundup – Featuring X570 AORUS Xtreme, ASRock X570 Taichi, MSI MEG X570 GODLIKE, ASUS Crosshair VIII HERO & More"</a>. <i>wccftech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-07-10</span></span>. <q>slide</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=wccftech&rft.atitle=AMD+X570+Motherboard+Roundup+%E2%80%93+Featuring+X570+AORUS+Xtreme%2C+ASRock+X570+Taichi%2C+MSI+MEG+X570+GODLIKE%2C+ASUS+Crosshair+VIII+HERO+%26+More&rft.date=2019-05-27&rft.au=Hassan+Mujtaba&rft_id=https%3A%2F%2Fwccftech.com%2Famd-x570-motherboard-roundup-aorus-asus-asrock-msi-colorful-biostar%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGavin_Bonshor2019" class="citation web cs1">Gavin Bonshor (2019-05-26). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14406/amd-reveals-the-x570-chipset-pcie-4-is-here">"AMD Reveals the X570 Chipset: PCIe 4.0 is Here"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2020-08-19</span></span>. <q>One of the caveats to a more powerful chipset is that it draws around 11 W of power.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=AMD+Reveals+the+X570+Chipset%3A+PCIe+4.0+is+Here&rft.date=2019-05-26&rft.au=Gavin+Bonshor&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14406%2Famd-reveals-the-x570-chipset-pcie-4-is-here&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/255729/amd-x570-unofficial-platform-diagram-revealed-chipset-puts-out-pcie-gen-4">"AMD X570 Unofficial Platform Diagram Revealed, Chipset Puts out PCIe Gen 4"</a>. <i>TechPowerUp</i>. 2019-05-20<span class="reference-accessdate">. Retrieved <span class="nowrap">2020-08-19</span></span>. <q>The source also mentions the TDP of the AMD X570 chipset to be at least 15 Watts, a 3-fold increase over the X470 with its 5W TDP.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=AMD+X570+Unofficial+Platform+Diagram+Revealed%2C+Chipset+Puts+out+PCIe+Gen+4&rft.date=2019-05-20&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F255729%2Famd-x570-unofficial-platform-diagram-revealed-chipset-puts-out-pcie-gen-4&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFIan_Cutress2017" class="citation web cs1">Ian Cutress (2017-03-02). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/11177/making-amd-tick-a-very-zen-interview-with-dr-lisa-su-ceo">"Making AMD Tick: A Very Zen Interview with Dr. Lisa Su, CEO"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-06-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Making+AMD+Tick%3A+A+Very+Zen+Interview+with+Dr.+Lisa+Su%2C+CEO&rft.date=2017-03-02&rft.au=Ian+Cutress&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F11177%2Fmaking-amd-tick-a-very-zen-interview-with-dr-lisa-su-ceo&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFGavin_Bonshor" class="citation web cs1">Gavin Bonshor. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14406/amd-reveals-the-x570-chipset-pcie-4-is-here">"AMD Reveals the X570 Chipset: PCIe 4.0 is Here"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-06-10</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=AMD+Reveals+the+X570+Chipset%3A+PCIe+4.0+is+Here&rft.au=Gavin+Bonshor&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14406%2Famd-reveals-the-x570-chipset-pcie-4-is-here&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFIan_Cutress2017" class="citation web cs1">Ian Cutress (2017-03-02). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/11177/making-amd-tick-a-very-zen-interview-with-dr-lisa-su-ceo">"Making AMD Tick: A Very Zen Interview with Dr. Lisa Su, CEO"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-06-10</span></span>. <q>Q6: It has been noted that AMD has been working with ASMedia on the chipset side of the platform, using a 55nm PCIe 3.0x4 based chipset.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Making+AMD+Tick%3A+A+Very+Zen+Interview+with+Dr.+Lisa+Su%2C+CEO&rft.date=2017-03-02&rft.au=Ian+Cutress&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F11177%2Fmaking-amd-tick-a-very-zen-interview-with-dr-lisa-su-ceo&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFDr._Ian_Cutress2019" class="citation web cs1">Dr. Ian Cutress [@IanCutress] (June 11, 2019). <a rel="nofollow" class="external text" href="https://x.com/IanCutress/status/1138443875154944000">"So for clarity: Rome large IO die = GF 14nm Matisse small IO die = GF 12nm X570 Chipset = Matisse IO die on GF 14nm That's right. The X570 chipset is the same floorplan as the Matisse, but with diff chicken bits enabled/disabled. AMD has good reuse of chips"</a> (<a href="/wiki/Tweet_(social_media)" title="Tweet (social media)">Tweet</a>). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201107230846/https://twitter.com/IanCutress/status/1138443875154944000">Archived</a> from the original on November 7, 2020<span class="reference-accessdate">. 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Retrieved <span class="nowrap">22 October</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HotHardware&rft.atitle=AMD+Threadripper+Pro+7000+Debut%3A+96-Core+Zen+4+CPU+Benchmarked&rft.date=2023-10-20&rft.aulast=Chiappetta&rft.aufirst=Marco&rft_id=https%3A%2F%2Fhothardware.com%2Freviews%2Famd-threadripper-pro-7000wx-and-threadripper-7000-hedt-launch&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-servethehome-wrx90-82"><span class="mw-cite-backlink">^ <a href="#cite_ref-servethehome-wrx90_82-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-servethehome-wrx90_82-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFKennedy2023" class="citation web cs1">Kennedy, Patrick (19 October 2023). <a rel="nofollow" class="external text" href="https://www.servethehome.com/amd-ryzen-threadripper-pro-7000wx-at-96-cores-and-threadripper-7000-hedt/">"AMD Ryzen Threadripper Pro 7000WX at 96 Cores and Threadripper 7000 HEDT"</a>. <i>ServeTheHome</i><span class="reference-accessdate">. Retrieved <span class="nowrap">22 October</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ServeTheHome&rft.atitle=AMD+Ryzen+Threadripper+Pro+7000WX+at+96+Cores+and+Threadripper+7000+HEDT&rft.date=2023-10-19&rft.aulast=Kennedy&rft.aufirst=Patrick&rft_id=https%3A%2F%2Fwww.servethehome.com%2Famd-ryzen-threadripper-pro-7000wx-at-96-cores-and-threadripper-7000-hedt%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> <li id="cite_note-pugetsystems-str5-83"><span class="mw-cite-backlink">^ <a href="#cite_ref-pugetsystems-str5_83-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-pugetsystems-str5_83-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFLagergren2023" class="citation web cs1">Lagergren, Evan (30 October 2023). <a rel="nofollow" class="external text" href="https://www.pugetsystems.com/labs/articles/amd-trx50-vs-wrx90/">"AMD TRX50 vs WRX90"</a>. <i>Puget Systems</i><span class="reference-accessdate">. Retrieved <span class="nowrap">10 January</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Puget+Systems&rft.atitle=AMD+TRX50+vs+WRX90&rft.date=2023-10-30&rft.aulast=Lagergren&rft.aufirst=Evan&rft_id=https%3A%2F%2Fwww.pugetsystems.com%2Flabs%2Farticles%2Famd-trx50-vs-wrx90%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+chipsets" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&section=18" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/chipsets-motherboards-desktop">AMD Chipsets</a></li></ul> <div class="navbox-styles"><link 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class="nv-talk"><a href="/wiki/Template_talk:AMD_CPU_sockets" title="Template talk:AMD CPU sockets"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_CPU_sockets" title="Special:EditPage/Template:AMD CPU sockets"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_sockets_and_chipsets157" style="font-size:114%;margin:0 4em"><a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> sockets and chipsets</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="AMD_sockets157" style="font-size:114%;margin:0 4em"><a href="/wiki/Category:AMD_sockets" title="Category:AMD sockets">AMD sockets</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Desktop sockets</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Super_Socket_7" title="Super Socket 7">Super Socket 7</a> (1998)</li> <li><a href="/wiki/Slot_A" title="Slot A">Slot A</a> (1999)</li> <li><a href="/wiki/Socket_939" title="Socket 939">939</a> (2004)</li> <li><a href="/wiki/Socket_940" title="Socket 940">940</a> (2003)</li> <li><a href="/wiki/Socket_AM2" title="Socket AM2">AM2</a> (2006)</li> <li><a href="/wiki/Socket_AM2%2B" title="Socket AM2+">AM2+</a> (2007)</li> <li><a href="/wiki/Socket_AM3" title="Socket AM3">AM3</a> (2009)</li> <li><a href="/wiki/Socket_AM3%2B" title="Socket AM3+">AM3+</a> (2011)</li> <li><a href="/wiki/Socket_FM1" title="Socket FM1">FM1</a> (2011)</li> <li><a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a> (2012)</li> <li><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a> (2014)</li> <li><a href="/wiki/Socket_AM1" title="Socket AM1">AM1</a> (2014)</li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> (2016)</li> <li><a href="/wiki/Socket_TR4" title="Socket TR4">TR4</a> (2017)</li> <li><a href="/wiki/Socket_sTRX4" title="Socket sTRX4">sTRX4</a> (2019)</li> <li><a href="/wiki/Socket_sWRX8" title="Socket sWRX8">sWRX8</a> (2020)</li> <li><a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a> (2022)</li> <li><a href="/wiki/Socket_sTR5" title="Socket sTR5">sTR5</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile sockets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_563" title="Socket 563">563</a></li> <li><a href="/wiki/Socket_S1" title="Socket S1">S1</a> (2006)</li> <li><a href="/wiki/Socket_FT1" title="Socket FT1">FT1</a> (2011)</li> <li><a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a> (2012)</li> <li><a href="/wiki/Socket_FS1" title="Socket FS1">FS1</a></li> <li><a href="/wiki/Socket_FT3" title="Socket FT3">FT3</a></li> <li><a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a> (2014)</li> <li><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a> (2015)</li> <li><a href="/w/index.php?title=Socket_FT4&action=edit&redlink=1" class="new" title="Socket FT4 (page does not exist)">FT4</a> (2016)</li> <li><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> (2019)</li> <li><a href="/w/index.php?title=Socket_FT5&action=edit&redlink=1" class="new" title="Socket FT5 (page does not exist)">FT5</a></li> <li><a href="/w/index.php?title=Socket_FP6&action=edit&redlink=1" class="new" title="Socket FP6 (page does not exist)">FP6</a> (2020)</li> <li><a href="/w/index.php?title=Socket_FP7&action=edit&redlink=1" class="new" title="Socket FP7 (page does not exist)">FP7</a> (2022)</li> <li><a href="/w/index.php?title=Socket_FP8&action=edit&redlink=1" class="new" title="Socket FP8 (page does not exist)">FP8</a></li> <li><a href="/w/index.php?title=Socket_FL1&action=edit&redlink=1" class="new" title="Socket FL1 (page does not exist)">FL1</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Server sockets</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_940" title="Socket 940">940</a></li> <li><a href="/wiki/Socket_F" title="Socket F">F</a> (2006)</li> <li><a href="/wiki/Socket_F%2B" title="Socket F+">F+</a></li> <li><a href="/wiki/AMD_Socket_G3" title="AMD Socket G3">G3</a> (not released)</li> <li><a href="/wiki/Socket_G34" title="Socket G34">G34</a></li> <li><a href="/wiki/Socket_C32" title="Socket C32">C32</a> (2010)</li> <li><a href="/wiki/Socket_SP3" title="Socket SP3">SP3</a> (2017)</li> <li><a href="/w/index.php?title=Socket_SP4&action=edit&redlink=1" class="new" title="Socket SP4 (page does not exist)">SP4</a> (2018)</li> <li><a href="/wiki/Socket_SP5" title="Socket SP5">SP5</a> (2022)</li> <li><a href="/wiki/Socket_SP6" title="Socket SP6">SP6</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Combined sockets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_A" title="Socket A">Socket A</a> (2000)</li> <li><a href="/wiki/Socket_754" title="Socket 754">754</a> (2003)</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="ATI_/_AMD_chipsets157" style="font-size:114%;margin:0 4em"><a class="mw-selflink selflink">ATI / AMD chipsets</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_ATI_chipsets" title="List of ATI chipsets">ATI chipsets</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>IGP 300 series/RX380</li> <li><a href="/wiki/Xpress_200" title="Xpress 200">Radeon Xpress 200</a></li> <li><a href="/wiki/Xpress_3200" title="Xpress 3200">CrossFire Xpress 3200</a></li> <li><a href="/wiki/AMD_690_chipset_series#Radeon_Xpress_1250" title="AMD 690 chipset series">Radeon Xpress 1250</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">AMD chipsets</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">480X/570X/580X</a></li> <li><a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">690 Series</a></li> <li><a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">7-Series</a></li> <li><a href="/wiki/AMD_800_chipset_series" title="AMD 800 chipset series">8-Series</a></li> <li><a href="/wiki/AMD_900_chipset_series" title="AMD 900 chipset series">9-Series</a></li> <li><a class="mw-selflink-fragment" href="#Fusion_controller_hubs_(FCH)">Fusion Controller Hubs</a></li> <li><a class="mw-selflink-fragment" href="#AM4_chipsets">AM4 chipsets</a></li> <li><a class="mw-selflink-fragment" href="#TR4_chipsets">TR4 chipsets</a></li> <li><a class="mw-selflink-fragment" href="#sTRX4_chipsets">sTRX4 chipsets</a></li> <li><a class="mw-selflink-fragment" href="#sWRX8_chipsets">sWRX8 chipsets</a></li> <li><a class="mw-selflink-fragment" href="#AM5_chipsets">AM5 chipsets</a></li> <li><a class="mw-selflink-fragment" href="#sTR5_chipsets">sTR5 chipsets</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Combined means that the given socket is supported by all platforms, including desktop, mobile, and server.</div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="AMD_processors178" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:AMD_processors" title="Template:AMD processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_processors" title="Template talk:AMD processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_processors" title="Special:EditPage/Template:AMD processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_processors178" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_AMD_processors" title="List of AMD processors">AMD processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_AMD_processors" title="List of AMD processors">Processors</a> <ul><li><a href="/wiki/List_of_AMD_K5_processors" title="List of AMD K5 processors">K5</a></li> <li><a href="/wiki/List_of_AMD_K6_processors" title="List of AMD K6 processors">K6</a></li> <li><a href="/wiki/List_of_AMD_Athlon_processors" title="List of AMD Athlon processors">Athlon</a> <ul><li><a href="/wiki/List_of_AMD_Athlon_XP_processors" title="List of AMD Athlon XP processors">XP</a></li> <li><a href="/wiki/List_of_AMD_Athlon_64_processors" title="List of AMD Athlon 64 processors">64</a></li> <li><a href="/wiki/List_of_AMD_Athlon_X2_processors" title="List of AMD Athlon X2 processors">X2</a></li> <li><a href="/wiki/List_of_AMD_Athlon_II_processors" title="List of AMD Athlon II processors">II</a></li></ul></li> <li><a href="/wiki/List_of_AMD_Phenom_processors" title="List of AMD Phenom processors">Phenom</a></li> <li><a href="/wiki/List_of_AMD_FX_processors" title="List of AMD FX processors">FX</a></li> <li><a href="/wiki/List_of_AMD_Ryzen_processors" title="List of AMD Ryzen processors">Ryzen</a></li> <li><a href="/wiki/List_of_AMD_Duron_processors" title="List of AMD Duron processors">Duron</a></li> <li><a href="/wiki/List_of_AMD_Sempron_processors" title="List of AMD Sempron processors">Sempron</a></li> <li><a href="/wiki/List_of_AMD_Turion_processors" title="List of AMD Turion processors">Turion</a></li> <li><a href="/wiki/List_of_AMD_Opteron_processors" title="List of AMD Opteron processors">Opteron</a></li> <li><a href="/wiki/List_of_AMD_Epyc_processors" class="mw-redirect" title="List of AMD Epyc processors">Epyc</a></li></ul></li> <li><a href="/wiki/List_of_AMD_processors_with_3D_graphics" title="List of AMD processors with 3D graphics">APUs</a></li> <li><a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">Microarchitectures</a></li> <li><a class="mw-selflink selflink">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K5" title="AMD K5">K5</a></li> <li><a href="/wiki/AMD_K6" title="AMD K6">K6</a></li> <li><a href="/wiki/Athlon" title="Athlon">Athlon/K7</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">x86-64 desktop</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K8" title="AMD K8">K8</a></li> <li><a href="/wiki/AMD_K9" title="AMD K9">K9</a></li> <li><a href="/wiki/AMD_10h" title="AMD 10h">K10 (aka 10h)</a></li> <li>15h <ul><li><a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a></li> <li><a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a></li> <li><a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a></li> <li><a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a></li></ul></li> <li><a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a> <ul><li><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">1st gen</a></li> <li><a href="/wiki/Zen%2B" title="Zen+">Zen+</a></li> <li><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a></li> <li><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a></li> <li><a href="/wiki/Zen_3%2B" class="mw-redirect" title="Zen 3+">Zen 3+</a></li> <li><a href="/wiki/Zen_4" title="Zen 4">Zen 4</a></li> <li><a href="/wiki/Zen_5" title="Zen 5">Zen 5</a></li> <li><i><a href="/wiki/Zen_6" title="Zen 6">Zen 6</a></i></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">x86-64 low-power</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat (aka 14h)</a></li> <li>16h <ul><li><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a></li> <li><a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_architecture_family#ARMv8-A" title="ARM architecture family">ARM64</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K12" title="AMD K12">K12 (aka 12h)</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Athlon" title="Athlon">Athlon</a></li> <li><a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></li> <li><a href="/wiki/Threadripper" title="Threadripper">Threadripper</a></li> <li><a href="/wiki/Epyc" title="Epyc">Epyc</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;background-color: #DDDDDD">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6">Early x86 (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Am286" class="mw-redirect" title="Am286">Am286</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Am386" title="Am386">Am386</a></li> <li><a href="/wiki/Am486" title="Am486">Am486</a></li> <li><a href="/wiki/Am5x86" title="Am5x86">Am5x86</a></li> <li><a href="/wiki/AMD_K5" title="AMD K5">K5</a></li> <li><a href="/wiki/AMD_K6" title="AMD K6">K6</a></li> <li><a href="/wiki/AMD_K6-2" title="AMD K6-2">K6-2</a></li> <li><a href="/wiki/AMD_K6-III" title="AMD K6-III">K6-III</a></li> <li><a href="/wiki/Athlon" title="Athlon">Athlon</a> <ul><li><a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">XP</a></li> <li><a href="/wiki/Athlon_MP" class="mw-redirect" title="Athlon MP">MP</a></li></ul></li> <li><a href="/wiki/Duron" title="Duron">Duron</a></li> <li><a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode</a></li> <li><a href="/wiki/AMD_%C3%89lan" title="AMD Élan">AMD Élan</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a> <ul><li><a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">X2</a></li> <li><a href="/wiki/Athlon_II" title="Athlon II">II</a></li></ul></li> <li><a href="/wiki/Sempron" title="Sempron">Sempron</a></li> <li><a href="/wiki/AMD_Turion" title="AMD Turion">Turion</a></li> <li><a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a> <ul><li><a href="/wiki/Phenom_II" title="Phenom II">II</a></li></ul></li> <li><a href="/wiki/AMD_FX" title="AMD FX">FX</a></li> <li><a href="/wiki/Opteron" title="Opteron">Opteron</a></li> <li><a href="/wiki/AMD_APU" title="AMD APU">A-series APUs</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am9080" title="AMD Am9080">Am9080</a></li> <li><a href="/wiki/AMD_Am2900" title="AMD Am2900">Am2900</a> <ul><li><a href="/wiki/List_of_AMD_Am2900_and_Am29000_families" title="List of AMD Am2900 and Am29000 families">list</a></li></ul></li> <li><a href="/wiki/AMD_Am29000" title="AMD Am29000">Am29000</a></li> <li><a href="/wiki/Alchemy_(microarchitecture)" class="mw-redirect" title="Alchemy (microarchitecture)">Alchemy</a> <ul><li><a href="/wiki/MIPS_architecture#MIPS32" title="MIPS architecture">MIPS32</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div><i>Italics</i> indicates an upcoming architecture.</div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235" /></div><div role="navigation" class="navbox" aria-labelledby="AMD_graphics16" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374" /><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231" /><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:AMD_graphics" title="Template:AMD graphics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_graphics" title="Template talk:AMD graphics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_graphics" title="Special:EditPage/Template:AMD graphics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_graphics16" style="font-size:114%;margin:0 4em"><a href="/wiki/AMD" title="AMD">AMD</a> graphics</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Radeon-brandList_of_GPUs_(GPU_features_template)_and_List_of_APUs_(APU_features_template)16" style="font-size:114%;margin:0 4em"><a href="/wiki/Radeon" title="Radeon">Radeon</a>-brand<br /><small><a href="/wiki/List_of_AMD_graphics_processing_units" title="List of AMD graphics processing units">List of GPUs</a> (<a href="/wiki/Template:AMD_GPU_features" title="Template:AMD GPU features">GPU features template</a>) and <a href="/wiki/List_of_AMD_processors_with_3D_graphics" title="List of AMD processors with 3D graphics">List of APUs</a> (<a href="/wiki/Template:AMD_APU_features" class="mw-redirect" title="Template:AMD APU features">APU features template</a>)</small></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Fixed pipeline</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ATI_Wonder" title="ATI Wonder">Wonder</a></li> <li><a href="/wiki/ATI_Mach" title="ATI Mach">Mach</a></li> <li><a href="/wiki/ATI_Rage" title="ATI Rage">Rage</a></li> <li><a href="/wiki/All-in-Wonder" title="All-in-Wonder">All-in-Wonder</a> (before 2000)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Vertex and fragment shaders</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_R100_series" title="Radeon R100 series">R100</a></li> <li><a href="/wiki/Radeon_R200_series" title="Radeon R200 series">R200</a></li> <li><a href="/wiki/Radeon_R300_series" title="Radeon R300 series">R300</a></li> <li><a href="/wiki/Radeon_R400_series" title="Radeon R400 series">R400</a></li> <li><a href="/wiki/Radeon_X1000_series" title="Radeon X1000 series">R500</a></li> <li><a href="/wiki/All-in-Wonder" title="All-in-Wonder">All-in-Wonder</a> (after 1999)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="TeraScale43" scope="row" class="navbox-group" style="width:1%"><a href="/wiki/TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_HD_2000_series" title="Radeon HD 2000 series">HD 2000</a></li> <li><a href="/wiki/Radeon_HD_3000_series" title="Radeon HD 3000 series">HD 3000</a></li> <li><a href="/wiki/Radeon_HD_4000_series" title="Radeon HD 4000 series">HD 4000</a></li> <li><a href="/wiki/Radeon_HD_5000_series" title="Radeon HD 5000 series">HD 5000</a></li> <li><a href="/wiki/Radeon_HD_6000_series" title="Radeon HD 6000 series">HD 6000</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Unified shaders & <a href="/wiki/Unified_Memory_Architecture" class="mw-redirect" title="Unified Memory Architecture">memory</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">GCN</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_HD_7000_series" title="Radeon HD 7000 series">HD 7000</a></li> <li><a href="/wiki/Radeon_HD_8000_series" title="Radeon HD 8000 series">HD 8000</a></li> <li><a href="/wiki/Radeon_200_series" title="Radeon 200 series">200</a></li> <li><a href="/wiki/Radeon_300_series" title="Radeon 300 series">300</a></li> <li><a href="/wiki/Radeon_400_series" title="Radeon 400 series">400</a></li> <li><a href="/wiki/Radeon_500_series" title="Radeon 500 series">500</a></li> <li><a href="/wiki/Radeon_RX_Vega_series" title="Radeon RX Vega series">RX Vega</a></li> <li><a href="/wiki/Radeon_600_series" title="Radeon 600 series">600</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_RX_5000_series" title="Radeon RX 5000 series">RX 5000</a></li> <li><a href="/wiki/Radeon_RX_6000_series" title="Radeon RX 6000 series">RX 6000</a></li> <li><a href="/wiki/Radeon_RX_7000_series" title="Radeon RX 7000 series">RX 7000</a></li> <li><a href="/wiki/Radeon_RX_9000_series" title="Radeon RX 9000 series">RX 9000</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Current_technologies_and_software16" style="font-size:114%;margin:0 4em">Current technologies and software</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Audio/Video acceleration</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder (UVD)</a></li> <li><a href="/wiki/Video_Coding_Engine" title="Video Coding Engine">Video Coding Engine (VCE)</a></li> <li><a href="/wiki/Video_Core_Next" title="Video Core Next">Video Core Next (VCN)</a></li> <li><a href="/wiki/AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">GPU technologies</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">Eyefinity</a></li> <li><a href="/wiki/FreeSync" title="FreeSync">FreeSync</a></li> <li><a href="/wiki/AMD_PowerTune" title="AMD PowerTune">PowerTune</a></li> <li><a href="/wiki/AMD_CrossFire" title="AMD CrossFire">CrossFire</a></li> <li><a href="/wiki/AMD_Hybrid_Graphics" title="AMD Hybrid Graphics">Hybrid Graphics</a></li> <li><a href="/wiki/HyperMemory" title="HyperMemory">HyperMemory</a></li> <li><a href="/wiki/HyperZ" title="HyperZ">HyperZ</a></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">HSA</a></li> <li><a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a> <ul><li><a href="/wiki/RDNA_2" title="RDNA 2">2</a></li> <li><a href="/wiki/RDNA_3" title="RDNA 3">3</a></li> <li><a href="/wiki/RDNA_4" title="RDNA 4">4</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Radeon_Software" class="mw-redirect" title="AMD Radeon Software">AMD Radeon Software</a> <ul><li><a href="/wiki/AMD_HD3D" title="AMD HD3D">HD3D</a></li></ul></li> <li><a href="/wiki/ROCm" title="ROCm">ROCm</a></li> <li><a href="/wiki/AMDGPU" class="mw-redirect" title="AMDGPU">AMDGPU</a></li> <li><a href="/wiki/GPUOpen" title="GPUOpen">GPUOpen</a> <ul><li><a href="/wiki/TressFX" title="TressFX">TressFX</a></li></ul></li> <li><a href="/wiki/HLSL2GLSL" title="HLSL2GLSL">HLSL2GLSL</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_APP_SDK" title="AMD APP SDK">AMD APP SDK</a></li> <li><a href="/wiki/AMD_Catalyst" class="mw-redirect" title="AMD Catalyst">Catalyst</a></li> <li><a href="/wiki/Close_to_Metal" title="Close to Metal">Close to Metal</a></li> <li><a href="/wiki/AMD_CodeAnalyst" title="AMD CodeAnalyst">CodeAnalyst</a></li> <li><a href="/wiki/AMD_GPU_PerfStudio" class="mw-redirect" title="AMD GPU PerfStudio">GPU PerfStudio</a></li> <li><a href="/wiki/Mantle_(API)" title="Mantle (API)">Mantle</a></li> <li><a href="/wiki/CodeXL" title="CodeXL">CodeXL</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Other_brands_and_products16" style="font-size:114%;margin:0 4em">Other brands and products</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Workstation" title="Workstation">Workstations</a> <br />& <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_Pro" title="Radeon Pro">Radeon Pro</a></li> <li><a href="/wiki/Radeon_Instinct" class="mw-redirect" title="Radeon Instinct">Radeon Instinct</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_FirePro" title="AMD FirePro">FireGL/FirePro</a></li> <li><a href="/wiki/AMD_FireMV" title="AMD FireMV">FireMV</a></li> <li><a href="/wiki/AMD_FireStream" title="AMD FireStream">FireStream</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Video_game_console" title="Video game console">Consoles</a><br />& <a href="/wiki/Handheld_PC" title="Handheld PC">handheld PCs</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Flipper_(graphics_chip)" class="mw-redirect" title="Flipper (graphics chip)">Flipper</a> (<a href="/wiki/GameCube" title="GameCube">GameCube</a>)</li> <li><a href="/wiki/Xenos_(graphics_chip)" title="Xenos (graphics chip)">Xenos</a> (<a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a>)</li> <li><a href="/wiki/Hollywood_(graphics_chip)" title="Hollywood (graphics chip)">Hollywood</a> (<a href="/wiki/Wii" title="Wii">Wii</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_2" title="Graphics Core Next">Liverpool</a> (<a href="/wiki/PlayStation_4" title="PlayStation 4">PlayStation 4</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_2" title="Graphics Core Next">Durango</a> (<a href="/wiki/Xbox_One" title="Xbox One">Xbox One</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_4" title="Graphics Core Next">Neo</a> (<a href="/wiki/PlayStation_4_Pro" class="mw-redirect" title="PlayStation 4 Pro">PlayStation 4 Pro</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_4" title="Graphics Core Next">Scorpio</a> (<a href="/wiki/Xbox_One_X" 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