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mw-first-heading"><span class="mw-page-title-main">Soft microprocessor</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. 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href="https://fr.wikipedia.org/wiki/Processeur_softcore" title="Processeur softcore – French" lang="fr" hreflang="fr" data-title="Processeur softcore" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%86%8C%ED%94%84%ED%8A%B8_%EB%A7%88%EC%9D%B4%ED%81%AC%EB%A1%9C%ED%94%84%EB%A1%9C%EC%84%B8%EC%84%9C" title="소프트 마이크로프로세서 – Korean" lang="ko" hreflang="ko" data-title="소프트 마이크로프로세서" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hi mw-list-item"><a href="https://hi.wikipedia.org/wiki/%E0%A4%A8%E0%A4%AE%E0%A5%8D%E0%A4%B0_%E0%A4%AA%E0%A5%8D%E0%A4%B0%E0%A5%8B%E0%A4%B8%E0%A5%87%E0%A4%B8%E0%A4%B0" title="नम्र प्रोसेसर – Hindi" lang="hi" hreflang="hi" data-title="नम्र प्रोसेसर" data-language-autonym="हिन्दी" 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0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Missing_information plainlinks metadata ambox ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/en/thumb/6/6c/Wiki_letter_w.svg/44px-Wiki_letter_w.svg.png" decoding="async" width="44" height="44" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/6/6c/Wiki_letter_w.svg/66px-Wiki_letter_w.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/6/6c/Wiki_letter_w.svg/88px-Wiki_letter_w.svg.png 2x" data-file-width="44" data-file-height="44" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This <b>is missing information</b> about three <a href="/wiki/OpenPOWER" class="mw-redirect" title="OpenPOWER">OpenPOWER</a> cores, one Moxie core, both at RTL level.<span class="hide-when-compact"> Please expand the to include this information. Further details may exist on the <a href="/wiki/Talk:Soft_microprocessor" title="Talk:Soft microprocessor">talk page</a>.</span> <span class="date-container"><i>(<span class="date">July 2020</span>)</i></span></div></td></tr></tbody></table> <p>A <b>soft microprocessor</b> (also called softcore microprocessor or a <b>soft processor</b>) is a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> core that can be wholly implemented using <a href="/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a>. It can be implemented via different <a href="/wiki/Semiconductor" title="Semiconductor">semiconductor</a> devices containing programmable logic (e.g., <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>, <a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a>), including both high-end and commodity variations.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p>Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In those <a href="/wiki/Multi-core" class="mw-redirect" title="Multi-core">multi-core</a> systems, rarely used resources can be shared between all the cores in a cluster. </p><p>While many people put exactly one soft microprocessor on a FPGA, a sufficiently large FPGA can hold two or more soft microprocessors, resulting in a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a>. The number of soft processors on a single FPGA is limited only by the size of the FPGA.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Some people have put dozens or hundreds of soft microprocessors on a single FPGA.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> This is one way to implement <a href="/wiki/Massively_parallel" title="Massively parallel">massive parallelism</a> in computing and can likewise be applied to <a href="/wiki/In-memory_processing" title="In-memory processing">in-memory computing</a>. </p><p>A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Core_comparison">Core comparison</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Soft_microprocessor&action=edit&section=1" title="Edit section: Core comparison"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable"> <tbody><tr> <th>Processor </th> <th>Developer </th> <th>Open source </th> <th>Bus support </th> <th>Notes </th> <th>Project home </th> <th>Description language </th></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> instruction set architecture</i> </td></tr> <tr> <td><a href="/wiki/Amber_(processor_core)" class="mw-redirect" title="Amber (processor core)">Amber</a> </td> <td>Conor Santifort </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">LGPLv2.1 </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td><a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARMv2a</a> 3-stage or 5-stage pipeline </td> <td><a rel="nofollow" class="external text" href="https://opencores.org/project/amber">Project page at Opencores</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/Cortex-M1" class="mw-redirect" title="Cortex-M1">Cortex-M1</a> </td> <td><a href="/wiki/ARM_Holdings" class="mw-redirect" title="ARM Holdings">ARM</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td><a rel="nofollow" class="external autonumber" href="http://www.arm.com/products/system-ip/interconnect/index.php">[6]</a> </td> <td>70–200<span class="nowrap"> </span>MHz, 32-bit RISC </td> <td><a rel="nofollow" class="external autonumber" href="http://www.arm.com/products/CPUs/ARM_Cortex-M1.html">[7]</a> </td> <td>Verilog </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a> instruction set architecture</i> </td></tr> <tr> <td>Navré </td> <td>Sébastien Bourdeauducq </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Direct SRAM </td> <td><a href="/wiki/Atmel_AVR" class="mw-redirect" title="Atmel AVR">Atmel AVR</a>-compatible 8-bit RISC </td> <td><a rel="nofollow" class="external text" href="http://opencores.org/project,navre">Project page at Opencores</a> </td> <td>Verilog </td></tr> <tr> <td>pAVR </td> <td>Doru Cuturela </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td><a href="/wiki/Atmel_AVR" class="mw-redirect" title="Atmel AVR">Atmel AVR</a>-compatible 8-bit RISC </td> <td><a rel="nofollow" class="external text" href="http://opencores.org/project,pavr">Project page at Opencores</a> </td> <td>VHDL </td></tr> <tr> <td>softavrcore </td> <td>Andras Pal </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM) </td> <td><a href="/wiki/Atmel_AVR" class="mw-redirect" title="Atmel AVR">Atmel AVR</a>-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included </td> <td><a rel="nofollow" class="external text" href="http://opencores.org/project/softavrcore">Project page at Opencores</a> </td> <td>Verilog </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a> instruction set architecture</i> </td></tr> <tr> <td><a href="/w/index.php?title=AEMB&action=edit&redlink=1" class="new" title="AEMB (page does not exist)">AEMB</a> </td> <td>Shawn Tan </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>MicroBlaze EDK 3.2 compatible </td> <td><a rel="nofollow" class="external text" href="http://www.aeste.my/aemb">AEMB</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a> </td> <td><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>PLB, OPB, FSL, LMB, AXI4 </td> <td> </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030430214925/http://www.xilinx.com/microblaze/">Xilinx MicroBlaze</a> </td> <td> </td></tr> <tr> <td><a href="/w/index.php?title=OpenFire_Soft_Processor&action=edit&redlink=1" class="new" title="OpenFire Soft Processor (page does not exist)">OpenFire</a> </td> <td>Virginia Tech CCM Lab </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>OPB, FSL </td> <td>Binary compatible with the MicroBlaze </td> <td><a rel="nofollow" class="external autonumber" href="https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html">[8]</a><sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </td> <td>Verilog </td></tr> <tr> <td><a href="/w/index.php?title=SecretBlaze&action=edit&redlink=1" class="new" title="SecretBlaze (page does not exist)">SecretBlaze</a> </td> <td>LIRMM, University of Montpellier / CNRS </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>MicroBlaze ISA, VHDL </td> <td><a rel="nofollow" class="external text" href="http://www.lirmm.fr/ADAC/?page_id=462">SecretBlaze</a> </td> <td>VHDL </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/MCS-51" title="MCS-51">MCS-51</a> instruction set architecture</i> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.microcorelabs.com">MCL51</a> </td> <td><a href="/w/index.php?title=MicroCore_Labs&action=edit&redlink=1" class="new" title="MicroCore Labs (page does not exist)">MicroCore Labs</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Ultra-small-footprint microsequencer-based 8051 core </td> <td>312 Artix-7 LUTs. Quad-core 8051 version is 1227 LUTs. </td> <td><a rel="nofollow" class="external text" href="http://www.microcorelabs.com">MCL51 Core</a> </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131008041359/http://wiki.altium.com/display/ADOH/TSK51x+MCU">TSK51/52</a> </td> <td><a href="/wiki/Altium" title="Altium">Altium</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Royalty-free </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> / <a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">Intel 8051</a> </td> <td>8-bit <a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">Intel 8051</a> instruction set compatible, lower clock cycle alternative </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design">Embedded Design on Altium Wiki</a> </td> <td> </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> instruction set architecture</i> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.cl.cam.ac.uk/research/security/ctsrd/beri/">BERI</a> </td> <td><a href="/wiki/University_of_Cambridge" title="University of Cambridge">University of Cambridge</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">BSD </td> <td> </td> <td><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> </td> <td><a rel="nofollow" class="external text" href="http://www.cl.cam.ac.uk/research/security/ctsrd/beri/">Project page</a> </td> <td><a href="/wiki/Bluespec" title="Bluespec">Bluespec</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.dossmatik.de/mais-cpu.html">Dossmatik</a> </td> <td><a href="/w/index.php?title=Ren%C3%A9_Doss&action=edit&redlink=1" class="new" title="René Doss (page does not exist)">René Doss</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CC BY-NC 3.0, except <i>commercial applicants have to pay a licence fee</i>. </td> <td>Pipelined bus </td> <td>MIPS I instruction set pipeline stages </td> <td><a rel="nofollow" class="external text" href="http://www.dossmatik.de/mais-cpu.html">Dossmatik</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131020113429/http://wiki.altium.com/display/ADOH/TSK3000A">TSK3000A</a> </td> <td><a href="/wiki/Altium" title="Altium">Altium</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Royalty-free </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>32-bit <a href="/wiki/R3000" title="R3000">R3000</a>-style RISC modified Harvard-architecture CPU </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160306202550/http://wiki.altium.com/display/adoh/processor-based+fpga+design">Embedded Design on Altium Wiki</a> </td> <td> </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a> instruction set architecture</i> </td></tr> <tr> <td><a href="/w/index.php?title=PacoBlaze&action=edit&redlink=1" class="new" title="PacoBlaze (page does not exist)">PacoBlaze</a> </td> <td>Pablo Bleyer </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td>Compatible with the PicoBlaze processors </td> <td><a rel="nofollow" class="external text" href="http://bleyer.org/pacoblaze">PacoBlaze</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a> </td> <td><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td> </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030501203653/http://www.xilinx.com/picoblaze/">Xilinx PicoBlaze</a> </td> <td>VHDL, Verilog </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/RISC-V" title="RISC-V">RISC-V</a> instruction set architecture</i> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/f32c/f32c">f32c</a> </td> <td>University of Zagreb </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">BSD </td> <td>AXI, SDRAM, SRAM </td> <td>32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain </td> <td><a rel="nofollow" class="external text" href="https://github.com/f32c/f32c">f32c</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/stnolting/neorv32">NEORV32</a> </td> <td>Stephan Nolting </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">BSD </td> <td>Wishbone b4, AXI4 </td> <td>rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain </td> <td><a rel="nofollow" class="external text" href="https://github.com/stnolting/neorv32">GitHub</a> <a rel="nofollow" class="external text" href="https://opencores.org/projects/neorv32">OpenCores</a> </td> <td>VHDL </td></tr> <tr> <td>VexRiscv </td> <td>SpinalHDL </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>AXI4 / Avalon </td> <td>32-bit, RISC-V, up to 340<span class="nowrap"> </span>MHz on Artix 7. Up to 1.44<span class="nowrap"> </span>DMIPS/MHz. </td> <td><a rel="nofollow" class="external free" href="https://github.com/SpinalHDL/VexRiscv">https://github.com/SpinalHDL/VexRiscv</a> </td> <td>VHDLVerilog (SpinalHDL) </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/SPARC" title="SPARC">SPARC</a> instruction set architecture</i> </td></tr> <tr> <td><a href="/wiki/LEON" title="LEON">LEON2(-FT)</a> </td> <td><a href="/wiki/European_Space_Agency" title="European Space Agency">ESA</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>AMBA2 </td> <td>SPARC V8 </td> <td><a rel="nofollow" class="external text" href="http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html">ESA</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/LEON" title="LEON">LEON3/4</a> </td> <td>Aeroflex Gaisler </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>AMBA2 </td> <td>SPARC V8 </td> <td><a rel="nofollow" class="external text" href="http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=156&Itemid=104">Aeroflex Gaisler</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://parallel.princeton.edu/openpiton/specs.html">OpenPiton</a> </td> <td>Princeton Parallel Group </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a> <a href="/wiki/SPARC" title="SPARC">SPARC V9</a> </td> <td><a rel="nofollow" class="external text" href="http://parallel.princeton.edu/openpiton/specs.html">OpenPiton</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/OpenSPARC" title="OpenSPARC">OpenSPARC T1</a> </td> <td><a href="/wiki/Sun_Microsystems" title="Sun Microsystems">Sun</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td>64-bit </td> <td><a rel="nofollow" class="external text" href="http://www.opensparc.net/opensparc-t1/index.html">OpenSPARC.net</a> </td> <td>Verilog </td></tr> <tr> <td>Tacus/PIPE5 </td> <td>TemLib </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Pipelined bus </td> <td>SPARC V8 </td> <td><a rel="nofollow" class="external text" href="http://temlib.org">TEMLIB</a> </td> <td>VHDL </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/X86" title="X86">x86</a> instruction set architecture</i> </td></tr> <tr> <td>CPU86 </td> <td>HT-Lab </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td> </td> <td>8088-compatible CPU in VHDL </td> <td><a rel="nofollow" class="external text" href="http://www.ht-lab.com/cpu86.htm">cpu86</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.microcorelabs.com">MCL86</a> </td> <td><a href="/w/index.php?title=MicroCore_Labs&action=edit&redlink=1" class="new" title="MicroCore Labs (page does not exist)">MicroCore Labs</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>8088 BIU provided. Others easy to create. </td> <td>Cycle accurate 8088/8086 implemented with a microsequencer. Less than 2% utilization of Kintex-7. </td> <td><a rel="nofollow" class="external text" href="http://www.microcorelabs.com">MCL86 Core</a> </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.jamieiles.com/80186/">s80x86</a> </td> <td>Jamie Iles </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">GPLv3 </td> <td>Custom </td> <td>80186-compatible GPLv3 core </td> <td><a rel="nofollow" class="external text" href="https://www.jamieiles.com/80186/">s80x86</a> </td> <td>SystemVerilog </td></tr> <tr> <td><a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a> </td> <td>Zeus Gómez Marmolejo </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>x86 PC clone </td> <td><a rel="nofollow" class="external text" href="https://archive.today/20130112150552/http://zet.aluzina.org/">Zet</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/w/index.php?title=Ao486_(hardware)&action=edit&redlink=1" class="new" title="Ao486 (hardware) (page does not exist)">ao486</a> </td> <td>Aleksander Osman </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">3-Clause BSD </td> <td>Avalon </td> <td>i486 SX compatible core </td> <td><a rel="nofollow" class="external text" href="https://github.com/alfikpl/ao486">ao486</a> </td> <td>Verilog </td></tr> <tr> <td colspan="7" align="center"><i>based on the <a href="/wiki/Power_ISA" title="Power ISA">PowerPC/Power</a> instruction set architecture</i> </td></tr> <tr> <td><a href="/wiki/PowerPC_400#PowerPC_405" title="PowerPC 400">PowerPC 405S</a> </td> <td>IBM </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a> </td> <td>32-bit PowerPC v.2.03 Book E </td> <td><a href="/wiki/IBM" title="IBM">IBM</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/PowerPC_400#PowerPC_440" title="PowerPC 400">PowerPC 440S</a> </td> <td>IBM </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a> </td> <td>32-bit PowerPC v.2.03 Book E </td> <td><a href="/wiki/IBM" title="IBM">IBM</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/PowerPC_400#PowerPC_470" title="PowerPC 400">PowerPC 470S</a> </td> <td>IBM </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td><a href="/wiki/CoreConnect" title="CoreConnect">CoreConnect</a> </td> <td>32-bit PowerPC v.2.05 Book E </td> <td><a href="/wiki/IBM" title="IBM">IBM</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/OpenPower_Microwatt" class="mw-redirect" title="OpenPower Microwatt">Microwatt</a> </td> <td>IBM/OpenPOWER </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CC-BY 4.0 </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>64-bit PowerISA 3.0 proof of concept </td> <td><a rel="nofollow" class="external text" href="https://github.com/antonblanchard/microwatt">Microwatt @ Github</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/OpenPower_Microwatt#Chiselwatt" class="mw-redirect" title="OpenPower Microwatt">Chiselwatt</a> </td> <td>IBM/OpenPOWER </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CC-BY 4.0 </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>64-bit PowerISA 3.0 </td> <td><a rel="nofollow" class="external text" href="https://github.com/antonblanchard/chiselwatt">Chiselwatt @ Github</a> </td> <td>Chisel </td></tr> <tr> <td><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a> </td> <td><a rel="nofollow" class="external text" href="https://libre-soc.org">Libre-SoC.org</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">BSD/LGPLv2+ </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions </td> <td><a rel="nofollow" class="external text" href="https://libre-soc.org">Libre-SoC.org</a> </td> <td>python/nMigen </td></tr> <tr> <td><a href="/wiki/IBM_A2#A2I" title="IBM A2">A2I</a> </td> <td>IBM/OpenPOWER </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CC-BY 4.0 </td> <td>Custom PBus </td> <td>64-bit PowerPC 2.6 Book E. In order core </td> <td><a rel="nofollow" class="external text" href="https://github.com/openpower-cores/a2i">A2I @ Github</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/IBM_A2#A2O" title="IBM A2">A2O</a> </td> <td>IBM/OpenPOWER </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">CC-BY 4.0 </td> <td>Custom PBus </td> <td>64-bit PowerPC 2.7 Book E. Out of order core </td> <td><a rel="nofollow" class="external text" href="https://github.com/openpower-cores/a2o">A2O @ Github</a> </td> <td>Verilog </td></tr> <tr> <td colspan="7" align="center"><i>Other architectures</i> </td></tr> <tr> <td><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a> </td> <td><a href="/wiki/Synopsys#ARC_International" title="Synopsys">ARC International</a>, <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td>16/32/64-bit ISA RISC </td> <td><a rel="nofollow" class="external text" href="https://www.synopsys.com/designware-ip/processor-solutions.html">DesignWare ARC</a> </td> <td>Verilog </td></tr> <tr> <td>ERIC5 </td> <td>Entner Electronics </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td> </td> <td>9-bit RISC, very small size, C-programmable </td> <td><a rel="nofollow" class="external text" href="http://www.entner-electronics.com/tl/index.php/eric5.html">ERIC5</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html">Archived</a> 2016-03-05 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/howerj/forth-cpu">H2 CPU</a> </td> <td>Richard James Howe </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">MIT </td> <td>Custom </td> <td>16-bit Stack Machine, designed to execute Forth directly, small </td> <td><a rel="nofollow" class="external text" href="https://github.com/howerj/forth-cpu">H2 CPU</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a> </td> <td><a rel="nofollow" class="external text" href="http://www.fpga-cores.com/">FPGA Cores</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>Custom </td> <td>32-bit RISC-V M Extension, SoC defined by C++ </td> <td><a rel="nofollow" class="external text" href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/Java_optimized_processor" class="mw-redirect" title="Java optimized processor">JOP</a> </td> <td>Martin Schoeberl </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/w/index.php?title=SimpCon&action=edit&redlink=1" class="new" title="SimpCon (page does not exist)">SimpCon</a> / <a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> (extension) </td> <td>Stack-oriented, hard real-time support, executing <a href="/wiki/Java_bytecode" title="Java bytecode">Java bytecode</a> directly </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20190417225405/http://www.jopdesign.com/">Jop</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a> </td> <td><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td> </td> <td><a rel="nofollow" class="external text" href="http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx">LatticeMico8</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a> </td> <td><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td> </td> <td><a rel="nofollow" class="external text" href="http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm">LatticeMico32</a> </td> <td>Verilog </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://lxp32.github.io/">LXP32</a> </td> <td>Alex Kuznetsov </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">MIT </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>32-bit, 3-stage pipeline, <a href="/wiki/Register_file" title="Register file">register file</a> based on block RAM </td> <td><a rel="nofollow" class="external text" href="https://lxp32.github.io/">lxp32</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/MicroCoreLabs/Projects">MCL65</a> </td> <td><a href="/w/index.php?title=MicroCore_Labs&action=edit&redlink=1" class="new" title="MicroCore Labs (page does not exist)">MicroCore Labs</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Ultra-small-footprint microsequencer-based 6502 core </td> <td>252 Spartan-7 LUTs. Clock cycle-exact. </td> <td><a rel="nofollow" class="external text" href="https://github.com/MicroCoreLabs/Projects">MCL65 Core</a> </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://mrisc32.bitsnbites.eu/">MRISC32-A1</a> </td> <td>Marcus Geelnard </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a>, B4/pipelined </td> <td>32-bit RISC/Vector CPU implementing the MRISC32 ISA </td> <td><a rel="nofollow" class="external text" href="https://mrisc32.bitsnbites.eu/">MRISC32</a> </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/stnolting/neo430">NEO430</a> </td> <td>Stephan Nolting </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Wishbone (Avalon, AXI4-Lite) </td> <td>16-bit MSP430 ISA-compatible, very small size, many peripherals, highly customizable </td> <td><a rel="nofollow" class="external text" href="https://github.com/stnolting/neo430">NEO430</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a>, <a href="/wiki/Nios_II" title="Nios II">Nios II</a> </td> <td><a href="/wiki/Altera" title="Altera">Altera</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>Avalon </td> <td> </td> <td><a rel="nofollow" class="external text" href="https://web.archive.org/web/20101225092752/http://www.altera.com/products/ip/processors/nios2/ni2-index.html">Altera Nios II</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> </td> <td><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>32-bit; done in ASIC, Actel, Altera, Xilinx FPGA. </td> <td><a rel="nofollow" class="external autonumber" href="https://openrisc.io/">[9]</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/w/index.php?title=SpartanMC&action=edit&redlink=1" class="new" title="SpartanMC (page does not exist)">SpartanMC</a> </td> <td>TU Darmstadt / TU Dresden </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Custom (<a href="/wiki/Advanced_eXtensible_Interface" title="Advanced eXtensible Interface">AXI</a> support in development) </td> <td>18-bit ISA (GNU Binutils / GCC support in development) </td> <td><a rel="nofollow" class="external text" href="http://www.spartanmc.de">SpartanMC</a> </td> <td>Verilog </td></tr> <tr> <td>SYNPIC12 </td> <td>Miguel Angel Ajo Pelayo </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">MIT </td> <td> </td> <td>PIC12F compatible, program synthesised in gates </td> <td><a rel="nofollow" class="external text" href="http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core">nbee.es</a> </td> <td>VHDL </td></tr> <tr> <td><a href="/w/index.php?title=Xr16&action=edit&redlink=1" class="new" title="Xr16 (page does not exist)">xr16</a> </td> <td>Jan Gray </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td>XSOC abstract bus </td> <td>16-bit RISC CPU and SoC featured in Circuit Cellar Magazine #116-118 </td> <td><a rel="nofollow" class="external text" href="http://www.fpgacpu.org/xsoc/index.html">XSOC/xr16</a> </td> <td>Schematic </td></tr> <tr> <td><a href="/w/index.php?title=YASEP_(architecture)&action=edit&redlink=1" class="new" title="YASEP (architecture) (page does not exist)">YASEP</a> </td> <td>Yann Guidon </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">AGPLv3 </td> <td>Direct SRAM </td> <td>16 or 32 bits, RTL in <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121207045204/http://yasep.org/VHDL/">VHDL</a> & <a rel="nofollow" class="external text" href="http://yasep.org/#!ASM/impASM#examples/keywords.yas">asm</a> in <a href="/wiki/JavaScript" title="JavaScript">JS</a>, microcontroller subset : ready </td> <td><a rel="nofollow" class="external text" href="http://yasep.org">yasep.org</a> (<a rel="nofollow" class="external text" href="http://www.mozilla.com/">Firefox</a> required) </td> <td>VHDL </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://zipcpu.com/about/zipcpu.html">ZipCPU</a> </td> <td><a rel="nofollow" class="external text" href="http://zipcpu.com/about/gisselquist-technology.html">Gisselquist Technology</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">GPLv3 </td> <td>Wishbone, B4/pipelined </td> <td>32-bit CPU targeted for minimal FPGA resource usage </td> <td><a rel="nofollow" class="external text" href="http://zipcpu.com/about/zipcpu.html">zipcpu.com</a> </td> <td>Verilog </td></tr> <tr> <td><a href="/wiki/ZPU_(microprocessor)" class="mw-redirect" title="ZPU (microprocessor)">ZPU</a> </td> <td>Zylin AS </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td><a href="/wiki/Wishbone_(computer_bus)" title="Wishbone (computer bus)">Wishbone</a> </td> <td>Stack based CPU, configurable 16/32 bit datapath, <a href="/wiki/ECos" title="ECos">eCos</a> support </td> <td><a rel="nofollow" class="external text" href="http://opensource.zylin.com/zpu.htm">Zylin CPU</a> </td> <td>VHDL </td></tr> <tr> <td>RISC5 </td> <td>Niklaus Wirth </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>Custom </td> <td>Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board. </td> <td><a rel="nofollow" class="external text" href="http://www.projectoberon.com/">www.projectoberon.com/</a> </td> <td>Verilog </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Soft_microprocessor&action=edit&section=2" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System-on-a-chip</a> (SoC) <ul><li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network-on-a-chip</a> (NoC)</li></ul></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a></li> <li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a></li></ul></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Soft_microprocessor&action=edit&section=3" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external free" href="http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html">http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html">Archived</a> 2018-10-13 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> "Zet soft core running Windows 3.0" by Andrew Felch 2011</span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration 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Archived from <a rel="nofollow" class="external text" href="https://www.embedded.com/print/4015159">the original</a> on 2016-10-13.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%22Using+FPGAs+to+avoid+microprocessor+obsolescence%22&rft.date=2008&rft.au=John+Swan&rft.au=Tomek+Krzyzak.&rft_id=http%3A%2F%2Fwww.embedded.com%2Fprint%2F4015159&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASoft+microprocessor" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFStaff2010" class="citation web cs1">Staff (2010-02-03). <a rel="nofollow" class="external text" href="https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/">"FPGA processor IP needs to be supported"</a>. <i>Electronics Weekly</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2019-04-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Electronics+Weekly&rft.atitle=FPGA+processor+IP+needs+to+be+supported&rft.date=2010-02-03&rft.au=Staff&rft_id=https%3A%2F%2Fwww.electronicsweekly.com%2Fnews%2Fproducts%2Ffpga-news%2Ffpga-processor-ip-needs-to-be-supported-2010-02%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASoft+microprocessor" class="Z3988"></span></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://opencores.org/project,openfire_core,overview">"Overview :: OpenFire Processor Core :: OpenCores"</a>.</cite><span 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href="https://web.archive.org/web/20070615082550/http://www.ews.uiuc.edu/~pdabrows/soft_processor_comparison.html">Detailed Comparison of 12 Soft Microprocessors</a></li> <li><a rel="nofollow" class="external text" href="http://www.fpgacpu.org">FPGA CPU News</a></li> <li><a rel="nofollow" class="external text" href="http://f-cpu.org">Freedom CPU website</a></li> <li><a rel="nofollow" class="external text" href="http://opencores.org/projects">Microprocessor cores</a> on Opencores.org (Expand the "Processor" tab)</li> <li><a rel="nofollow" class="external text" href="http://www.niktech.com">NikTech</a> 32 bit RISC Microprocessor MANIK.</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output 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block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a class="mw-selflink selflink">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a 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