CINXE.COM

<!DOCTYPE html> <html> <head> <meta charset="utf-8"> <meta http-equiv="X-UA-Compatible" content="IE=edge"> <meta name="viewport" content="width=device-width, initial-scale=1"> <title>About the ZipCPU</title> <meta name="description" content="The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design. "> <link rel="shortcut icon" type="image/x-icon" href="/img/GT.ico"> <link rel="stylesheet" href="/css/main.css"> <link rel="canonical" href="https://zipcpu.com/about/zipcpu.html"> <link rel="alternate" type="application/rss+xml" title="The ZipCPU by Gisselquist Technology" href="https://zipcpu.com/feed.xml"> </head> <body>  <script async src="https://www.googletagmanager.com/gtag/js?id=G-4ZK7HKHSVW"></script> <script> window.dataLayer = window.dataLayer || []; function gtag(){dataLayer.push(arguments);} gtag('js', new Date()); gtag('config', 'G-4ZK7HKHSVW'); </script> <header class="site-header"> <div id="banner"> <a href="/"><picture> <img height=120 id="site-logo" src="/img/fullgqtech.png" alt="Gisselquist Technology, LLC"> </picture></A> </div> <div class="site-nav"> <ul> <li><a HREF="/">Main/Blog</a> <li><a HREF="/about/">About Us</a> <li><a HREF="/fpga-hell.html">FPGA Hell</a> <li><a HREF="/tutorial/">Tutorial</a> <li><a HREF="/tutorial/formal.html">Formal training</a> <li><a HREF="/quiz/quizzes.html">Quizzes</a> <li><a HREF="/projects.html">Projects</a> <li><a HREF="/topics.html">Site Index</a> <HR> <li><a href="https://twitter.com/zipcpu"><span class="icon--twitter"><svg viewBox="0 0 400 400"><path fill="#1da1f2" d="M153.62,301.59c94.34,0,145.94-78.16,145.94-145.94,0-2.22,0-4.43-.15-6.63A104.36,104.36,0,0,0,325,122.47a102.38,102.38,0,0,1-29.46,8.07,51.47,51.47,0,0,0,22.55-28.37,102.79,102.79,0,0,1-32.57,12.45,51.34,51.34,0,0,0-87.41,46.78A145.62,145.62,0,0,1,92.4,107.81a51.33,51.33,0,0,0,15.88,68.47A50.91,50.91,0,0,1,85,169.86c0,.21,0,.43,0,.65a51.31,51.31,0,0,0,41.15,50.28,51.21,51.21,0,0,1-23.16.88,51.35,51.35,0,0,0,47.92,35.62,102.92,102.92,0,0,1-63.7,22A104.41,104.41,0,0,1,75,278.55a145.21,145.21,0,0,0,78.62,23"/></svg> </span><span class="username">@zipcpu</span></a> <li><a href="https://www.reddit.com/r/ZipCPU"><span class="username">Reddit</a> <li><a HREF="https://www.patreon.com/ZipCPU"><IMG SRC="/img/patreon_logomark_color_on_white.png" WIDTH="25"> Support</a> </ul> </div> </header> <div class="page-content"> <div class="wrapper"> <article class="post"> <header class="post-header"> <h1 class="post-title">About the ZipCPU</h1> </header> <div class="post-content"> <p>The <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> is an <a href="https://www.gnu.org/licenses/gpl-3.0.en.html">open source</a>, fully-functional, <a href="https://en.wikipedia.org/wiki/Soft_microprocessor">soft core</a> <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a> built for <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a> environments by <a href="/about/gisselquist-technology.html">Gisselquist Technology, LLC</a>.</p> <p>The <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> was initially designed with the sole purpose of creating a simple <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a> within an <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a>, and particularly one that was powerful enough to run Linux.</p> <p>In bullets, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> is:</p> <ul> <li> <p>A 32-bit CPU. All registers are 32-bits wide, addresses are 32-bits wide, instructions are 32-bits wide, etc.</p> </li> <li> <p>A <a href="https://en.wikipedia.org/wiki/Reduced_instruction_set_computer">RISC CPU</a>. It implements only a minimum set of instructions, a much smaller set than most other “RISC” CPU’s.</p> </li> <li> <p>A <a href="https://en.wikipedia.org/wiki/Load/store_architecture">Load/Store architecture</a>. Only load and store instructions can access memory</p> </li> <li> <p><a href="https://opencores.org/opencores,wishbone">Wishbone compliant</a>. All peripherals are accessed via <a href="https://en.wikipedia.org/wiki/Memory_mapped_I/O">memory mapped I/O</a> across a common <a href="https://opencores.org/opencores,wishbone">Wishbone bus</a>.</p> </li> <li> <p>A <a href="https://en.wikipedia.org/wiki/Von_Neumann_architecture">Von-Neumann architecture</a>. Both instructions and data share a common bus</p> </li> <li> <p>A <a href="https://en.wikipedia.org/wiki/Pipline_(computing)">pipelined architecture</a>, having stages for <em>prefetch</em>, <em>decode</em>, <em>read-operand</em>, <em>execute</em>, and <em>write-back</em>. The <em>execute</em> stage is implemented by one of four blocks: an <a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/cpuops.v">arithmetic logic unit (ALU)</a>, a <a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/pipemem.v">memory unit</a>, a <a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/div.v">divide coprocessor</a>, and a (not yet implemented) floating point coprocessor. The last two blocks, the <a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/div.v">divide</a> and floating point coprocessor, will only ever be options to the <a href="https://github.com/ZipCPU/zipcpu">CPU</a>. Their inclusion will be chosen based upon your implementation needs.</p> </li> <li> <p><a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/cpudefs.v">A configurable CPU</a>: You can choose how much logic goes into the <a href="https://github.com/ZipCPU/zipcpu">CPU</a>, and therefore trade LUTs for speed if desired.</p> </li> </ul> <h2 id="low-cost">Low Cost</h2> <p>The ZipCPU was designed to be implemented on a low cost FPGA board. Reasons for this include:</p> <ol> <li> <p>I couldn’t afford the <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a> board that I really wanted, the <a href="https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html">VC707</a>, much less the license I would need to program it. Instead, I could afford the much smaller boards ($50-$150), such as the ones <a href="https://store.digilentinc.com">Digilent</a> sells.</p> </li> <li> <p>I wanted to know how to build a <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>. This includes learning how to build not only a <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>, but also backends for <a href="https://sourceware.org/newlib">the C-library</a>, <a href="https://gcc.gnu.org">GCC</a> and <a href="https://www.gnu.org/software/binutils">binutils</a> (<a href="https://www.gnu.org/s/gdb">GDB</a> soon to come).</p> </li> <li> <p>Prior to purchasing any boards or licenses, I simulated my designs using <a href="https://www.veripool.org/wiki/verilator">Verilator</a>. However, <a href="https://www.veripool.org/wiki/verilator">Verilator</a> only works with Verilog source, not encrypted proprietary IP components. Hence, when I wanted to simulate <a href="https://github.com/ZipCPU/dblclockfft">an FFT</a> with neither hardware nor proprietary IP, I was forced to <a href="https://github.com/ZipCPU/dblclockfft">build my own</a>. The same became true for the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a>. Incidentally, the “simulate before you buy” technique worked so well for <a href="https://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users">my first board</a>, that I had my initial design running within two days after I received the board.</p> </li> <li> <p>I’m still hoping to integrate an <a href="https://github.com/ZipCPU/zipcpu/blob/master/rtl/peripherals/zipmmu.v">optional MMU</a> into <a href="https://github.com/ZipCPU/zipcpu">the CPU</a>, and with it to run Linux, but this feature remains sometime in the future.</p> </li> </ol> <h2 id="unique-features-of-the-zipcpu">Unique Features of the ZipCPU</h2> <p>While the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> was the result of my own desire to learn how <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>’s operate, now that it has been built it solves many of the problems that many of the more proprietary <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>’s struggle with.</p> <ul> <li> <p>Because the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> is completely open source, <a href="https://www.veripool.org/wiki/verilator">opensource tools</a> may be used to simulate and run the CPU–even without an <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a>.</p> <p>o Your simulation CPU’s power is the limit of this simulation. As an example, you could, if you wished to, run the <a href="https://github.com/ZipCPU/s6soc">CMod-S6</a> <a href="https://github.com/ZipCPU/s6soc/blob/master/sim/verilator/zip_sim.cpp">simulation</a> all the way from power up through several rounds of <a href="https://github.com/ZipCPU/tttt">4x4x4 Tic-Tac-Toe</a>. (Just don’t run it in debug mode all night, at the peril of filling up your disk drive.)</p> <p>o In a similar fashion, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> is not tied to <a href="https:www.altera.com">Altera</a>, <a href="https://www.xilinx.com">Xilinx</a>, nor <a href="https://github.com/ZipCPU/icozip">its more recent port</a> to the <a href="https://www.latticesemi.com">Lattice</a> iCE40 <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a>’s.</p> <p>o Hence, it offers more flexibility than either <a href="https://www.xilinx.com/products/design-tools/microblaze.html">MicroBlaze</a> or <a href="https://www.altera.com/products/processors/overview.html">Nios2</a>.</p> </li> <li> <p>Because the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> was designed to be simple, it can be <a href="https://github.com/ZipCPU/s6soc">a component</a> on a very small <a href="https://en.wikipedia.org/wiki/Field-programmable_gate_array">FPGA</a>, such as the Spartan 6LX4 used in the <a href="https://store.digilentinc.com">Digilent’s</a> <a href="https://store.digilentinc.com/cmod-s6-breadboardable-spartan-6-fpga-module">CMod S6</a>.</p> </li> <li> <p>Since the <a href="https://github.com/ZipCPU">ZipCPU</a> was designed around the pipelined <a href="http://opencores.org/opencores,wishbone">Wishbone bus</a>, found within the <a href="http://opencores.org/cdn/downloads/wbspec_b4.pdf">Wishbone B4 specification</a>, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> enjoys memory accesses that are between three and thirty times faster than the <a href="https://openrisc.io">OpenRISC</a> core. (Their cache implementation is still better than mine, though …) Further, because of the many, many options and channels required in order to implement the <a href="http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf">AXI bus</a> used by <a href="https://www.xilinx.com">Xilinx</a>’s IP, the <a href="http://opencores.org/opencores,wishbone">Wishbone</a> is simpler and hence both easier to work with, and it requires less logic to use.</p> </li> <li> <p>Because <a href="/about/gisselquist-technology.html">Gisselquist Technology, LLC</a>, owns all of the code for the <a href="https://github.com/ZipCPU">ZipCPU</a> and its peripherals, proprietary licenses may be purchased. This sets the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> apart from the other OpenSource <a href="https://en.wikipedia.org/wiki/Soft_microprocessor">soft core CPUs</a>, such as <a href="https://openrisc.io">OpenRISC</a>, whose IP may not be owned by any single entity with whom one might negotiate a purchase.</p> </li> </ul> <p>You can find out many of the details of this <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a> within the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> repository on <a href="https://github.com">GitHub</a>. There, you will find the <a href="https://github.com/ZipCPU/zipcpu/blob/master/doc/spec.pdf">specification for the CPU</a> which contains not only the obligatory description of its instruction set, but also examples of how to program with it as well as my ongoing “honest assessment” of it as a <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>.</p> <h2 id="example-zipcpu-designs">Example ZipCPU designs</h2> <p>In many ways, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> is just that: a <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a> and only a <a href="https://en.wikipedia.org/wiki/Central_processing_unit">CPU</a>. It has a connection to its memory and peripherals, but these are not a part of the ZipCPU itself.</p> <p>However, <a href="/about/gisselquist-technology.html">Gisselquist Technology</a> has publicly released several designs that use the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a>, all available on <a href="https://github.com/ZipCPU">GitHub</a> for you to examine. These include the <a href="https://github.com/ZipCPU/s6soc">S6SoC</a> project, which fits on the <a href="https://www.xilinx.com">Xilinx</a> Spartan-6LX4 found within a <a href="https://store.digilentinc.com">Digilent</a> <a href="https://store.digilentinc.com/cmod-s6-breadboardable-spartan-6-fpga-module">CMod S6</a>, the <a href="https://github.com/ZipCPU/openarty">OpenArty</a> which fits on a <a href="https://store.digilentinc.com">Digilent</a> <a href="https://store.digilentinc.com/arty-artix-7-fpga-development-board-for-makers-and-hobbyists/">Arty</a>, or the <a href="https://github.com/ZipCPU/xulalx25soc">xulalx25soc</a> which fits on <a href="https://xess.com">Xess.com</a>’s <a href="https://xess.com/shop/product/xula2-lx25/">XuLA2-LX25</a> board. Upon customer request, the <a href="https://github.com/ZipCPU/xulalx25soc">xulalx25soc</a> now has a build option which can be used to build a version for the Spartan-6LX9 found on the XuLA2-LX9 board which <a href="https://xess.com">Xess.com</a> used to sell.</p> <p>Another ZipCPU design you may wish to look at is the basic ZipCPU design called <a href="https://github.com/ZipCPU/zbasic">zbasic</a>. This design has support for a flash, block RAM, and a serial port. It’s also my testing grounds for getting the <a href="https://github.com/ZipCPU/sdspi">SD Card controller</a> to work.</p> <h2 id="current-status">Current Status</h2> <p>The <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> has undergone several instruction set revisions, going from a four bit opcode supporting only 32-bit bytes, to a five bit opcode, and finally to a 5-bit opcode with support for 16-bit compressed instructions and 8-bit bytes. I see no reason at this time to adjust the instruction set any more.</p> <p>The current instruction set has newlib, GCC, and binutils support–although the soft floating point emulation support is lagging a touch.</p> <p>A <a href="https://github.com/ZipCPU/s6soc/tree/master/sw/zipos">minimal O/S</a> exists for the ZipCPU. Further O/S support is expected, but lagging behind getting more peripheral support.</p> <h2 id="performance">Performance</h2> <p>Here’s a summary of the clock rates the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> can achieve on a variety of commercial boards:</p> <table class="bordered-table"> <thead> <tr> <th>Design</th> <th>Clock Rate</th> <th>CPI</th> <th>Notes</th> </tr> </thead> <tbody> <tr> <td>Ico-Board</td> <td>40 MHz</td> <td>?</td> <td>This icoboard design is still in development</td> </tr> <tr> <td>S6SoC</td> <td>80 MHz</td> <td>18</td> <td>When running from flash</td> </tr> <tr> <td>XuLA2</td> <td>80 MHz</td> <td>1</td> <td> </td> </tr> <tr> <td>Basys-3</td> <td>100 MHz</td> <td>1</td> <td> </td> </tr> <tr> <td>Arty</td> <td>82 MHz</td> <td>1</td> <td>Clock speed limited by SDRAM clock</td> </tr> <tr> <td>Nexys-Video</td> <td>82 MHz</td> <td>1</td> <td> </td> </tr> </tbody> </table> <p>The <a href="https://github.com/ZipCPU/xulalx25soc">XuLA design</a> was used in the summer of 2016 to benchmark the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> using the <a href="https://en.wikipedia.org/wiki/Dhrystone">Dhrystone benchmark</a>. At the time, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> only supported 32-bit bytes, so it wasn’t a proper fit for the <a href="https://en.wikipedia.org/wiki/Dhrystone">Dhrystone benchmark</a>. Still, it was able to accomplish <strong>0.744 DMIPS/MHz</strong> packing one character in each 32-bit byte. If you instead packed four characters into the 32-bit bytes used by the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> at the time, the <a href="https://github.com/ZipCPU/zipcpu">CPU</a> could achieve <strong>0.95 (modified) DMIPS/MHz</strong>. <a href="https://github.com/ZipCPU/zipcpu/blob/master/doc/orconf.pdf">These results</a> were presented at ORCONF, 2016.</p> <p>Since then, the CPU has been modified to support 8-bit bytes. I have not returned to the <a href="https://en.wikipedia.org/wiki/Dhrystone">Dhrystone benchmark</a>, though, to update its performance measure.</p> <p>As of ORCONF, 2016, the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> used between 1286 and 4926 6-LUTs, depending upon how it is configured. This number is out of date, though, for the same reason that the <a href="https://en.wikipedia.org/wiki/Dhrystone">Dhrystone benchmark</a> measure is out of date: the <a href="https://github.com/ZipCPU/zipcpu">ZipCPU</a> has since been modified to support 8-bit bytes. I can say, though, that I was able to pack more logic into the CMod-S6 as a result than I could pack into it before, suggesting that the new and improved CPU uses even fewer resources.</p> </div> </article> </div> </div> <footer class="site-footer"> <div class="wrapper"> <h2 class="footer-heading">The ZipCPU by Gisselquist Technology</h2> <div class="footer-col-wrapper"> <div class="footer-col footer-col-1"> <ul class="contact-list">  <li><a href="mailto:zipcpu@gmail.com">zipcpu@gmail.com</a></li> </ul> </div> <div class="footer-col footer-col-2"> <ul class="soc-medlist"> <li> <a href="https://github.com/ZipCPU"><span class="icon icon--github"><svg viewBox="0 0 16 16"><path fill="#828282" d="M7.999,0.431c-4.285,0-7.76,3.474-7.76,7.761 c0,3.428,2.223,6.337,5.307,7.363c0.388,0.071,0.53-0.168,0.53-0.374c0-0.184-0.007-0.672-0.01-1.32 c-2.159,0.469-2.614-1.04-2.614-1.04c-0.353-0.896-0.862-1.135-0.862-1.135c-0.705-0.481,0.053-0.472,0.053-0.472 c0.779,0.055,1.189,0.8,1.189,0.8c0.692,1.186,1.816,0.843,2.258,0.645c0.071-0.502,0.271-0.843,0.493-1.037 C4.86,11.425,3.049,10.76,3.049,7.786c0-0.847,0.302-1.54,0.799-2.082C3.768,5.507,3.501,4.718,3.924,3.65 c0,0,0.652-0.209,2.134,0.796C6.677,4.273,7.34,4.187,8,4.184c0.659,0.003,1.323,0.089,1.943,0.261 c1.482-1.004,2.132-0.796,2.132-0.796c0.423,1.068,0.157,1.857,0.077,2.054c0.497,0.542,0.798,1.235,0.798,2.082 c0,2.981-1.814,3.637-3.543,3.829c0.279,0.24,0.527,0.713,0.527,1.437c0,1.037-0.01,1.874-0.01,2.129 c0,0.208,0.14,0.449,0.534,0.373c3.081-1.028,5.302-3.935,5.302-7.362C15.76,3.906,12.285,0.431,7.999,0.431z"/></svg> </span><span class="username">ZipCPU</span></a> </li> <li> <a href="https://twitter.com/zipcpu"><span class="icon icon--twitter"><svg viewBox="0 0 16 16"><path fill="#828282" d="M15.969,3.058c-0.586,0.26-1.217,0.436-1.878,0.515c0.675-0.405,1.194-1.045,1.438-1.809c-0.632,0.375-1.332,0.647-2.076,0.793c-0.596-0.636-1.446-1.033-2.387-1.033c-1.806,0-3.27,1.464-3.27,3.27 c0,0.256,0.029,0.506,0.085,0.745C5.163,5.404,2.753,4.102,1.14,2.124C0.859,2.607,0.698,3.168,0.698,3.767 c0,1.134,0.577,2.135,1.455,2.722C1.616,6.472,1.112,6.325,0.671,6.08c0,0.014,0,0.027,0,0.041c0,1.584,1.127,2.906,2.623,3.206 C3.02,9.402,2.731,9.442,2.433,9.442c-0.211,0-0.416-0.021-0.615-0.059c0.416,1.299,1.624,2.245,3.055,2.271 c-1.119,0.877-2.529,1.4-4.061,1.4c-0.264,0-0.524-0.015-0.78-0.046c1.447,0.928,3.166,1.469,5.013,1.469 c6.015,0,9.304-4.983,9.304-9.304c0-0.142-0.003-0.283-0.009-0.423C14.976,4.29,15.531,3.714,15.969,3.058z"/></svg> </span><span class="username">@zipcpu</span></a> </li> <li><A href="https://www.patreon.com/ZipCPU"><img src="/img/become_a_patron_button.png"></a></li> </ul> </div> <div class="footer-col footer-col-3"> <p>The ZipCPU blog, featuring how to discussions of FPGA and soft-core CPU design. This site will be focused on Verilog solutions, using exclusively OpenSource IP products for FPGA design. Particular focus areas include topics often left out of more mainstream FPGA design courses such as how to debug an FPGA design. </p> </div> </div> </div> </footer> </body> </html>