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class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Series of x86 manycore processors from Intel</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Not to be confused with the ATI <a href="/wiki/Xenos_(graphics_chip)" title="Xenos (graphics chip)">Xenos</a>, <a href="/wiki/Xenon_(processor)" title="Xenon (processor)">Xenon</a>, or the regular Intel <a href="/wiki/Xeon" title="Xeon">Xeon</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output 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.mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Xeon Phi</caption><tbody><tr><td colspan="2" class="infobox-image"><a href="/wiki/File:Intel_Xeon_Phi_5100.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d7/Intel_Xeon_Phi_5100.jpg/220px-Intel_Xeon_Phi_5100.jpg" decoding="async" width="220" height="146" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d7/Intel_Xeon_Phi_5100.jpg/330px-Intel_Xeon_Phi_5100.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d7/Intel_Xeon_Phi_5100.jpg/440px-Intel_Xeon_Phi_5100.jpg 2x" data-file-width="2100" data-file-height="1395" /></a><div class="infobox-caption">Xeon Phi 5100 without <a href="/wiki/Heatsink" class="mw-redirect" title="Heatsink">heatsink</a></div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">2010</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">2020<a href="#cite_note-1">[1]</a></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>Intel</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">1.053 GHz to 1.7 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">32 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> per core</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">512 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> per core</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label">Application</th><td class="infobox-data">Supercomputers High-performance computing</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm transistors</a> to <a href="/wiki/14_nanometer" class="mw-redirect" title="14 nanometer">14 nm transistors</a> (<a href="/wiki/FinFET" class="mw-redirect" title="FinFET">tri-gate</a>)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a> (except coprocessor form factor), <a href="/wiki/IA-32" title="IA-32">IA-32</a>, <a href="/wiki/X86-64" title="X86-64">x86-64</a><a href="#cite_note-2">[2]</a></td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>32-72</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Random-access_memory" title="Random-access memory">Memory (RAM)</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Up to 384 GB and 16 GB</li><li>Up to DDR4 115.4 GB/s with ECC support</li><li>MCDRAM 400+ GB/s</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/LGA_3647" title="LGA 3647">LGA 3647</a></li><li><a href="/wiki/PCI_Express_3.0" class="mw-redirect" title="PCI Express 3.0">PCI Express 3.0</a> x16</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Core names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Knights Ferry</li><li>Knights Corner</li><li>Knights Landing</li><li>Knights Mill</li><li><s>Knights Hill</s></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Model</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Xeon Phi 3100</li><li>Xeon Phi 5100</li><li>Xeon Phi 7100</li><li>Xeon Phi 7200</li></ul></div></li></ul></div></td></tr></tbody></table> Xeon Phi<a href="#cite_note-IntelXeonPhiName-3">[3]</a> is a discontinued series of <a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Manycore_processor" title="Manycore processor">manycore processors</a> designed and made by <a href="/wiki/Intel" title="Intel">Intel</a>. It was intended for use in supercomputers, servers, and high-end workstations. Its architecture allowed use of standard programming languages and <a href="/wiki/Application_programming_interface" class="mw-redirect" title="Application programming interface">application programming interfaces</a> (APIs) such as <a href="/wiki/OpenMP" title="OpenMP">OpenMP</a>.<a href="#cite_note-4">[4]</a><a href="#cite_note-5">[5]</a> Xeon Phi launched in 2010. Since it was originally based on an earlier GPU design (<a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">codenamed "Larrabee"</a>) by Intel<a href="#cite_note-6">[6]</a> that was cancelled in 2009,<a href="#cite_note-7">[7]</a> it shared application areas with GPUs. The main difference between Xeon Phi and a <a href="/wiki/GPGPU" class="mw-redirect" title="GPGPU">GPGPU</a> like <a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a> was that Xeon Phi, with an x86-compatible core, could, with less modification, run software that was originally targeted to a standard x86 CPU. Initially in the form of <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a>-based add-on cards, a second-generation product, codenamed Knights Landing, was announced in June 2013.<a href="#cite_note-8">[8]</a> These second-generation chips could be used as a standalone CPU, rather than just as an add-in card. <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Tianhe-2.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0a/Tianhe-2.jpg/220px-Tianhe-2.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0a/Tianhe-2.jpg/330px-Tianhe-2.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0a/Tianhe-2.jpg/440px-Tianhe-2.jpg 2x" data-file-width="4608" data-file-height="3456" /></a><figcaption>The <a href="/wiki/Tianhe-2" title="Tianhe-2">Tianhe-2</a> supercomputer uses Xeon Phi processors.</figcaption></figure> In June 2013, the <a href="/wiki/Tianhe-2" title="Tianhe-2">Tianhe-2</a> supercomputer at the <a href="/wiki/National_Supercomputer_Center_in_Guangzhou" title="National Supercomputer Center in Guangzhou">National Supercomputer Center in Guangzhou</a> (NSCC-GZ) was announced<a href="#cite_note-top500june2013-9">[9]</a> as the world's fastest supercomputer (as of June 2023<a class="external text" href="https://en.wikipedia.org/w/index.php?title=Xeon_Phi&action=edit">[update]</a>, it is No. 10<a href="#cite_note-10">[10]</a>). It used Intel Xeon Phi coprocessors and <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a>-EP Xeon E5 v2 processors to achieve 33.86 petaFLOPS.<a href="#cite_note-knightslandingjune2013-11">[11]</a> The Xeon Phi product line directly competed with <a href="/wiki/Nvidia" title="Nvidia">Nvidia</a>'s <a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Tesla</a> and AMD <a href="/wiki/Radeon_Instinct" class="mw-redirect" title="Radeon Instinct">Radeon Instinct</a> lines of deep learning and GPGPU cards. It was discontinued due to a lack of demand and Intel's problems with its 10nm node.<a href="#cite_note-12">[12]</a> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=1" title="Edit section: History">edit</a>]</div> <table class="wikitable"> <tbody><tr> <th>Code name</th> <th>Process</th> <th>Comments </th></tr> <tr> <td>Knights Ferry</td> <td>45 nm</td> <td>offered as PCI Express card; derived from Larrabee project </td></tr> <tr> <td>Knights Corner</td> <td>22 nm</td> <td>derived from P54C; vector processing unit; first device to be announced as Xeon Phi; AVX-512-like encoding </td></tr> <tr> <td>Knights Landing</td> <td>14 nm</td> <td>derived from Silvermont/Airmont (Intel Atom);<a href="#cite_note-13">[13]</a> AVX-512 </td></tr> <tr> <td>Knights Mill</td> <td>14 nm</td> <td>nearly identical to Knights Landing but optimized for deep learning </td></tr> <tr> <td>Knights Hill</td> <td>10 nm</td> <td>cancelled </td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_Phi_Lineup.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Intel_Xeon_Phi_Lineup.jpg/220px-Intel_Xeon_Phi_Lineup.jpg" decoding="async" width="220" height="171" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Intel_Xeon_Phi_Lineup.jpg/330px-Intel_Xeon_Phi_Lineup.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4d/Intel_Xeon_Phi_Lineup.jpg/440px-Intel_Xeon_Phi_Lineup.jpg 2x" data-file-width="3819" data-file-height="2976" /></a><figcaption>A lineup of the Xeon Phi coprocessors. From the left; Knights Ferry, Knights Corner, Knights Landing.</figcaption></figure> <div class="mw-heading mw-heading3"><h3 id="Background">Background</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=2" title="Edit section: Background">edit</a>]</div> The <a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee microarchitecture</a> (in development since 2006<a href="#cite_note-14">[14]</a>) introduced very wide (512-bit) <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> units to an <a href="/wiki/X86" title="X86">x86</a> architecture based processor design, extended to a <a href="/wiki/Cache_coherence" title="Cache coherence">cache-coherent</a> multiprocessor system connected via a ring bus to memory; each core was capable of four-way multithreading. Due to the design being intended for GPU as well as general purpose computing, the Larrabee chips also included specialised hardware for texture sampling.<a href="#cite_note-15">[15]</a><a href="#cite_note-16">[16]</a> The project to produce a retail GPU product directly from the Larrabee research project was terminated in May 2010.<a href="#cite_note-17">[17]</a> Another contemporary Intel research project implementing x86 architecture on a many-multicore processor was the '<a href="/wiki/Single-chip_Cloud_Computer" title="Single-chip Cloud Computer">Single-chip Cloud Computer</a>' (prototype introduced 2009<a href="#cite_note-18">[18]</a>), a design mimicking a <a href="/wiki/Cloud_computing" title="Cloud computing">cloud computing</a> computer datacentre on a single chip with multiple independent cores: the prototype design included 48 cores per chip with hardware support for selective frequency and voltage control of cores to maximize energy efficiency, and incorporated a <a href="/wiki/Mesh_networking" title="Mesh networking">mesh network</a> for inter-chip messaging. The design lacked cache-coherent cores and focused on principles that would allow the design to scale to many more cores.<a href="#cite_note-19">[19]</a> The <a href="/wiki/Teraflops_Research_Chip" title="Teraflops Research Chip">Teraflops Research Chip</a> (prototype unveiled 2007<a href="#cite_note-20">[20]</a>) is an experimental 80-core chip with two <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> units per core, implementing a 96-bit <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> architecture instead of the x86 architecture.<a href="#cite_note-21">[21]</a> The project investigated intercore communication methods, per-chip power management, and achieved 1.01 <a href="/wiki/TFLOPS" class="mw-redirect" title="TFLOPS">TFLOPS</a> at 3.16 GHz consuming 62 W of power.<a href="#cite_note-22">[22]</a><a href="#cite_note-23">[23]</a> <div class="mw-heading mw-heading3"><h3 id="Knights_Ferry">Knights Ferry</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=3" title="Edit section: Knights Ferry">edit</a>]</div> Intel's Many Integrated Core (MIC) prototype board, named Knights Ferry, incorporating a processor codenamed Aubrey Isle was announced 31 May 2010. The product was stated to be a derivative of the Larrabee project and other Intel research including the Single-chip Cloud Computer.<a href="#cite_note-zdin1-24">[24]</a><a href="#cite_note-25">[25]</a> The development product was offered as a PCIe card with 32 in-order cores at up to 1.2 GHz with four threads per core, 2 GB GDDR5 memory,<a href="#cite_note-gox-26">[26]</a> and 8 MB coherent L2 cache (256 KB per core with 32 KB L1 cache), and a power requirement of ~300 W,<a href="#cite_note-gox-26">[26]</a> built at a 45 nm process.<a href="#cite_note-thi-27">[27]</a> In the Aubrey Isle core a 1,024-bit ring bus (512-bit bi-directional) connects processors to main memory.<a href="#cite_note-28">[28]</a> Single-board performance has exceeded 750 GFLOPS.<a href="#cite_note-thi-27">[27]</a> The prototype boards only support <a href="/wiki/Single-precision" class="mw-redirect" title="Single-precision">single-precision</a> floating-point instructions.<a href="#cite_note-29">[29]</a> Initial developers included <a href="/wiki/CERN" title="CERN">CERN</a>, <a href="/wiki/Korea_Institute_of_Science_and_Technology_Information" title="Korea Institute of Science and Technology Information">Korea Institute of Science and Technology Information</a> (KISTI) and <a href="/wiki/Leibniz_Supercomputing_Centre" title="Leibniz Supercomputing Centre">Leibniz Supercomputing Centre</a>. Hardware vendors for prototype boards included IBM, SGI, HP, Dell and others.<a href="#cite_note-30">[30]</a> <div class="mw-heading mw-heading3"><h3 id="Knights_Corner">Knights Corner</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=4" title="Edit section: Knights Corner">edit</a>]</div> The Knights Corner product line is made at a 22 nm process size, using Intel's <a href="/wiki/Trigate_Transistors" class="mw-redirect" title="Trigate Transistors">Tri-gate</a> technology with more than 50 cores per chip, and is Intel's first many-cores commercial product.<a href="#cite_note-zdin1-24">[24]</a><a href="#cite_note-thi-27">[27]</a> In June 2011, <a href="/wiki/Silicon_Graphics_International" title="Silicon Graphics International">SGI</a> announced a partnership with Intel to use the MIC architecture in its high-performance computing products.<a href="#cite_note-31">[31]</a> In September 2011, it was announced that the <a href="/wiki/Texas_Advanced_Computing_Center" title="Texas Advanced Computing Center">Texas Advanced Computing Center</a> (TACC) will use Knights Corner cards in their 10-petaFLOPS "Stampede" supercomputer, providing 8 petaFLOPS of compute power.<a href="#cite_note-TACC_Press_Release-32">[32]</a> According to "Stampede: A Comprehensive Petascale Computing Environment" the "second-generation Intel (Knights Landing) MICs will be added when they become available, increasing Stampede's aggregate peak performance to at least 15 PetaFLOPS."<a href="#cite_note-stampedeieee-33">[33]</a> On 15 November 2011, Intel showed an early silicon version of a Knights Corner processor.<a href="#cite_note-34">[34]</a><a href="#cite_note-35">[35]</a> On 5 June 2012, Intel released open source software and documentation regarding Knights Corner.<a href="#cite_note-36">[36]</a> On 18 June 2012, Intel announced at the 2012 Hamburg <a href="/wiki/International_Supercomputing_Conference" class="mw-redirect" title="International Supercomputing Conference">International Supercomputing Conference</a> that Xeon Phi will be the <a href="/wiki/Brand_name" class="mw-redirect" title="Brand name">brand name</a> used for all products based on their Many Integrated Core architecture.<a href="#cite_note-IntelXeonPhiName-3">[3]</a><a href="#cite_note-37">[37]</a><a href="#cite_note-38">[38]</a><a href="#cite_note-IntelXeonPhiPlans-39">[39]</a><a href="#cite_note-EETimesXeonPhiName-40">[40]</a><a href="#cite_note-EngadgetXeonPhiName-41">[41]</a><a href="#cite_note-EWeekXeonPhiName-42">[42]</a> In June 2012, <a href="/wiki/Cray" title="Cray">Cray</a> announced it would be offering 22 nm 'Knight's Corner' chips (branded as 'Xeon Phi') as a co-processor in its 'Cascade' systems.<a href="#cite_note-43">[43]</a><a href="#cite_note-44">[44]</a> In June 2012, ScaleMP announced a virtualization update allowing Xeon Phi as a transparent processor extension, allowing legacy <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>/<a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a> code to run without code changes.<a href="#cite_note-45">[45]</a> An important component of the Intel Xeon Phi coprocessor's core is its vector processing unit (VPU).<a href="#cite_note-46">[46]</a> The VPU features a novel 512-bit SIMD instruction set, officially known as Intel Initial Many Core Instructions (Intel IMCI). Thus, the VPU can execute 16 <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">single-precision</a> (SP) or 8 <a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision</a> (DP) operations per cycle. The VPU also supports Fused Multiply-Add (FMA) instructions and hence can execute 32 SP or 16 DP floating point operations per cycle. It also provides support for integers. The VPU also features an Extended Math Unit (EMU) that can execute operations such as reciprocal, square root, and logarithm, thereby allowing these operations to be executed in a vector fashion with high bandwidth. The EMU operates by calculating polynomial approximations of these functions. On 12 November 2012, Intel announced two Xeon Phi coprocessor families using the 22 nm process size: the Xeon Phi 3100 and the Xeon Phi 5110P.<a href="#cite_note-IntelXeonPhiProducts2012-47">[47]</a><a href="#cite_note-ComputerworldXeonPhiProducts2012-48">[48]</a><a href="#cite_note-AnandtechXeonPhiProducts2012-49">[49]</a> The Xeon Phi 3100 will be capable of more than 1 teraFLOPS of <a href="/wiki/Double-precision" class="mw-redirect" title="Double-precision">double-precision</a> floating-point instructions with 240 GB/s memory bandwidth at 300 W.<a href="#cite_note-IntelXeonPhiProducts2012-47">[47]</a><a href="#cite_note-ComputerworldXeonPhiProducts2012-48">[48]</a><a href="#cite_note-AnandtechXeonPhiProducts2012-49">[49]</a> The Xeon Phi 5110P will be capable of 1.01 teraFLOPS of double-precision floating-point instructions with 320 GB/s memory bandwidth at 225 W.<a href="#cite_note-IntelXeonPhiProducts2012-47">[47]</a><a href="#cite_note-ComputerworldXeonPhiProducts2012-48">[48]</a><a href="#cite_note-AnandtechXeonPhiProducts2012-49">[49]</a> The Xeon Phi 7120P will be capable of 1.2 teraFLOPS of double-precision floating-point instructions with 352 GB/s memory bandwidth at 300 W. On 17 June 2013, the <a href="/wiki/Tianhe-2" title="Tianhe-2">Tianhe-2</a> supercomputer was announced<a href="#cite_note-top500june2013-9">[9]</a> by <a href="/wiki/TOP500" title="TOP500">TOP500</a> as the world's fastest. Tianhe-2 used Intel Ivy Bridge Xeon and Xeon Phi processors to achieve 33.86 petaFLOPS. It was the fastest on the list for two and a half years, lastly in November 2015.<a href="#cite_note-top500tianhe2-50">[50]</a> <div class="mw-heading mw-heading4"><h4 id="Design_and_programming">Design and programming</h4>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=5" title="Edit section: Design and programming">edit</a>]</div> The cores of Knights Corner are based on a modified version of <a href="/wiki/P5_(microarchitecture)#P54C" class="mw-redirect" title="P5 (microarchitecture)">P54C</a> design, used in the original Pentium.<a href="#cite_note-51">[51]</a> The basis of the Intel MIC architecture is to leverage x86 legacy by creating an x86-compatible multiprocessor architecture that can use existing parallelization software tools.<a href="#cite_note-thi-27">[27]</a> Programming tools include <a href="/wiki/OpenMP" title="OpenMP">OpenMP</a>,<a href="#cite_note-52">[52]</a> <a href="/wiki/OpenCL" title="OpenCL">OpenCL</a>,<a href="#cite_note-53">[53]</a> <a href="/wiki/Cilk" title="Cilk">Cilk</a>/<a href="/wiki/Cilk_Plus" class="mw-redirect" title="Cilk Plus">Cilk Plus</a> and specialised versions of Intel's Fortran, C++<a href="#cite_note-54">[54]</a> and math libraries.<a href="#cite_note-55">[55]</a> Design elements inherited from the Larrabee project include x86 ISA, 4-way <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a> per core, 512-bit SIMD units, 32 KB L1 instruction cache, 32 KB L1 data cache, coherent L2 cache (512 KB per core<a href="#cite_note-56">[56]</a>), and ultra-wide ring bus connecting processors and memory. The Knights Corner 512-bit SIMD instructions share many intrinsic functions with AVX-512 extension . The instruction set documentation is available from Intel under the extension name of KNC.<a href="#cite_note-57">[57]</a><a href="#cite_note-58">[58]</a><a href="#cite_note-59">[59]</a><a href="#cite_note-60">[60]</a> <table class="wikitable sortable"> <caption>Models of Xeon Phi X100 Series </caption> <tbody><tr> <th rowspan="2">Name </th> <th rowspan="2">Serial Code </th> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Threads</a> @ 4× core) </th> <th colspan="2">Clock (MHz) </th> <th rowspan="2">L2 cache </th> <th colspan="3">GDDR5 ECC memory </th> <th rowspan="2">Peak DP compute (GFLOPS) </th> <th rowspan="2">TDP (W) </th> <th rowspan="2">Cooling system </th> <th rowspan="2">Form factor </th> <th rowspan="2">Released </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th>Quantity </th> <th>Channels </th> <th colspan="1"><abbr title="Total memory Bandwidth">BW</abbr> GB/s </th></tr> <tr> <td rowspan="2">Xeon Phi 3110X<a href="#cite_note-61">[61]</a> </td> <td rowspan="2">SE3110X </td> <td rowspan="2">061 (244) </td> <td rowspan="2">1053 </td> <td rowspan="2">– </td> <td rowspan="2">30.5 MB </td> <td>06 GB </td> <td>12 </td> <td>240 </td> <td rowspan="2">1028 </td> <td rowspan="2">300 </td> <td rowspan="2">Bare board </td> <td rowspan="6">PCIe 2.0 x16 card </td> <td rowspan="2">November, 2012 </td></tr> <tr> <td>08 GB </td> <td>16 </td> <td>320 </td></tr> <tr> <td>Xeon Phi 3120A<a href="#cite_note-62">[62]</a> </td> <td>SC3120A </td> <td>057 (228) </td> <td>1100 </td> <td>– </td> <td>28.5 MB </td> <td>06 GB </td> <td>12 </td> <td>240 </td> <td>1003 </td> <td>300 </td> <td>Fan/<a href="/wiki/Heatsink" class="mw-redirect" title="Heatsink">heatsink</a> </td> <td>17 June 2013 </td></tr> <tr> <td>Xeon Phi 3120P <a href="#cite_note-63">[63]</a> </td> <td>SC3120P </td> <td>057 (228) </td> <td>1100 </td> <td>– </td> <td>28.5 MB </td> <td>06 GB </td> <td>12 </td> <td>240 </td> <td>1003 </td> <td>300 </td> <td>Passive heatsink </td> <td>17 June 2013 </td></tr> <tr> <td>Xeon Phi 31S1P<a href="#cite_note-64">[64]</a> </td> <td>BC31S1P </td> <td>057 (228) </td> <td>1100 </td> <td>– </td> <td>28.5 MB </td> <td>08 GB </td> <td>16 </td> <td>320 </td> <td>1003 </td> <td>270 </td> <td>Passive heatsink </td> <td>17 June 2013 </td></tr> <tr> <td>Xeon Phi 5110P<a href="#cite_note-65">[65]</a> </td> <td>SC5110P </td> <td>060 (240) </td> <td>1053 </td> <td>– </td> <td>30.0 MB </td> <td>08 GB </td> <td>16 </td> <td>320 </td> <td>1011 </td> <td>225 </td> <td>Passive heatsink </td> <td>12 Nov 2012 </td></tr> <tr> <td rowspan="2">Xeon Phi 5120D<a href="#cite_note-66">[66]</a> </td> <td>SC5120D </td> <td rowspan="2">060 (240) </td> <td rowspan="2">1053 </td> <td rowspan="2">- </td> <td rowspan="2">30.0 MB </td> <td rowspan="2">08 GB </td> <td rowspan="2">16 </td> <td rowspan="2">352 </td> <td rowspan="2">1011 </td> <td rowspan="2">245 </td> <td rowspan="2">Bare board </td> <td rowspan="2">SFF 230-pin card </td> <td rowspan="2">17 June 2013 </td></tr> <tr> <td>BC5120D </td></tr> <tr> <td>Xeon Phi SE10P<a href="#cite_note-67">[67]</a> </td> <td>SE10P </td> <td>061 (244) </td> <td>1100 </td> <td>- </td> <td>30.5 MB </td> <td>08 GB </td> <td>16 </td> <td>352 </td> <td>1074 </td> <td>300 </td> <td>Passive heatsink </td> <td rowspan="5">PCIe 2.0 x16 card </td> <td>12 Nov. 2012 </td></tr> <tr> <td>Xeon Phi SE10X<a href="#cite_note-68">[68]</a> </td> <td>SE10X </td> <td>061 (244) </td> <td>1100 </td> <td>– </td> <td>30.5 MB </td> <td>08 GB </td> <td>16 </td> <td>352 </td> <td>1074 </td> <td>300 </td> <td>Bare board </td> <td>12 Nov. 2012 </td></tr> <tr> <td>Xeon Phi 7110P<a href="#cite_note-69">[69]</a> </td> <td>SC7110P </td> <td>061 (244) </td> <td>1100 </td> <td>1250 </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1220 </td> <td>300 </td> <td>Passive heatsink </td> <td>??? </td></tr> <tr> <td>Xeon Phi 7110X<a href="#cite_note-70">[70]</a> </td> <td>SC7110X </td> <td>061 (244) </td> <td>1250 </td> <td>??? </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1220 </td> <td>300 </td> <td>Bare board </td> <td>??? </td></tr> <tr> <td>Xeon Phi 7120A<a href="#cite_note-71">[71]</a> </td> <td>SC7120A </td> <td>061 (244) </td> <td>1238 </td> <td>1333 </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1208 </td> <td>300 </td> <td>Fan/heatsink </td> <td>6 April 2014 </td></tr> <tr> <td>Xeon Phi 7120D<a href="#cite_note-72">[72]</a> </td> <td>SC7120D </td> <td>061 (244) </td> <td>1238 </td> <td>1333 </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1208 </td> <td>270 </td> <td>Bare board </td> <td>SFF 230-pin card </td> <td>March ??, 2014 </td></tr> <tr> <td>Xeon Phi 7120P<a href="#cite_note-73">[73]</a> </td> <td>SC7120P </td> <td>061 (244) </td> <td>1238 </td> <td>1333 </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1208 </td> <td>300 </td> <td>Passive heatsink </td> <td rowspan="2">PCIe 2.0 x16 card </td> <td>17 June 2013 </td></tr> <tr> <td>Xeon Phi 7120X<a href="#cite_note-74">[74]</a> </td> <td>SC7120X </td> <td>061 (244) </td> <td>1238 </td> <td>1333 </td> <td>30.5 MB </td> <td>16 GB </td> <td>16 </td> <td>352 </td> <td>1208 </td> <td>300 </td> <td>Bare board </td> <td>17 June 2013 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Knights_Landing">Knights Landing</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=6" title="Edit section: Knights Landing">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel@14nm@Xeon_Phi@Knights_Landing@Xeon(ES)@QHL6_DSCx1.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg/220px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg" decoding="async" width="220" height="276" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg/330px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/83/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg/440px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx1.jpg 2x" data-file-width="3052" data-file-height="3832" /></a><figcaption>Intel Xeon Phi Knights Landing <a href="/wiki/Engineering_sample" title="Engineering sample">engineering sample</a></figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel@14nm@Xeon_Phi@Knights_Landing@Xeon(ES)@QHL6_DSCx3.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg/220px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg" decoding="async" width="220" height="175" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg/330px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg/440px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx3.jpg 2x" data-file-width="3835" data-file-height="3053" /></a><figcaption>The same processor, <a href="/wiki/Decapping" title="Decapping">delidded</a></figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel@14nm@Xeon_Phi@Knights_Landing@Xeon(ES)@QHL6_DSCx7@5x.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg/220px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg" decoding="async" width="220" height="145" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg/330px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg/440px-Intel%4014nm%40Xeon_Phi%40Knights_Landing%40Xeon%28ES%29%40QHL6_DSCx7%405x.jpg 2x" data-file-width="27590" data-file-height="18182" /></a><figcaption>Die shot</figcaption></figure> Code name for the second-generation MIC architecture product from Intel.<a href="#cite_note-stampedeieee-33">[33]</a> Intel officially first revealed details of its second-generation Intel Xeon Phi products on 17 June 2013.<a href="#cite_note-knightslandingjune2013-11">[11]</a> Intel said that the next generation of Intel MIC Architecture-based products will be available in two forms, as a coprocessor or a host processor (CPU), and be manufactured using Intel's <a href="/wiki/14_nanometer" class="mw-redirect" title="14 nanometer">14 nm</a> process technology. Knights Landing products will include integrated on-package memory for significantly higher memory bandwidth. Knights Landing contains up to 72 <a href="/wiki/Airmont_(microarchitecture)" class="mw-redirect" title="Airmont (microarchitecture)">Airmont</a> (Atom) cores with four threads per core,<a href="#cite_note-75">[75]</a><a href="#cite_note-76">[76]</a> using <a href="/wiki/LGA_3647" title="LGA 3647">LGA 3647</a> socket<a href="#cite_note-tomshardware_xeonphi-77">[77]</a> supporting up to 384 GB of "far" DDR4 2133 RAM and 8–16 GB of stacked "near" 3D <a href="/wiki/MCDRAM" title="MCDRAM">MCDRAM</a>, a version of the <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a>. Each core has two 512-bit vector units and supports <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> SIMD instructions, specifically the Intel AVX-512 Foundational Instructions (AVX-512F) with Intel AVX-512 Conflict Detection Instructions (AVX-512CD), Intel AVX-512 Exponential and Reciprocal Instructions (AVX-512ER), and Intel AVX-512 Prefetch Instructions (AVX-512PF). Support for IMCI has been removed in favor of AVX-512.<a href="#cite_note-78">[78]</a> The <a href="/wiki/National_Energy_Research_Scientific_Computing_Center" title="National Energy Research Scientific Computing Center">National Energy Research Scientific Computing Center</a> announced that Phase 2 of its newest supercomputing system "Cori" would use Knights Landing Xeon Phi coprocessors.<a href="#cite_note-79">[79]</a> On 20 June 2016, Intel launched the Intel Xeon Phi product family x200 based on the Knights Landing architecture, stressing its applicability to not just traditional simulation workloads, but also to <a href="/wiki/Machine_learning" title="Machine learning">machine learning</a>.<a href="#cite_note-raj_hazra_isc16_keynote-80">[80]</a><a href="#cite_note-81">[81]</a> The model lineup announced at launch included only Xeon Phi of bootable form-factor, but two versions of it: standard processors and processors with integrated Intel <a href="/wiki/Omni-Path" title="Omni-Path">Omni-Path</a> architecture fabric.<a href="#cite_note-82">[82]</a> The latter is denoted by the suffix F in the model number. Integrated fabric is expected to provide better latency at a lower cost than discrete high-performance network cards.<a href="#cite_note-raj_hazra_isc16_keynote-80">[80]</a> On 14 November 2016, the 48th list of <a href="/wiki/TOP500" title="TOP500">TOP500</a> contained two systems using Knights Landing in the Top 10.<a href="#cite_note-83">[83]</a> The <a href="/wiki/PCIe" class="mw-redirect" title="PCIe">PCIe</a> based co-processor variant of Knight's Landing was never offered to the general market and was discontinued by August 2017.<a href="#cite_note-84">[84]</a> This included the 7220A, 7240P and 7220P coprocessor cards. Intel announced they were discontinuing Knights Landing in summer 2018.<a href="#cite_note-Knights_Landing_Product_Discontinuance-85">[85]</a> <div class="mw-heading mw-heading4"><h4 id="Models">Models</h4>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=7" title="Edit section: Models">edit</a>]</div> All models can boost to their peak speeds, adding 200 MHz to their base frequency when running just one or two cores. When running from three to the maximum number of cores, the chips can only boost 100 MHz above the base frequency. All chips run high-AVX code at a frequency reduced by 200 MHz.<a href="#cite_note-86">[86]</a> <table class="wikitable sortable"> <caption>Models of Xeon Phi X200 Coprocessor Series </caption> <tbody><tr> <th rowspan="2">Name </th> <th rowspan="2">Serial Code </th> <th rowspan="2">Cores (Threads @ 4× core) </th> <th colspan="2">Clock (MHz) </th> <th rowspan="2">L2 cache </th> <th colspan="2">MCDRAM memory </th> <th colspan="2">DDR4 memory </th> <th rowspan="2">TDP (W) </th> <th rowspan="2">Cooling system </th> <th rowspan="2">Form factor </th> <th rowspan="2">Released </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th>Quantity </th> <th><abbr title="Bandwidth">BW</abbr> </th> <th colspan="1">Capacity </th> <th><abbr title="Bandwidth">BW</abbr> </th></tr> <tr> <td>Xeon Phi 7220A<a href="#cite_note-87">[87]</a> </td> <td>SC7220A </td> <td rowspan="3">68 (272) </td> <td rowspan="2">1200 </td> <td rowspan="2">1400 </td> <td rowspan="3">34 MB </td> <td rowspan="3">16 GB </td> <td rowspan="3">400+ GB/s </td> <td rowspan="3">384 GB </td> <td rowspan="3">102.4 GB/s </td> <td rowspan="3">275 </td> <td>Active heatsink </td> <td rowspan="3">PCIe 3.0 x16 card </td> <td rowspan="3">??? </td></tr> <tr> <td>Xeon Phi 7220P<a href="#cite_note-88">[88]</a> </td> <td>SC7220P </td> <td rowspan="2">Passive heatsink </td></tr> <tr> <td>Xeon Phi 7240P<a href="#cite_note-89">[89]</a> </td> <td>SC7240P </td> <td>1300 </td> <td>1500 </td></tr></tbody></table> <table class="wikitable sortable"> <caption>Models of Xeon Phi X200 CPU Series </caption> <tbody><tr> <th rowspan="2">Xeon Phi 7200 Series </th> <th rowspan="2"><a href="/w/index.php?title=SSpec&action=edit&redlink=1" class="new" title="SSpec (page does not exist)">sSpec</a> number </th> <th rowspan="2">Cores (Threads) </th> <th colspan="2">Clock (MHz) </th> <th rowspan="2">L2 cache </th> <th colspan="2">MCDRAM memory </th> <th colspan="2">DDR4 memory </th> <th rowspan="2">Peak DP compute </th> <th rowspan="2"><a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a> (W) </th> <th rowspan="2" class="unsortable">Socket </th> <th rowspan="2" class="unsortable">Release date </th> <th rowspan="2">Part number </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Quantity </th> <th class="unsortable"><abbr title="Bandwidth">BW</abbr> </th> <th class="unsortable">Capacity </th> <th class="unsortable"><abbr title="Bandwidth">BW</abbr> </th></tr> <tr> <td rowspan="2">Xeon Phi 7210<a href="#cite_note-90">[90]</a> </td> <td>SR2ME (B0) </td> <td rowspan="6">64 (256) </td> <td rowspan="6">1300 </td> <td rowspan="6">1500 </td> <td rowspan="6">32 MB </td> <td rowspan="11">16 GB </td> <td rowspan="11">400+ GB/s </td> <td rowspan="11">384 GB </td> <td rowspan="11">102.4 GB/s </td> <td rowspan="6">2662 GFLOPS </td> <td rowspan="2">215 </td> <td rowspan="11" style="text-align:center; vertical-align: center;">SVLCLGA3647 </td> <td rowspan="11">20 June 2016 </td> <td rowspan="2">HJ8066702859300 </td></tr> <tr> <td>SR2X4 (B0) </td></tr> <tr> <td>Xeon Phi 7210F<a href="#cite_note-91">[91]</a> </td> <td>SR2X5 (B0) </td> <td>230 </td> <td>HJ8066702975000 </td></tr> <tr> <td rowspan="2">Xeon Phi 7230<a href="#cite_note-92">[92]</a> </td> <td>SR2MF (B0) </td> <td rowspan="2">215 </td> <td rowspan="2">HJ8066702859400 </td></tr> <tr> <td>SR2X3 (B0) </td></tr> <tr> <td>Xeon Phi 7230F<a href="#cite_note-93">[93]</a> </td> <td>SR2X2 (B0) </td> <td>230 </td> <td>HJ8066702269002 </td></tr> <tr> <td rowspan="2">Xeon Phi 7250<a href="#cite_note-94">[94]</a> </td> <td>SR2MD (B0) </td> <td rowspan="3">68 (272) </td> <td rowspan="3">1400 </td> <td rowspan="3">1600 </td> <td rowspan="3">34 MB </td> <td rowspan="3">3046 GFLOPS<a href="#cite_note-95">[95]</a> </td> <td rowspan="2">215 </td> <td rowspan="2">HJ8066702859200 </td></tr> <tr> <td>SR2X1 (B0) </td></tr> <tr> <td>Xeon Phi 7250F<a href="#cite_note-96">[96]</a> </td> <td>SR2X0 (B0) </td> <td>230 </td> <td>HJ8066702268900 </td></tr> <tr> <td>Xeon Phi 7290<a href="#cite_note-97">[97]</a> </td> <td>SR2WY (B0) </td> <td rowspan="2">72 (288) </td> <td rowspan="2">1500 </td> <td rowspan="2">1700 </td> <td rowspan="2">36 MB </td> <td rowspan="2">3456 GFLOPS </td> <td>245 </td> <td>HJ8066702974700 </td></tr> <tr> <td>Xeon Phi 7290F<a href="#cite_note-98">[98]</a> </td> <td>SR2WZ (B0) </td> <td>260 </td> <td>HJ8066702975200 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Knights_Mill">Knights Mill</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=8" title="Edit section: Knights Mill">edit</a>]</div> Knights Mill is Intel's codename for a Xeon Phi product specialized in <a href="/wiki/Deep_learning" title="Deep learning">deep learning</a>,<a href="#cite_note-99">[99]</a> initially released in December 2017.<a href="#cite_note-100">[100]</a> Nearly identical in specifications to Knights Landing, Knights Mill includes optimizations for better utilization of AVX-512 instructions. Single-precision and variable-precision floating-point performance increased, at the expense of double-precision floating-point performance. <dl><dt>Models</dt></dl> <table class="wikitable sortable"> <caption>Models of Xeon Phi X205 CPU Series </caption> <tbody><tr> <th rowspan="2">Xeon Phi 72x5 Series </th> <th rowspan="2"><a href="/w/index.php?title=SSpec&action=edit&redlink=1" class="new" title="SSpec (page does not exist)">sSpec</a> number </th> <th rowspan="2">Cores (Threads) </th> <th colspan="2">Clock (MHz) </th> <th rowspan="2">L2 cache </th> <th colspan="2">MCDRAM memory </th> <th colspan="2">DDR4 memory </th> <th rowspan="2">Peak DP compute </th> <th rowspan="2"><a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a> (W) </th> <th rowspan="2" class="unsortable">Socket </th> <th rowspan="2" class="unsortable">Release date </th> <th rowspan="2">Part number </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Quantity </th> <th class="unsortable"><abbr title="Bandwidth">BW</abbr> </th> <th class="unsortable">Capacity </th> <th class="unsortable"><abbr title="Bandwidth">BW</abbr> </th></tr> <tr> <td>Xeon Phi 7235 </td> <td>SR3VF (A0) </td> <td>64 (256) </td> <td>1300 </td> <td>1400 </td> <td>32 MB </td> <td rowspan="4">16 GB </td> <td rowspan="4">400+ GB/s </td> <td rowspan="4">384 GB </td> <td>102.4 GB/s </td> <td data-sort-value="" style="background: #DDF; color:black; vertical-align: middle; text-align: center;" class="skin-invert no table-no2"><abbr title="To be announced">TBA</abbr> </td> <td>250 </td> <td rowspan="4">SVLCLGA3647 </td> <td rowspan="4">Q4 2017 </td> <td>HJ8068303823900 </td></tr> <tr> <td>Xeon Phi 7255 </td> <td>SR3VG (A0) </td> <td>68 (272) </td> <td>1100 </td> <td>1200 </td> <td>34 MB </td> <td>115.2 GB/s </td> <td data-sort-value="" style="background: #DDF; color:black; vertical-align: middle; text-align: center;" class="skin-invert no table-no2"><abbr title="To be announced">TBA</abbr> </td> <td>215 </td> <td>HJ8068303826300 </td></tr> <tr> <td>Xeon Phi 7285 </td> <td>SR3VE (A0) </td> <td>68 (272) </td> <td>1300 </td> <td>1400 </td> <td>34 MB </td> <td>115.2 GB/s </td> <td data-sort-value="" style="background: #DDF; color:black; vertical-align: middle; text-align: center;" class="skin-invert no table-no2"><abbr title="To be announced">TBA</abbr> </td> <td>250 </td> <td>HJ8068303823800 </td></tr> <tr> <td>Xeon Phi 7295 </td> <td>SR3VD (A0) </td> <td>72 (288) </td> <td>1500 </td> <td>1600 </td> <td>36 MB </td> <td>115.2 GB/s </td> <td data-sort-value="" style="background: #DDF; color:black; vertical-align: middle; text-align: center;" class="skin-invert no table-no2"><abbr title="To be announced">TBA</abbr> </td> <td>320 </td> <td>HJ8068303823700 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Knights_Hill">Knights Hill</h3>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=9" title="Edit section: Knights Hill">edit</a>]</div> Knights Hill was the codename for the third-generation MIC architecture, for which Intel announced the first details at SC14.<a href="#cite_note-101">[101]</a> It was to be manufactured in a 10 nm process.<a href="#cite_note-102">[102]</a> Knights Hill was expected to be used in the <a href="/wiki/United_States_Department_of_Energy" title="United States Department of Energy">United States Department of Energy</a> <a href="/wiki/Aurora_(supercomputer)" title="Aurora (supercomputer)">Aurora supercomputer</a>, to be deployed at <a href="/wiki/Argonne_National_Laboratory" title="Argonne National Laboratory">Argonne National Laboratory</a>.<a href="#cite_note-103">[103]</a><a href="#cite_note-104">[104]</a> However, Aurora was delayed in favor of using an "advanced architecture" with a focus on machine learning.<a href="#cite_note-105">[105]</a><a href="#cite_note-106">[106]</a> In 2017, Intel announced that Knights Hill had been canceled in favor of another architecture built from the ground up to enable <a href="/wiki/Exascale_computing" title="Exascale computing">Exascale computing</a> in the future. This new architecture is now expected for 2020–2021[<a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers">needs update</a>].<a href="#cite_note-107">[107]</a><a href="#cite_note-108">[108]</a> <div class="mw-heading mw-heading2"><h2 id="Programming">Programming</h2>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=10" title="Edit section: Programming">edit</a>]</div> One performance and programmability study reported that achieving high performance with Xeon Phi still needs help from programmers and that merely relying on compilers with traditional programming models is insufficient.<a href="#cite_note-comprehensive-109">[109]</a> Other studies in various domains, such as life sciences<a href="#cite_note-110">[110]</a> and deep learning,<a href="#cite_note-111">[111]</a> have shown that exploiting the thread- and SIMD-parallelism of Xeon Phi achieves significant speed-ups. <div class="mw-heading mw-heading2"><h2 id="Competitors">Competitors</h2>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=11" title="Edit section: Competitors">edit</a>]</div> <ul><li><a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Nvidia Tesla</a>, a direct competitor in the <a href="/wiki/High-performance_computing" title="High-performance computing">HPC</a> market<a href="#cite_note-112">[112]</a></li> <li><a href="/wiki/AMD_Radeon_Pro" class="mw-redirect" title="AMD Radeon Pro">AMD Radeon Pro</a> and <a href="/wiki/Radeon_Instinct" class="mw-redirect" title="Radeon Instinct">AMD Radeon Instinct</a> direct competitors in the HPC market</li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=12" title="Edit section: See also">edit</a>]</div> <ul><li><a href="/wiki/Texas_Advanced_Computing_Center" title="Texas Advanced Computing Center">Texas Advanced Computing Center</a> – "Stampede" supercomputer incorporates Xeon Phi chips.<a href="#cite_note-StampedeSupercomputerXeonPhi-113">[113]</a> Stampede is capable of 10 petaFLOPS.<a href="#cite_note-StampedeSupercomputerXeonPhi-113">[113]</a></li> <li><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a></li> <li><a href="/wiki/Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">Cell (microprocessor)</a></li> <li><a href="/wiki/Intel_Tera-Scale" title="Intel Tera-Scale">Intel Tera-Scale</a></li> <li><a href="/wiki/Massively_parallel" title="Massively parallel">Massively parallel</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=Xeon_Phi&action=edit&section=13" title="Edit section: References">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist 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sistersitebox"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"> <div class="side-box-flex"> <div class="side-box-image"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/30px-Commons-logo.svg.png" decoding="async" width="30" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/45px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/59px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></div> <div class="side-box-text plainlist">Wikimedia Commons has media related to <a href="https://commons.wikimedia.org/wiki/Category:Xeon_Phi" class="extiw" title="commons:Category:Xeon Phi">Xeon Phi</a>.</div></div> </div> <ul><li>Intel pages: <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/processors/xeon-phi/xeon-phi-processors.html">Intel Xeon Phi Processors</a></li> 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style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=Xeon_Phi&oldid=1258957169">https://en.wikipedia.org/w/index.php?title=Xeon_Phi&oldid=1258957169</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Coprocessors" title="Category:Coprocessors">Coprocessors</a></li><li><a href="/wiki/Category:Intel" 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