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id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=Static_logic_(digital_logic)&redirect=no" class="mw-redirect" title="Static logic (digital logic)">Static logic (digital logic)</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Design methodology for combinatorial logic integrated circuits</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">For the subject in <a href="/wiki/Theoretical_computer_science" title="Theoretical computer science">theoretical computer science</a>, see <a href="/wiki/Dynamic_logic_(modal_logic)" title="Dynamic logic (modal logic)">dynamic logic (modal logic)</a>.</div> <p>In <a href="/wiki/Integrated_circuit_design" title="Integrated circuit design">integrated circuit design</a>, <b>dynamic logic</b> (or sometimes <b>clocked logic</b>) is a design methodology in <a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a> circuits, particularly those implemented in <a href="/wiki/MOSFET" title="MOSFET">metal–oxide–semiconductor</a> (MOS) technology. It is distinguished from the so-called <a href="/wiki/Static_logic" class="mw-redirect" title="Static logic">static logic</a> by exploiting temporary storage of information in <a href="/wiki/Stray_capacitance" class="mw-redirect" title="Stray capacitance">stray</a> and <a href="/wiki/Gate_capacitance" title="Gate capacitance">gate capacitances</a>.<sup id="cite_ref-Wanhammar1999_1-0" class="reference"><a href="#cite_note-Wanhammar1999-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> It was popular in the 1970s and has seen a recent resurgence in the design of high-speed <a href="/wiki/Digital_electronics" title="Digital electronics">digital electronics</a><sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="There is no evidence that dynamic logic is used for modern digital circuits (April 2023)">citation needed</span></a></i>]</sup>, particularly <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic,<sup id="cite_ref-MarshallNatarajan2002_2-0" class="reference"><a href="#cite_note-MarshallNatarajan2002-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> but the <a href="/wiki/CPU_power_dissipation" class="mw-redirect" title="CPU power dissipation">capacitive loads</a> being transitioned are smaller<sup id="cite_ref-Raj/latha_3-0" class="reference"><a href="#cite_note-Raj/latha-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> so the overall <a href="/wiki/Power_consumption" class="mw-redirect" title="Power consumption">power consumption</a> of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular <a href="/wiki/Logic_family" title="Logic family">logic family</a>, the dynamic adjective usually suffices to distinguish the design methodology, e.g. <i>dynamic <a href="/wiki/CMOS" title="CMOS">CMOS</a></i><sup id="cite_ref-JacobNg2007_4-0" class="reference"><a href="#cite_note-JacobNg2007-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> or <i>dynamic <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a></i> design.<sup id="cite_ref-MarshallNatarajan2002_2-1" class="reference"><a href="#cite_note-MarshallNatarajan2002-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>Besides its use of dynamic state storage via voltages on capacitances, dynamic logic is distinguished from so-called <i>static logic</i> in that dynamic logic uses a <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a> in its implementation of combinational logic. The usual use of a clock signal is to synchronize transitions in <a href="/wiki/Sequential_logic" title="Sequential logic">sequential logic</a> circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. <a href="/wiki/Static_RAM" class="mw-redirect" title="Static RAM">static RAM</a> from <a href="/wiki/Dynamic_RAM" class="mw-redirect" title="Dynamic RAM">dynamic RAM</a>, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.<sup id="cite_ref-Harris2001_5-0" class="reference"><a href="#cite_note-Harris2001-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Static_versus_dynamic_logic">Static versus dynamic logic</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=1" title="Edit section: Static versus dynamic logic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The largest difference between static and dynamic logic is that in dynamic logic, a <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a> is used to evaluate <a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a>. In most types of logic design, termed <i>static logic</i>, there is always some mechanism to drive the output either high or low. In many of the popular logic styles, such as <a href="/wiki/Transistor-transistor_logic" class="mw-redirect" title="Transistor-transistor logic">TTL</a> and traditional <a href="/wiki/CMOS" title="CMOS">CMOS</a>, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply <a href="/wiki/Voltage" title="Voltage">voltage</a> or the <a href="/wiki/Ground_(electricity)" title="Ground (electricity)">ground</a>. As a side note, there is, of course, an exception in this definition in the case of high <a href="/wiki/Electrical_impedance" title="Electrical impedance">impedance</a> outputs, such as a <a href="/wiki/Tri-state_buffer" class="mw-redirect" title="Tri-state buffer">tri-state buffer</a>; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic. </p><p>In contrast, in <i>dynamic logic</i>, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level. </p><p>Dynamic logic requires a minimum <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven. </p><p>Static logic has no minimum <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a>—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages: </p> <ul><li>being able to pause a system at any time makes debugging and testing much easier, enabling techniques such as <a href="/wiki/Instruction_step" title="Instruction step">single stepping</a>.</li> <li>being able to run a system at extremely low <a href="/wiki/Clock_rate" title="Clock rate">clock rates</a> allows <a href="/wiki/Low-power_electronics" title="Low-power electronics">low-power electronics</a> to run longer on a given battery.</li> <li>a fully-static system can instantly resume exactly where it left off; a person doesn't have to wait for the system to boot up or resume.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li></ul> <p>Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the <a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">6502</a>), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal. </p><p>In particular, although many popular CPUs use dynamic logic,<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (July 2014)">citation needed</span></a></i>]</sup> only <a href="/wiki/Static_core" title="Static core">static cores</a>—CPUs designed with fully static technology—are usable in space satellites owing to their higher <a href="/wiki/Radiation_hardening" title="Radiation hardening">radiation hardness</a>.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template noprint noexcerpt Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:NOTRS" class="mw-redirect" title="Wikipedia:NOTRS"><span title="Citation discusses radiation hardness as pertaining to a specific project, but does not clearly or reliably make or support the claim that this makes fully-static logic families mandatory. (September 2021)">better source needed</span></a></i>]</sup> </p><p>When properly designed, dynamic logic can be over twice as fast as static logic. It uses only the <a href="/wiki/MOSFET#Single-type" title="MOSFET">faster NMOS transistors</a>, which improves transistor sizing optimizations. Static logic is slower because it has twice the <a href="/wiki/Capacitor" title="Capacitor">capacitive</a> <a href="/wiki/Electronic_load" class="mw-redirect" title="Electronic load">loading</a>, higher <a href="/wiki/Threshold_voltage" title="Threshold voltage">thresholds</a>, and uses slow PMOS transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days <sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The time period mentioned near this tag is ambiguous. (February 2011)">when?</span></a></i>]</sup> require dynamic logic, although some manufacturers such as Intel have designed chips using completely static logic to reduce power consumption.<sup id="cite_ref-anandtech_8-0" class="reference"><a href="#cite_note-anandtech-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost. </p><p>In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS.<sup id="cite_ref-anandtech_8-1" class="reference"><a href="#cite_note-anandtech-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> There are several <a href="/wiki/Low-power_electronics" title="Low-power electronics">powersaving techniques</a> that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic. </p> <div class="mw-heading mw-heading2"><h2 id="Static_logic_example">Static logic example</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=2" title="Edit section: Static logic example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As an example, consider the static logic implementation of a CMOS NAND gate: </p> <figure class="mw-halign-center" typeof="mw:File"><a href="/wiki/File:CMOS_NAND.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e2/CMOS_NAND.svg/150px-CMOS_NAND.svg.png" decoding="async" width="150" height="244" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e2/CMOS_NAND.svg/225px-CMOS_NAND.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e2/CMOS_NAND.svg/300px-CMOS_NAND.svg.png 2x" data-file-width="310" data-file-height="505" /></a><figcaption></figcaption></figure> <p>This circuit implements the logic function </p> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle Out={\overline {AB}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mi>O</mi> <mi>u</mi> <mi>t</mi> <mo>=</mo> <mrow class="MJX-TeXAtom-ORD"> <mover> <mrow> <mi>A</mi> <mi>B</mi> </mrow> <mo accent="false">¯</mo> </mover> </mrow> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle Out={\overline {AB}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/4da1e58dcb1325294c4703e699b08089c8a77258" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:10.663ex; height:3.009ex;" alt="{\displaystyle Out={\overline {AB}}}"></span></dd></dl> <p>If <i>A</i> and <i>B</i> are both high, the output will be pulled low. If either <i>A</i> or <i>B</i> are low, the output will be pulled high. At all times, the output is pulled either low or high. </p> <div class="mw-heading mw-heading2"><h2 id="Dynamic_logic_example">Dynamic logic example</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=3" title="Edit section: Dynamic logic example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Consider now a dynamic logic implementation of the same logic function: </p> <figure class="mw-halign-center" typeof="mw:File"><a href="/wiki/File:Dlnand.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/18/Dlnand.svg/200px-Dlnand.svg.png" decoding="async" width="200" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/18/Dlnand.svg/300px-Dlnand.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/18/Dlnand.svg/400px-Dlnand.svg.png 2x" data-file-width="801" data-file-height="1173" /></a><figcaption></figcaption></figure> <p>The dynamic logic circuit requires two phases. The first phase, when <i>Clock</i> is low, is called the <i>setup phase</i> or the <i>precharge phase</i>, and the second phase, when <i>Clock</i> is high, is called the <i>evaluation phase</i>. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs <i>A</i> and <i>B</i>). The <a href="/wiki/Capacitor" title="Capacitor">capacitor</a>, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase. </p><p>During the <i>evaluation phase</i>, <i>Clock</i> is high. If <i>A</i> and <i>B</i> are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance). </p><p>Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously when it is valid. </p><p>Also, when both <i>A</i> and <i>B</i> are high, so that the output is low, the circuit will pump one capacitor load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the <i>A</i> and <i>B</i> inputs are constant and both high, the dynamic NAND gate uses power in proportion to the <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a>, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low. This, in turn, reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit derived from an equilibrium between clock speed and load capacitance. </p><p>A popular implementation is <a href="/wiki/Domino_logic" title="Domino logic">domino logic</a>. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=4" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Domino_logic" title="Domino logic">Domino logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=5" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-Wanhammar1999-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-Wanhammar1999_1-0">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFLars_Wanhammar1999" class="citation book cs1">Lars Wanhammar (1999). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=O88sXLox7tAC&pg=PA37"><i>DSP integrated circuits</i></a>. Academic Press. p. 37. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-734530-7" title="Special:BookSources/978-0-12-734530-7"><bdi>978-0-12-734530-7</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=DSP+integrated+circuits&rft.pages=37&rft.pub=Academic+Press&rft.date=1999&rft.isbn=978-0-12-734530-7&rft.au=Lars+Wanhammar&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DO88sXLox7tAC%26pg%3DPA37&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-MarshallNatarajan2002-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-MarshallNatarajan2002_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-MarshallNatarajan2002_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndrew_MarshallSreedhar_Natarajan2002" class="citation book cs1">Andrew Marshall; Sreedhar Natarajan (2002). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=EgXw8sjIX0oC&pg=PA125"><i>SOI design: analog, memory and digital techniques</i></a>. Springer. p. 125. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7923-7640-8" title="Special:BookSources/978-0-7923-7640-8"><bdi>978-0-7923-7640-8</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=SOI+design%3A+analog%2C+memory+and+digital+techniques&rft.pages=125&rft.pub=Springer&rft.date=2002&rft.isbn=978-0-7923-7640-8&rft.au=Andrew+Marshall&rft.au=Sreedhar+Natarajan&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DEgXw8sjIX0oC%26pg%3DPA125&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-Raj/latha-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-Raj/latha_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFA._Albert_Raj,_T._Latha2008" class="citation book cs1">A. Albert Raj, T. Latha (21 October 2008). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=Fg3PBibITjAC&pg=PA167"><i>VLSI Design</i></a>. PHI Learning Pvt. Ltd. p. 167. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-81-203-3431-1" title="Special:BookSources/978-81-203-3431-1"><bdi>978-81-203-3431-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=VLSI+Design&rft.pages=167&rft.pub=PHI+Learning+Pvt.+Ltd.&rft.date=2008-10-21&rft.isbn=978-81-203-3431-1&rft.au=A.+Albert+Raj%2C+T.+Latha&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DFg3PBibITjAC%26pg%3DPA167&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-JacobNg2007-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-JacobNg2007_4-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBruce_JacobSpencer_NgDavid_Wang2007" class="citation book cs1">Bruce Jacob; Spencer Ng; David Wang (2007). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=G-D6KFwnVsgC&pg=PA270"><i>Memory systems: cache, DRAM, disk</i></a>. Morgan Kaufmann. p. 270. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-379751-3" title="Special:BookSources/978-0-12-379751-3"><bdi>978-0-12-379751-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Memory+systems%3A+cache%2C+DRAM%2C+disk&rft.pages=270&rft.pub=Morgan+Kaufmann&rft.date=2007&rft.isbn=978-0-12-379751-3&rft.au=Bruce+Jacob&rft.au=Spencer+Ng&rft.au=David+Wang&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DG-D6KFwnVsgC%26pg%3DPA270&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-Harris2001-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-Harris2001_5-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDavid_Harris2001" class="citation book cs1">David Harris (2001). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=Sg23rIYuIPEC&pg=PA38"><i>Skew-tolerant circuit design</i></a>. Morgan Kaufmann. p. 38. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-55860-636-4" title="Special:BookSources/978-1-55860-636-4"><bdi>978-1-55860-636-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Skew-tolerant+circuit+design&rft.pages=38&rft.pub=Morgan+Kaufmann&rft.date=2001&rft.isbn=978-1-55860-636-4&rft.au=David+Harris&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DSg23rIYuIPEC%26pg%3DPA38&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"> Richard Murray. <a rel="nofollow" class="external text" href="https://heyrick.eu/software/pb2/hardware.html">"PocketBook II hardware"</a>.</span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGülzow" class="citation web cs1">Gülzow, Peter. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130413133157/http://www.amsat-dl.org/yahue.html">"No RISC, No Fun!"</a>. <i>AMSAT-DL</i>. Translated by Moe, Don. Archived from <a rel="nofollow" class="external text" href="https://amsat-dl.org/yahue.html/">the original</a> on 13 April 2013<span class="reference-accessdate">. Retrieved <span class="nowrap">15 September</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMSAT-DL&rft.atitle=No+RISC%2C+No+Fun%21&rft.aulast=G%C3%BClzow&rft.aufirst=Peter&rft_id=https%3A%2F%2Famsat-dl.org%2Fyahue.html%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> <li id="cite_note-anandtech-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-anandtech_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-anandtech_8-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448&p=9">"The Dark Knight: Intel's Core i7"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+Dark+Knight%3A+Intel%27s+Core+i7&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fcpuchipsets%2Fintel%2Fshowdoc.aspx%3Fi%3D3448%26p%3D9&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span></span> </li> </ol></div></div> <p><b>General references</b> </p> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSung-Mo_KangYusuf_Leblebici2003" class="citation book cs1">Sung-Mo Kang; Yusuf Leblebici (2003). <i>CMOS digital integrated circuits: analysis and design</i> (3rd ed.). McGraw-Hill. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-07-246053-7" title="Special:BookSources/978-0-07-246053-7"><bdi>978-0-07-246053-7</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=CMOS+digital+integrated+circuits%3A+analysis+and+design&rft.edition=3rd&rft.pub=McGraw-Hill&rft.date=2003&rft.isbn=978-0-07-246053-7&rft.au=Sung-Mo+Kang&rft.au=Yusuf+Leblebici&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span> Chapter 9, "Dynamic logic circuits" (chapter 7 in the 2nd edition)</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFR._Jacob_Baker2010" class="citation book cs1">R. Jacob Baker (2010). <i>CMOS: Circuit Design, Layout, and Simulation</i> (3rd ed.). Wiley-IEEE. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-470-88132-3" title="Special:BookSources/978-0-470-88132-3"><bdi>978-0-470-88132-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=CMOS%3A+Circuit+Design%2C+Layout%2C+and+Simulation&rft.edition=3rd&rft.pub=Wiley-IEEE&rft.date=2010&rft.isbn=978-0-470-88132-3&rft.au=R.+Jacob+Baker&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span> Chapter 14, "Dynamic logic gates"</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAndrew_MarshallSreedhar_Natarajan2002" class="citation book cs1">Andrew Marshall; Sreedhar Natarajan (2002). <i>SOI design: analog, memory and digital techniques</i>. Springer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7923-7640-8" title="Special:BookSources/978-0-7923-7640-8"><bdi>978-0-7923-7640-8</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=SOI+design%3A+analog%2C+memory+and+digital+techniques&rft.pub=Springer&rft.date=2002&rft.isbn=978-0-7923-7640-8&rft.au=Andrew+Marshall&rft.au=Sreedhar+Natarajan&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADynamic+logic+%28digital+electronics%29" class="Z3988"></span> Chapter 7, "Dynamic SOI Design"</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Dynamic_logic_(digital_electronics)&action=edit&section=6" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.cmosvlsi.com/lect9.pdf">Introduction to CMOS VLSI Design – Lecture 9: Circuit Families</a> – David Harris' lecture notes on the subject.</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul 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