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id="toc-Desktop_processors-sublist" class="vector-toc-list"> <li id="toc-Core_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Core 2</span> </div> </a> <ul id="toc-Core_2-sublist" class="vector-toc-list"> <li id="toc-"Allendale"_(65_nm,_800_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Allendale"_(65_nm,_800_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.1</span> <span>"Allendale" (65 nm, 800 MT/s)</span> </div> </a> <ul id="toc-"Allendale"_(65_nm,_800_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Conroe"_(65_nm,_1066_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Conroe"_(65_nm,_1066_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.2</span> <span>"Conroe" (65 nm, 1066 MT/s)</span> </div> </a> <ul id="toc-"Conroe"_(65_nm,_1066_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Conroe"_(65_nm,_1333_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Conroe"_(65_nm,_1333_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.3</span> <span>"Conroe" (65 nm, 1333 MT/s)</span> </div> </a> <ul id="toc-"Conroe"_(65_nm,_1333_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Conroe-CL"_(65_nm,_1066_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Conroe-CL"_(65_nm,_1066_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.4</span> <span>"Conroe-CL" (65 nm, 1066 MT/s)</span> </div> </a> <ul id="toc-"Conroe-CL"_(65_nm,_1066_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Conroe_XE"_(65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Conroe_XE"_(65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.5</span> <span>"Conroe XE" (65 nm)</span> </div> </a> <ul id="toc-"Conroe_XE"_(65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kentsfield"_(65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kentsfield"_(65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.6</span> <span>"Kentsfield" (65 nm)</span> </div> </a> <ul id="toc-"Kentsfield"_(65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kentsfield_XE"_(65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kentsfield_XE"_(65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.7</span> <span>"Kentsfield XE" (65 nm)</span> </div> </a> <ul id="toc-"Kentsfield_XE"_(65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Wolfdale-3M"_(45_nm,_1066_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Wolfdale-3M"_(45_nm,_1066_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.8</span> <span>"Wolfdale-3M" (45 nm, 1066 MT/s)</span> </div> </a> <ul id="toc-"Wolfdale-3M"_(45_nm,_1066_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Wolfdale"_(45_nm,_1333_MT/s)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Wolfdale"_(45_nm,_1333_MT/s)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.9</span> <span>"Wolfdale" (45 nm, 1333 MT/s)</span> </div> </a> <ul id="toc-"Wolfdale"_(45_nm,_1333_MT/s)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Yorkfield-6M"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Yorkfield-6M"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.10</span> <span>"Yorkfield-6M" (45 nm)</span> </div> </a> <ul id="toc-"Yorkfield-6M"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Yorkfield_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Yorkfield_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.11</span> <span>Yorkfield (45 nm)</span> </div> </a> <ul id="toc-Yorkfield_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Yorkfield_XE"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Yorkfield_XE"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1.12</span> <span>"Yorkfield XE" (45 nm)</span> </div> </a> <ul id="toc-"Yorkfield_XE"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(1st_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(1st_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Core i (1st gen)</span> </div> </a> <ul id="toc-Core_i_(1st_gen)-sublist" class="vector-toc-list"> <li id="toc-Lynnfield" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Lynnfield"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.1</span> <span>Lynnfield</span> </div> </a> <ul id="toc-Lynnfield-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bloomfield" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Bloomfield"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.2</span> <span>Bloomfield</span> </div> </a> <ul id="toc-Bloomfield-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Clarkdale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Clarkdale"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.3</span> <span>Clarkdale</span> </div> </a> <ul id="toc-Clarkdale-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gulftown" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Gulftown"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2.4</span> <span>Gulftown</span> </div> </a> <ul id="toc-Gulftown-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(2nd_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(2nd_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Core i (2nd gen)</span> </div> </a> <ul id="toc-Core_i_(2nd_gen)-sublist" class="vector-toc-list"> <li id="toc-Sandy_Bridge-DT" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sandy_Bridge-DT"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3.1</span> <span>Sandy Bridge-DT</span> </div> </a> <ul id="toc-Sandy_Bridge-DT-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(3rd_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(3rd_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Core i (3rd gen)</span> </div> </a> <ul id="toc-Core_i_(3rd_gen)-sublist" class="vector-toc-list"> <li id="toc-Ivy_Bridge-DT" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ivy_Bridge-DT"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4.1</span> <span>Ivy Bridge-DT</span> </div> </a> <ul id="toc-Ivy_Bridge-DT-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sandy_Bridge-E" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sandy_Bridge-E"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4.2</span> <span>Sandy Bridge-E</span> </div> </a> <ul id="toc-Sandy_Bridge-E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(4th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(4th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5</span> <span>Core i (4th gen)</span> </div> </a> <ul id="toc-Core_i_(4th_gen)-sublist" class="vector-toc-list"> <li id="toc-Haswell-DT" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-DT"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5.1</span> <span>Haswell-DT</span> </div> </a> <ul id="toc-Haswell-DT-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5.2</span> <span>Haswell-H</span> </div> </a> <ul id="toc-Haswell-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ivy_Bridge-E" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ivy_Bridge-E"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.5.3</span> <span>Ivy Bridge-E</span> </div> </a> <ul id="toc-Ivy_Bridge-E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(5th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(5th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6</span> <span>Core i (5th gen)</span> </div> </a> <ul id="toc-Core_i_(5th_gen)-sublist" class="vector-toc-list"> <li id="toc-Broadwell-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6.1</span> <span>Broadwell-H</span> </div> </a> <ul id="toc-Broadwell-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-E" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-E"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.6.2</span> <span>Haswell-E</span> </div> </a> <ul id="toc-Haswell-E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(6th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(6th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.7</span> <span>Core i (6th gen)</span> </div> </a> <ul id="toc-Core_i_(6th_gen)-sublist" class="vector-toc-list"> <li id="toc-Skylake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.7.1</span> <span>Skylake-S</span> </div> </a> <ul id="toc-Skylake-S-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.7.2</span> <span>Skylake-H</span> </div> </a> <ul id="toc-Skylake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Broadwell-E" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-E"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.7.3</span> <span>Broadwell-E</span> </div> </a> <ul id="toc-Broadwell-E-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(7th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(7th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.8</span> <span>Core i (7th gen)</span> </div> </a> <ul id="toc-Core_i_(7th_gen)-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.8.1</span> <span>Kaby Lake-S</span> </div> </a> <ul id="toc-Kaby_Lake-S-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-X" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-X"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.8.2</span> <span>Skylake-X</span> </div> </a> <ul id="toc-Skylake-X-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-X" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-X"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.8.3</span> <span>Kaby Lake-X</span> </div> </a> <ul id="toc-Kaby_Lake-X-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(8th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(8th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.9</span> <span>Core i (8th gen)</span> </div> </a> <ul id="toc-Core_i_(8th_gen)-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.9.1</span> <span>Coffee Lake-S</span> </div> </a> <ul id="toc-Coffee_Lake-S-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(9th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(9th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.10</span> <span>Core i (9th gen)</span> </div> </a> <ul id="toc-Core_i_(9th_gen)-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-R" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-R"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.10.1</span> <span>Coffee Lake-R</span> </div> </a> <ul id="toc-Coffee_Lake-R-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-X_(9xxx)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-X_(9xxx)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.10.2</span> <span>Skylake-X (9xxx)</span> </div> </a> <ul id="toc-Skylake-X_(9xxx)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(10th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(10th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.11</span> <span>Core i (10th gen)</span> </div> </a> <ul id="toc-Core_i_(10th_gen)-sublist" class="vector-toc-list"> <li id="toc-Comet_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comet_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.11.1</span> <span>Comet Lake-S</span> </div> </a> <ul id="toc-Comet_Lake-S-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comet_Lake-S_(refresh)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comet_Lake-S_(refresh)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.11.2</span> <span>Comet Lake-S (refresh)</span> </div> </a> <ul id="toc-Comet_Lake-S_(refresh)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cascade_Lake-X_(10xxx)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Cascade_Lake-X_(10xxx)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.11.3</span> <span>Cascade Lake-X (10xxx)</span> </div> </a> <ul id="toc-Cascade_Lake-X_(10xxx)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(11th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(11th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.12</span> <span>Core i (11th gen)</span> </div> </a> <ul id="toc-Core_i_(11th_gen)-sublist" class="vector-toc-list"> <li id="toc-Rocket_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Rocket_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.12.1</span> <span>Rocket Lake-S</span> </div> </a> <ul id="toc-Rocket_Lake-S-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tiger_Lake-B" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-B"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.12.2</span> <span>Tiger Lake-B</span> </div> </a> <ul id="toc-Tiger_Lake-B-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(12th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(12th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.13</span> <span>Core i (12th gen)</span> </div> </a> <ul id="toc-Core_i_(12th_gen)-sublist" class="vector-toc-list"> <li id="toc-Alder_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.13.1</span> <span>Alder Lake-S</span> </div> </a> <ul id="toc-Alder_Lake-S-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(13th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(13th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.14</span> <span>Core i (13th gen)</span> </div> </a> <ul id="toc-Core_i_(13th_gen)-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.14.1</span> <span>Raptor Lake-S</span> </div> </a> <ul id="toc-Raptor_Lake-S-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(14th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(14th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.15</span> <span>Core i (14th gen)</span> </div> </a> <ul id="toc-Core_i_(14th_gen)-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-S_Refresh" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-S_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.15.1</span> <span>Raptor Lake-S Refresh</span> </div> </a> <ul id="toc-Raptor_Lake-S_Refresh-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_Ultra_(Series_2)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_Ultra_(Series_2)"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.16</span> <span>Core Ultra (Series 2)</span> </div> </a> <ul id="toc-Core_Ultra_(Series_2)-sublist" class="vector-toc-list"> <li id="toc-Arrow_Lake-S" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Arrow_Lake-S"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.16.1</span> <span>Arrow Lake-S</span> </div> </a> <ul id="toc-Arrow_Lake-S-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Mobile_processors" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Mobile_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Mobile processors</span> </div> </a> <button aria-controls="toc-Mobile_processors-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Mobile processors subsection</span> </button> <ul id="toc-Mobile_processors-sublist" class="vector-toc-list"> <li id="toc-Core" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Core</span> </div> </a> <ul id="toc-Core-sublist" class="vector-toc-list"> <li id="toc-Yonah" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Yonah"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.1</span> <span>Yonah</span> </div> </a> <ul id="toc-Yonah-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_2_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_2_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Core 2</span> </div> </a> <ul id="toc-Core_2_2-sublist" class="vector-toc-list"> <li id="toc-"Merom-L"_(65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merom-L"_(65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.1</span> <span>"Merom-L" (65 nm)</span> </div> </a> <ul id="toc-"Merom-L"_(65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Merom",_"Merom-2M"_(standard-voltage,_65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merom",_"Merom-2M"_(standard-voltage,_65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.2</span> <span>"Merom", "Merom-2M" (standard-voltage, 65 nm)</span> </div> </a> <ul id="toc-"Merom",_"Merom-2M"_(standard-voltage,_65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Merom"_(low-voltage,_65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merom"_(low-voltage,_65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.3</span> <span>"Merom" (low-voltage, 65 nm)</span> </div> </a> <ul id="toc-"Merom"_(low-voltage,_65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Merom-2M"_(ultra-low-voltage,_65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merom-2M"_(ultra-low-voltage,_65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.4</span> <span>"Merom-2M" (ultra-low-voltage, 65 nm)</span> </div> </a> <ul id="toc-"Merom-2M"_(ultra-low-voltage,_65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Merom_XE"_(65_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merom_XE"_(65_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.5</span> <span>"Merom XE" (65 nm)</span> </div> </a> <ul id="toc-"Merom_XE"_(65_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn-L"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn-L"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.6</span> <span>"Penryn-L" (45 nm)</span> </div> </a> <ul id="toc-"Penryn-L"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn"_(Apple_iMac_specific,_45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn"_(Apple_iMac_specific,_45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.7</span> <span>"Penryn" (Apple iMac specific, 45 nm)</span> </div> </a> <ul id="toc-"Penryn"_(Apple_iMac_specific,_45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn",_"Penryn-3M"_(standard-voltage,_45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn",_"Penryn-3M"_(standard-voltage,_45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.8</span> <span>"Penryn", "Penryn-3M" (standard-voltage, 45 nm)</span> </div> </a> <ul id="toc-"Penryn",_"Penryn-3M"_(standard-voltage,_45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn",_"Penryn-3M"_(medium-voltage,_45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn",_"Penryn-3M"_(medium-voltage,_45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.9</span> <span>"Penryn", "Penryn-3M" (medium-voltage, 45 nm)</span> </div> </a> <ul id="toc-"Penryn",_"Penryn-3M"_(medium-voltage,_45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn"_(medium-voltage,_45_nm,_Small_Form_Factor)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn"_(medium-voltage,_45_nm,_Small_Form_Factor)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.10</span> <span>"Penryn" (medium-voltage, 45 nm, Small Form Factor)</span> </div> </a> <ul id="toc-"Penryn"_(medium-voltage,_45_nm,_Small_Form_Factor)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn"_(low-voltage,_45_nm,_Small_Form_Factor)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn"_(low-voltage,_45_nm,_Small_Form_Factor)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.11</span> <span>"Penryn" (low-voltage, 45 nm, Small Form Factor)</span> </div> </a> <ul id="toc-"Penryn"_(low-voltage,_45_nm,_Small_Form_Factor)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.12</span> <span>"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)</span> </div> </a> <ul id="toc-"Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn_XE"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn_XE"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.13</span> <span>"Penryn XE" (45 nm)</span> </div> </a> <ul id="toc-"Penryn_XE"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn_QC"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn_QC"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.14</span> <span>"Penryn QC" (45 nm)</span> </div> </a> <ul id="toc-"Penryn_QC"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Penryn_QC_XE"_(45_nm)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Penryn_QC_XE"_(45_nm)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.15</span> <span>"Penryn QC XE" (45 nm)</span> </div> </a> <ul id="toc-"Penryn_QC_XE"_(45_nm)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(1st_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(1st_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Core i (1st gen)</span> </div> </a> <ul id="toc-Core_i_(1st_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Clarksfield" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Clarksfield"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>Clarksfield</span> </div> </a> <ul id="toc-Clarksfield-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Arrandale" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Arrandale"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.2</span> <span>Arrandale</span> </div> </a> <ul id="toc-Arrandale-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(2nd_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(2nd_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Core i (2nd gen)</span> </div> </a> <ul id="toc-Core_i_(2nd_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Sandy_Bridge-M" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sandy_Bridge-M"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>Sandy Bridge-M</span> </div> </a> <ul id="toc-Sandy_Bridge-M-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(3rd_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(3rd_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5</span> <span>Core i (3rd gen)</span> </div> </a> <ul id="toc-Core_i_(3rd_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Ivy_Bridge" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ivy_Bridge"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.5.1</span> <span>Ivy Bridge</span> </div> </a> <ul id="toc-Ivy_Bridge-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(4th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(4th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6</span> <span>Core i (4th gen)</span> </div> </a> <ul id="toc-Core_i_(4th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Haswell-MB" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-MB"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6.1</span> <span>Haswell-MB</span> </div> </a> <ul id="toc-Haswell-MB-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-ULT" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-ULT"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6.2</span> <span>Haswell-ULT</span> </div> </a> <ul id="toc-Haswell-ULT-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-ULX" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-ULX"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6.3</span> <span>Haswell-ULX</span> </div> </a> <ul id="toc-Haswell-ULX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.6.4</span> <span>Haswell-H</span> </div> </a> <ul id="toc-Haswell-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(5th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(5th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7</span> <span>Core i (5th gen)</span> </div> </a> <ul id="toc-Core_i_(5th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Broadwell-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7.1</span> <span>Broadwell-U</span> </div> </a> <ul id="toc-Broadwell-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Broadwell-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.7.2</span> <span>Broadwell-H</span> </div> </a> <ul id="toc-Broadwell-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_M_(5th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_M_(5th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.8</span> <span>Core M (5th gen)</span> </div> </a> <ul id="toc-Core_M_(5th_gen)-sublist" class="vector-toc-list"> <li id="toc-Broadwell-Y" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-Y"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.8.1</span> <span>Broadwell-Y</span> </div> </a> <ul id="toc-Broadwell-Y-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(6th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(6th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.9</span> <span>Core i (6th gen)</span> </div> </a> <ul id="toc-Core_i_(6th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Skylake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.9.1</span> <span>Skylake-U</span> </div> </a> <ul id="toc-Skylake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.9.2</span> <span>Skylake-H</span> </div> </a> <ul id="toc-Skylake-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_M_(6th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_M_(6th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.10</span> <span>Core M (6th gen)</span> </div> </a> <ul id="toc-Core_M_(6th_gen)-sublist" class="vector-toc-list"> <li id="toc-Skylake-Y" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-Y"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.10.1</span> <span>Skylake-Y</span> </div> </a> <ul id="toc-Skylake-Y-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(7th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(7th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11</span> <span>Core i (7th gen)</span> </div> </a> <ul id="toc-Core_i_(7th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11.1</span> <span>Kaby Lake-U</span> </div> </a> <ul id="toc-Kaby_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11.2</span> <span>Kaby Lake-H</span> </div> </a> <ul id="toc-Kaby_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-Y" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-Y"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.11.3</span> <span>Kaby Lake-Y</span> </div> </a> <ul id="toc-Kaby_Lake-Y-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_M_(7th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_M_(7th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.12</span> <span>Core M (7th gen)</span> </div> </a> <ul id="toc-Core_M_(7th_gen)-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake-Y_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-Y_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.12.1</span> <span>Kaby Lake-Y</span> </div> </a> <ul id="toc-Kaby_Lake-Y_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(8th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(8th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13</span> <span>Core i (8th gen)</span> </div> </a> <ul id="toc-Core_i_(8th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.1</span> <span>Coffee Lake-U</span> </div> </a> <ul id="toc-Coffee_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.2</span> <span>Coffee Lake-H</span> </div> </a> <ul id="toc-Coffee_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake-B" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-B"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.3</span> <span>Coffee Lake-B</span> </div> </a> <ul id="toc-Coffee_Lake-B-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake_Refresh" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.4</span> <span>Kaby Lake Refresh</span> </div> </a> <ul id="toc-Kaby_Lake_Refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-G" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-G"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.5</span> <span>Kaby Lake-G</span> </div> </a> <ul id="toc-Kaby_Lake-G-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Amber_Lake-Y" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Amber_Lake-Y"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.6</span> <span>Amber Lake-Y</span> </div> </a> <ul id="toc-Amber_Lake-Y-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Whiskey_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Whiskey_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.7</span> <span>Whiskey Lake-U</span> </div> </a> <ul id="toc-Whiskey_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cannon_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Cannon_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.13.8</span> <span>Cannon Lake-U</span> </div> </a> <ul id="toc-Cannon_Lake-U-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_M_(8th_gen)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_M_(8th_gen)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.14</span> <span>Core M (8th gen)</span> </div> </a> <ul id="toc-Core_M_(8th_gen)-sublist" class="vector-toc-list"> <li id="toc-Amber_Lake-Y_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Amber_Lake-Y_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.14.1</span> <span>Amber Lake-Y</span> </div> </a> <ul id="toc-Amber_Lake-Y_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(9th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(9th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.15</span> <span>Core i (9th gen)</span> </div> </a> <ul id="toc-Core_i_(9th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-H_(refresh)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-H_(refresh)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.15.1</span> <span>Coffee Lake-H (refresh)</span> </div> </a> <ul id="toc-Coffee_Lake-H_(refresh)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(10th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(10th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16</span> <span>Core i (10th gen)</span> </div> </a> <ul id="toc-Core_i_(10th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Comet_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comet_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16.1</span> <span>Comet Lake-U</span> </div> </a> <ul id="toc-Comet_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comet_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comet_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16.2</span> <span>Comet Lake-H</span> </div> </a> <ul id="toc-Comet_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ice_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ice_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16.3</span> <span>Ice Lake-U</span> </div> </a> <ul id="toc-Ice_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ice_Lake-Y" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ice_Lake-Y"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16.4</span> <span>Ice Lake-Y</span> </div> </a> <ul id="toc-Ice_Lake-Y-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Amber_Lake-Y_(10xxx)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Amber_Lake-Y_(10xxx)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.16.5</span> <span>Amber Lake-Y (10xxx)</span> </div> </a> <ul id="toc-Amber_Lake-Y_(10xxx)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(11th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(11th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.17</span> <span>Core i (11th gen)</span> </div> </a> <ul id="toc-Core_i_(11th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Tiger_Lake-UP3" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-UP3"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.17.1</span> <span>Tiger Lake-UP3</span> </div> </a> <ul id="toc-Tiger_Lake-UP3-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tiger_Lake-UP4" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-UP4"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.17.2</span> <span>Tiger Lake-UP4</span> </div> </a> <ul id="toc-Tiger_Lake-UP4-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tiger_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.17.3</span> <span>Tiger Lake-H</span> </div> </a> <ul id="toc-Tiger_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tiger_Lake-H35" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-H35"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.17.4</span> <span>Tiger Lake-H35</span> </div> </a> <ul id="toc-Tiger_Lake-H35-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(12th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(12th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18</span> <span>Core i (12th gen)</span> </div> </a> <ul id="toc-Core_i_(12th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Alder_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18.1</span> <span>Alder Lake-U</span> </div> </a> <ul id="toc-Alder_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-P" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-P"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18.2</span> <span>Alder Lake-P</span> </div> </a> <ul id="toc-Alder_Lake-P-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18.3</span> <span>Alder Lake-H</span> </div> </a> <ul id="toc-Alder_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-HX" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-HX"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18.4</span> <span>Alder Lake-HX</span> </div> </a> <ul id="toc-Alder_Lake-HX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-N" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-N"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.18.5</span> <span>Alder Lake-N</span> </div> </a> <ul id="toc-Alder_Lake-N-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(13th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(13th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19</span> <span>Core i (13th gen)</span> </div> </a> <ul id="toc-Core_i_(13th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19.1</span> <span>Raptor Lake-U</span> </div> </a> <ul id="toc-Raptor_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-P" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-P"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19.2</span> <span>Raptor Lake-P</span> </div> </a> <ul id="toc-Raptor_Lake-P-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19.3</span> <span>Raptor Lake-H</span> </div> </a> <ul id="toc-Raptor_Lake-H-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-PX" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-PX"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19.4</span> <span>Raptor Lake-PX</span> </div> </a> <ul id="toc-Raptor_Lake-PX-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-HX" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-HX"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.19.5</span> <span>Raptor Lake-HX</span> </div> </a> <ul id="toc-Raptor_Lake-HX-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(14th_gen)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(14th_gen)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.20</span> <span>Core i (14th gen)</span> </div> </a> <ul id="toc-Core_i_(14th_gen)_2-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-HX_Refresh" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-HX_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.20.1</span> <span>Raptor Lake-HX Refresh</span> </div> </a> <ul id="toc-Raptor_Lake-HX_Refresh-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_/_Core_Ultra_3/5/7/9_(Series_1)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_/_Core_Ultra_3/5/7/9_(Series_1)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.21</span> <span>Core / Core Ultra 3/5/7/9 (Series 1)</span> </div> </a> <ul id="toc-Core_/_Core_Ultra_3/5/7/9_(Series_1)-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-U_Refresh" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-U_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.21.1</span> <span>Raptor Lake-U Refresh</span> </div> </a> <ul id="toc-Raptor_Lake-U_Refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Meteor_Lake-U" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Meteor_Lake-U"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.21.2</span> <span>Meteor Lake-U</span> </div> </a> <ul id="toc-Meteor_Lake-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Meteor_Lake-H" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Meteor_Lake-H"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.21.3</span> <span>Meteor Lake-H</span> </div> </a> <ul id="toc-Meteor_Lake-H-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_Ultra_5/7/9_(Series_2)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_Ultra_5/7/9_(Series_2)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.22</span> <span>Core Ultra 5/7/9 (Series 2)</span> </div> </a> <ul id="toc-Core_Ultra_5/7/9_(Series_2)-sublist" class="vector-toc-list"> <li id="toc-Lunar_Lake" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Lunar_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.22.1</span> <span>Lunar Lake</span> </div> </a> <ul id="toc-Lunar_Lake-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Embedded_processors" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Embedded_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Embedded processors</span> </div> </a> <button aria-controls="toc-Embedded_processors-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Embedded processors subsection</span> </button> <ul id="toc-Embedded_processors-sublist" class="vector-toc-list"> <li id="toc-Core_i_(1st_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(1st_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Core i (1st gen)</span> </div> </a> <ul id="toc-Core_i_(1st_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Arrandale_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Arrandale_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.1</span> <span>Arrandale</span> </div> </a> <ul id="toc-Arrandale_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(2nd_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(2nd_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Core i (2nd gen)</span> </div> </a> <ul id="toc-Core_i_(2nd_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Sandy_Bridge-DT_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sandy_Bridge-DT_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.1</span> <span>Sandy Bridge-DT</span> </div> </a> <ul id="toc-Sandy_Bridge-DT_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sandy_Bridge-M_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sandy_Bridge-M_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.2</span> <span>Sandy Bridge-M</span> </div> </a> <ul id="toc-Sandy_Bridge-M_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gladden" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Gladden"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.3</span> <span>Gladden</span> </div> </a> <ul id="toc-Gladden-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(3rd_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(3rd_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Core i (3rd gen)</span> </div> </a> <ul id="toc-Core_i_(3rd_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Ivy_Bridge-DT_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ivy_Bridge-DT_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.1</span> <span>Ivy Bridge-DT</span> </div> </a> <ul id="toc-Ivy_Bridge-DT_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ivy_Bridge-M" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Ivy_Bridge-M"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.2</span> <span>Ivy Bridge-M</span> </div> </a> <ul id="toc-Ivy_Bridge-M-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gladden_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Gladden_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.3</span> <span>Gladden</span> </div> </a> <ul id="toc-Gladden_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(4th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(4th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Core i (4th gen)</span> </div> </a> <ul id="toc-Core_i_(4th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Haswell-DT_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-DT_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.1</span> <span>Haswell-DT</span> </div> </a> <ul id="toc-Haswell-DT_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Haswell-H_3" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Haswell-H_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.2</span> <span>Haswell-H</span> </div> </a> <ul id="toc-Haswell-H_3-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(5th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(5th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Core i (5th gen)</span> </div> </a> <ul id="toc-Core_i_(5th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Broadwell-H_3" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Broadwell-H_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5.1</span> <span>Broadwell-H</span> </div> </a> <ul id="toc-Broadwell-H_3-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(6th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(6th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>Core i (6th gen)</span> </div> </a> <ul id="toc-Core_i_(6th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Skylake-S_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-S_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6.1</span> <span>Skylake-S</span> </div> </a> <ul id="toc-Skylake-S_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake-H_3" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Skylake-H_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6.2</span> <span>Skylake-H</span> </div> </a> <ul id="toc-Skylake-H_3-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(7th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(7th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7</span> <span>Core i (7th gen)</span> </div> </a> <ul id="toc-Core_i_(7th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake-S_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-S_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7.1</span> <span>Kaby Lake-S</span> </div> </a> <ul id="toc-Kaby_Lake-S_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kaby_Lake-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7.2</span> <span>Kaby Lake-H</span> </div> </a> <ul id="toc-Kaby_Lake-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(8th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(8th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.8</span> <span>Core i (8th gen)</span> </div> </a> <ul id="toc-Core_i_(8th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Whiskey_Lake-U_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Whiskey_Lake-U_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.8.1</span> <span>Whiskey Lake-U</span> </div> </a> <ul id="toc-Whiskey_Lake-U_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(9th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(9th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.9</span> <span>Core i (9th gen)</span> </div> </a> <ul id="toc-Core_i_(9th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Coffee_Lake-R_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-R_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.9.1</span> <span>Coffee Lake-R</span> </div> </a> <ul id="toc-Coffee_Lake-R_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake-H_(refresh)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Coffee_Lake-H_(refresh)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.9.2</span> <span>Coffee Lake-H (refresh)</span> </div> </a> <ul id="toc-Coffee_Lake-H_(refresh)_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(10th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(10th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10</span> <span>Core i (10th gen)</span> </div> </a> <ul id="toc-Core_i_(10th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Comet_Lake-S_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comet_Lake-S_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10.1</span> <span>Comet Lake-S</span> </div> </a> <ul id="toc-Comet_Lake-S_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(11th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(11th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.11</span> <span>Core i (11th gen)</span> </div> </a> <ul id="toc-Core_i_(11th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Tiger_Lake-UP3_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-UP3_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.11.1</span> <span>Tiger Lake-UP3</span> </div> </a> <ul id="toc-Tiger_Lake-UP3_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tiger_Lake-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Tiger_Lake-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.11.2</span> <span>Tiger Lake-H</span> </div> </a> <ul id="toc-Tiger_Lake-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(12th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(12th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12</span> <span>Core i (12th gen)</span> </div> </a> <ul id="toc-Core_i_(12th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Alder_Lake-S_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-S_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12.1</span> <span>Alder Lake-S</span> </div> </a> <ul id="toc-Alder_Lake-S_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-U_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-U_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12.2</span> <span>Alder Lake-U</span> </div> </a> <ul id="toc-Alder_Lake-U_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-P_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-P_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12.3</span> <span>Alder Lake-P</span> </div> </a> <ul id="toc-Alder_Lake-P_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-PS" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-PS"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12.4</span> <span>Alder Lake-PS</span> </div> </a> <ul id="toc-Alder_Lake-PS-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Alder_Lake-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Alder_Lake-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.12.5</span> <span>Alder Lake-H</span> </div> </a> <ul id="toc-Alder_Lake-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i_(13th_gen)_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i_(13th_gen)_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.13</span> <span>Core i (13th gen)</span> </div> </a> <ul id="toc-Core_i_(13th_gen)_3-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake-S_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-S_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.13.1</span> <span>Raptor Lake-S</span> </div> </a> <ul id="toc-Raptor_Lake-S_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-U_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-U_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.13.2</span> <span>Raptor Lake-U</span> </div> </a> <ul id="toc-Raptor_Lake-U_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-P_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-P_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.13.3</span> <span>Raptor Lake-P</span> </div> </a> <ul id="toc-Raptor_Lake-P_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Raptor_Lake-H_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Raptor_Lake-H_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.13.4</span> <span>Raptor Lake-H</span> </div> </a> <ul id="toc-Raptor_Lake-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_/_Core_Ultra_3/5/7/9_(Series_1)_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_/_Core_Ultra_3/5/7/9_(Series_1)_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.14</span> <span>Core / Core Ultra 3/5/7/9 (Series 1)</span> </div> </a> <ul id="toc-Core_/_Core_Ultra_3/5/7/9_(Series_1)_2-sublist" class="vector-toc-list"> <li id="toc-Meteor_Lake-PS" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Meteor_Lake-PS"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.14.1</span> <span>Meteor Lake-PS</span> </div> </a> <ul id="toc-Meteor_Lake-PS-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> 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href="/w/index.php?title=List_of_Intel_Core_i5_microprocessors&redirect=no" class="mw-redirect" title="List of Intel Core i5 microprocessors">List of Intel Core i5 microprocessors</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">For a shorter list of the latest processors by Intel, see <a href="/wiki/List_of_Intel_processors#Latest" title="List of Intel processors">List of Intel processors § Latest</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Split plainlinks metadata ambox ambox-move" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a7/Split-arrows.svg/50px-Split-arrows.svg.png" decoding="async" width="50" height="17" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a7/Split-arrows.svg/75px-Split-arrows.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a7/Split-arrows.svg/100px-Split-arrows.svg.png 2x" data-file-width="60" data-file-height="20" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">It has been suggested that this article be <b><a href="/wiki/Wikipedia:Splitting" title="Wikipedia:Splitting">split</a></b> into articles titled <i><a href="/w/index.php?title=List_of_Intel_Core_i3/i5/i7/i9_processors&action=edit&redlink=1" class="new" title="List of Intel Core i3/i5/i7/i9 processors (page does not exist)">List of Intel Core i3/i5/i7/i9 processors</a></i> and <i><a href="/w/index.php?title=List_of_Intel_Core_and_Core_Ultra_3/5/7/9_processors&action=edit&redlink=1" class="new" title="List of Intel Core and Core Ultra 3/5/7/9 processors (page does not exist)">List of Intel Core and Core Ultra 3/5/7/9 processors</a></i>. (<a href="/wiki/Talk:List_of_Intel_Core_processors#Splitting_proposal" title="Talk:List of Intel Core processors">discuss</a>) <span class="date-container"><i>(<span class="date">May 2024</span>)</i></span></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Core_2023_logo.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/220px-Intel_Core_2023_logo.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/330px-Intel_Core_2023_logo.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/440px-Intel_Core_2023_logo.png 2x" data-file-width="443" data-file-height="443" /></a><figcaption>The latest badge promoting the Intel Core branding</figcaption></figure> <p> The following is a list of <b>Intel Core</b> <a href="/wiki/List_of_Intel_processors" title="List of Intel processors">processors</a>. This includes <a href="/wiki/Intel" title="Intel">Intel</a>'s original Core (Solo/Duo) mobile series based on the Enhanced Pentium M <a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">microarchitecture</a>, as well as its Core 2- (Solo/Duo/Quad/Extreme), Core i3-, Core i5-, Core i7-, Core i9-, Core M- (m3/m5/m7), Core 3-, Core 5-, and Core 7-branded processors. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Desktop_processors">Desktop processors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=1" title="Edit section: Desktop processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1212047051">.mw-parser-output .release-timeline{padding:.75em 1em;font-size:85%;line-height:.9;border-collapse:separate;border-spacing:0 1px;background-color:transparent}.mw-parser-output .release-timeline>caption{padding:.4em .4em .2em;font-size:112.5%}.mw-parser-output .release-timeline .rt-subtitle{padding-top:.3em;font-size:90%;font-weight:normal}.mw-parser-output .release-timeline td,.mw-parser-output .release-timeline th{border:none;padding:.4em;background:none;font:inherit;color:inherit}.mw-parser-output .release-timeline td{text-align:left}.mw-parser-output .release-timeline th{text-align:right}.mw-parser-output .release-timeline .rt-first{padding:.4em .4em .2em}.mw-parser-output .release-timeline .rt-next,.mw-parser-output .release-timeline .rt-last{padding:.2em .4em}@media(min-width:720px){.mw-parser-output .release-timeline{float:right;clear:right;margin:.5em 0 .5em 1.4em}.mw-parser-output .rt-left{float:left;clear:left;margin:.5em 1.4em .5em 0}.mw-parser-output .release-timeline caption{white-space:nowrap}}</style><table class="release-timeline wikitable"><caption>Release timeline<div class="rt-subtitle"><b>Desktop processors</b></div></caption><tbody><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2008</th><td><a href="#Core_i_(1st_gen)">Nehalem microarchitecture (1st generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #228B22">2009</th></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2010</th><td><a href="#Core_i_(1st_gen)">Westmere microarchitecture (1st generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2011</th><td><a href="#Core_i_(2nd_gen)">Sandy Bridge microarchitecture (2nd generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2012</th><td><a href="#Core_i_(3rd_gen)">Ivy Bridge microarchitecture (3rd generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2013</th><td><a href="#Core_i_(4th_gen)">Haswell microarchitecture (4th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #228B22">2014</th></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid #0BDA51">2015</th><td class="rt-first"><a href="#Core_i_(5th_gen)">Broadwell microarchitecture (5th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(6th_gen)">Skylake microarchitecture (6th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #228B22">2016</th></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid #0BDA51">2017</th><td class="rt-first"><a href="#Core_i_(7th_gen)">Kaby Lake microarchitecture (7th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(8th_gen)">Coffee Lake microarchitecture (8th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #228B22">2018</th></tr><tr><th scope="row" style="border-right:1.4em solid #228B22">2019</th></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2020</th><td><a href="#Core_i_(10th_gen)">Comet Lake microarchitecture (10th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2021</th><td><a href="#Core_i_(11th_gen)">Rocket Lake (11th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid #0BDA51">2022</th><td><a href="#Core_i_(12th_gen)">Alder Lake (12th generation)</a></td></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid #0BDA51">2023</th><td class="rt-first"><a href="#Core_i_(13th_gen)">Raptor Lake (13th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(14th_gen)">Raptor Lake (14th generation)</a></td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_2">Core 2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=2" title="Edit section: Core 2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Citation_style plainlinks metadata ambox ambox-style ambox-citation_style" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/40px-Edit-clear.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/60px-Edit-clear.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/f/f2/Edit-clear.svg/80px-Edit-clear.svg.png 2x" data-file-width="48" data-file-height="48" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>has an unclear <a href="/wiki/Wikipedia:Citing_sources#Citation_style" title="Wikipedia:Citing sources">citation style</a></b>. The reason given is: <b>Some footnotes, some raw references (as below).</b><span class="hide-when-compact"> The references used may be made clearer with a different or consistent style of <a href="/wiki/Wikipedia:Citing_sources" title="Wikipedia:Citing sources">citation</a> and <a href="/wiki/Help:Footnotes" title="Help:Footnotes">footnoting</a>.</span> <span class="date-container"><i>(<span class="date">October 2018</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:2_Duo_T7500_Processor.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6a/2_Duo_T7500_Processor.jpg/220px-2_Duo_T7500_Processor.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6a/2_Duo_T7500_Processor.jpg/330px-2_Duo_T7500_Processor.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6a/2_Duo_T7500_Processor.jpg/440px-2_Duo_T7500_Processor.jpg 2x" data-file-width="4032" data-file-height="3024" /></a><figcaption>Front side of an Intel Core 2 Duo T7500 Processor</figcaption></figure> <div class="mw-heading mw-heading4"><h4 id=""Allendale"_(65_nm,_800_MT/s)"><span id=".22Allendale.22_.2865_nm.2C_800_MT.2Fs.29"></span>"Allendale" (65 nm, 800 MT/s) <span class="anchor" id=""Allendale"_(65_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=3" title="Edit section: "Allendale" (65 nm, 800 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For versions of the Allendale core with half the L2 cache disabled under the <a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> brand, see <a href="/wiki/List_of_Intel_Pentium_Dual-Core_microprocessors#"Allendale"_(65_nm)" class="mw-redirect" title="List of Intel Pentium Dual-Core microprocessors">List of Intel Pentium Dual-Core microprocessors § "Allendale" (65 nm)</a>.</div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2)</i><sup class="plainlinks nourlexpansion citation" id="ref_NoTXT"><a href="#endnote_NoTXT">a</a></sup></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 111 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">L2</a><sup class="plainlinks nourlexpansion citation" id="ref_MoreAgressiveHaltStateL2"><a href="#endnote_MoreAgressiveHaltStateL2">b</a></sup>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">M0</a><sup class="plainlinks nourlexpansion citation" id="ref_MoreAgressiveHaltStateM0"><a href="#endnote_MoreAgressiveHaltStateM0">c</a></sup>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">G0</a><sup class="plainlinks nourlexpansion citation" id="ref_MoreAgressiveHaltStateG0"><a href="#endnote_MoreAgressiveHaltStateG0">d</a></sup></li></ul> <p><br /> </p> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E4300"></span><span class="anchor" id="ark28024"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/28024.html">Core 2 Duo E4300</a> </td> <td><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"> <ul><li>SL9TB (L2)</li> <li>SLA99 (M0)</li> <li>SLA5G</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>9× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">January 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PG0332M</li> <li>BX80557E4300</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E4400"></span><span class="anchor" id="ark29753"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29753.html">Core 2 Duo E4400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3F (L2)</li> <li>SLA98 (M0)</li> <li>SLA5F</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PG0412M</li> <li>BX80557E4400</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E4500"></span><span class="anchor" id="ark30781"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30781.html">Core 2 Duo E4500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA95 (M0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>11× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PG0492M</li> <li>BX80557E4500</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E4600"></span><span class="anchor" id="ark32242"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/32242.html">Core 2 Duo E4600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA94 (M0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>12× </td> <td>1.162–1.312 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">October 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PG0562M</li> <li>BX80557E4600</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E4700"></span><span class="anchor" id="ark34441"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/34441.html">Core 2 Duo E4700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLALT (G0)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>13× </td> <td>1.162–1.312 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PG0642M</li> <li>BX80557E4700</li></ul> </div> </td> <td>$133 </td></tr> </tbody></table> <p><style data-mw-deduplicate="TemplateStyles:r1041539562">.mw-parser-output .citation{word-wrap:break-word}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}</style><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateM0"><b><a href="#ref_MoreAgressiveHaltStateM0">^c</a></b></span> Note: The <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">M0 and G0 Steppings</a> have better optimizations to lower idle power consumption from 12W to 8W. </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateG0"><b><a href="#ref_MoreAgressiveHaltStateG0">^d</a></b></span> Note: The E4700 uses <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">G0 Stepping</a> which makes it a Conroe CPU. </p> <div class="mw-heading mw-heading4"><h4 id=""Conroe"_(65_nm,_1066_MT/s)"><span id=".22Conroe.22_.2865_nm.2C_1066_MT.2Fs.29"></span>"Conroe" (65 nm, 1066 MT/s) <span class="anchor" id=""Conroe"_(65_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=4" title="Edit section: "Conroe" (65 nm, 1066 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2)</i><sup class="plainlinks nourlexpansion citation" id="ref_NoTXT"><a href="#endnote_NoTXT">a</a></sup></li> <li>All models support: <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B2</a>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">G0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6300"></span><span class="anchor" id="ark27248"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27248.html">Core 2 Duo E6300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SA (B2)</li> <li>SL9TA (L2)</li> <li>SLA2L (?)</li> <li>SLA5E (?)</li></ul> </div> </td> <td>2 </td> <td>1.87 GHz </td> <td>2 MB </td> <td>1066 MT/s </td> <td>7× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0362M</li> <li>BX80557E6300</li> <li>BX80557E6300T2</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6320"></span><span class="anchor" id="ark29754"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29754.html">Core 2 Duo E6320</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4U (B2)</li></ul> </div> </td> <td>2 </td> <td>1.87 GHz </td> <td>4 MB </td> <td>1066 MT/s </td> <td>7× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0364M</li> <li>BX80557E6320</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6400"></span><span class="anchor" id="ark27249"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27249.html">Core 2 Duo E6400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9S9 (B2)</li> <li>SLA5D (?)</li> <li>SL9T9 (L2)</li> <li>SLA97 (M0)</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>2 MB </td> <td>1066 MT/s </td> <td>8× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0462M</li> <li>BX80557E6400</li></ul> </div> </td> <td>$224 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6420"></span><span class="anchor" id="ark29755"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29755.html">Core 2 Duo E6420</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4T (B2)</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>4 MB </td> <td>1066 MT/s </td> <td>8× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0464M</li> <li>BX80557E6420</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6600"></span><span class="anchor" id="ark27250"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27250.html">Core 2 Duo E6600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9S8 (B2)</li> <li>SL9ZL (B2)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>4 MB </td> <td>1066 MT/s </td> <td>9× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0564M</li> <li>BX80557E6600</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6700"></span><span class="anchor" id="ark27251"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27251.html">Core 2 Duo E6700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9S7 (B2)</li> <li>SL9ZF (B2)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>4 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0674M</li> <li>BX80557E6700</li></ul> </div> </td> <td>$530 </td></tr> </tbody></table> <p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoTXT"><b><a href="#ref_NoTXT">^a</a></b></span> Note: of the E6000 series processors, only models E6550, E6750, and E6850 support Intel's <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT).<sup id="cite_ref-E6xxxCompare_1-0" class="reference"><a href="#cite_note-E6xxxCompare-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateL2"><b><a href="#ref_MoreAgressiveHaltStateL2">^b</a></b></span> Note: The <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">L2 Stepping</a>, and models with sSpec SL9ZL, SL9ZF, SLA4U, SLA4T, have better optimizations to lower idle power consumption from 22W to 12W.<sup id="cite_ref-moreagressivehaltstate_2-0" class="reference"><a href="#cite_note-moreagressivehaltstate-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateM0"><b><a href="#ref_MoreAgressiveHaltStateM0">^c</a></b></span> Note: The <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">M0 and G0 Steppings</a> have better optimizations to lower idle power consumption from 12W to 8W. </p> <div class="mw-heading mw-heading4"><h4 id=""Conroe"_(65_nm,_1333_MT/s)"><span id=".22Conroe.22_.2865_nm.2C_1333_MT.2Fs.29"></span>"Conroe" (65 nm, 1333 MT/s)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=5" title="Edit section: "Conroe" (65 nm, 1333 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2)</i><sup class="plainlinks nourlexpansion citation" id="ref_NoTXT"><a href="#endnote_NoTXT">a</a></sup></li> <li>All models support: <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></li> <li>All E6x50 models support: <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup></li> <li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a>: 291 million</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B2</a>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">G0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6540"></span><span class="anchor" id="ark30782"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30782.html">Core 2 Duo E6540</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAA5 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.33 GHz </td> <td>4 MB </td> <td>1333 MT/s </td> <td>7× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PJ0534M</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6550"></span><span class="anchor" id="ark30783"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30783.html">Core 2 Duo E6550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA9X (G0)</li> <li>SLAAT (?)</li></ul> </div> </td> <td>2 </td> <td>2.33 GHz </td> <td>4 MB </td> <td>1333 MT/s </td> <td>7× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PJ0534MG</li> <li>BX80557E6550</li> <li>BX80557E6550R</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6750"></span><span class="anchor" id="ark30784"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30784.html">Core 2 Duo E6750</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA9V (G0)</li> <li>SLAAR (?)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>4 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PJ0674MG</li> <li>BX80557E6750</li> <li>BX80557E6750R</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6850"></span><span class="anchor" id="ark30785"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30785.html">Core 2 Duo E6850</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA9U (G0)</li></ul> </div> </td> <td>2 </td> <td>3 GHz </td> <td>4 MB </td> <td>1333 MT/s </td> <td>9× </td> <td>0.85–1.5 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PJ0804MG</li> <li>BX80557E6850</li></ul> </div> </td> <td>$266 </td></tr> </tbody></table> <p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoTXT"><b><a href="#ref_NoTXT">^a</a></b></span> Note: of the E6000 series processors, only models E6550, E6750, and E6850 support Intel's <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT).<sup id="cite_ref-E6xxxCompare_1-1" class="reference"><a href="#cite_note-E6xxxCompare-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateL2"><b><a href="#ref_MoreAgressiveHaltStateL2">^b</a></b></span> Note: The <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">L2 Stepping</a>, and models with sSpec SL9ZL, SL9ZF, SLA4U, SLA4T, have better optimizations to lower idle power consumption from 22W to 12W.<sup id="cite_ref-moreagressivehaltstate_2-1" class="reference"><a href="#cite_note-moreagressivehaltstate-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_MoreAgressiveHaltStateM0"><b><a href="#ref_MoreAgressiveHaltStateM0">^c</a></b></span> Note: The <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">M0 and G0 Steppings</a> have better optimizations to lower idle power consumption from 12W to 8W. </p> <div class="mw-heading mw-heading4"><h4 id=""Conroe-CL"_(65_nm,_1066_MT/s)"><span id=".22Conroe-CL.22_.2865_nm.2C_1066_MT.2Fs.29"></span>"Conroe-CL" (65 nm, 1066 MT/s)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=6" title="Edit section: "Conroe-CL" (65 nm, 1066 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 111 mm<sup>2</sup> (Conroe)</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: ?</li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6305"></span><span class="anchor" id="ark35276"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35276.html">Core 2 Duo E6305</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAGF</li></ul> </div> </td> <td>2 </td> <td>1.87 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>7× </td> <td> </td> <td>65 W </td> <td><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557KH036F</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E6405"></span><span class="anchor" id="ark35056"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35056.html">Core 2 Duo E6405</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAGG</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>2 MB </td> <td>1066 MT/s </td> <td>8× </td> <td> </td> <td>65 W </td> <td><a href="/wiki/LGA_771" title="LGA 771">LGA 771</a> </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557KH046F</li></ul> </div> </td> <td> </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Conroe_XE"_(65_nm)"><span id=".22Conroe_XE.22_.2865_nm.29"></span>"Conroe XE" (65 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=7" title="Edit section: "Conroe XE" (65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><sup id="cite_ref-conroespeculation_3-0" class="reference"><a href="#cite_note-conroespeculation-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-x6900_4-0" class="reference"><a href="#cite_note-x6900-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p><i>These models feature an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a></i> </p> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B1, B2</a></li> <li>The X6900 was never publicly released.</li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_X6800"></span><span class="anchor" id="ark27258"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27258.html">Core 2 Extreme X6800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9S5 (B2)</li> <li>QPHV (B1)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>11× </td> <td>0.85–1.5 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">75 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">July 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0677M</li> <li>BX80557X6800</li></ul> </div> </td> <td>$999 </td></tr> <tr> <td><span class="cite-bracket" id="cite_ref-6"></span>Core 2 Extreme X6900<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>QTOM (B2)</li> <li>SL9S4 (B2)</li></ul> </div> </td> <td>2 </td> <td>3.2 GHz </td> <td>4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>12× </td> <td>0.85–1.5 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">75 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">N/A </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80557PH0884M</li></ul> </div> </td> <td>N/A </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Kentsfield"_(65_nm)"><span id=".22Kentsfield.22_.2865_nm.29"></span>"Kentsfield" (65 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=8" title="Edit section: "Kentsfield" (65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><sup id="cite_ref-q6600_7-0" class="reference"><a href="#cite_note-q6600-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-q6600rel_8-0" class="reference"><a href="#cite_note-q6600rel-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 ×143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B3, G0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="cite-bracket" id="Core_2_Quad_Q6400<sup_id="></span>Core 2 Quad Q6400<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9UN (B3)</li></ul> </div> </td> <td>4 </td> <td>2.13 GHz </td> <td>2 × 4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>8× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">105 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562PH0468M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q6600"></span><span class="anchor" id="ark29765"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29765.html">Core 2 Quad Q6600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9UM (B3)</li> <li>SLACR (G0)</li></ul> </div> </td> <td>4 </td> <td>2.4 GHz </td> <td>2 × 4 MB </td> <td>1066 MT/s </td> <td>9× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;"> <ul><li>105 W</li> <li>95 W</li></ul> </div> </td> <td>LGA 775 </td> <td style="text-align:right;">January 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562PH0568M</li> <li>BX80562Q6600</li> <li>BXC80562Q6600</li></ul> </div> </td> <td>$851 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q6700"></span><span class="anchor" id="ark30790"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30790.html">Core 2 Quad Q6700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLACQ (G0)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 4 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562PH0678M</li> <li>BX80562Q6700</li> <li>BXC80562Q6700</li></ul> </div> </td> <td>$530 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Kentsfield_XE"_(65_nm)"><span id=".22Kentsfield_XE.22_.2865_nm.29"></span>"Kentsfield XE" (65 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=9" title="Edit section: "Kentsfield XE" (65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><sup id="cite_ref-qx6700_10-0" class="reference"><a href="#cite_note-qx6700-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p><i>These models feature an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a></i> </p> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 ×143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B3, G0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX6700"></span><span class="anchor" id="ark28028"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/28028.html">Core 2 Extreme QX6700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9UL (B3)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>10× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">130 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">November 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562PH0678M</li></ul> </div> </td> <td>$999 </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX6800"></span><span class="anchor" id="ark30720"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30720.html">Core 2 Extreme QX6800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9UK (B3)</li> <li>SLACP (G0)</li></ul> </div> </td> <td>4 </td> <td>2.93 GHz </td> <td>2 × 4 MB </td> <td>1066 MT/s </td> <td>11× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">130 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562PH0778M</li> <li>HH80562XH0778M</li></ul> </div> </td> <td>$1199 </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX6850"></span><span class="anchor" id="ark30789"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30789.html">Core 2 Extreme QX6850</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAFN (G0)</li></ul> </div> </td> <td>4 </td> <td>3 GHz </td> <td>2 × 4 MB </td> <td>1333 MT/s </td> <td>9× </td> <td>0.8500–1.500 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">130 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>HH80562XJ0808M</li></ul> </div> </td> <td>$999 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Wolfdale-3M"_(45_nm,_1066_MT/s)"><span id=".22Wolfdale-3M.22_.2845_nm.2C_1066_MT.2Fs.29"></span>"Wolfdale-3M" (45 nm, 1066 MT/s)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=10" title="Edit section: "Wolfdale-3M" (45 nm, 1066 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 82 mm<sup>2</sup></li> <li>Transistor Count: 230 million</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0, R0</a></li> <li>Models with a part number ending in "ML" instead of "M" support <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E7200"></span><span class="anchor" id="ark35348"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35348.html">Core 2 Duo E7200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPC (M0)</li> <li>SLAVN (M0)</li> <li>SLB9W (?)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>3 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>9.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80571PH0613M</li> <li>BX80571E7200</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E7300"></span><span class="anchor" id="ark36463"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36463.html">Core 2 Duo E7300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPB (M0)</li> <li>SLB9X (R0)</li> <li>SLGA9 (R0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80571PH0673M</li> <li>AT80571PH0673M</li> <li>BX80571E7300</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E7400"></span><span class="anchor" id="ark36500"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36500.html">Core 2 Duo E7400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB9Y (R0)</li> <li>SLGQ8 (R0)</li> <li>SLGW3 (R0, with VT)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>10.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">October 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80571PH0723M</li> <li>AT80571PH0723ML</li> <li>BX80571E7400</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E7500"></span><span class="anchor" id="ark36503"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36503.html">Core 2 Duo E7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB9Z (R0)</li> <li>SLGTE (R0, with VT)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>11× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80571PH0773M</li> <li>AT80571PH0773ML</li> <li>BX80571E7500</li></ul> </div> </td> <td>$133 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E7600"></span><span class="anchor" id="ark41495"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/41495.html">Core 2 Duo E7600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGTD (R0, with VT)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">May 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80571PH0833ML</li> <li>BX80571E7600</li></ul> </div> </td> <td>$133 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Wolfdale"_(45_nm,_1333_MT/s)"><span id=".22Wolfdale.22_.2845_nm.2C_1333_MT.2Fs.29"></span>"Wolfdale" (45 nm, 1333 MT/s)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=11" title="Edit section: "Wolfdale" (45 nm, 1333 MT/s)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models(except E8190) support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), iAMT2 (<a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a>), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><sup class="citation nobold" id="ref_NoVT-xa"><a href="#endnote_NoVT-xa">[a]</a></sup>, <a href="/wiki/Intel_VT-d" class="mw-redirect" title="Intel VT-d">Intel VT-d</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><sup class="citation nobold" id="ref_NoVT-db"><a href="#endnote_NoVT-db">[b]</a></sup>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li>Transistor Count: 410 million</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8190"></span><span class="anchor" id="ark34442"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/34442.html">Core 2 Duo E8190</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQR (C0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570PJ0676MN</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8200"></span><span class="anchor" id="ark33909"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33909.html">Core 2 Duo E8200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPP (C0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570PJ0676M</li> <li>BX80570E8200</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="cite-bracket" id="Core_2_Duo_E8290<sup_id="></span>Core 2 Duo E8290<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQQ (?)</li></ul> </div> </td> <td>2 </td> <td>2.83 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">? </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570PJ0736MN</li></ul> </div> </td> <td>? </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8300"></span><span class="anchor" id="ark35070"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35070.html">Core 2 Duo E8300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPJ (C0)</li> <li>SLAPN (C0)</li></ul> </div> </td> <td>2 </td> <td>2.83 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570AJ0736M</li> <li>EU80570PJ0736M</li></ul> </div> </td> <td>$163 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8400"></span><span class="anchor" id="ark33910"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33910.html">Core 2 Duo E8400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPL (C0)</li> <li>SLB9J (E0)</li></ul> </div> </td> <td>2 </td> <td>3 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>9× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570PJ0806M</li> <li>AT80570PJ0806M</li> <li>BX80570E8400</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8500"></span><span class="anchor" id="ark33911"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33911.html">Core 2 Duo E8500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPK (C0)</li> <li>SLB9K (E0)</li></ul> </div> </td> <td>2 </td> <td>3.17 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>9.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80570PJ0876M</li> <li>AT80570PJ0876M</li> <li>BX80570E8500</li></ul> </div> </td> <td>$266 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8600"></span><span class="anchor" id="ark35605"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35605.html">Core 2 Duo E8600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB9L (E0)</li></ul> </div> </td> <td>2 </td> <td>3.33 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>10× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80570PJ0876M</li> <li>BX80570E8600</li></ul> </div> </td> <td>$266 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8700"></span>Core 2 Duo E8700 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB9E (E0)</li></ul> </div> </td> <td>2 </td> <td>3.5 GHz </td> <td>6 MB </td> <td>1333 MT/s </td> <td>10.5× </td> <td>0.85–1.3625 V </td> <td>65 W </td> <td>LGA 775 </td> <td style="text-align:right;">January 2009* </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80570PJ1006M(OEM)</li></ul> </div> </td> <td>NA </td></tr> </tbody></table> <p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoVT-da"><a href="#ref_NoVT-da"><b><sup>a</sup></b></a></span> Note: The E8190 and E8290 do not support Intel VT-d. </p><p>Note 2: E8700 is a very rare example in Intel's history where a model was yanked from Intel ARK without a recall notice and after a SSPEC was assigned. Working examples were seen, believed to have been released to OEM,<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> but none was offered in retail PCs. </p><p>See also: Versions of the same Wolfdale core in an LGA 771 are available under the <a href="/wiki/List_of_Intel_Xeon_microprocessors#"Wolfdale-DP"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Xeon microprocessors">Dual-Core Xeon</a> brand. </p> <div class="mw-heading mw-heading4"><h4 id=""Yorkfield-6M"_(45_nm)"><span id=".22Yorkfield-6M.22_.2845_nm.29"></span>"Yorkfield-6M" (45 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=12" title="Edit section: "Yorkfield-6M" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><sup class="citation nobold" id="ref_NoVT-xa"><a href="#endnote_NoVT-xa">[a]</a></sup>, <a href="/wiki/Intel_VT-d" class="mw-redirect" title="Intel VT-d">Intel VT-d</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><sup class="citation nobold" id="ref_NoVT-db"><a href="#endnote_NoVT-db">[b]</a></sup>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT) <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><sup class="citation nobold" id="ref_NoTXTc"><a href="#endnote_NoTXTc">[c]</a></sup></i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 × 82 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0, M1, R0</a></li> <li>All Q8xxx models are Yorkfield-6M MCMs with only 2 × 2 MB L2 cache enabled.</li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q8200"></span><span class="anchor" id="ark36547"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36547.html">Core 2 Quad Q8200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5M (M1)</li> <li>SLG9S (R0)</li></ul> </div> </td> <td>4 </td> <td>2.33 GHz </td> <td>2 × 2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1333 MT/s </td> <td>7× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80580PJ0534MN</li> <li>AT80580PJ0534MN</li></ul> </div> </td> <td>$224 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q8200S"></span><span class="anchor" id="ark40816"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40816.html">Core 2 Quad Q8200S</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLG9T (R0)</li> <li>SLGSS (R0, with Intel VT-x)</li></ul> </div> </td> <td>4 </td> <td>2.33 GHz </td> <td>2 × 2 MB </td> <td>1333 MT/s </td> <td>7× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">65 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580AJ0534MN</li> <li>AT80580AJ0534ML</li></ul> </div> </td> <td>$245 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q8300"></span><span class="anchor" id="ark39107"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/39107.html">Core 2 Quad Q8300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5W (R0)</li> <li>SLGUR (R0, with Intel VT-x)</li></ul> </div> </td> <td>4 </td> <td>2.5 GHz </td> <td>2 × 2 MB </td> <td>1333 MT/s </td> <td>7.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">November 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580PJ0604MN</li> <li>AT80580PJ0604ML</li></ul> </div> </td> <td>$224 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q8400"></span><span class="anchor" id="ark38512"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/38512.html">Core 2 Quad Q8400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGT6 (R0, with Intel VT-x)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 2 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">April 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580PJ0674ML</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q8400S"></span><span class="anchor" id="ark42112"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42112.html">Core 2 Quad Q8400S</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGT7 (R0, with Intel VT-x)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 2 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">65 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">April 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580AJ0674ML</li></ul> </div> </td> <td>$245 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9300"></span><span class="anchor" id="ark33922"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33922.html">Core 2 Quad Q9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAMX (M0)</li> <li>SLAWE (M1)</li></ul> </div> </td> <td>4 </td> <td>2.5 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>7.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80580PJ0606M</li></ul> </div> </td> <td>$266 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9400"></span><span class="anchor" id="ark35365"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35365.html">Core 2 Quad Q9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB6B (R0)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580PJ0676M</li></ul> </div> </td> <td>$266 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9400S"></span><span class="anchor" id="ark40814"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40814.html">Core 2 Quad Q9400S</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLG9U (R0)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">65 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580AJ0676M</li></ul> </div> </td> <td>$320 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9500"></span><span class="anchor" id="ark37159"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37159.html">Core 2 Quad Q9500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGZ4 (R0)</li></ul> </div> </td> <td>4 </td> <td>2.83 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">January 2010 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580PJ0736ML</li></ul> </div> </td> <td>$183 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9505"></span><span class="anchor" id="ark42920"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42920.html">Core 2 Quad Q9505</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGYY (R0)</li></ul> </div> </td> <td>4 </td> <td>2.83 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">August 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580PJ0736MG</li></ul> </div> </td> <td>$213 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9505S"></span><span class="anchor" id="ark42921"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42921.html">Core 2 Quad Q9505S</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGYZ (R0)</li></ul> </div> </td> <td>4 </td> <td>2.83 GHz </td> <td>2 × 3 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">65 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">August 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80580AJ0736MG</li></ul> </div> </td> <td>$277 </td></tr> </tbody></table> <p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoVT-xa"><a href="#ref_NoVT-xa"><b><sup>a</sup></b></a></span> Note: Q8200, Q8200S, Q8300 SLB5W does not support Intel VT-x. </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoVT-db"><a href="#ref_NoVT-db"><b><sup>b</sup></b></a></span> Note: Q8200, Q8200S, Q8300, Q8400, Q8400S, Q9500 does not support Intel VT-d. </p><p><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_NoTXTc"><a href="#ref_NoTXTc"><b><sup>c</sup></b></a></span> Note: Q8200, Q8200S, Q8300, Q8400, Q8400S does not support TXT. </p> <div class="mw-heading mw-heading4"><h4 id="Yorkfield_(45_nm)"><span id="Yorkfield_.2845_nm.29"></span>Yorkfield (45 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=13" title="Edit section: Yorkfield (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Intel_VT-d" class="mw-redirect" title="Intel VT-d">Intel VT-d</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 × 107 mm<sup>2</sup></li> <li>The "S" suffix denotes to low power consumption specs with 65W TDP, equivalent to that of a standard Core 2 Duo. Supplied to OEM channels only and mostly seen as options for SFF platforms. The first batch of Q9550S has no "S" marking on lid, thus only differentiated by SSPEC.</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, C1, E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9450"></span><span class="anchor" id="ark33923"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33923.html">Core 2 Quad Q9450</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAN6 (C0)</li> <li>SLAWR (C1)</li></ul> </div> </td> <td>4 </td> <td>2.67 GHz </td> <td>2 × 6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1333 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80569PJ067N</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9550"></span><span class="anchor" id="ark33924"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33924.html">Core 2 Quad Q9550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAN4 (C0)</li> <li>SLAWQ (C1)</li> <li>SLB8V (E0)</li></ul> </div> </td> <td>4 </td> <td>2.83 GHz </td> <td>2 × 6 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80569PJ073N</li> <li>AT80569PJ073N</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9550S*"></span><span class="anchor" id="ark40815"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40815.html">Core 2 Quad Q9550S*</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGAE (E0)</li></ul> </div> </td> <td>4 </td> <td>2.83 GHz </td> <td>2 × 6 MB </td> <td>1333 MT/s </td> <td>8.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">65 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80569AJ073N</li></ul> </div> </td> <td>$369 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9650"></span><span class="anchor" id="ark35428"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35428.html">Core 2 Quad Q9650</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB8W (E0)</li></ul> </div> </td> <td>4 </td> <td>3 GHz </td> <td>2 × 6 MB </td> <td>1333 MT/s </td> <td>9× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">95 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80569PJ080N</li> <li>BX80569Q9650</li></ul> </div> </td> <td>$530 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Yorkfield_XE"_(45_nm)"><span id=".22Yorkfield_XE.22_.2845_nm.29"></span>"Yorkfield XE" (45 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=14" title="Edit section: "Yorkfield XE" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>These models feature an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a></li> <li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></i></li> <li>I/O Acceleration Technology (Intel I/OAT) supported by: QX9775</li> <li>Intel VT-d supported by: QX9650<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 × 107 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, C1, E0</a></li> <li>The QX9750 was never publicly released. Engineering samples have surfaced along with claims that Intel gave them away to employees sometime in 2009.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX9650"></span><span class="anchor" id="ark33921"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33921.html">Core 2 Extreme QX9650</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAN3 (C0)</li> <li>SLAWN (C1)</li></ul> </div> </td> <td>4 </td> <td>3 GHz </td> <td>2 × 6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1333 MT/s </td> <td>9× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">130 W </div> </td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> </td> <td style="text-align:right;">November 2007<sup id="cite_ref-channelregister-071116_17-0" class="reference"><a href="#cite_note-channelregister-071116-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80569XJ080NL</li> <li>BX80569QX9650</li></ul> </div> </td> <td>$999 </td></tr> <tr> <td><span class="cite-bracket" id="Core_2_Extreme_QX9750<sup_id="></span>Core 2 Extreme QX9750<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>QJEE (E0)</li> <li>SLBBU (E0)</li></ul> </div> </td> <td>4 </td> <td>3.17 GHz </td> <td>2 × 6 MB </td> <td>1333 MT/s </td> <td>9.5× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">130 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">N/A </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AT80569XL087NL</li></ul> </div> </td> <td>N/A </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX9770"></span><span class="anchor" id="ark34444"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/34444.html">Core 2 Extreme QX9770</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAN2 (C0)</li> <li>SLAWM (C1)</li></ul> </div> </td> <td>4 </td> <td>3.2 GHz </td> <td>2 × 6 MB </td> <td>1600 MT/s </td> <td>8× </td> <td>0.85–1.3625 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">136 W </div> </td> <td>LGA 775 </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80569XL088NL</li> <li>BX80569QX9770</li></ul> </div> </td> <td>$1399 </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX9775"></span><span class="anchor" id="ark34692"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/34692.html">Core 2 Extreme QX9775</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLANY (C0)</li></ul> </div> </td> <td>4 </td> <td>3.2 GHz </td> <td>2 × 6 MB </td> <td>1600 MT/s </td> <td>8× </td> <td>0.85–1.35 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">150 W </div> </td> <td>LGA 771 </td> <td style="text-align:right;">March 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EU80574XL088N</li> <li>BX80574QX9775</li></ul> </div> </td> <td>$1499 </td></tr> </tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(1st_gen)"><span id="Core_i_.281st_gen.29"></span>Core i (1st gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=15" title="Edit section: Core i (1st gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Lynnfield">Lynnfield<span class="anchor" id=""Lynnfield"_(45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=16" title="Edit section: Lynnfield"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM at up to 1333 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 1.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/45_nm_process" title="45 nm process">45 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="6">Core i7 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48500.html">880</a> </th> <td rowspan="6">4 (8) </td> <td>3.06 </td> <td>3.73 </td> <td rowspan="9">8 MB </td> <td rowspan="3">95 W </td> <td rowspan="2"><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td> <td>US $583 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48499.html">875K</a> </th> <td rowspan="2">2.93 </td> <td rowspan="3">3.60 </td> <td>US $342 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/41315.html">870</a> </th> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td> <td>US $562 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48498.html">870S</a> </th> <td>2.67 </td> <td>82 W </td> <td><span data-sort-value="000000002010-07-01-0000" style="white-space:nowrap">July 2010</span> </td> <td>US $351 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/41316.html">860</a> </th> <td>2.80 </td> <td rowspan="2">3.46 </td> <td>95 W </td> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td> <td>US $284 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/41318.html">860S</a> </th> <td>2.53 </td> <td>82 W </td> <td><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td> <td>US $337 </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48496.html">760</a> </th> <td rowspan="3">4 (4) </td> <td>2.80 </td> <td>3.33 </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002010-07-01-0000" style="white-space:nowrap">July 2010</span> </td> <td>US $205 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42915.html">750</a> </th> <td>2.66 </td> <td rowspan="2">3.20 </td> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td> <td>US $196 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42917.html">750S</a> </th> <td>2.40 </td> <td>82 W </td> <td><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td> <td>US $259 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Bloomfield">Bloomfield<span class="anchor" id=""Bloomfield"_(45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=17" title="Edit section: Bloomfield"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a>.</li> <li>All the CPUs support triple-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1066 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>PCIe lanes are provided by the northbridge on the motherboard rather than by the CPU.</li> <li>All CPUs feature a <a href="/wiki/QuickPath_Interconnect" class="mw-redirect" title="QuickPath Interconnect">QPI</a> bus to the chipset (<a href="/wiki/Northbridge_(computing)" title="Northbridge (computing)">northbridge</a>). <ul><li>Bus speed is 4.8 <a href="/wiki/GT/s" class="mw-redirect" title="GT/s">GT/s</a> on all the processors except for the Extreme Edition models, which run at 6.4 GT/s.</li></ul></li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/45_nm_process" title="45 nm process">45 nm</a>.</li> <li>Extreme Edition processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="7">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37153.html">975 Extreme Edition</a> </th> <td rowspan="7">4 (8) </td> <td>3.33 </td> <td>3.60 </td> <td rowspan="7">8 MB </td> <td rowspan="7">130 W </td> <td><span data-sort-value="000000002009-06-01-0000" style="white-space:nowrap">June 2009</span> </td> <td rowspan="2">US $999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37149.html">965 Extreme Edition</a> </th> <td rowspan="2">3.20 </td> <td rowspan="2">3.46 </td> <td><span data-sort-value="000000002008-11-01-0000" style="white-space:nowrap">November 2008</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37151.html">960</a> </th> <td><span data-sort-value="000000002009-10-01-0000" style="white-space:nowrap">October 2009</span> </td> <td rowspan="3">US $562 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37150.html">950</a> </th> <td>3.06 </td> <td>3.33 </td> <td><span data-sort-value="000000002009-06-01-0000" style="white-space:nowrap">June 2009</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37148.html">940</a> </th> <td>2.93 </td> <td>3.20 </td> <td><span data-sort-value="000000002008-11-01-0000" style="white-space:nowrap">November 2008</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/41447.html">930</a> </th> <td>2.80 </td> <td>3.06 </td> <td><span data-sort-value="000000002010-02-01-0000" style="white-space:nowrap">February 2010</span> </td> <td>US $294 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37147.html">920</a> </th> <td>2.66 </td> <td>2.93 </td> <td><span data-sort-value="000000002008-11-01-0000" style="white-space:nowrap">November 2008</span> </td> <td>US $284 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Clarkdale">Clarkdale<span class="anchor" id=""Clarkdale"_(MCP,_32_nm)"></span><span class="anchor" id=""Clarkdale"_(MCP,_32_nm_dual-core)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=18" title="Edit section: Clarkdale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i3_540_(Westmere)_(PNG).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9e/Intel_i3_540_%28Westmere%29_%28PNG%29.png/220px-Intel_i3_540_%28Westmere%29_%28PNG%29.png" decoding="async" width="220" height="246" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9e/Intel_i3_540_%28Westmere%29_%28PNG%29.png/330px-Intel_i3_540_%28Westmere%29_%28PNG%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9e/Intel_i3_540_%28Westmere%29_%28PNG%29.png/440px-Intel_i3_540_%28Westmere%29_%28PNG%29.png 2x" data-file-width="10305" data-file-height="11500" /></a><figcaption>Intel i3 540 CPU die shot (Westmere)</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i3_540_CPU_and_IGPU_Dies_(50212178048).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6d/Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg/220px-Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg" decoding="async" width="220" height="206" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6d/Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg/330px-Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6d/Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg/440px-Intel_i3_540_CPU_and_IGPU_Dies_%2850212178048%29.jpg 2x" data-file-width="2607" data-file-height="2440" /></a><figcaption>Intel i3 540 CPU and IGPU Dies</figcaption></figure> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1333 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 1.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="6">Core i5 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48504.html">680</a> </th> <td rowspan="10">2 (4) </td> <td>3.60 </td> <td>3.86 </td> <td rowspan="10"><a href="/wiki/Intel_Graphics_Technology#Westmere" title="Intel Graphics Technology">HD Graphics</a> </td> <td rowspan="2">733 </td> <td rowspan="10">4 MB </td> <td rowspan="2">73 W </td> <td><span data-sort-value="000000002010-04-01-0000" style="white-space:nowrap">April 2010</span> </td> <td>US $294 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43556.html">670</a> </th> <td>3.46 </td> <td>3.73 </td> <td rowspan="3"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td> <td>US $284 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43553.html">661</a> </th> <td rowspan="2">3.33 </td> <td rowspan="2">3.60 </td> <td>900 </td> <td>87 W </td> <td rowspan="2">US $196 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43550.html">660</a> </th> <td rowspan="7">733 </td> <td rowspan="7">73 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48750.html">655K</a> </th> <td rowspan="2">3.20 </td> <td rowspan="2">3.46 </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td> <td>US $216 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43546.html">650</a> </th> <td><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td> <td>US $176 </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50177.html">560</a> </th> <td>3.33 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002010-08-01-0000" style="white-space:nowrap">August 2010</span> </td> <td rowspan="2">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48505.html">550</a> </th> <td>3.20 </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/46473.html">540</a> </th> <td>3.06 </td> <td rowspan="2"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td> <td>US $133 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/46472.html">530</a> </th> <td>2.93 </td> <td>US $113 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Gulftown">Gulftown<span class="anchor" id=""Gulftown"_(32_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=19" title="Edit section: Gulftown"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a>.</li> <li>All the CPUs support triple-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1066 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>PCIe lanes are provided by the northbridge on the motherboard rather than by the CPU.</li> <li>All CPUs feature a <a href="/wiki/QuickPath_Interconnect" class="mw-redirect" title="QuickPath Interconnect">QPI</a> bus to the chipset (<a href="/wiki/Northbridge_(computing)" title="Northbridge (computing)">northbridge</a>). <ul><li>Bus speed is 4.8 <a href="/wiki/GT/s" class="mw-redirect" title="GT/s">GT/s</a> on all the processors except for the X-suffix models, which run at 6.4 GT/s.</li></ul></li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li> <li>X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52585.html">990X</a> </th> <td rowspan="4">6 (12) </td> <td>3.46 </td> <td>3.73 </td> <td rowspan="4">12 MB </td> <td rowspan="4">130 W </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td> <td rowspan="2">US $999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47932.html">980X</a> </th> <td rowspan="2">3.33 </td> <td rowspan="2">3.60 </td> <td><span data-sort-value="000000002010-03-01-0000" style="white-space:nowrap">March 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/58664.html">980</a> </th> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td> <td>US $583 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47933.html">970</a> </th> <td>3.20 </td> <td>3.46 </td> <td><span data-sort-value="000000002010-07-01-0000" style="white-space:nowrap">July 2010</span> </td> <td>US $885 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(2nd_gen)"><span id="Core_i_.282nd_gen.29"></span>Core i (2nd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=20" title="Edit section: Core i (2nd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Sandy_Bridge-DT">Sandy Bridge-DT<span class="anchor" id=""Sandy_Bridge"_(32_nm)"></span><span class="anchor" id=""Sandy_Bridge"_(dual-core,_32_nm)"></span><span class="anchor" id=""Sandy_Bridge"_(quad-core,_32_nm)"></span><span class="anchor" id=""Sandy_Bridge-DT"_(32_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=21" title="Edit section: Sandy Bridge-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i5_2500_-_ring_light_(98%25_quality_JPG).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/cc/Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg/220px-Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg" decoding="async" width="220" height="114" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/cc/Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg/330px-Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/cc/Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg/440px-Intel_i5_2500_-_ring_light_%2898%25_quality_JPG%29.jpg 2x" data-file-width="23527" data-file-height="12210" /></a><figcaption>Intel i5 2500 die shot</figcaption></figure> <ul><li>Socket: <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1333 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i3-2120, i5-2400, and i7-2600 are available as embedded processors.</li> <li>The Core i3-2102, once upgraded via Intel Upgrade Service, operates at 3.6 GHz, has 3 MB L3 cache and is recognized as Core i3-2153.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/61275.html">2700K</a> </th> <td rowspan="4">4 (8) </td> <td>3.5 </td> <td>3.9 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Sandy_Bridge" title="Intel Graphics Technology">HD 3000</a> </td> <td rowspan="4">850–1350 </td> <td rowspan="4">8 MB </td> <td rowspan="3">95 W </td> <td><span data-sort-value="000000002011-10-01-0000" style="white-space:nowrap">October 2011</span> </td> <td>US $332 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52214.html">2600K</a> </th> <td rowspan="2">3.4 </td> <td rowspan="4">3.8 </td> <td rowspan="3"><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td> <td>US $317 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52213.html">2600</a> </th> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Sandy_Bridge" title="Intel Graphics Technology">HD 2000</a> </td> <td>US $294 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52215.html">2600S</a> </th> <td>2.8 </td> <td>65 W </td> <td>US $306 </td></tr> <tr> <th rowspan="14">Core i5 </th> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65647.html">2550K</a> </th> <td rowspan="9">4 (4) </td> <td>3.4 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="9">6 MB </td> <td rowspan="3">95 W </td> <td><span data-sort-value="000000002012-01-01-0000" style="white-space:nowrap">January 2012</span> </td> <td>US $225 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52210.html">2500K</a> </th> <td rowspan="2">3.3 </td> <td rowspan="3">3.7 </td> <td>HD 3000 </td> <td rowspan="3">850–1100 </td> <td rowspan="4"><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td> <td>US $216 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52209.html">2500</a> </th> <td rowspan="3">HD 2000 </td> <td>US $205 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52211.html">2500S</a> </th> <td>2.7 </td> <td>65 W </td> <td rowspan="2">US $216 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52212.html">2500T</a> </th> <td>2.3 </td> <td>3.3 </td> <td>650–1250 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64843.html">2450P</a> </th> <td>3.2 </td> <td>3.5 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002012-01-01-0000" style="white-space:nowrap">January 2012</span> </td> <td>US $195 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52207.html">2400</a> </th> <td>3.1 </td> <td>3.4 </td> <td>HD 2000 </td> <td rowspan="3">850–1100 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td> <td>US $184 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/55446.html">2405S</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">3.3 </td> <td>HD 3000 </td> <td rowspan="2">65 W </td> <td><span data-sort-value="000000002011-05-01-0000" style="white-space:nowrap">May 2011</span> </td> <td>US $205 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52208.html">2400S</a> </th> <td rowspan="2">HD 2000 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td> <td rowspan="2">US $195 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53448.html">2390T</a> </th> <td>2 (4) </td> <td>2.7 </td> <td>3.5 </td> <td>650–1100 </td> <td>3 MB </td> <td>35 W </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64844.html">2380P</a> </th> <td rowspan="4">4 (4) </td> <td>3.1 </td> <td>3.4 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">6 MB </td> <td rowspan="4">95 W </td> <td><span data-sort-value="000000002012-01-01-0000" style="white-space:nowrap">January 2012</span> </td> <td rowspan="4">US $177 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53446.html">2320</a> </th> <td>3.0 </td> <td>3.3 </td> <td rowspan="4">HD 2000 </td> <td rowspan="3">850–1100 </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53445.html">2310</a> </th> <td>2.9 </td> <td>3.2 </td> <td><span data-sort-value="000000002011-05-01-0000" style="white-space:nowrap">May 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52206.html">2300</a> </th> <td>2.8 </td> <td>3.1 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th rowspan="8">Core i3 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53428.html">2130</a> </th> <td rowspan="8">2 (4) </td> <td>3.4 </td> <td rowspan="8" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">850–1100 </td> <td rowspan="8">3 MB </td> <td rowspan="3">65 W </td> <td rowspan="2"><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td> <td>US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/59080.html">2125</a> </th> <td rowspan="2">3.3 </td> <td>HD 3000 </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53426.html">2120</a> </th> <td rowspan="2">HD 2000 </td> <td rowspan="2"><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td> <td>US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53427.html">2120T</a> </th> <td>2.6 </td> <td>650–1100 </td> <td>35 W </td> <td>US $127 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/55448.html">2105</a> </th> <td rowspan="3">3.1 </td> <td>HD 3000 </td> <td rowspan="3">850–1100 </td> <td rowspan="3">65 W </td> <td><span data-sort-value="000000002011-05-01-0000" style="white-space:nowrap">May 2011</span> </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53424.html">2102</a> </th> <td rowspan="3">HD 2000 </td> <td>Q2 2011 </td> <td>US $127 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53422.html">2100</a> </th> <td rowspan="2"><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td> <td>US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53423.html">2100T</a> </th> <td>2.5 </td> <td>650–1100 </td> <td>35 W </td> <td>US $127 </td></tr> </tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(3rd_gen)"><span id="Core_i_.283rd_gen.29"></span>Core i (3rd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=22" title="Edit section: Core i (3rd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Ivy_Bridge-DT">Ivy Bridge-DT<span class="anchor" id=""Ivy_Bridge"_(22_nm)"></span><span class="anchor" id=""Ivy_Bridge"_(dual-core,_22_nm)"></span><span class="anchor" id=""Ivy_Bridge"_(quad-core,_22_nm)"></span><span class="anchor" id=""Ivy_Bridge-DT"_(22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=23" title="Edit section: Ivy Bridge-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1600 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of PCIe. i5 and up models support it at <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> speeds while i3 models support it at PCIe 2.0 speeds.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i3-3220, i5-3550S and i7-3770 are available as embedded processors.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku31"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65523.html">3770K</a> </th> <td rowspan="4">4 (8) </td> <td>3.5 </td> <td rowspan="3">3.9 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Ivy_Bridge" title="Intel Graphics Technology">HD 4000</a> </td> <td rowspan="10">650–1150 </td> <td rowspan="4">8 MB </td> <td rowspan="2">77 W </td> <td rowspan="5"><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td> <td>US $342 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku30"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65719.html">3770</a> </th> <td>3.4 </td> <td>US $305 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku29"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65524.html">3770S</a> </th> <td>3.1 </td> <td>65 W </td> <td>US $305 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65525.html">3770T</a> </th> <td>2.5 </td> <td>3.7 </td> <td>45 W </td> <td>US $294 </td></tr> <tr> <th rowspan="18">Core i5 </th> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65520.html">3570K</a> </th> <td rowspan="9">4 (4) </td> <td rowspan="2">3.4 </td> <td rowspan="3">3.8 </td> <td rowspan="9">6 MB </td> <td rowspan="2">77 W </td> <td>US $225 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65702.html">3570</a> </th> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Ivy_Bridge" title="Intel Graphics Technology">HD 2500</a> </td> <td rowspan="2"><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td> <td rowspan="5">US $205 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65701.html">3570S</a> </th> <td>3.1 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65521.html">3570T</a> </th> <td>2.3 </td> <td>3.3 </td> <td>45 W </td> <td rowspan="3"><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65516.html">3550</a> </th> <td>3.3 </td> <td rowspan="2">3.7 </td> <td>77 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65518.html">3550S</a> </th> <td>3.0 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/68316.html">3470</a> </th> <td>3.2 </td> <td rowspan="4">3.6 </td> <td rowspan="6">650–1100 </td> <td>77 W </td> <td rowspan="4"><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td> <td>US $184 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65515.html">3475S</a> </th> <td rowspan="3">2.9 </td> <td>HD 4000 </td> <td rowspan="2">65 W </td> <td>US $201 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/68315.html">3470S</a> </th> <td rowspan="4">HD 2500 </td> <td rowspan="4">US $184 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65703.html">3470T</a> </th> <td>2 (4) </td> <td>3 MB </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65511.html">3450</a> </th> <td rowspan="8">4 (4) </td> <td>3.1 </td> <td rowspan="2">3.5 </td> <td rowspan="8">6 MB </td> <td>77 W </td> <td rowspan="2"><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65512.html">3450S</a> </th> <td>2.8 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/69114.html">3350P</a> </th> <td rowspan="2">3.1 </td> <td rowspan="3">3.3 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>69 W </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td> <td>US $177 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76342.html">3340</a> </th> <td rowspan="3">HD 2500 </td> <td rowspan="14">650–1050 </td> <td>77 W </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td> <td rowspan="3">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76343.html">3340S</a> </th> <td>2.8 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65509.html">3330</a> </th> <td>3.0 </td> <td rowspan="3">3.2 </td> <td>77 W </td> <td rowspan="3"><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11">3335S </th> <td rowspan="2">2.7 </td> <td>HD 4000 </td> <td rowspan="2">65 W </td> <td>US $194 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65510.html">3330S</a> </th> <td rowspan="3">HD 2500 </td> <td>US $177 </td></tr> <tr> <th rowspan="9">Core i3 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/74744.html">3250</a> </th> <td rowspan="9">2 (4) </td> <td>3.5 </td> <td rowspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="9">3 MB </td> <td>55 W </td> <td rowspan="3"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td> <td rowspan="2">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/74745.html">3250T</a> </th> <td>3.0 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230629210739/https://ark.intel.com/content/www/us/en/ark/products/74746/intel-core-i33245-processor-3m-cache-3-40-ghz.html">3245</a> </th> <td rowspan="2">3.4 </td> <td>HD 4000 </td> <td rowspan="2">55 W </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65690.html">3240</a> </th> <td rowspan="2">HD 2500 </td> <td rowspan="5"><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td> <td rowspan="2">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/66168.html">3240T</a> </th> <td>2.9 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65692.html">3225</a> </th> <td rowspan="2">3.3 </td> <td>HD 4000 </td> <td rowspan="2">55 W </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65693.html">3220</a> </th> <td rowspan="3">HD 2500 </td> <td rowspan="3">US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65694.html">3220T</a> </th> <td>2.8 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71053.html">3210</a> </th> <td>3.2 </td> <td>55 W </td> <td><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Sandy_Bridge-E">Sandy Bridge-E<span class="anchor" id=""Sandy_Bridge-E"_(32_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=24" title="Edit section: Sandy Bridge-E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>-1600 RAM.</li> <li>All CPU models provide 40 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li> <li>K-suffix and X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/70845.html">3970X</a> </th> <td rowspan="3">6 (12) </td> <td>3.5 </td> <td>4.0 </td> <td rowspan="2">15 MB </td> <td>150 W </td> <td><span data-sort-value="000000002012-11-01-0000" style="white-space:nowrap">November 2012</span> </td> <td rowspan="2">US $999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/63696.html">3960X</a> </th> <td>3.3 </td> <td>3.9 </td> <td rowspan="3">130 W </td> <td rowspan="2"><span data-sort-value="000000002011-11-01-0000" style="white-space:nowrap">November 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/63697.html">3930K</a> </th> <td>3.2 </td> <td>3.8 </td> <td>12 MB </td> <td>US $583 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/63698.html">3820</a> </th> <td>4 (8) </td> <td>3.6 </td> <td>3.8 </td> <td>10 MB </td> <td><span data-sort-value="000000002012-02-01-0000" style="white-space:nowrap">February 2012</span> </td> <td>US $294 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(4th_gen)"><span id="Core_i_.284th_gen.29"></span>Core i (4th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=25" title="Edit section: Core i (4th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Haswell-DT">Haswell-DT<span class="anchor" id=""Haswell-DT"_(22_nm)"></span><span class="anchor" id=""Haswell-DT"_(dual-core,_22_nm)"></span><span class="anchor" id=""Haswell-DT"_(quad-core,_22_nm,_4th_generation)"></span><span class="anchor" id="Haswell-DT_(quad-core,_22_nm)"></span><span class="anchor" id=""Haswell-DT"_(quad-core,_22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=26" title="Edit section: Haswell-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i3_4130,_Haswell_22nm_(PNG).png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c9/Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png/220px-Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png" decoding="async" width="220" height="111" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c9/Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png/330px-Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c9/Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png/440px-Intel_i3_4130%2C_Haswell_22nm_%28PNG%29.png 2x" data-file-width="15000" data-file-height="7556" /></a><figcaption>Intel i3 4130, Haswell 22nm die shot</figcaption></figure> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM at up to 1600 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>The following models are available as embedded processors: i3- 4330, 4350T, 4360, i5- 4570S, 4590T, 4590S, i7- 4770S, 4790S.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="11">Core i7 </th> <th style="text-align:left;" data-sort-value="sku50"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80807.html">4790K</a> </th> <td rowspan="11">4 (8) </td> <td>4.0 </td> <td>4.4 </td> <td rowspan="42"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4600</a> </td> <td>350–1250 </td> <td rowspan="11">8 MB </td> <td>88 W </td> <td><span data-sort-value="000000002014-06-01-0000" style="white-space:nowrap">June 2014</span> </td> <td>US $350 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku49"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80806.html">4790</a> </th> <td>3.6 </td> <td rowspan="2">4.0 </td> <td rowspan="4">350–1200 </td> <td>84 W </td> <td rowspan="4"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td> <td rowspan="2">US $312 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku48"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80808.html">4790S</a> </th> <td>3.2 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku47"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80809.html">4790T</a> </th> <td>2.7 </td> <td>3.9 </td> <td>45 W </td> <td rowspan="2">US $303 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku46"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80814.html">4785T</a> </th> <td>2.2 </td> <td>3.2 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku45"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75123.html">4770K</a> </th> <td rowspan="2">3.5 </td> <td rowspan="4">3.9 </td> <td>350–1250 </td> <td rowspan="3">84 W </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td> <td>US $350 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku44"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77656.html">4771</a> </th> <td rowspan="13">350–1200 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td> <td>US $320 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku43"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75122.html">4770</a> </th> <td>3.4 </td> <td rowspan="4"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td> <td>US $312 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku42"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75124.html">4770S</a> </th> <td>3.1 </td> <td>65 W </td> <td>US $305 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku41"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75125.html">4770T</a> </th> <td>2.5 </td> <td>3.7 </td> <td>45 W </td> <td rowspan="2">US $303 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku40"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75121.html">4765T</a> </th> <td>2.0 </td> <td>3.0 </td> <td>35 W </td></tr> <tr> <th rowspan="22">Core i5 </th> <th style="text-align:left;" data-sort-value="sku39"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80811.html">4690K</a> </th> <td rowspan="13">4 (4) </td> <td rowspan="2">3.5 </td> <td rowspan="3">3.9 </td> <td rowspan="13">6 MB </td> <td>88 W </td> <td><span data-sort-value="000000002014-06-01-0000" style="white-space:nowrap">June 2014</span> </td> <td>US $242 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku38"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80810.html">4690</a> </th> <td>84 W </td> <td rowspan="3"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td> <td rowspan="3">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku37"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80812.html">4690S</a> </th> <td>3.2 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku36"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80813.html">4690T</a> </th> <td>2.5 </td> <td>3.5 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku35"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75048.html">4670K</a> </th> <td rowspan="2">3.4 </td> <td rowspan="3">3.8 </td> <td rowspan="2">84 W </td> <td rowspan="4"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td> <td>US $242 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku34"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75047.html">4670</a> </th> <td rowspan="3">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku33"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75049.html">4670S</a> </th> <td>3.1 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku32"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75050.html">4670T</a> </th> <td>2.3 </td> <td>3.3 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku31"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80815.html">4590</a> </th> <td>3.3 </td> <td rowspan="2">3.7 </td> <td rowspan="5">350–1150 </td> <td>84 W </td> <td rowspan="3"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td> <td rowspan="6">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku30"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80816.html">4590S</a> </th> <td>3.0 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku29"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78928.html">4590T</a> </th> <td>2.0 </td> <td>3.0 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75043.html">4570</a> </th> <td>3.2 </td> <td rowspan="3">3.6 </td> <td>84 W </td> <td rowspan="3"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75044.html">4570S</a> </th> <td rowspan="2">2.9 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75045.html">4570T</a> </th> <td>2 (4) </td> <td>200–1150 </td> <td>4 MB </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25">4470 </th> <td rowspan="8">4 (4) </td> <td>3.3 </td> <td>3.5 </td> <td rowspan="8">350–1100 </td> <td rowspan="8">6 MB </td> <td rowspan="2">84 W </td> <td rowspan="3"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80817.html">4460</a> </th> <td>3.2 </td> <td rowspan="2">3.4 </td> <td rowspan="7">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80818.html">4460S</a> </th> <td>2.9 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78927.html">4460T</a> </th> <td>1.9 </td> <td>2.7 </td> <td>35 W </td> <td><span data-sort-value="000000002014-03-01-0000" style="white-space:nowrap">March 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75038.html">4440</a> </th> <td>3.1 </td> <td rowspan="2">3.3 </td> <td>84 W </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75040.html">4440S</a> </th> <td>2.8 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75036.html">4430</a> </th> <td>3.0 </td> <td rowspan="2">3.2 </td> <td>84 W </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75037.html">4430S</a> </th> <td>2.7 </td> <td>65 W </td></tr> <tr> <th rowspan="17">Core i3 </th> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77495.html">4370</a> </th> <td rowspan="17">2 (4) </td> <td>3.8 </td> <td rowspan="17" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–1150 </td> <td rowspan="9">4 MB </td> <td>54 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td> <td>US $149 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81207.html">4370T</a> </th> <td>3.3 </td> <td>200–1150 </td> <td>35 W </td> <td><span data-sort-value="000000002015-03-01-0000" style="white-space:nowrap">March 2015</span> </td> <td>US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77493.html">4360</a> </th> <td>3.7 </td> <td>350–1150 </td> <td>54 W </td> <td><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td> <td>US $149 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77494.html">4360T</a> </th> <td>3.2 </td> <td>200–1150 </td> <td>35 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td> <td rowspan="3">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77491.html">4350</a> </th> <td>3.6 </td> <td>350–1150 </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77492.html">4350T</a> </th> <td>3.1 </td> <td>200–1150 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77771.html">4340</a> </th> <td>3.6 </td> <td rowspan="2">350–1150 </td> <td rowspan="2">54 W </td> <td rowspan="3"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td> <td>US $149 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77769.html">4330</a> </th> <td>3.5 </td> <td rowspan="2">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77770.html">4330T</a> </th> <td>3.0 </td> <td>200–1150 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77490.html">4170</a> </th> <td>3.7 </td> <td rowspan="8"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4400</a> </td> <td>350–1150 </td> <td rowspan="8">3 MB </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002015-03-01-0000" style="white-space:nowrap">March 2015</span> </td> <td rowspan="6">US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81209.html">4170T</a> </th> <td>3.2 </td> <td>200–1150 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77488.html">4160</a> </th> <td>3.6 </td> <td>350–1150 </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77489.html">4160T</a> </th> <td>3.1 </td> <td>200–1150 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77486.html">4150</a> </th> <td>3.5 </td> <td>350–1150 </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77487.html">4150T</a> </th> <td>3.0 </td> <td>200–1150 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77480.html">4130</a> </th> <td>3.4 </td> <td>350–1150 </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td> <td rowspan="2">US $122 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77481.html">4130T</a> </th> <td>2.9 </td> <td>200–1150 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Haswell-H">Haswell-H<span class="anchor" id=""Haswell-H"_(MCP,_quad-core,_22_nm)"></span><span class="anchor" id="Haswell-H_(MCP,_quad-core,_22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=27" title="Edit section: Haswell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1364 (soldered).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1600 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>In addition to the Smart Cache (L3 cache), Haswell-H CPUs also contain 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76642.html">4770R</a> </th> <td>4 (8) </td> <td>3.2 </td> <td>3.9 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">Iris Pro 5200</a> </td> <td rowspan="2">200–1300 </td> <td>6 MB </td> <td rowspan="3">65 W </td> <td rowspan="3"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76641.html">4670R</a> </th> <td rowspan="2">4 (4) </td> <td>3.0 </td> <td>3.7 </td> <td rowspan="2">4 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76640.html">4570R</a> </th> <td>2.7 </td> <td>3.2 </td> <td>200–1150 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Ivy_Bridge-E">Ivy Bridge-E<span class="anchor" id=""Ivy_Bridge-E"_(22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=28" title="Edit section: Ivy Bridge-E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>-1866 RAM.</li> <li>All CPU models provide 40 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>K-suffix and X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77779.html">4960X</a> </th> <td rowspan="2">6 (12) </td> <td>3.6 </td> <td>4.0 </td> <td>15 MB </td> <td rowspan="3">130 W </td> <td rowspan="3"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td> <td>US $990 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77780.html">4930K</a> </th> <td>3.4 </td> <td rowspan="2">3.9 </td> <td>12 MB </td> <td>US $555 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77781.html">4820K</a> </th> <td>4 (8) </td> <td>3.7 </td> <td>10 MB </td> <td>US $310 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(5th_gen)"><span id="Core_i_.285th_gen.29"></span>Core i (5th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=29" title="Edit section: Core i (5th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Broadwell-H">Broadwell-H<span class="anchor" id=""Broadwell-H"_(quad-core,_14_nm)"></span><span class="anchor" id="Broadwell-H_(quad-core,_14_nm)"></span><span class="anchor" id=""Broadwell-DT"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=30" title="Edit section: Broadwell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a> for C-suffix processors, BGA 1364 soldered for R-suffix.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM. C-suffix processors support it at speeds up to 1600 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a>, while R-suffix support it at 1866 MT/s.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>In addition to the Smart Cache (L3 cache), Broadwell-H CPUs also contain 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87718.html">5775R</a> </th> <td rowspan="2">4 (8) </td> <td rowspan="2">3.3 </td> <td>3.8 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">Iris Pro 6200</a> </td> <td rowspan="2">300–1150 </td> <td rowspan="2">6 MB </td> <td rowspan="5">65 W </td> <td rowspan="5"><span data-sort-value="000000002015-06-01-0000" style="white-space:nowrap">June 2015</span> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88040.html">5775C</a> </th> <td>3.7 </td> <td>US $366 </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87715.html">5675R</a> </th> <td rowspan="3">4 (4) </td> <td rowspan="2">3.1 </td> <td rowspan="2">3.6 </td> <td rowspan="2">300–1100 </td> <td rowspan="3">4 MB </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88095.html">5675C</a> </th> <td>US $276 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87714.html">5575R</a> </th> <td>2.8 </td> <td>3.3 </td> <td>300–1050 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Haswell-E">Haswell-E<span class="anchor" id=""Haswell-E"_(22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=31" title="Edit section: Haswell-E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2011-3" class="mw-redirect" title="LGA 2011-3">LGA 2011-3</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133 RAM.</li> <li>i7-5820K provides 28 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>; i7-5930K and 5960X provide 40 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>K-suffix and X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/82930.html">5960X</a> </th> <td>8 (16) </td> <td>3.0 </td> <td>3.5 </td> <td>20 MB </td> <td rowspan="3">140 W </td> <td rowspan="3"><span data-sort-value="000000002014-08-01-0000" style="white-space:nowrap">August 2014</span> </td> <td>US $999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/82931.html">5930K</a> </th> <td rowspan="2">6 (12) </td> <td>3.5 </td> <td>3.7 </td> <td rowspan="2">15 MB </td> <td>US $583 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/82932.html">5820K</a> </th> <td>3.3 </td> <td>3.6 </td> <td>US $389 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(6th_gen)"><span id="Core_i_.286th_gen.29"></span>Core i (6th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=32" title="Edit section: Core i (6th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Skylake-S">Skylake-S<span class="anchor" id=""Skylake-S"_(14_nm)"></span><span class="anchor" id=""Skylake-S"_(quad-core,_14_nm)"></span><span class="anchor" id="Skylake-S_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=33" title="Edit section: Skylake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88195.html">6700K</a> </th> <td rowspan="3">4 (8) </td> <td>4.0 </td> <td>4.2 </td> <td rowspan="8"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 530</a> </td> <td rowspan="2">350–1150 </td> <td rowspan="3">8 MB </td> <td>91 W </td> <td><span data-sort-value="000000002015-08-01-0000" style="white-space:nowrap">August 2015</span> </td> <td>US $339 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88196.html">6700</a> </th> <td>3.4 </td> <td>4.0 </td> <td>65 W </td> <td rowspan="2"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td> <td rowspan="2">US $303 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88200.html">6700T</a> </th> <td>2.8 </td> <td>3.6 </td> <td>350–1100 </td> <td>35 W </td></tr> <tr> <th rowspan="8">Core i5 </th> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88191.html">6600K</a> </th> <td rowspan="8">4 (4) </td> <td>3.5 </td> <td rowspan="2">3.9 </td> <td rowspan="2">350–1150 </td> <td rowspan="8">6 MB </td> <td>91 W </td> <td><span data-sort-value="000000002015-08-01-0000" style="white-space:nowrap">August 2015</span> </td> <td>US $243 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88188.html">6600</a> </th> <td>3.3 </td> <td>65 W </td> <td rowspan="4"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88189.html">6600T</a> </th> <td>2.7 </td> <td>3.5 </td> <td>350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88184.html">6500</a> </th> <td>3.2 </td> <td>3.6 </td> <td>350–1050 </td> <td>65 W </td> <td rowspan="2">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88183.html">6500T</a> </th> <td>2.5 </td> <td>3.1 </td> <td>350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93277.html">6402P</a> </th> <td>2.8 </td> <td>3.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 510</a> </td> <td rowspan="3">350–950 </td> <td rowspan="2">65 W </td> <td><span data-sort-value="000000002015-12-01-0000" style="white-space:nowrap">December 2015</span> </td> <td rowspan="3">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88185.html">6400</a> </th> <td>2.7 </td> <td>3.3 </td> <td rowspan="7">HD 530 </td> <td rowspan="7"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88187.html">6400T</a> </th> <td>2.2 </td> <td>2.8 </td> <td>35 W </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90733.html">6320</a> </th> <td rowspan="6">2 (4) </td> <td>3.9 </td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">350–1150 </td> <td rowspan="3">4 MB </td> <td rowspan="2">51 W </td> <td>US $148 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90731.html">6300</a> </th> <td>3.8 </td> <td>US $139 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90728.html">6300T</a> </th> <td>3.3 </td> <td>350–950 </td> <td>35 W </td> <td>US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90729.html">6100</a> </th> <td>3.7 </td> <td>350–1050 </td> <td rowspan="3">3 MB </td> <td>51 W </td> <td rowspan="3">US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90734.html">6100T</a> </th> <td>3.2 </td> <td>350–950 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93366.html">6098P</a> </th> <td>3.6 </td> <td>HD 510 </td> <td>350–1050 </td> <td>54 W </td> <td><span data-sort-value="000000002015-12-01-0000" style="white-space:nowrap">December 2015</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Skylake-H">Skylake-H<span class="anchor" id=""Skylake-H"_(quad-core,_14_nm)"></span><span class="anchor" id="Skylake-H_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=34" title="Edit section: Skylake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440 (soldered).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>In addition to the Smart Cache (L3 cache), Skylake-H CPUs also contain 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93339.html">6785R</a> </th> <td>4 (8) </td> <td>3.3 </td> <td>3.9 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">Iris Pro 580</a> </td> <td rowspan="2">350–1150 </td> <td>8 MB </td> <td rowspan="3">65 W </td> <td rowspan="3"><span data-sort-value="000000002016-05-01-0000" style="white-space:nowrap">May 2016</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93338.html">6685R</a> </th> <td rowspan="2">4 (4) </td> <td>3.2 </td> <td>3.8 </td> <td rowspan="2">6 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93337.html">6585R</a> </th> <td>2.8 </td> <td>3.6 </td> <td>350–1100 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Broadwell-E">Broadwell-E<span class="anchor" id=""Broadwell-E"_(14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=35" title="Edit section: Broadwell-E"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2011-3" class="mw-redirect" title="LGA 2011-3">LGA 2011-3</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 RAM.</li> <li>i7-6800K provides 28 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>; all other models provide 40 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix and X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/94456.html">6950X</a> </th> <td>10 (20) </td> <td>3.0 </td> <td>3.5 </td> <td>25 MB </td> <td rowspan="4">140 W </td> <td rowspan="4"><span data-sort-value="000000002016-05-01-0000" style="white-space:nowrap">May 2016</span> </td> <td>US $1723 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/94196.html">6900K</a> </th> <td>8 (16) </td> <td>3.2 </td> <td>3.7 </td> <td>20 MB </td> <td>US $1089 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/94188.html">6850K</a> </th> <td rowspan="2">6 (12) </td> <td>3.6 </td> <td rowspan="2">3.8 </td> <td rowspan="2">15 MB </td> <td>US $617 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/94189.html">6800K</a> </th> <td>3.4 </td> <td>US $434 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(7th_gen)"><span id="Core_i_.287th_gen.29"></span>Core i (7th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=36" title="Edit section: Core i (7th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-S">Kaby Lake-S<span class="anchor" id=""Kaby_Lake-S"_(14_nm)"></span><span class="anchor" id="Kaby_Lake-S"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=37" title="Edit section: Kaby Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97129.html">7700K</a> </th> <td rowspan="3">4 (8) </td> <td>4.2 </td> <td>4.5 </td> <td rowspan="16"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 630</a> </td> <td rowspan="5">350–1150 </td> <td rowspan="3">8 MB </td> <td>91 W </td> <td rowspan="16"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td> <td>US $339 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97128.html">7700</a> </th> <td>3.6 </td> <td>4.2 </td> <td>65 W </td> <td rowspan="2">US $303 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97122.html">7700T</a> </th> <td>2.9 </td> <td>3.8 </td> <td>35 W </td></tr> <tr> <th rowspan="7">Core i5 </th> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97144.html">7600K</a> </th> <td rowspan="7">4 (4) </td> <td>3.8 </td> <td>4.2 </td> <td rowspan="7">6 MB </td> <td>91 W </td> <td>US $242 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97150.html">7600</a> </th> <td>3.5 </td> <td>4.1 </td> <td>65 W </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97183.html">7600T</a> </th> <td>2.8 </td> <td>3.7 </td> <td rowspan="3">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97123.html">7500</a> </th> <td>3.4 </td> <td>3.8 </td> <td>65 W </td> <td rowspan="2">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97121.html">7500T</a> </th> <td>2.7 </td> <td>3.3 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97147.html">7400</a> </th> <td>3.0 </td> <td>3.5 </td> <td rowspan="2">350–1000 </td> <td>65 W </td> <td rowspan="2">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97184.html">7400T</a> </th> <td>2.4 </td> <td>3.0 </td> <td>35 W </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97527.html">7350K</a> </th> <td rowspan="6">2 (4) </td> <td>4.2 </td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">350–1150 </td> <td rowspan="4">4 MB </td> <td>60 W </td> <td>US $168 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97484.html">7320</a> </th> <td>4.1 </td> <td rowspan="2">51 W </td> <td>US $157 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97458.html">7300</a> </th> <td>4.0 </td> <td rowspan="2">US $147 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97457.html">7300T</a> </th> <td>3.5 </td> <td rowspan="3">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97455.html">7100</a> </th> <td>3.9 </td> <td rowspan="2">3 MB </td> <td>51 W </td> <td rowspan="2">US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97485.html">7100T</a> </th> <td>3.4 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Skylake-X">Skylake-X<span class="anchor" id=""Skylake-X"_(14_nm)"></span><span class="anchor" id="Skylake-X_(14_nm,_7th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=38" title="Edit section: Skylake-X"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the 9th generation refresh, see section <a href="#Skylake-X_(9xxx)">§ Skylake-X (9xxx)</a> below.</div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2066" title="LGA 2066">LGA 2066</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 RAM. Models i7-7820X and above support it up to 2666 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speeds.</li> <li>i7 models provide 28 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>; i9 models provide 44 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>X-suffix, and XE-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo<br />2.0 </th> <th class="unsortable">Turbo<br />3.0 </th></tr> <tr> <th rowspan="5">Core i9 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126699.html">7980XE</a> </th> <td>18 (36) </td> <td>2.6 </td> <td rowspan="2">4.2 </td> <td rowspan="4">4.4 </td> <td>24.75 MB </td> <td rowspan="3">165 W </td> <td rowspan="3"><span data-sort-value="000000002017-09-01-0000" style="white-space:nowrap">September 2017</span> </td> <td>US $1999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126697.html">7960X</a> </th> <td>16 (32) </td> <td>2.8 </td> <td>22 MB </td> <td>US $1699 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126695.html">7940X</a> </th> <td>14 (28) </td> <td>3.1 </td> <td rowspan="4">4.3 </td> <td>19.25 MB </td> <td>US $1399 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126240.html">7920X</a> </th> <td>12 (24) </td> <td>2.9 </td> <td>16.5 MB </td> <td rowspan="4">140 W </td> <td><span data-sort-value="000000002017-08-01-0000" style="white-space:nowrap">August 2017</span> </td> <td>US $1199 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/123613.html">7900X</a> </th> <td>10 (20) </td> <td>3.3 </td> <td rowspan="2">4.5 </td> <td>13.75 MB </td> <td rowspan="4"><span data-sort-value="000000002017-06-01-0000" style="white-space:nowrap">June 2017</span> </td> <td>US $989 </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/123767.html">7820X</a> </th> <td>8 (16) </td> <td>3.6 </td> <td>11 MB </td> <td>US $599 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/123589.html">7800X</a> </th> <td>6 (12) </td> <td>3.5 </td> <td>4.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>8.25 MB </td> <td>US $389 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-X">Kaby Lake-X<span class="anchor" id=""Kaby_Lake-X"_(14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=39" title="Edit section: Kaby Lake-X"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2066" title="LGA 2066">LGA 2066</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>X-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/121499.html">7740X</a> </th> <td>4 (8) </td> <td>4.3 </td> <td>4.5 </td> <td>8 MB </td> <td rowspan="2">112 W </td> <td rowspan="2"><span data-sort-value="000000002017-06-01-0000" style="white-space:nowrap">June 2017</span> </td> <td>US $339 </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/121500.html">7640X</a> </th> <td>4 (4) </td> <td>4.0 </td> <td>4.2 </td> <td>6 MB </td> <td>US $242 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(8th_gen)"><span id="Core_i_.288th_gen.29"></span>Core i (8th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=40" title="Edit section: Core i (8th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-S">Coffee Lake-S<span class="anchor" id=""Coffee_Lake-S"_(14_nm)_(9th_gen_is_Coffee_Lake-R)"></span><span class="anchor" id=""Coffee_Lake-S"_(14_nm)"></span><span class="anchor" id="Coffee_Lake-S"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=41" title="Edit section: Coffee Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the 9th generation refresh, see section <a href="#Coffee_Lake-R">§ Coffee Lake-R</a> below.</div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151-2" class="mw-redirect" title="LGA 1151-2">LGA 1151-2</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> RAM at up to 2400 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed. Models i5 and up support it at up to 2666 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/148263.html">8086K</a> </th> <td rowspan="4">6 (12) </td> <td>4.0 </td> <td>5.0 </td> <td rowspan="15"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="4">350–1200 </td> <td rowspan="4">12 MB </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002018-06-01-0000" style="white-space:nowrap">June 2018</span> </td> <td>US $425 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126684.html">8700K</a> </th> <td>3.7 </td> <td>4.7 </td> <td rowspan="2"><span data-sort-value="000000002017-10-01-0000" style="white-space:nowrap">October 2017</span> </td> <td>US $359 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126686.html">8700</a> </th> <td>3.2 </td> <td>4.6 </td> <td>65 W </td> <td rowspan="2">US $303 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129948.html">8700T</a> </th> <td>2.4 </td> <td>4.0 </td> <td>35 W </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th rowspan="7">Core i5 </th> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126685.html">8600K</a> </th> <td rowspan="7">6 (6) </td> <td>3.6 </td> <td rowspan="2">4.3 </td> <td rowspan="3">350–1150 </td> <td rowspan="7">9 MB </td> <td>95 W </td> <td><span data-sort-value="000000002017-10-01-0000" style="white-space:nowrap">October 2017</span> </td> <td>US $257 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129937.html">8600</a> </th> <td>3.1 </td> <td>65 W </td> <td rowspan="4"><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129938.html">8600T</a> </th> <td>2.3 </td> <td>3.7 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129939.html">8500</a> </th> <td>3.0 </td> <td>4.1 </td> <td rowspan="2">350–1100 </td> <td>65 W </td> <td rowspan="2">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129941.html">8500T</a> </th> <td>2.1 </td> <td>3.5 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126687.html">8400</a> </th> <td>2.8 </td> <td>4.0 </td> <td rowspan="2">350–1050 </td> <td>65 W </td> <td><span data-sort-value="000000002017-10-01-0000" style="white-space:nowrap">October 2017</span> </td> <td rowspan="2">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129940.html">8400T</a> </th> <td>1.7 </td> <td>3.3 </td> <td>35 W </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126689.html">8350K</a> </th> <td rowspan="6">4 (4) </td> <td>4.0 </td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">350–1150 </td> <td rowspan="3">8 MB </td> <td>91 W </td> <td><span data-sort-value="000000002017-10-01-0000" style="white-space:nowrap">October 2017</span> </td> <td>US $168 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129942.html">8300</a> </th> <td>3.7 </td> <td>62 W </td> <td rowspan="2"><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td> <td rowspan="2">US $138 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129943.html">8300T</a> </th> <td>3.2 </td> <td rowspan="2">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/126688.html">8100</a> </th> <td rowspan="2">3.6 </td> <td rowspan="3">6 MB </td> <td rowspan="2">65 W </td> <td><span data-sort-value="000000002017-10-01-0000" style="white-space:nowrap">October 2017</span> </td> <td rowspan="3">US $117 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2">8100F </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/129944.html">8100T</a> </th> <td>3.1 </td> <td>UHD 630 </td> <td>350–1100 </td> <td>35 W </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(9th_gen)"><span id="Core_i_.289th_gen.29"></span>Core i (9th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=42" title="Edit section: Core i (9th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-R">Coffee Lake-R<span class="anchor" id="Coffee_Lake-S_Refresh_(14_nm,_9th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=43" title="Edit section: Coffee Lake-R"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151-2" class="mw-redirect" title="LGA 1151-2">LGA 1151-2</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> RAM at up to 2400 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed. Models i5 and up support it at up to 2666 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9-9900KS has all-core boost clock of 5.0 GHz.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="5">Core i9 </th> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192943.html">9900KS</a> </th> <td rowspan="5">8 (16) </td> <td>4.0 </td> <td rowspan="4">5.0 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">350–1200 </td> <td rowspan="5">16 MB </td> <td>127 W </td> <td><span data-sort-value="000000002019-10-01-0000" style="white-space:nowrap">October 2019</span> </td> <td>US $524 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/186605.html">9900K</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002018-10-01-0000" style="white-space:nowrap">October 2018</span> </td> <td>US $488 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190887.html">9900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td> <td>US $463 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191789.html">9900</a> </th> <td>3.1 </td> <td rowspan="3">UHD 630 </td> <td rowspan="3">350–1200 </td> <td>65 W </td> <td rowspan="2"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td> <td rowspan="2">US $439 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191044.html">9900T</a> </th> <td>2.1 </td> <td>4.4 </td> <td>35 W </td></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/186604.html">9700K</a> </th> <td rowspan="5">8 (8) </td> <td rowspan="2">3.6 </td> <td rowspan="2">4.9 </td> <td rowspan="5">12 MB </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002018-10-01-0000" style="white-space:nowrap">October 2018</span> </td> <td rowspan="2">US $374 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190885.html">9700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191792.html">9700</a> </th> <td rowspan="2">3.0 </td> <td rowspan="2">4.7 </td> <td>UHD 630 </td> <td>350–1200 </td> <td rowspan="2">65 W </td> <td rowspan="3"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td> <td rowspan="3">US $323 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193738.html">9700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191048.html">9700T</a> </th> <td>2.0 </td> <td>4.3 </td> <td rowspan="2">UHD 630 </td> <td>350–1200 </td> <td>35 W </td></tr> <tr> <th rowspan="10">Core i5 </th> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134896.html">9600K</a> </th> <td rowspan="10">6 (6) </td> <td rowspan="2">3.7 </td> <td rowspan="3">4.6 </td> <td>350–1150 </td> <td rowspan="10">9 MB </td> <td rowspan="2">95 W </td> <td><span data-sort-value="000000002018-10-01-0000" style="white-space:nowrap">October 2018</span> </td> <td>US $262 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190884.html">9600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td> <td>US $263 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134900.html">9600</a> </th> <td>3.1 </td> <td rowspan="3">UHD 630 </td> <td rowspan="2">350–1150 </td> <td>65 W </td> <td rowspan="5"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191051.html">9600T</a> </th> <td>2.3 </td> <td>3.9 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134895.html">9500</a> </th> <td rowspan="2">3.0 </td> <td rowspan="2">4.2 </td> <td>350–1100 </td> <td rowspan="2">65 W </td> <td rowspan="3">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190890.html">9500F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191052.html">9500T</a> </th> <td>2.2 </td> <td>3.7 </td> <td rowspan="2">UHD 630 </td> <td>350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134898.html">9400</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">4.1 </td> <td>350–1050 </td> <td rowspan="2">65 W </td> <td rowspan="2"><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td> <td rowspan="3">US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190883.html">9400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134893.html">9400T</a> </th> <td>1.8 </td> <td>3.4 </td> <td rowspan="2">UHD 630 </td> <td>350–1050 </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th rowspan="8">Core i3 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/186606.html">9350K</a> </th> <td rowspan="8">4 (4) </td> <td rowspan="2">4.0 </td> <td rowspan="2">4.6 </td> <td>350–1150 </td> <td rowspan="5">8 MB </td> <td rowspan="2">91 W </td> <td rowspan="2">US $173 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191126.html">9350KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191793.html">9320</a> </th> <td rowspan="2">3.7 </td> <td>4.4 </td> <td rowspan="4">UHD 630 </td> <td rowspan="2">350–1150 </td> <td rowspan="2">62 W </td> <td rowspan="6"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td> <td>US $154 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134886.html">9300</a> </th> <td>4.3 </td> <td rowspan="2">US $143 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134875.html">9300T</a> </th> <td>3.2 </td> <td>3.8 </td> <td rowspan="2">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134870.html">9100</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">4.2 </td> <td rowspan="3">6 MB </td> <td rowspan="2">65 W </td> <td rowspan="3">US $122 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190886.html">9100F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134871.html">9100T</a> </th> <td>3.1 </td> <td>3.7 </td> <td>UHD 630 </td> <td>350–1100 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Skylake-X_(9xxx)"><span id="Skylake-X_.289xxx.29"></span>Skylake-X (9xxx)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=44" title="Edit section: Skylake-X (9xxx)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2066" title="LGA 2066">LGA 2066</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM.</li> <li>All CPU models provide 44 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>X-suffix, and XE-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo<br />2.0 </th> <th class="unsortable">Turbo<br />3.0 </th></tr> <tr> <th rowspan="7">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8">9990XE<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </th> <td>14 (28) </td> <td>4.0 </td> <td>5.0 </td> <td>5.0 </td> <td>19.25 MB </td> <td>255 W </td> <td><span data-sort-value="000000002019-01-01-0000" style="white-space:nowrap">January 2019</span> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189126.html">9980XE</a> </th> <td>18 (36) </td> <td>3.0 </td> <td rowspan="5">4.4 </td> <td rowspan="5">4.5 </td> <td>24.75 MB </td> <td rowspan="7">165 W </td> <td rowspan="6">Q4 2018 </td> <td>US $1979 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189123.html">9960X</a> </th> <td>16 (32) </td> <td>3.1 </td> <td>22 MB </td> <td>US $1684 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189125.html">9940X</a> </th> <td>14 (28) </td> <td>3.3 </td> <td rowspan="3">19.25 MB </td> <td>US $1387 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189127.html">9920X</a> </th> <td>12 (24) </td> <td rowspan="2">3.5 </td> <td>US $1189 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189124.html">9900X</a> </th> <td rowspan="2">10 (20) </td> <td>US $989 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189121.html">9820X</a> </th> <td>3.3 </td> <td>4.1 </td> <td>4.2 </td> <td rowspan="2">16.5 MB </td> <td>US $889 </td></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189122.html">9800X</a> </th> <td>8 (16) </td> <td>3.8 </td> <td>4.4 </td> <td>4.5 </td> <td><span data-sort-value="000000002018-11-01-0000" style="white-space:nowrap">November 2018</span> </td> <td>US $589 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(10th_gen)"><span id="Core_i_.2810th_gen.29"></span>Core i (10th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=45" title="Edit section: Core i (10th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Comet_Lake-S">Comet Lake-S<span class="anchor" id=""Comet_Lake-S"_(14_nm)"></span><span class="anchor" id="Comet_Lake-S"></span><span class="anchor" id="Comet_Lake-S_(14_nm,_10th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=46" title="Edit section: Comet Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the i3- and i5-10xx5 refresh, see section <a href="#Comet_Lake-S_(refresh)">§ Comet Lake-S (refresh)</a> below.</div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> RAM at up to 2666 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a> speed. Models i7 and up support it at up to 2933 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 4-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9 and i7 models support Turbo Boost 3.0, while i5 and i3 only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="7">Core i9 </th> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199332.html">10900K</a> </th> <td rowspan="7">10 (20) </td> <td rowspan="2">3.7 </td> <td rowspan="2">5.2 </td> <td rowspan="2">5.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td>350–1200 </td> <td rowspan="7">20 MB </td> <td rowspan="3">125 W </td> <td rowspan="2"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td> <td>US $488 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199331.html">10900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $472 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/204448.html">10910</a> </th> <td>3.6 </td> <td>5.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">UHD 630 </td> <td rowspan="2">350–1200 </td> <td>Q3 2020 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199328.html">10900</a> </th> <td rowspan="2">2.8 </td> <td rowspan="2">5.1 </td> <td rowspan="2">5.2 </td> <td rowspan="2">65 W </td> <td rowspan="3"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td> <td>US $439 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199329.html">10900F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $422 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199324.html">10900T</a> </th> <td>1.9 </td> <td>4.6 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">UHD 630 </td> <td rowspan="3">350–1200 </td> <td>35 W </td> <td>US $439 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/205904.html">10850K</a> </th> <td>3.6 </td> <td>5.1 </td> <td>5.2 </td> <td rowspan="3">125 W </td> <td><span data-sort-value="000000002020-07-01-0000" style="white-space:nowrap">July 2020</span> </td> <td>US $453 </td></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199335.html">10700K</a> </th> <td rowspan="5">8 (16) </td> <td rowspan="2">3.8 </td> <td rowspan="2">5.1 </td> <td rowspan="20" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="5">16 MB </td> <td rowspan="5"><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td> <td>US $374 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199325.html">10700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $349 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199316.html">10700</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">4.8 </td> <td>UHD 630 </td> <td>350–1200 </td> <td rowspan="2">65 W </td> <td>US $323 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199318.html">10700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $298 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199314.html">10700T</a> </th> <td>2.0 </td> <td>4.5 </td> <td rowspan="2">UHD 630 </td> <td rowspan="2">350–1200 </td> <td>35 W </td> <td>US $325 </td></tr> <tr> <th rowspan="9">Core i5 </th> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199311.html">10600K</a> </th> <td rowspan="9">6 (12) </td> <td rowspan="2">4.1 </td> <td rowspan="3">4.8 </td> <td rowspan="9">12 MB </td> <td rowspan="2">125 W </td> <td rowspan="13"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td> <td>US $262 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199315.html">10600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $237 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199273.html">10600</a> </th> <td>3.3 </td> <td rowspan="5">UHD 630 </td> <td rowspan="2">350–1200 </td> <td>65 W </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199279.html">10600T</a> </th> <td>2.4 </td> <td>4.0 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199277.html">10500</a> </th> <td>3.1 </td> <td>4.5 </td> <td rowspan="2">350–1150 </td> <td>65 W </td> <td rowspan="2">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199275.html">10500T</a> </th> <td>2.3 </td> <td>3.8 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199271.html">10400</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">4.3 </td> <td>350–1100 </td> <td rowspan="2">65 W </td> <td>US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199278.html">10400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $157 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199276.html">10400T</a> </th> <td>2.0 </td> <td>3.6 </td> <td rowspan="5">UHD 630 </td> <td>350–1100 </td> <td>35 W </td> <td>US $182 </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199280.html">10320</a> </th> <td rowspan="6">4 (8) </td> <td>3.8 </td> <td>4.6 </td> <td rowspan="2">350–1150 </td> <td rowspan="3">8 MB </td> <td rowspan="2">65 W </td> <td>US $154 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199281.html">10300</a> </th> <td>3.7 </td> <td>4.4 </td> <td rowspan="2">US $143 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199282.html">10300T</a> </th> <td>3.0 </td> <td>3.9 </td> <td rowspan="2">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199283.html">10100</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">4.3 </td> <td rowspan="3">6 MB </td> <td rowspan="2">65 W </td> <td>US $122 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203473.html">10100F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002020-10-01-0000" style="white-space:nowrap">October 2020</span> </td> <td>US $97 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199284.html">10100T</a> </th> <td>3.0 </td> <td>3.8 </td> <td>UHD 630 </td> <td>350–1100 </td> <td>35 W </td> <td><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td> <td>US $122 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Comet_Lake-S_(refresh)"><span id="Comet_Lake-S_.28refresh.29"></span>Comet Lake-S (refresh)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=47" title="Edit section: Comet Lake-S (refresh)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Released on the same day as the 11th gen Rocket Lake-S desktop processors. </p><p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 4-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>All models support Turbo Boost 2.0.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201891.html">10505</a> </th> <td>6 (12) </td> <td>3.2 </td> <td>4.6 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td>350–1200 </td> <td>12 MB </td> <td rowspan="3">65 W </td> <td rowspan="7"><span data-sort-value="000000002021-03-01-0000" style="white-space:nowrap">March 2021</span> </td> <td>US $192 </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201889.html">10325</a> </th> <td rowspan="6">4 (8) </td> <td>3.9 </td> <td>4.7 </td> <td rowspan="2">350–1150 </td> <td rowspan="3">8 MB </td> <td>US $154 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199281.html">10305</a> </th> <td>3.8 </td> <td>4.5 </td> <td rowspan="2">US $143 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201898.html">10305T</a> </th> <td>3.0 </td> <td>4.0 </td> <td rowspan="2">350–1100 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201894.html">10105</a> </th> <td rowspan="2">3.7 </td> <td rowspan="2">4.4 </td> <td rowspan="3">6 MB </td> <td rowspan="2">65 W </td> <td>US $122 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203474.html">10105F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $97 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201890.html">10105T</a> </th> <td>3.0 </td> <td>3.9 </td> <td>UHD 630 </td> <td>350–1100 </td> <td>35 W </td> <td>US $122 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Cascade_Lake-X_(10xxx)"><span id="Cascade_Lake-X_.2810xxx.29"></span>Cascade Lake-X (10xxx)<span class="anchor" id="Cascade_Lake-X_(14_nm,_enthusiast)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=48" title="Edit section: Cascade Lake-X (10xxx)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_2066" title="LGA 2066">LGA 2066</a>.</li> <li>All the CPUs support quad-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2933 RAM.</li> <li>All CPU models provide 48 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>X-suffix, and XE-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo<br />2.0 </th> <th class="unsortable">Turbo<br />3.0 </th></tr> <tr> <th rowspan="4">Core i9 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198017.html">10980XE</a> </th> <td>18 (36) </td> <td>3.0 </td> <td rowspan="3">4.6 </td> <td rowspan="3">4.8 </td> <td>24.75 MB </td> <td rowspan="4">165 W </td> <td rowspan="4"><span data-sort-value="000000002019-10-01-0000" style="white-space:nowrap">October 2019</span> </td> <td>US $979 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198014.html">10940X</a> </th> <td>14 (28) </td> <td>3.3 </td> <td rowspan="3">19.25 MB </td> <td>US $784 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198012.html">10920X</a> </th> <td>12 (24) </td> <td>3.5 </td> <td>US $689 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198019.html">10900X</a> </th> <td>10 (20) </td> <td>3.7 </td> <td>4.5 </td> <td>4.7 </td> <td>US $590 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(11th_gen)"><span id="Core_i_.2811th_gen.29"></span>Core i (11th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=49" title="Edit section: Core i (11th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Rocket_Lake-S">Rocket Lake-S<span class="anchor" id=""Rocket_Lake-S"_(14_nm)"></span><span class="anchor" id="Rocket_Lake-S_(14_nm,_11th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=50" title="Edit section: Rocket Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM. The Core i9 K/KF processors enable a 1:1 ratio of DRAM to memory controller by default at DDR4-3200, whereas the Core i9 non K/KF and all other CPUs listed below enable a 2:1 ratio of DRAM to memory controller by default at DDR4-3200 and a 1:1 ratio by default at DDR4-2933.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9 and i7 models support Turbo Boost 3.0, while i5 only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th> <th class="unsortable" rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="5">Core i9 </th> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212325.html">11900K</a> </th> <td rowspan="10">8 (16) </td> <td rowspan="2">3.5 </td> <td rowspan="2">5.2 </td> <td rowspan="2">5.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 750</a> </td> <td>350–1300 </td> <td rowspan="10">16 MB </td> <td rowspan="2">125 W </td> <td rowspan="19"><span data-sort-value="000000002021-03-01-0000" style="white-space:nowrap">March 2021</span> </td> <td>US $539 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212321.html">11900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $513 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212252.html">11900</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">5.1 </td> <td rowspan="2">5.2 </td> <td>UHD 750 </td> <td>350–1300 </td> <td rowspan="2">65 W </td> <td>US $439 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212254.html">11900F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $422 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212256.html">11900T</a> </th> <td>1.5 </td> <td>4.9 </td> <td rowspan="15" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">UHD 750 </td> <td rowspan="2">350–1300 </td> <td>35 W </td> <td>US $439 </td></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212047.html">11700K</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">5.0 </td> <td rowspan="2">125 W </td> <td>US $399 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212048.html">11700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $374 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212279.html">11700</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">4.9 </td> <td>UHD 750 </td> <td>350–1300 </td> <td rowspan="2">65 W </td> <td>US $323 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212280.html">11700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $298 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212251.html">11700T</a> </th> <td>1.4 </td> <td>4.6 </td> <td rowspan="2">UHD 750 </td> <td rowspan="2">350–1300 </td> <td>35 W </td> <td>US $323 </td></tr> <tr> <th rowspan="9">Core i5 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212275.html">11600K</a> </th> <td rowspan="9">6 (12) </td> <td rowspan="2">3.9 </td> <td rowspan="2">4.9 </td> <td rowspan="9">12 MB </td> <td rowspan="2">125 W </td> <td>US $262 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212276.html">11600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $237 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212274.html">11600</a> </th> <td>2.8 </td> <td>4.8 </td> <td rowspan="4">UHD 750 </td> <td rowspan="3">350–1300 </td> <td>65 W </td> <td rowspan="2">US $213 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212278.html">11600T</a> </th> <td>1.7 </td> <td>4.1 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212277.html">11500</a> </th> <td>2.7 </td> <td>4.6 </td> <td>65 W </td> <td rowspan="2">US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212272.html">11500T</a> </th> <td>1.5 </td> <td>3.9 </td> <td>350–1200 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212270.html">11400</a> </th> <td rowspan="2">2.6 </td> <td rowspan="2">4.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td>350–1300 </td> <td rowspan="2">65 W </td> <td>US $182 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212271.html">11400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $157 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212273.html">11400T</a> </th> <td>1.3 </td> <td>3.7 </td> <td>UHD 730 </td> <td>350–1200 </td> <td>35 W </td> <td>US $182 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-B">Tiger Lake-B<span class="anchor" id=""Tiger_Lake-B"_(10_nm_SuperFin)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=51" title="Edit section: Tiger Lake-B"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1787 (soldered).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/compare.html?productIds=215570,128915,128916,215569">These CPUs</a> were sold to OEMs only.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i9 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/215570.html">11900KB</a> </th> <td rowspan="2">8 (16) </td> <td>3.3 </td> <td>4.9 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="3">350–1450 </td> <td rowspan="2">24 MB </td> <td rowspan="2">55–65 W </td> <td rowspan="4"><span data-sort-value="000000002021-05-01-0000" style="white-space:nowrap">May 2021</span> </td></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/128915.html">11700B</a> </th> <td>3.2 </td> <td>4.8 </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/128916.html">11500B</a> </th> <td>6 (12) </td> <td>3.3 </td> <td>4.6 </td> <td rowspan="2">12 MB </td> <td rowspan="2">65 W </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/215569.html">11100B</a> </th> <td>4 (8) </td> <td>3.6 </td> <td>4.4 </td> <td>UHD Graphics<br />(16 EU) </td> <td>350–1400 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(12th_gen)"><span id="Core_i_.2812th_gen.29"></span>Core i (12th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=52" title="Edit section: Core i (12th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-S">Alder Lake-S<span class="anchor" id=""Alder_Lake"_(Intel_7)"></span><span class="anchor" id=""Alder_Lake-S"_(Intel_7)"></span><span class="anchor" id="Alder_Lake_(Intel_7,_12th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=53" title="Edit section: Alder Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 RAM.</li> <li>All the CPUs provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores)</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9 and i7 models support Turbo Boost 3.0 on the P-cores, while i5 only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="4">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th> <th class="unsortable" rowspan="3"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="6">Core i9 </th> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/225916.html">12900KS</a> </th> <td rowspan="11">8 (16) </td> <td>3.4 </td> <td>5.3 </td> <td>5.5 </td> <td rowspan="6">8 (8) </td> <td>2.5 </td> <td>4.0 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 770</a> </td> <td rowspan="2">300–1550 </td> <td rowspan="6">30 MB </td> <td>150 W </td> <td rowspan="3">241 W </td> <td><span data-sort-value="000000002022-04-01-0000" style="white-space:nowrap">April 2022</span> </td> <td>US $739 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134599.html">12900K</a> </th> <td rowspan="2">3.2 </td> <td rowspan="2">5.2 </td> <td rowspan="25" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">2.4 </td> <td rowspan="2">3.9 </td> <td rowspan="2">125 W </td> <td rowspan="2"><span data-sort-value="000000002021-11-01-0000" style="white-space:nowrap">November 2021</span> </td> <td>US $589 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134600.html">12900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $564 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134597.html">12900</a> </th> <td rowspan="2">2.4 </td> <td rowspan="2">5.1 </td> <td rowspan="2">1.8 </td> <td rowspan="2">3.8 </td> <td>UHD 770 </td> <td>300–1550 </td> <td rowspan="2">65 W </td> <td rowspan="2">202 W </td> <td rowspan="3"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td> <td>US $489 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134598.html">12900F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $464 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134601.html">12900T</a> </th> <td>1.4 </td> <td>4.9 </td> <td>1.0 </td> <td>3.6 </td> <td rowspan="2">UHD 770 </td> <td>300–1550 </td> <td>35 W </td> <td>106 W </td> <td>US $489 </td></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134594.html">12700K</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">5.0 </td> <td rowspan="7">4 (4) </td> <td rowspan="2">2.7 </td> <td rowspan="2">3.8 </td> <td>300–1500 </td> <td rowspan="5">25 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">190 W </td> <td rowspan="2"><span data-sort-value="000000002021-11-01-0000" style="white-space:nowrap">November 2021</span> </td> <td>US $409 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134595.html">12700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $384 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134591.html">12700</a> </th> <td rowspan="2">2.1 </td> <td rowspan="2">4.9 </td> <td rowspan="2">1.6 </td> <td rowspan="2">3.6 </td> <td>UHD 770 </td> <td>300–1500 </td> <td rowspan="2">65 W </td> <td rowspan="2">180 W </td> <td rowspan="3"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td> <td>US $339 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134592.html">12700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $314 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134596.html">12700T</a> </th> <td>1.4 </td> <td>4.7 </td> <td>1.0 </td> <td>3.4 </td> <td rowspan="2">UHD 770 </td> <td>300–1500 </td> <td>35 W </td> <td>106 W </td> <td>US $339 </td></tr> <tr> <th rowspan="10">Core i5 </th> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134589.html">12600K</a> </th> <td rowspan="10">6 (12) </td> <td rowspan="2">3.7 </td> <td rowspan="2">4.9 </td> <td rowspan="2">2.8 </td> <td rowspan="2">3.6 </td> <td>300–1450 </td> <td rowspan="2">20 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">150 W </td> <td rowspan="2"><span data-sort-value="000000002021-11-01-0000" style="white-space:nowrap">November 2021</span> </td> <td>US $289 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134590.html">12600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $264 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96149.html">12600</a> </th> <td>3.3 </td> <td>4.8 </td> <td colspan="3" rowspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">UHD 770 </td> <td rowspan="4">300–1450 </td> <td rowspan="4">18 MB </td> <td>65 W </td> <td>117 W </td> <td rowspan="4"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td> <td rowspan="2">US $223 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96150.html">12600T</a> </th> <td>2.1 </td> <td rowspan="2">4.6 </td> <td>35 W </td> <td>74 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96144.html">12500</a> </th> <td>3.0 </td> <td>65 W </td> <td>117 W </td> <td rowspan="2">US $202 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96140.html">12500T</a> </th> <td>2.0 </td> <td>4.4 </td> <td>35 W </td> <td>74 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9">12490F<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </th> <td>3.0 </td> <td>4.6 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>20 MB </td> <td rowspan="3">65 W </td> <td rowspan="3">117 W </td> <td><span data-sort-value="000000002022-02-01-0000" style="white-space:nowrap">February 2022</span> </td> <td>CN ¥1599 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134587.html">12400</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">4.4 </td> <td>UHD 730 </td> <td>300–1450 </td> <td rowspan="3">18 MB </td> <td rowspan="8"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td> <td>US $202 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134587.html">12400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $192 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223094.html">12400T</a> </th> <td>1.8 </td> <td>4.2 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td rowspan="3">350–1450 </td> <td>35 W </td> <td>74 W </td> <td>US $202 </td></tr> <tr> <th rowspan="5">Core i3 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223095.html">12300</a> </th> <td rowspan="5">4 (8) </td> <td>3.5 </td> <td>4.4 </td> <td rowspan="5">12 MB </td> <td>60 W </td> <td>89 W </td> <td rowspan="2">US $143 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223096.html">12300T</a> </th> <td>2.3 </td> <td>4.2 </td> <td>35 W </td> <td>69 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134584.html">12100</a> </th> <td rowspan="2">3.3 </td> <td rowspan="2">4.3 </td> <td>300–1400 </td> <td>60 W </td> <td rowspan="2">89 W </td> <td>US $122 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132223.html">12100F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>58 W </td> <td>US $97 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223097.html">12100T</a> </th> <td>2.2 </td> <td>4.1 </td> <td>UHD 730 </td> <td>300–1400 </td> <td>35 W </td> <td>69 W </td> <td>US $122 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(13th_gen)"><span id="Core_i_.2813th_gen.29"></span>Core i (13th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=54" title="Edit section: Core i (13th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-S">Raptor Lake-S<span class="anchor" id=""Raptor_Lake"_(Intel_7)"></span><span class="anchor" id=""Raptor_Lake-S"_(Intel_7)"></span><span class="anchor" id="Raptor_Lake_(Intel_7,_13th/14th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=55" title="Edit section: Raptor Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the 14th generation refresh, see section <a href="#Raptor_Lake-S_Refresh">§ Raptor Lake-S Refresh</a> below.</div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 RAM.</li> <li>All the CPUs provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core on i5-13600K/KF and above models, 1.25 MB per core on 13600 and below models.</li> <li>E-cores: 4 MB per E-core cluster on i5-13600K/KF and above models, 2 MB per cluster on 13600 and below models (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9 and i7 models support Turbo Boost 3.0 on the P-cores, while i5 only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="4">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th> <th class="unsortable" rowspan="3"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="6">Core i9 </th> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232167.html">13900KS</a> </th> <td rowspan="12">8 (16) </td> <td>3.2 </td> <td>5.8 </td> <td>6.0 </td> <td rowspan="6">16 (16) </td> <td>2.4 </td> <td rowspan="3">4.3 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 770</a> </td> <td rowspan="2">300–1650 </td> <td rowspan="6">36 MB </td> <td>150 W </td> <td rowspan="3">253 W </td> <td><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td> <td>US $689 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230496.html">13900K</a> </th> <td rowspan="2">3.0 </td> <td rowspan="2">5.7 </td> <td rowspan="2">5.8 </td> <td rowspan="2">2.2 </td> <td rowspan="2">125 W </td> <td rowspan="2"><span data-sort-value="000000002022-10-01-0000" style="white-space:nowrap">October 2022</span> </td> <td>US $589 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230497.html">13900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $564 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230499.html">13900</a> </th> <td rowspan="2">2.0 </td> <td rowspan="2">5.5 </td> <td rowspan="2">5.6 </td> <td rowspan="2">1.5 </td> <td rowspan="2">4.2 </td> <td>UHD 770 </td> <td>300–1650 </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td> <td rowspan="3"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td> <td>US $549 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230502.html">13900F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $524 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230498.html">13900T</a> </th> <td>1.1 </td> <td>5.3 </td> <td rowspan="20" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>0.8 </td> <td>3.9 </td> <td>UHD 770 </td> <td>300–1650 </td> <td>35 W </td> <td>106 W </td> <td>US $549 </td></tr> <tr> <th rowspan="6">Core i7 </th> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232174.html">13790F</a> </th> <td>2.1 </td> <td>5.2 </td> <td rowspan="12">8 (8) </td> <td>1.5 </td> <td>4.1 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>33 MB </td> <td>65 W </td> <td>219 W </td> <td><span data-sort-value="000000002023-02-01-0000" style="white-space:nowrap">February 2023</span> </td> <td>CN ¥2999 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230500.html">13700K</a> </th> <td rowspan="2">3.4 </td> <td rowspan="2">5.4 </td> <td rowspan="2">2.5 </td> <td rowspan="2">4.2 </td> <td>UHD 770 </td> <td>300–1600 </td> <td rowspan="5">30 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">253 W </td> <td rowspan="2"><span data-sort-value="000000002022-10-01-0000" style="white-space:nowrap">October 2022</span> </td> <td>US $409 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230489.html">13700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">US $384 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230490.html">13700</a> </th> <td rowspan="2">2.1 </td> <td rowspan="2">5.2 </td> <td rowspan="2">1.5 </td> <td rowspan="2">4.1 </td> <td>UHD 770 </td> <td>300–1600 </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td> <td rowspan="3"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230491.html">13700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $359 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230492.html">13700T</a> </th> <td>1.4 </td> <td>4.9 </td> <td>1.0 </td> <td>3.6 </td> <td rowspan="2">UHD 770 </td> <td>300–1600 </td> <td>35 W </td> <td>106 W </td> <td>US $384 </td></tr> <tr> <th rowspan="10">Core i5 </th> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230493.html">13600K</a> </th> <td rowspan="10">6 (12) </td> <td rowspan="2">3.5 </td> <td rowspan="2">5.1 </td> <td rowspan="2">2.6 </td> <td rowspan="2">3.9 </td> <td>300–1500 </td> <td rowspan="7">24 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">181 W </td> <td rowspan="2"><span data-sort-value="000000002022-10-01-0000" style="white-space:nowrap">October 2022</span> </td> <td>US $319 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230494.html">13600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $294 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230574.html">13600</a> </th> <td>2.7 </td> <td>5.0 </td> <td>2.0 </td> <td>3.7 </td> <td rowspan="4">UHD 770 </td> <td rowspan="4">300–1550 </td> <td>65 W </td> <td>154 W </td> <td rowspan="4"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td> <td rowspan="2">US $255 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230573.html">13600T</a> </th> <td>1.8 </td> <td rowspan="2">4.8 </td> <td>1.3 </td> <td>3.4 </td> <td>35 W </td> <td>92 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230580.html">13500</a> </th> <td>2.5 </td> <td>1.8 </td> <td>3.5 </td> <td>65 W </td> <td>154 W </td> <td rowspan="2">US $232 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230578.html">13500T</a> </th> <td>1.6 </td> <td>4.6 </td> <td>1.2 </td> <td>3.2 </td> <td>35 W </td> <td>92 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232140.html">13490F</a> </th> <td rowspan="3">2.5 </td> <td>4.8 </td> <td rowspan="4">4 (4) </td> <td rowspan="3">1.8 </td> <td>3.5 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>65 W </td> <td>148 W </td> <td><span data-sort-value="000000002023-02-01-0000" style="white-space:nowrap">February 2023</span> </td> <td>CN ¥1599 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230495.html">13400</a> </th> <td rowspan="2">4.6 </td> <td rowspan="2">3.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td>300–1550 </td> <td rowspan="3">20 MB </td> <td rowspan="2">65 W </td> <td>154 W </td> <td rowspan="6"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td> <td>US $221 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230501.html">13400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>148 W </td> <td>US $196 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/230577.html">13400T</a> </th> <td>1.3 </td> <td>4.4 </td> <td>1.0 </td> <td>3.0 </td> <td rowspan="2">UHD 730 </td> <td>300–1550 </td> <td>35 W </td> <td>82 W </td> <td>US $221 </td></tr> <tr> <th rowspan="3">Core i3 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230575.html">13100</a> </th> <td rowspan="3">4 (8) </td> <td rowspan="2">3.4 </td> <td rowspan="2">4.5 </td> <td colspan="3" rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>300–1500 </td> <td rowspan="3">12 MB </td> <td rowspan="2">60 W </td> <td rowspan="2">89 W </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230576.html">13100F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $109 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230579.html">13100T</a> </th> <td>2.5 </td> <td>4.2 </td> <td>UHD 730 </td> <td>300–1500 </td> <td>35 W </td> <td>69 W </td> <td>US $134 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(14th_gen)"><span id="Core_i_.2814th_gen.29"></span>Core i (14th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=56" title="Edit section: Core i (14th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-S_Refresh">Raptor Lake-S Refresh</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=57" title="Edit section: Raptor Lake-S Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 RAM.</li> <li>All the CPUs provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core on i5-14600/T/K/KF and above models, 1.25 MB per core on 14500 and below models.</li> <li>E-cores: 4 MB per E-core cluster on i5-14600/T/K/KF and above models, 2 MB per cluster on 14500 and below models (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>i9 and i7 models support Turbo Boost 3.0 on the P-cores, while i5 only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="4">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th> <th class="unsortable" rowspan="3"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="6">Core i9 </th> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237504.html">14900KS</a> </th> <td rowspan="12">8 (16) </td> <td rowspan="3">3.2 </td> <td>5.9 </td> <td>6.2 </td> <td rowspan="6">16 (16) </td> <td rowspan="3">2.4 </td> <td>4.5 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 770</a> </td> <td rowspan="2">300–1650 </td> <td rowspan="7">36 MB </td> <td>150 W </td> <td rowspan="3">253 W </td> <td><span data-sort-value="000000002024-03-01-0000" style="white-space:nowrap">March 2024</span> </td> <td>US $689 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236773.html">14900K</a> </th> <td rowspan="2">5.8 </td> <td rowspan="2">6.0 </td> <td rowspan="2">4.4 </td> <td rowspan="2">125 W </td> <td rowspan="2"><span data-sort-value="000000002023-10-01-0000" style="white-space:nowrap">October 2023</span> </td> <td>US $589 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236787.html">14900KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $564 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236793.html">14900</a> </th> <td rowspan="2">2.0 </td> <td rowspan="2">5.6 </td> <td rowspan="2">5.8 </td> <td rowspan="2">1.5 </td> <td rowspan="2">4.3 </td> <td>UHD 770 </td> <td>300–1650 </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td> <td rowspan="4"><span data-sort-value="000000002024-01-01-0000" style="white-space:nowrap">January 2024</span> </td> <td>US $549 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236853.html">14900F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $524 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236791.html">14900T</a> </th> <td>1.1 </td> <td>5.5 </td> <td rowspan="20" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>0.9 </td> <td>3.7 </td> <td>UHD 770 </td> <td>300–1650 </td> <td>35 W </td> <td>106 W </td> <td>US $549 </td></tr> <tr> <th rowspan="6">Core i7 </th> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236779.html">14790F</a> </th> <td>2.1 </td> <td>5.4 </td> <td>8 (8) </td> <td>1.5 </td> <td>4.2 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>65 W </td> <td>219 W </td> <td>China only </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236783.html">14700K</a> </th> <td rowspan="2">3.4 </td> <td rowspan="2">5.6 </td> <td rowspan="5">12 (12) </td> <td rowspan="2">2.5 </td> <td rowspan="2">4.3 </td> <td>UHD 770 </td> <td>300–1600 </td> <td rowspan="5">33 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">253 W </td> <td rowspan="2"><span data-sort-value="000000002023-10-01-0000" style="white-space:nowrap">October 2023</span> </td> <td>US $409 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236789.html">14700KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">US $384 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236781.html">14700</a> </th> <td rowspan="2">2.1 </td> <td rowspan="2">5.4 </td> <td rowspan="2">1.5 </td> <td rowspan="2">4.2 </td> <td>UHD 770 </td> <td>300–1600 </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td> <td rowspan="3"><span data-sort-value="000000002024-01-01-0000" style="white-space:nowrap">January 2024</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236854.html">14700F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $359 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236794.html">14700T</a> </th> <td>1.3 </td> <td>5.2 </td> <td>0.9 </td> <td>3.7 </td> <td rowspan="2">UHD 770 </td> <td>300–1600 </td> <td>35 W </td> <td>106 W </td> <td>US $384 </td></tr> <tr> <th rowspan="10">Core i5 </th> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236799.html">14600K</a> </th> <td rowspan="10">6 (12) </td> <td rowspan="2">3.5 </td> <td rowspan="2">5.3 </td> <td rowspan="6">8 (8) </td> <td rowspan="2">2.6 </td> <td rowspan="2">4.0 </td> <td>300–1550 </td> <td rowspan="7">24 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">181 W </td> <td rowspan="2"><span data-sort-value="000000002023-10-01-0000" style="white-space:nowrap">October 2023</span> </td> <td>US $319 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236778.html">14600KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $294 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236845.html">14600</a> </th> <td>2.7 </td> <td>5.2 </td> <td>2.0 </td> <td>3.9 </td> <td rowspan="4">UHD 770 </td> <td rowspan="4">300–1550 </td> <td>65 W </td> <td>154 W </td> <td rowspan="11"><span data-sort-value="000000002024-01-01-0000" style="white-space:nowrap">January 2024</span> </td> <td rowspan="2">US $255 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236782.html">14600T</a> </th> <td>1.8 </td> <td>5.1 </td> <td>1.3 </td> <td>3.6 </td> <td>35 W </td> <td>92 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236784.html">14500</a> </th> <td>2.6 </td> <td>5.0 </td> <td>1.9 </td> <td>3.7 </td> <td>65 W </td> <td>154 W </td> <td rowspan="2">US $232 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236780.html">14500T</a> </th> <td>1.7 </td> <td>4.8 </td> <td>1.2 </td> <td>3.4 </td> <td>35 W </td> <td>92 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236792.html">14490F</a> </th> <td>2.8 </td> <td>4.9 </td> <td rowspan="4">4 (4) </td> <td>2.1 </td> <td>3.7 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">65 W </td> <td rowspan="3">148 W </td> <td>China only </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236788.html">14400</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">4.7 </td> <td rowspan="2">1.8 </td> <td rowspan="2">3.5 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td>300–1550 </td> <td rowspan="3">20 MB </td> <td>US $221 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236777.html">14400F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $196 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236790.html">14400T</a> </th> <td>1.5 </td> <td>4.5 </td> <td>1.1 </td> <td>3.2 </td> <td rowspan="2">UHD 730 </td> <td>300–1550 </td> <td>35 W </td> <td>82 W </td> <td>US $221 </td></tr> <tr> <th rowspan="3">Core i3 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236774.html">14100</a> </th> <td rowspan="3">4 (8) </td> <td rowspan="2">3.5 </td> <td rowspan="2">4.7 </td> <td colspan="3" rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>300–1500 </td> <td rowspan="3">12 MB </td> <td rowspan="2">60 W </td> <td rowspan="2">110 W </td> <td>US $134 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236786.html">14100F</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $109 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236775.html">14100T</a> </th> <td>2.7 </td> <td>4.4 </td> <td>UHD 730 </td> <td>300–500 </td> <td>35 W </td> <td>69 W </td> <td>US $134 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_Ultra_(Series_2)"><span id="Core_Ultra_.28Series_2.29"></span>Core Ultra (Series 2)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=58" title="Edit section: Core Ultra (Series 2)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Arrow_Lake-S">Arrow Lake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=59" title="Edit section: Arrow Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1851" title="LGA 1851">LGA 1851</a>.</li> <li>All the CPUs support up to dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 (UDIMM) or DDR5-6400 (<a href="/wiki/CUDIMM" class="mw-redirect" title="CUDIMM">CUDIMM</a>) RAM.<sup id="cite_ref-tomshardware-cudimm-memory-needed-for-faster-base-spec_22-0" class="reference"><a href="#cite_note-tomshardware-cudimm-memory-needed-for-faster-base-spec-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup></li> <li>All the CPUs provide 20 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 112 KB (48 KB (12-Way) data + 64 KB (16-Way) instructions) per core.</li> <li>E-cores: 96 KB (32 KB (8-Way) data + 64 KB (16-Way) instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 3 MB (12-Way) per core.</li> <li>E-cores: 4 MB (16-Way) per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: Compute Tile (Contains the CPU cores) <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s <a href="/wiki/3_nm_process" title="3 nm process">N3B</a> node.</li> <li>K-suffix processors have an unlocked multiplier and can be overclocked.</li> <li>Core Ultra 9 and Core Ultra 7 models support Turbo Boost 3.0 on the P-cores, while Core Ultra 5 models only support Turbo Boost 2.0. The turbo clock speeds shown are of the highest turbo boost version supported by the processor.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="4">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th> <th class="unsortable" rowspan="3"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="1">Core Ultra 9 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/241060/intel-core-ultra-9-processor-285k-36m-cache-up-to-5-70-ghz.html">285K</a> </th> <td rowspan="3">8 (8) </td> <td>3.7 </td> <td>5.6 </td> <td>5.7 </td> <td>16 (16) </td> <td>3.2 </td> <td rowspan="5">4.6 </td> <td rowspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Graphics</a><br />(4 Xe-cores) </td> <td rowspan="2">300–2000 </td> <td>36 MB </td> <td rowspan="5">125 W </td> <td rowspan="3">250 W </td> <td rowspan="5"><span data-sort-value="000000002024-10-01-0000" style="white-space:nowrap">October 2024</span> </td> <td>US $589 </td></tr> <tr> <th rowspan="2">Core Ultra 7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/241063/intel-core-ultra-7-processor-265k-30m-cache-up-to-5-50-ghz.html">265K</a> </th> <td rowspan="2">3.9 </td> <td rowspan="2">5.5 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">12 (12) </td> <td rowspan="2">3.3 </td> <td rowspan="2">30 MB </td> <td>US $394 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/241062/intel-core-ultra-7-processor-265kf-30m-cache-up-to-5-50-ghz.html">265KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $379 </td></tr> <tr> <th rowspan="2">Core Ultra 5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/241067/intel-core-ultra-5-processor-245k-24m-cache-up-to-5-20-ghz.html">245K</a> </th> <td rowspan="2">6 (6) </td> <td rowspan="2">4.2 </td> <td rowspan="2">5.2 </td> <td rowspan="2">8 (8) </td> <td rowspan="2">3.6 </td> <td>Intel Graphics<br />(4 Xe-cores) </td> <td>300–1900 </td> <td rowspan="2">24 MB </td> <td rowspan="2">159 W </td> <td>US $309 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/241066/intel-core-ultra-5-processor-245kf-24m-cache-up-to-5-20-ghz.html">245KF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>US $294 </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Mobile_processors">Mobile processors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=60" title="Edit section: Mobile processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1212047051"><table class="release-timeline wikitable"><caption>Release timeline<div class="rt-subtitle"><b>Mobile processors</b></div></caption><tbody><tr><th scope="row" style="border-right:1.4em solid yellow">2009</th><td><a href="#Core_i_(1st_gen)_2">Nehalem microarchitecture (1st generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2010</th><td><a href="#Arrandale">Westmere microarchitecture (1st generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2011</th><td><a href="#Core_i_(2nd_gen)_2">Sandy Bridge microarchitecture (2nd generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2012</th><td><a href="#Core_i_(3rd_gen)_2">Ivy Bridge microarchitecture (3rd generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2013</th><td><a href="#Core_i_(4th_gen)_2">Haswell microarchitecture (4th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid gold">2014</th></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid yellow">2015</th><td class="rt-first"><a href="#Core_i_(5th_gen)_2">Broadwell microarchitecture (5th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(6th_gen)_2">Skylake microarchitecture (6th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid gold">2016</th></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2017</th><td><a href="#Core_i_(7th_gen)_2">Kaby Lake microarchitecture (7th/8th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2018</th><td><a href="#Core_i_(8th_gen)_2">Coffee Lake microarchitecture (8th generation)</a></td></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid yellow">2019</th><td class="rt-first"><a href="#Core_i_(10th_gen)_2">Comet Lake microarchitecture (10th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(10th_gen)_2">Ice Lake (10th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2020</th><td><a href="#Core_i_(11th_gen)_2">Tiger Lake (11th generation)</a></td></tr><tr><th scope="row" style="border-right:1.4em solid gold">2021</th></tr><tr><th scope="row" style="border-right:1.4em solid yellow">2022</th><td><a href="#Core_i_(12th_gen)_2">Alder Lake (12th generation)</a></td></tr><tr><th scope="row" rowspan="2" style="border-right:1.4em solid yellow">2023</th><td class="rt-first"><a href="#Core_i_(13th_gen)_2">Raptor Lake (13th generation)</a></td></tr><tr><td class="rt-last"><a href="#Core_i_(14th_gen)_2">Raptor Lake (14th generation)</a></td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core">Core</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=61" title="Edit section: Core"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Yonah">Yonah<span class="anchor" id=""Yonah""></span><span class="anchor" id=""Yonah"_(65_nm)"></span><span class="anchor" id=""Yonah"_(low-voltage,_65_nm)"></span><span class="anchor" id=""Yonah"_(ultra-low-voltage,_65_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=62" title="Edit section: Yonah"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah (microprocessor)</a></div> <p><br /> </p> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th scope="row">Model </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) <p><br /> </p><p><br /> </p> </th></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_U1300"></span><span class="anchor" id="ark27246"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27246.html">Core Solo U1300</a> </th> <td>1.07 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>8× </td> <td>0.95–1.05 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a></li></ul> </div> </td> <td style="text-align:right;">April 2006 </td> <td>$241 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_U1400"></span><span class="anchor" id="ark27247"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27247.html">Core Solo U1400</a> </th> <td>1.2 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>9× </td> <td>0.95–1.05 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td>Socket 479/FC-μBGA </td> <td style="text-align:right;">April 2006 </td> <td>$262 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_U1500"></span><span class="anchor" id="ark28022"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/28022.html">Core Solo U1500</a> </th> <td>1.33 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>10× </td> <td>0.85–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td>Socket 479/FC-μBGA </td> <td style="text-align:right;">January 2007 </td> <td>$262 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_U2400"></span><span class="anchor" id="ark27239"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27239.html">Core Duo U2400</a> </th> <td>1.07 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>8× </td> <td>0.8–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">9 W </div> </td> <td>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a> </td> <td style="text-align:right;">June 2006 </td> <td>$262 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_U2500"></span><span class="anchor" id="ark27240"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27240.html">Core Duo U2500</a> </th> <td>1.2 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>9× </td> <td>0.8–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">9 W </div> </td> <td>Socket 479/FC-μBGA </td> <td style="text-align:right;">June 2006 </td> <td>$289 <p><br /> </p><p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_L2300"></span><span class="anchor" id="ark27228"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27228.html">Core Duo L2300</a> </th> <td>1.5 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>667 MT/s </td> <td>9× </td> <td>0.762–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">15 W </div> </td> <td>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a> </td> <td style="text-align:right;">January 2006 </td> <td>$284 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_L2400"></span><span class="anchor" id="ark27229"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27229.html">Core Duo L2400</a> </th> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.762–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">15 W </div> </td> <td>Socket 479/FC-μBGA </td> <td style="text-align:right;">January 2006 </td> <td>$316 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_L2500"></span><span class="anchor" id="ark27230"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27230.html">Core Duo L2500</a> </th> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.762–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">15 W </div> </td> <td>Socket 479/FC-μBGA </td> <td style="text-align:right;">September 2006 </td> <td>$316 <p><br /> </p><p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1200"></span>Core Solo T1200 </th> <td>1.5 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>667 MT/s </td> <td>9× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">27 W </div> </td> <td><a href="/wiki/Socket_M" title="Socket M">Socket M</a> </td> <td style="text-align:right;">July 2006 </td> <td> <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1250"></span><span class="anchor" id="ark37246"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37246.html">Core Solo T1250</a> </th> <td>1.73 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>13× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td>Socket M </td> <td style="text-align:right;"> </td> <td> <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1300"></span><span class="anchor" id="ark27242"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27242.html">Core Solo T1300</a> </th> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">27 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a></li> <li>Socket 479/FC-μBGA</li> <li>Socket M</li> <li>Socket M</li></ul> </div> </td> <td style="text-align:right;">January 2006 </td> <td>$209 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1350"></span><span class="anchor" id="ark27243"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27243.html">Core Solo T1350</a> </th> <td>1.87 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>14× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td>Socket M </td> <td style="text-align:right;">July 2006 </td> <td> <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1400"></span><span class="anchor" id="ark27242"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27242.html">Core Solo T1400</a> </th> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">27 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket 479/FC-μBGA</li> <li>Socket 479/FC-μBGA</li> <li>Socket M</li> <li>Socket M</li></ul> </div> </td> <td style="text-align:right;">May 2006 </td> <td>$209 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Solo_T1500"></span>Core Solo T1500 </th> <td>2 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>12× </td> <td>0.7625–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">27 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket 479/FC-μBGA</li> <li>Socket M</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td> <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2050"></span><span class="anchor" id="ark27231"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27231.html">Core Duo T2050</a> </th> <td>1.6 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>12× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><a href="/wiki/Socket_M" title="Socket M">Socket M</a> </td> <td style="text-align:right;">May 2006 </td> <td>$140 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2250"></span><span class="anchor" id="ark27232"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27232.html">Core Duo T2250</a> </th> <td>1.73 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>13× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td>Socket M </td> <td style="text-align:right;">May 2006 </td> <td>OEM <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2300"></span><span class="anchor" id="ark27233"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27233.html">Core Duo T2300</a> </th> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket M</li> <li>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a></li> <li>Socket 479/<a href="/wiki/BGA2" class="mw-redirect" title="BGA2">FC-μBGA</a></li></ul> </div> </td> <td style="text-align:right;">January 2006 </td> <td>$241 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2300E"></span><span class="anchor" id="ark27234"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27234.html">Core Duo T2300E</a> </th> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket M</li> <li>μFCBGA-479</li> <li>μFCBGA-479</li></ul> </div> </td> <td style="text-align:right;">May 2006 </td> <td>$209 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2350"></span><span class="anchor" id="ark29751"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29751.html">Core Duo T2350</a> </th> <td>1.87 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>14× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td>Socket M </td> <td style="text-align:right;"> </td> <td>OEM <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2400"></span><span class="anchor" id="ark27235"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27235.html">Core Duo T2400</a> </th> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;"> <ul><li>31 W</li> <li>31 W</li> <li>27 W</li> <li>27 W</li></ul> </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket M</li> <li>Socket 479/FC-μBGA</li> <li>Socket 479/FC-μBGA</li></ul> </div> </td> <td style="text-align:right;">January 2006 </td> <td>$294 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2450"></span><span class="anchor" id="ark29752"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29752.html">Core Duo T2450</a> </th> <td>2 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>15× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td>Socket M </td> <td style="text-align:right;"> </td> <td>OEM <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2500"></span><span class="anchor" id="ark27236"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27236.html">Core Duo T2500</a> </th> <td>2 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>12× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket M</li> <li>Socket 479/FC-μBGA</li> <li>Socket 479/FC-μBGA</li></ul> </div> </td> <td style="text-align:right;">January 2006 </td> <td>$423 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2600"></span><span class="anchor" id="ark27237"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27237.html">Core Duo T2600</a> </th> <td>2.17 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>13× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket M</li> <li>Socket 479/FC-μBGA</li> <li>Socket 479/FC-μBGA</li></ul> </div> </td> <td style="text-align:right;">January 2006 </td> <td>$637 <p><br /> </p> </td></tr> <tr> <th scope="row"><span class="anchor" id="Core_Duo_T2700"></span><span class="anchor" id="ark27238"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27238.html">Core Duo T2700</a> </th> <td>2.33 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>14× </td> <td>0.762–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">31 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li> <li>Socket 479/FC-μBGA</li></ul> </div> </td> <td style="text-align:right;">June 2006 </td> <td>$637 <p><br /> </p> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_2_2">Core 2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=63" title="Edit section: Core 2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Laptop-intel-core2duo-t5500.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/220px-Laptop-intel-core2duo-t5500.jpg" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/330px-Laptop-intel-core2duo-t5500.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/440px-Laptop-intel-core2duo-t5500.jpg 2x" data-file-width="1536" data-file-height="2048" /></a><figcaption>Inside of old Sony VAIO laptop (VGN-C140G)</figcaption></figure> <div class="mw-heading mw-heading4"><h4 id=""Merom-L"_(65_nm)"><span id=".22Merom-L.22_.2865_nm.29"></span>"Merom-L" (65 nm) <span class="anchor" id=""Merom-L"_(ultra-low-voltage,_65_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=64" title="Edit section: "Merom-L" (65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 81 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">A1</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td align="left" colspan="12" style="background:#127cc1;color: white"><b>ultra-low voltage</b> </td></tr> <tr> <td><span class="anchor" id="Core_2_Solo_ULV_U2100"></span><span class="anchor" id="ark31789"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31789.html">Core 2 Solo ULV U2100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAGM (A1)</li></ul> </div> </td> <td>1 </td> <td>1.07 GHz </td> <td>1 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>8× </td> <td>0.86–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td><a href="/wiki/Micro-FCBGA" class="mw-redirect" title="Micro-FCBGA">Micro-FCBGA</a> </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0041M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Solo_ULV_U2200"></span><span class="anchor" id="ark31790"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31790.html">Core 2 Solo ULV U2200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAGL (A1)</li></ul> </div> </td> <td>1 </td> <td>1.2 GHz </td> <td>1 MB </td> <td>533 MT/s </td> <td>9× </td> <td>0.86–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td>Micro-FCBGA </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0091M</li></ul> </div> </td> <td>$262 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Merom",_"Merom-2M"_(standard-voltage,_65_nm)"><span id=".22Merom.22.2C_.22Merom-2M.22_.28standard-voltage.2C_65_nm.29"></span>"Merom", "Merom-2M" (standard-voltage, 65 nm) <span class="anchor" id=""Merom-2M"_(standard-voltage,_65_nm)"></span><span class="anchor" id=""Merom"_(standard-voltage,_65_nm)"></span><span class="anchor" id="T7600"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=65" title="Edit section: "Merom", "Merom-2M" (standard-voltage, 65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2)</i></li> <li>Model T7600G features an unlocked clock multiplier. Only sold OEM in the <a href="/wiki/Dell_XPS" title="Dell XPS">Dell XPS</a> M1710.</li> <li><i><a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></i>: Supported by T5500 (L2), T5600 and all T7xxx</li> <li><i>Intel Dynamic Front Side Bus Frequency Switching</i>: Supported by <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">E1, G0, G2, M0 Steppings</a></li> <li>Socket P processors can throttle the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) anywhere between 400 and 800 MT/s as needed.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup> (Merom), 111 mm<sup>2</sup> (Merom-2M)</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B2, E1, G0, G2</a> (Merom), <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">L2, M0</a> (Merom-2M)</li> <li>All models of stepping B2 released in July 2006, stepping L2 released in January 2007.</li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5200"></span><span class="anchor" id="ark27252"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27252.html">Core 2 Duo T5200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9VP (B2)</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><a href="/wiki/Socket_M" title="Socket M">Socket M</a> </td> <td style="text-align:right;">October 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GE0252M</li></ul> </div> </td> <td><a href="/wiki/Original_equipment_manufacturer" title="Original equipment manufacturer">OEM</a> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5250"></span><span class="anchor" id="ark30786"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30786.html">Core 2 Duo T5250</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA9S (M0)</li></ul> </div> </td> <td>2 </td> <td>1.5 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>9× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">Q2 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0212M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5270"></span><span class="anchor" id="ark33096"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33096.html">Core 2 Duo T5270</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLALK (M0)</li></ul> </div> </td> <td>2 </td> <td>1.4 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>7× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">October 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0172M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5300"></span><span class="anchor" id="ark29758"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29758.html">Core 2 Duo T5300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9WE (L2)</li></ul> </div> </td> <td>2 </td> <td>1.73 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td>Socket M </td> <td style="text-align:right;">Q1 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GE0302M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5450"></span><span class="anchor" id="ark30787"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30787.html">Core 2 Duo T5450</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4F (M0)</li></ul> </div> </td> <td>2 </td> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q2 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0282MT</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5470"></span><span class="anchor" id="ark31788"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31788.html">Core 2 Duo T5470</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAEB (M0)</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>8× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0252M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5500"></span><span class="anchor" id="ark27253"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27253.html">Core 2 Duo T5500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SH (B2)</li> <li>SLGFK (G2)</li> <li>SL9U4 (L2)</li></ul> </div> </td> <td>2 </td> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td>Socket M </td> <td style="text-align:right;">August 28, 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0282M</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5500"></span><span class="anchor" id="ark27253"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27253.html">Core 2 Duo T5500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SQ (B2)</li> <li>SL9U8 (L2)</li></ul> </div> </td> <td>2 </td> <td>1.67 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td>BGA479 </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GF0282M</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5550"></span><span class="anchor" id="ark32427"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/32427.html">Core 2 Duo T5550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4E (M0)</li></ul> </div> </td> <td>2 </td> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0342MT</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5600"></span><span class="anchor" id="ark27254"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27254.html">Core 2 Duo T5600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SG (B2)</li> <li>SL9U3 (L2)</li></ul> </div> </td> <td>2 </td> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td>Socket M </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0342M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5600"></span><span class="anchor" id="ark27254"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27254.html">Core 2 Duo T5600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SP (B2)</li> <li>SL9U7 (L2)</li></ul> </div> </td> <td>2 </td> <td>1.83 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td>BGA479 </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GF0342M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5670"></span><span class="anchor" id="ark35163"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35163.html">Core 2 Duo T5670</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAJ5 (M0)</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>9× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q2 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0332MN</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5750"></span><span class="anchor" id="ark33915"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33915.html">Core 2 Duo T5750</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4D (M0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0412M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5800"></span><span class="anchor" id="ark35581"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35581.html">Core 2 Duo T5800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB6E (M0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q4 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG041F</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="cite-bracket" id="Core_2_Duo_T5850<sup_id="></span>Core 2 Duo T5850<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4C (M0)</li></ul> </div> </td> <td>2 </td> <td>2.17 GHz </td> <td>2 MB </td> <td>667 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q4 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0482M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T5870"></span><span class="anchor" id="ark37034"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37034.html">Core 2 Duo T5870</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAZR (M0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0412MN</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="cite-bracket" id="Core_2_Duo_T5900<sup_id="></span>Core 2 Duo T5900<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB6D (M0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG049F</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7100"></span><span class="anchor" id="ark29759"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29759.html">Core 2 Duo T7100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA4A (M0)</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>9× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0332M</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7100"></span><span class="anchor" id="ark29759"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29759.html">Core 2 Duo T7100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3U (M1)</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>9× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0332M</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7200"></span><span class="anchor" id="ark27255"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27255.html">Core 2 Duo T7200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SF (B2)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0414M</li></ul> </div> </td> <td>$294 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7200"></span><span class="anchor" id="ark27255"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27255.html">Core 2 Duo T7200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SL (B2)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GF0414M</li></ul> </div> </td> <td>$294 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7250"></span><span class="anchor" id="ark31728"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31728.html">Core 2 Duo T7250</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA49 (M0)</li> <li>SLAXH (M0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0412M</li></ul> </div> </td> <td>$290 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7250"></span><span class="anchor" id="ark31728"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31728.html">Core 2 Duo T7250</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3T (M1)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0412M</li></ul> </div> </td> <td>$290 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7300"></span><span class="anchor" id="ark29760"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29760.html">Core 2 Duo T7300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAMD (G0)</li> <li>SLA45 (E1)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0414M</li> <li>LF80537GG0414M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7300"></span><span class="anchor" id="ark29760"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29760.html">Core 2 Duo T7300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3P (E1)</li> <li>SLAMF (G0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>10× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0414M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7400"></span><span class="anchor" id="ark27256"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27256.html">Core 2 Duo T7400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SE (B2)</li> <li>SLGFJ (G2)</li></ul> </div> </td> <td>2 </td> <td>2.17 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0484M</li></ul> </div> </td> <td>$423 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7400"></span><span class="anchor" id="ark27256"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27256.html">Core 2 Duo T7400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SK (B2)</li> <li>SLGFV (G2)</li></ul> </div> </td> <td>2 </td> <td>2.17 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GF0484M</li></ul> </div> </td> <td>$423 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7500"></span><span class="anchor" id="ark29761"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29761.html">Core 2 Duo T7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA44 (E1)</li> <li>SLAF8 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0494M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7500"></span><span class="anchor" id="ark29761"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29761.html">Core 2 Duo T7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3N (E1)</li> <li>SLADM (G0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>11× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0494M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7600"></span><span class="anchor" id="ark27257"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27257.html">Core 2 Duo T7600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SD (B2)</li></ul> </div> </td> <td>2 </td> <td>2.33 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>14× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0534M</li></ul> </div> </td> <td>$637 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7600"></span><span class="anchor" id="ark27257"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/27257.html">Core 2 Duo T7600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SJ (B2)</li></ul> </div> </td> <td>2 </td> <td>2.33 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>14× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">August 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GF0534M</li></ul> </div> </td> <td>$637 </td></tr> <tr> <td><span class="cite-bracket" id="Core_2_Duo_T7600G<sup_id="></span>Core 2 Duo T7600G<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9U5 (B2)</li></ul> </div> </td> <td>2 </td> <td>2.33 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>14× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">34 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket M</li></ul> </div> </td> <td style="text-align:right;">December 2006 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GF0534MU</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7700"></span><span class="anchor" id="ark29762"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29762.html">Core 2 Duo T7700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA43 (E1)</li> <li>SLAF7 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0564M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7700"></span><span class="anchor" id="ark29762"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29762.html">Core 2 Duo T7700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3M (E1)</li> <li>SLADL (G0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>12× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0564M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7800"></span><span class="anchor" id="ark31729"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31729.html">Core 2 Duo T7800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAF6 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>Socket P</li></ul> </div> </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0644ML</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T7800"></span><span class="anchor" id="ark31729"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31729.html">Core 2 Duo T7800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA75 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>13× </td> <td>0.95–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FCBGA6</li></ul> </div> </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537GG0644M</li></ul> </div> </td> <td>$530 </td></tr> </tbody></table> <p>See also: Versions of the same Merom-2M core with half the L2 cache disabled are available under the <a href="/wiki/List_of_Intel_Pentium_Dual-Core_microprocessors#"Merom-M",_"Merom-2M"_(65_nm)" class="mw-redirect" title="List of Intel Pentium Dual-Core microprocessors">Pentium Dual-Core</a> brand. </p> <div class="mw-heading mw-heading4"><h4 id=""Merom"_(low-voltage,_65_nm)"><span id=".22Merom.22_.28low-voltage.2C_65_nm.29"></span>"Merom" (low-voltage, 65 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=66" title="Edit section: "Merom" (low-voltage, 65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li><i>Intel Dynamic Front Side Bus Frequency Switching</i>: Supported by <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">E1, G0, G2 Steppings</a></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">B2, E1, G0, G2</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="cite-bracket" id="Core_2_Duo_SL7100<sup_id="></span>Core 2 Duo SL7100<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAJD</li> <li>SLAT4</li></ul> </div> </td> <td>2 </td> <td>1.2 GHz </td> <td>4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>6× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">12 W </div> </td> <td><a href="/wiki/%CE%9CFC-BGA_956" class="mw-redirect" title="ΜFC-BGA 956">μFC-BGA 956</a> </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SY80537LG0094M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_L7200"></span><span class="anchor" id="ark28025"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/28025.html">Core 2 Duo L7200</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SN (B2)</li></ul> </div> </td> <td>2 </td> <td>1.33 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>8× </td> <td>0.9–1.2 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">Q1 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537LF0144M</li></ul> </div> </td> <td>$284 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_L7300"></span><span class="anchor" id="ark29756"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29756.html">Core 2 Duo L7300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3S (E1)</li></ul> </div> </td> <td>2 </td> <td>1.4 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>7× </td> <td>0.9–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537LG0174M</li></ul> </div> </td> <td>$284 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_L7400"></span><span class="anchor" id="ark28026"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/28026.html">Core 2 Duo L7400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL9SM (B2)</li> <li>SLGFX (G2)</li></ul> </div> </td> <td>2 </td> <td>1.5 GHz </td> <td>4 MB </td> <td>667 MT/s </td> <td>9× </td> <td>0.9–1.2 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">Q1 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537LF0214M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_L7500"></span><span class="anchor" id="ark29757"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29757.html">Core 2 Duo L7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA3R (E1)</li> <li>SLAET (G0)</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>8× </td> <td>0.9–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">May 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537LG0254M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td>Core 2 Duo SP7500<sup id="cite_ref-intel.com_27-0" class="reference"><a href="#cite_note-intel.com-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability"><span title="The material near this tag failed verification of its source citation(s). (October 2018)">failed verification</span></a></i>]</sup><sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAT2</li> <li>SLAEV</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>8× </td> <td>1.0–1.25 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">20 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SY80537GG0254M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_L7700"></span><span class="anchor" id="ark32243"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/32243.html">Core 2 Duo L7700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAES (G0)</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>9× </td> <td>0.9–1.1 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">September 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537LG0334M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td>Core 2 Duo SP7700<sup id="cite_ref-intel.com_27-1" class="reference"><a href="#cite_note-intel.com-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability"><span title="The material near this tag failed verification of its source citation(s). (October 2018)">failed verification</span></a></i>]</sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLALQ</li> <li>SLALR</li> <li>SLASZ</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>9× </td> <td>1.0–1.25 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">20 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;"> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SY80537GG0334M</li> <li>SY80537GG0334ML</li></ul> </div> </td> <td>OEM </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Merom-2M"_(ultra-low-voltage,_65_nm)"><span id=".22Merom-2M.22_.28ultra-low-voltage.2C_65_nm.29"></span>"Merom-2M" (ultra-low-voltage, 65 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=67" title="Edit section: "Merom-2M" (ultra-low-voltage, 65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 111 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">L2, M0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7500"></span><span class="anchor" id="ark36931"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36931.html">Core 2 Duo U7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA2V (L2)</li> <li>SLAUT (M0)</li></ul> </div> </td> <td>2 </td> <td>1.07 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>533 MT/s </td> <td>8× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket M) </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0042M</li></ul> </div> </td> <td>$262 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7500"></span><span class="anchor" id="ark29763"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29763.html">Core 2 Duo U7500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLV3X (M0)</li></ul> </div> </td> <td>2 </td> <td>1.07 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>8× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket P) </td> <td style="text-align:right;">February 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0042ML</li></ul> </div> </td> <td>$262 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7600"></span><span class="anchor" id="ark29764"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29764.html">Core 2 Duo U7600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA2U (L2)</li> <li>SLAUS (M0)</li></ul> </div> </td> <td>2 </td> <td>1.2 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>9× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket M) </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0092M</li></ul> </div> </td> <td>$289 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7600"></span><span class="anchor" id="ark29764"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/29764.html">Core 2 Duo U7600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLV3W (M0)</li></ul> </div> </td> <td>2 </td> <td>1.2 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>9× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket P) </td> <td style="text-align:right;">April 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0092ML</li></ul> </div> </td> <td>$289 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7700"></span><span class="anchor" id="ark33920"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33920.html">Core 2 Duo U7700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA6X (L2)</li> <li>SLAUR (M0)</li></ul> </div> </td> <td>2 </td> <td>1.33 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>10× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket M) </td> <td style="text-align:right;">December 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0142M</li></ul> </div> </td> <td>$289 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_U7700"></span><span class="anchor" id="ark33920"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33920.html">Core 2 Duo U7700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLV3V (M0)</li></ul> </div> </td> <td>2 </td> <td>1.33 GHz </td> <td>2 MB </td> <td>533 MT/s </td> <td>10× </td> <td>0.8–0.975 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">10 W </div> </td> <td>FCBGA6 (Socket P) </td> <td style="text-align:right;">February 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LE80537UE0142ML</li></ul> </div> </td> <td>$289 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Merom_XE"_(65_nm)"><span id=".22Merom_XE.22_.2865_nm.29"></span>"Merom XE" (65 nm) <span class="anchor" id=""Merom_XE"_(standard-voltage,_65_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=68" title="Edit section: "Merom XE" (65 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><i>These models feature an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a></i> </p> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT), Intel Dynamic Front Side Bus Frequency Switching</i></li> <li>Merom XE processors support Dynamic Front Side Bus Throttling between 400 and 800 MT/s.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 143 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_65nm_process" title="Intel Core (microarchitecture)">E1, G0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_X7800"></span><span class="anchor" id="ark30788"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/30788.html">Core 2 Extreme X7800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA6Z (E1)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>13× </td> <td>1.0375–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">July 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0644M</li></ul> </div> </td> <td>$851 </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_X7900"></span><span class="anchor" id="ark31730"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/31730.html">Core 2 Extreme X7900</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLA33 (E1)</li> <li>SLAF4 (G0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>4 MB </td> <td>800 MT/s </td> <td>14× </td> <td>1.0375–1.3 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">August 2007 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>LF80537GG0724M</li></ul> </div> </td> <td>$851 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn-L"_(45_nm)"><span id=".22Penryn-L.22_.2845_nm.29"></span>"Penryn-L" (45 nm) <span class="anchor" id=""Penryn-L"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=69" title="Edit section: "Penryn-L" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT), Intel Dynamic Acceleration (IDA)</i></li> <li><a href="/wiki/Socket_P" title="Socket P">Socket P</a> processors can throttle the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) anywhere between 400 and 800 MT/s as needed.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 82 mm<sup>2</sup></li> <li>228 million transistors</li> <li>Package size: 22 mm × 22 mm</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0, R0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td align="left" colspan="12" style="background:#127cc1;color: white"><b>Small Form Factor, ultra-low voltage</b> </td></tr> <tr> <td><span class="anchor" id="Core_2_Solo_SU3300"></span><span class="anchor" id="ark36728"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36728.html">Core 2 Solo SU3300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGAR (M0)</li> <li>SLGAJ (R0)</li></ul> </div> </td> <td>1 </td> <td>1.2 GHz </td> <td>3 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>6× </td> <td>1.05–1.15 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td><a href="/wiki/%CE%9CFC-BGA_956" class="mw-redirect" title="ΜFC-BGA 956">μFC-BGA 956</a> </td> <td style="text-align:right;">May 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80585UG0093M</li></ul> </div> </td> <td>$262 </td></tr> <tr> <td><span class="anchor" id="Core_2_Solo_SU3500"></span><span class="anchor" id="ark37133"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37133.html">Core 2 Solo SU3500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGFM (R0)</li></ul> </div> </td> <td>1 </td> <td>1.4 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>7× </td> <td>1.05–1.15 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">5.5 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">Q2 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80585UG0173M</li></ul> </div> </td> <td>$262 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn"_(Apple_iMac_specific,_45_nm)"><span id=".22Penryn.22_.28Apple_iMac_specific.2C_45_nm.29"></span>"Penryn" (Apple iMac specific, 45 nm)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=70" title="Edit section: "Penryn" (Apple iMac specific, 45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li>The 2008 20" iMac used the E8135 and E8335 CPUs at a lower than specified clock frequency, explaining why the same model is used at different frequencies. This list shows the frequencies used by Apple.</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8135"></span>Core 2 Duo E8135 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQA (C0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>9× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576E8135</li> <li>FF80576GH0676M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8135"></span>Core 2 Duo E8135 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLG8W (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">March 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0676M</li> <li>AW80576E8135</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8135"></span>Core 2 Duo E8135 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGED (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">March 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0676M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8235"></span>Core 2 Duo E8235 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQB (C0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10.5× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576GH0726M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8335"></span>Core 2 Duo E8335 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQC (C0)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576GH0776M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8335"></span>Core 2 Duo E8335 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEB (E0)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11× </td> <td>1.0500–1.2250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">March 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0776M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8435"></span>Core 2 Duo E8435 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQD (C0)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td>1.0500–1.2375 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">55 W </div> </td> <td>Socket P </td> <td style="text-align:right;">April 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576GH0836M</li></ul> </div> </td> <td> </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_E8435"></span>Core 2 Duo E8435 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEA (E0)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">March 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0836M</li></ul> </div> </td> <td> </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn",_"Penryn-3M"_(standard-voltage,_45_nm)"><span id=".22Penryn.22.2C_.22Penryn-3M.22_.28standard-voltage.2C_45_nm.29"></span>"Penryn", "Penryn-3M" (standard-voltage, 45 nm) <span class="anchor" id=""Penryn-2M"_(standard-voltage,_45_nm)"></span><span class="anchor" id=""Penryn-3M"_(standard-voltage,_45_nm)"></span><span class="anchor" id=""Penryn"_(standard-voltage,_45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=71" title="Edit section: "Penryn", "Penryn-3M" (standard-voltage, 45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), Intel Dynamic Acceleration (IDA)</i><sup id="cite_ref-T6xxx_29-0" class="reference"><a href="#cite_note-T6xxx-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></li> <li>T6570,<sup id="cite_ref-T6570_30-0" class="reference"><a href="#cite_note-T6570-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> T6670, all T8xxx and T9xxx models support <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a></li> <li>All T9xxx models support <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</li> <li>T6xxx models are Penryn-3M processors with 1 MB L2 cache disabled.</li></ul> <p>Note that models T8100, T8300, T9300, T9500 are Penryn processors designed for Santa Rosa Refresh platforms with maximum FSB of 800 MT/s, whereas the rest of the Penryn processors are designed for Montevina platforms that can go up to maximum FSB of 1066 MT/s. </p><p>Penryn processors support Dynamic Front Side Bus Throttling between 400–800MT/s. </p> <ul><li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup> (Penryn), 82 mm<sup>2</sup> (Penryn-3M)</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, E0</a> (Penryn) <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0, R0</a> (Penryn-3M)<sup id="cite_ref-T6xxx_29-1" class="reference"><a href="#cite_note-T6xxx-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6400"></span><span class="anchor" id="ark40479"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40479.html">Core 2 Duo T6400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGJ4 (R0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>10× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li><a href="/wiki/Socket_P" title="Socket P">Socket P</a></li></ul> </div> </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0412MA</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6500"></span><span class="anchor" id="ark39311"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/39311.html">Core 2 Duo T6500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGF4 (R0)</li></ul> </div> </td> <td>2 </td> <td>2.1 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0452ML</li> <li>AW80577GG0452MA</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6570"></span><span class="anchor" id="ark42841"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42841.html">Core 2 Duo T6570</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLL (R0)</li></ul> </div> </td> <td>2 </td> <td>2.1 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>10.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q3 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0452MH</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6600"></span><span class="anchor" id="ark37255"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37255.html">Core 2 Duo T6600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGJ9 (R0)</li> <li>SLGF5 (R0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>11× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0492MA</li> <li>AW80577GG0492ML</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6670"></span><span class="anchor" id="ark42109"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42109.html">Core 2 Duo T6670</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLK (R0)</li> <li>SLGLJ (R0)</li></ul> </div> </td> <td>2 </td> <td>2.2 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>11× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q3 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0492MH</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6900"></span>Core 2 Duo T6900 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGHZ (?)</li></ul> </div> </td> <td>2 </td> <td>2.5 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>12.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">? </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0602MA</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T6970"></span>Core 2 Duo T6970 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLJ (R0)</li></ul> </div> </td> <td>2 </td> <td>2.5 GHz </td> <td>2 MB </td> <td>800 MT/s </td> <td>12.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">? </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577GG0602MH</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T8100"></span><span class="anchor" id="ark33916"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33916.html">Core 2 Duo T8100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAP9 (M0)</li> <li>SLAVJ (M0)</li> <li>SLAYP (M0)</li> <li>SLAYZ (C0)</li> <li>SLAUU (C0)</li></ul> </div> </td> <td>2 </td> <td>2.1 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>10.5× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80577GG0453M (M0)</li> <li>FF80577GG0453MN</li> <li>FF80576GG0453M (C0)</li> <li>BX80577T8100</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T8100"></span><span class="anchor" id="ark33916"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33916.html">Core 2 Duo T8100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPS (M0)</li> <li>SLAXG (M0)</li> <li>SLAPT (C0)</li> <li>SLAZD (C0)</li></ul> </div> </td> <td>2 </td> <td>2.1 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>10.5× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EC80577GG0453M (M0)</li> <li>EC80576GG0453M (C0)</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T8300"></span><span class="anchor" id="ark33099"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33099.html">Core 2 Duo T8300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPA (M0)</li> <li>SLAYQ (M0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>12× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80577GG0563M</li> <li>BX80577T8300</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T8300"></span><span class="anchor" id="ark33099"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33099.html">Core 2 Duo T8300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPR (M0)</li> <li>SLAPU (C0)</li> <li>SLAZC (C0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>12× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EC80577GG0563M (M0)</li> <li>EC80576GG0563M (C0)</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9300"></span><span class="anchor" id="ark33917"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33917.html">Core 2 Duo T9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQG (C0)</li> <li>SLAYY (C0)</li></ul> </div> </td> <td>2 </td> <td>2.5 GHz </td> <td>6 MB </td> <td>800 MT/s </td> <td>12.5× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576GG0606M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9300"></span><span class="anchor" id="ark33917"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33917.html">Core 2 Duo T9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPV (C0)</li> <li>SLAZB (C0)</li></ul> </div> </td> <td>2 </td> <td>2.5 GHz </td> <td>6 MB </td> <td>800 MT/s </td> <td>12.5× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EC80576GG0606M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9400"></span><span class="anchor" id="ark35562"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35562.html">Core 2 Duo T9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB46 (C0)</li> <li>SLB4D (C0)</li> <li>SLGE5 (E0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.050–1.162 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0616M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9400"></span><span class="anchor" id="ark35562"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35562.html">Core 2 Duo T9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SL3BX (C0)</li> <li>SLGEK (E0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.050–1.162 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576GH0616M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9500"></span><span class="anchor" id="ark33918"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33918.html">Core 2 Duo T9500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQH (C0)</li> <li>SLAYX (C0)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>6 MB </td> <td>800 MT/s </td> <td>13× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576GG0646M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9500"></span><span class="anchor" id="ark33918"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/33918.html">Core 2 Duo T9500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAPW (C0)</li> <li>SLAZA (C0)</li> <li>SLB49 (C0)</li> <li>SLB4A (C0)</li></ul> </div> </td> <td>2 </td> <td>2.6 GHz </td> <td>6 MB </td> <td>800 MT/s </td> <td>13× </td> <td>1.000–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>EC80576GG0646M</li> <li>AV80576SH0616M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9550"></span><span class="anchor" id="ark37130"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37130.html">Core 2 Duo T9550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGE4 (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>1.050–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0676MG</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9550"></span><span class="anchor" id="ark37130"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37130.html">Core 2 Duo T9550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEL (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>1.050–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576GH0676MG</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9600"></span><span class="anchor" id="ark35563"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35563.html">Core 2 Duo T9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB47 (C0)</li> <li>SLG8N (C0)</li> <li>SLG9F (E0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10.5× </td> <td>1.050–1.162 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0726M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9600"></span><span class="anchor" id="ark35563"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35563.html">Core 2 Duo T9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB43 (C0)</li> <li>SLGEM (E0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10.5× </td> <td>1.050–1.162 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576GH0726M</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9800"></span><span class="anchor" id="ark37005"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37005.html">Core 2 Duo T9800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGES (E0)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11× </td> <td>1.050–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0776MG</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9800"></span><span class="anchor" id="ark37005"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37005.html">Core 2 Duo T9800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEP (E0)</li></ul> </div> </td> <td>2 </td> <td>2.93 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11× </td> <td>1.050–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576GH0776MG</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9900"></span><span class="anchor" id="ark39312"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/39312.html">Core 2 Duo T9900</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEE (E0)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td>1.050–1.2125 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>Socket P </td> <td style="text-align:right;">April 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0836MG</li></ul> </div> </td> <td>$530 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_T9900"></span><span class="anchor" id="ark39312"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/39312.html">Core 2 Duo T9900</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGKH (E0)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td>1.050–1.2125 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">35 W </div> </td> <td>FCBGA6 </td> <td style="text-align:right;">April 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576GH0836MG</li></ul> </div> </td> <td>$530 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn",_"Penryn-3M"_(medium-voltage,_45_nm)"><span id=".22Penryn.22.2C_.22Penryn-3M.22_.28medium-voltage.2C_45_nm.29"></span>"Penryn", "Penryn-3M" (medium-voltage, 45 nm) <span class="anchor" id=""Penryn"_(medium-voltage,_45_nm)"></span><span class="anchor" id=""Penryn-3M"_(medium-voltage,_45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=72" title="Edit section: "Penryn", "Penryn-3M" (medium-voltage, 45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a> (except the non-Mac P7350, P7450),<sup id="cite_ref-P7350_31-0" class="reference"><a href="#cite_note-P7350-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-P7450_32-0" class="reference"><a href="#cite_note-P7450-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-P7550_33-0" class="reference"><a href="#cite_note-P7550-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT), Intel Dynamic Acceleration (IDA)</i></li> <li>Select <a href="/wiki/Apple_Inc." title="Apple Inc.">Apple</a> subsets of P7000 series processors support Intel VT-x.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup></li> <li>Penryn and Penryn-3M processors support Dynamic Front Side Bus Throttling between 533–1066MT/s.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup> (Penryn), 82 mm<sup>2</sup> (Penryn-3M)</li> <li>Package size: 35 mm × 35 mm</li> <li>Transistors: 410 million <sup id="cite_ref-Techarp20151218_35-0" class="reference"><a href="#cite_note-Techarp20151218-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: (<a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">Core microarchitecture 45nm steppings</a>) <ul><li><a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, E0</a> (Penryn)</li> <li><a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0, R0</a> (Penryn-3M)</li> <li>stepping C0/M0 is only used in the Intel Mobile 965 Express (<a href="/wiki/Centrino#Santa_Rosa_platform_(2007)" title="Centrino">Santa Rosa refresh</a>) platform</li> <li>stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and supports the later Intel Mobile 4 Express (<a href="/wiki/Centrino#Montevina_platform_(2008)" title="Centrino">Montevina</a>) platform</li></ul></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7350"></span><span class="anchor" id="ark36750"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36750.html">Core 2 Duo P7350</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB44 (C0)</li> <li>SLB53 (M0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>3 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>7.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Mid 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0413M</li> <li>AW80577SH0413M</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7350"></span><span class="anchor" id="ark36750"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36750.html">Core 2 Duo P7350</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLG8E (C0)</li> <li>SLGE3 (R0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>3 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>7.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">Mid 2008 </td> <td> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7370"></span><span class="anchor" id="ark37117"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37117.html">Core 2 Duo P7370</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLG8X (R0)</li> <li>SLGF9 (R0)</li></ul> </div> </td> <td>2 </td> <td>2 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>7.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0413M</li> <li>AW80577SH0413ML</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7450"></span><span class="anchor" id="ark36734"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36734.html">Core 2 Duo P7450</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB45 (C0)</li> <li>SLGF7 (R0)</li> <li>SLB54 (M0)</li> <li>SLB56 (M0)</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0463M</li> <li>AW80576GH0463M (C0)</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7450"></span><span class="anchor" id="ark36734"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36734.html">Core 2 Duo P7450</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGFF (C0)</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">January 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577P7450M (C0)</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7550"></span><span class="anchor" id="ark42014"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42014.html">Core 2 Duo P7550</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGF8 (R0)</li></ul> </div> </td> <td>2 </td> <td>2.27 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">June 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0513MA</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P7570"></span><span class="anchor" id="ark42167"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42167.html">Core 2 Duo P7570</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLW (R0)</li></ul> </div> </td> <td>2 </td> <td>2.27 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q3 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0513ML</li></ul> </div> </td> <td>OEM </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8400"></span><span class="anchor" id="ark35569"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35569.html">Core 2 Duo P8400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB3R (M0)</li> <li>SLB3Q (M0)</li> <li>SLB52 (M0)</li> <li>SLG8Z (M0)</li> <li>SLGCC (R0)</li> <li>SLGCQ (R0)</li> <li>SLGCF (R0)</li> <li>SLGFC (R0)</li> <li>SLGCL (R0)</li></ul> </div> </td> <td>2 </td> <td>2.27 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">June 13, 2008<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0513M</li> <li>AW80577SH0513MN</li> <li>BX80577P8400</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8400"></span><span class="anchor" id="ark35569"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35569.html">Core 2 Duo P8400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB4M (M0)</li></ul> </div> </td> <td>2 </td> <td>2.27 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>8.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">June 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577SH0513M</li></ul> </div> </td> <td>$209 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8600"></span><span class="anchor" id="ark35568"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35568.html">Core 2 Duo P8600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB3S (M0)</li> <li>SLGA4 (M0)</li> <li>SLGFD (R0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>9× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">June 2008<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0563M</li> <li>BX80577P8600</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8600"></span><span class="anchor" id="ark35568"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35568.html">Core 2 Duo P8600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB4N (M0)</li> <li>SLGDZ (R0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>9× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">June 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577SH0563M</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8700"></span><span class="anchor" id="ark37006"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37006.html">Core 2 Duo P8700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGFE (R0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0613MG</li> <li>BX80577P8700</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8700"></span><span class="anchor" id="ark37006"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37006.html">Core 2 Duo P8700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGFG (R0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577SH0613MG</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8800"></span><span class="anchor" id="ark40380"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40380.html">Core 2 Duo P8800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLR (R0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">Q2 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80577SH0673MG</li> <li>BX80577P8800</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P8800"></span><span class="anchor" id="ark40380"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40380.html">Core 2 Duo P8800</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGLA (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>3 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>1.00–1.250 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>FC-BGA478 </td> <td style="text-align:right;">Q2 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577SH0673MG</li></ul> </div> </td> <td>$241 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P9500"></span><span class="anchor" id="ark35566"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35566.html">Core 2 Duo P9500</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB4E (C0)</li> <li>SLGE8 (E0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.05–1.162 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576SH0616M</li> <li>AV80576SH0616M</li></ul> </div> </td> <td>$348 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P9600"></span><span class="anchor" id="ark37266"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37266.html">Core 2 Duo P9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGE6 (E0)</li></ul> </div> </td> <td>2 </td> <td>2.67 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10× </td> <td>1.05–1.212 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>Socket P </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576SH0676MG</li></ul> </div> </td> <td>$348 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_P9700"></span><span class="anchor" id="ark42599"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42599.html">Core 2 Duo P9700</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGQS (E0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>10.5× </td> <td>1.012–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">28 W </div> </td> <td>Socket P </td> <td style="text-align:right;">June 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576SH0726MG</li></ul> </div> </td> <td>$348 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn"_(medium-voltage,_45_nm,_Small_Form_Factor)"><span id=".22Penryn.22_.28medium-voltage.2C_45_nm.2C_Small_Form_Factor.29"></span>"Penryn" (medium-voltage, 45 nm, Small Form Factor)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=73" title="Edit section: "Penryn" (medium-voltage, 45 nm, Small Form Factor)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT), Intel Dynamic Acceleration (IDA)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li>Package size: 22 mm × 22 mm</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0</a>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SP9300"></span><span class="anchor" id="ark36691"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36691.html">Core 2 Duo SP9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB63 (C0)</li></ul> </div> </td> <td>2 </td> <td>2.27 GHz </td> <td>6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>8.5× </td> <td>0.900–1.225 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td><a href="/wiki/%CE%9CFC-BGA_956" class="mw-redirect" title="ΜFC-BGA 956">μFC-BGA 956</a> </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576SH0516M</li></ul> </div> </td> <td>$284 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SP9400"></span><span class="anchor" id="ark36693"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36693.html">Core 2 Duo SP9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB64 (C0)</li> <li>SLGHG (C0)</li> <li>SLGAA (E0)</li></ul> </div> </td> <td>2 </td> <td>2.4 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>9× </td> <td>0.900–1.225 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576SH0566M</li></ul> </div> </td> <td>$284 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SP9600"></span><span class="anchor" id="ark37260"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37260.html">Core 2 Duo SP9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGER (E0)</li></ul> </div> </td> <td>2 </td> <td>2.53 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>9.5× </td> <td>0.900–1.225 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">25 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">Q1 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576SH0516M</li> <li>AV80576SH0616M</li></ul> </div> </td> <td>$316 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn"_(low-voltage,_45_nm,_Small_Form_Factor)"><span id=".22Penryn.22_.28low-voltage.2C_45_nm.2C_Small_Form_Factor.29"></span>"Penryn" (low-voltage, 45 nm, Small Form Factor)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=74" title="Edit section: "Penryn" (low-voltage, 45 nm, Small Form Factor)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT), Intel Dynamic Acceleration (IDA)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li>Package size: 22 mm × 22 mm</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0</a>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SL9300"></span><span class="anchor" id="ark36686"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36686.html">Core 2 Duo SL9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB65 (C0)</li> <li>SLGHC (C0)</li> <li>SLGAG (E0)</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>1066 MT/s </td> <td>6× </td> <td>1.050–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td><a href="/wiki/%CE%9CFC-BGA_956" class="mw-redirect" title="ΜFC-BGA 956">μFC-BGA 956</a> </td> <td style="text-align:right;">September 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576LH0256M</li></ul> </div> </td> <td>$284 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SL9380"></span><span class="anchor" id="ark37210"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37210.html">Core 2 Duo SL9380</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGA2 (C0)</li> <li>SLGAD (E0)</li></ul> </div> </td> <td>2 </td> <td>1.8 GHz </td> <td>6 MB </td> <td>800 MT/s </td> <td>9× </td> <td>1.050–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">September 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576LG0336M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SL9400"></span><span class="anchor" id="ark36689"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36689.html">Core 2 Duo SL9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB66 (C0)</li> <li>SLGHD (C0)</li> <li>SLGAB (E0)</li></ul> </div> </td> <td>2 </td> <td>1.87 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>7× </td> <td>1.050–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">September 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576LH0366M</li></ul> </div> </td> <td>$316 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SL9600"></span><span class="anchor" id="ark37262"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37262.html">Core 2 Duo SL9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEQ (E0)</li></ul> </div> </td> <td>2 </td> <td>2.13 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>8× </td> <td>1.050–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">17 W </div> </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">Q1'09 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80576LH0466M</li></ul> </div> </td> <td>$316 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)"><span id=".22Penryn-3M.22_.28ultra-low-voltage.2C_45_nm.2C_Small_Form_Factor.29"></span>"Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=75" title="Edit section: "Penryn-3M" (ultra-low-voltage, 45 nm, Small Form Factor)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT) (except SU7300), Intel Dynamic Acceleration (IDA)</i></li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li>Package size: 22 mm × 22 mm</li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">M0</a>, <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">R0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SU7300"></span><span class="anchor" id="ark42791"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/42791.html">Core 2 Duo SU7300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGS6 (R0)</li> <li>SLGYV (R0)</li></ul> </div> </td> <td>2 </td> <td>1.3 GHz </td> <td>3 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>6.5× </td> <td>1.05–1.15 V </td> <td>10 W </td> <td><a href="/wiki/%CE%9CFC-BGA_956" class="mw-redirect" title="ΜFC-BGA 956">μFC-BGA 956</a> </td> <td style="text-align:right;">September 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577UG0133M</li> <li>AV80577UG0133ML</li></ul> </div> </td> <td>$289 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SU9300"></span><span class="anchor" id="ark36695"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36695.html">Core 2 Duo SU9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5Q (M0)</li> <li>SLGAL (R0)</li></ul> </div> </td> <td>2 </td> <td>1.2 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>6× </td> <td>1.05–1.15 V </td> <td>10 W </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">September 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577UG0093M</li></ul> </div> </td> <td>$262 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SU9400"></span><span class="anchor" id="ark36697"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36697.html">Core 2 Duo SU9400</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5V (M0)</li> <li>SLGHN (M0)</li> <li>SLGAK (R0)</li></ul> </div> </td> <td>2 </td> <td>1.4 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>7× </td> <td>1.05–1.15 V </td> <td>10 W </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">September 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577UG0173M</li></ul> </div> </td> <td>$289 </td></tr> <tr> <td><span class="anchor" id="Core_2_Duo_SU9600"></span><span class="anchor" id="ark37264"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37264.html">Core 2 Duo SU9600</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEX (R0)</li> <li>SLGFN (R0)</li></ul> </div> </td> <td>2 </td> <td>1.6 GHz </td> <td>3 MB </td> <td>800 MT/s </td> <td>8× </td> <td>1.05–1.15 V </td> <td>10 W </td> <td>μFC-BGA 956 </td> <td style="text-align:right;">Q1 2009 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AV80577UG0253M</li></ul> </div> </td> <td>$289 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn_XE"_(45_nm)"><span id=".22Penryn_XE.22_.2845_nm.29"></span>"Penryn XE" (45 nm) <span class="anchor" id=""Penryn_XE"_(standard-voltage,_45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=76" title="Edit section: "Penryn XE" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>These models feature an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a></li> <li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li>Penryn XE processors support Dynamic Front Side Bus Throttling between 400–800 MT/s and 533–1066 MT/s.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 107 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">C0, E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_X9000"></span><span class="anchor" id="ark34443"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/34443.html">Core 2 Extreme X9000</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLAQJ (C0)</li> <li>SLAZ3 (C0)</li></ul> </div> </td> <td>2 </td> <td>2.8 GHz </td> <td>6 <a href="/wiki/Megabyte" title="Megabyte">MB</a> </td> <td>800 MT/s </td> <td>14× </td> <td>1.062–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">January 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>FF80576ZG0726M</li></ul> </div> </td> <td>$851 </td></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_X9100"></span><span class="anchor" id="ark35431"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/35431.html">Core 2 Extreme X9100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB48 (C0)</li> <li>SLG8M (C0)</li> <li>SLGE7 (E0)</li></ul> </div> </td> <td>2 </td> <td>3.07 GHz </td> <td>6 MB </td> <td>1066 MT/s </td> <td>11.5× </td> <td>1.062–1.150 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">44 W </div> </td> <td>Socket P </td> <td style="text-align:right;">July 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80576GH0836M</li></ul> </div> </td> <td>$851 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn_QC"_(45_nm)"><span id=".22Penryn_QC.22_.2845_nm.29"></span>"Penryn QC" (45 nm) <span class="anchor" id=""Penryn_QC"_(standard-voltage,_45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=77" title="Edit section: "Penryn QC" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li>Can throttle the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) anywhere between 533 and 1066 MT/s as needed.</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 × 107 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9000"></span><span class="anchor" id="ark40480"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/40480.html">Core 2 Quad Q9000</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLGEJ (E0)</li></ul> </div> </td> <td>4 </td> <td>2 GHz </td> <td>2 × 3 MB </td> <td>1066 MT/s </td> <td>7.5× </td> <td>1.050–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">45 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">December 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80581GH0416M</li> <li>BX80581Q9000</li></ul> </div> </td> <td>$348 </td></tr> <tr> <td><span class="anchor" id="Core_2_Quad_Q9100"></span><span class="anchor" id="ark37033"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/37033.html">Core 2 Quad Q9100</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5G (E0)</li></ul> </div> </td> <td>4 </td> <td>2.27 GHz </td> <td>2 × 6 MB </td> <td>1066 MT/s </td> <td>8.5× </td> <td>1.050–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">45 W </div> </td> <td>Socket P </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80581GH051003</li></ul> </div> </td> <td>$851 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id=""Penryn_QC_XE"_(45_nm)"><span id=".22Penryn_QC_XE.22_.2845_nm.29"></span>"Penryn QC XE" (45 nm) <span class="anchor" id=""Penryn_QC_XE"_(standard-voltage,_45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=78" title="Edit section: "Penryn QC XE" (45 nm)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>This model features an <a href="/wiki/CPU_locking" class="mw-redirect" title="CPU locking">unlocked</a> <a href="/wiki/Clock_multiplier" class="mw-redirect" title="Clock multiplier">clock multiplier</a> usually manipulated through the systems BIOS however some manufacturers (such as <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a>) do not have this feature enabled on their laptops that use this processor.</li> <li>All models support: <i><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4" title="SSE4">SSE4</a>.1, Enhanced Intel <a href="/wiki/SpeedStep" title="SpeedStep">SpeedStep</a> Technology (EIST), <a href="/wiki/Intel_64" class="mw-redirect" title="Intel 64">Intel 64</a>, XD bit (an <a href="/wiki/NX_bit" title="NX bit">NX bit</a> implementation), <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT2), <a href="/wiki/Intel_VT-x" class="mw-redirect" title="Intel VT-x">Intel VT-x</a>, <a href="/wiki/Trusted_Execution_Technology" title="Trusted Execution Technology">Trusted Execution Technology</a> (TXT)</i></li> <li>Can throttle the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB) anywhere between 533 and 1066 MT/s as needed.</li> <li>Package size: 35 mm × 35 mm</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 2 × 107 mm<sup>2</sup></li> <li><a href="/wiki/Stepping_level" title="Stepping level">Steppings</a>: <a href="/wiki/Intel_Core_(microarchitecture)#Steppings_using_45nm_process" title="Intel Core (microarchitecture)">E0</a></li></ul> <table class="wikitable mw-datatable plainrowheaders sortable"> <tbody><tr> <th>Model </th> <th>sSpec<br />number </th> <th>Cores </th> <th><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2<br />cache</a> </th> <th><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> </th> <th><a href="/wiki/CPU_multiplier" title="CPU multiplier">Mult.</a> </th> <th><a href="/wiki/CPU_core_voltage" title="CPU core voltage">Voltage</a> </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th style="text-align:right;">Release date </th> <th>Part<br />number(s) </th> <th>Release<br />price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <td><span class="anchor" id="Core_2_Extreme_QX9300"></span><span class="anchor" id="ark36727"></span><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/36727.html">Core 2 Extreme QX9300</a> </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>SLB5J (E0)</li></ul> </div> </td> <td>4 </td> <td>2.53 GHz </td> <td>2 × 6 <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> </td> <td>1066 MT/s </td> <td>9.5× </td> <td>1.050–1.175 V </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist" style="margin-left: 2em;">45 W </div> </td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a> </td> <td style="text-align:right;">August 2008 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>AW80581ZH061003</li></ul> </div> </td> <td>$1038 </td></tr> </tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(1st_gen)_2"><span id="Core_i_.281st_gen.29_2"></span>Core i (1st gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=79" title="Edit section: Core i (1st gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Clarksfield">Clarksfield<span class="anchor" id=""Clarksfield"_(45_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=80" title="Edit section: Clarksfield"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Socket_G1" title="Socket G1">G1</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>-1333 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 1.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/45_nm_process" title="45 nm process">45 nm</a>.</li> <li>XM-suffix processors have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="6">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43127.html">940XM</a> </th> <td rowspan="6">4 (8) </td> <td>2.13 </td> <td>3.33 </td> <td rowspan="4">8 MB </td> <td rowspan="2">55 W </td> <td><span data-sort-value="000000002010-06-01-0000" style="white-space:nowrap">June 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43126.html">920XM</a> </th> <td>2.00 </td> <td rowspan="2">3.20 </td> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43125.html">840QM</a> </th> <td>1.86 </td> <td rowspan="4">45 W </td> <td><span data-sort-value="000000002010-06-01-0000" style="white-space:nowrap">June 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43124.html">820QM</a> </th> <td rowspan="2">1.73 </td> <td>3.06 </td> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49024.html">740QM</a> </th> <td>2.93 </td> <td rowspan="2">6 MB </td> <td><span data-sort-value="000000002010-06-01-0000" style="white-space:nowrap">June 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43122.html">720QM</a> </th> <td>1.60 </td> <td>2.80 </td> <td><span data-sort-value="000000002009-09-01-0000" style="white-space:nowrap">September 2009</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Arrandale">Arrandale<span class="anchor" id=""Arrandale"_(MCP,_32_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=81" title="Edit section: Arrandale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: All models (except i3-380M) are available in BGA-1288; M-suffix (excluding UM- and LM-suffix) models are also available as <a href="/wiki/Socket_G1" title="Socket G1">Socket G1</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM. All models support it at 800 MT/s speeds while M- and LM-suffix models support up to 1066 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 1.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="9">Core i7 </th> <th style="text-align:left;" data-sort-value="sku29"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49664.html">680UM</a> </th> <td rowspan="29">2 (4) </td> <td>1.46 </td> <td>2.53 </td> <td rowspan="29"><a href="/wiki/Intel_Graphics_Technology#Westmere" title="Intel Graphics Technology">HD Graphics</a> </td> <td>166–500 </td> <td rowspan="9">4 MB </td> <td>18 W </td> <td rowspan="2"><span data-sort-value="000000002010-09-01-0000" style="white-space:nowrap">September 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49654.html">660LM</a> </th> <td>2.26 </td> <td>3.06 </td> <td>266–566 </td> <td>25 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49158.html">660UM</a> </th> <td>1.33 </td> <td>2.40 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49666.html">640M</a> </th> <td>2.80 </td> <td>3.46 </td> <td>500–766 </td> <td>35 W </td> <td><span data-sort-value="000000002010-09-01-0000" style="white-space:nowrap">September 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43563.html">640LM</a> </th> <td>2.13 </td> <td>2.93 </td> <td>266–566 </td> <td>25 W </td> <td rowspan="5"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47700.html">640UM</a> </th> <td>1.20 </td> <td>2.27 </td> <td>166–500 </td> <td>18 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43560.html">620M</a> </th> <td>2.66 </td> <td>3.33 </td> <td>500–766 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43559.html">620LM</a> </th> <td>2.00 </td> <td>2.80 </td> <td>266–566 </td> <td>25 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43562.html">620UM</a> </th> <td>1.06 </td> <td>2.13 </td> <td>166–500 </td> <td>18 W </td></tr> <tr> <th rowspan="13">Core i5 </th> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49652.html">580M</a> </th> <td rowspan="2">2.66 </td> <td>3.33 </td> <td rowspan="2">500–766 </td> <td rowspan="20">3 MB </td> <td rowspan="2">35 W </td> <td rowspan="3"><span data-sort-value="000000002010-09-01-0000" style="white-space:nowrap">September 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49653.html">560M</a> </th> <td>3.20 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49665.html">560UM</a> </th> <td>1.33 </td> <td>2.13 </td> <td>166–500 </td> <td>18 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43544.html">540M</a> </th> <td>2.53 </td> <td>3.07 </td> <td>500–766 </td> <td>35 W </td> <td><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49159.html">540UM</a> </th> <td>1.20 </td> <td>2.00 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47341.html">520M</a> </th> <td>2.40 </td> <td>2.93 </td> <td>500–766 </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47554.html">520UM</a> </th> <td>1.07 </td> <td>1.87 </td> <td>166–500 </td> <td>18 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52952.html">480M</a> </th> <td>2.66 </td> <td>2.93 </td> <td>500–766 </td> <td>35 W </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50026.html">470UM</a> </th> <td>1.33 </td> <td>1.86 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-10-01-0000" style="white-space:nowrap">October 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50179.html">460M</a> </th> <td>2.53 </td> <td>2.80 </td> <td rowspan="3">500–766 </td> <td rowspan="3">35 W </td> <td><span data-sort-value="000000002010-09-01-0000" style="white-space:nowrap">September 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49022.html">450M</a> </th> <td>2.40 </td> <td>2.66 </td> <td><span data-sort-value="000000002010-06-01-0000" style="white-space:nowrap">June 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43537.html">430M</a> </th> <td>2.26 </td> <td>2.53 </td> <td><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49023.html">430UM</a> </th> <td>1.20 </td> <td>1.73 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td></tr> <tr> <th rowspan="7">Core i3 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52955.html">390M</a> </th> <td>2.66 </td> <td rowspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">500–667 </td> <td rowspan="2">35 W </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50178.html">380M</a> </th> <td>2.53 </td> <td><span data-sort-value="000000002010-09-01-0000" style="white-space:nowrap">September 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50028.html">380UM</a> </th> <td>1.33 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-10-01-0000" style="white-space:nowrap">October 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49020.html">370M</a> </th> <td>2.40 </td> <td rowspan="3">500–667 </td> <td rowspan="3">35 W </td> <td><span data-sort-value="000000002010-06-01-0000" style="white-space:nowrap">June 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/43529.html">350M</a> </th> <td>2.26 </td> <td rowspan="2"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47663.html">330M</a> </th> <td>2.13 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/49021.html">330UM</a> </th> <td>1.20 </td> <td>166–500 </td> <td>18 W </td> <td><span data-sort-value="000000002010-05-01-0000" style="white-space:nowrap">May 2010</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(2nd_gen)_2"><span id="Core_i_.282nd_gen.29_2"></span>Core i (2nd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=82" title="Edit section: Core i (2nd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Sandy_Bridge-M">Sandy Bridge-M<span class="anchor" id=""Sandy_Bridge"_(32_nm)"></span><span class="anchor" id=""Sandy_Bridge-M"_(dual-core,_32_nm)"></span><span class="anchor" id=""Sandy_Bridge-M"_(quad-core)_(32_nm)"></span><span class="anchor" id=""Sandy_Bridge"_(32_nm)_2"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=83" title="Edit section: Sandy Bridge-M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Socket_G2" title="Socket G2">G2</a>, BGA 1023 (dual-core models), BGA 1224 (quad-core models).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM. All models support it at 1333 MT/s speeds while i7-2720QM and above support up to 1600 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li> <li>XM-suffix models have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="18">Core i7 </th> <th style="text-align:left;" data-sort-value="sku42"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53478.html">2960XM</a> </th> <td rowspan="10">4 (8) </td> <td>2.7 </td> <td>3.7 </td> <td rowspan="42"><a href="/wiki/Intel_Graphics_Technology#Sandy_Bridge" title="Intel Graphics Technology">HD 3000</a> </td> <td rowspan="6">650–1300 </td> <td rowspan="4">8 MB </td> <td rowspan="2">55 W </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku41"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52237.html">2920XM</a> </th> <td rowspan="2">2.5 </td> <td>3.5 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku40"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53476.html">2860QM</a> </th> <td>3.6 </td> <td rowspan="8">45 W </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku39"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52227.html">2820QM</a> </th> <td>2.3 </td> <td>3.4 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku38"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53474.html">2760QM</a> </th> <td>2.4 </td> <td>3.5 </td> <td rowspan="6">6 MB </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku37"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50067.html">2720QM</a> </th> <td rowspan="3">2.2 </td> <td>3.3 </td> <td><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku36"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53470.html">2675QM</a> </th> <td rowspan="2">3.1 </td> <td>650–1200 </td> <td rowspan="2"><span data-sort-value="000000002011-10-01-0000" style="white-space:nowrap">October 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku35"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53469.html">2670QM</a> </th> <td>650–1100 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku34"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53463.html">2635QM</a> </th> <td rowspan="2">2.0 </td> <td rowspan="2">2.9 </td> <td>650–1200 </td> <td rowspan="2"><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku33"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52219.html">2630QM</a> </th> <td>650–1100 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku32"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54617.html">2677M</a> </th> <td rowspan="32">2 (4) </td> <td>1.8 </td> <td>2.9 </td> <td>350–1200 </td> <td rowspan="8">4 MB </td> <td rowspan="2">17 W </td> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku31"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54615.html">2657M</a> </th> <td>1.6 </td> <td>2.7 </td> <td>350–1000 </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku30"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53464.html">2640M</a> </th> <td>2.8 </td> <td>3.5 </td> <td>650–1300 </td> <td>35 W </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku29"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54611.html">2649M</a> </th> <td>2.3 </td> <td>3.2 </td> <td>500–1100 </td> <td>25 W </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54618.html">2637M</a> </th> <td>1.7 </td> <td>2.8 </td> <td>350–1200 </td> <td>17 W </td> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52231.html">2620M</a> </th> <td>2.7 </td> <td>3.4 </td> <td>650–1300 </td> <td>35 W </td> <td rowspan="3"><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54610.html">2629M</a> </th> <td>2.1 </td> <td>3.0 </td> <td>500–1100 </td> <td>25 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54616.html">2617M</a> </th> <td>1.5 </td> <td>2.6 </td> <td>350–950 </td> <td rowspan="2">17 W </td></tr> <tr> <th rowspan="10">Core i5 </th> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54620.html">2557M</a> </th> <td>1.7 </td> <td>2.7 </td> <td>350–1200 </td> <td rowspan="24">3 MB </td> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50072.html">2540M</a> </th> <td>2.6 </td> <td>3.3 </td> <td>650–1300 </td> <td>35 W </td> <td rowspan="3"><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54619.html">2537M</a> </th> <td>1.4 </td> <td>2.3 </td> <td>350–900 </td> <td>17 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52229.html">2520M</a> </th> <td>2.5 </td> <td>3.2 </td> <td>650–1300 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/56858.html">2467M</a> </th> <td>1.6 </td> <td>2.3 </td> <td>350–1150 </td> <td>17 W </td> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53452.html">2450M</a> </th> <td>2.5 </td> <td>3.1 </td> <td rowspan="2">650–1300 </td> <td rowspan="6">35 W </td> <td><span data-sort-value="000000002012-01-01-0000" style="white-space:nowrap">January 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/60636.html">2435M</a> </th> <td rowspan="2">2.4 </td> <td rowspan="2">3.0 </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53450.html">2430M</a> </th> <td>650–1200 </td> <td><span data-sort-value="000000002011-10-01-0000" style="white-space:nowrap">October 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53449.html">2415M</a> </th> <td rowspan="2">2.3 </td> <td rowspan="2">2.9 </td> <td>650–1300 </td> <td>Q1 2011 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52224.html">2410M</a> </th> <td>650–1200 </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th rowspan="14">Core i3 </th> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53442.html">2370M</a> </th> <td>2.4 </td> <td rowspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>650–1150 </td> <td><span data-sort-value="000000002012-01-01-0000" style="white-space:nowrap">January 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54834.html">2377M</a> </th> <td rowspan="2">1.5 </td> <td rowspan="4">350–1000 </td> <td rowspan="4">17 W </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/74259.html">2375M</a> </th> <td>Q1 2013 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/59798.html">2367M</a> </th> <td rowspan="2">1.4 </td> <td><span data-sort-value="000000002011-10-01-0000" style="white-space:nowrap">October 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/70272.html">2365M</a> </th> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53438.html">2350M</a> </th> <td>2.3 </td> <td>650–1150 </td> <td>35 W </td> <td><span data-sort-value="000000002011-10-01-0000" style="white-space:nowrap">October 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54624.html">2357M</a> </th> <td>1.3 </td> <td>350–950 </td> <td>17 W </td> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/74542.html">2348M</a> </th> <td>2.3 </td> <td>650–1150 </td> <td rowspan="7">35 W </td> <td><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6">2332M<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </th> <td rowspan="3">2.2 </td> <td rowspan="6">650–1100 </td> <td><span data-sort-value="000000002011-09-01-0000" style="white-space:nowrap">September 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53434.html">2330M</a> </th> <td><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/70927.html">2328M</a> </th> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53432.html">2312M</a> </th> <td rowspan="3">2.1 </td> <td>Q2 2011 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/52220.html">2310M</a> </th> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1">2308M<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </th> <td>Q3 2012 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(3rd_gen)_2"><span id="Core_i_.283rd_gen.29_2"></span>Core i (3rd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=84" title="Edit section: Core i (3rd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Ivy_Bridge">Ivy Bridge<span class="anchor" id=""Ivy_Bridge"_(22_nm)"></span><span class="anchor" id=""Ivy_Bridge-M"_(dual-core,_22_nm)"></span><span class="anchor" id=""Ivy_Bridge-M"_(quad-core)_(22_nm)"></span><span class="anchor" id=""Ivy_Bridge"_(22_nm)_2"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=85" title="Edit section: Ivy Bridge"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i5_3230M_(Ivy_Bridge,_JPG,_Full_Scale,_85%25_Quality).jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg/220px-Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg" decoding="async" width="220" height="124" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg/330px-Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1a/Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg/440px-Intel_i5_3230M_%28Ivy_Bridge%2C_JPG%2C_Full_Scale%2C_85%25_Quality%29.jpg 2x" data-file-width="34346" data-file-height="19362" /></a><figcaption>Intel i5 3230M die shot</figcaption></figure> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Socket_G2" title="Socket G2">G2</a>, BGA 1023 (dual-core models), BGA 1224 (quad-core models).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of PCIe, except Y-suffix models which do not have PCIe support. i5 and i7 M-, QM- and XM-suffix models support it at <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> speeds, while all other models support it at PCIe 2.0 speeds.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>XM-suffix models have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="19">Core i7 </th> <th style="text-align:left;" data-sort-value="sku37"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71096.html">3940XM</a> </th> <td rowspan="12">4 (8) </td> <td>3.0 </td> <td>3.9 </td> <td rowspan="37"><a href="/wiki/Intel_Graphics_Technology#Ivy_Bridge" title="Intel Graphics Technology">HD 4000</a> </td> <td>650–1350 </td> <td rowspan="4">8 MB </td> <td rowspan="2">55 W </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku36"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64887.html">3920XM</a> </th> <td>2.9 </td> <td rowspan="2">3.8 </td> <td rowspan="2">650–1300 </td> <td><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku35"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/70846.html">3840QM</a> </th> <td>2.8 </td> <td rowspan="6">45 W </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku34"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64889.html">3820QM</a> </th> <td rowspan="2">2.7 </td> <td rowspan="2">3.7 </td> <td>650–1250 </td> <td><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku33"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/70847.html">3740QM</a> </th> <td>650–1300 </td> <td rowspan="8">6 MB </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku32"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64891.html">3720QM</a> </th> <td>2.6 </td> <td>3.6 </td> <td>650–1250 </td> <td><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku31"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71460.html">3635QM</a> </th> <td rowspan="2">2.4 </td> <td rowspan="2">3.4 </td> <td>650–1200 </td> <td rowspan="2"><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku30"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71459.html">3630QM</a> </th> <td rowspan="2">650–1150 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku29"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71458.html">3632QM</a> </th> <td>2.2 </td> <td>3.2 </td> <td>35 W </td> <td><span data-sort-value="000000002012-10-01-0000" style="white-space:nowrap">October 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku28"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64900.html">3615QM</a> </th> <td rowspan="2">2.3 </td> <td rowspan="2">3.3 </td> <td>650–1200 </td> <td rowspan="2">45 W </td> <td rowspan="3"><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku27"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64899.html">3610QM</a> </th> <td rowspan="2">650–1100 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/67356.html">3612QM</a> </th> <td>2.1 </td> <td>3.1 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71258.html">3687U</a> </th> <td rowspan="25">2 (4) </td> <td>2.1 </td> <td>3.3 </td> <td>350–1200 </td> <td rowspan="7">4 MB </td> <td>17 W </td> <td rowspan="2"><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72015.html">3689Y</a> </th> <td>1.5 </td> <td>2.6 </td> <td>350–850 </td> <td>13 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64898.html">3667U</a> </th> <td>2.0 </td> <td>3.2 </td> <td>350–1150 </td> <td>17 W </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71255.html">3540M</a> </th> <td>3.0 </td> <td>3.7 </td> <td>650–1300 </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72054.html">3537U</a> </th> <td>2.0 </td> <td>3.1 </td> <td>350–1200 </td> <td>17 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64893.html">3520M</a> </th> <td>2.9 </td> <td>3.6 </td> <td>650–1250 </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65714.html">3517U</a> </th> <td rowspan="2">1.9 </td> <td>3.0 </td> <td>350–1150 </td> <td rowspan="2">17 W </td></tr> <tr> <th rowspan="12">Core i5 </th> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71259.html">3437U</a> </th> <td>2.9 </td> <td>650–1200 </td> <td rowspan="18">3 MB </td> <td rowspan="2"><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72014.html">3439Y</a> </th> <td>1.5 </td> <td>2.3 </td> <td>350–850 </td> <td>13 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64903.html">3427U</a> </th> <td>1.8 </td> <td>2.8 </td> <td>350–1150 </td> <td>17 W </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71256.html">3380M</a> </th> <td>2.9 </td> <td>3.6 </td> <td>650–1250 </td> <td rowspan="3">35 W </td> <td><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64895.html">3360M</a> </th> <td>2.8 </td> <td>3.5 </td> <td>650–1200 </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71257.html">3340M</a> </th> <td>2.7 </td> <td>3.4 </td> <td>650–1250 </td> <td rowspan="3"><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72055.html">3337U</a> </th> <td>1.8 </td> <td>2.7 </td> <td>350–1100 </td> <td>17 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72013.html">3339Y</a> </th> <td>1.5 </td> <td>2.0 </td> <td>350–850 </td> <td>13 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/64896.html">3320M</a> </th> <td>2.6 </td> <td>3.3 </td> <td>650–1200 </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65707.html">3317U</a> </th> <td>1.7 </td> <td>2.6 </td> <td>350–1050 </td> <td>17 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72056.html">3230M</a> </th> <td>2.6 </td> <td>3.2 </td> <td rowspan="2">650–1100 </td> <td rowspan="2">35 W </td> <td><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65708.html">3210M</a> </th> <td>2.5 </td> <td>3.1 </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th rowspan="6">Core i3 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72057.html">3227U</a> </th> <td>1.9 </td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–1100 </td> <td>17 W </td> <td rowspan="2"><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72012.html">3229Y</a> </th> <td>1.4 </td> <td>350–850 </td> <td>13 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65697.html">3217U</a> </th> <td>1.8 </td> <td>350–1050 </td> <td>17 W </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/72058.html">3130M</a> </th> <td>2.6 </td> <td rowspan="2">650–1100 </td> <td rowspan="3">35 W </td> <td><span data-sort-value="000000002013-01-01-0000" style="white-space:nowrap">January 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/71465.html">3120M</a> </th> <td>2.5 </td> <td><span data-sort-value="000000002012-09-01-0000" style="white-space:nowrap">September 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65700.html">3110M</a> </th> <td>2.4 </td> <td>650–1000 </td> <td><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(4th_gen)_2"><span id="Core_i_.284th_gen.29_2"></span>Core i (4th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=86" title="Edit section: Core i (4th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Haswell-MB">Haswell-MB<span class="anchor" id=""Haswell-MB"_(22_nm)"></span><span class="anchor" id=""Haswell-MB"_(dual-core,_22_nm)"></span><span class="anchor" id=""Haswell-MB"_(quad-core,_22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=87" title="Edit section: Haswell-MB"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Intel_Socket_G3" title="Intel Socket G3">G3</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of PCIe. i5 and i7 models support it at <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> speeds, while i3 models support it at PCIe 2.0 speeds.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>MX-suffix models have an unlocked multiplier and can be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="12">Core i7 </th> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78940.html">4940MX</a> </th> <td rowspan="10">4 (8) </td> <td>3.1 </td> <td>4.0 </td> <td rowspan="22"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4600</a> </td> <td rowspan="2">400–1350 </td> <td rowspan="4">8 MB </td> <td rowspan="2">57 W </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75133.html">4930MX</a> </th> <td>3.0 </td> <td rowspan="2">3.9 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78939.html">4910MQ</a> </th> <td>2.9 </td> <td rowspan="4">400–1300 </td> <td rowspan="5">47 W </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75131.html">4900MQ</a> </th> <td rowspan="2">2.8 </td> <td rowspan="2">3.8 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78937.html">4810MQ</a> </th> <td rowspan="6">6 MB </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75128.html">4800MQ</a> </th> <td>2.7 </td> <td>3.7 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78931.html">4710MQ</a> </th> <td>2.5 </td> <td>3.5 </td> <td rowspan="4">400–1150 </td> <td rowspan="2"><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78933.html">4712MQ</a> </th> <td>2.3 </td> <td>3.3 </td> <td>37 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75117.html">4700MQ</a> </th> <td>2.4 </td> <td>3.4 </td> <td>47 W </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75119.html">4702MQ</a> </th> <td>2.2 </td> <td>3.2 </td> <td rowspan="13">37 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80345.html">4610M</a> </th> <td rowspan="12">2 (4) </td> <td>3.0 </td> <td>3.7 </td> <td rowspan="2">400–1300 </td> <td rowspan="2">4 MB </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76349.html">4600M</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">3.6 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th rowspan="6">Core i5 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80344.html">4340M</a> </th> <td rowspan="4">400–1250 </td> <td rowspan="10">3 MB </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76750.html">4330M</a> </th> <td>2.8 </td> <td>3.5 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80373.html">4310M</a> </th> <td>2.7 </td> <td>3.4 </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76347.html">4300M</a> </th> <td rowspan="2">2.6 </td> <td>3.3 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81012.html">4210M</a> </th> <td>3.2 </td> <td rowspan="2">400–1150 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76348.html">4200M</a> </th> <td>2.5 </td> <td>3.1 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77483.html">4110M</a> </th> <td>2.6 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">400–1100 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76346.html">4100M</a> </th> <td rowspan="2">2.5 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2">4010M<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </th> <td>Q3 2014 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75104.html">4000M</a> </th> <td>2.4 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Haswell-ULT">Haswell-ULT<span class="anchor" id=""Haswell-ULT"_(SiP,_22_nm)"></span><span class="anchor" id=""Haswell-ULT"_(SiP,_dual-core,_22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=88" title="Edit section: Haswell-ULT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1168.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a> except i3-4xx5U models, which provide 10 lanes of PCIe 2.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="7">Core i7 </th> <th style="text-align:left;" data-sort-value="sku26"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75114.html">4650U</a> </th> <td rowspan="26">2 (4) </td> <td>1.7 </td> <td rowspan="2">3.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 5000</a> </td> <td rowspan="2">200–1100 </td> <td rowspan="7">4 MB </td> <td rowspan="2">15 W </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku25"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76616.html">4600U</a> </th> <td>2.1 </td> <td><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4400</a> </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku24"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83506.html">4578U</a> </th> <td>3.0 </td> <td>3.5 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">Iris 5100</a> </td> <td rowspan="2">200–1200 </td> <td rowspan="2">28 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku23"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75992.html">4558U</a> </th> <td>2.8 </td> <td>3.3 </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku22"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75112.html">4550U</a> </th> <td>1.5 </td> <td>3.0 </td> <td>HD 5000 </td> <td rowspan="6">200–1100 </td> <td rowspan="6">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku21"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81015.html">4510U</a> </th> <td>2.0 </td> <td>3.1 </td> <td rowspan="2">HD 4400 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku20"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75460.html">4500U</a> </th> <td>1.8 </td> <td rowspan="2">3.0 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th rowspan="12">Core i5 </th> <th style="text-align:left;" data-sort-value="sku19"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75034.html">4360U</a> </th> <td>1.5 </td> <td rowspan="2">HD 5000 </td> <td rowspan="19">3 MB </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75033.html">4350U</a> </th> <td>1.4 </td> <td>2.9 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80343.html">4310U</a> </th> <td>2.0 </td> <td>3.0 </td> <td>HD 4400 </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83507.html">4308U</a> </th> <td>2.8 </td> <td>3.3 </td> <td>Iris 5100 </td> <td>200–1200 </td> <td>28 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76308.html">4300U</a> </th> <td>1.9 </td> <td>2.9 </td> <td>HD 4400 </td> <td>200–1100 </td> <td>15 W </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75991.html">4288U</a> </th> <td rowspan="2">2.6 </td> <td rowspan="2">3.1 </td> <td rowspan="2">Iris 5100 </td> <td>200–1200 </td> <td rowspan="2">28 W </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83508.html">4278U</a> </th> <td>200–1100 </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75030.html">4260U</a> </th> <td>1.4 </td> <td>2.7 </td> <td>HD 5000 </td> <td>200–1000 </td> <td>15 W </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75990.html">4258U</a> </th> <td>2.4 </td> <td>2.9 </td> <td>Iris 5100 </td> <td>200–1100 </td> <td>28 W </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75028.html">4250U</a> </th> <td>1.3 </td> <td>2.6 </td> <td>HD 5000 </td> <td rowspan="3">200–1000 </td> <td rowspan="3">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81016.html">4210U</a> </th> <td>1.7 </td> <td>2.7 </td> <td rowspan="2">HD 4400 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75459.html">4200U</a> </th> <td>1.6 </td> <td>2.6 </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th rowspan="7">Core i3 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75989.html">4158U</a> </th> <td rowspan="2">2.0 </td> <td rowspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>Iris 5100 </td> <td>200–1100 </td> <td>28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81017.html">4120U</a> </th> <td rowspan="6">HD 4400 </td> <td rowspan="3">200–1000 </td> <td rowspan="6">15 W </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75110.html">4100U</a> </th> <td>1.8 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81018.html">4030U</a> </th> <td rowspan="2">1.9 </td> <td rowspan="2"><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81019.html">4025U</a> </th> <td>200–950 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75107.html">4010U</a> </th> <td rowspan="2">1.7 </td> <td>200–1000 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75105.html">4005U</a> </th> <td>200–950 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Haswell-ULX">Haswell-ULX<span class="anchor" id=""Haswell-ULX"_(SiP,_22_nm)"></span><span class="anchor" id=""Haswell-ULX"_(SiP,_dual-core,_22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=89" title="Edit section: Haswell-ULX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1168.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76618.html">4610Y</a> </th> <td rowspan="11">2 (4) </td> <td>1.7 </td> <td>2.9 </td> <td rowspan="11"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4200</a> </td> <td rowspan="11">200–850 </td> <td>4 MB </td> <td rowspan="11">11.5 W </td> <td rowspan="3"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th rowspan="6">Core i5 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76613.html">4302Y</a> </th> <td rowspan="3">1.6 </td> <td rowspan="2">2.3 </td> <td rowspan="10">3 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76612.html">4300Y</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81020.html">4220Y</a> </th> <td>2.0 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76611.html">4210Y</a> </th> <td>1.5 </td> <td>1.9 </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76610.html">4202Y</a> </th> <td>1.6 </td> <td>2.0 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75802.html">4200Y</a> </th> <td>1.4 </td> <td>1.9 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/81021.html">4030Y</a> </th> <td>1.6 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76609.html">4020Y</a> </th> <td rowspan="2">1.5 </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76608.html">4012Y</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75988.html">4010Y</a> </th> <td>1.3 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Haswell-H_2">Haswell-H<span class="anchor" id=""Haswell-H"_(dual-core,_22_nm)"></span><span class="anchor" id=""Haswell-H"_(MCP,_quad-core,_22_nm)"></span><span class="anchor" id=""Haswell-H"_(MCP,_quad-core,_(22_nm)_2"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=90" title="Edit section: Haswell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1364.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 5200 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li> <li>i7-4950HQ comes with an unlocked multiplier, allowing for users to overclock it beyond the factory set clock speed.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="15">Core i7 </th> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83503.html">4980HQ</a> </th> <td rowspan="15">4 (8) </td> <td>2.8 </td> <td>4.0 </td> <td rowspan="9"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">Iris Pro 5200</a> </td> <td rowspan="3">200–1300 </td> <td rowspan="15">6 MB </td> <td rowspan="10">47 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76088.html">4960HQ</a> </th> <td>2.6 </td> <td>3.8 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76085.html">4950HQ</a> </th> <td>2.4 </td> <td>3.6 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83504.html">4870HQ</a> </th> <td>2.5 </td> <td>3.7 </td> <td rowspan="6">200–1200 </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76089.html">4860HQ</a> </th> <td>2.4 </td> <td>3.6 </td> <td><span data-sort-value="000000002014-02-01-0000" style="white-space:nowrap">February 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76086.html">4850HQ</a> </th> <td>2.3 </td> <td>3.5 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83505.html">4770HQ</a> </th> <td>2.2 </td> <td>3.4 </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76090.html">4760HQ</a> </th> <td>2.1 </td> <td>3.3 </td> <td><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76087.html">4750HQ</a> </th> <td>2.0 </td> <td>3.2 </td> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78934.html">4720HQ</a> </th> <td>2.6 </td> <td>3.6 </td> <td rowspan="8"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4600</a> </td> <td>400–1200 </td> <td rowspan="2"><span data-sort-value="000000002015-01-01-0000" style="white-space:nowrap">January 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78935.html">4722HQ</a> </th> <td>2.4 </td> <td>3.4 </td> <td>400–1150 </td> <td>37 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78930.html">4710HQ</a> </th> <td>2.5 </td> <td>3.5 </td> <td>400–1200 </td> <td>47 W </td> <td rowspan="2"><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78932.html">4712HQ</a> </th> <td>2.3 </td> <td>3.3 </td> <td>400–1150 </td> <td>37 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75116.html">4700HQ</a> </th> <td>2.4 </td> <td>3.4 </td> <td>400–1200 </td> <td>47 W </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75118.html">4702HQ</a> </th> <td>2.2 </td> <td>3.2 </td> <td rowspan="3">400–1150 </td> <td>37 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78929.html">4210H</a> </th> <td rowspan="2">2 (4) </td> <td>2.9 </td> <td>3.5 </td> <td rowspan="2">3 MB </td> <td rowspan="2">47 W </td> <td><span data-sort-value="000000002014-07-01-0000" style="white-space:nowrap">July 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75027.html">4200H</a> </th> <td>2.8 </td> <td>3.4 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(5th_gen)_2"><span id="Core_i_.285th_gen.29_2"></span>Core i (5th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=91" title="Edit section: Core i (5th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Broadwell-U">Broadwell-U<span class="anchor" id=""Broadwell-U"_(14_nm)"></span><span class="anchor" id=""Broadwell-U"_(dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=92" title="Edit section: Broadwell-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1168.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a> RAM, at up to 1600 MT/s speed. Models i5-5350U or above, along with all ix-5xx7 models, support LPDDR3 up to 1866 MT/s speed.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84995.html">5650U</a> </th> <td rowspan="16">2 (4) </td> <td>2.2 </td> <td rowspan="2">3.2 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">HD 6000</a> </td> <td>300–1000 </td> <td rowspan="5">4 MB </td> <td rowspan="2">15 W </td> <td rowspan="12"><span data-sort-value="000000002015-01-01-0000" style="white-space:nowrap">January 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/85215.html">5600U</a> </th> <td>2.6 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">HD 5500</a> </td> <td>300–950 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84993.html">5557U</a> </th> <td>3.1 </td> <td>3.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">Iris 6100</a> </td> <td>300–1100 </td> <td>28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84992.html">5550U</a> </th> <td>2.0 </td> <td rowspan="2">3.0 </td> <td>HD 6000 </td> <td>300–1000 </td> <td rowspan="4">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/85214.html">5500U</a> </th> <td>2.4 </td> <td>HD 5500 </td> <td>300–950 </td></tr> <tr> <th rowspan="6">Core i5 </th> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84990.html">5350U</a> </th> <td>1.8 </td> <td rowspan="2">2.9 </td> <td>HD 6000 </td> <td>300–1000 </td> <td rowspan="11">3 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/85213.html">5300U</a> </th> <td>2.3 </td> <td>HD 5500 </td> <td>300–900 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84988.html">5287U</a> </th> <td>2.9 </td> <td>3.3 </td> <td rowspan="2">Iris 6100 </td> <td>300–1100 </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84985.html">5257U</a> </th> <td>2.7 </td> <td>3.1 </td> <td>300–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84984.html">5250U</a> </th> <td>1.6 </td> <td rowspan="2">2.7 </td> <td>HD 6000 </td> <td>300–1000 </td> <td rowspan="2">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/85212.html">5200U</a> </th> <td>2.2 </td> <td>HD 5500 </td> <td>300–900 </td></tr> <tr> <th rowspan="5">Core i3 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84982.html">5157U</a> </th> <td>2.5 </td> <td rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>Iris 6100 </td> <td>300–1000 </td> <td>28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84699.html">5020U</a> </th> <td>2.2 </td> <td rowspan="4">HD 5500 </td> <td>300–900 </td> <td rowspan="4">15 W </td> <td rowspan="2"><span data-sort-value="000000002015-03-01-0000" style="white-space:nowrap">March 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84698.html">5015U</a> </th> <td rowspan="2">2.1 </td> <td>300–850 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84697.html">5010U</a> </th> <td>300–900 </td> <td rowspan="2"><span data-sort-value="000000002015-01-01-0000" style="white-space:nowrap">January 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84695.html">5005U</a> </th> <td>2.0 </td> <td>300–850 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Broadwell-H_2">Broadwell-H<span class="anchor" id=""Broadwell-H"_(dual-core,_14_nm)"></span><span class="anchor" id=""Broadwell-H"_(MCP,_quad-core,_14_nm)"></span><span class="anchor" id=""Broadwell-H"_([[Multi-chip_package|MCP]],_quad-core,_14_nm)_2"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=93" title="Edit section: Broadwell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1364.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a> RAM, at up to 1866 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 6200 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87720.html">5950HQ</a> </th> <td rowspan="4">4 (8) </td> <td>2.9 </td> <td>3.7 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">Iris Pro 6200</a> </td> <td>300–1150 </td> <td rowspan="4">6 MB </td> <td rowspan="5">47 W </td> <td rowspan="5"><span data-sort-value="000000002015-06-01-0000" style="white-space:nowrap">June 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87719.html">5850HQ</a> </th> <td>2.7 </td> <td>3.6 </td> <td>300–1100 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87717.html">5750HQ</a> </th> <td>2.5 </td> <td>3.4 </td> <td rowspan="3">300–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87716.html">5700HQ</a> </th> <td>2.7 </td> <td rowspan="2">3.5 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">HD 5600</a> </td></tr> <tr> <th rowspan="1">Core i5 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/87713.html">5350H</a> </th> <td>2 (4) </td> <td>3.1 </td> <td>Iris Pro 6200 </td> <td>4 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_M_(5th_gen)"><span id="Core_M_.285th_gen.29"></span>Core M (5th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=94" title="Edit section: Core M (5th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Broadwell-Y">Broadwell-Y<span class="anchor" id=""Broadwell-Y"_(SoC,_dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=95" title="Edit section: Broadwell-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1234.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>, <a href="/w/index.php?title=DDR3L-RS&action=edit&redlink=1" class="new" title="DDR3L-RS (page does not exist)">DDR3L-RS</a> or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="7">Core M </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84672.html">5Y71</a> </th> <td rowspan="7">2 (4) </td> <td>1.2 </td> <td>2.9 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">HD 5300</a> </td> <td>300–900 </td> <td rowspan="7">4 MB </td> <td rowspan="7">4.5 W </td> <td><span data-sort-value="000000002014-10-01-0000" style="white-space:nowrap">October 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83612.html">5Y70</a> </th> <td rowspan="2">1.1 </td> <td rowspan="2">2.6 </td> <td>100–850 </td> <td><span data-sort-value="000000002014-09-01-0000" style="white-space:nowrap">September 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84669.html">5Y51</a> </th> <td>300–900 </td> <td rowspan="3"><span data-sort-value="000000002014-10-01-0000" style="white-space:nowrap">October 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/84666.html">5Y31</a> </th> <td>0.9 </td> <td>2.4 </td> <td>300–850 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/85234.html">5Y10c</a> </th> <td rowspan="3">0.8 </td> <td rowspan="3">2.0 </td> <td>300–800 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83610.html">5Y10a</a> </th> <td rowspan="2">100–800 </td> <td rowspan="2"><span data-sort-value="000000002014-09-01-0000" style="white-space:nowrap">September 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/83611.html">5Y10</a> </th></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(6th_gen)_2"><span id="Core_i_.286th_gen.29_2"></span>Core i (6th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=96" title="Edit section: Core i (6th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Skylake-U">Skylake-U<span class="anchor" id=""Skylake-U"_(14_nm)"></span><span class="anchor" id=""Skylake-U"_(dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=97" title="Edit section: Skylake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1356.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133, <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="7">Core i7 </th> <th style="text-align:left;" data-sort-value="sku18"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91169.html">6660U</a> </th> <td rowspan="18">2 (4) </td> <td>2.4 </td> <td rowspan="3">3.4 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">Iris 540</a> </td> <td rowspan="3">300–1050 </td> <td rowspan="7">4 MB </td> <td rowspan="3">15 W </td> <td><span data-sort-value="000000002016-03-01-0000" style="white-space:nowrap">March 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku17"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91497.html">6650U</a> </th> <td>2.2 </td> <td rowspan="5"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku16"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88192.html">6600U</a> </th> <td>2.6 </td> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 520</a> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91167.html">6567U</a> </th> <td>3.3 </td> <td>3.6 </td> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">Iris 550</a> </td> <td>300–1100 </td> <td>28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91163.html">6560U</a> </th> <td>2.2 </td> <td>3.2 </td> <td>Iris 540 </td> <td rowspan="3">300–1050 </td> <td rowspan="5">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88194.html">6500U</a> </th> <td rowspan="2">2.5 </td> <td rowspan="3">3.1 </td> <td>HD 520 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93430.html">6498DU</a> </th> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 510</a> </td> <td><span data-sort-value="000000002015-12-01-0000" style="white-space:nowrap">December 2015</span> </td></tr> <tr> <th rowspan="7">Core i5 </th> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91156.html">6360U</a> </th> <td>2.0 </td> <td>Iris 540 </td> <td rowspan="2">300–1000 </td> <td rowspan="2">3 MB </td> <td rowspan="6"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88190.html">6300U</a> </th> <td>2.4 </td> <td>3.0 </td> <td>HD 520 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91164.html">6287U</a> </th> <td>3.1 </td> <td>3.5 </td> <td rowspan="2">Iris 550 </td> <td>300–1100 </td> <td rowspan="3">4 MB </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91166.html">6267U</a> </th> <td>2.9 </td> <td>3.3 </td> <td>300–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91160.html">6260U</a> </th> <td>1.8 </td> <td>2.9 </td> <td>Iris 540 </td> <td>300–950 </td> <td rowspan="3">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88193.html">6200U</a> </th> <td rowspan="2">2.3 </td> <td rowspan="2">2.8 </td> <td>HD 520 </td> <td rowspan="5">300–1000 </td> <td rowspan="6">3 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93432.html">6198DU</a> </th> <td>HD 510 </td> <td rowspan="2"><span data-sort-value="000000002015-12-01-0000" style="white-space:nowrap">December 2015</span> </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91154.html">6167U</a> </th> <td>2.7 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">Iris 550 </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96484.html">6157U</a> </th> <td>2.4 </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88180.html">6100U</a> </th> <td>2.3 </td> <td rowspan="2">HD 520 </td> <td rowspan="2">15 W </td> <td><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91157.html">6006U</a> </th> <td>2.0 </td> <td>300–900 </td> <td><span data-sort-value="000000002016-11-01-0000" style="white-space:nowrap">November 2016</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Skylake-H_2">Skylake-H<span class="anchor" id=""Skylake-H"_(14_nm)"></span><span class="anchor" id=""Skylake-H"_(quad-core,_14_nm)"></span><span class="anchor" id=""Skylake-H"_(MCP,_quad-core,_14_nm)"></span><span class="anchor" id=""Skylake-H"_(MCP,_quad-core,_14_nm)_2"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=98" title="Edit section: Skylake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133, <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 580 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="7">Core i7 </th> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93336.html">6970HQ</a> </th> <td rowspan="7">4 (8) </td> <td>2.8 </td> <td>3.7 </td> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">Iris Pro 580</a> </td> <td rowspan="2">350–1050 </td> <td rowspan="5">8 MB </td> <td rowspan="10">45 W </td> <td><span data-sort-value="000000002016-01-01-0000" style="white-space:nowrap">January 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88972.html">6920HQ</a> </th> <td>2.9 </td> <td>3.8 </td> <td><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 530</a> </td> <td><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93340.html">6870HQ</a> </th> <td rowspan="3">2.7 </td> <td rowspan="3">3.6 </td> <td>Iris Pro 580 </td> <td>350–1000 </td> <td><span data-sort-value="000000002016-01-01-0000" style="white-space:nowrap">January 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88970.html">6820HQ</a> </th> <td rowspan="2">HD 530 </td> <td rowspan="2">350–1050 </td> <td rowspan="2"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88969.html">6820HK</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93341.html">6770HQ</a> </th> <td rowspan="3">2.6 </td> <td rowspan="3">3.5 </td> <td>Iris Pro 580 </td> <td>350–950 </td> <td rowspan="5">6 MB </td> <td><span data-sort-value="000000002016-01-01-0000" style="white-space:nowrap">January 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88967.html">6700HQ</a> </th> <td rowspan="2">HD 530 </td> <td>350–1050 </td> <td rowspan="2"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88962.html">6440HQ</a> </th> <td rowspan="3">4 (4) </td> <td>350–950 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/93335.html">6350HQ</a> </th> <td rowspan="2">2.3 </td> <td rowspan="2">3.2 </td> <td>Iris Pro 580 </td> <td>350–900 </td> <td><span data-sort-value="000000002016-02-01-0000" style="white-space:nowrap">February 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88959.html">6300HQ</a> </th> <td rowspan="2">HD 530 </td> <td>350–950 </td> <td rowspan="2"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/89063.html">6100H</a> </th> <td>2 (4) </td> <td>2.7 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–900 </td> <td>3 MB </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_M_(6th_gen)"><span id="Core_M_.286th_gen.29"></span>Core M (6th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=99" title="Edit section: Core M (6th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Skylake-Y">Skylake-Y<span class="anchor" id=""Skylake-Y"_(SoC,_dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=100" title="Edit section: Skylake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1515.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core m7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88199.html">6Y75</a> </th> <td rowspan="4">2 (4) </td> <td>1.2 </td> <td>3.1 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 515</a> </td> <td>300–1000 </td> <td rowspan="4">4 MB </td> <td rowspan="4">4.5 W </td> <td rowspan="4"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th rowspan="2">Core m5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88197.html">6Y57</a> </th> <td rowspan="2">1.1 </td> <td>2.8 </td> <td rowspan="2">300–900 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88202.html">6Y54</a> </th> <td>2.7 </td></tr> <tr> <th>Core m3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88198.html">6Y30</a> </th> <td>0.9 </td> <td>2.2 </td> <td>300–850 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(7th_gen)_2"><span id="Core_i_.287th_gen.29_2"></span>Core i (7th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=101" title="Edit section: Core i (7th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-U">Kaby Lake-U<span class="anchor" id=""Kaby_Lake-U"_(14_nm)"></span><span class="anchor" id=""Kaby_Lake-U"_(dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=102" title="Edit section: Kaby Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1356.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133, <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97537.html">7660U</a> </th> <td rowspan="15">2 (4) </td> <td>2.5 </td> <td>4.0 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">Iris Plus 640</a> </td> <td>300–1100 </td> <td rowspan="6">4 MB </td> <td rowspan="2">15 W </td> <td rowspan="4"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97466.html">7600U</a> </th> <td>2.8 </td> <td>3.9 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 620</a> </td> <td rowspan="2">300–1150 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97541.html">7567U</a> </th> <td>3.5 </td> <td>4.0 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">Iris Plus 650</a> </td> <td>28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97540.html">7560U</a> </th> <td>2.4 </td> <td>3.8 </td> <td>Iris Plus 640 </td> <td rowspan="2">300–1050 </td> <td rowspan="4">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95451.html">7500U</a> </th> <td>2.7 </td> <td>3.5 </td> <td>HD 620 </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr> <tr> <th rowspan="6">Core i5 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97535.html">7360U</a> </th> <td>2.3 </td> <td>3.6 </td> <td>Iris Plus 640 </td> <td>300–1000 </td> <td rowspan="5"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97472.html">7300U</a> </th> <td>2.6 </td> <td>3.5 </td> <td>HD 620 </td> <td rowspan="2">300–1100 </td> <td>3 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97531.html">7287U</a> </th> <td>3.3 </td> <td>3.7 </td> <td rowspan="2">Iris Plus 650 </td> <td rowspan="3">4 MB </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97528.html">7267U</a> </th> <td>3.1 </td> <td>3.5 </td> <td>300–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97539.html">7260U</a> </th> <td>2.2 </td> <td>3.4 </td> <td>Iris Plus 640 </td> <td>300–950 </td> <td rowspan="2">15 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95443.html">7200U</a> </th> <td>2.5 </td> <td>3.1 </td> <td>HD 620 </td> <td rowspan="5">300–1000 </td> <td rowspan="5">3 MB </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97666.html">7167U</a> </th> <td>2.8 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>Iris Plus 650 </td> <td>28 W </td> <td><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/124977.html">7130U</a> </th> <td>2.7 </td> <td rowspan="3">HD 620 </td> <td rowspan="3">15 W </td> <td><span data-sort-value="000000002017-06-01-0000" style="white-space:nowrap">June 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95442.html">7100U</a> </th> <td>2.4 </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/122590.html">7020U</a> </th> <td>2.3 </td> <td>Q2 2018 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-H">Kaby Lake-H<span class="anchor" id=""Kaby_Lake-H"_(14_nm)"></span><span class="anchor" id=""Kaby_Lake-H"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=103" title="Edit section: Kaby Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400, <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97462.html">7920HQ</a> </th> <td rowspan="4">4 (8) </td> <td>3.1 </td> <td>4.1 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 630</a> </td> <td rowspan="4">350–1100 </td> <td rowspan="3">8 MB </td> <td rowspan="6">45 W </td> <td rowspan="7"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97464.html">7820HK</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">3.9 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97496.html">7820HQ</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97185.html">7700HQ</a> </th> <td rowspan="2">2.8 </td> <td rowspan="2">3.8 </td> <td rowspan="3">6 MB </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97459.html">7440HQ</a> </th> <td rowspan="2">4 (4) </td> <td rowspan="2">300–1000 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97456.html">7300HQ</a> </th> <td>2.5 </td> <td>3.5 </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97126.html">7100H</a> </th> <td>2 (4) </td> <td>3.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>300–950 </td> <td>3 MB </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-Y">Kaby Lake-Y<span class="anchor" id=""Kaby_Lake-Y"_(dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=104" title="Edit section: Kaby Lake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1515.</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95441.html">7Y75</a> </th> <td rowspan="3">2 (4) </td> <td>1.3 </td> <td>3.6 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 615</a> </td> <td>300–1050 </td> <td rowspan="3">4 MB </td> <td rowspan="3">4.5 W </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97461.html">7Y57</a> </th> <td rowspan="2">1.2 </td> <td>3.3 </td> <td rowspan="2">300–950 </td> <td><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95452.html">7Y54</a> </th> <td>3.2 </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_M_(7th_gen)"><span id="Core_M_.287th_gen.29"></span>Core M (7th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=105" title="Edit section: Core M (7th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-Y_2">Kaby Lake-Y<span class="anchor" id=""Kaby_Lake-Y"_(SoC,_dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=106" title="Edit section: Kaby Lake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Core m5 and Core m7 models were rebranded as <a href="#"Kaby_Lake-Y"_(dual-core,_14_nm)">Core i5</a> and <a href="#"Kaby_Lake-Y"_(dual-core,_14_nm)">Core i7</a>. </p><p>Common features: </p> <ul><li>Socket: BGA 1515.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core m3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97538.html">7Y32</a> </th> <td rowspan="2">2 (4) </td> <td>1.1 </td> <td>3.0 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 615</a> </td> <td rowspan="2">300–900 </td> <td rowspan="2">4 MB </td> <td rowspan="2">4.5 W </td> <td><span data-sort-value="000000002017-04-01-0000" style="white-space:nowrap">April 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/95449.html">7Y30</a> </th> <td>1.0 </td> <td>2.6 </td> <td><span data-sort-value="000000002016-09-01-0000" style="white-space:nowrap">September 2016</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(8th_gen)_2"><span id="Core_i_.288th_gen.29_2"></span>Core i (8th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=107" title="Edit section: Core i (8th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-U">Coffee Lake-U<span class="anchor" id=""Coffee_Lake-U"_(dual-core,_14_nm)"></span><span class="anchor" id=""Coffee_Lake-U"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=108" title="Edit section: Coffee Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1528.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191050.html">8569U</a> </th> <td rowspan="8">4 (8) </td> <td>2.8 </td> <td>4.7 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">Iris Plus 655</a> </td> <td rowspan="2">300–1200 </td> <td rowspan="3">8 MB </td> <td rowspan="2">28 W </td> <td><span data-sort-value="000000002019-05-01-0000" style="white-space:nowrap">May 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/137979.html">8559U</a> </th> <td>2.7 </td> <td rowspan="2">4.5 </td> <td><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192996.html">8557U</a> </th> <td>1.7 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">Iris Plus 645</a> </td> <td rowspan="2">300–1150 </td> <td>15 W </td> <td><span data-sort-value="000000002019-07-01-0000" style="white-space:nowrap">July 2019</span> </td></tr> <tr> <th rowspan="5">Core i5 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191070.html">8279U</a> </th> <td>2.4 </td> <td>4.1 </td> <td rowspan="2">Iris Plus 655 </td> <td rowspan="5">6 MB </td> <td rowspan="2">28 W </td> <td><span data-sort-value="000000002019-05-01-0000" style="white-space:nowrap">May 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/137980.html">8269U</a> </th> <td>2.6 </td> <td>4.2 </td> <td rowspan="2">300–1100 </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198389.html">8260U</a> </th> <td>1.6 </td> <td>3.9 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td>15 W </td> <td>Q4 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/135935.html">8259U</a> </th> <td>2.3 </td> <td>3.8 </td> <td>Iris Plus 655 </td> <td rowspan="2">300–1050 </td> <td>28 W </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191067.html">8257U</a> </th> <td>1.4 </td> <td rowspan="2">3.9 </td> <td>Iris Plus 645 </td> <td>15 W </td> <td><span data-sort-value="000000002019-07-01-0000" style="white-space:nowrap">July 2019</span> </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198391.html">8140U</a> </th> <td rowspan="2">2 (4) </td> <td>2.1 </td> <td>UHD 620 </td> <td>300–1000 </td> <td rowspan="2">4 MB </td> <td>15 W </td> <td>Q4 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/135936.html">8109U</a> </th> <td>3.0 </td> <td>3.6 </td> <td>Iris Plus 655 </td> <td>300–1050 </td> <td>28 W </td> <td><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-H">Coffee Lake-H<span class="anchor" id=""Coffee_Lake-H"_(quad-core,_14_nm)"></span><span class="anchor" id=""Coffee_Lake-H"_(hexa-core,_14_nm)"></span><span class="anchor" id="Coffee_Lake-H_(14_nm,_8th/9th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=109" title="Edit section: Coffee Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the 9th generation refresh, see section <a href="#Coffee_Lake-H_(refresh)">§ Coffee Lake-H (refresh)</a> below.</div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM. Models i5-8300H and above also support <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i9 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134903.html">8950HK</a> </th> <td rowspan="3">6 (12) </td> <td>2.9 </td> <td>4.8 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td>350–1200 </td> <td>12 MB </td> <td rowspan="6">45 W </td> <td rowspan="5"><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134899.html">8850H</a> </th> <td>2.6 </td> <td>4.3 </td> <td>350–1150 </td> <td rowspan="2">9 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134906.html">8750H</a> </th> <td>2.2 </td> <td>4.1 </td> <td rowspan="2">350–1100 </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134877.html">8400H</a> </th> <td rowspan="2">4 (8) </td> <td>2.5 </td> <td>4.2 </td> <td rowspan="2">8 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134876.html">8300H</a> </th> <td>2.3 </td> <td>4.0 </td> <td rowspan="2">350–1000 </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/149160.html">8100H</a> </th> <td>4 (4) </td> <td>3.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>6 MB </td> <td><span data-sort-value="000000002018-07-01-0000" style="white-space:nowrap">July 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-B">Coffee Lake-B<span class="anchor" id=""Coffee_Lake-B"_(quad-core,_14_nm)"></span><span class="anchor" id=""Coffee_Lake-B"_(hexa-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=110" title="Edit section: Coffee Lake-B"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134905.html">8700B</a> </th> <td>6 (12) </td> <td>3.2 </td> <td>4.6 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td>350–1200 </td> <td>12 MB </td> <td rowspan="4">65 W </td> <td rowspan="3"><span data-sort-value="000000002018-04-01-0000" style="white-space:nowrap">April 2018</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134892.html">8500B</a> </th> <td rowspan="2">6 (6) </td> <td>3.0 </td> <td>4.1 </td> <td>350–1100 </td> <td rowspan="2">9 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134888.html">8400B</a> </th> <td>2.8 </td> <td>4.0 </td> <td rowspan="2">350–1050 </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189980.html">8100B</a> </th> <td>4 (4) </td> <td>3.6 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>6 MB </td> <td>Q3 2018 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake_Refresh">Kaby Lake Refresh<span class="anchor" id=""Kaby_Lake_Refresh"_(14_nm)"></span><span class="anchor" id=""Kaby_Lake_Refresh"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=111" title="Edit section: Kaby Lake Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1356.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 12 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/124968.html">8650U</a> </th> <td rowspan="4">4 (8) </td> <td>1.9 </td> <td>4.2 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td rowspan="2">300–1150 </td> <td rowspan="2">8 MB </td> <td rowspan="5">15 W </td> <td rowspan="4"><span data-sort-value="000000002017-08-01-0000" style="white-space:nowrap">August 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/122589.html">8550U</a> </th> <td>1.8 </td> <td>4.0 </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/124969.html">8350U</a> </th> <td>1.7 </td> <td>3.6 </td> <td rowspan="2">300–1100 </td> <td rowspan="2">6 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/124967.html">8250U</a> </th> <td>1.6 </td> <td rowspan="2">3.4 </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/137977.html">8130U</a> </th> <td>2 (4) </td> <td>2.2 </td> <td>300–1000 </td> <td>4 MB </td> <td><span data-sort-value="000000002018-02-01-0000" style="white-space:nowrap">February 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-G">Kaby Lake-G<span class="anchor" id=""Kaby_Lake-G"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=112" title="Edit section: Kaby Lake-G"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 2270.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>Kaby Lake-G CPUs have an embedded discrete Radeon RX Vega M GPU as listed in the table below, which have <a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a> <a href="/wiki/VRAM" class="mw-redirect" title="VRAM">VRAM</a> also embedded on the CPU package.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th colspan="2">Embedded dGPU </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/130409.html">8809G</a> </th> <td rowspan="5">4 (8) </td> <td rowspan="4">3.1 </td> <td>4.2 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 630</a> </td> <td rowspan="4">350–1100 </td> <td rowspan="2"><a href="/wiki/Kaby_Lake#Discrete_GPU_specifications" title="Kaby Lake">RX Vega M GH</a> </td> <td rowspan="2">1063–1190 </td> <td rowspan="4">8 MB </td> <td rowspan="2">100 W </td> <td rowspan="5"><span data-sort-value="000000002018-02-01-0000" style="white-space:nowrap">February 2018</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/130407.html">8709G</a> </th> <td rowspan="3">4.1 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/130406.html">8706G</a> </th> <td rowspan="3"><a href="/wiki/Kaby_Lake#Discrete_GPU_specifications" title="Kaby Lake">RX Vega M GL</a> </td> <td rowspan="3">931–1011 </td> <td rowspan="3">65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/130411.html">8705G</a> </th></tr> <tr> <th rowspan="1">Core i5 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/130408.html">8305G</a> </th> <td>2.8 </td> <td>3.2 </td> <td>350–1000 </td> <td>6 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Amber_Lake-Y">Amber Lake-Y<span class="anchor" id=""Amber_Lake-Y"_(dual-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=113" title="Edit section: Amber Lake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the Core m3 models, see section <a href="#Amber_Lake-Y_2">§ Core M (8th gen) § Amber Lake-Y</a> below. For the 10th generation series, see section <a href="#Amber_Lake-Y_(10xxx)">§ Amber Lake-Y (10xxx)</a> below.</div> <p>Common features: </p> <ul><li>Socket: BGA 1515.</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/185281.html">8500Y</a> </th> <td rowspan="4">2 (4) </td> <td>1.5 </td> <td>4.2 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 615</a> </td> <td rowspan="3">300–1050 </td> <td rowspan="4">4 MB </td> <td>5 W </td> <td><span data-sort-value="000000002018-08-01-0000" style="white-space:nowrap">August 2018</span> </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194697.html">8310Y</a> </th> <td rowspan="2">1.6 </td> <td>3.9 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 617</a> </td> <td rowspan="2">7 W </td> <td>Q1 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189912.html">8210Y</a> </th> <td>3.6 </td> <td><span data-sort-value="000000002018-10-01-0000" style="white-space:nowrap">October 2018</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/185280.html">8200Y</a> </th> <td>1.3 </td> <td>3.9 </td> <td>UHD 615 </td> <td>300–950 </td> <td>5 W </td> <td><span data-sort-value="000000002018-08-01-0000" style="white-space:nowrap">August 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Whiskey_Lake-U">Whiskey Lake-U<span class="anchor" id=""Whiskey_Lake-U"_(dual-core,_14_nm)"></span><span class="anchor" id=""Whiskey_Lake-U"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=114" title="Edit section: Whiskey Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1528.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193563.html">8665U</a> </th> <td rowspan="4">4 (8) </td> <td>1.9 </td> <td>4.8 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td rowspan="2">300–1150 </td> <td rowspan="2">8 MB </td> <td rowspan="5">15 W </td> <td><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/149091.html">8565U</a> </th> <td>1.8 </td> <td>4.6 </td> <td><span data-sort-value="000000002018-08-01-0000" style="white-space:nowrap">August 2018</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193555.html">8365U</a> </th> <td rowspan="2">1.6 </td> <td>4.1 </td> <td rowspan="2">300–1100 </td> <td rowspan="2">6 MB </td> <td><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/149088.html">8265U</a> </th> <td rowspan="2">3.9 </td> <td rowspan="2"><span data-sort-value="000000002018-08-01-0000" style="white-space:nowrap">August 2018</span> </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/149090.html">8145U</a> </th> <td>2 (4) </td> <td>2.1 </td> <td>300–1000 </td> <td>4 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Cannon_Lake-U">Cannon Lake-U<span class="anchor" id=""Cannon_Lake-U"_(dual-core,_10_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=115" title="Edit section: Cannon Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1528.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>(x)-2400 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/136863.html">8121U</a> </th> <td>2 (4) </td> <td>2.2 </td> <td>3.2 </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4 MB </td> <td>15 W </td> <td><span data-sort-value="000000002018-05-01-0000" style="white-space:nowrap">May 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_M_(8th_gen)"><span id="Core_M_.288th_gen.29"></span>Core M (8th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=116" title="Edit section: Core M (8th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Amber_Lake-Y_2">Amber Lake-Y</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=117" title="Edit section: Amber Lake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Core m5 and Core m7 models were rebranded as Core i5 and Core i7. </p><p>Common features: </p> <ul><li>Socket: BGA 1515.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core m3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/185282.html">8100Y</a> </th> <td>2 (4) </td> <td>1.1 </td> <td>3.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 615</a> </td> <td>300–900 </td> <td>4 MB </td> <td>5 W </td> <td><span data-sort-value="000000002018-08-01-0000" style="white-space:nowrap">August 2018</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(9th_gen)_2"><span id="Core_i_.289th_gen.29_2"></span>Core i (9th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=118" title="Edit section: Core i (9th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-H_(refresh)"><span id="Coffee_Lake-H_.28refresh.29"></span>Coffee Lake-H (refresh)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=119" title="Edit section: Coffee Lake-H (refresh)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192990.html">9980HK</a> </th> <td rowspan="2">8 (16) </td> <td>2.4 </td> <td>5.0 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td>350–1250 </td> <td rowspan="2">16 MB </td> <td rowspan="8">45 W </td> <td rowspan="8"><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192987.html">9880H</a> </th> <td>2.3 </td> <td>4.8 </td> <td>350–1200 </td></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191047.html">9850H</a> </th> <td rowspan="3">6 (12) </td> <td rowspan="3">2.6 </td> <td>4.6 </td> <td rowspan="2">350–1150 </td> <td rowspan="3">12 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191045.html">9750H</a> </th> <td rowspan="2">4.5 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191046.html">9750HF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191078.html">9400H</a> </th> <td rowspan="3">4 (8) </td> <td>2.5 </td> <td>4.3 </td> <td rowspan="2">UHD 630 </td> <td>350–1100 </td> <td rowspan="3">8 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191075.html">9300H</a> </th> <td rowspan="2">2.4 </td> <td rowspan="2">4.1 </td> <td>350–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191080.html">9300HF</a> </th> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(10th_gen)_2"><span id="Core_i_.2810th_gen.29_2"></span>Core i (10th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=120" title="Edit section: Core i (10th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Comet_Lake-U">Comet Lake-U<span class="anchor" id=""Comet_Lake-U"_(dual-core,_14_nm)"></span><span class="anchor" id=""Comet_Lake-U"_(quad-core,_14_nm)"></span><span class="anchor" id=""Comet_Lake-U"_(14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=121" title="Edit section: Comet Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1528.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666, <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-2933 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196448.html">10810U</a> </th> <td rowspan="2">6 (12) </td> <td rowspan="2">1.1 </td> <td rowspan="2">4.7 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td rowspan="5">300–1150 </td> <td rowspan="2">12 MB </td> <td rowspan="7">15 W </td> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196448.html">10710U</a> </th> <td><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201896.html">10610U</a> </th> <td rowspan="4">4 (8) </td> <td rowspan="2">1.8 </td> <td rowspan="2">4.9 </td> <td rowspan="2">8 MB </td> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196449.html">10510U</a> </th> <td><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201892.html">10310U</a> </th> <td>1.7 </td> <td>4.4 </td> <td rowspan="2">6 MB </td> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195436.html">10210U</a> </th> <td>1.6 </td> <td>4.2 </td> <td>300–1100 </td> <td rowspan="2"><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196451.html">10110U</a> </th> <td>2 (4) </td> <td>2.1 </td> <td>4.1 </td> <td>300–1000 </td> <td>4 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Comet_Lake-H">Comet Lake-H<span class="anchor" id=""Comet_Lake-H"_(quad-core,_14_nm)"></span><span class="anchor" id=""Comet_Lake-H"_(14_nm)"></span><span class="anchor" id="Comet_Lake-H_(14_nm,_10th_generation)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=122" title="Edit section: Comet Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> RAM, at up to 2933 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable"><abbr title="Thermal Velocity Boost">TVB</abbr> </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201838.html">10980HK</a> </th> <td rowspan="4">8 (16) </td> <td rowspan="2">2.4 </td> <td rowspan="2">5.1 </td> <td rowspan="2">5.3 </td> <td rowspan="10"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">350–1250 </td> <td rowspan="4">16 MB </td> <td rowspan="10">45 W </td> <td><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203682.html">10885H</a> </th> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/202329.html">10875H</a> </th> <td>2.3 </td> <td>4.9 </td> <td>5.1 </td> <td rowspan="2">350–1200 </td> <td><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208018.html">10870H</a> </th> <td>2.2 </td> <td>4.8 </td> <td>5.0 </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201897.html">10850H</a> </th> <td rowspan="3">6 (12) </td> <td>2.7 </td> <td>4.9 </td> <td>5.1 </td> <td rowspan="2">350–1150 </td> <td rowspan="3">12 MB </td> <td rowspan="2"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201837.html">10750H</a> </th> <td>2.6 </td> <td>4.8 </td> <td>5.0 </td></tr> <tr> <th rowspan="4">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201905.html">10500H</a> </th> <td>2.5 </td> <td>4.5 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–1050 </td> <td><span data-sort-value="000000002020-12-01-0000" style="white-space:nowrap">December 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201895.html">10400H</a> </th> <td rowspan="3">4 (8) </td> <td>2.6 </td> <td>4.6 </td> <td>350–1100 </td> <td rowspan="3">8 MB </td> <td rowspan="2"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201839.html">10300H</a> </th> <td>2.5 </td> <td>4.5 </td> <td rowspan="2">350–1050 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208016.html">10200H</a> </th> <td>2.4 </td> <td>4.1 </td> <td><span data-sort-value="000000002020-08-01-0000" style="white-space:nowrap">August 2020</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Ice_Lake-U">Ice Lake-U<span class="anchor" id=""Ice_Lake-U"_(dual-core,_10_nm)"></span><span class="anchor" id=""Ice_Lake-U"_(quad-core,_10_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=123" title="Edit section: Ice Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1526, except for models with 'N' in the name which use a smaller BGA 1344 package.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-3733 RAM.</li> <li><a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> support.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196593.html">1068NG7</a> </th> <td rowspan="7">4 (8) </td> <td rowspan="2">2.3 </td> <td rowspan="2">4.1 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">Iris Plus (G7)</a> </td> <td rowspan="3">300–1100 </td> <td rowspan="3">8 MB </td> <td rowspan="2">28 W </td> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7">1068G7<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> </th> <td rowspan="2"><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196597.html">1065G7</a> </th> <td>1.3 </td> <td>3.9 </td> <td>15 W </td></tr> <tr> <th rowspan="4">Core i5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196594.html">1038NG7</a> </th> <td>2.0 </td> <td>3.8 </td> <td rowspan="4">300–1050 </td> <td rowspan="4">6 MB </td> <td>28 W </td> <td><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196592.html">1035G7</a> </th> <td>1.2 </td> <td rowspan="2">3.7 </td> <td rowspan="4">15 W </td> <td rowspan="4"><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196591.html">1035G4</a> </th> <td>1.1 </td> <td><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">Iris Plus (G4)</a> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196603.html">1035G1</a> </th> <td>1.0 </td> <td>2.6 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">UHD Graphics (G1)</a> </td></tr> <tr> <th rowspan="1">Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196588.html">1005G1</a> </th> <td>2 (4) </td> <td>1.2 </td> <td>3.4 </td> <td>300–900 </td> <td>4 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Ice_Lake-Y">Ice Lake-Y<span class="anchor" id=""Ice_Lake-Y"_(dual-core,_10_nm)"></span><span class="anchor" id=""Ice_Lake-Y"_(quad-core,_10_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=124" title="Edit section: Ice Lake-Y"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1377, except for models with 'N' in the name which use a smaller BGA 1044 package.</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a> RAM, at up to 3733 MT/s speed.</li> <li><a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> support.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197120.html">1060G7</a> </th> <td rowspan="4">4 (8) </td> <td>1.0 </td> <td>3.8 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">Iris Plus (G7)</a> </td> <td>300–1100 </td> <td>8 MB </td> <td>9 W </td> <td>Q3 2019 </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196589.html">1030NG7</a> </th> <td>1.1 </td> <td rowspan="3">3.5 </td> <td rowspan="3">300–1050 </td> <td rowspan="3">6 MB </td> <td>10 W </td> <td>Q2 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197119.html">1030G7</a> </th> <td>0.8 </td> <td rowspan="5">9 W </td> <td rowspan="2">Q3 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197121.html">1030G4</a> </th> <td>0.7 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">Iris Plus (G4)</a> </td></tr> <tr> <th rowspan="3">Core i3 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196586.html">1000NG4</a> </th> <td rowspan="3">2 (4) </td> <td rowspan="3">1.1 </td> <td rowspan="3">3.2 </td> <td rowspan="3">300–900 </td> <td rowspan="3">4 MB </td> <td>Q2 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197123.html">1000G4</a> </th> <td rowspan="2">Q3 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197122.html">1000G1</a> </th> <td><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">UHD Graphics (G1)</a> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Amber_Lake-Y_(10xxx)"><span id="Amber_Lake-Y_.2810xxx.29"></span>Amber Lake-Y (10xxx)<span class="anchor" id=""Amber_Lake-Y"_(quad-core,_14_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=125" title="Edit section: Amber Lake-Y (10xxx)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1377, except for i3-10100Y which uses a smaller BGA package of unknown name.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM. Models i3-10110Y and up support LPDDR3 at up to 2133 MT/s speed.</li> <li>All CPU models provide 10 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="1">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196452.html">10510Y</a> </th> <td rowspan="3">4 (8) </td> <td>1.2 </td> <td>4.5 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td>300–1150 </td> <td>8 MB </td> <td rowspan="4">7 W </td> <td rowspan="4"><span data-sort-value="000000002019-08-01-0000" style="white-space:nowrap">August 2019</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196453.html">10310Y</a> </th> <td>1.1 </td> <td>4.1 </td> <td rowspan="2">300–1050 </td> <td rowspan="2">6 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196454.html">10210Y</a> </th> <td rowspan="2">1.0 </td> <td rowspan="2">4.0 </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196455.html">10110Y</a> </th> <td rowspan="2">2 (4) </td> <td rowspan="2">300–1000 </td> <td rowspan="2">4 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213356.html">10100Y</a> </th> <td>1.3 </td> <td>3.9 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 615</a> </td> <td>5 W </td> <td><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(11th_gen)_2"><span id="Core_i_.2811th_gen.29_2"></span>Core i (11th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=126" title="Edit section: Core i (11th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-UP3">Tiger Lake-UP3<span class="anchor" id=""Tiger_Lake-UP3"_(10_nm_SuperFin)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=127" title="Edit section: Tiger Lake-UP3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1449.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-3733 RAM. i5 models and up support LPDDR4X at up to 4266 MT/s speed.</li> <li>All CPU models provide 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>The base clock speed that the CPU runs at corresponds with the configurable TDP (cTDP) setting chosen.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217181.html">1195G7</a> </th> <td rowspan="7">4 (8) </td> <td>1.3–2.9 </td> <td>5.0 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1400 </td> <td rowspan="3">12 MB </td> <td rowspan="8">12–28 W </td> <td><span data-sort-value="000000002021-06-01-0000" style="white-space:nowrap">June 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208664.html">1185G7</a> </th> <td>1.2–3.0 </td> <td>4.8 </td> <td>?–1350 </td> <td rowspan="2"><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208921.html">1165G7</a> </th> <td>1.2–2.8 </td> <td>4.7 </td> <td>?–1300 </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217184.html">1155G7</a> </th> <td>1.0–2.5 </td> <td>4.5 </td> <td rowspan="3">Iris Xe<br />(80 EU) </td> <td>?–1350 </td> <td rowspan="4">8 MB </td> <td><span data-sort-value="000000002021-06-01-0000" style="white-space:nowrap">June 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208660.html">1145G7</a> </th> <td>1.1–2.6 </td> <td>4.4 </td> <td rowspan="2">?–1300 </td> <td><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208922.html">1135G7</a> </th> <td>0.9–2.4 </td> <td>4.2 </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/209735.html">1125G4</a> </th> <td>0.9–2.0 </td> <td>3.7 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td rowspan="2">?–1250 </td> <td>Q1 2021 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208652.html">1115G4</a> </th> <td>2 (4) </td> <td>1.7–3.0 </td> <td>4.1 </td> <td>6 MB </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-UP4">Tiger Lake-UP4<span class="anchor" id=""Tiger_Lake-UP4"_(10_nm_SuperFin)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=128" title="Edit section: Tiger Lake-UP4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1598.</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>The base clock speed that the CPU runs at corresponds with the configurable TDP (cTDP) setting chosen.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208663.html">1180G7</a> </th> <td rowspan="5">4 (8) </td> <td>0.9–2.2 </td> <td>4.6 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="6">?–1100 </td> <td rowspan="2">12 MB </td> <td rowspan="6">7–15 W </td> <td><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208661.html">1160G7</a> </th> <td>0.9–2.1 </td> <td>4.4 </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208659.html">1140G7</a> </th> <td rowspan="2">0.8–1.8 </td> <td>4.2 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="3">8 MB </td> <td><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208657.html">1130G7</a> </th> <td>4.0 </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/209736.html">1120G4</a> </th> <td>0.8–1.5 </td> <td>3.5 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>Q1 2021 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208651.html">1110G4</a> </th> <td>2 (4) </td> <td>1.8 </td> <td>3.9 </td> <td>6 MB </td> <td><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-H">Tiger Lake-H<span class="anchor" id=""Tiger_Lake-H"_(10_nm_SuperFin)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=129" title="Edit section: Tiger Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1598.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to 24 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>The base clock speed that the CPU runs at corresponds with the configurable TDP (cTDP) setting chosen.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i9 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213800.html">11980HK</a> </th> <td rowspan="5">8 (16) </td> <td>2.6–3.3 </td> <td rowspan="2">5.0 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="8">350–1450 </td> <td rowspan="5">24 MB </td> <td rowspan="1">45–65 W </td> <td rowspan="5"><span data-sort-value="000000002021-05-01-0000" style="white-space:nowrap">May 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213798.html">11950H</a> </th> <td>2.1–2.6 </td> <td rowspan="8">35–45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213801.html">11900H</a> </th> <td rowspan="2">2.1–2.5 </td> <td>4.9 </td></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213799.html">11850H</a> </th> <td>4.8 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213803.html">11800H</a> </th> <td>1.9–2.3 </td> <td rowspan="3">4.6 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213802.html">11600H</a> </th> <td rowspan="4">6 (12) </td> <td>2.5–2.9 </td> <td>18 MB </td> <td><span data-sort-value="000000002021-07-01-0000" style="white-space:nowrap">July 2021</span> </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213804.html">11500H</a> </th> <td>2.4–2.9 </td> <td rowspan="3">12 MB </td> <td rowspan="3"><span data-sort-value="000000002021-05-01-0000" style="white-space:nowrap">May 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213805.html">11400H</a> </th> <td>2.2–2.7 </td> <td>4.5 </td> <td rowspan="2">UHD Graphics<br />(16 EU) </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213806.html">11260H</a> </th> <td>2.1–2.6 </td> <td>4.4 </td> <td>350–1400 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-H35">Tiger Lake-H35<span class="anchor" id=""Tiger_Lake-H35"_(10_nm_SuperFin)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=130" title="Edit section: Tiger Lake-H35"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1449.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li><a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> support; 12× PCIe lanes provided by on-package PCH are revision 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>The base clock speed that the CPU runs at corresponds with the configurable TDP (cTDP) setting chosen.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217182.html">11390H</a> </th> <td rowspan="5">4 (8) </td> <td>2.9–3.4 </td> <td rowspan="2">5.0 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1400 </td> <td rowspan="3">12 MB </td> <td rowspan="5">28–35 W </td> <td><span data-sort-value="000000002021-06-01-0000" style="white-space:nowrap">June 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197384.html">11375H</a> </th> <td rowspan="2">3.0–3.3 </td> <td rowspan="3">?–1350 </td> <td rowspan="2"><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196655.html">11370H</a> </th> <td>4.8 </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217183.html">11320H</a> </th> <td>2.5–3.2 </td> <td>4.5 </td> <td rowspan="2">8 MB </td> <td><span data-sort-value="000000002021-06-01-0000" style="white-space:nowrap">June 2021</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196656.html">11300H</a> </th> <td>2.6–3.1 </td> <td>4.4 </td> <td>Iris Xe<br />(80 EU) </td> <td>?–1300 </td> <td><span data-sort-value="000000002021-01-01-0000" style="white-space:nowrap">January 2021</span> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(12th_gen)_2"><span id="Core_i_.2812th_gen.29_2"></span>Core i (12th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=131" title="Edit section: Core i (12th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-U">Alder Lake-U<span class="anchor" id=""Alder_Lake-U"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=132" title="Edit section: Alder Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1781 (ix-12x0U), BGA 1744 (ix-12x5U).</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM. ix-12x5U models also support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 and <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM in addition.</li> <li>ix-12x0 models provide 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 8 lanes of PCIe 3.0, while ix-12x5U models provide 8 lanes of PCIe 4.0 and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup></li></ul> <table class="wikitable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th>L3 Cache </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th>MB </th> <th rowspan="2" class="unsortable">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th> </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226258.html">1265U</a> </th> <td rowspan="10">2 (4) </td> <td>1.8 </td> <td>4.8 </td> <td rowspan="8">8 (8) </td> <td>1.3 </td> <td>3.6 </td> <td> </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1250 </td> <td rowspan="8">12 MB </td> <td>15 W </td> <td>55 W </td> <td rowspan="10"><span data-sort-value="000000002022-02-01-0000" style="white-space:nowrap">February 2022</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226455.html">1260U</a> </th> <td>1.6 </td> <td rowspan="3">4.7 </td> <td>0.8 </td> <td rowspan="3">3.5 </td> <td>12 </td> <td>?–950 </td> <td>9 W </td> <td>29 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226259.html">1255U</a> </th> <td>1.7 </td> <td>1.2 </td> <td> </td> <td>?–1250 </td> <td>15 W </td> <td>55 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226454.html">1250U</a> </th> <td>1.1 </td> <td>0.8 </td> <td> </td> <td>?–950 </td> <td>9 W </td> <td>29 W </td></tr> <tr> <th rowspan="4">Core i5 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226260.html">1245U</a> </th> <td>1.6 </td> <td rowspan="6">4.4 </td> <td>1.2 </td> <td rowspan="6">3.3 </td> <td> </td> <td rowspan="4">Iris Xe<br />(80 EU) </td> <td>?–1200 </td> <td>15 W </td> <td>55 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226452.html">1240U</a> </th> <td>1.1 </td> <td>0.8 </td> <td> </td> <td>?–900 </td> <td>9 W </td> <td>29 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226261.html">1235U</a> </th> <td>1.3 </td> <td>0.9 </td> <td> </td> <td>?–1200 </td> <td>15 W </td> <td>55 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226453.html">1230U</a> </th> <td>1.0 </td> <td>0.7 </td> <td> </td> <td>?–850 </td> <td>9 W </td> <td>29 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226263.html">1215U</a> </th> <td>1.2 </td> <td rowspan="2">4 (4) </td> <td>0.9 </td> <td> </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td> <td>?–1100 </td> <td rowspan="2">10 MB </td> <td>15 W </td> <td>55 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226451.html">1210U</a> </th> <td>1.0 </td> <td>0.7 </td> <td> </td> <td>?–850 </td> <td>9 W </td> <td>29 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-P">Alder Lake-P<span class="anchor" id=""Alder_Lake-P"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=133" title="Edit section: Alder Lake-P"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>The following models are available with IPU (image processing unit): <a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226266.html">i5-1235U</a>, <a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226269.html">i3-1215U</a>. Specifications between them and the respective processor without IPU are completely identical, apart from the addition of the IPU.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226253.html">1280P</a> </th> <td>6 (12) </td> <td>1.8 </td> <td rowspan="2">4.8 </td> <td rowspan="6">8 (8) </td> <td>1.3 </td> <td>3.6 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1450 </td> <td>24 MB </td> <td rowspan="6">28 W </td> <td rowspan="6">64 W </td> <td rowspan="6"><span data-sort-value="000000002022-02-01-0000" style="white-space:nowrap">February 2022</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226255.html">1270P</a> </th> <td rowspan="4">4 (8) </td> <td>2.2 </td> <td>1.6 </td> <td>3.5 </td> <td rowspan="3">?–1400 </td> <td rowspan="2">18 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226254.html">1260P</a> </th> <td>2.1 </td> <td>4.7 </td> <td>1.5 </td> <td>3.4 </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226256.html">1250P</a> </th> <td rowspan="2">1.7 </td> <td rowspan="3">4.4 </td> <td rowspan="2">1.2 </td> <td rowspan="3">3.3 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="3">12 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132221.html">1240P</a> </th> <td>?–1300 </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226257.html">1220P</a> </th> <td>2 (4) </td> <td>1.5 </td> <td>1.1 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td> <td>?–1100 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-H">Alder Lake-H<span class="anchor" id=""Alder_Lake-H"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=134" title="Edit section: Alder Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132215.html">12900HK</a> </th> <td rowspan="5">6 (12) </td> <td rowspan="2">2.5 </td> <td rowspan="2">5.0 </td> <td rowspan="4">8 (8) </td> <td rowspan="3">1.8 </td> <td rowspan="2">3.8 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1450 </td> <td rowspan="5">24 MB </td> <td rowspan="8">45 W </td> <td rowspan="5">115 W </td> <td rowspan="8"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132214.html">12900H</a> </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226059.html">12800H</a> </th> <td>2.4 </td> <td>4.8 </td> <td>3.7 </td> <td rowspan="4">?–1400 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132228.html">12700H</a> </th> <td rowspan="2">2.3 </td> <td rowspan="2">4.7 </td> <td rowspan="2">1.7 </td> <td rowspan="2">3.5 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226066.html">12650H</a> </th> <td>4 (4) </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96156.html">12600H</a> </th> <td rowspan="3">4 (8) </td> <td>2.7 </td> <td rowspan="2">4.5 </td> <td rowspan="2">8 (8) </td> <td>2.0 </td> <td rowspan="3">3.3 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="2">18 MB </td> <td rowspan="3">95 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96141.html">12500H</a> </th> <td>2.5 </td> <td>1.8 </td> <td>?–1300 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132222.html">12450H</a> </th> <td>2.0 </td> <td>4.4 </td> <td>4 (4) </td> <td>1.5 </td> <td>UHD Graphics<br />(48 EU) </td> <td>?–1200 </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-HX">Alder Lake-HX<span class="anchor" id=""Alder_Lake-HX"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=135" title="Edit section: Alder Lake-HX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1964.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 or <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of PCIe 4.0, in addition to 16 lanes of PCIe 4.0 and 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the on-package chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>The i9 models have unlocked multipliers, allowing them to be overclocked.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228439.html">12950HX</a> </th> <td rowspan="4">8 (16) </td> <td rowspan="2">2.3 </td> <td rowspan="2">5.0 </td> <td rowspan="6">8 (8) </td> <td rowspan="2">1.7 </td> <td rowspan="2">3.6 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="2">?–1550 </td> <td rowspan="2">30 MB </td> <td rowspan="7">55 W </td> <td rowspan="7">157 W </td> <td rowspan="7"><span data-sort-value="000000002022-05-01-0000" style="white-space:nowrap">May 2022</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228441.html">12900HX</a> </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228442.html">12850HX</a> </th> <td>2.1 </td> <td rowspan="2">4.8 </td> <td rowspan="3">1.5 </td> <td rowspan="2">3.4 </td> <td rowspan="3">?–1450 </td> <td rowspan="2">25 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226058.html">12800HX</a> </th> <td rowspan="2">2.0 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228795.html">12650HX</a> </th> <td>6 (12) </td> <td>4.7 </td> <td rowspan="2">3.3 </td> <td>24 MB </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228438.html">12600HX</a> </th> <td rowspan="2">4 (8) </td> <td>2.5 </td> <td>4.6 </td> <td rowspan="2">1.8 </td> <td>?–1350 </td> <td>18 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228794.html">12450HX</a> </th> <td>2.4 </td> <td>4.4 </td> <td>4 (4) </td> <td>3.1 </td> <td>UHD Graphics<br />(16 EU) </td> <td>?–1300 </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-N">Alder Lake-N<span class="anchor" id=""Alder_Lake-N"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=136" title="Edit section: Alder Lake-N"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>These are essentially "E-core-only" CPUs, utilizing the <a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> architecture. </p><p>Common features: </p> <ul><li>Socket: BGA 1264.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-4800 RAM.</li> <li>All CPU models provide 9 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 96 KB (64 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 2 MB per cluster (each "cluster" contains four cores).</li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th> <th>Base </th> <th class="unsortable">Max.<br />Turbo </th></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/231805.html">N305</a> </th> <td rowspan="2">8 (8) </td> <td>1.8 </td> <td rowspan="2">3.8 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="2">?–1250 </td> <td rowspan="2">6 MB </td> <td>15 W </td> <td>35 W </td> <td rowspan="2"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/231806.html">N300</a> </th> <td>0.8 </td> <td>7 W </td> <td>25 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(13th_gen)_2"><span id="Core_i_.2813th_gen.29_2"></span>Core i (13th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=137" title="Edit section: Core i (13th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-U">Raptor Lake-U<span class="anchor" id=""Raptor_Lake-U"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=138" title="Edit section: Raptor Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>The <a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/233459.html">i3-1315U</a> is available with IPU (image processing unit). Specifications between it and the respective processor without IPU are completely identical, apart from the addition of the IPU.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232141.html">1365U</a> </th> <td rowspan="6">2 (4) </td> <td>1.8 </td> <td>5.2 </td> <td rowspan="5">8 (8) </td> <td>1.3 </td> <td>3.9 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1300 </td> <td rowspan="5">12 MB </td> <td rowspan="7">15 W </td> <td rowspan="7">55 W </td> <td rowspan="7"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232160.html">1355U</a> </th> <td>1.7 </td> <td>5.0 </td> <td rowspan="2">1.2 </td> <td>3.7 </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232127.html">1345U</a> </th> <td>1.6 </td> <td>4.7 </td> <td>3.5 </td> <td rowspan="3">Iris Xe<br />(80 EU) </td> <td rowspan="5">?–1250 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232153.html">1335U</a> </th> <td rowspan="2">1.3 </td> <td rowspan="2">4.6 </td> <td rowspan="3">0.9 </td> <td rowspan="2">3.4 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232143.html">1334U</a> </th></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232136.html">1315U</a> </th> <td>1.2 </td> <td rowspan="2">4.5 </td> <td rowspan="2">4 (4) </td> <td rowspan="2">3.3 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td> <td rowspan="2">10 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232909.html">1305U</a> </th> <td>1 (2) </td> <td>1.6 </td> <td>1.2 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-P">Raptor Lake-P<span class="anchor" id=""Raptor_Lake-P"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=139" title="Edit section: Raptor Lake-P"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232146.html">1370P</a> </th> <td>6 (12) </td> <td>1.9 </td> <td>5.2 </td> <td rowspan="4">8 (8) </td> <td>1.4 </td> <td>3.9 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="3">?–1500 </td> <td>24 MB </td> <td rowspan="4">28 W </td> <td rowspan="4">64 W </td> <td rowspan="4"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232155.html">1360P</a> </th> <td rowspan="3">4 (8) </td> <td>2.2 </td> <td>5.0 </td> <td>1.6 </td> <td>3.7 </td> <td>18 MB </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232103.html">1350P</a> </th> <td rowspan="2">1.9 </td> <td>4.7 </td> <td rowspan="2">1.4 </td> <td>3.5 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="2">12 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232126.html">1340P</a> </th> <td>4.6 </td> <td>3.4 </td> <td>?–1450 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-H">Raptor Lake-H<span class="anchor" id=""Raptor_Lake-H"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=140" title="Edit section: Raptor Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 8 lanes of PCIe 4.0, in addition to 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>K-suffix processors have an unlocked multiplier, allowing it to be overclocked.</li> <li>The <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/233458.html">i5-13500H</a> is available with IPU (image processing unit). Specifications between it and the respective processor without IPU are completely identical, apart from the addition of the IPU.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232144.html">13900HK</a> </th> <td rowspan="5">6 (12) </td> <td rowspan="2">2.6 </td> <td rowspan="2">5.4 </td> <td rowspan="4">8 (8) </td> <td rowspan="2">1.9 </td> <td rowspan="2">4.1 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="6">?–1500 </td> <td rowspan="5">24 MB </td> <td rowspan="8">45 W </td> <td rowspan="5">115 W </td> <td rowspan="8"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232135.html">13900H</a> </th></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232164.html">13800H</a> </th> <td>2.5 </td> <td>5.2 </td> <td rowspan="3">1.8 </td> <td>4.0 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232128.html">13700H</a> </th> <td rowspan="2">2.4 </td> <td>5.0 </td> <td>3.7 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232130.html">13620H</a> </th> <td>4.9 </td> <td>4 (4) </td> <td rowspan="2">3.6 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232145.html">13600H</a> </th> <td rowspan="3">4 (8) </td> <td>2.8 </td> <td>4.8 </td> <td rowspan="2">8 (8) </td> <td>2.1 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="2">18 MB </td> <td rowspan="3">95 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232147.html">13500H</a> </th> <td>2.6 </td> <td>4.7 </td> <td>1.9 </td> <td>3.5 </td> <td>?–1450 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232173.html">13420H</a> </th> <td>2.1 </td> <td>4.6 </td> <td>4 (4) </td> <td>1.5 </td> <td>3.4 </td> <td>UHD Graphics<br />(48 EU) </td> <td>?–1400 </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-PX">Raptor Lake-PX<span class="anchor" id=""Raptor_Lake-PX"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=141" title="Edit section: Raptor Lake-PX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1792.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 8 lanes of PCIe 4.0, in addition to 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i9 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232172.html">13905H</a> </th> <td rowspan="2">6 (12) </td> <td>2.6 </td> <td>5.4 </td> <td rowspan="3">8 (8) </td> <td>1.9 </td> <td>4.1 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1500 </td> <td rowspan="2">24 MB </td> <td rowspan="3">45 W </td> <td rowspan="3">115 W </td> <td rowspan="3"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232139.html">13705H</a> </th> <td>2.4 </td> <td>5.0 </td> <td>1.8 </td> <td>3.7 </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232107.html">13505H</a> </th> <td>4 (8) </td> <td>2.6 </td> <td>4.7 </td> <td>1.9 </td> <td>3.5 </td> <td>Iris Xe<br />(80 EU) </td> <td>?–1450 </td> <td>18 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-HX">Raptor Lake-HX<span class="anchor" id=""Raptor_Lake-HX"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=142" title="Edit section: Raptor Lake-HX"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the 14th generation refresh, see section <a href="#Raptor_Lake-HX_Refresh">§ Raptor Lake-HX Refresh</a> below.</div> <p>Common features: </p> <ul><li>Socket: BGA 1964.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 or <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM. Models i7-13850HX and up support DDR5 at up to 5600 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of PCIe 4.0, in addition to 16 lanes of PCIe 4.0 and 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the on-package chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>All models support CPU, iGPU, and memory overclocking.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup></li> <li>i9-13980HX features Thermal Velocity Boost. Without it enabled, the maximum boost clock speed is 0.1 GHz lower.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="3">Core i9 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232138.html">13980HX</a> </th> <td rowspan="5">8 (16) </td> <td rowspan="3">2.2 </td> <td rowspan="1">5.6 </td> <td rowspan="3">16 (16) </td> <td rowspan="3">1.6 </td> <td rowspan="2">4.0 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="3">?–1650 </td> <td rowspan="3">36 MB </td> <td rowspan="9">55 W </td> <td rowspan="9">157 W </td> <td rowspan="9"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232149.html">13950HX</a> </th> <td>5.5 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232171.html">13900HX</a> </th> <td>5.4 </td> <td>3.9 </td></tr> <tr> <th rowspan="3">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232161.html">13850HX</a> </th> <td rowspan="2">2.1 </td> <td>5.1 </td> <td>12 (12) </td> <td rowspan="2">1.5 </td> <td>3.8 </td> <td>?–1600 </td> <td rowspan="2">30 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232166.html">13700HX</a> </th> <td>5.0 </td> <td rowspan="4">8 (8) </td> <td rowspan="3">3.6 </td> <td rowspan="2">?–1550 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232101.html">13650HX</a> </th> <td rowspan="4">6 (12) </td> <td rowspan="2">2.6 </td> <td>4.9 </td> <td rowspan="2">1.9 </td> <td>UHD Graphics<br />(16 EU) </td> <td rowspan="3">24 MB </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232154.html">13600HX</a> </th> <td>4.7 </td> <td rowspan="2">UHD Graphics<br />(32 EU) </td> <td rowspan="2">?–1500 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232156.html">13500HX</a> </th> <td>2.5 </td> <td rowspan="2">4.6 </td> <td rowspan="2">1.8 </td> <td>3.5 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232132.html">13450HX</a> </th> <td>2.4 </td> <td>4 (4) </td> <td>3.4 </td> <td>UHD Graphics<br />(16 EU) </td> <td>?–1450 </td> <td>20 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(14th_gen)_2"><span id="Core_i_.2814th_gen.29_2"></span>Core i (14th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=143" title="Edit section: Core i (14th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-HX_Refresh">Raptor Lake-HX Refresh</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=144" title="Edit section: Raptor Lake-HX Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1964.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 or <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of PCIe 4.0, in addition to 16 lanes of PCIe 4.0 and 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>All models support CPU, iGPU, and memory overclocking.</li> <li>i7-14650HX, i7-14700HX, and i9-14900HX feature Thermal Velocity Boost. Without it enabled, the maximum boost clock speed is 0.1 GHz lower.</li> <li>i7-14700HX, and i9-14900HX feature Intel Application Optimization.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="1">Core i9 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/235995.html">14900HX</a> </th> <td rowspan="3">8 (16) </td> <td>2.2 </td> <td>5.8 </td> <td>16 (16) </td> <td>1.6 </td> <td>4.1 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td>?–1650 </td> <td>36 MB </td> <td rowspan="5">55 W </td> <td rowspan="5">157 W </td> <td rowspan="5"><span data-sort-value="000000002024-01-01-0000" style="white-space:nowrap">January 2024</span> </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/235997.html">14700HX</a> </th> <td>2.1 </td> <td>5.5 </td> <td>12 (12) </td> <td>1.5 </td> <td>3.9 </td> <td rowspan="2">?–1600 </td> <td>33 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/235996.html">14650HX</a> </th> <td>2.2 </td> <td>5.2 </td> <td rowspan="2">8 (8) </td> <td>1.6 </td> <td>3.7 </td> <td>UHD Graphics<br />(16 EU) </td> <td>30 MB </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/235999.html">14500HX</a> </th> <td rowspan="2">6 (12) </td> <td>2.6 </td> <td>4.9 </td> <td>1.9 </td> <td rowspan="2">3.5 </td> <td>UHD Graphics<br />(32 EU) </td> <td>?–1550 </td> <td>24 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/235998.html">14450HX</a> </th> <td>2.4 </td> <td>4.8 </td> <td>4 (4) </td> <td>1.8 </td> <td>UHD Graphics<br />(16 EU) </td> <td>?–1500 </td> <td>20 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_/_Core_Ultra_3/5/7/9_(Series_1)"><span id="Core_.2F_Core_Ultra_3.2F5.2F7.2F9_.28Series_1.29"></span>Core / Core Ultra 3/5/7/9 (Series 1)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=145" title="Edit section: Core / Core Ultra 3/5/7/9 (Series 1)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-U_Refresh">Raptor Lake-U Refresh</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=146" title="Edit section: Raptor Lake-U Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>Includes integrated graphics based on Xe-LP architecture.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>The <a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/238762.html">Core 3 100U</a> is available with IPU (image processing unit). Specifications between it and the respective processor without IPU are completely identical, apart from the addition of the IPU.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th class="unsortable" rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th class="unsortable" rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core 7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236795.html">150U</a> </th> <td rowspan="3">2 (4) </td> <td>1.8 </td> <td>5.4 </td> <td rowspan="2">8 (8) </td> <td>1.2 </td> <td>4.0 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Intel Graphics</a><br />(96 EU) </td> <td>?–1300 </td> <td rowspan="2">12 MB </td> <td rowspan="3">15 W </td> <td rowspan="3">55 W </td> <td rowspan="3"><span data-sort-value="000000002024-01-01-0000" style="white-space:nowrap">January 2024</span> </td></tr> <tr> <th>Core 5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236796.html">120U</a> </th> <td>1.4 </td> <td>5.0 </td> <td rowspan="2">0.9 </td> <td>3.8 </td> <td>Intel Graphics<br />(80 EU) </td> <td rowspan="2">?–1250 </td></tr> <tr> <th>Core 3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236776.html">100U</a> </th> <td>1.2 </td> <td>4.7 </td> <td>4 (4) </td> <td>3.3 </td> <td>Intel Graphics<br />(64 EU) </td> <td>10 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Meteor_Lake-U">Meteor Lake-U</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=147" title="Edit section: Meteor Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 2049.</li> <li>All the CPUs except 1x4U models support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 or <a href="/wiki/LPDDR5X" class="mw-redirect" title="LPDDR5X">LPDDR5X</a>-7466 RAM. 1x4U models support dual-channel LPDDR5(X)-6400.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>Includes integrated graphics based on <a href="/wiki/Arc_Alchemist" class="mw-redirect" title="Arc Alchemist">Alchemist</a> architecture.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 112 KB (48 KB data + 64 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>All processor models also feature 2× "LP E-Cores" which are clocked at 0.7 GHz base (0.4 GHz on 1x4U models), 2.1 GHz boost and have 2 MB of L2 cache.</li> <li>Fabrication process: <a href="/wiki/5_nm_process" title="5 nm process">Intel 4</a> (compute tile).</li> <li>Configurable TDP (cTDP) of 12–28 W is featured on 1x5U models, and 9–15 W on 1x4U models.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th class="unsortable" rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th class="unsortable" rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="3">Core Ultra 7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237329.html">165U</a> </th> <td rowspan="7">2 (4) </td> <td>1.7 </td> <td>4.9 </td> <td rowspan="6">8 (8) </td> <td>1.2 </td> <td rowspan="3">3.8 </td> <td rowspan="6"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Graphics</a><br />(4 Xe-cores) </td> <td>?–2000 </td> <td rowspan="6">12 MB </td> <td>15 W </td> <td>57 W </td> <td rowspan="7"><span data-sort-value="000000002023-12-01-0000" style="white-space:nowrap">December 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237508.html">164U</a> </th> <td>1.1 </td> <td rowspan="2">4.8 </td> <td>0.7 </td> <td>?–1800 </td> <td>9 W </td> <td>30 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237327.html">155U</a> </th> <td>1.7 </td> <td>1.2 </td> <td>?–1950 </td> <td rowspan="2">15 W </td> <td rowspan="2">57 W </td></tr> <tr> <th rowspan="4">Core Ultra 5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237328.html">135U</a> </th> <td>1.6 </td> <td rowspan="2">4.4 </td> <td>1.1 </td> <td rowspan="3">3.6 </td> <td>?–1900 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237507.html">134U</a> </th> <td>0.7 </td> <td>0.5 </td> <td>?–1750 </td> <td>9 W </td> <td>30 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237330.html">125U</a> </th> <td>1.3 </td> <td>4.3 </td> <td>0.8 </td> <td>?–1850 </td> <td rowspan="2">15 W </td> <td rowspan="2">57 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237505.html">115U</a> </th> <td>1.5 </td> <td>4.2 </td> <td>4 (4) </td> <td>1.0 </td> <td>3.5 </td> <td>Intel Graphics<br />(3 Xe-cores) </td> <td>?–1800 </td> <td>10 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Meteor_Lake-H">Meteor Lake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=148" title="Edit section: Meteor Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 2049.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 or <a href="/wiki/LPDDR5X" class="mw-redirect" title="LPDDR5X">LPDDR5X</a>-7466 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 20 lanes of PCIe 4.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>Includes integrated graphics based on <a href="/wiki/Arc_Alchemist" class="mw-redirect" title="Arc Alchemist">Alchemist</a> architecture.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 112 KB (48 KB data + 64 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>All processor models also feature 2× "LP E-Cores" which are clocked at 0.7 GHz base (1.0 GHz on Core Ultra 9 185H), 2.5 GHz boost and have 2 MB of L2 cache.</li> <li>Fabrication process: <a href="/wiki/5_nm_process" title="5 nm process">Intel 4</a> (compute tile).</li> <li>Configurable TDP (cTDP) of 35–65 W is featured on Core Ultra 9 185H, and 20–65 W on all other models.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th class="unsortable" rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th class="unsortable" rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core Ultra 9 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236849.html">185H</a> </th> <td rowspan="3">6 (12) </td> <td>2.3 </td> <td>5.1 </td> <td rowspan="5">8 (8) </td> <td>1.8 </td> <td rowspan="3">3.8 </td> <td rowspan="4"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Arc</a><br />(8 Xe-cores) </td> <td>?–2350 </td> <td rowspan="3">24 MB </td> <td>45 W </td> <td rowspan="5">115 W </td> <td rowspan="5"><span data-sort-value="000000002023-12-01-0000" style="white-space:nowrap">December 2023</span> </td></tr> <tr> <th rowspan="2">Core Ultra 7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236851.html">165H</a> </th> <td rowspan="2">1.4 </td> <td>5.0 </td> <td rowspan="2">0.9 </td> <td>?–2300 </td> <td rowspan="4">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236847.html">155H</a> </th> <td>4.8 </td> <td>?–2250 </td></tr> <tr> <th rowspan="2">Core Ultra 5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236850.html">135H</a> </th> <td rowspan="2">4 (8) </td> <td>1.7 </td> <td>4.6 </td> <td>1.2 </td> <td rowspan="2">3.6 </td> <td rowspan="2">?–2200 </td> <td rowspan="2">18 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236848.html">125H</a> </th> <td>1.2 </td> <td>4.5 </td> <td>0.7 </td> <td>Intel Arc<br />(7 Xe-cores) </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_Ultra_5/7/9_(Series_2)"><span id="Core_Ultra_5.2F7.2F9_.28Series_2.29"></span>Core Ultra 5/7/9 (Series 2)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=149" title="Edit section: Core Ultra 5/7/9 (Series 2)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Lunar_Lake">Lunar Lake</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=150" title="Edit section: Lunar Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 2833.</li> <li>All the CPUs support dual-channel <a href="/wiki/LPDDR5X" class="mw-redirect" title="LPDDR5X">LPDDR5X</a>-8533 RAM (on package).</li> <li>All CPU models provide 4 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a>.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 112 KB (48 KB (12-Way) data + 64 KB (16-Way) instructions) per core.</li> <li>E-cores: 96 KB (32 KB (8-Way) data + 64 KB (16-Way) instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2.5 MB (10-Way) per core.</li> <li>E-cores: 4 MB (16-Way) per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: Compute Tile (Contains the CPU cores) <a href="/wiki/TSMC" title="TSMC">TSMC</a>'s <a href="/wiki/3_nm_process" title="3 nm process">N3B</a> node.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/AI_accelerator" title="AI accelerator">NPU</a> </th> <th colspan="2">Integrated memory </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th class="unsortable" rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th class="unsortable" rowspan="2">Neural<br />computes<br />engines </th> <th class="unsortable" rowspan="2">NPU<br />AI<br />TOPS </th> <th class="unsortable" rowspan="2">Memory<br />speed </th> <th class="unsortable" rowspan="2">Memory<br />capacity </th> <th class="unsortable" rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core Ultra 9 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240961/intel-core-ultra-9-processor-288v-12m-cache-up-to-5-10-ghz/specifications.html">288V</a> </th> <td rowspan="9">4 (4) </td> <td>3.3 </td> <td>5.1 </td> <td rowspan="9">4 (4) </td> <td>3.3 </td> <td rowspan="5">3.7 </td> <td rowspan="5"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Arc 140V</a><br />(8 Xe-cores) </td> <td>?–2050 </td> <td rowspan="5">12 MB </td> <td rowspan="5">6x<br />Gen4 </td> <td rowspan="3">48 </td> <td rowspan="9">LPDDR5X<br />8533 MT/s </td> <td rowspan="2">32 GB </td> <td>30 W<br />(Min:17 W) </td> <td rowspan="9">37 W </td> <td rowspan="9"><span data-sort-value="000000002024-09-01-0000" style="white-space:nowrap">September 2024</span> </td></tr> <tr> <th rowspan="4">Core Ultra 7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240958/intel-core-ultra-7-processor-268v-12m-cache-up-to-5-00-ghz/specifications.html">268V</a> </th> <td rowspan="4">2.2 </td> <td rowspan="2">5.0 </td> <td rowspan="4">2.2 </td> <td rowspan="2">?–2000 </td> <td rowspan="8">17 W<br />(Min:8 W) </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240956/intel-core-ultra-7-processor-266v-12m-cache-up-to-5-00-ghz/specifications.html">266V</a> </th> <td>16 GB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240957/intel-core-ultra-7-processor-258v-12m-cache-up-to-4-80-ghz/specifications.html">258V</a> </th> <td rowspan="2">4.8 </td> <td rowspan="2">?–1950 </td> <td rowspan="2">47 </td> <td>32 GB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240954/intel-core-ultra-7-processor-256v-12m-cache-up-to-4-80-ghz/specifications.html">256V</a> </th> <td>16 GB </td></tr> <tr> <th rowspan="4">Core Ultra 5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240951/intel-core-ultra-5-processor-238v-8m-cache-up-to-4-70-ghz/specifications.html">238V</a> </th> <td rowspan="4">2.1 </td> <td rowspan="2">4.7 </td> <td rowspan="4">2.1 </td> <td rowspan="4">3.5 </td> <td rowspan="4"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Arc 130V</a><br />(7 Xe-cores) </td> <td rowspan="4">?–1850 </td> <td rowspan="4">8 MB </td> <td rowspan="4">5x<br />Gen4 </td> <td rowspan="4">40 </td> <td>32 GB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240959/intel-core-ultra-5-processor-236v-8m-cache-up-to-4-70-ghz/specifications.html">236V</a> </th> <td>16 GB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240955/intel-core-ultra-5-processor-228v-8m-cache-up-to-4-50-ghz/specifications.html">228V</a> </th> <td rowspan="2">4.5 </td> <td>32 GB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/240960/intel-core-ultra-5-processor-226v-8m-cache-up-to-4-50-ghz/specifications.html">226V</a> </th> <td>16 GB </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Embedded_processors">Embedded processors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=151" title="Edit section: Embedded processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Core_i_(1st_gen)_3"><span id="Core_i_.281st_gen.29_3"></span>Core i (1st gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=152" title="Edit section: Core i (1st gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Arrandale_2">Arrandale</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=153" title="Edit section: Arrandale"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1288.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM. All models support it at 800 MT/s speeds while E- and LE-suffix models support up to 1066 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 1.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/50022.html">660UE</a> </th> <td rowspan="6">2 (4) </td> <td>1.33 </td> <td>2.40 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Westmere" title="Intel Graphics Technology">HD Graphics</a> </td> <td>166–500 </td> <td rowspan="4">4 MB </td> <td>18 W </td> <td><span data-sort-value="000000002010-08-01-0000" style="white-space:nowrap">August 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47934.html">620LE</a> </th> <td>2.00 </td> <td>2.80 </td> <td>266–566 </td> <td>25 W </td> <td rowspan="5"><span data-sort-value="000000002010-01-01-0000" style="white-space:nowrap">January 2010</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47935.html">620UE</a> </th> <td>1.06 </td> <td>2.13 </td> <td>166–500 </td> <td>18 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48139.html">610E</a> </th> <td>2.53 </td> <td>3.20 </td> <td rowspan="2">500–766 </td> <td rowspan="3">35 W </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/47936.html">520E</a> </th> <td>2.40 </td> <td>2.93 </td> <td rowspan="2">3 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/48140.html">330E</a> </th> <td>2.13 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>500–666 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(2nd_gen)_3"><span id="Core_i_.282nd_gen.29_3"></span>Core i (2nd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=154" title="Edit section: Core i (2nd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Sandy_Bridge-DT_2">Sandy Bridge-DT</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=155" title="Edit section: Sandy Bridge-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following models from the Sandy Bridge desktop range are available as embedded processors: </p> <ul><li>Core i7-2600</li> <li>Core i5-2400</li> <li>Core i3-2120</li></ul> <p>See section <a href="#Sandy_Bridge-DT">Desktop processors § Sandy Bridge-DT</a> for full info. </p> <div class="mw-heading mw-heading4"><h4 id="Sandy_Bridge-M_2">Sandy Bridge-M</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=156" title="Edit section: Sandy Bridge-M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Socket_G2" title="Socket G2">G2</a> (2xx0E and 2xx0QE models except i3-2310E), BGA 1023 (all other models).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM. All models support it at 1333 MT/s speeds while i7-2720QM and above support up to 1600 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54644.html">2715QE</a> </th> <td rowspan="2">4 (8) </td> <td rowspan="2">2.1 </td> <td rowspan="2">3.0 </td> <td rowspan="9"><a href="/wiki/Intel_Graphics_Technology#Sandy_Bridge" title="Intel Graphics Technology">HD 3000</a> </td> <td rowspan="2">650–1200 </td> <td rowspan="2">6 MB </td> <td rowspan="2">45 W </td> <td rowspan="2"><span data-sort-value="000000002011-01-01-0000" style="white-space:nowrap">January 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53472.html">2710QE</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54642.html">2655LE</a> </th> <td rowspan="7">2 (4) </td> <td>2.2 </td> <td>2.9 </td> <td>650–1000 </td> <td rowspan="2">4 MB </td> <td>25 W </td> <td rowspan="4"><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54645.html">2610UE</a> </th> <td>1.5 </td> <td>2.4 </td> <td>350–850 </td> <td>17 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54647.html">2515E</a> </th> <td rowspan="2">2.5 </td> <td rowspan="2">3.1 </td> <td rowspan="2">650–1100 </td> <td rowspan="5">3 MB </td> <td rowspan="2">35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53456.html">2510E</a> </th></tr> <tr> <th rowspan="3">Core i3 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54646.html">2340UE</a> </th> <td>1.3 </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–800 </td> <td>17 W </td> <td rowspan="2"><span data-sort-value="000000002011-06-01-0000" style="white-space:nowrap">June 2011</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/53433.html">2330E</a> </th> <td>2.2 </td> <td rowspan="2">650–1050 </td> <td rowspan="2">35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/54643.html">2310E</a> </th> <td>2.1 </td> <td><span data-sort-value="000000002011-02-01-0000" style="white-space:nowrap">February 2011</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Gladden">Gladden<span class="anchor" id=""Gladden"_(32_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=157" title="Edit section: Gladden"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1284.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>-1333 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_2.0" class="mw-redirect" title="PCIe 2.0">PCIe 2.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/68332.html">2115C</a> </th> <td>2 (4) </td> <td>2.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>3 MB </td> <td>25 W </td> <td>Q2 2012 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(3rd_gen)_3"><span id="Core_i_.283rd_gen.29_3"></span>Core i (3rd gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=158" title="Edit section: Core i (3rd gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Ivy_Bridge-DT_2">Ivy Bridge-DT</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=159" title="Edit section: Ivy Bridge-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following models from the Ivy Bridge desktop range are available as embedded processors: </p> <ul><li>Core i7-3770</li> <li>Core i5-3550S</li> <li>Core i3-3220</li></ul> <p>See section <a href="#Ivy_Bridge-DT">Desktop processors § Ivy Bridge-DT</a> for full info. </p> <div class="mw-heading mw-heading4"><h4 id="Ivy_Bridge-M">Ivy Bridge-M</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=160" title="Edit section: Ivy Bridge-M"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/Socket_G2" title="Socket G2">G2</a> (3xx0ME/QE models only), BGA 1023 (all other models and also i5-3610ME, i3-3120ME).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> and <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>i7 models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>, while i5 models provide 1 lane of PCIe 3.0 and i3 models provide 1 lane of PCIe 2.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/32_nm_process" title="32 nm process">32 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="5">Core i7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65709.html">3615QE</a> </th> <td rowspan="3">4 (8) </td> <td rowspan="2">2.3 </td> <td rowspan="2">3.3 </td> <td rowspan="8"><a href="/wiki/Intel_Graphics_Technology#Ivy_Bridge" title="Intel Graphics Technology">HD 4000</a> </td> <td rowspan="3">650–1000 </td> <td rowspan="3">6 MB </td> <td rowspan="2">45 W </td> <td rowspan="3"><span data-sort-value="000000002012-04-01-0000" style="white-space:nowrap">April 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65711.html">3610QE</a> </th></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65710.html">3612QE</a> </th> <td>2.1 </td> <td>3.1 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65712.html">3555LE</a> </th> <td rowspan="5">2 (4) </td> <td>2.5 </td> <td>3.2 </td> <td>550–1000 </td> <td rowspan="2">4 MB </td> <td>25 W </td> <td rowspan="3"><span data-sort-value="000000002012-06-01-0000" style="white-space:nowrap">June 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65713.html">3517UE</a> </th> <td>1.7 </td> <td>2.8 </td> <td>350–1000 </td> <td>17 W </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65704.html">3610ME</a> </th> <td>2.7 </td> <td>3.3 </td> <td>650–950 </td> <td rowspan="3">3 MB </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65696.html">3217UE</a> </th> <td>1.6 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>350–900 </td> <td>17 W </td> <td rowspan="2"><span data-sort-value="000000002012-08-01-0000" style="white-space:nowrap">August 2012</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/65698.html">3120ME</a> </th> <td>2.4 </td> <td>650–900 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Gladden_2">Gladden<span class="anchor" id=""Gladden"_(22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=161" title="Edit section: Gladden"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1284.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> and <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> 1333 MT/s RAM.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>No integrated graphics.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/78170.html">3115C</a> </th> <td>2 (4) </td> <td>2.5 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4 MB </td> <td>25 W </td> <td>Q3 2013 </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(4th_gen)_3"><span id="Core_i_.284th_gen.29_3"></span>Core i (4th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=162" title="Edit section: Core i (4th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Haswell-DT_2">Haswell-DT</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=163" title="Edit section: Haswell-DT"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75610.html">4770TE</a> </th> <td>4 (8) </td> <td>2.3 </td> <td rowspan="2">3.3 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4600</a> </td> <td rowspan="4">350–1000 </td> <td>8 MB </td> <td>45 W </td> <td rowspan="2"><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75468.html">4570TE</a> </th> <td rowspan="3">2 (4) </td> <td>2.7 </td> <td rowspan="3">4 MB </td> <td rowspan="3">35 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/80918.html">4340TE</a> </th> <td>2.6 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span data-sort-value="000000002014-05-01-0000" style="white-space:nowrap">May 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/77778.html">4330TE</a> </th> <td>2.4 </td> <td><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr></tbody></table> <p>The following models from the Haswell-DT desktop range are also available as embedded processors: </p> <ul><li>Core i7-4790S</li> <li>Core i7-4770S</li> <li>Core i5-4590S</li> <li>Core i5-4590T</li> <li>Core i5-4570S</li> <li>Core i3-4360</li> <li>Core i3-4350T</li> <li>Core i3-4330</li></ul> <p>See section <a href="#Haswell-DT">Desktop processors § Haswell-DT</a> for full info. </p> <div class="mw-heading mw-heading4"><h4 id="Haswell-H_3">Haswell-H<span class="anchor" id=""Haswell-H"_(22_nm)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=164" title="Edit section: Haswell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1364.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 5200 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/22_nm_process" title="22 nm process">22 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="6">Core i7 </th> <th style="text-align:left;" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76298.html">4860EQ</a> </th> <td rowspan="6">4 (8) </td> <td>1.8 </td> <td>3.2 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">Iris Pro 5200</a> </td> <td>750–1000 </td> <td rowspan="4">6 MB </td> <td rowspan="4">47 W </td> <td rowspan="2"><span data-sort-value="000000002013-08-01-0000" style="white-space:nowrap">August 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76299.html">4850EQ</a> </th> <td>1.6 </td> <td>3.2 </td> <td>650–1000 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76297.html">4701EQ</a> </th> <td rowspan="2">2.4 </td> <td rowspan="2">3.4 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Haswell" title="Intel Graphics Technology">HD 4600</a> </td> <td rowspan="2">400–1000 </td> <td>Q3 2013 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75469.html">4700EQ</a> </th> <td><span data-sort-value="000000002013-06-01-0000" style="white-space:nowrap">June 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75555.html">4700EC</a> </th> <td>2.7 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="2" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">8 MB </td> <td>43 W </td> <td rowspan="2"><span data-sort-value="000000002014-03-01-0000" style="white-space:nowrap">March 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75556.html">4702EC</a> </th> <td>2.0 </td> <td>27 W </td></tr> <tr> <th rowspan="5">Core i5 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/79201.html">4422E</a> </th> <td rowspan="9">2 (4) </td> <td>1.8 </td> <td>2.9 </td> <td rowspan="4">HD 4600 </td> <td>400–900 </td> <td rowspan="4">3 MB </td> <td>25 W </td> <td rowspan="2"><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/79199.html">4410E</a> </th> <td>2.9 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>400–1000 </td> <td rowspan="2">37 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76292.html">4400E</a> </th> <td>2.7 </td> <td>3.3 </td> <td>400–1000 </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76307.html">4402E</a> </th> <td>1.6 </td> <td>2.7 </td> <td>400–900 </td> <td>25 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/75554.html">4402EC</a> </th> <td>2.5 </td> <td rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4 MB </td> <td>27 W </td> <td><span data-sort-value="000000002014-03-01-0000" style="white-space:nowrap">March 2014</span> </td></tr> <tr> <th rowspan="4">Core i3 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/79197.html">4110E</a> </th> <td>2.6 </td> <td rowspan="4">HD 4600 </td> <td rowspan="4">400–900 </td> <td rowspan="4">3 MB </td> <td>37 W </td> <td rowspan="2"><span data-sort-value="000000002014-04-01-0000" style="white-space:nowrap">April 2014</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/79198.html">4112E</a> </th> <td>1.8 </td> <td>25 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76293.html">4100E</a> </th> <td>2.4 </td> <td>37 W </td> <td rowspan="2"><span data-sort-value="000000002013-09-01-0000" style="white-space:nowrap">September 2013</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/76294.html">4102E</a> </th> <td>1.6 </td> <td>25 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(5th_gen)_3"><span id="Core_i_.285th_gen.29_3"></span>Core i (5th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=165" title="Edit section: Core i (5th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Broadwell-H_3">Broadwell-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=166" title="Edit section: Broadwell-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1364.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a> RAM, at up to 1600 MT/s speed.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 2.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 6200 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88094.html">5850EQ</a> </th> <td rowspan="2">4 (8) </td> <td>2.7 </td> <td rowspan="2">3.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">Iris Pro 6200</a> </td> <td rowspan="2">300–1000 </td> <td rowspan="2">6 MB </td> <td rowspan="2">47 W </td> <td rowspan="2"><span data-sort-value="000000002015-06-01-0000" style="white-space:nowrap">June 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88093.html">5700EQ</a> </th> <td>2.6 </td> <td><a href="/wiki/Intel_Graphics_Technology#Broadwell" title="Intel Graphics Technology">HD 5600</a> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(6th_gen)_3"><span id="Core_i_.286th_gen.29_3"></span>Core i (6th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=167" title="Edit section: Core i (6th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Skylake-S_2">Skylake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=168" title="Edit section: Skylake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88201.html">6700TE</a> </th> <td>4 (8) </td> <td>2.4 </td> <td>3.4 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 530</a> </td> <td rowspan="3">350–1000 </td> <td>8 MB </td> <td rowspan="3">35 W </td> <td rowspan="2"><span data-sort-value="000000002015-09-01-0000" style="white-space:nowrap">September 2015</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88186.html">6500TE</a> </th> <td>4 (4) </td> <td>2.3 </td> <td>3.3 </td> <td>6 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88181.html">6100TE</a> </th> <td>2 (4) </td> <td>2.7 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4 MB </td> <td>Q4 2015 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Skylake-H_3">Skylake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=169" title="Edit section: Skylake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2133, <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-1866 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Models with Iris Pro 580 iGPU also feature 128 MB of <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>, acting as L4 cache.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90426.html">6820EQ</a> </th> <td rowspan="2">4 (8) </td> <td>2.8 </td> <td>3.5 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Skylake" title="Intel Graphics Technology">HD 530</a> </td> <td rowspan="4">350–1000 </td> <td rowspan="2">8 MB </td> <td>45 W </td> <td rowspan="6"><span data-sort-value="000000002015-10-01-0000" style="white-space:nowrap">October 2015</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90615.html">6822EQ</a> </th> <td>2.0 </td> <td>2.8 </td> <td>25 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90425.html">6440EQ</a> </th> <td rowspan="2">4 (4) </td> <td>2.7 </td> <td>3.4 </td> <td rowspan="2">6 MB </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90617.html">6442EQ</a> </th> <td>1.9 </td> <td>2.7 </td> <td>25 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90611.html">6100E</a> </th> <td rowspan="2">2 (4) </td> <td>2.7 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">350–950 </td> <td rowspan="2">3 MB </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/90612.html">6102E</a> </th> <td>1.9 </td> <td>25 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(7th_gen)_3"><span id="Core_i_.287th_gen.29_3"></span>Core i (7th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=170" title="Edit section: Core i (7th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-S_2">Kaby Lake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=171" title="Edit section: Kaby Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97130.html">7101E</a> </th> <td rowspan="2">2 (4) </td> <td>3.9 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 610</a> </td> <td rowspan="2">350–1100 </td> <td rowspan="2">3 MB </td> <td>54 W </td> <td rowspan="2"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97125.html">7101TE</a> </th> <td>3.4 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Kaby_Lake-H_2">Kaby Lake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=172" title="Edit section: Kaby Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97127.html">7820EQ</a> </th> <td>4 (8) </td> <td>3.0 </td> <td>3.7 </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake" title="Intel Graphics Technology">HD 630</a> </td> <td rowspan="3">350–1000 </td> <td>8 MB </td> <td rowspan="2">45 W </td> <td rowspan="5"><span data-sort-value="000000002017-01-01-0000" style="white-space:nowrap">January 2017</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97523.html">7440EQ</a> </th> <td rowspan="2">4 (4) </td> <td>2.9 </td> <td>3.6 </td> <td rowspan="2">6 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97532.html">7442EQ</a> </th> <td>2.1 </td> <td>2.9 </td> <td>25 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97131.html">7100E</a> </th> <td rowspan="2">2 (4) </td> <td>2.9 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">350–950 </td> <td rowspan="2">3 MB </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/97124.html">7102E</a> </th> <td>2.1 </td> <td>25 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(8th_gen)_3"><span id="Core_i_.288th_gen.29_3"></span>Core i (8th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=173" title="Edit section: Core i (8th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Whiskey_Lake-U_2">Whiskey Lake-U</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=174" title="Edit section: Whiskey Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1528.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 or <a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3</a>-2133 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193554.html">8665UE</a> </th> <td rowspan="2">4 (8) </td> <td>1.7 </td> <td>4.4 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 620</a> </td> <td>300–1150 </td> <td>8 MB </td> <td rowspan="3">15 W </td> <td><span data-sort-value="000000002019-04-01-0000" style="white-space:nowrap">April 2019</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193559.html">8365UE</a> </th> <td>1.6 </td> <td>4.1 </td> <td>300–1050 </td> <td>6 MB </td> <td rowspan="2"><span data-sort-value="000000002019-06-01-0000" style="white-space:nowrap">June 2019</span> </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193560.html">8145UE</a> </th> <td>2 (4) </td> <td>2.2 </td> <td>3.9 </td> <td>300–1000 </td> <td>4 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(9th_gen)_3"><span id="Core_i_.289th_gen.29_3"></span>Core i (9th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=175" title="Edit section: Core i (9th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-R_2">Coffee Lake-R</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=176" title="Edit section: Coffee Lake-R"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1151-2" class="mw-redirect" title="LGA 1151-2">LGA 1151-2</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2400 RAM. i5 models and up support it at up to 2666 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195306.html">9700E</a> </th> <td rowspan="2">8 (8) </td> <td>2.6 </td> <td>4.4 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">350–1150 </td> <td rowspan="2">12 MB </td> <td>65 W </td> <td rowspan="6"><span data-sort-value="000000002019-06-01-0000" style="white-space:nowrap">June 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195329.html">9700TE</a> </th> <td>1.8 </td> <td>3.8 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195324.html">9500E</a> </th> <td rowspan="2">6 (6) </td> <td>3.0 </td> <td>4.2 </td> <td rowspan="2">350–1100 </td> <td rowspan="2">9 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195327.html">9500TE</a> </th> <td>2.2 </td> <td>3.6 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194374.html">9100E</a> </th> <td rowspan="2">4 (4) </td> <td>3.1 </td> <td>3.7 </td> <td rowspan="2">350–1050 </td> <td rowspan="2">6 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194376.html">9100TE</a> </th> <td>2.2 </td> <td>3.2 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Coffee_Lake-H_(refresh)_2"><span id="Coffee_Lake-H_.28refresh.29_2"></span>Coffee Lake-H (refresh)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=177" title="Edit section: Coffee Lake-H (refresh)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1440.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195328.html">9850HE</a> </th> <td rowspan="2">6 (12) </td> <td>2.7 </td> <td>4.4 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">350–1150 </td> <td rowspan="2">9 MB </td> <td>45 W </td> <td rowspan="3"><span data-sort-value="000000002019-06-01-0000" style="white-space:nowrap">June 2019</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195333.html">9850HL</a> </th> <td>1.9 </td> <td>4.1 </td> <td rowspan="2">25 W </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194375.html">9100HL</a> </th> <td>4 (4) </td> <td>1.6 </td> <td>2.9 </td> <td>350–1100 </td> <td>6 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(10th_gen)_3"><span id="Core_i_.2810th_gen.29_3"></span>Core i (10th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=178" title="Edit section: Core i (10th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Comet_Lake-S_2">Comet Lake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=179" title="Edit section: Comet Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-2666 RAM. i7 models and higher support it at up to 2933 MT/s speeds.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 4-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 64 KB (32 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 256 KB per core.</li> <li>Fabrication process: <a href="/wiki/14_nm_process" title="14 nm process">14 nm</a>.</li> <li>i9-10900E features Thermal Velocity Boost.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203902.html">10900E</a> </th> <td rowspan="2">10 (20) </td> <td>2.8 </td> <td>4.7 </td> <td rowspan="8"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">350–1200 </td> <td rowspan="2">20 MB </td> <td>65 W </td> <td rowspan="2"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203901.html">10900TE</a> </th> <td>1.8 </td> <td rowspan="2">4.5 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203908.html">10700E</a> </th> <td rowspan="2">8 (16) </td> <td>2.9 </td> <td rowspan="4">350–1150 </td> <td rowspan="2">16 MB </td> <td>65 W </td> <td rowspan="2"><span data-sort-value="000000002020-05-01-0000" style="white-space:nowrap">May 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203906.html">10700TE</a> </th> <td>2.0 </td> <td>4.4 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203893.html">10500E</a> </th> <td rowspan="2">6 (12) </td> <td>3.1 </td> <td>4.2 </td> <td rowspan="2">12 MB </td> <td>65 W </td> <td rowspan="4"><span data-sort-value="000000002020-04-01-0000" style="white-space:nowrap">April 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203891.html">10500TE</a> </th> <td>2.3 </td> <td>3.7 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203898.html">10100E</a> </th> <td rowspan="2">4 (8) </td> <td>3.2 </td> <td>3.8 </td> <td rowspan="2">350–1100 </td> <td rowspan="2">6 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203899.html">10100TE</a> </th> <td>2.3 </td> <td>3.6 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(11th_gen)_3"><span id="Core_i_.2811th_gen.29_3"></span>Core i (11th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=180" title="Edit section: Core i (11th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-UP3_2">Tiger Lake-UP3</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=181" title="Edit section: Tiger Lake-UP3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1449.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-3733 RAM. i5 models and up support LPDDR4X at up to 4266 MT/s speed.</li> <li>All CPU models provide 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>All models have configurable TDP (cTDP), which can be set from a minimum of 12 W to 28 W. Base clocks shown are at 15 W TDP; they will be different depending on the cTDP setting chosen.</li> <li>-GRE suffix models have a minimum operating temperature of -40°C as opposed to 0°C for the normal models, and also feature "in-band <a href="/wiki/Error_correcting_code" class="mw-redirect" title="Error correcting code">ECC</a>" for memory.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208082.html">1185GRE</a> </th> <td rowspan="4">4 (8) </td> <td rowspan="2">1.8 </td> <td rowspan="2">4.4 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1350 </td> <td rowspan="2">12 MB </td> <td rowspan="6">15 W </td> <td rowspan="6"><span data-sort-value="000000002020-09-01-0000" style="white-space:nowrap">September 2020</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208076.html">1185G7E</a> </th></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208078.html">1145GRE</a> </th> <td rowspan="2">1.5 </td> <td rowspan="2">4.1 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="2">?–1300 </td> <td rowspan="2">8 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208081.html">1145G7E</a> </th></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208074.html">1115GRE</a> </th> <td rowspan="2">2 (4) </td> <td rowspan="2">2.2 </td> <td rowspan="2">3.9 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td rowspan="2">?–1250 </td> <td rowspan="2">6 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208079.html">1115G4E</a> </th></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Tiger_Lake-H_2">Tiger Lake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=182" title="Edit section: Tiger Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1598.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to 24 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 3.0 bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>L2 cache: 1.25 MB per core.</li> <li>Fabrication process: <a href="/wiki/10_nm_process" title="10 nm process">10 nm</a>.</li> <li>The base clock speed that the CPU runs at corresponds with the configurable TDP (cTDP) setting chosen.</li> <li>Minimum operating temperature: 0°C.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="2"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release<br />date </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Model </th> <th class="unsortable">Clock (MHz) </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217379.html">11850HE</a> </th> <td>8 (16) </td> <td rowspan="2">2.1–2.6 </td> <td>4.7 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(32 EU) </td> <td rowspan="2">350–1350 </td> <td>24 MB </td> <td rowspan="3">35–45 W </td> <td rowspan="3"><span data-sort-value="000000002021-08-01-0000" style="white-space:nowrap">August 2021</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217369.html">11500HE</a> </th> <td>6 (12) </td> <td>4.5 </td> <td>12 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217371.html">11100HE</a> </th> <td>4 (8) </td> <td>1.9–2.4 </td> <td>4.4 </td> <td>UHD Graphics<br />(16 EU) </td> <td>350–1250 </td> <td>8 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(12th_gen)_3"><span id="Core_i_.2812th_gen.29_3"></span>Core i (12th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=183" title="Edit section: Core i (12th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-S_2">Alder Lake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=184" title="Edit section: Alder Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 RAM</li> <li>All the CPUs provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>Turbo Boost version is 2.0.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132212.html">12900E</a> </th> <td rowspan="4">8 (16) </td> <td>2.3 </td> <td>5.0 </td> <td rowspan="2">8 (8) </td> <td>1.7 </td> <td>3.8 </td> <td rowspan="6"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 770</a> </td> <td rowspan="2">300–1550 </td> <td rowspan="2">30 MB </td> <td>65 W </td> <td rowspan="8"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132211.html">12900TE</a> </th> <td>1.1 </td> <td rowspan="2">4.8 </td> <td>1.0 </td> <td rowspan="2">3.6 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132219.html">12700E</a> </th> <td>2.1 </td> <td rowspan="2">4 (4) </td> <td>1.6 </td> <td rowspan="2">300–1500 </td> <td rowspan="2">25 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132216.html">12700TE</a> </th> <td>1.4 </td> <td>4.6 </td> <td>1.0 </td> <td>3.4 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96143.html">12500E</a> </th> <td rowspan="2">6 (12) </td> <td>2.9 </td> <td>4.5 </td> <td colspan="3" rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">300–1450 </td> <td rowspan="2">18 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96142.html">12500TE</a> </th> <td>1.9 </td> <td>4.3 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132225.html">12100E</a> </th> <td rowspan="2">4 (8) </td> <td>3.2 </td> <td>4.2 </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td rowspan="2">300–1400 </td> <td rowspan="2">12 MB </td> <td>60 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132224.html">12100TE</a> </th> <td>2.1 </td> <td>4.0 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-U_2">Alder Lake-U</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=185" title="Edit section: Alder Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/227853.html">1265UE</a> </th> <td rowspan="3">2 (4) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4.7 </td> <td rowspan="2">8 (8) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.5 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1250 </td> <td rowspan="2">12 MB </td> <td rowspan="3">15 W </td> <td rowspan="3">55 W </td> <td rowspan="3"><span data-sort-value="000000002022-02-01-0000" style="white-space:nowrap">February 2022</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/227854.html">1245UE</a> </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td rowspan="2">4.4 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td rowspan="2">3.3 </td> <td>Iris Xe<br />(80 EU) </td> <td>?–1200 </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/227851.html">1215UE</a> </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4 (4) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td> <td>?–1100 </td> <td>10 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-P_2">Alder Lake-P</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=186" title="Edit section: Alder Lake-P"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132217.html">1270PE</a> </th> <td rowspan="3">4 (8) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4.5 </td> <td rowspan="2">8 (8) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1350 </td> <td>18 MB </td> <td rowspan="3">28 W </td> <td rowspan="3">64 W </td> <td rowspan="2"><span data-sort-value="000000002022-02-01-0000" style="white-space:nowrap">February 2022</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/227850.html">1250PE</a> </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4.4 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.2 </td> <td>Iris Xe<br />(80 EU) </td> <td>?–1300 </td> <td rowspan="2">12 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/227852.html">1220PE</a> </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4.2 </td> <td>4 (4) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.1 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>?–1250 </td> <td>Q1 2022 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-PS">Alder Lake-PS<span class="anchor" id=""Alder_Lake-PS"_(Intel_7)"></span></h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=187" title="Edit section: Alder Lake-PS"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: LGA 1700. While sharing the same socket as Alder Lake-S and Raptor Lake-S, this revision of LGA 1700 is electrically <i>incompatible</i> with other 12th and 13th generation Intel Core desktop processors.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800 or <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="4">Core i7 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/229953.html">12800HL</a> </th> <td rowspan="2">6 (12) </td> <td>2.4 </td> <td>4.8 </td> <td rowspan="8">8 (8) </td> <td>1.8 </td> <td>3.7 </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1400 </td> <td rowspan="2">24 MB </td> <td rowspan="2">45 W </td> <td rowspan="2">65 W </td> <td rowspan="10">Q3 2022 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228459.html">12700HL</a> </th> <td>2.3 </td> <td>4.7 </td> <td>1.7 </td> <td>3.5 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230905.html">1265UL</a> </th> <td rowspan="2">2 (4) </td> <td>1.8 </td> <td>4.8 </td> <td>1.3 </td> <td>2.7 </td> <td rowspan="2">?–1250 </td> <td rowspan="2">12 MB </td> <td rowspan="2">15 W </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230904.html">1255UL</a> </th> <td>1.7 </td> <td>4.7 </td> <td>1.2 </td> <td>2.6 </td></tr> <tr> <th rowspan="4">Core i5 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/229975.html">12600HL</a> </th> <td rowspan="2">4 (8) </td> <td>2.7 </td> <td rowspan="2">4.5 </td> <td>2.0 </td> <td rowspan="2">3.3 </td> <td rowspan="4">Iris Xe<br />(80 EU) </td> <td rowspan="2">?–1400 </td> <td rowspan="2">18 MB </td> <td rowspan="2">45 W </td> <td rowspan="2">65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/229976.html">12500HL</a> </th> <td>2.5 </td> <td>1.8 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230900.html">1245UL</a> </th> <td rowspan="2">2 (4) </td> <td>1.6 </td> <td rowspan="4">4.4 </td> <td>1.2 </td> <td rowspan="2">2.5 </td> <td>?–1250 </td> <td rowspan="3">12 MB </td> <td rowspan="2">15 W </td> <td rowspan="2">28 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230901.html">1235UL</a> </th> <td>1.3 </td> <td>1.1 </td> <td>?–1200 </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/219491.html">12300HL</a> </th> <td>4 (8) </td> <td>2.0 </td> <td rowspan="2">4 (4) </td> <td>1.5 </td> <td>3.3 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>?–1400 </td> <td>45 W </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230902.html">1215UL</a> </th> <td>2 (4) </td> <td>1.2 </td> <td>0.9 </td> <td>2.5 </td> <td>UHD Graphics<br />(64 EU) </td> <td>?–1100 </td> <td>10 MB </td> <td>15 W </td> <td>28 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Alder_Lake-H_2">Alder Lake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=188" title="Edit section: Alder Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-4800, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5200 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 16 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, in addition to 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 1.25 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226055.html">12800HE</a> </th> <td>6 (12) </td> <td>2.4 </td> <td>4.6 </td> <td rowspan="2">8 (8) </td> <td rowspan="2">1.8 </td> <td>3.5 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1350 </td> <td>24 MB </td> <td rowspan="3">45 W </td> <td rowspan="3">115 W </td> <td rowspan="3"><span data-sort-value="000000002022-01-01-0000" style="white-space:nowrap">January 2022</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96158.html">12600HE</a> </th> <td rowspan="2">4 (8) </td> <td>2.5 </td> <td>4.5 </td> <td rowspan="2">3.3 </td> <td>Iris Xe<br />(80 EU) </td> <td>?–1300 </td> <td>18 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132226.html">12300HE</a> </th> <td>1.9 </td> <td>4.3 </td> <td>4 (4) </td> <td>1.5 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>?–1150 </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i_(13th_gen)_3"><span id="Core_i_.2813th_gen.29_3"></span>Core i (13th gen)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=189" title="Edit section: Core i (13th gen)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-S_2">Raptor Lake-S</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=190" title="Edit section: Raptor Lake-S"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: <a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a>.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200 or <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 RAM.</li> <li>All the CPUs provide 16 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 4 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>, but support may vary depending on motherboard and chipsets.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core on i7 and above models, 1.25 MB per core on i5 and below models.</li> <li>E-cores: 4 MB per E-core cluster on i7 and above models, 2 MB per cluster on i5 and below models (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li> <li>Turbo Boost version is 2.0.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="2">Core i9 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232099.html">13900E</a> </th> <td rowspan="4">8 (16) </td> <td>1.8 </td> <td>5.2 </td> <td rowspan="2">16 (16) </td> <td>1.3 </td> <td>4.0 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 770</a> </td> <td rowspan="2">300–1650 </td> <td rowspan="2">36 MB </td> <td>65 W </td> <td rowspan="9"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232162.html">13900TE</a> </th> <td>1.0 </td> <td>5.0 </td> <td>0.8 </td> <td rowspan="2">3.9 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Core i7 </th> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232168.html">13700E</a> </th> <td>1.9 </td> <td>5.1 </td> <td rowspan="4">8 (8) </td> <td>1.3 </td> <td rowspan="2">300–1600 </td> <td rowspan="2">30 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232131.html">13700TE</a> </th> <td>1.1 </td> <td>4.8 </td> <td>0.8 </td> <td>3.6 </td> <td>35 W </td></tr> <tr> <th rowspan="3">Core i5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232134.html">13500E</a> </th> <td rowspan="3">6 (12) </td> <td>2.4 </td> <td>4.6 </td> <td>1.5 </td> <td>3.3 </td> <td rowspan="3">300–1550 </td> <td rowspan="2">24 MB </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232108.html">13500TE</a> </th> <td>1.3 </td> <td>4.5 </td> <td>1.1 </td> <td>3.1 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/232148.html">13400E</a> </th> <td>2.4 </td> <td>4.6 </td> <td>4 (4) </td> <td>1.5 </td> <td>3.3 </td> <td>20 MB </td> <td>65 W </td></tr> <tr> <th rowspan="2">Core i3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232163.html">13100E</a> </th> <td rowspan="2">4 (8) </td> <td>3.3 </td> <td>4.4 </td> <td colspan="3" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD 730</a> </td> <td rowspan="2">300–1500 </td> <td rowspan="2">12 MB </td> <td>60 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232105.html">13100TE</a> </th> <td>2.4 </td> <td>4.1 </td> <td>35 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-U_2">Raptor Lake-U</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=191" title="Edit section: Raptor Lake-U"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/233390.html">1365UE</a> </th> <td rowspan="4">2 (4) </td> <td>1.7 </td> <td>4.9 </td> <td rowspan="3">8 (8) </td> <td>1.3 </td> <td>3.7 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td>?–1300 </td> <td rowspan="3">12 MB </td> <td rowspan="4">15 W </td> <td rowspan="4">55 W </td> <td rowspan="4"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/233392.html">1345UE</a> </th> <td>1.4 </td> <td>4.6 </td> <td>1.2 </td> <td>3.4 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="2">?–1250 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/233389.html">1335UE</a> </th> <td>1.3 </td> <td rowspan="2">4.5 </td> <td rowspan="2">0.9 </td> <td rowspan="2">3.3 </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/233391.html">1315UE</a> </th> <td>1.2 </td> <td>4 (4) </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(64 EU) </td> <td>?–1200 </td> <td>10 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-P_2">Raptor Lake-P</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=192" title="Edit section: Raptor Lake-P"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a> and 12 lanes of PCIe 3.0.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232175.html">1370PE</a> </th> <td>6 (12) </td> <td>1.9 </td> <td>4.8 </td> <td rowspan="3">8 (8) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.7 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1400 </td> <td>24 MB </td> <td rowspan="4">28 W </td> <td rowspan="4">64 W </td> <td rowspan="4"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th rowspan="2">Core i5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232133.html">1350PE</a> </th> <td rowspan="3">4 (8) </td> <td rowspan="2">1.8 </td> <td>4.6 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>3.4 </td> <td rowspan="2">Iris Xe<br />(80 EU) </td> <td rowspan="3">12 MB </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232157.html">1340PE</a> </th> <td rowspan="2">4.5 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td rowspan="2">3.3 </td> <td>?–1350 </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232169.html">1320PE</a> </th> <td>1.7 </td> <td>4 (4) </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>?–1200 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Raptor_Lake-H_2">Raptor Lake-H</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=193" title="Edit section: Raptor Lake-H"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: BGA 1744.</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5200, <a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a>-3200, <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 or <a href="/wiki/LPDDR4X" class="mw-redirect" title="LPDDR4X">LPDDR4X</a>-4266 RAM.</li> <li>All CPU models provide 8 lanes of <a href="/wiki/PCIe_5.0" class="mw-redirect" title="PCIe 5.0">PCIe 5.0</a> and 8 lanes of PCIe 4.0, in addition to 12 lanes of PCIe 3.0 provided by the on-package PCH.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 80 KB (48 KB data + 32 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 4 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>Fabrication process: <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a>.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th>Core i7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232150.html">13800HE</a> </th> <td>6 (12) </td> <td>2.5 </td> <td>5.0 </td> <td rowspan="2">8 (8) </td> <td>1.8 </td> <td>4.0 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Iris Xe</a><br />(96 EU) </td> <td rowspan="2">?–1400 </td> <td>24 MB </td> <td rowspan="3">45 W </td> <td rowspan="3">115 W </td> <td rowspan="3"><span data-sort-value="000000002023-01-01-0000" style="white-space:nowrap">January 2023</span> </td></tr> <tr> <th>Core i5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232152.html">13600HE</a> </th> <td rowspan="2">4 (8) </td> <td>2.7 </td> <td>4.8 </td> <td>2.1 </td> <td>3.6 </td> <td>Iris Xe<br />(80 EU) </td> <td>18 MB </td></tr> <tr> <th>Core i3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232151.html">13300HE</a> </th> <td>2.1 </td> <td>4.6 </td> <td>4 (4) </td> <td>1.9 </td> <td>3.4 </td> <td><a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">UHD Graphics</a><br />(48 EU) </td> <td>?–1300 </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_/_Core_Ultra_3/5/7/9_(Series_1)_2"><span id="Core_.2F_Core_Ultra_3.2F5.2F7.2F9_.28Series_1.29_2"></span>Core / Core Ultra 3/5/7/9 (Series 1)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=194" title="Edit section: Core / Core Ultra 3/5/7/9 (Series 1)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Meteor_Lake-PS">Meteor Lake-PS</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=195" title="Edit section: Meteor Lake-PS"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Common features: </p> <ul><li>Socket: LGA 1851 (electrically incompatible with the socket used by non-embedded processors such as Arrow Lake-S).</li> <li>All the CPUs support dual-channel <a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a>-5600 RAM.</li> <li>All CPU models provide 20 lanes of <a href="/wiki/PCIe_4.0" class="mw-redirect" title="PCIe 4.0">PCIe 4.0</a>.</li> <li>All CPUs feature a <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a> 4.0 8-lane bus to the chipset (<a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCH</a>).</li> <li>Includes integrated graphics based on <a href="/wiki/Arc_Alchemist" class="mw-redirect" title="Arc Alchemist">Alchemist</a> architecture.</li> <li>L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a>: <ul><li>P-cores: 112 KB (48 KB data + 64 KB instructions) per core.</li> <li>E-cores: 96 KB (64 KB data + 32 KB instructions) per core.</li></ul></li> <li>L2 cache: <ul><li>P-cores: 2 MB per core.</li> <li>E-cores: 2 MB per E-core cluster (each "cluster" contains four cores).</li></ul></li> <li>All processor models also feature 2× "LP E-Cores" which are clocked at 0.7 GHz base, 2.1 GHz boost (2.5 GHz on HL-suffix models) and have 2 MB of L2 cache.</li> <li>Fabrication process: <a href="/wiki/5_nm_process" title="5 nm process">Intel 4</a> (compute tile).</li> <li>Configurable TDP (cTDP) of 12–28 W is featured on UL-suffix models, and 20–65 W on HL-suffix models.</li></ul> <table class="wikitable sortable nowrap" style="text-align: center;"> <tbody><tr> <th class="unsortable" rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th colspan="3">P-core (performance) </th> <th colspan="3">E-core (efficiency) </th> <th colspan="2">Integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> </th> <th class="unsortable" rowspan="3"><a href="/wiki/Smart_Cache" class="mw-redirect" title="Smart Cache">Smart<br />Cache</a> </th> <th colspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release<br />date </th></tr> <tr> <th class="unsortable" rowspan="2"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a><br />(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th class="unsortable" rowspan="2">Cores<br />(Threads) </th> <th colspan="2">Clock rate (GHz) </th> <th class="unsortable" rowspan="2">Model </th> <th class="unsortable" rowspan="2">Clock (MHz) </th> <th rowspan="2">Base </th> <th class="unsortable" rowspan="2">Max.<br />Turbo </th></tr> <tr> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th> <th class="unsortable">Base </th> <th class="unsortable">Turbo </th></tr> <tr> <th rowspan="4">Core Ultra 7 </th> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239788.html">165HL</a> </th> <td rowspan="2">6 (12) </td> <td rowspan="2">1.4 </td> <td>5.0 </td> <td rowspan="8">8 (8) </td> <td rowspan="2">0.9 </td> <td rowspan="4">3.8 </td> <td rowspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Arc</a><br />(8 Xe-cores) </td> <td>?–2300 </td> <td rowspan="2">24 MB </td> <td rowspan="2">45 W </td> <td rowspan="2">115 W </td> <td rowspan="9"><span data-sort-value="000000002024-04-01-0000" style="white-space:nowrap">April 2024</span> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239786.html">155HL</a> </th> <td>4.8 </td> <td>?–2250 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239802.html">165UL</a> </th> <td rowspan="2">2 (4) </td> <td rowspan="3">1.7 </td> <td>4.9 </td> <td rowspan="2">1.2 </td> <td rowspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Graphics</a><br />(4 Xe-cores) </td> <td>?–2000 </td> <td rowspan="2">12 MB </td> <td rowspan="2">15 W </td> <td rowspan="2">57 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239787.html">155UL</a> </th> <td>4.8 </td> <td>?–1950 </td></tr> <tr> <th rowspan="4">Core Ultra 5 </th> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239784.html">135HL</a> </th> <td rowspan="2">4 (8) </td> <td>4.6 </td> <td>1.2 </td> <td rowspan="4">3.6 </td> <td>Intel Arc<br />(8 Xe-cores) </td> <td rowspan="2">?–2200 </td> <td rowspan="2">18 MB </td> <td rowspan="2">45 W </td> <td rowspan="2">115 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239782.html">125HL</a> </th> <td>1.2 </td> <td>4.5 </td> <td>0.7 </td> <td>Intel Arc<br />(7 Xe-cores) </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239785.html">135UL</a> </th> <td rowspan="3">2 (4) </td> <td>1.6 </td> <td>4.4 </td> <td>1.1 </td> <td rowspan="2">Intel Graphics<br />(4 Xe-cores) </td> <td>?–1900 </td> <td rowspan="2">12 MB </td> <td rowspan="3">15 W </td> <td rowspan="3">57 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239783.html">125UL</a> </th> <td>1.3 </td> <td>4.3 </td> <td>0.8 </td> <td>?–1850 </td></tr> <tr> <th>Core Ultra 3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239781.html">105UL</a> </th> <td>1.5 </td> <td>4.2 </td> <td>4 (4) </td> <td>1.0 </td> <td>3.5 </td> <td>Intel Graphics<br />(3 Xe-cores) </td> <td>?–1800 </td> <td>10 MB </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=196" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_Intel_Pentium_M_microprocessors" class="mw-redirect" title="List of Intel Pentium M microprocessors">List of Intel Pentium M microprocessors</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">List of Intel Celeron processors</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">List of Intel Pentium processors</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Intel Core</a></li> <li><a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a></li> <li><a href="/wiki/Comparison_of_Intel_processors" title="Comparison of Intel processors">Comparison of Intel processors</a></li> <li><a href="/wiki/Enhanced_Pentium_M_(microarchitecture)" class="mw-redirect" title="Enhanced Pentium M (microarchitecture)">Enhanced Pentium M (microarchitecture)</a></li> <li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Intel Core (microarchitecture)</a></li> <li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn (microarchitecture)</a></li> <li><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake (microprocessor)</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=197" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output 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(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/Compare.aspx?ids=30785,27251,30784,27248,29754,27249,29755,30782,30783,27250">"Advanced Technologies"</a>. Intel Corporation<span class="reference-accessdate">. Retrieved <span class="nowrap">February 12,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Advanced+Technologies&rft.pub=Intel+Corporation&rft_id=http%3A%2F%2Fark.intel.com%2FCompare.aspx%3Fids%3D30785%2C27251%2C30784%2C27248%2C29754%2C27249%2C29755%2C30782%2C30783%2C27250&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-moreagressivehaltstate-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-moreagressivehaltstate_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-moreagressivehaltstate_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.behardware.com/news/8499/less-power-greedy-core-2-duo.html">Less power greedy Core 2 Duo</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120216124605/http://www.behardware.com/news/8499/less-power-greedy-core-2-duo.html">Archived</a> February 16, 2012, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, BeHardware November 15, 2006</span> </li> <li id="cite_note-conroespeculation-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-conroespeculation_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20061231025917/http://www.theinquirer.net/default.aspx?article=29504">"Details regarding Conroe models"</a>. <i><a href="/wiki/The_Inquirer" title="The Inquirer">The Inquirer</a></i>. February 6, 2006. Archived from the original on December 31, 2006.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Inquirer&rft.atitle=Details+regarding+Conroe+models&rft.date=2006-02-06&rft_id=http%3A%2F%2Fwww.theinquirer.net%2Fdefault.aspx%3Farticle%3D29504&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-x6900-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-x6900_4-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.dailytech.com/article.aspx?newsid=2625">DailyTech article on upcoming Core 2 Extreme CPUs</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060615031921/http://www.dailytech.com/article.aspx?newsid=2625">Archived</a> 2006-06-15 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, May 31, 2006</span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/sspec/QT/QTOM.html">"QTOM (Intel Core 2 Duo 3.2 GHZ)"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230505013727/https://www.cpu-world.com/sspec/QT/QTOM.html">Archived</a> from the original on May 5, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">May 1,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=QTOM+%28Intel+Core+2+Duo+3.2+GHZ%29&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fsspec%2FQT%2FQTOM.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/forum/viewtopic.php?t=13930">"forums :: View topic – Need help with identifying a Core 2 (TM) CPU (ES) processor"</a>. Cpu-world.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230507102100/https://www.cpu-world.com/forum/viewtopic.php?t=13930">Archived</a> from the original on May 7, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">April 4,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=forums+%3A%3A+View+topic+%E2%80%93+Need+help+with+identifying+a+Core+2+%28TM%29+CPU+%28ES%29+processor&rft.pub=Cpu-world.com&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fforum%2Fviewtopic.php%3Ft%3D13930&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-q6600-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-q6600_7-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.dailytech.com/article.aspx?newsid=4217">Intel Core 2 Quad Announced Internally</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20060921090718/http://www.dailytech.com/article.aspx?newsid=4217">Archived</a> 2006-09-21 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, DailyTech, September 19, 2006</span> </li> <li id="cite_note-q6600rel-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-q6600rel_8-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.dailytech.com/article.aspx?newsid=5595">Intel Hard-Launches Three New Quad-core Processors</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160405061432/http://www.dailytech.com/article.aspx?newsid=5595">Archived</a> 2016-04-05 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, DailyTech, January 7, 2007</span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/sspec/SL/SL9UN.html">"SL9UN (Intel Core 2 Quad Q6400)"</a>. <i>CPU-World</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230504070929/https://www.cpu-world.com/sspec/SL/SL9UN.html">Archived</a> from the original on May 4, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=SL9UN+%28Intel+Core+2+Quad+Q6400%29&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fsspec%2FSL%2FSL9UN.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-qx6700-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-qx6700_10-0">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.dailytech.com/article.aspx?newsid=3829">"Kentsfield" to Debut at 2.66 GHz</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20061021081154/http://www.dailytech.com/article.aspx?newsid=3829">Archived</a> 2006-10-21 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, DailyTech, August 16, 2006</span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Duo%20E8290%20EU80570PJ0736MN.html">"Intel Core 2 Duo E8290 – EU80570PJ0736MN"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220605200100/https://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Duo%20E8290%20EU80570PJ0736MN.html">Archived</a> from the original on June 5, 2022<span class="reference-accessdate">. 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Retrieved <span class="nowrap">May 1,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=guru3D+Forums&rft.atitle=Qx9750%21%21%21+%3A%29&rft_id=https%3A%2F%2Fforums.guru3d.com%2Fthreads%2Fqx9750.299053%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><b><a href="#cite_ref-15">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://forums.anandtech.com/threads/building-around-my-new-qx-9750.295480/">"Building around my new QX-9750"</a>. <i>AnandTech Forums: Technology, Hardware, Software, and Deals</i>. May 27, 2009. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230501101236/https://forums.anandtech.com/threads/building-around-my-new-qx-9750.295480/">Archived</a> from the original on May 1, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">May 1,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech+Forums%3A+Technology%2C+Hardware%2C+Software%2C+and+Deals&rft.atitle=Building+around+my+new+QX-9750.&rft.date=2009-05-27&rft_id=https%3A%2F%2Fforums.anandtech.com%2Fthreads%2Fbuilding-around-my-new-qx-9750.295480%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://hardforum.com/threads/my-new-chip-woo-hoo.1411896/">"My new chip WOO HOO!!!"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=My+new+chip+WOO+HOO%21%21%21&rft_id=https%3A%2F%2Fhardforum.com%2Fthreads%2Fmy-new-chip-woo-hoo.1411896%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-channelregister-071116-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-channelregister-071116_17-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIntel_Corporation2007" class="citation web cs1">Intel Corporation (November 11, 2007). <a rel="nofollow" class="external text" href="http://www.intel.com/pressroom/archive/releases/2007/20071111comp.htm">"Intel's Fundamental Advance in Transistor Design Extends Moore's Law, Computing Performance"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230507102100/https://www.intel.com/pressroom/archive/releases/2007/20071111comp.htm">Archived</a> from the original on May 7, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">May 1,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%27s+Fundamental+Advance+in+Transistor+Design+Extends+Moore%27s+Law%2C+Computing+Performance&rft.date=2007-11-11&rft.au=Intel+Corporation&rft_id=http%3A%2F%2Fwww.intel.com%2Fpressroom%2Farchive%2Freleases%2F2007%2F20071111comp.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Extreme%20QX9750.html">"Intel Core 2 Extreme QX9750 AT80569XJ087NL"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210316235344/https://www.cpu-world.com/CPUs/Core_2/Intel-Core%202%20Extreme%20QX9750.html">Archived</a> from the original on March 16, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">May 1,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core+2+Extreme+QX9750+AT80569XJ087NL&rft_id=http%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FCore_2%2FIntel-Core%25202%2520Extreme%2520QX9750.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><b><a href="#cite_ref-19">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2019" class="citation web cs1">Cutress, Ian (October 28, 2019). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14980/the-intel-core-i9-9990xe-review">"The Intel Core i9-9990XE Review: All 14 Cores at 5.0 GHz"</a>. <i>www.anandtech.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230208104454/http://www5.anandtech.com/show/14980/the-intel-core-i9-9990xe-review">Archived</a> from the original on February 8, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">May 20,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=The+Intel+Core+i9-9990XE+Review%3A+All+14+Cores+at+5.0+GHz&rft.date=2019-10-28&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14980%2Fthe-intel-core-i9-9990xe-review&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2021" class="citation web cs1">Cutress, Ian (March 16, 2021). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16523/intel-core-11th-gen-rocket-lake-core-i9-core-i7-core-i5">"Intel Launches Rocket Lake 11th Gen Core i9, Core i7, and Core i5"</a>. <i>AnandTech</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20211219163601/https://www.anandtech.com/show/16523/intel-core-11th-gen-rocket-lake-core-i9-core-i7-core-i5">Archived</a> from the original on December 19, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">March 17,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Intel+Launches+Rocket+Lake+11th+Gen+Core+i9%2C+Core+i7%2C+and+Core+i5&rft.date=2021-03-16&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16523%2Fintel-core-11th-gen-rocket-lake-core-i9-core-i7-core-i5&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://videocardz.com/newz/intel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache">"Intel Core i5-12490F is China exclusive 6-core Alder Lake desktop CPU with 20MB L3 cache"</a>. <i>VideoCardz.com</i>. January 5, 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220228060444/https://videocardz.com/newz/intel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache">Archived</a> from the original on February 28, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">July 23,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VideoCardz.com&rft.atitle=Intel+Core+i5-12490F+is+China+exclusive+6-core+Alder+Lake+desktop+CPU+with+20MB+L3+cache&rft.date=2022-01-05&rft_id=https%3A%2F%2Fvideocardz.com%2Fnewz%2Fintel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-tomshardware-cudimm-memory-needed-for-faster-base-spec-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-tomshardware-cudimm-memory-needed-for-faster-base-spec_22-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMorales2024" class="citation news cs1">Morales, Jowi (October 15, 2024). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/pc-components/ram/intels-arrow-lake-official-memory-speeds-are-unchanged-with-standard-memory-sticks-pricier-cudimm-memory-needed-for-faster-base-spec">"Intel's Arrow Lake official memory speeds are unchanged with standard memory sticks — pricier CUDIMM memory needed for faster base spec"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 21,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel%27s+Arrow+Lake+official+memory+speeds+are+unchanged+with+standard+memory+sticks+%E2%80%94+pricier+CUDIMM+memory+needed+for+faster+base+spec&rft.date=2024-10-15&rft.aulast=Morales&rft.aufirst=Jowi&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fpc-components%2Fram%2Fintels-arrow-lake-official-memory-speeds-are-unchanged-with-standard-memory-sticks-pricier-cudimm-memory-needed-for-faster-base-spec&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/sspec/SL/SLA4C.html">"SLA4C (Intel Core 2 Duo T5850)"</a>. <i>CPU-World</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230503160531/https://www.cpu-world.com/sspec/SL/SLA4C.html">Archived</a> from the original on May 3, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=SLA4C+%28Intel+Core+2+Duo+T5850%29&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fsspec%2FSL%2FSLA4C.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/sspec/SL/SLB6D.html">"SLB6D (Intel Core 2 Duo T5900)"</a>. <i>CPU-World</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230505013720/https://www.cpu-world.com/sspec/SL/SLB6D.html">Archived</a> from the original on May 5, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=SLB6D+%28Intel+Core+2+Duo+T5900%29&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fsspec%2FSL%2FSLB6D.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/sspec/SL/SL9U5.html">"SL9U5 (Intel Core 2 Duo T7600G)"</a>. <i>CPU-World</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230506205211/https://www.cpu-world.com/sspec/SL/SL9U5.html">Archived</a> from the original on May 6, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=SL9U5+%28Intel+Core+2+Duo+T7600G%29&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fsspec%2FSL%2FSL9U5.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShah2008" class="citation web cs1">Shah, Agam (February 11, 2008). <a rel="nofollow" class="external text" href="https://www.infoworld.com/article/2650885/computer-hardware/intel-develops-processor-similar-to-macbook-air-chip.html">"Intel develops processor similar to MacBook Air chip"</a>. <i><a href="/wiki/InfoWorld" title="InfoWorld">InfoWorld</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20181028033609/https://www.infoworld.com/article/2650885/computer-hardware/intel-develops-processor-similar-to-macbook-air-chip.html">Archived</a> from the original on October 28, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=InfoWorld&rft.atitle=Intel+develops+processor+similar+to+MacBook+Air+chip&rft.date=2008-02-11&rft.aulast=Shah&rft.aufirst=Agam&rft_id=https%3A%2F%2Fwww.infoworld.com%2Farticle%2F2650885%2Fcomputer-hardware%2Fintel-develops-processor-similar-to-macbook-air-chip.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-intel.com-27"><span class="mw-cite-backlink">^ <a href="#cite_ref-intel.com_27-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-intel.com_27-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/support/products/873/processors.html">"Support for Intel Processors"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190623123110/https://www.intel.com/content/www/us/en/support/products/873/processors.html">Archived</a> from the original on June 23, 2019<span class="reference-accessdate">. Retrieved <span class="nowrap">June 26,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Support+for+Intel+Processors&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fsupport%2Fproducts%2F873%2Fprocessors.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShimpi2008" class="citation web cs1">Shimpi, Anand Lai (January 17, 2008). <a rel="nofollow" class="external text" href="http://www.anandtech.com/mac/showdoc.aspx?i=3203">"The MacBook Air CPU Mystery: More Details Revealed"</a>. <i><a href="/wiki/AnandTech" title="AnandTech">AnandTech</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100105075850/http://www.anandtech.com/mac/showdoc.aspx?i=3203">Archived</a> from the original on January 5, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=The+MacBook+Air+CPU+Mystery%3A+More+Details+Revealed&rft.date=2008-01-17&rft.aulast=Shimpi&rft.aufirst=Anand+Lai&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fmac%2Fshowdoc.aspx%3Fi%3D3203&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-T6xxx-29"><span class="mw-cite-backlink">^ <a href="#cite_ref-T6xxx_29-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-T6xxx_29-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090212072827/http://ark.intel.com/cpu.aspx?groupID=40479&code=t6400">"Intel Core2 Duo Processor T6400 (2M Cache, 2.00 GHz, 800 MHz FSB)"</a>. Intel Corporation. Archived from <a rel="nofollow" class="external text" href="http://ark.intel.com/cpu.aspx?groupID=40479&code=t6400">the original</a> on February 12, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">February 6,</span> 2009</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Duo+Processor+T6400+%282M+Cache%2C+2.00+GHz%2C+800+MHz+FSB%29&rft.pub=Intel+Corporation&rft_id=http%3A%2F%2Fark.intel.com%2Fcpu.aspx%3FgroupID%3D40479%26code%3Dt6400&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-T6570-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-T6570_30-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/Product.aspx?id=42841">"Intel Core2 Duo Processor T6570 (2M Cache, 2.10 GHz, 800 MHz FSB)"</a>. Intel Corporation. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110704160259/http://ark.intel.com/Product.aspx?id=42841">Archived</a> from the original on July 4, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">March 20,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Duo+Processor+T6570+%282M+Cache%2C+2.10+GHz%2C+800+MHz+FSB%29&rft.pub=Intel+Corporation&rft_id=http%3A%2F%2Fark.intel.com%2FProduct.aspx%3Fid%3D42841&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-P7350-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-P7350_31-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090205000256/http://processorfinder.intel.com/details.aspx?sSpec=SLB53">"Intel® Core™2 Duo Mobile Processor P7350 – SLB53"</a>. Archived from <a rel="nofollow" class="external text" href="http://processorfinder.intel.com/details.aspx?sSpec=SLB53">the original</a> on February 5, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">February 9,</span> 2009</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A22+Duo+Mobile+Processor+P7350+%E2%80%93+SLB53&rft_id=http%3A%2F%2Fprocessorfinder.intel.com%2Fdetails.aspx%3FsSpec%3DSLB53&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-P7450-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-P7450_32-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090516173831/http://processorfinder.intel.com/details.aspx?sSpec=SLB54">"Intel® Core™2 Duo Mobile Processor P7450 – SLB54"</a>. Archived from <a rel="nofollow" class="external text" href="http://processorfinder.intel.com/Details.aspx?sSpec=SLB54">the original</a> on May 16, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">May 2,</span> 2009</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%C2%AE+Core%E2%84%A22+Duo+Mobile+Processor+P7450+%E2%80%93+SLB54&rft_id=http%3A%2F%2Fprocessorfinder.intel.com%2FDetails.aspx%3FsSpec%3DSLB54&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-P7550-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-P7550_33-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark.html">"Intel product specifications"</a>. <i>ark.intel.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110704232233/http://ark.intel.com/Product.aspx?id=42915&processor=i5-750&spec-codes=SLBLC">Archived</a> from the original on July 4, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">June 26,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ark.intel.com&rft.atitle=Intel+product+specifications&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEric_Tung2009" class="citation web cs1">Eric Tung (March 13, 2009). <a rel="nofollow" class="external text" href="http://communities.vmware.com/thread/199449#1198447">"Re: Does VMware Fusion require a CPU supporting Intel VT-x?"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090719145012/http://communities.vmware.com/thread/199449#1198447">Archived</a> from the original on July 19, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">April 18,</span> 2009</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+Does+VMware+Fusion+require+a+CPU+supporting+Intel+VT-x%3F&rft.date=2009-03-13&rft.au=Eric+Tung&rft_id=http%3A%2F%2Fcommunities.vmware.com%2Fthread%2F199449%231198447&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-Techarp20151218-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-Techarp20151218_35-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.techarp.com/showarticle.aspx?artno=347&pgno=8">"Tech ARP – Mobile CPU Comparison Guide Rev. 12.3"</a>. Techarp.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150910082804/http://www.techarp.com/showarticle.aspx?artno=347&pgno=8">Archived</a> from the original on September 10, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">December 18,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Tech+ARP+%E2%80%93+Mobile+CPU+Comparison+Guide+Rev.+12.3&rft.pub=Techarp.com&rft_id=http%3A%2F%2Fwww.techarp.com%2Fshowarticle.aspx%3Fartno%3D347%26pgno%3D8&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080902235441/http://www.hardware.info/en-US/productdb/bGRkapiUmJjKY8g/viewproduct/Intel_Core_2_Duo_P8400/">"[ Hardware.Info ] – Intel Core 2 Duo P8400 [BX80577P8400]"</a>. September 2, 2008. Archived from <a rel="nofollow" class="external text" href="http://www.hardware.info/en-US/productdb/bGRkapiUmJjKY8g/viewproduct/Intel_Core_2_Duo_P8400/">the original</a> on September 2, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">June 26,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%5B+Hardware.Info+%5D+%E2%80%93+Intel+Core+2+Duo+P8400+%5BBX80577P8400%5D&rft.date=2008-09-02&rft_id=http%3A%2F%2Fwww.hardware.info%2Fen-US%2Fproductdb%2FbGRkapiUmJjKY8g%2Fviewproduct%2FIntel_Core_2_Duo_P8400%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090208032055/http://www.hardware.info/en-US/productdb/bGRkapiUmJjKZMg/viewproductprices/Intel_Core_2_Duo_P8600_BX80577P8600">"[ Hardware.Info ] – Intel Core 2 Duo P8600 [BX80577P8600]"</a>. February 8, 2009. Archived from <a rel="nofollow" class="external text" href="http://www.hardware.info/en-US/productdb/bGRkapiUmJjKZMg/viewproductprices/Intel_Core_2_Duo_P8600_BX80577P8600">the original</a> on February 8, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">June 26,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%5B+Hardware.Info+%5D+%E2%80%93+Intel+Core+2+Duo+P8600+%5BBX80577P8600%5D&rft.date=2009-02-08&rft_id=http%3A%2F%2Fwww.hardware.info%2Fen-US%2Fproductdb%2FbGRkapiUmJjKZMg%2Fviewproductprices%2FIntel_Core_2_Duo_P8600_BX80577P8600&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-upgrade.com/CPUs/Intel/Core_i3_Mobile/i3-2332M.html">"CPU-Upgrade: Intel Core i3-2332M CPU"</a>. <i>cpu-upgrade.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170918105705/http://www.cpu-upgrade.com/CPUs/Intel/Core_i3_Mobile/i3-2332M.html">Archived</a> from the original on September 18, 2017<span class="reference-accessdate">. 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Retrieved <span class="nowrap">October 21,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=cpu-upgrade.com&rft.atitle=CPU-Upgrade%3A+Intel+Core+i3-4010M+CPU&rft_id=https%3A%2F%2Fwww.cpu-upgrade.com%2FCPUs%2FIntel%2FCore_i3_Mobile%2Fi3-4010M.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPirzada2019" class="citation web cs1">Pirzada, Usman (August 1, 2019). <a rel="nofollow" class="external text" href="https://wccftech.com/intel-launches-10th-generation-10nm-ice-lake-mobility-processors-led-by-core-i7-1068g7-flagship-with-3-6-ghz-all-core-boost/">"Intel Launches 10th Generation 10nm 'Ice Lake' Mobility Processors - Led By Core i7 1068G7 Flagship With 3.6 GHZ All Core Boost"</a>. <i>Wccftech</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230501114942/https://wccftech.com/intel-launches-10th-generation-10nm-ice-lake-mobility-processors-led-by-core-i7-1068g7-flagship-with-3-6-ghz-all-core-boost/">Archived</a> from the original on May 1, 2023<span class="reference-accessdate">. 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Retrieved <span class="nowrap">October 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechUp+Daily&rft.atitle=i7-1365u+vs+i7-1260u+Gaming%3A+Performance+Showdown&rft.date=2024-10-19&rft.aulast=Ali&rft.aufirst=Yusuf&rft_id=https%3A%2F%2Ftechupdaily.site%2Fi7-1365u-vs-i7-1260u-gaming-performance-showdown%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> <li id="cite_note-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-43">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFIntel_Corporation" class="citation web cs1">Intel Corporation. <a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/docs/processors/core/13th-gen-core-mobile-brief.html">"13th Gen Intel Core Mobile Processor Product Brief"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230511222628/http://www.intel.com/content/www/us/en/products/docs/processors/core/13th-gen-core-mobile-brief.html">Archived</a> from the original on May 11, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">January 7,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=13th+Gen+Intel+Core+Mobile+Processor+Product+Brief&rft.au=Intel+Corporation&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fproducts%2Fdocs%2Fprocessors%2Fcore%2F13th-gen-core-mobile-brief.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+Intel+Core+processors" class="Z3988"></span></span> </li> </ol></div></div> <ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100304212004/http://www.reghardware.co.uk/2006/05/23/ati_confirms_intel_allendale/">ATI provides pointer to Intel's 'Allendale'</a>, May 23, 2006</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060716013939/http://www.theinquirer.net/default.aspx?article=32026">Rumoured prices and specifications for Intel Core 2</a>, May 30, 2006</li> <li><a rel="nofollow" class="external text" href="http://www.tgdaily.com/2006/07/24/intel_to_launch_core_2_duo">TGDaily indicates leaked release dates</a>,<sup class="noprint Inline-Template"><span style="white-space: nowrap;">[<i><a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot"><span title=" Dead link tagged April 2018">permanent dead link</span></a></i><span style="visibility:hidden; color:transparent; padding-left:2px">‍</span>]</span></sup> July 24, 2006</li> <li><a rel="nofollow" class="external text" href="http://digitimes.com/mobos/a20060717PB213.html">Intel to unveil five Merom CPUs in July, paper says</a><span style="font-size:0.95em; font-size:95%; color: var( --color-subtle, #555 )">(subscription required)</span> as re-reported by DigiTimes, July 17, 2006</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060811230151/http://www.intel.com/pressroom/archive/releases/20060727comp.htm">Intel Unveils World's Best Processor</a>,<sup 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href="http://xtreview.com/addcomment-id-2933-view-Core-2-duo-1333-mhz-stepping.html">CORE 2 DUO 1333 MHZ STEPPING</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220520215131/http://xtreview.com/addcomment-id-2933-view-Core-2-duo-1333-mhz-stepping.html">Archived</a> May 20, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, July 18, 2007</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=List_of_Intel_Core_processors&action=edit&section=198" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://qdms.intel.com/MDDS/MDDSView.aspx">Search MDDS Database</a></li> <li><a rel="nofollow" class="external text" href="http://ark.intel.com/">Intel ARK Database</a></li> <li><a rel="nofollow" class="external text" href="http://ark.intel.com/sspecqdf.aspx">SSPEC/QDF Reference</a> (Intel)</li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor_number">Intel® Processor Names, Numbers and Generation List</a></li> <li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/360/112/html/1.jpg.html">Intel CPU Transition Roadmap 2008–2013</a></li> <li><a rel="nofollow" class="external text" href="http://pc.watch.impress.co.jp/img/pcw/docs/360/112/html/2.jpg.html">Intel Desktop CPU Roadmap 2004–2011</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/notebook/sb/CS-022129.htm">Intel Core Solo mobile processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/notebook/sb/CS-022128.htm">Intel Core Duo mobile processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://download.intel.com/design/mobile/datashts/30922106.pdf">Intel Core Duo Processor and Core Solo Processor on 65 nm Process Datasheet</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20071129150113/http://download.intel.com/design/mobile/SPECUPDT/30922210.pdf">Intel Core Duo Processor and Core Solo Processor on 65 nm Process Specification Update</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/design/intarch/core2duo/tech_docs.htm">Intel Core 2 Duo Processors Technical Documents</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei3/sb/CS-031170.htm">Intel Core i3 desktop processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/corei3/sb/CS-031171.htm">Intel Core i3 mobile processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei5/sb/CS-030855.htm">Intel Core i5 desktop processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/corei5/sb/CS-031172.htm">Intel Core i5 mobile processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei7/sb/CS-029906.htm">Intel Core i7 desktop processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/corei7/sb/CS-030872.htm">Intel Core i7 mobile processor product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei7ee/sb/CS-029905.htm">Intel Core i7 desktop processor Extreme Edition product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/corei7extreme/sb/CS-030874.htm">Intel Core i7 mobile processor Extreme Edition product order code table</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor/corei7/index.htm">Intel's Core i7 web page</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor/corei7EE/index.htm">Intel's Core i7 Extreme Edition web page</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor_number/chart/corei7.htm?iid=pn_det+list_ci7">Intel's Core i7 Processor Numbers</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/products/processor_number/chart/corei7ee.htm?iid=pn_det+list_ci7ee">Intel's Core i7 Extreme Edition Processor Numbers</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141104224122/http://www.intc.com/pricelist.cfm">Intel Corporation – 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href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a class="mw-selflink selflink">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=List_of_Intel_Core_processors&oldid=1259506937">https://en.wikipedia.org/w/index.php?title=List_of_Intel_Core_processors&oldid=1259506937</a>"</div></div> <div id="catlinks" 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