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6.2525 5.55125C6.2525 5.55125 7.17375 5.2625 9.2775 6.67875C10.1575 6.43125 11.0925 6.3075 12.0275 6.3075C12.9625 6.3075 13.8975 6.43125 14.7775 6.67875C16.8813 5.24875 17.8025 5.55125 17.8025 5.55125C18.4075 7.06375 18.0225 8.19125 17.9125 8.46625C18.6138 9.23625 19.04 10.2125 19.04 11.4225C19.04 15.6437 16.4688 16.5787 14.0213 16.8537C14.42 17.1975 14.7638 17.8575 14.7638 18.8887C14.7638 20.36 14.75 21.5425 14.75 21.9137C14.75 22.2025 14.9563 22.5462 15.5063 22.4362C19.8513 20.9787 23 16.8537 23 12C23 5.9225 18.0775 1 12 1Z"></path> </svg> </a> <div class="flex-1 flex-order-2 text-right"> <a href="/login?return_to=https%3A%2F%2Fgithub.com%2Fhsluoyz%2FAtalanta" class="HeaderMenu-link HeaderMenu-button d-inline-flex d-lg-none flex-order-1 f5 no-underline border color-border-default rounded-2 px-2 py-1 color-fg-inherit js-prevent-focus-on-mobile-nav" data-hydro-click="{"event_type":"authentication.click","payload":{"location_in_page":"site header menu","repository_id":null,"auth_type":"SIGN_UP","originating_url":"https://github.com/hsluoyz/Atalanta","user_id":null}}" data-hydro-click-hmac="e0b442d2cac8a1e8d538c2624ac4d8739316a90aae7b42b7f01e29a20d174a38" data-analytics-event="{"category":"Marketing nav","action":"click to Sign in","label":"ref_page:Marketing;ref_cta:Sign in;ref_loc:Header"}" > Sign in </a> </div> </div> <div class="HeaderMenu js-header-menu height-fit position-lg-relative d-lg-flex flex-column flex-auto top-0"> <div class="HeaderMenu-wrapper d-flex flex-column flex-self-start flex-lg-row flex-auto rounded rounded-lg-0"> <nav class="HeaderMenu-nav" aria-label="Global"> <ul class="d-lg-flex list-style-none"> <li class="HeaderMenu-item position-relative flex-wrap flex-justify-between flex-items-center d-block d-lg-flex flex-lg-nowrap flex-lg-items-center js-details-container js-header-menu-item"> <button type="button" class="HeaderMenu-link border-0 width-full width-lg-auto px-0 px-lg-2 py-lg-2 no-wrap d-flex flex-items-center flex-justify-between js-details-target" aria-expanded="false"> Product <svg opacity="0.5" aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-chevron-down HeaderMenu-icon ml-1"> <path d="M12.78 5.22a.749.749 0 0 1 0 1.06l-4.25 4.25a.749.749 0 0 1-1.06 0L3.22 6.28a.749.749 0 1 1 1.06-1.06L8 8.939l3.72-3.719a.749.749 0 0 1 1.06 0Z"></path> </svg> </button> <div class="HeaderMenu-dropdown dropdown-menu rounded m-0 p-0 pt-2 pt-lg-4 position-relative position-lg-absolute left-0 left-lg-n3 pb-2 pb-lg-4 d-lg-flex flex-wrap dropdown-menu-wide"> <div class="HeaderMenu-column px-lg-4 border-lg-right mb-4 mb-lg-0 pr-lg-7"> <div class="border-bottom pb-3 pb-lg-0 border-lg-bottom-0"> <ul class="list-style-none f5" > <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"github_copilot","context":"product","tag":"link","label":"github_copilot_link_product_navbar"}" href="https://github.com/features/copilot"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-copilot color-fg-subtle mr-3"> <path d="M23.922 16.992c-.861 1.495-5.859 5.023-11.922 5.023-6.063 0-11.061-3.528-11.922-5.023A.641.641 0 0 1 0 16.736v-2.869a.841.841 0 0 1 .053-.22c.372-.935 1.347-2.292 2.605-2.656.167-.429.414-1.055.644-1.517a10.195 10.195 0 0 1-.052-1.086c0-1.331.282-2.499 1.132-3.368.397-.406.89-.717 1.474-.952 1.399-1.136 3.392-2.093 6.122-2.093 2.731 0 4.767.957 6.166 2.093.584.235 1.077.546 1.474.952.85.869 1.132 2.037 1.132 3.368 0 .368-.014.733-.052 1.086.23.462.477 1.088.644 1.517 1.258.364 2.233 1.721 2.605 2.656a.832.832 0 0 1 .053.22v2.869a.641.641 0 0 1-.078.256ZM12.172 11h-.344a4.323 4.323 0 0 1-.355.508C10.703 12.455 9.555 13 7.965 13c-1.725 0-2.989-.359-3.782-1.259a2.005 2.005 0 0 1-.085-.104L4 11.741v6.585c1.435.779 4.514 2.179 8 2.179 3.486 0 6.565-1.4 8-2.179v-6.585l-.098-.104s-.033.045-.085.104c-.793.9-2.057 1.259-3.782 1.259-1.59 0-2.738-.545-3.508-1.492a4.323 4.323 0 0 1-.355-.508h-.016.016Zm.641-2.935c.136 1.057.403 1.913.878 2.497.442.544 1.134.938 2.344.938 1.573 0 2.292-.337 2.657-.751.384-.435.558-1.15.558-2.361 0-1.14-.243-1.847-.705-2.319-.477-.488-1.319-.862-2.824-1.025-1.487-.161-2.192.138-2.533.529-.269.307-.437.808-.438 1.578v.021c0 .265.021.562.063.893Zm-1.626 0c.042-.331.063-.628.063-.894v-.02c-.001-.77-.169-1.271-.438-1.578-.341-.391-1.046-.69-2.533-.529-1.505.163-2.347.537-2.824 1.025-.462.472-.705 1.179-.705 2.319 0 1.211.175 1.926.558 2.361.365.414 1.084.751 2.657.751 1.21 0 1.902-.394 2.344-.938.475-.584.742-1.44.878-2.497Z"></path><path d="M14.5 14.25a1 1 0 0 1 1 1v2a1 1 0 0 1-2 0v-2a1 1 0 0 1 1-1Zm-5 0a1 1 0 0 1 1 1v2a1 1 0 0 1-2 0v-2a1 1 0 0 1 1-1Z"></path> </svg> <div> <div class="color-fg-default h4">GitHub Copilot</div> Write better code with AI </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"security","context":"product","tag":"link","label":"security_link_product_navbar"}" href="https://github.com/features/security"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-shield-check color-fg-subtle mr-3"> <path d="M16.53 9.78a.75.75 0 0 0-1.06-1.06L11 13.19l-1.97-1.97a.75.75 0 0 0-1.06 1.06l2.5 2.5a.75.75 0 0 0 1.06 0l5-5Z"></path><path d="m12.54.637 8.25 2.675A1.75 1.75 0 0 1 22 4.976V10c0 6.19-3.771 10.704-9.401 12.83a1.704 1.704 0 0 1-1.198 0C5.77 20.705 2 16.19 2 10V4.976c0-.758.489-1.43 1.21-1.664L11.46.637a1.748 1.748 0 0 1 1.08 0Zm-.617 1.426-8.25 2.676a.249.249 0 0 0-.173.237V10c0 5.46 3.28 9.483 8.43 11.426a.199.199 0 0 0 .14 0C17.22 19.483 20.5 15.461 20.5 10V4.976a.25.25 0 0 0-.173-.237l-8.25-2.676a.253.253 0 0 0-.154 0Z"></path> </svg> <div> <div class="color-fg-default h4">Security</div> Find and fix vulnerabilities </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"actions","context":"product","tag":"link","label":"actions_link_product_navbar"}" href="https://github.com/features/actions"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-workflow color-fg-subtle mr-3"> <path d="M1 3a2 2 0 0 1 2-2h6.5a2 2 0 0 1 2 2v6.5a2 2 0 0 1-2 2H7v4.063C7 16.355 7.644 17 8.438 17H12.5v-2.5a2 2 0 0 1 2-2H21a2 2 0 0 1 2 2V21a2 2 0 0 1-2 2h-6.5a2 2 0 0 1-2-2v-2.5H8.437A2.939 2.939 0 0 1 5.5 15.562V11.5H3a2 2 0 0 1-2-2Zm2-.5a.5.5 0 0 0-.5.5v6.5a.5.5 0 0 0 .5.5h6.5a.5.5 0 0 0 .5-.5V3a.5.5 0 0 0-.5-.5ZM14.5 14a.5.5 0 0 0-.5.5V21a.5.5 0 0 0 .5.5H21a.5.5 0 0 0 .5-.5v-6.5a.5.5 0 0 0-.5-.5Z"></path> </svg> <div> <div class="color-fg-default h4">Actions</div> Automate any workflow </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"codespaces","context":"product","tag":"link","label":"codespaces_link_product_navbar"}" href="https://github.com/features/codespaces"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-codespaces color-fg-subtle mr-3"> <path d="M3.5 3.75C3.5 2.784 4.284 2 5.25 2h13.5c.966 0 1.75.784 1.75 1.75v7.5A1.75 1.75 0 0 1 18.75 13H5.25a1.75 1.75 0 0 1-1.75-1.75Zm-2 12c0-.966.784-1.75 1.75-1.75h17.5c.966 0 1.75.784 1.75 1.75v4a1.75 1.75 0 0 1-1.75 1.75H3.25a1.75 1.75 0 0 1-1.75-1.75ZM5.25 3.5a.25.25 0 0 0-.25.25v7.5c0 .138.112.25.25.25h13.5a.25.25 0 0 0 .25-.25v-7.5a.25.25 0 0 0-.25-.25Zm-2 12a.25.25 0 0 0-.25.25v4c0 .138.112.25.25.25h17.5a.25.25 0 0 0 .25-.25v-4a.25.25 0 0 0-.25-.25Z"></path><path d="M10 17.75a.75.75 0 0 1 .75-.75h6.5a.75.75 0 0 1 0 1.5h-6.5a.75.75 0 0 1-.75-.75Zm-4 0a.75.75 0 0 1 .75-.75h.5a.75.75 0 0 1 0 1.5h-.5a.75.75 0 0 1-.75-.75Z"></path> </svg> <div> <div class="color-fg-default h4">Codespaces</div> Instant dev environments </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"issues","context":"product","tag":"link","label":"issues_link_product_navbar"}" href="https://github.com/features/issues"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon 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0-1.1l3.5-3.25a.75.75 0 0 1 1.06.04Zm3.44 1.06a.75.75 0 1 1 1.02-1.1l3.5 3.25a.75.75 0 0 1 0 1.1l-3.5 3.25a.75.75 0 1 1-1.02-1.1l2.908-2.7-2.908-2.7Z"></path><path d="M1.5 4.25c0-.966.784-1.75 1.75-1.75h17.5c.966 0 1.75.784 1.75 1.75v12.5a1.75 1.75 0 0 1-1.75 1.75h-9.69l-3.573 3.573A1.458 1.458 0 0 1 5 21.043V18.5H3.25a1.75 1.75 0 0 1-1.75-1.75ZM3.25 4a.25.25 0 0 0-.25.25v12.5c0 .138.112.25.25.25h2.5a.75.75 0 0 1 .75.75v3.19l3.72-3.72a.749.749 0 0 1 .53-.22h10a.25.25 0 0 0 .25-.25V4.25a.25.25 0 0 0-.25-.25Z"></path> </svg> <div> <div class="color-fg-default h4">Code Review</div> Manage code changes </div> </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description pb-lg-3" data-analytics-event="{"location":"navbar","action":"discussions","context":"product","tag":"link","label":"discussions_link_product_navbar"}" href="https://github.com/features/discussions"> <svg aria-hidden="true" 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class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary d-flex flex-items-center Link--has-description" data-analytics-event="{"location":"navbar","action":"code_search","context":"product","tag":"link","label":"code_search_link_product_navbar"}" href="https://github.com/features/code-search"> <svg aria-hidden="true" height="24" viewBox="0 0 24 24" version="1.1" width="24" data-view-component="true" class="octicon octicon-code-square color-fg-subtle mr-3"> <path d="M10.3 8.24a.75.75 0 0 1-.04 1.06L7.352 12l2.908 2.7a.75.75 0 1 1-1.02 1.1l-3.5-3.25a.75.75 0 0 1 0-1.1l3.5-3.25a.75.75 0 0 1 1.06.04Zm3.44 1.06a.75.75 0 1 1 1.02-1.1l3.5 3.25a.75.75 0 0 1 0 1.1l-3.5 3.25a.75.75 0 1 1-1.02-1.1l2.908-2.7-2.908-2.7Z"></path><path d="M2 3.75C2 2.784 2.784 2 3.75 2h16.5c.966 0 1.75.784 1.75 1.75v16.5A1.75 1.75 0 0 1 20.25 22H3.75A1.75 1.75 0 0 1 2 20.25Zm1.75-.25a.25.25 0 0 0-.25.25v16.5c0 .138.112.25.25.25h16.5a.25.25 0 0 0 .25-.25V3.75a.25.25 0 0 0-.25-.25Z"></path> </svg> <div> <div class="color-fg-default h4">Code Search</div> Find more, search less </div> </a></li> </ul> </div> </div> <div class="HeaderMenu-column px-lg-4"> <div class="border-bottom pb-3 pb-lg-0 border-lg-bottom-0 border-bottom-0"> <span class="d-block h4 color-fg-default my-1" id="product-explore-heading">Explore</span> <ul class="list-style-none f5" aria-labelledby="product-explore-heading"> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary" data-analytics-event="{"location":"navbar","action":"all_features","context":"product","tag":"link","label":"all_features_link_product_navbar"}" href="https://github.com/features"> All features </a></li> <li> <a class="HeaderMenu-dropdown-link d-block no-underline position-relative py-2 Link--secondary Link--external" target="_blank" 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1.275.326.749.749 0 0 1-.215.734L9.06 8l3.22 3.22a.749.749 0 0 1-.326 1.275.749.749 0 0 1-.734-.215L8 9.06l-3.22 3.22a.751.751 0 0 1-1.042-.018.751.751 0 0 1-.018-1.042L6.94 8 3.72 4.78a.75.75 0 0 1 0-1.06Z"></path> </svg></button> </div> </div> </div> <scrollable-region data-labelled-by="custom-scopes-dialog-title"> <div data-view-component="true" class="Overlay-body"> <div data-target="custom-scopes.customScopesModalDialogFlash"></div> <div hidden class="create-custom-scope-form" data-target="custom-scopes.createCustomScopeForm"> </option></form><form id="custom-scopes-dialog-form" data-turbo="false" action="/search/custom_scopes" accept-charset="UTF-8" method="post"><input type="hidden" data-csrf="true" name="authenticity_token" value="/6dgu754/sZMdZVemnT4Ti8EOwDw3DVs5E7JIB2kWZBfMhsrqLMekLZvsHHCc/OzrdataP/c6t7HwdgATHiUMw==" /> <div data-target="custom-scopes.customScopesModalDialogFlash"></div> <input type="hidden" id="custom_scope_id" name="custom_scope_id" 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aria-label="78 users starred this repository" data-singular-suffix="user starred this repository" data-plural-suffix="users starred this repository" data-turbo-replace="true" title="78" data-view-component="true" class="Counter js-social-count">78</span> </a></div> </li> </ul> </div> </div> <div id="responsive-meta-container" data-turbo-replace> <div class="d-block d-md-none mb-2 px-3 px-md-4 px-lg-5"> <p class="f4 mb-3 "> Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University. </p> <div class="mb-3"> <a class="Link--secondary no-underline mr-3" href="/hsluoyz/Atalanta/stargazers"> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-star mr-1"> <path d="M8 .25a.75.75 0 0 1 .673.418l1.882 3.815 4.21.612a.75.75 0 0 1 .416 1.279l-3.046 2.97.719 4.192a.751.751 0 0 1-1.088.791L8 12.347l-3.766 1.98a.75.75 0 0 1-1.088-.79l.72-4.194L.818 6.374a.75.75 0 0 1 .416-1.28l4.21-.611L7.327.668A.75.75 0 0 1 8 .25Zm0 2.445L6.615 5.5a.75.75 0 0 1-.564.41l-3.097.45 2.24 2.184a.75.75 0 0 1 .216.664l-.528 3.084 2.769-1.456a.75.75 0 0 1 .698 0l2.77 1.456-.53-3.084a.75.75 0 0 1 .216-.664l2.24-2.183-3.096-.45a.75.75 0 0 1-.564-.41L8 2.694Z"></path> </svg> <span class="text-bold">78</span> stars </a> <a class="Link--secondary no-underline mr-3" href="/hsluoyz/Atalanta/forks"> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-repo-forked mr-1"> <path d="M5 5.372v.878c0 .414.336.75.75.75h4.5a.75.75 0 0 0 .75-.75v-.878a2.25 2.25 0 1 1 1.5 0v.878a2.25 2.25 0 0 1-2.25 2.25h-1.5v2.128a2.251 2.251 0 1 1-1.5 0V8.5h-1.5A2.25 2.25 0 0 1 3.5 6.25v-.878a2.25 2.25 0 1 1 1.5 0ZM5 3.25a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Zm6.75.75a.75.75 0 1 0 0-1.5.75.75 0 0 0 0 1.5Zm-3 8.75a.75.75 0 1 0-1.5 0 .75.75 0 0 0 1.5 0Z"></path> </svg> <span class="text-bold">35</span> forks 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pattern generator for stuck-at faults\nin combinational circuits. It employs the FAN algorithm for test \npattern generation and the parallel pattern single fault propagation \ntechnique for fault simulation. \n\nATALANTA was developed in the Bradley Department of Electrical\nand Computer Engineering, Virginia Polytechnic Institute \u0026amp; State University\n(VPI\u0026amp;SU) and the copy right belongs to VPI\u0026amp;SU.\nThe source code is released for teaching and research use only. \nAny publication in which ATALANTA was used to obtain the results should\ncite the reference given below. (Please do not say that a public domain\ntool was used in this research.)\n\nThis program, or any derivative thereof, may not be reproduced\nnor used for any commercial product without a written permission form\nfrom Prof. Dong S. Ha. For commercial use of ATALANTA or if any bugs found, \nplease contact to\n\n\tProf. Dong S. Ha\n\tDepartment of Electrical and Computer Eng.\n\tVirginia Tech\n\tBlacksburg, VA 24061\n\n Ph.: (540) 231-4942\n Fax: (540) 231-3362\n E-Mail: ha@vt.edu\n Web: \u003ca href=\"http://www.ee.vt.edu/ha\" rel=\"nofollow\"\u003ehttp://www.ee.vt.edu/ha\u003c/a\u003e\n\n************************************************************************\n\nREFERENCE: H. K. Lee and D. S. Ha, \"On the Generation of Test Patterns \n\t for Combinational Circuits,\" Technical Report No. 12_93,\n\t Dep't of Electrical Eng., Virginia Polytechnic Institute\n and State University.\n\n\n***************************** HISTORY **********************************\n\n atalanta: version 1.0\n\n Original: H. K. Lee, 8/15/1990\n\n atalanta: version 1.1\n\n Shuffling Compaction, Sarita Thakar 12/15/93\n Added learning, dynamic unique path sensitization, H. K. Lee, 4/30/1994\n Read the fault list file, H. K. Lee, 4/30/1994\n\n atalanta: version 2.0 \n Removed the option -I, H. K. Lee, 6/30/1997\n Combined HOPE and atalanta, H. K. Lee, 6/30/1997\n (Added options: -H, -0, -1, -X, -R)\n Added diagnostic options, H. K. Lee, 6/30/1997\n (Added options: -A, -D, -Z, -N)\n\n ********************** Important Note **********************\n * *\n * Atalanta reads circuits in ISCAS89 netlist format *\n * rather than the original ISCAS85 netlist format. *\n * This is done so, since ISCAS89 netlist format is more *\n * flexible. *\n * *\n ************************************************************\n\n************************************************************************\n\n----------------- Installation Procedure -----------------------------\n\nI. To install atalanta, follow the procedures described below.\n \n 1. To install atalanta, make a bin directory under your home\n directory. Suppose that the home directory is ~cad and\n the source code of atalanta is under the directory\n ~cad/atalanta.\n \n 2. Go to the directory atalanta using\n \"cd ~cad/atalanta\".\n \n 3. To compile atalanta, type \"make\".\n An execution file \"atalanta\" will be created.\n \n 4. Copy or symbolically link atalanta to the directory ~cad/bin using\n \"cp atalanta ~cad/bin\" or\n \"ln -s atalanta ~cad/bin\".\n \n \nII. Before using atalanta, each user should set the following\n two environment variables as described below.\n \n 1. Set your path (or PATH) environment variable to include\n ~cad/bin in your search path. This variable, in general,\n can be found in your \".cshrc\" file. For example, the line\n \n set path = (... ~cad/bin ...)\n \n includes ~cad/bin to your search path.\n \n 2. Set the ATALANTA_MAN environment variable to indicate the\n directory atalanta, where the on-line manual of atalanta is \n located, using the setenv statement as shown below.\n \n \"setenv ATALANTA_MAN ~cad/atalanta\"\n \n If you use atalanta frequently, add the above statement to your\n \".cshrc\" file.\n\n\nRun atalanta as described below.\n\n\n\n----------------- User's Guide for ATALANTA --------------------------\n\nNAME:\tatalanta --- Automatic Test Pattern Generator for stuck-at \n\t\t faults in combinational circuits\n\nSYNOPSIS: atalanta [options] circuit_file [\u0026gt; outfile]\n\nOPTIONS: Several options are available for atalanta.\n If an option is not specified, the default value is used.\n\n-A Diagnostic mode\n Atalanta derives all test patterns for each fault.\n In this option, all unspecified inputs are left unknown, and\n fault simulation is not performed.\n (default: Normal test generation mode)\n-D n Diagnostic mode\n Atalanta derives n test patterns for each fault.\n In this option, all unspecified inputs are left unknown, and\n fault simulation is not performed. If both -A and -D option\n are specified, -D option is applied.\n (default: Normal test generation mode)\n-b n\t The number of maximum backtrackings for the FAN \n\t algorithm phase 1. (default: -b 10)\n-B n\t If -B n (n\u0026gt;0) option is specified, atalanta generates test\n\t patterns in two phases. In phase 1, static unique path \n\t sensitization is employed. If the test generation for a\n\t target fault is aborted in phase 1, the test generation\n\t is tried in phase 2. In phase 2, dynamic unique path\n\t sensitization is employed. If n=0, phase 2 is not performed.\n\t If n\u0026gt;0, phase 2 test generation is performed with the\n\t backtrack limit of n.\n\t (default: -B 0, i.e., phase 2 is not performed.)\n-f fn Faults are read from the file fn. \n\t This option is available only for ISCAS89 netlist format.\n (default: faults are generated internally.)\n-h f Displays the fault list format\n-h g Displays the on-line user's guide.\n-h n Displays an example netlist format.\n-h t Displays an example test pattern file.\n-h a Displays the entire on-line manual file.\n (default: no manual is displayed)\n-H HOPE, which is a parallel fault fault simulator, is employed\n for fault simulation. In this option, three logic values (0, 1\n and X), instead of two logic values (0 and 1), are employed.\n Due to the embedding of the unknown logic value and the parallel\n fault fault simulation algorithm, the test generation time is\n slower than the default mode.)\n (default: FSIM, which is a parallel pattern fault simulator,\n is employed, and two logic values are used.)\n-l fn Log file is created.\n\t (default: no logfile is created)\n-L Static learning is performed. (default: no learning)\n-c n Atalanta compacts test patterns using two different \n methods: reverse order compaction and shuffling \n compaction. First, test patterns are applied \n in the reverse order and fault simulated (reverse order \n compaction). Second, test patterns are shuffled randomly \n and fault simulated (shuffling compaction). During the fault \n simulations, all the test patterns which do not detect a \n new fault are eliminated. The option -c n specifies \n the limit of shuffling compaction. If n\u0026gt;0, shuffling \n compaction is terminated if n consecutive shuffles\n do not drop a test pattern. If n=0, shuffling\n compaction is not included and compaction is done only \n by the reverse order fault simulation.\n (default: -c 2)\n-N Test compaction is not performed.\n (default: -c 2)\n-r n\t Random Pattern Testing (RPT) Session is included before\n\t deterministic test pattern generation session.\n The RPT session stops if any n consecutive packets of\n 32 random patterns do not detect any new fault.\n\t If n=0, the RPT session is not included.\n\t (default: -r 16)\n-s n\t Initial seed for the random number generator (random()).\n\t If n=0, the initial seed is the current time.\n\t (default: -s 0)\n-t fn Test patterns are put into the file \"fn\".\n\t (default: *.test for a circuit named *.bench)\n-u Atalanta prints out all aborted fauts in a file. The name of this\n file is \u0026lt;ckt\u0026gt;.ufaults. In default, all identified redundant faults\n are not included in the file, but you can include them using the\n option -v. Note that atalanta does not update a fault file if one\n already exists in the run directory. This fault list file can\n be directly read by atalanta or hope.\n (default: no file is created)\n-U fn The same as -u, but atalanta writes aborted faults to the given\n file name.\n (default: no file is created)\n-v Atalanta prints out all identified redundant faults as well as\n aborted fauts in a file. If -U fn option is not given, Atalanta\n prints out the faults in a default file, \u0026lt;ckt\u0026gt;.ufaults.\n (default: no file is created)\n-Z Atalanta derives one test pattern for each fault. In this option,\n no fault simulation is performed during the entire test generation\n (including random pattern test generation session, deterministic\n test generation session and test compaction session). All unspecified\n inputs are left unknown.\n-0, -1, -X, -R: During test generation, some inputs can be unspecified.\n Atalanta provides various options to set these unspecified inputs\n into a certain value. The options are described below.\n -0 Unspecified inputs are set to logic 0.\n -1 Unspecified inputs are set to logic 1.\n -R Unspecified inputs are set to logic 0 or logic 1 randomly.\n -X Unspecified inputs are left to unknown (X).\n (default: -R)\n\nOUTPUTS: In default mode, one file is created. The summary \n\t of the test pattern generation is reported to the \n\t standard output and the test patterns are stored in\n\t the circuit_name.test file. If -l option \n\t is specified, atalanta creates a log file. \n\t The log file contains more detailed information\n\t on the test pattern generation result.\n\nON-LINE HELP: Type atalanta to see the available on-line\n help command.\n\nEXAMPLES:\n\tatalanta c432.bench\n\t --- generates test patterns for the circuit c432.bench\n\t with default options (i.e., the same as\n\t atalanta -r 16 -R -s 0 -b 10 -B 20 -c 2 -t c432.test \n \t c432.bench).\n\t The generated test patterns are stored in file \n\t c432.test and the summary of the test pattern\n\t is reported to the standard output (CRT terminal).\n\n atalanta -A -f c432.flt c432.bench\n --- Diagnostic mode run\n reads the fault list from the file c432.flt, and\n generates all test patterns for each fault.\n\n atalanta -D 2 c432.bench\n --- Diagnostic mode run\n Generates n test patterns for each fault.\n\n\n\n\nNETLIST FORMAT:\n\n\t The input netlist format for atalanta is ISCAS89 \n\tnetlist format except for the following two cases.\n\tThe first line should be # followed by the name of \n\tthe circuit. The lines beginning with # excluding\n\tthe first line are comment lines and ignored. These\n\tcomment lines may be put into any part of the netlist.\n\tIt should be noted that the order of gates appearing\n\tin the netlist is not significant.\n\tThe name of gates can be a string of alpha-numeric\n\tcharacters (0-9, A-Z, a-z, _, [, or ]).\n\n\tISCAS85 circuits translated in ISCAS89 netlist\n\tformat are stored in directory ISCAS85. The name of a \n\tcircuit in ISCAS89 netlist format is circuit_name.bench.\n\n\t Example netlists of the circuit c17 written in\n\tISCAS89 netlist format is shown below.\n\n\nEXAMPLE: ISCAS89 NETLIST FORMAT (c17.bench)\n--------------------------------------------------------------------\n# c17\n# 5 inputs\n# 2 outputs\n# 0 inverters\n# 6 gates ( 6 NANDs )\n\nINPUT(1)\nINPUT(2)\nINPUT(3)\nINPUT(6)\nINPUT(7)\n\nOUTPUT(22)\nOUTPUT(23)\n\n10 = NAND(1, 3)\n11 = NAND(3, 6)\n16 = NAND(2, 11)\n19 = NAND(11, 7)\n22 = NAND(10, 16)\n23 = NAND(16, 19)\n-------------------------------------------------------------------\n\n\n\nMANAGEABLE GATES:\n\n-------------------------------------------------------\n syntax gate type\n-------------------------------------------------------\n INPUT primary input\n OUTPUT primary output\n AND and gate\n NAND nand gate\n OR or gate\n NOR nor gate\n XOR 2-input exclusive-or gate\n BUFF or BUF buffer\n NOT inverter\n-------------------------------------------------------\n* Gate types can be also written in lower case.\n\n\n\n\nTEST PATTERN FILE:\n\n\t The line beginning with * is a comment line and\n\tignored. Each test pattern begins after a colon (:).\n\tFor an n input circuit, only the n bits following :\n\tare significant, and the remaining bits, if any, are\n\tignored. The j'th bit of a test pattern is the value \n\tof the j'th input of the circuit (in terms of their\n\tappearance in the circuit). For example, c17 has five\n\tinputs named input1, input2, input3, input6 and input7\n\twhich appear in the order in the netlist. The first bit\n\tof a test pattern is the value for input1, the second \n\tfor input2, ..., and the last for input7.\n\n\nEXAMPLE: TEST PATTERN FILE FOR C17\n\n___________________________________________________________\n* Name of circuit: c17\n\n 1: 01010\n 2: 11110\n 3: 10101\n 4: 00111\n 5: 10010\n 6: 00101\n__________________________________________________________\n\n\n\nFAULT LIST FILE:\n \n ATALANTA can read the fault list file supplied\n by the user. When the option \"-f fn\" is specified,\n the fault list is read from the file \"fn\". (In default,\n the fault list is created internally.)\n \n An example of the fault list file is shown below:\n \n ------ EXAMPLE: A FAULT LIST FILE ----------------------\n gate_A-\u0026gt;gate_B /1\n gate_A-\u0026gt;gate_B /0\n gate_A /1\n gate_B /1\n bin[2] -\u0026gt; gate_B /1\n --------------------------------------------------------\n \n In the above example, gate_A and gate_B are the name\n of gates. The first line, \"gate_A-\u0026gt;gate_B /1\" describes\n the stuck-at 1 fault on the gate_B input line, which\n is connected to gate_A. Similarly, the second line,\n \"gate_A-\u0026gt;gate_B /0\" describes the stuck-at 0 fault on the\n gate B input which is connected to gate_A. The third and\n fourth lines describe the stuck-at 1 faults on the gate_A\n output and the gate_B output, respectively. \n \n ******************* Note **********************************\n No fault collapsing is performed under the option -f. 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viewBox="0 0 16 16" width="16" height="16" fill="currentColor" display="inline-block" overflow="visible" style="vertical-align:text-bottom"><path d="M2 1.75C2 .784 2.784 0 3.75 0h6.586c.464 0 .909.184 1.237.513l2.914 2.914c.329.328.513.773.513 1.237v9.586A1.75 1.75 0 0 1 13.25 16h-9.5A1.75 1.75 0 0 1 2 14.25Zm1.75-.25a.25.25 0 0 0-.25.25v12.5c0 .138.112.25.25.25h9.5a.25.25 0 0 0 .25-.25V6h-2.75A1.75 1.75 0 0 1 9 4.25V1.5Zm6.75.062V4.25c0 .138.112.25.25.25h2.688l-.011-.013-2.914-2.914-.013-.011Z"></path></svg><div class="overflow-hidden"><div class="react-directory-filename-cell"><div class="react-directory-truncate"><a title="Atalanta.PO" aria-label="Atalanta.PO, (File)" class="Link--primary" href="/hsluoyz/Atalanta/blob/master/Atalanta.PO">Atalanta.PO</a></div></div></div></div></td><td class="react-directory-row-commit-cell"><div class="Skeleton Skeleton--text"> </div></td><td><div class="Skeleton Skeleton--text"> </div></td></tr><tr class="react-directory-row truncate-for-mobile" id="folder-row-10"><td class="react-directory-row-name-cell-small-screen" colSpan="2"><div class="react-directory-filename-column"><svg aria-hidden="true" focusable="false" class="octicon octicon-file color-fg-muted" viewBox="0 0 16 16" width="16" height="16" fill="currentColor" display="inline-block" overflow="visible" style="vertical-align:text-bottom"><path d="M2 1.75C2 .784 2.784 0 3.75 0h6.586c.464 0 .909.184 1.237.513l2.914 2.914c.329.328.513.773.513 1.237v9.586A1.75 1.75 0 0 1 13.25 16h-9.5A1.75 1.75 0 0 1 2 14.25Zm1.75-.25a.25.25 0 0 0-.25.25v12.5c0 .138.112.25.25.25h9.5a.25.25 0 0 0 .25-.25V6h-2.75A1.75 1.75 0 0 1 9 4.25V1.5Zm6.75.062V4.25c0 .138.112.25.25.25h2.688l-.011-.013-2.914-2.914-.013-.011Z"></path></svg><div class="overflow-hidden"><div class="react-directory-filename-cell"><div class="react-directory-truncate"><a title="Atalanta.PR" aria-label="Atalanta.PR, (File)" class="Link--primary" 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1h4.253c1.227 0 2.317.59 3 1.501A3.743 3.743 0 0 1 11.006 1h4.245a.75.75 0 0 1 .75.75v10.5a.75.75 0 0 1-.75.75h-4.507a2.25 2.25 0 0 0-1.591.659l-.622.621a.75.75 0 0 1-1.06 0l-.622-.621A2.25 2.25 0 0 0 5.258 13H.75a.75.75 0 0 1-.75-.75Zm7.251 10.324.004-5.073-.002-2.253A2.25 2.25 0 0 0 5.003 2.5H1.5v9h3.757a3.75 3.75 0 0 1 1.994.574ZM8.755 4.75l-.004 7.322a3.752 3.752 0 0 1 1.992-.572H14.5v-9h-3.495a2.25 2.25 0 0 0-2.25 2.25Z"></path></svg></span><span data-component="text" data-content="README">README</span></a></li></ul></nav></div><div class="Box-sc-g0xbh4-0 QkQOb js-snippet-clipboard-copy-unpositioned undefined" data-hpc="true"><div class="plain"><pre style="white-space: pre-wrap"> *********************************************************************** Welcome to ATALANTA <Version 2.0>! ATALANTA is an automatic test pattern generator for stuck-at faults in combinational circuits. It employs the FAN algorithm for test pattern generation and the parallel pattern single fault propagation technique for fault simulation. ATALANTA was developed in the Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute & State University (VPI&SU) and the copy right belongs to VPI&SU. The source code is released for teaching and research use only. Any publication in which ATALANTA was used to obtain the results should cite the reference given below. (Please do not say that a public domain tool was used in this research.) This program, or any derivative thereof, may not be reproduced nor used for any commercial product without a written permission form from Prof. Dong S. Ha. For commercial use of ATALANTA or if any bugs found, please contact to Prof. Dong S. Ha Department of Electrical and Computer Eng. Virginia Tech Blacksburg, VA 24061 Ph.: (540) 231-4942 Fax: (540) 231-3362 E-Mail: ha@vt.edu Web: <a href="http://www.ee.vt.edu/ha" rel="nofollow">http://www.ee.vt.edu/ha</a> ************************************************************************ REFERENCE: H. K. Lee and D. S. Ha, "On the Generation of Test Patterns for Combinational Circuits," Technical Report No. 12_93, Dep't of Electrical Eng., Virginia Polytechnic Institute and State University. ***************************** HISTORY ********************************** atalanta: version 1.0 Original: H. K. Lee, 8/15/1990 atalanta: version 1.1 Shuffling Compaction, Sarita Thakar 12/15/93 Added learning, dynamic unique path sensitization, H. K. Lee, 4/30/1994 Read the fault list file, H. K. Lee, 4/30/1994 atalanta: version 2.0 Removed the option -I, H. K. Lee, 6/30/1997 Combined HOPE and atalanta, H. K. Lee, 6/30/1997 (Added options: -H, -0, -1, -X, -R) Added diagnostic options, H. K. Lee, 6/30/1997 (Added options: -A, -D, -Z, -N) ********************** Important Note ********************** * * * Atalanta reads circuits in ISCAS89 netlist format * * rather than the original ISCAS85 netlist format. * * This is done so, since ISCAS89 netlist format is more * * flexible. * * * ************************************************************ ************************************************************************ ----------------- Installation Procedure ----------------------------- I. To install atalanta, follow the procedures described below. 1. To install atalanta, make a bin directory under your home directory. Suppose that the home directory is ~cad and the source code of atalanta is under the directory ~cad/atalanta. 2. Go to the directory atalanta using "cd ~cad/atalanta". 3. To compile atalanta, type "make". An execution file "atalanta" will be created. 4. Copy or symbolically link atalanta to the directory ~cad/bin using "cp atalanta ~cad/bin" or "ln -s atalanta ~cad/bin". II. Before using atalanta, each user should set the following two environment variables as described below. 1. Set your path (or PATH) environment variable to include ~cad/bin in your search path. This variable, in general, can be found in your ".cshrc" file. For example, the line set path = (... ~cad/bin ...) includes ~cad/bin to your search path. 2. Set the ATALANTA_MAN environment variable to indicate the directory atalanta, where the on-line manual of atalanta is located, using the setenv statement as shown below. "setenv ATALANTA_MAN ~cad/atalanta" If you use atalanta frequently, add the above statement to your ".cshrc" file. Run atalanta as described below. ----------------- User's Guide for ATALANTA -------------------------- NAME: atalanta --- Automatic Test Pattern Generator for stuck-at faults in combinational circuits SYNOPSIS: atalanta [options] circuit_file [> outfile] OPTIONS: Several options are available for atalanta. If an option is not specified, the default value is used. -A Diagnostic mode Atalanta derives all test patterns for each fault. In this option, all unspecified inputs are left unknown, and fault simulation is not performed. (default: Normal test generation mode) -D n Diagnostic mode Atalanta derives n test patterns for each fault. In this option, all unspecified inputs are left unknown, and fault simulation is not performed. If both -A and -D option are specified, -D option is applied. (default: Normal test generation mode) -b n The number of maximum backtrackings for the FAN algorithm phase 1. (default: -b 10) -B n If -B n (n>0) option is specified, atalanta generates test patterns in two phases. In phase 1, static unique path sensitization is employed. If the test generation for a target fault is aborted in phase 1, the test generation is tried in phase 2. In phase 2, dynamic unique path sensitization is employed. If n=0, phase 2 is not performed. If n>0, phase 2 test generation is performed with the backtrack limit of n. (default: -B 0, i.e., phase 2 is not performed.) -f fn Faults are read from the file fn. This option is available only for ISCAS89 netlist format. (default: faults are generated internally.) -h f Displays the fault list format -h g Displays the on-line user's guide. -h n Displays an example netlist format. -h t Displays an example test pattern file. -h a Displays the entire on-line manual file. (default: no manual is displayed) -H HOPE, which is a parallel fault fault simulator, is employed for fault simulation. In this option, three logic values (0, 1 and X), instead of two logic values (0 and 1), are employed. Due to the embedding of the unknown logic value and the parallel fault fault simulation algorithm, the test generation time is slower than the default mode.) (default: FSIM, which is a parallel pattern fault simulator, is employed, and two logic values are used.) -l fn Log file is created. (default: no logfile is created) -L Static learning is performed. (default: no learning) -c n Atalanta compacts test patterns using two different methods: reverse order compaction and shuffling compaction. First, test patterns are applied in the reverse order and fault simulated (reverse order compaction). Second, test patterns are shuffled randomly and fault simulated (shuffling compaction). During the fault simulations, all the test patterns which do not detect a new fault are eliminated. The option -c n specifies the limit of shuffling compaction. If n>0, shuffling compaction is terminated if n consecutive shuffles do not drop a test pattern. If n=0, shuffling compaction is not included and compaction is done only by the reverse order fault simulation. (default: -c 2) -N Test compaction is not performed. (default: -c 2) -r n Random Pattern Testing (RPT) Session is included before deterministic test pattern generation session. The RPT session stops if any n consecutive packets of 32 random patterns do not detect any new fault. If n=0, the RPT session is not included. (default: -r 16) -s n Initial seed for the random number generator (random()). If n=0, the initial seed is the current time. (default: -s 0) -t fn Test patterns are put into the file "fn". (default: *.test for a circuit named *.bench) -u Atalanta prints out all aborted fauts in a file. The name of this file is <ckt>.ufaults. In default, all identified redundant faults are not included in the file, but you can include them using the option -v. Note that atalanta does not update a fault file if one already exists in the run directory. This fault list file can be directly read by atalanta or hope. (default: no file is created) -U fn The same as -u, but atalanta writes aborted faults to the given file name. (default: no file is created) -v Atalanta prints out all identified redundant faults as well as aborted fauts in a file. If -U fn option is not given, Atalanta prints out the faults in a default file, <ckt>.ufaults. (default: no file is created) -Z Atalanta derives one test pattern for each fault. In this option, no fault simulation is performed during the entire test generation (including random pattern test generation session, deterministic test generation session and test compaction session). All unspecified inputs are left unknown. -0, -1, -X, -R: During test generation, some inputs can be unspecified. Atalanta provides various options to set these unspecified inputs into a certain value. The options are described below. -0 Unspecified inputs are set to logic 0. -1 Unspecified inputs are set to logic 1. -R Unspecified inputs are set to logic 0 or logic 1 randomly. -X Unspecified inputs are left to unknown (X). (default: -R) OUTPUTS: In default mode, one file is created. The summary of the test pattern generation is reported to the standard output and the test patterns are stored in the circuit_name.test file. If -l option is specified, atalanta creates a log file. The log file contains more detailed information on the test pattern generation result. ON-LINE HELP: Type atalanta to see the available on-line help command. EXAMPLES: atalanta c432.bench --- generates test patterns for the circuit c432.bench with default options (i.e., the same as atalanta -r 16 -R -s 0 -b 10 -B 20 -c 2 -t c432.test c432.bench). The generated test patterns are stored in file c432.test and the summary of the test pattern is reported to the standard output (CRT terminal). atalanta -A -f c432.flt c432.bench --- Diagnostic mode run reads the fault list from the file c432.flt, and generates all test patterns for each fault. atalanta -D 2 c432.bench --- Diagnostic mode run Generates n test patterns for each fault. NETLIST FORMAT: The input netlist format for atalanta is ISCAS89 netlist format except for the following two cases. The first line should be # followed by the name of the circuit. The lines beginning with # excluding the first line are comment lines and ignored. These comment lines may be put into any part of the netlist. It should be noted that the order of gates appearing in the netlist is not significant. The name of gates can be a string of alpha-numeric characters (0-9, A-Z, a-z, _, [, or ]). ISCAS85 circuits translated in ISCAS89 netlist format are stored in directory ISCAS85. The name of a circuit in ISCAS89 netlist format is circuit_name.bench. Example netlists of the circuit c17 written in ISCAS89 netlist format is shown below. EXAMPLE: ISCAS89 NETLIST FORMAT (c17.bench) -------------------------------------------------------------------- # c17 # 5 inputs # 2 outputs # 0 inverters # 6 gates ( 6 NANDs ) INPUT(1) INPUT(2) INPUT(3) INPUT(6) INPUT(7) OUTPUT(22) OUTPUT(23) 10 = NAND(1, 3) 11 = NAND(3, 6) 16 = NAND(2, 11) 19 = NAND(11, 7) 22 = NAND(10, 16) 23 = NAND(16, 19) ------------------------------------------------------------------- MANAGEABLE GATES: ------------------------------------------------------- syntax gate type ------------------------------------------------------- INPUT primary input OUTPUT primary output AND and gate NAND nand gate OR or gate NOR nor gate XOR 2-input exclusive-or gate BUFF or BUF buffer NOT inverter ------------------------------------------------------- * Gate types can be also written in lower case. TEST PATTERN FILE: The line beginning with * is a comment line and ignored. Each test pattern begins after a colon (:). For an n input circuit, only the n bits following : are significant, and the remaining bits, if any, are ignored. The j'th bit of a test pattern is the value of the j'th input of the circuit (in terms of their appearance in the circuit). For example, c17 has five inputs named input1, input2, input3, input6 and input7 which appear in the order in the netlist. The first bit of a test pattern is the value for input1, the second for input2, ..., and the last for input7. EXAMPLE: TEST PATTERN FILE FOR C17 ___________________________________________________________ * Name of circuit: c17 1: 01010 2: 11110 3: 10101 4: 00111 5: 10010 6: 00101 __________________________________________________________ FAULT LIST FILE: ATALANTA can read the fault list file supplied by the user. When the option "-f fn" is specified, the fault list is read from the file "fn". (In default, the fault list is created internally.) An example of the fault list file is shown below: ------ EXAMPLE: A FAULT LIST FILE ---------------------- gate_A->gate_B /1 gate_A->gate_B /0 gate_A /1 gate_B /1 bin[2] -> gate_B /1 -------------------------------------------------------- In the above example, gate_A and gate_B are the name of gates. The first line, "gate_A->gate_B /1" describes the stuck-at 1 fault on the gate_B input line, which is connected to gate_A. Similarly, the second line, "gate_A->gate_B /0" describes the stuck-at 0 fault on the gate B input which is connected to gate_A. The third and fourth lines describe the stuck-at 1 faults on the gate_A output and the gate_B output, respectively. ******************* Note ********************************** No fault collapsing is performed under the option -f. Hence, users should provide the collapsed fault list. *********************************************************** </pre></div></div></div></div></div></div>   <script type="application/json" id="__PRIMER_DATA_:R0:__">{"resolvedServerColorMode":"day"}</script></div> </react-partial> <input type="hidden" data-csrf="true" value="NTTz/abQwssXFQ8HNSC7s5ZQXtl2r4Qfnk8qYsenpoMEHyeorNn4BkhURn+OgUkZtiwa6pnCFwxKQ/S3fdvf9A==" /> </div> <div data-view-component="true" class="Layout-sidebar"> <div class="BorderGrid about-margin" data-pjax> <div class="BorderGrid-row"> <div class="BorderGrid-cell"> <div class="hide-sm hide-md"> <h2 class="mb-3 h4">About</h2> <p class="f4 my-3"> Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University. </p> <h3 class="sr-only">Topics</h3> <div class="my-3"> <div class="f6"> <a href="/topics/verilog" title="Topic: verilog" data-view-component="true" class="topic-tag topic-tag-link"> verilog </a> <a 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1 5 9.25Zm1.75-.25a.25.25 0 0 0-.25.25v7.5c0 .138.112.25.25.25h7.5a.25.25 0 0 0 .25-.25v-7.5a.25.25 0 0 0-.25-.25Z"></path> </svg> <svg aria-hidden="true" height="16" viewBox="0 0 16 16" version="1.1" width="16" data-view-component="true" class="octicon octicon-check js-clipboard-check-icon color-fg-success d-none"> <path d="M13.78 4.22a.75.75 0 0 1 0 1.06l-7.25 7.25a.75.75 0 0 1-1.06 0L2.22 9.28a.751.751 0 0 1 .018-1.042.751.751 0 0 1 1.042-.018L6 10.94l6.72-6.72a.75.75 0 0 1 1.06 0Z"></path> </svg> </clipboard-copy> </div> </template> </div> <div id="js-global-screen-reader-notice" class="sr-only mt-n1" aria-live="polite" aria-atomic="true" ></div> <div id="js-global-screen-reader-notice-assertive" class="sr-only mt-n1" aria-live="assertive" aria-atomic="true"></div> </body> </html>