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title="GDDR4 – Czech" lang="cs" hreflang="cs" data-title="GDDR4" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/GDDR4" title="GDDR4 – Spanish" lang="es" hreflang="es" data-title="GDDR4" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/GDDR4" title="GDDR4 – French" lang="fr" hreflang="fr" data-title="GDDR4" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM – Korean" lang="ko" hreflang="ko" data-title="GDDR4 SDRAM" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/GDDR4" title="GDDR4 – Japanese" lang="ja" hreflang="ja" data-title="GDDR4" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/GDDR4" title="GDDR4 – Polish" lang="pl" hreflang="pl" data-title="GDDR4" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/GDDR4" title="GDDR4 – Portuguese" lang="pt" hreflang="pt" data-title="GDDR4" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/GDDR4" title="GDDR4 – Russian" lang="ru" hreflang="ru" data-title="GDDR4" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/GDDR4" title="GDDR4 – Slovak" lang="sk" hreflang="sk" data-title="GDDR4" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/GDDR4" title="GDDR4 – Serbian" lang="sr" hreflang="sr" data-title="GDDR4" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li 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div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">This article is about DDR graphics RAM (SGRAM). For non-graphics (dynamic) DDR memory, see <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">GDDR4 SDRAM<br /><span style="font-size:85%;">Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory</span></caption><tbody><tr><td colspan="2" class="infobox-subheader">Type of <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a></td></tr><tr><th scope="row" class="infobox-label">Developer</th><td class="infobox-data"><a href="/wiki/JEDEC" title="JEDEC">JEDEC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a></td></tr><tr><th scope="row" class="infobox-label">Generation</th><td class="infobox-data">4th generation</td></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3 SDRAM</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5 SDRAM</a></td></tr></tbody></table> <p><b>GDDR4 SDRAM</b>, an abbreviation for <b>Graphics Double Data Rate 4 Synchronous Dynamic Random-Access Memory</b>, is a type of <a href="/wiki/Graphics_card" title="Graphics card">graphics card</a> <a href="/wiki/Random_access_memory" class="mw-redirect" title="Random access memory">memory</a> (SGRAM) specified by the <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> Semiconductor Memory Standard.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> It is a rival medium to <a href="/wiki/Rambus" title="Rambus">Rambus's</a> <a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a>. GDDR4 is based on <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> technology and was intended to replace the <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a>-based <a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>, but it ended up being replaced by <a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a> within a year. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>On October 26, 2005, <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> announced that it developed the first GDDR4 memory, a 256-<a href="/wiki/Mebibit" class="mw-redirect" title="Mebibit">Mbit</a> chip running at 2.5 <a href="/wiki/Gibibit" class="mw-redirect" title="Gibibit">Gbit/s</a>. Samsung also revealed plans to sample and mass-produce GDDR4 SDRAM rated at 2.8 Gbit/s per pin.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></li> <li>In 2005, <a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a> developed the first 512-Mbit GDDR4 memory chip.<sup id="cite_ref-hynix2000s_4-0" class="reference"><a href="#cite_note-hynix2000s-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup></li> <li>On February 14, 2006, Samsung announced the development of 32-bit 512-Mbit GDDR4 SDRAM capable of transferring 3.2 Gbit/s per pin, or 12.8 GB/s for the module.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup></li> <li>On July 5, 2006, Samsung announced the mass-production of 32-bit 512-Mbit GDDR4 SDRAM rated at 2.4 Gbit/s per pin, or 9.6 GB/s for the module. Although designed to match the performance of XDR DRAM on high-pin-count memory, it would not be able to match XDR performance on low-pin-count designs.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup></li> <li>On February 9, 2007, Samsung announced mass-production of 32-bit 512-Mbit GDDR4 SDRAM, rated at 2.8 Gbit/s per pin, or 11.2 GB/s per module. This module was used for some <a href="/wiki/AMD" title="AMD">AMD</a> cards.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup></li> <li>On February 23, 2007, Samsung announced 32-bit 512-Mbit GDDR4 SDRAM rated at 4.0 Gbit/s per pin or 16 GB/s for the module and expects the memory to appear on commercially available graphics cards by the end of year 2007.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Technologies">Technologies</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=2" title="Edit section: Technologies"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>GDDR4 SDRAM introduced DBI (Data Bus Inversion) and Multi-Preamble to reduce data transmission delay. <a href="/wiki/Prefetch_buffer" class="mw-redirect" title="Prefetch buffer">Prefetch</a> was increased from 4 to 8 bits. The maximum number of memory banks for GDDR4 has been increased to 8. Core voltage was decreased to 1.5 V. </p><p>Data Bus Inversion adds an additional <a href="/wiki/Active-low" class="mw-redirect" title="Active-low">active-low</a> DBI# pin to the address/command bus and each byte of data. If there are at more than four 0 bits in the data byte, the byte is inverted and the DBI# signal transmitted low. In this way, the number of 0 bits across all nine pins is limited to four.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 9">: 9 </span></sup> This reduces power consumption and <a href="/wiki/Ground_bounce" title="Ground bounce">ground bounce</a>. </p><p>On the signaling front, GDDR4 expands the chip I/O buffer to 8 bits per two cycles, allowing for greater sustained bandwidth during burst transmission, but at the expense of significantly increased <a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a> (CL), determined mainly by the double reduced count of the address/command pins and half-clocked DRAM cells, compared to GDDR3. The number of addressing pins was reduced to half that of the GDDR3 core, and were used for power and ground, which also increases latency. Another advantage of GDDR4 is power efficiency: running at 2.4 Gbit/s, it uses 45% less power when compared to GDDR3 chips running at 2.0 Gbit/s. </p><p>In Samsung's GDDR4 SDRAM datasheet, it was referred as 'GDDR4 SGRAM', or 'Graphics Double Data Rate version 4 Synchronous Graphics RAM'. However, the essential block write feature is not available, so it is not classified as <a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Adoption">Adoption</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=3" title="Edit section: Adoption"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The video memory manufacturer <a href="/wiki/Qimonda" title="Qimonda">Qimonda</a> (formerly <a href="/wiki/Infineon" class="mw-redirect" title="Infineon">Infineon</a> Memory Products division) has stated it will "skip" the development of GDDR4, and move directly to <a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=4" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_interface_bit_rates" title="List of interface bit rates">List of interface bit rates</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=5" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist 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a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jedec.org/standards-documents/results/SGRAM">"Standards & Documents Search: sgram"</a>. www.jedec.org<span class="reference-accessdate">. Retrieved <span class="nowrap">9 September</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Standards+%26+Documents+Search%3A+sgram&rft.pub=www.jedec.org&rft_id=http%3A%2F%2Fwww.jedec.org%2Fstandards-documents%2Fresults%2FSGRAM&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jedec.org/standards-documents/results/GDDR4">"Standards & Documents Search: gddr4"</a>. www.jedec.org<span class="reference-accessdate">. Retrieved <span class="nowrap">9 September</span> 2013</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Standards+%26+Documents+Search%3A+gddr4&rft.pub=www.jedec.org&rft_id=http%3A%2F%2Fwww.jedec.org%2Fstandards-documents%2Fresults%2FGDDR4&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-industrys-first-ultra-fast-gddr4-graphics-dram/">"Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM"</a>. <i><a href="/wiki/Samsung_Semiconductor" class="mw-redirect" title="Samsung Semiconductor">Samsung Semiconductor</a></i>. <a href="/wiki/Samsung" title="Samsung">Samsung</a>. October 26, 2005<span class="reference-accessdate">. Retrieved <span class="nowrap">8 July</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Samsung+Semiconductor&rft.atitle=Samsung+Electronics+Develops+Industry%27s+First+Ultra-Fast+GDDR4+Graphics+DRAM&rft.date=2005-10-26&rft_id=https%3A%2F%2Fwww.samsung.com%2Fsemiconductor%2Finsights%2Fnews-events%2Fsamsung-electronics-develops-industrys-first-ultra-fast-gddr4-graphics-dram%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-hynix2000s-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-hynix2000s_4-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20200806163108/https://www.skhynix.com/eng/about/history2000.jsp">"History: 2000s"</a>. <i><a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a></i>. Archived from <a rel="nofollow" class="external text" href="https://www.skhynix.com/eng/about/history2000.jsp">the original</a> on 6 August 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">8 July</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=SK+Hynix&rft.atitle=History%3A+2000s&rft_id=https%3A%2F%2Fwww.skhynix.com%2Feng%2Fabout%2Fhistory2000.jsp&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.samsung.com/Products/Semiconductor/News/GraphicsMemory/category_GraphicsMemory_20060214_0000233753.htm">Samsung Develops Ultra-fast Graphics Memory: A More Advanced GDDR4 at Higher Density</a></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060706142817/http://www.tgdaily.com/2006/07/05/samsung_gddr4/">Samsung sends GDDR4 graphics memory into mass production</a></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070212033434/http://theinquirer.net/default.aspx?article=37559">"Samsung releases fastest GDDR-4 SGRAM"</a>. <i><a href="/wiki/The_Inquirer" title="The Inquirer">The Inquirer</a></i>. Archived from the original on 2007-02-12.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Inquirer&rft.atitle=Samsung+releases+fastest+GDDR-4+SGRAM&rft_id=http%3A%2F%2Fwww.theinquirer.net%2Fdefault.aspx%3Farticle%3D37559&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070225083354/http://www.tgdaily.com/2007/02/23/samsung_gddr/">Samsung accelerates graphics memory to 2000 MHz</a></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChoi2011" class="citation conference cs1">Choi, J.S. (2011). <a rel="nofollow" class="external text" href="https://www.jedec.org/sites/default/files/JS_Choi_DDR4_miniWorkshop.pdf#page=9"><i>DDR4 Mini Workshop</i></a> <span class="cs1-format">(PDF)</span>. Server Memory Forum 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=DDR4+Mini+Workshop&rft.date=2011&rft.aulast=Choi&rft.aufirst=J.S.&rft_id=https%3A%2F%2Fwww.jedec.org%2Fsites%2Fdefault%2Ffiles%2FJS_Choi_DDR4_miniWorkshop.pdf%23page%3D9&rfr_id=info%3Asid%2Fen.wikipedia.org%3AGDDR4+SDRAM" class="Z3988"></span> This presentation is about DDR4 rather than GDDR4, but both use data bus inversion.</span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://news.softpedia.com/news/Qimonda-Plans-GDDR5-50282.shtml">Softpedia report</a></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=GDDR4_SDRAM&action=edit&section=6" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150128201329/http://www.xbitlabs.com/news/memory/display/20040505122429.html">X-Bit Labs (GDDR4 closing in)</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141228073217/http://www.xbitlabs.com/news/memory/display/20060214062714.html">X-Bit Labs (GDDR4 achieving 3.2 GHz)</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131203095557/http://www.dailytech.com/article.aspx?newsid=3781">DailyTech (ATI X1950 Now September 14)</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131203100000/http://www.dailytech.com/article.aspx?newsid=3446">DailyTech (ATI Radeon X1950 Announced)</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131203100546/http://www.dailytech.com/article.aspx?newsid=3162">(Samsung Shipping Production GDDR4)</a></li> <li><a rel="nofollow" class="external text" href="http://www.samsung.com/Products/Semiconductor/News/GraphicsMemory/category_GraphicsMemory_20060705_0000273583.htm">Samsung Mass Producing Most Advanced Graphics Memory: GDDR4, press release</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol 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title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)" style="font-size:114%;margin:0 4em"><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a></li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a></li></ul></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a class="mw-selflink selflink">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Timeline" title="Synchronous dynamic random-access memory">SDRAM timeline</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Dynamic_random-access_memory" title="List of interface bit rates">Bandwidth</a></li> <li><a href="/wiki/Transistor_count#Memory" title="Transistor count">Transistor count</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Graphics_processing_unit" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Graphics_Processing_Unit" title="Template:Graphics Processing Unit"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Graphics_Processing_Unit" title="Template talk:Graphics Processing Unit"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Graphics_Processing_Unit" title="Special:EditPage/Template:Graphics Processing Unit"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Graphics_processing_unit" style="font-size:114%;margin:0 4em"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">GPU</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Desktop</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel</a> <ul><li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">GT</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/List_of_Nvidia_graphics_processing_units" title="List of Nvidia graphics processing units">Nvidia</a> <ul><li><a href="/wiki/GeForce" title="GeForce">GeForce</a></li> <li><a href="/wiki/Quadro" title="Quadro">Quadro</a></li> <li><a href="/wiki/Nvidia_Tesla" title="Nvidia Tesla">Tesla</a></li> <li><a href="/wiki/Nvidia_Tegra" class="mw-redirect" title="Nvidia Tegra">Tegra</a></li></ul></li> <li><a href="/wiki/List_of_AMD_graphics_processing_units" title="List of AMD graphics processing units">AMD</a> <ul><li><a href="/wiki/Radeon" title="Radeon">Radeon</a></li> <li><a href="/wiki/Radeon_Pro" title="Radeon Pro">Radeon Pro</a></li> <li><a href="/wiki/AMD_Instinct" title="AMD Instinct">Instinct</a></li></ul></li> <li><a href="/wiki/Matrox" title="Matrox">Matrox</a></li> <li><a href="/wiki/InfiniteReality" title="InfiniteReality">InfiniteReality</a></li> <li><a href="/wiki/NEC_%C2%B5PD7220" class="mw-redirect" title="NEC µPD7220">NEC µPD7220</a></li> <li><a href="/wiki/Comparison_of_3dfx_graphics_processing_units" class="mw-redirect" title="Comparison of 3dfx graphics processing units">3dfx Voodoo</a></li> <li><a href="/wiki/S3_Graphics" title="S3 Graphics">S3</a></li> <li><a href="/wiki/Glaze3D" title="Glaze3D">Glaze3D</a></li> <li><a href="/wiki/Apple_silicon" title="Apple silicon">Apple silicon</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Adreno" title="Adreno">Adreno</a></li> <li><a href="/wiki/Apple_silicon" title="Apple silicon">Apple silicon</a></li> <li><a href="/wiki/Mali_(GPU)" class="mw-redirect" title="Mali (GPU)">Mali</a></li> <li><a href="/wiki/PowerVR" title="PowerVR">PowerVR</a></li> <li><a href="/wiki/VideoCore" title="VideoCore">VideoCore</a></li> <li><a href="/wiki/Vivante_Corporation" title="Vivante Corporation">Vivante</a></li> <li><a href="/wiki/Imageon" title="Imageon">Imageon</a></li> <li><a href="/wiki/Intel_2700G" title="Intel 2700G">Intel 2700G</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Architecture</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Compute_kernel" title="Compute kernel">Compute kernel</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> <ul><li><a href="/wiki/CMOS" title="CMOS">CMOS</a></li> <li><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a></li></ul></li> <li><a href="/wiki/Graphics_pipeline" title="Graphics pipeline">Graphics pipeline</a> <ul><li><a href="/wiki/Geometry_pipelines" title="Geometry pipelines">Geometry</a></li> <li><a href="/wiki/Vertex_pipeline" title="Vertex pipeline">Vertex</a></li></ul></li> <li><a href="/wiki/High-dynamic-range_rendering" title="High-dynamic-range rendering">HDR rendering</a></li> <li><a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">MAC</a></li> <li><a href="/wiki/Rasterisation" title="Rasterisation">Rasterisation</a> <ul><li><a href="/wiki/Shading" title="Shading">Shading</a></li></ul></li> <li><a href="/wiki/Ray-tracing_hardware" title="Ray-tracing hardware">Ray-tracing</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">SIMT</a></li></ul></li> <li><a href="/wiki/Tessellation_(computer_graphics)" title="Tessellation (computer graphics)">Tessellation</a></li> <li><a href="/wiki/Transform,_clipping,_and_lighting" title="Transform, clipping, and lighting">T&L</a></li> <li><a href="/wiki/Tiled_rendering" title="Tiled rendering">Tiled rendering</a></li> <li><a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shader model</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Blitter" title="Blitter">Blitter</a></li> <li><a href="/wiki/Geometry_processing" title="Geometry processing">Geometry processor</a></li> <li><a href="/wiki/Input%E2%80%93output_memory_management_unit" title="Input–output memory management unit">Input–output memory management unit</a></li> <li><a href="/wiki/Render_output_unit" title="Render output unit">Render output unit</a></li> <li><a href="/wiki/Shader" title="Shader">Shader unit</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream processor</a></li> <li><a href="/wiki/Tensor" title="Tensor">Tensor unit</a></li> <li><a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping unit</a></li> <li><a href="/wiki/Video_display_controller" title="Video display controller">Video display controller</a></li> <li><a href="/wiki/Video_processing_unit" class="mw-redirect" title="Video processing unit">Video processing unit</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Memory</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Direct_memory_access" title="Direct memory access">DMA</a></li> <li><a href="/wiki/Framebuffer" title="Framebuffer">Framebuffer</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a></li> <li><a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a></li> <li><a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a></li> <li><a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a></li> <li><a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a></li> <li><a href="/wiki/GDDR7" class="mw-redirect" title="GDDR7">GDDR7</a></li></ul></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Memory_bandwidth" title="Memory bandwidth">Memory bandwidth</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Memory controller</a></li> <li><a href="/wiki/Shared_graphics_memory" title="Shared graphics memory">Shared graphics memory</a></li> <li><a href="/wiki/Texture_memory" title="Texture memory">Texture memory</a></li> <li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Form factor</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP core</a></li> <li><a href="/wiki/Video_card" class="mw-redirect" title="Video card">Discrete graphics</a> <ul><li><a href="/wiki/GPU_cluster" title="GPU cluster">Clustering</a></li> <li><a href="/wiki/GPU_switching" title="GPU switching">Switching</a></li></ul></li> <li><a href="/wiki/External_GPU" class="mw-redirect" title="External GPU">External graphics</a></li> <li><a href="/wiki/Integrated_graphics" class="mw-redirect" title="Integrated graphics">Integrated graphics</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Performance</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Computer_display_standard" class="mw-redirect" title="Computer display standard">Display resolution</a></li> <li><a href="/wiki/Fillrate" title="Fillrate">Fillrate</a> <ul><li><a href="/wiki/Gigapixel_image" title="Gigapixel image">Pixel/s</a></li> <li><a href="/wiki/Texel_(graphics)" title="Texel (graphics)">Texel/s</a></li></ul></li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">FLOP/s</a></li> <li><a href="/wiki/Frame_rate" title="Frame rate">Frame rate</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a></li> <li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Misc</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/2D_computer_graphics" title="2D computer graphics">2D</a> <ul><li><a href="/wiki/Scrolling" title="Scrolling">Scrolling</a></li> <li><a href="/wiki/Sprite_(computer_graphics)" title="Sprite (computer graphics)">Sprite</a></li> <li><a href="/wiki/Tile-based_video_game" title="Tile-based video game">Tile</a></li></ul></li> <li><a href="/wiki/3D_computer_graphics" title="3D computer graphics">3D</a> <ul><li><a href="/wiki/Global_illumination" title="Global illumination">GI</a></li> <li><a href="/wiki/Texture_mapping" title="Texture mapping">Texture</a></li></ul></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li> <li><a href="/wiki/Graphics_library" title="Graphics library">Graphics library</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li> <li><a href="/wiki/Digital_image_processing" title="Digital image processing">Image processing</a> <ul><li><a href="/wiki/Image_compression" title="Image compression">Compression</a></li></ul></li> <li><a href="/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector processor</a></li> <li><a href="/wiki/Video_coding_format" title="Video coding format">Video coding</a> <ul><li><a href="/wiki/Video_codec" title="Video codec">Codec</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" 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