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<span>Memory modules</span> </div> </a> <ul id="toc-Memory_modules-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Operation" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Operation</span> </div> </a> <button aria-controls="toc-Operation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Operation subsection</span> </button> <ul id="toc-Operation-sublist" class="vector-toc-list"> <li id="toc-Command_encoding" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Command_encoding"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Command encoding</span> </div> </a> <ul id="toc-Command_encoding-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li 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<span>AMD</span> </div> </a> <ul id="toc-AMD-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>External links</span> </div> </a> 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title="DDR5 SDRAM – Czech" lang="cs" hreflang="cs" data-title="DDR5 SDRAM" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/DDR-SDRAM#DDR5-SDRAM" title="DDR-SDRAM – German" lang="de" hreflang="de" data-title="DDR-SDRAM" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Estonian" lang="et" hreflang="et" data-title="DDR5 SDRAM" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Spanish" lang="es" hreflang="es" data-title="DDR5 SDRAM" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – French" lang="fr" hreflang="fr" data-title="DDR5 SDRAM" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Korean" lang="ko" hreflang="ko" data-title="DDR5 SDRAM" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/DDR5" title="DDR5 – Italian" lang="it" hreflang="it" data-title="DDR5" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%A1%E0%B4%BF%E0%B4%A1%E0%B4%BF%E0%B4%86%E0%B5%BC_5_%E0%B4%8E%E0%B4%B8%E0%B5%8D%E0%B4%A1%E0%B4%BF%E0%B4%B1%E0%B4%BE%E0%B4%82" title="ഡിഡിആർ 5 എസ്ഡിറാം – Malayalam" lang="ml" hreflang="ml" data-title="ഡിഡിആർ 5 എസ്ഡിറാം" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Japanese" lang="ja" hreflang="ja" data-title="DDR5 SDRAM" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/DDR5" title="DDR5 – Polish" lang="pl" hreflang="pl" data-title="DDR5" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Portuguese" lang="pt" hreflang="pt" data-title="DDR5 SDRAM" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Russian" lang="ru" hreflang="ru" data-title="DDR5 SDRAM" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/DDR5_SDRAM" title="DDR5 SDRAM – Ukrainian" lang="uk" hreflang="uk" data-title="DDR5 SDRAM" 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</div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Type of computer memory</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">This article is about DDR5 SDRAM. For graphics DDR5, based on DDR3, see <a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5 SDRAM</a>.</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">DDR5 SDRAM<br /><span style="font-size:85%;">Double Data Rate 5 Synchronous Dynamic Random-Access Memory</span></caption><tbody><tr><td colspan="2" class="infobox-subheader">Type of <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a></td></tr><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:DDR5_SDRAM_IMGP6304_smial_wp.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/63/DDR5_SDRAM_IMGP6304_smial_wp.jpg/220px-DDR5_SDRAM_IMGP6304_smial_wp.jpg" decoding="async" width="220" height="147" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/63/DDR5_SDRAM_IMGP6304_smial_wp.jpg/330px-DDR5_SDRAM_IMGP6304_smial_wp.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/63/DDR5_SDRAM_IMGP6304_smial_wp.jpg/440px-DDR5_SDRAM_IMGP6304_smial_wp.jpg 2x" data-file-width="7360" data-file-height="4912" /></a></span><div class="infobox-caption">16 <a href="/wiki/Gigabyte" title="Gigabyte">GB</a><sup id="cite_ref-binpre_1-0" class="reference"><a href="#cite_note-binpre-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> DDR5-4800 1.1 V <a href="/wiki/UDIMM" class="mw-redirect" title="UDIMM">UDIMM</a></div></td></tr><tr><th scope="row" class="infobox-label">Developer</th><td class="infobox-data"><a href="/wiki/JEDEC" title="JEDEC">JEDEC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous dynamic random-access memory</a></td></tr><tr><th scope="row" class="infobox-label">Generation</th><td class="infobox-data">5th generation</td></tr><tr><th scope="row" class="infobox-label">Release date</th><td class="infobox-data">July 14, 2020<span class="noprint">; 4 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2020-07-14</span>)</span><sup id="cite_ref-anandtech-ddr5_2-0" class="reference"><a href="#cite_note-anandtech-ddr5-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Standards</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>DDR5-4000 (PC5-32000)</li><li>DDR5-4400 (PC5-35200)</li><li>DDR5-4800 (PC5-38400)</li><li>DDR5-5200 (PC5-41600)</li><li>DDR5-5600 (PC5-44800)</li><li>DDR5-6000 (PC5-48000)</li><li>DDR5-6200 (PC5-49600)</li><li>DDR5-6400 (PC5-51200)</li><li>DDR5-6800 (PC5-54400)</li><li>DDR5-7200 (PC5-57600)</li><li>DDR5-7600 (PC5-60800)</li><li>DDR5-8000 (PC5-64000)</li><li>DDR5-8400 (PC5-67200)</li><li>DDR5-8800 (PC5-70400)</li></ul></div><sup id="cite_ref-kingston-ddr5_3-0" class="reference"><a href="#cite_note-kingston-ddr5-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-micronsdramcore_4-0" class="reference"><a href="#cite_note-micronsdramcore-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></th><td class="infobox-data">2,000–4,400 MHz</td></tr><tr><th scope="row" class="infobox-label">Cycle time</th><td class="infobox-data">16n bank structure</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Prefetch_buffer" class="mw-redirect" title="Prefetch buffer">Prefetch buffer</a></th><td class="infobox-data">4n</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">Transfer rate</a></th><td class="infobox-data">4–8.8GT/s</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">Bandwidth</a></th><td class="infobox-data">32–64 GB/s<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Voltage" title="Voltage">Voltage</a></th><td class="infobox-data">1.1 V nominal (actual levels are regulated by on-the-module regulators)</td></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a> (2014)</td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/w/index.php?title=DDR6_SDRAM&action=edit&redlink=1" class="new" title="DDR6 SDRAM (page does not exist)">DDR6 SDRAM</a></td></tr></tbody></table> <p><b>Double Data Rate 5 Synchronous Dynamic Random-Access Memory</b> (<b>DDR5 SDRAM</b>) is a type of <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">synchronous dynamic random-access memory</a>. Compared to its predecessor <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>, DDR5 was planned to reduce power consumption, while doubling <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a>.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> The standard, originally targeted for 2018,<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> was released on July 14, 2020.<sup id="cite_ref-anandtech-ddr5_2-1" class="reference"><a href="#cite_note-anandtech-ddr5-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>A new feature called Decision Feedback Equalization (DFE) enables input/output (I/O) speed scalability for higher bandwidth and performance improvement. DDR5 has about the same <a href="/wiki/Memory_timings" title="Memory timings">latency</a> (around 14 <a href="/wiki/Nanosecond" title="Nanosecond">ns</a>) as DDR4 and DDR3.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> DDR5 octuples the maximum DIMM capacity from 64 GB to 512 GB.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-kingston-ddr5_3-1" class="reference"><a href="#cite_note-kingston-ddr5-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> DDR5 also has higher frequencies than DDR4, up to 8GT/s which translates into 64 GB/s (8 gigatransfers/second * 64-bit width / 8 bits/byte = 64 GB/s) of bandwidth per DIMM. </p><p><a href="/wiki/Rambus" title="Rambus">Rambus</a> announced a working DDR5 <a href="/wiki/DIMM" title="DIMM">dual in-line memory module</a> (DIMM) in September 2017.<sup id="cite_ref-pcgamer_10-0" class="reference"><a href="#cite_note-pcgamer-10"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-hexus_11-0" class="reference"><a href="#cite_note-hexus-11"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> On November 15, 2018, <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> announced completion of its first DDR5 RAM chip; running at 5.2 <a href="/wiki/Transfers_per_second" title="Transfers per second">GT/s</a> at 1.1 V.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> In February 2019, SK Hynix announced a 6.4 GT/s chip, the highest speed specified by the preliminary DDR5 standard.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> The first production DDR5 DRAM chip was officially launched by SK Hynix on October 6, 2020.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>The separate <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a> standard <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">Low Power Double Data Rate 5</a> (LPDDR5), intended for laptops and smartphones, was released in February 2019.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p><p>Compared to DDR4, DDR5 further reduces memory voltage to 1.1 <a href="/wiki/Voltage" title="Voltage">V</a>, thus reducing power consumption. DDR5 modules incorporate on-board voltage regulators in order to reach higher speeds.<sup id="cite_ref-hexus_11-1" class="reference"><a href="#cite_note-hexus-11"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Features">Features</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=1" title="Edit section: Features"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Unlike DDR4, all DDR5 chips have on-die <a href="/wiki/Error-correction_code" class="mw-redirect" title="Error-correction code">error-correction code</a>, that detects and corrects errors before sending data to the CPU, to improve reliability and allow denser RAM chips which lowers per-chip defect rate. However, on-die error-correction code is not the same as true <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a> with extra data correction chips on the memory module. There still exists non-ECC and ECC DDR5 DIMM variants; ECC variants have extra data lines to the CPU to send error-detection data, letting the CPU detect and correct errors occurring in transit.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p><p>Each DDR5 <a href="/wiki/DIMM" title="DIMM">DIMM</a> has two independent channels. Earlier DIMM generations featured only a single channel and one CA (Command/Address) bus controlling the whole memory module with its 64 (for non-ECC) or 72 (for ECC) data lines. Both subchannels on a DDR5 DIMM each have their own CA bus, controlling 32 bits for non-ECC memory and either 36 or 40 data lines for ECC memory, resulting in a total number of either 64, 72 or 80 data lines. The reduced bus width is compensated by a doubled minimum burst length of 16, which preserves the minimum access size of 64 bytes, which matches the <a href="/wiki/Cache_line" class="mw-redirect" title="Cache line">cache line</a> size used by modern <a href="/wiki/X86" title="X86">x86</a> microprocessors.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Memory_modules">Memory modules</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=2" title="Edit section: Memory modules"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Multiple DDR5 memory chips can be mounted on a circuit board to form memory modules. For use in personal computers and servers, DDR5 memory is usually supplied in 288-pin dual in-line memory modules, more commonly known as <a href="/wiki/DIMM" title="DIMM">DIMMs</a>. As with previous memory generations, there are multiple DIMM variants available for DDR5. </p><p>Unbuffered memory modules (UDIMMs) directly expose the memory chip interface to the module connector. Registered or load-reduced variants (RDIMMs/LRDIMMs) use additional active circuitry on the memory module in order to buffer the signals between the memory controller and the DRAM chips. This reduces the <a href="/wiki/Capacitance" title="Capacitance">capacitive</a> load on the DDR5 bus. </p><p>DDR5 RDIMMs/LRDIMMs use 12 <a href="/wiki/Voltage" title="Voltage">V</a> and UDIMMs use 5 V input.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> In order to prevent damage by accidental insertion of the wrong memory type, DDR5 UDIMMs and (L)RDIMMs are not mechanically compatible. Additionally, DDR5 DIMMs are supplied with management interface power at 3.3 V,<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> and use on-board circuitry (a <a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">power management integrated circuit</a><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> and associated <a href="/wiki/Passive_component" class="mw-redirect" title="Passive component">passive components</a>) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of <a href="/wiki/Voltage_regulator_module" title="Voltage regulator module">voltage regulator modules</a> for CPU power supplies. </p> <div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=3" title="Edit section: Operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Standard DDR5 memory speeds range from 4,000 to 6,400 million transfers per second (PC5-32000 to PC5-51200).<sup id="cite_ref-kingston-ddr5_3-2" class="reference"><a href="#cite_note-kingston-ddr5-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Higher speeds may be added later, as happened with previous generations. </p><p>Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after eight transfers. The addressing range is also slightly extended as follows: </p> <ul><li>The number of chip ID bits remains at three bits, allowing up to eight stacked chips (3 → 3).</li> <li>A third bank group bit (BG2) was added, allowing up to eight bank groups (2 → 3).</li> <li>The maximum number of banks per bank group remains at four (2 → 2),</li> <li>The number of row address bits remains at 17, for a maximum of 128K rows (17 → 17).</li> <li>One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips (11 → 12).</li> <li>The least-significant three column-address bits (C0, C1, C2) are <i>removed</i>. All reads and writes must begin at a column address which is a multiple of 8 (3 → 0). This is necessary due to the internal ECC.</li> <li>One bit is reserved for addressing expansion as <i>either</i> a fourth chip ID bit (CID3) <i>or</i> an additional row address bit (R17) (0 → 1).</li></ul> <div class="mw-heading mw-heading3"><h3 id="Command_encoding">Command encoding</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=4" title="Edit section: Command encoding"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable plainrowheaders" style="text-align: center; font-size: 95%;"> <caption>DDR5 command encoding<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-micronsdramcore_4-1" class="reference"><a href="#cite_note-micronsdramcore-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th rowspan="2">Command</th> <th rowspan="2"><span style="text-decoration:overline;">CS</span></th> <th colspan="14">Command/address (CA) bits </th></tr> <tr> <th>0</th> <th>1</th> <th>2</th> <th>3</th> <th>4</th> <th>5</th> <th>6</th> <th>7</th> <th>8</th> <th>9</th> <th>10</th> <th>11</th> <th>12</th> <th>13 </th></tr> <tr> <td style="text-align:left;" rowspan="2">Activate <br />(Open a row) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="4">Row R0–3</td> <td colspan="2">Bank</td> <td colspan="3">Bank group</td> <td colspan="3">Chip CID0–2 </td></tr> <tr style="line-height:100%"> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="13">Row R4–16</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">R17/<br />CID3 </td></tr> <tr> <td style="text-align:left; background: #ececec; color: #2C2C2C;" rowspan="2"><i>reserved</i> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Reserved </td></tr> <tr> <td style="text-align:left; background: #ececec; color: #2C2C2C;" rowspan="2"><i>reserved for future use</i> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;" rowspan="2">Write pattern </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="2">Bank</td> <td colspan="3">Bank group</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td colspan="8">Column C3–10</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td><span style="text-decoration:overline;">AP</span></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3 </td></tr> <tr> <td style="text-align:left; background: #ececec; color: #2C2C2C;" rowspan="2"><i>reserved for future use</i> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;" rowspan="2">Mode register write </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="8">Address MRA0–7</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="8">Opcode OP0-7</td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>CW</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;" rowspan="2">Mode register read </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="8">Address MRA0–7</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td>CW</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;" rowspan="2">Write </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td><span style="text-decoration:overline;">BL</span></td> <td colspan="2">Bank</td> <td colspan="3">Bank group</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td colspan="8">Column C3–10</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td><span style="text-decoration:overline;">AP</span></td> <td><span style="text-decoration:overline;">WRP</span></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3 </td></tr> <tr> <td style="text-align:left;" rowspan="2">Read </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td><span style="text-decoration:overline;">BL</span></td> <td colspan="2">Bank</td> <td colspan="3">Bank group</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td colspan="8">Column C3–10</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td><span style="text-decoration:overline;">AP</span></td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3 </td></tr> <tr> <td style="text-align:left;">Vref CA </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="7">Opcode OP0-6</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Vref CS </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="7">Opcode OP0-6</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Refresh all </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Refresh management all </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td colspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Refresh same bank </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="2">Bank</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td colspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Refresh management same bank </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="2">Bank</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Precharge all </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Precharge same bank </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="2">Bank</td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left;">Precharge </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">CID3</td> <td colspan="2">Bank</td> <td colspan="3">Bank group</td> <td colspan="3">Chip CID0–2 </td></tr> <tr> <td style="text-align:left; background: #ececec; color: #2C2C2C;"><i>reserved for future use</i> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Self-refresh entry </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Power-down entry </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td><span style="text-decoration:overline;">ODT</span></td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Multi-purpose command </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td colspan="8">Opcode OP0–7</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Power-down exit; No operation </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">L</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">V </td></tr> <tr> <td style="text-align:left;">Deselect (no operation) </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">H</td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">X </td></tr> <tr> <td colspan="16" style="background-color:#FFF;"><small><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}</style><div class="hlist"> <ul><li>Signal level <ul><li>H, high</li> <li>L, low</li> <li>V, valid, either low or high</li> <li>X, irrelevant</li></ul></li> <li>Logic level <ul><li><style data-mw-deduplicate="TemplateStyles:r981673959">.mw-parser-output .legend{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .legend-color{display:inline-block;min-width:1.25em;height:1.25em;line-height:1.25;margin:1px 0;text-align:center;border:1px solid black;background-color:transparent;color:black}.mw-parser-output .legend-text{}</style><span class="legend-color mw-no-invert" style="background-color:#9f9; color:black;"> </span> Active</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r981673959"><span class="legend-color mw-no-invert" style="background-color:#f99; color:black;"> </span> Inactive</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r981673959"><span class="legend-color mw-no-invert" style="background-color:#ececec; color:black;"> </span> Unused</li></ul></li></ul> </div><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><div class="hlist"> <ul><li>Control bits <ul><li><span style="text-decoration:overline;">AP</span>, Auto-precharge</li> <li>CW, Control word</li> <li><span style="text-decoration:overline;">BL</span>, Burst length ≠ 16</li> <li><span style="text-decoration:overline;">WRP</span>, Write partial</li> <li><span style="text-decoration:overline;">ODT</span>, <a href="/wiki/On-die_termination" title="On-die termination">ODT</a> remains enabled</li></ul></li></ul> </div></small> </td></tr></tbody></table> <p>The command encoding was significantly rearranged and takes inspiration from that of <a href="/wiki/LPDDR#LPDDR4" title="LPDDR">LPDDR4</a>; commands are sent using either one or two cycles with 14-bit bus. Some simple commands (e.g. precharge) take one cycle, while any that include an address (activate, read, write) use two cycles to include 28 bits of information. </p><p>Also like LPDDR, there are now 256 8-bit mode registers, rather than eight 13-bit mode registers. Also, rather than one register (MR7) being reserved for use by the registered clock driver chip, a complete second bank of mode registers is defined (selected using the CW bit). </p><p>The "Write Pattern" command is new for DDR5; this is identical to a write command, but the range is filled in with copies of a one-byte mode register (which defaults to all-zero) instead of individual data. Although this normally takes the same amount of time as a normal write, not driving the data lines saves energy. Also, writes to multiple banks may be interleaved more closely as the command bus is freed earlier. </p><p>The multi-purpose command includes various sub-commands for training and calibration of the data bus. </p> <div class="mw-heading mw-heading2"><h2 id="Support">Support</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=5" title="Edit section: Support"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Intel">Intel</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=6" title="Edit section: Intel"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The 12th generation <a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a>, 13th generation <a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake</a>, as well as 14th generation <a href="/wiki/Raptor_Lake_Refresh" class="mw-redirect" title="Raptor Lake Refresh">Raptor Lake Refresh</a> CPUs support both DDR5 and DDR4 but, usually, there are only DIMM sockets for either one or the other on a motherboard. Some mainboards with Intel's H610 chipset support both DDR4 and DDR5, but not simultaneously.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Sapphire_Rapids" title="Sapphire Rapids">Sapphire Rapids</a> server CPUs, Core Ultra Series 1 <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> mobile CPUs, and the latest Core Ultra Series 2 <a href="/wiki/Arrow_Lake_(microprocessor)" title="Arrow Lake (microprocessor)">Arrow Lake</a> desktop CPUs all exclusively support DDR5. </p> <div class="mw-heading mw-heading3"><h3 id="AMD">AMD</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=7" title="Edit section: AMD"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>DDR5 and <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a> are supported by the <a href="/wiki/Ryzen_6000" class="mw-redirect" title="Ryzen 6000">Ryzen 6000</a> series mobile APUs, powered by their <a href="/wiki/Zen_3%2B" class="mw-redirect" title="Zen 3+">Zen 3+</a> architecture. <a href="/wiki/Ryzen_7000" class="mw-redirect" title="Ryzen 7000">Ryzen 7000</a> and <a href="/wiki/Ryzen_9000" class="mw-redirect" title="Ryzen 9000">Ryzen 9000</a> series desktop processors also support DDR5 memory as standard.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Epyc" title="Epyc">Epyc</a> fourth-generation <i>Genoa</i> and <i>Bergamo</i> server CPUs have support for 12-channel DDR5 on the <a href="/wiki/Socket_SP5" title="Socket SP5">SP5</a> socket.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <div style="clear:right;" class=""></div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=8" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text">64 GB/s assumes 8 GT/s, each with 64 bits of bus width, then divided by 8 to convert from bits to bytes</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=9" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-binpre-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-binpre_1-0">^</a></b></span> <span class="reference-text">Here, <i>K</i>, <i>M</i>, <i>G</i>, or <i>T</i> refer to the <a href="/wiki/Binary_prefix" title="Binary prefix">binary prefixes</a> based on powers of 1024.</span> </li> <li id="cite_note-anandtech-ddr5-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-anandtech-ddr5_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-anandtech-ddr5_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFSmith2020" class="citation web cs1">Smith, Ryan (July 14, 2020). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond">"DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond"</a>. <i>AnandTech</i><span class="reference-accessdate">. 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Archived from <a rel="nofollow" class="external text" href="https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/modules/unbuffered_dimm/ddr5/ddr5_udimm_core.pdf?rev=fdbd9476506c4e019360a5e402827caa">the original</a> <span class="cs1-format">(PDF)</span> on December 25, 2023. <q>Voltage (external supply, nominal) / VIN_Bulk: 5V / Bulk input DC supply voltage from system</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DDR5+SDRAM+UDIMM+Core%3A+Product+Description&rft.pages=1&rft.pub=Micron+Technology%2C+Inc.&rft_id=https%3A%2F%2Fmedia-www.micron.com%2F-%2Fmedia%2Fclient%2Fglobal%2Fdocuments%2Fproducts%2Fdata-sheet%2Fmodules%2Funbuffered_dimm%2Fddr5%2Fddr5_udimm_core.pdf%3Frev%3Dfdbd9476506c4e019360a5e402827caa&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.idt.com/us/en/products/power-management/power-management-ics-pmic-and-pmus/p8900-pmic-ddr5-rdimms-and-lrdimms">"P8900 PMIC for DDR5 RDIMMs and LRDIMMs"</a>. <a href="/wiki/Renesas" class="mw-redirect" title="Renesas">Renesas</a><span class="reference-accessdate">. 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Retrieved <span class="nowrap">July 19,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=P8911+PMIC+for+Client+DDR5+Memory+Modules&rft.pub=Renesas&rft_id=https%3A%2F%2Fwww.idt.com%2Fus%2Fen%2Fproducts%2Fpower-management%2Fpower-management-ics-pmic-and-pmus%2Fp8911-pmic-client-ddr5-memory-modules&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20211029163115/https://mis-prod-koce-producthomepage-cdn-01-blob-ep.azureedge.net/web/TR-20210526195932644.pdf">"DDR5 SDRAM RDIMM Based on 16Gb M-die"</a> <span class="cs1-format">(PDF)</span>. <i>SK Hynix</i>. p. 7. Archived from <a rel="nofollow" class="external text" href="https://mis-prod-koce-producthomepage-cdn-01-blob-ep.azureedge.net/web/TR-20210526195932644.pdf">the original</a> <span class="cs1-format">(PDF)</span> on October 29, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">October 29,</span> 2021</span>. <q>VIN_BULK[:] 12 V power input supply pin to the PMIC. VIN_MGMT[:] 3.3 V power input supply pin to the PMIC for VOUT_1.8V & VOUT_1.0V LDO output, side band management access, internal memory read operation.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=SK+Hynix&rft.atitle=DDR5+SDRAM+RDIMM+Based+on+16Gb+M-die&rft.pages=7&rft_id=https%3A%2F%2Fmis-prod-koce-producthomepage-cdn-01-blob-ep.azureedge.net%2Fweb%2FTR-20210526195932644.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1041539562">.mw-parser-output .citation{word-wrap:break-word}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}</style><span class="citation patent" id="CITEREFPatel,_Shwetal_ArvindZhang,_AndyMeng,_Wen_JieChenxiao_Ren,_Alejandro_F.Gonzalez2019"><a rel="nofollow" class="external text" href="https://worldwide.espacenet.com/textdoc?DB=EPODOC&IDX=US10769082">US patent 10769082</a>, Patel, Shwetal Arvind; Zhang, Andy & Meng, Wen Jie et al., "DDR5 PMIC Interface Protocol and Operation", published 2019-11-07,  assigned to <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">Integrated Device Technology</a>, Inc.</span><span class="Z3988" title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.number=10769082&rft.cc=US&rft.title=DDR5+PMIC+Interface+Protocol+and+Operation&rft.inventor=Patel%2C+Shwetal+Arvind&rft.assignee=%5B%5BIntegrated+Device+Technology%5D%5D%2C+Inc.&rft.appldate=2018-05-01&rft.pubdate=2019-11-07&rft.prioritydate=2018-05-01"><span style="display: none;"> </span></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.jedec.org/standards-documents/docs/jesd79-5">"JEDEC DDR5 SDRAM Specification"</a>. JEDEC committee JC42.3<span class="reference-accessdate">. Retrieved <span class="nowrap">May 15,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=JEDEC+DDR5+SDRAM+Specification&rft.pub=JEDEC+committee+JC42.3&rft_id=https%3A%2F%2Fwww.jedec.org%2Fstandards-documents%2Fdocs%2Fjesd79-5&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.computerbase.de/2022-03/intel-h610-ddr4-ddr5-speicher/">"DDR4 und DDR5: H610-Mainboard kombiniert beide Speicher-Generationen"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=DDR4+und+DDR5%3A+H610-Mainboard+kombiniert+beide+Speicher-Generationen&rft_id=https%3A%2F%2Fwww.computerbase.de%2F2022-03%2Fintel-h610-ddr4-ddr5-speicher%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCopeman2023" class="citation web cs1">Copeman, Anyron (June 15, 2023). <a rel="nofollow" class="external text" href="https://www.techadvisor.com/article/743561/amd-ryzen-7000-series-everything-we-know-so-far.html">"Everything you need to know about the AMD Ryzen 7000 Series"</a>. <i>Tech Advisor</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230617083049/https://www.techadvisor.com/article/743561/amd-ryzen-7000-series-everything-we-know-so-far.html">Archived</a> from the original on June 17, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">June 28,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tech+Advisor&rft.atitle=Everything+you+need+to+know+about+the+AMD+Ryzen+7000+Series&rft.date=2023-06-15&rft.aulast=Copeman&rft.aufirst=Anyron&rft_id=https%3A%2F%2Fwww.techadvisor.com%2Farticle%2F743561%2Famd-ryzen-7000-series-everything-we-know-so-far.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGoetting2022" class="citation web cs1">Goetting, Chris (November 10, 2022). <a rel="nofollow" class="external text" href="https://hothardware.com/reviews/amd-genoa-data-center-cpu-launch">"AMD 4th Gen EPYC 9004 Series Launched: Genoa Tested In A Data Center Benchmark Gauntlet"</a>. <i>HotHardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">June 28,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HotHardware&rft.atitle=AMD+4th+Gen+EPYC+9004+Series+Launched%3A+Genoa+Tested+In+A+Data+Center+Benchmark+Gauntlet&rft.date=2022-11-10&rft.aulast=Goetting&rft.aufirst=Chris&rft_id=https%3A%2F%2Fhothardware.com%2Freviews%2Famd-genoa-data-center-cpu-launch&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGoetting2023" class="citation web cs1">Goetting, Chris (June 13, 2023). <a rel="nofollow" class="external text" href="https://hothardware.com/news/amd-epyc-bergamo-genoa-x-instinct-mi300x">"AMD Unleashes EPYC Bergamo And Genoa-X Data Center CPUs, AI-Ready Instinct MI300X GPUs"</a>. <i>HotHardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">June 28,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HotHardware&rft.atitle=AMD+Unleashes+EPYC+Bergamo+And+Genoa-X+Data+Center+CPUs%2C+AI-Ready+Instinct+MI300X+GPUs&rft.date=2023-06-13&rft.aulast=Goetting&rft.aufirst=Chris&rft_id=https%3A%2F%2Fhothardware.com%2Fnews%2Famd-epyc-bergamo-genoa-x-instinct-mi300x&rfr_id=info%3Asid%2Fen.wikipedia.org%3ADDR5+SDRAM" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=DDR5_SDRAM&action=edit&section=10" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" 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.navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:DRAM" title="Template:DRAM"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:DRAM" title="Template talk:DRAM"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:DRAM" title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)" style="font-size:114%;margin:0 4em"><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a></li> <li><a class="mw-selflink selflink">DDR5</a></li></ul></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li> <li><a href="/wiki/Synchronous_dynamic_random-access_memory#Timeline" title="Synchronous dynamic random-access memory">SDRAM timeline</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Dynamic_random-access_memory" title="List of interface bit rates">Bandwidth</a></li> <li><a href="/wiki/Transistor_count#Memory" title="Transistor count">Transistor count</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=DDR5_SDRAM&oldid=1256348112">https://en.wikipedia.org/w/index.php?title=DDR5_SDRAM&oldid=1256348112</a>"</div></div> <div id="catlinks" class="catlinks" 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