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class="vector-dropdown " title="Change the appearance of the page's font size, width, and color" > <input type="checkbox" id="vector-appearance-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-appearance-dropdown" class="vector-dropdown-checkbox " aria-label="Appearance" > <label id="vector-appearance-dropdown-label" for="vector-appearance-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-appearance mw-ui-icon-wikimedia-appearance"></span> <span class="vector-dropdown-label-text">Appearance</span> </label> <div class="vector-dropdown-content"> <div id="vector-appearance-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <div id="p-vector-user-menu-notifications" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <div id="p-vector-user-menu-overflow" class="vector-menu mw-portlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-sitesupport-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="https://donate.wikimedia.org/wiki/Special:FundraiserRedirector?utm_source=donate&utm_medium=sidebar&utm_campaign=C13_en.wikipedia.org&uselang=en" class=""><span>Donate</span></a> </li> <li id="pt-createaccount-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="/w/index.php?title=Special:CreateAccount&returnto=CPU+cache" title="You are encouraged to create an account and log in; however, it is not mandatory" class=""><span>Create account</span></a> </li> <li id="pt-login-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" 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[o]" accesskey="o"><span class="vector-icon mw-ui-icon-logIn mw-ui-icon-wikimedia-logIn"></span> <span>Log in</span></a></li> </ul> </div> </div> <div id="p-user-menu-anon-editor" class="vector-menu mw-portlet mw-portlet-user-menu-anon-editor" > <div class="vector-menu-heading"> Pages for logged out editors <a href="/wiki/Help:Introduction" aria-label="Learn more about editing"><span>learn more</span></a> </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-anoncontribs" class="mw-list-item"><a href="/wiki/Special:MyContributions" title="A list of edits made from this IP address [y]" accesskey="y"><span>Contributions</span></a></li><li id="pt-anontalk" class="mw-list-item"><a href="/wiki/Special:MyTalk" title="Discussion about edits from this IP address [n]" accesskey="n"><span>Talk</span></a></li> </ul> </div> </div> </div> </div> </nav> </div> </header> </div> <div class="mw-page-container"> <div class="mw-page-container-inner"> <div class="vector-sitenotice-container"> <div id="siteNotice"></div> </div> <div class="vector-column-start"> <div class="vector-main-menu-container"> <div id="mw-navigation"> <nav id="mw-panel" class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-pinned-container" class="vector-pinned-container"> </div> </nav> </div> </div> <div class="vector-sticky-pinned-container"> <nav id="mw-panel-toc" aria-label="Contents" data-event-name="ui.sidebar-toc" class="mw-table-of-contents-container vector-toc-landmark"> <div id="vector-toc-pinned-container" class="vector-pinned-container"> <div id="vector-toc" class="vector-toc vector-pinnable-element"> <div class="vector-pinnable-header vector-toc-pinnable-header vector-pinnable-header-pinned" data-feature-name="toc-pinned" data-pinnable-element-id="vector-toc" > <h2 class="vector-pinnable-header-label">Contents</h2> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-Overview" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Overview"> <div class="vector-toc-text"> <span class="vector-toc-numb">1</span> <span>Overview</span> </div> </a> <ul id="toc-Overview-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-History" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#History"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>History</span> </div> </a> <ul id="toc-History-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Operation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Operation</span> </div> </a> <button aria-controls="toc-Operation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Operation subsection</span> </button> <ul id="toc-Operation-sublist" class="vector-toc-list"> <li id="toc-Cache_entries" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Cache_entries"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Cache entries</span> </div> </a> <ul id="toc-Cache_entries-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Policies" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Policies"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Policies</span> </div> </a> <ul id="toc-Policies-sublist" class="vector-toc-list"> <li id="toc-Replacement_policies" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Replacement_policies"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.1</span> <span>Replacement policies</span> </div> </a> <ul id="toc-Replacement_policies-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Write_policies" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Write_policies"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2.2</span> <span>Write policies</span> </div> </a> <ul id="toc-Write_policies-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cache_performance" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Cache_performance"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Cache performance</span> </div> </a> <ul id="toc-Cache_performance-sublist" class="vector-toc-list"> <li id="toc-CPU_stalls" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#CPU_stalls"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.1</span> <span>CPU stalls</span> </div> </a> <ul id="toc-CPU_stalls-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Associativity" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Associativity"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Associativity</span> </div> </a> <button aria-controls="toc-Associativity-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Associativity subsection</span> </button> <ul id="toc-Associativity-sublist" class="vector-toc-list"> <li id="toc-Direct-mapped_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Direct-mapped_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Direct-mapped cache</span> </div> </a> <ul id="toc-Direct-mapped_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Two-way_set_associative_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Two-way_set_associative_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.2</span> <span>Two-way set associative cache</span> </div> </a> <ul id="toc-Two-way_set_associative_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Speculative_execution" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Speculative_execution"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.3</span> <span>Speculative execution</span> </div> </a> <ul id="toc-Speculative_execution-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Two-way_skewed_associative_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Two-way_skewed_associative_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.4</span> <span>Two-way skewed associative cache</span> </div> </a> <ul id="toc-Two-way_skewed_associative_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Pseudo-associative_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Pseudo-associative_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.5</span> <span>Pseudo-associative cache</span> </div> </a> <ul id="toc-Pseudo-associative_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multicolumn_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Multicolumn_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.6</span> <span>Multicolumn cache</span> </div> </a> <ul id="toc-Multicolumn_cache-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cache_entry_structure" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cache_entry_structure"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Cache entry structure</span> </div> </a> <button aria-controls="toc-Cache_entry_structure-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cache entry structure subsection</span> </button> <ul id="toc-Cache_entry_structure-sublist" class="vector-toc-list"> <li id="toc-Example" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Example"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>Example</span> </div> </a> <ul id="toc-Example-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Flag_bits" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Flag_bits"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.2</span> <span>Flag bits</span> </div> </a> <ul id="toc-Flag_bits-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cache_miss" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cache_miss"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Cache miss</span> </div> </a> <ul id="toc-Cache_miss-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Address_translation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Address_translation"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Address translation</span> </div> </a> <button aria-controls="toc-Address_translation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Address translation subsection</span> </button> <ul id="toc-Address_translation-sublist" class="vector-toc-list"> <li id="toc-Homonym_and_synonym_problems" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Homonym_and_synonym_problems"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>Homonym and synonym problems</span> </div> </a> <ul id="toc-Homonym_and_synonym_problems-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Virtual_tags_and_vhints" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Virtual_tags_and_vhints"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.2</span> <span>Virtual tags and vhints</span> </div> </a> <ul id="toc-Virtual_tags_and_vhints-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Page_coloring" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Page_coloring"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.3</span> <span>Page coloring</span> </div> </a> <ul id="toc-Page_coloring-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cache_hierarchy_in_a_modern_processor" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cache_hierarchy_in_a_modern_processor"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Cache hierarchy in a modern processor</span> </div> </a> <button aria-controls="toc-Cache_hierarchy_in_a_modern_processor-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cache hierarchy in a modern processor subsection</span> </button> <ul id="toc-Cache_hierarchy_in_a_modern_processor-sublist" class="vector-toc-list"> <li id="toc-Specialized_caches" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Specialized_caches"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Specialized caches</span> </div> </a> <ul id="toc-Specialized_caches-sublist" class="vector-toc-list"> <li id="toc-Victim_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Victim_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.1</span> <span>Victim cache</span> </div> </a> <ul id="toc-Victim_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Trace_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Trace_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.2</span> <span>Trace cache</span> </div> </a> <ul id="toc-Trace_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Write_Coalescing_Cache_(WCC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Write_Coalescing_Cache_(WCC)"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.3</span> <span>Write Coalescing Cache (WCC)</span> </div> </a> <ul id="toc-Write_Coalescing_Cache_(WCC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Micro-operation_(μop_or_uop)_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Micro-operation_(μop_or_uop)_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.4</span> <span>Micro-operation (μop or uop) cache</span> </div> </a> <ul id="toc-Micro-operation_(μop_or_uop)_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Branch_target_instruction_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Branch_target_instruction_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.5</span> <span>Branch target instruction cache</span> </div> </a> <ul id="toc-Branch_target_instruction_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Smart_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Smart_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1.6</span> <span>Smart cache</span> </div> </a> <ul id="toc-Smart_cache-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Multi-level_caches" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Multi-level_caches"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2</span> <span>Multi-level caches</span> </div> </a> <ul id="toc-Multi-level_caches-sublist" class="vector-toc-list"> <li id="toc-Multi-core_chips" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Multi-core_chips"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.1</span> <span>Multi-core chips</span> </div> </a> <ul id="toc-Multi-core_chips-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Separate_versus_unified" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Separate_versus_unified"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.2</span> <span>Separate versus unified</span> </div> </a> <ul id="toc-Separate_versus_unified-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Exclusive_versus_inclusive" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Exclusive_versus_inclusive"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.2.3</span> <span>Exclusive versus inclusive</span> </div> </a> <ul id="toc-Exclusive_versus_inclusive-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Scratchpad_memory" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Scratchpad_memory"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.3</span> <span>Scratchpad memory</span> </div> </a> <ul id="toc-Scratchpad_memory-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Example:_the_K8" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Example:_the_K8"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.4</span> <span>Example: the K8</span> </div> </a> <ul id="toc-Example:_the_K8-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-More_hierarchies" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#More_hierarchies"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.5</span> <span>More hierarchies</span> </div> </a> <ul id="toc-More_hierarchies-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Tag_RAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Tag_RAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.6</span> <span>Tag RAM</span> </div> </a> <ul id="toc-Tag_RAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Implementation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Implementation"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Implementation</span> </div> </a> <button aria-controls="toc-Implementation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Implementation subsection</span> </button> <ul id="toc-Implementation-sublist" class="vector-toc-list"> <li id="toc-History_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#History_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1</span> <span>History</span> </div> </a> <ul id="toc-History_2-sublist" class="vector-toc-list"> <li id="toc-First_TLB_implementations" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#First_TLB_implementations"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.1</span> <span>First TLB implementations</span> </div> </a> <ul id="toc-First_TLB_implementations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-First_instruction_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#First_instruction_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.2</span> <span>First instruction cache</span> </div> </a> <ul id="toc-First_instruction_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-First_data_cache" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#First_data_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.3</span> <span>First data cache</span> </div> </a> <ul id="toc-First_data_cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-In_68k_microprocessors" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#In_68k_microprocessors"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.4</span> <span>In 68k microprocessors</span> </div> </a> <ul id="toc-In_68k_microprocessors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-In_x86_microprocessors" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#In_x86_microprocessors"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.5</span> <span>In x86 microprocessors</span> </div> </a> <ul id="toc-In_x86_microprocessors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-In_ARM_microprocessors" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#In_ARM_microprocessors"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.6</span> <span>In ARM microprocessors</span> </div> </a> <ul id="toc-In_ARM_microprocessors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Current_research" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Current_research"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1.7</span> <span>Current research</span> </div> </a> <ul id="toc-Current_research-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Multi-ported_cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Multi-ported_cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.2</span> <span>Multi-ported cache</span> </div> </a> <ul id="toc-Multi-ported_cache-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav 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class="firstHeading mw-first-heading"><span class="mw-page-title-main">CPU cache</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 30 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-30" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">30 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B0%D8%A7%D9%83%D8%B1%D8%A9_%D9%88%D8%AD%D8%AF%D8%A9_%D8%A7%D9%84%D9%85%D8%B9%D8%A7%D9%84%D8%AC%D8%A9_%D8%A7%D9%84%D9%85%D8%B1%D9%83%D8%B2%D9%8A%D8%A9" title="ذاكرة وحدة المعالجة المركزية – Arabic" lang="ar" hreflang="ar" data-title="ذاكرة وحدة المعالجة المركزية" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bh mw-list-item"><a href="https://bh.wikipedia.org/wiki/%E0%A4%95%E0%A5%88%E0%A4%B6_%E0%A4%AE%E0%A5%87%E0%A4%AE%E0%A5%8B%E0%A4%B0%E0%A5%80" title="कैश मेमोरी – Bhojpuri" lang="bh" hreflang="bh" data-title="कैश मेमोरी" data-language-autonym="भोजपुरी" data-language-local-name="Bhojpuri" class="interlanguage-link-target"><span>भोजपुरी</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%9F%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80%D0%B5%D0%BD_%D0%BA%D0%B5%D1%88" title="Процесорен кеш – Bulgarian" lang="bg" hreflang="bg" data-title="Процесорен кеш" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Mem%C3%B2ria_cau_de_la_CPU" title="Memòria cau de la CPU – Catalan" lang="ca" hreflang="ca" data-title="Memòria cau de la CPU" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Befehlscache" title="Befehlscache – German" lang="de" hreflang="de" data-title="Befehlscache" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Protsessori_vahem%C3%A4lu" title="Protsessori vahemälu – Estonian" lang="et" hreflang="et" data-title="Protsessori vahemälu" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Cach%C3%A9_de_CPU" title="Caché de CPU – Spanish" lang="es" hreflang="es" data-title="Caché de CPU" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%AD%D8%A7%D9%81%D8%B8%D9%87_%D9%86%D9%87%D8%A7%D9%86_%D8%B3%DB%8C%E2%80%8C%D9%BE%DB%8C%E2%80%8C%DB%8C%D9%88" title="حافظه نهان سی‌پی‌یو – Persian" lang="fa" hreflang="fa" data-title="حافظه نهان سی‌پی‌یو" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Cache_de_processeur" title="Cache de processeur – French" lang="fr" hreflang="fr" data-title="Cache de processeur" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ga mw-list-item"><a href="https://ga.wikipedia.org/wiki/Taisc-chuimhne" title="Taisc-chuimhne – Irish" lang="ga" hreflang="ga" data-title="Taisc-chuimhne" data-language-autonym="Gaeilge" data-language-local-name="Irish" class="interlanguage-link-target"><span>Gaeilge</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/CPU_%EC%BA%90%EC%8B%9C" title="CPU 캐시 – Korean" lang="ko" hreflang="ko" data-title="CPU 캐시" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Tembolok_CPU" title="Tembolok CPU – Indonesian" lang="id" hreflang="id" data-title="Tembolok CPU" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/CPU_cache" title="CPU cache – Italian" lang="it" hreflang="it" data-title="CPU cache" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/Procesora_ke%C5%A1atmi%C5%86a" title="Procesora kešatmiņa – Latvian" lang="lv" hreflang="lv" data-title="Procesora kešatmiņa" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target"><span>Latviešu</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/Procesoriaus_spartinan%C4%8Dioji_atmintin%C4%97" title="Procesoriaus spartinančioji atmintinė – Lithuanian" lang="lt" hreflang="lt" data-title="Procesoriaus spartinančioji atmintinė" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/%D0%9E%D0%B1%D1%80%D0%B0%D0%B1%D0%BE%D1%82%D1%83%D0%B2%D0%B0%D1%87%D0%BA%D0%B8_%D0%BC%D0%B5%D1%93%D1%83%D1%81%D0%BA%D0%BB%D0%B0%D0%B4" title="Обработувачки меѓусклад – Macedonian" lang="mk" hreflang="mk" data-title="Обработувачки меѓусклад" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target"><span>Македонски</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%B8%E0%B4%BF.%E0%B4%AA%E0%B4%BF.%E0%B4%AF%E0%B5%81._%E0%B4%95%E0%B4%BE%E0%B4%B7%E0%B5%8D" title="സി.പി.യു. കാഷ് – Malayalam" lang="ml" hreflang="ml" data-title="സി.പി.യു. കാഷ്" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/CPU-cache" title="CPU-cache – Dutch" lang="nl" hreflang="nl" data-title="CPU-cache" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%82%AD%E3%83%A3%E3%83%83%E3%82%B7%E3%83%A5%E3%83%A1%E3%83%A2%E3%83%AA" title="キャッシュメモリ – Japanese" lang="ja" hreflang="ja" data-title="キャッシュメモリ" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Hurtigminne" title="Hurtigminne – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Hurtigminne" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Pami%C4%99%C4%87_podr%C4%99czna_procesora" title="Pamięć podręczna procesora – Polish" lang="pl" hreflang="pl" data-title="Pamięć podręczna procesora" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Cache_do_processador" title="Cache do processador – Portuguese" lang="pt" hreflang="pt" data-title="Cache do processador" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%9A%D1%8D%D1%88_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80%D0%B0" title="Кэш процессора – Russian" lang="ru" hreflang="ru" data-title="Кэш процессора" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/R%C3%BDchla_vyrovn%C3%A1vacia_pam%C3%A4%C5%A5_procesora" title="Rýchla vyrovnávacia pamäť procesora – Slovak" lang="sk" hreflang="sk" data-title="Rýchla vyrovnávacia pamäť procesora" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%9A%D0%B5%D1%88_%D1%86%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D0%BD%D0%B5_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80%D1%81%D0%BA%D0%B5_%D1%98%D0%B5%D0%B4%D0%B8%D0%BD%D0%B8%D1%86%D0%B5" title="Кеш централне процесорске јединице – Serbian" lang="sr" hreflang="sr" data-title="Кеш централне процесорске јединице" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-ta mw-list-item"><a href="https://ta.wikipedia.org/wiki/%E0%AE%AA%E0%AE%A4%E0%AF%81%E0%AE%95%E0%AF%8D%E0%AE%95%E0%AF%81_%E0%AE%A8%E0%AE%BF%E0%AE%A9%E0%AF%88%E0%AE%B5%E0%AE%95%E0%AE%AE%E0%AF%8D" title="பதுக்கு நினைவகம் – Tamil" lang="ta" hreflang="ta" data-title="பதுக்கு நினைவகம்" data-language-autonym="தமிழ்" data-language-local-name="Tamil" class="interlanguage-link-target"><span>தமிழ்</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/%C4%B0%C5%9Flemci_%C3%B6nbelle%C4%9Fi" title="İşlemci önbelleği – Turkish" lang="tr" hreflang="tr" data-title="İşlemci önbelleği" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%9A%D0%B5%D1%88_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80%D0%B0" title="Кеш процесора – Ukrainian" lang="uk" hreflang="uk" data-title="Кеш процесора" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/CPU_cache" title="CPU cache – Vietnamese" lang="vi" hreflang="vi" data-title="CPU cache" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/CPU%E7%BC%93%E5%AD%98" title="CPU缓存 – Chinese" lang="zh" hreflang="zh" data-title="CPU缓存" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q352090#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Hardware cache of a central processing unit</div> <p>A <b>CPU cache</b> is a <a href="/wiki/Hardware_cache" class="mw-redirect" title="Hardware cache">hardware cache</a> used by the <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU) of a <a href="/wiki/Computer" title="Computer">computer</a> to reduce the average cost (time or energy) to access <a href="/wiki/Data_(computer_science)" title="Data (computer science)">data</a> from the <a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> A cache is a smaller, faster memory, located closer to a <a href="/wiki/Processor_core" class="mw-redirect" title="Processor core">processor core</a>, which stores copies of the data from frequently used main <a href="/wiki/Memory_location" class="mw-redirect" title="Memory location">memory locations</a>. Most CPUs have a hierarchy of multiple cache <a href="#MULTILEVEL">levels</a> (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> The cache memory is typically implemented with <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>. </p><p>Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB) which is part of the <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) which most CPUs have. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview"><span class="anchor" id="ICACHE"></span><span class="anchor" id="DCACHE"></span><span class="anchor" id="instruction_cache"></span><span class="anchor" id="data_cache"></span>Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>When trying to read from or write to a location in the main memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to the cache instead of the much slower main memory. </p><p>Many modern <a href="/wiki/Desktop_computer" title="Desktop computer">desktop</a>, <a href="/wiki/Server_(computing)" title="Server (computing)">server</a>, and industrial CPUs have at least three independent levels of caches (L1, L2 and L3) and different types of caches: </p> <dl><dt><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</dt> <dd>Used to speed virtual-to-physical address translation for both executable instructions and data. A single TLB can be provided for access to both instructions and data, or a separate Instruction TLB (ITLB) and data TLB (DTLB) can be provided. However, the TLB cache is part of the <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) and not directly related to the CPU caches.</dd></dl> <dl><dt><b>Instruction cache</b></dt> <dd> <dl><dt><a href="/wiki/Micro-operation" title="Micro-operation">MicroOp-cache</a></dt> <dd></dd> <dt><a href="/wiki/Branch_target_buffer" class="mw-redirect" title="Branch target buffer">Branch target buffer</a></dt> <dd></dd> <dt>Instruction cache (I-cache)</dt> <dd>Used to speed executable instruction fetch</dd></dl></dd></dl> <dl><dt><b>Data cache</b></dt> <dd> <dl><dt>Data cache (D-cache)</dt> <dd>Used to speed data fetch and store; the data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.; see also <a href="#Multi-level_caches">multi-level caches</a> below).</dd></dl></dd></dl> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=2" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:NeXTcube_motherboard.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/220px-NeXTcube_motherboard.jpg" decoding="async" width="220" height="216" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/330px-NeXTcube_motherboard.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d6/NeXTcube_motherboard.jpg/440px-NeXTcube_motherboard.jpg 2x" data-file-width="3371" data-file-height="3310" /></a><figcaption><a href="/wiki/Motherboard" title="Motherboard">Motherboard</a> of a <a href="/wiki/NeXTcube" title="NeXTcube">NeXTcube</a> computer (1990). At the lower edge of the image left from the middle, there is the CPU <a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a> operated at 25 <a href="/wiki/MHz" class="mw-redirect" title="MHz">MHz</a> with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.</figcaption></figure> <p>Early examples of CPU caches include the <a href="/wiki/Titan_(1963_computer)" title="Titan (1963 computer)">Atlas 2</a><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/IBM_System/360_Model_85" title="IBM System/360 Model 85">IBM System/360 Model 85</a><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> in the 1960s. The first CPUs that used a cache had only one level of cache; unlike later level 1 cache, it was not split into L1d (for data) and L1i (for instructions). Split L1 cache started in 1976 with the <a href="/wiki/IBM_801" title="IBM 801">IBM 801</a> CPU,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> became mainstream in the late 1980s, and in 1997 entered the embedded CPU market with the ARMv5TE. In 2015, even sub-dollar <a href="/wiki/System_on_a_chip" title="System on a chip">SoCs</a> split the L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split, and acts as a common repository for the already split L1 cache. Every core of a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a> has a dedicated L1 cache and is usually not shared between the cores. The L2 cache, and higher-level caches, may be shared between the cores. L4 cache is currently uncommon, and is generally <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic random-access memory</a> (DRAM) on a separate die or chip, rather than <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM). An exception to this is when <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> is used for all levels of cache, down to L1. Historically L1 was also on a separate die, however bigger die sizes have allowed integration of it as well as other cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and optimized differently. </p><p>Caches (like for RAM historically) have generally been sized in powers of: 2, 4, 8, 16 etc. <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KiB</a>; when up to <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> sizes (i.e. for larger non-L1), very early on the pattern broke down, to allow for larger caches without being forced into the doubling-in-size paradigm, with e.g. <a href="/wiki/Intel_Core_2_Duo" class="mw-redirect" title="Intel Core 2 Duo">Intel Core 2 Duo</a> with 3 MiB L2 cache in April 2008. This happened much later for L1 caches, as their size is generally still a small number of KiB. The <a href="/wiki/IBM_zEC12_(microprocessor)" class="mw-redirect" title="IBM zEC12 (microprocessor)">IBM zEC12</a> from 2012 is an exception however, to gain unusually large 96 KiB L1 data cache for its time, and e.g. the <a href="/wiki/IBM_z13_(microprocessor)" class="mw-redirect" title="IBM z13 (microprocessor)">IBM z13</a> having a 96 KiB L1 instruction cache (and 128 KiB L1 data cache),<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> and Intel <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a>-based processors from 2018, having 48 KiB L1 data cache and 48 KiB L1 instruction cache. In 2020, some <a href="/wiki/Intel_Atom" title="Intel Atom">Intel Atom</a> CPUs (with up to 24 cores) have (multiple of) 4.5 MiB and 15 MiB cache sizes.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=3" title="Edit section: Operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Cache_entries"><span class="anchor" id="cache_lines"></span><span class="anchor" id="CACHE-LINES"></span>Cache entries</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=4" title="Edit section: Cache entries"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Data is transferred between memory and cache in blocks of fixed size, called <i>cache lines</i> or <i>cache blocks</i>. When a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (called a tag). </p><p>When the processor needs to read or write a location in memory, it first checks for a corresponding entry in the cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a <b>cache hit</b> has occurred. However, if the processor does not find the memory location in the cache, a <b>cache miss</b> has occurred. In the case of a cache hit, the processor immediately reads or writes the data in the cache line. For a cache miss, the cache allocates a new entry and copies data from main memory, then the request is fulfilled from the contents of the cache. </p> <div class="mw-heading mw-heading3"><h3 id="Policies">Policies</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=5" title="Edit section: Policies"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Replacement_policies"><span class="anchor" id="EVICTION"></span>Replacement policies</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=6" title="Edit section: Replacement policies"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">Cache replacement policies</a></div> <p>To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, <a href="/wiki/Least-recently_used" class="mw-redirect" title="Least-recently used">least-recently used</a> (LRU), replaces the least recently accessed entry. </p><p>Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids the overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on the context. </p> <div class="mw-heading mw-heading4"><h4 id="Write_policies">Write policies</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=7" title="Edit section: Write policies"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cache_(computing)#WRITEPOLICIES" title="Cache (computing)">Cache (computing) § Writing policies</a></div> <p>If data is written to the cache, at some point it must also be written to main memory; the timing of this write is known as the write policy. In a <a href="/wiki/Write-through" class="mw-redirect" title="Write-through">write-through</a> cache, every write to the cache causes a write to main memory. Alternatively, in a <a href="/wiki/Write-back" class="mw-redirect" title="Write-back">write-back</a> or copy-back cache, writes are not immediately mirrored to the main memory, and the cache instead tracks which locations have been written over, marking them as <a href="/wiki/Dirty_bit" title="Dirty bit">dirty</a>. The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read the new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for the new memory location. </p><p>There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization). </p><p>Cached data from the main memory may be changed by other entities (e.g., peripherals using <a href="/wiki/Direct_memory_access" title="Direct memory access">direct memory access</a> (DMA) or another core in a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a>), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a <a href="/wiki/Multiprocessor" class="mw-redirect" title="Multiprocessor">multiprocessor</a> system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep the data consistent are known as <a href="/wiki/Cache_coherence" title="Cache coherence">cache coherence</a> protocols. </p> <div class="mw-heading mw-heading3"><h3 id="Cache_performance">Cache performance</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=8" title="Edit section: Cache performance"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance measurement</a> has become important in recent times where the speed gap between the memory performance and the processor performance is increasing exponentially. The cache was introduced to reduce this speed gap. Thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important, especially in high-performance systems. The cache hit rate and the cache miss rate play an important role in determining this performance. To improve the cache performance, reducing the miss rate becomes one of the necessary steps among other steps. Decreasing the access time to the cache also gives a boost to its performance and helps with optimization. </p> <div class="mw-heading mw-heading4"><h4 id="CPU_stalls">CPU stalls</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=9" title="Edit section: CPU stalls"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The time taken to fetch one cache line from memory (read <a href="/wiki/Latency_(engineering)" title="Latency (engineering)">latency</a> due to a cache miss) matters because the CPU will run out of work while waiting for the cache line. When a CPU reaches this state, it is called a stall. As CPUs become faster compared to main memory, stalls due to cache misses displace more potential computation; modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory. </p><p>Various techniques have been employed to keep the CPU busy during this time, including <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> in which the CPU attempts to execute independent instructions after the instruction that is waiting for the cache miss data. Another technology, used by many processors, is <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> (SMT), which allows an alternate thread to use the CPU core while the first thread waits for required CPU resources to become available. </p> <div class="mw-heading mw-heading2"><h2 id="Associativity">Associativity</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=10" title="Edit section: Associativity"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Cache,associative-fill-both.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/93/Cache%2Cassociative-fill-both.png/370px-Cache%2Cassociative-fill-both.png" decoding="async" width="370" height="184" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/9/93/Cache%2Cassociative-fill-both.png 1.5x" data-file-width="546" data-file-height="271" /></a><figcaption>An illustration of different ways in which memory locations can be cached by particular cache locations</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cache_placement_policies" title="Cache placement policies">Cache placement policies</a></div> <p>The <a href="/wiki/Cache_placement_policies" title="Cache placement policies">placement policy</a> decides where in the cache a copy of a particular entry of main memory will go. If the placement policy is free to choose any entry in the cache to hold the copy, the cache is called <i>fully associative</i>. At the other extreme, if each entry in the main memory can go in just one place in the cache, the cache is <i>direct-mapped</i>. Many caches implement a compromise in which each entry in the main memory can go to any one of N places in the cache, and are described as N-way set associative.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> For example, the level-1 data cache in an <a href="/wiki/AMD_Athlon" class="mw-redirect" title="AMD Athlon">AMD Athlon</a> is two-way set associative, which means that any particular location in main memory can be cached in either of two locations in the level-1 data cache. </p><p>Choosing the right value of associativity involves a <a href="/wiki/Trade-off" title="Trade-off">trade-off</a>. If there are ten places to which the placement policy could have mapped a memory location, then to check if that location is in the cache, ten cache entries must be searched. Checking more places takes more power and chip area, and potentially more time. On the other hand, caches with more associativity suffer fewer misses (see <a href="/wiki/Cache_performance_measurement_and_metric#Conflict_misses" title="Cache performance measurement and metric">conflict misses</a>), so that the CPU wastes less time reading from the slow main memory. The general guideline is that doubling the associativity, from direct mapped to two-way, or from two-way to four-way, has about the same effect on raising the hit rate as doubling the cache size. However, increasing associativity more than four does not improve hit rate as much,<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> and are generally done for other reasons (see <a href="#Virtual_aliasing">virtual aliasing</a>). Some CPUs can dynamically reduce the associativity of their caches in low-power states, which acts as a power-saving measure.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p>In order of worse but simple to better but complex: </p> <ul><li>Direct mapped cache – good best-case time, but unpredictable in the worst case</li> <li>Two-way set associative cache</li> <li>Two-way skewed associative cache<sup id="cite_ref-Seznec_14-0" class="reference"><a href="#cite_note-Seznec-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li> <li>Four-way set-associative cache</li> <li>Eight-way set-associative cache, a common choice for later implementations</li> <li>12-way set associative cache, similar to eight-way</li> <li>Fully associative cache – the best miss rates, but practical only for a small number of entries</li></ul> <div class="mw-heading mw-heading3"><h3 id="Direct-mapped_cache">Direct-mapped cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=11" title="Edit section: Direct-mapped cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In this cache organization, each location in the main memory can go in only one entry in the cache. Therefore, a direct-mapped cache can also be called a "one-way set associative" cache. It does not have a placement policy as such, since there is no choice of which cache entry's contents to evict. This means that if two locations map to the same entry, they may continually knock each other out. Although simpler, a direct-mapped cache needs to be much larger than an associative one to give comparable performance, and it is more unpredictable. Let <span class="texhtml mvar" style="font-style:italic;">x</span> be block number in cache, <span class="texhtml mvar" style="font-style:italic;">y</span> be block number of memory, and <span class="texhtml mvar" style="font-style:italic;">n</span> be number of blocks in cache, then mapping is done with the help of the equation <span class="texhtml"><i>x</i> = <i>y</i> mod <i>n</i></span>. </p> <div class="mw-heading mw-heading3"><h3 id="Two-way_set_associative_cache">Two-way set associative cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=12" title="Edit section: Two-way set associative cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>If each location in the main memory can be cached in either of two locations in the cache, one logical question is: <i>which one of the two?</i> The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in the cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster. Also <a href="/wiki/Cache_algorithms" class="mw-redirect" title="Cache algorithms">LRU</a> algorithm is especially simple since only one bit needs to be stored for each pair. </p> <div class="mw-heading mw-heading3"><h3 id="Speculative_execution">Speculative execution</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=13" title="Edit section: Speculative execution"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>One of the advantages of a direct-mapped cache is that it allows simple and fast <a href="/wiki/Speculative_execution" title="Speculative execution">speculation</a>. Once the address has been computed, the one cache index which might have a copy of that location in memory is known. That cache entry can be read, and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address. </p><p>The idea of having the processor use the cached data before the tag match completes can be applied to associative caches as well. A subset of the tag, called a <i>hint</i>, can be used to pick just one of the possible cache entries mapping to the requested address. The entry selected by the hint can then be used in parallel with checking the full tag. The hint technique works best when used in the context of address translation, as explained below. </p> <div class="mw-heading mw-heading3"><h3 id="Two-way_skewed_associative_cache">Two-way skewed associative cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=14" title="Edit section: Two-way skewed associative cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Other schemes have been suggested, such as the <i>skewed cache</i>,<sup id="cite_ref-Seznec_14-1" class="reference"><a href="#cite_note-Seznec-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> where the index for way 0 is direct, as above, but the index for way 1 is formed with a <a href="/wiki/Hash_function" title="Hash function">hash function</a>. A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside is extra latency from computing the hash function.<sup id="cite_ref-CK_15-0" class="reference"><a href="#cite_note-CK-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; <a href="/wiki/Cache_algorithms" class="mw-redirect" title="Cache algorithms">LRU</a> tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Pseudo-associative_cache">Pseudo-associative cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=15" title="Edit section: Pseudo-associative cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A true set-associative cache tests all the possible ways simultaneously, using something like a <a href="/wiki/Content-addressable_memory" title="Content-addressable memory">content-addressable memory</a>. A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache. </p><p>In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than a direct-mapped cache, closer to the miss rate of a fully associative cache.<sup id="cite_ref-CK_15-1" class="reference"><a href="#cite_note-CK-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Multicolumn_cache">Multicolumn cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=16" title="Edit section: Multicolumn cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Comparing with a direct-mapped cache, a set associative cache has a reduced number of bits for its cache set index that maps to a cache set, where multiple ways or blocks stays, such as 2 blocks for a 2-way set associative cache and 4 blocks for a 4-way set associative cache. Comparing with a direct mapped cache, the unused cache index bits become a part of the tag bits. For example, a 2-way set associative cache contributes 1 bit to the tag and a 4-way set associative cache contributes 2 bits to the tag. The basic idea of the multicolumn cache<sup id="cite_ref-Two-fast_17-0" class="reference"><a href="#cite_note-Two-fast-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> is to use the set index to map to a cache set as a conventional set associative cache does, and to use the added tag bits to index a way in the set. For example, in a 4-way set associative cache, the two bits are used to index way 00, way 01, way 10, and way 11, respectively. This double cache indexing is called a "major location mapping", and its latency is equivalent to a direct-mapped access. Extensive experiments in multicolumn cache design<sup id="cite_ref-Two-fast_17-1" class="reference"><a href="#cite_note-Two-fast-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> shows that the hit ratio to major locations is as high as 90%. If cache mapping conflicts with a cache block in the major location, the existing cache block will be moved to another cache way in the same set, which is called "selected location". Because the newly indexed cache block is a most recently used (MRU) block, it is placed in the major location in multicolumn cache with a consideration of temporal locality. Since multicolumn cache is designed for a cache with a high associativity, the number of ways in each set is high; thus, it is easy find a selected location in the set. A selected location index by an additional hardware is maintained for the major location in a cache block.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (May 2023)">citation needed</span></a></i>]</sup> </p><p>Multicolumn cache remains a high hit ratio due to its high associativity, and has a comparable low latency to a direct-mapped cache due to its high percentage of hits in major locations. The concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in ARM Cortex R chip,<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> Intel's way-predicting cache memory,<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> IBM's reconfigurable multi-way associative cache memory<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> and Oracle's dynamic cache replacement way selection based on address tab bits.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Cache_entry_structure">Cache entry structure</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=17" title="Edit section: Cache entry structure"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Cache row entries usually have the following structure: </p> <table style="width:30%; text-align:center" border="1"> <tbody><tr> <td>tag</td> <td>data block</td> <td>flag bits </td></tr></tbody></table> <p>The <i>data block</i> (cache line) contains the actual data fetched from the main memory. The <i>tag</i> contains (part of) the address of the actual data fetched from the main memory. The flag bits are <a href="#Flag_bits">discussed below</a>. </p><p>The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in the cache. (The tag, flag and <a href="/wiki/ECC_memory#Cache" title="ECC memory">error correction code</a> bits are not included in the size,<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> although they do affect the physical area of a cache.) </p><p>An effective memory address which goes along with the cache line (memory block) is split (<a href="/wiki/Most_significant_bit" class="mw-redirect" title="Most significant bit">MSB</a> to <a href="/wiki/Least_significant_bit" class="mw-redirect" title="Least significant bit">LSB</a>) into the tag, the index and the block offset.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> </p> <table style="width:30%; text-align:center" border="1"> <tbody><tr> <td>tag</td> <td>index</td> <td>block offset </td></tr></tbody></table> <p>The index describes which cache set that the data has been put in. The index length is <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \lceil \log _{2}(s)\rceil }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo fence="false" stretchy="false">⌈</mo> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mo stretchy="false">(</mo> <mi>s</mi> <mo stretchy="false">)</mo> <mo fence="false" stretchy="false">⌉</mo> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \lceil \log _{2}(s)\rceil }</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/b36533bd5e32a9b0885d6a902752ea25dd1312c3" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:8.991ex; height:2.843ex;" alt="{\displaystyle \lceil \log _{2}(s)\rceil }"></span> bits for <span class="texhtml mvar" style="font-style:italic;">s</span> cache sets. </p><p>The block offset specifies the desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \lceil \log _{2}(b)\rceil }"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mo fence="false" stretchy="false">⌈</mo> <msub> <mi>log</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msub> <mo>⁡</mo> <mo stretchy="false">(</mo> <mi>b</mi> <mo stretchy="false">)</mo> <mo fence="false" stretchy="false">⌉</mo> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \lceil \log _{2}(b)\rceil }</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/1b8034533918755b6862f7ec7898c7912b636bbc" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.838ex; width:8.898ex; height:2.843ex;" alt="{\displaystyle \lceil \log _{2}(b)\rceil }"></span> bits, where <span class="texhtml mvar" style="font-style:italic;">b</span> is the number of bytes per data block. The tag contains the most significant bits of the address, which are checked against all rows in the current set (the set has been retrieved by index) to see if this set contains the requested address. If it does, a cache hit occurs. The tag length in bits is as follows: </p> <dl><dd><dl><dd><code>tag_length = address_length - index_length - block_offset_length</code></dd></dl></dd></dl> <p>Some authors refer to the block offset as simply the "offset"<sup id="cite_ref-ccs.neu.edu_25-0" class="reference"><a href="#cite_note-ccs.neu.edu-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> or the "displacement".<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Example">Example</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=18" title="Edit section: Example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The original <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> processor had a four-way set associative L1 data cache of 8 <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KiB</a> in size, with 64-byte cache blocks. Hence, there are 8 KiB / 64 = 128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 2<sup>5</sup> = 32 different indices. There are 2<sup>6</sup> = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 32 − 5 − 6 = 21 bits for the tag field. </p><p>The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KiB in size, with 128-byte cache blocks. This implies 32 − 8 − 7 = 17 bits for the tag field.<sup id="cite_ref-ccs.neu.edu_25-1" class="reference"><a href="#cite_note-ccs.neu.edu-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Flag_bits"><span class="anchor" id="Flag_bits"></span> Flag bits</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=19" title="Edit section: Flag bits"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data. </p><p>On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times, such as when multi-master <a href="/wiki/Bus_snooping" title="Bus snooping">bus snooping</a> hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in the local cache are now stale and should be marked invalid. </p><p>A data cache typically requires two flag bits per cache line – a valid bit and a <a href="/wiki/Dirty_bit" title="Dirty bit">dirty bit</a>. Having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory ("dirty"), meaning that the processor has written data to that line and the new value has not propagated all the way to main memory. </p> <div class="mw-heading mw-heading2"><h2 id="Cache_miss"><span class="anchor" id="CACHE-MISS"></span>Cache miss</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=20" title="Edit section: Cache miss"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A cache miss is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss. </p><p><i>Cache read misses</i> from an <i>instruction</i> cache generally cause the largest delay, because the processor, or at least the <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">thread of execution</a>, has to wait (stall) until the instruction is fetched from main memory. <i>Cache read misses</i> from a <i>data</i> cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution. <i>Cache write misses</i> to a <i>data</i> cache generally cause the shortest delay, because the write can be queued and there are few limitations on the execution of subsequent instructions; the processor can continue until the queue is full. For a detailed introduction to the types of misses, see <a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">cache performance measurement and metric</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Address_translation"><span class="anchor" id="ADDRTRANS"></span>Address translation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=21" title="Edit section: Address translation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Most general purpose CPUs implement some form of <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a>. To summarize, either each program running on the machine sees its own simplified <a href="/wiki/Address_space" title="Address space">address space</a>, which contains code and data for that program only, or all programs run in a common virtual address space. A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write. </p><p>Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory. The portion of the processor that does this translation is known as the <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU). The fast path through the MMU can perform those translations stored in the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB), which is a cache of mappings from the operating system's <a href="/wiki/Page_table" title="Page table">page table</a>, segment table, or both. </p><p>For the purposes of the present discussion, there are three important features of address translation: </p> <ul><li><i>Latency:</i> The physical address is available from the MMU some time, perhaps a few cycles, after the virtual address is available from the address generator.</li> <li><span class="anchor" id="Virtual_aliasing"></span><i>Aliasing:</i> Multiple virtual addresses can map to a single physical address. Most processors guarantee that all updates to that single physical address will happen in program order. To deliver on that guarantee, the processor must ensure that only one copy of a physical address resides in the cache at any given time.</li> <li><i>Granularity:</i> The virtual address space is broken up into pages. For instance, a 4 <a href="/wiki/Gibibyte" class="mw-redirect" title="Gibibyte">GiB</a> virtual address space might be cut up into 1,048,576 pages of 4 KiB size, each of which can be independently mapped. There may be multiple page sizes supported; see <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a> for elaboration.</li></ul> <p>One early virtual memory system, the <a href="/wiki/IBM_M44/44X" title="IBM M44/44X">IBM M44/44X</a>, required an access to a mapping table held in <a href="/wiki/Core_memory" class="mw-redirect" title="Core memory">core memory</a> before every programmed access to main memory.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>NB 1<span class="cite-bracket">]</span></a></sup> With no caches, and with the mapping table memory running at the same speed as main memory this effectively cut the speed of memory access in half. Two early machines that used a <a href="/wiki/Page_table" title="Page table">page table</a> in main memory for mapping, the <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">IBM System/360 Model 67</a> and the <a href="/wiki/GE_645" title="GE 645">GE 645</a>, both had a small associative memory as a cache for accesses to the in-memory page table. Both machines predated the first machine with a cache for main memory, the <a href="/wiki/IBM_System/360_Model_85" title="IBM System/360 Model 85">IBM System/360 Model 85</a>, so the first hardware cache used in a computer system was not a data or instruction cache, but rather a TLB. </p><p>Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses: </p> <ul><li><i>Physically indexed, physically tagged</i> (PIPT) caches use the physical address for both the index and the tag. While this is simple and avoids problems with aliasing, it is also slow, as the physical address must be looked up (which could involve a TLB miss and access to main memory) before that address can be looked up in the cache.</li> <li><i>Virtually indexed, virtually tagged</i> (VIVT) caches use the virtual address for both the index and the tag. This caching scheme can result in much faster lookups, since the MMU does not need to be consulted first to determine the physical address for a given virtual address. However, VIVT suffers from aliasing problems, where several different virtual addresses may refer to the same physical address. The result is that such addresses would be cached separately despite referring to the same memory, causing coherency problems. Although solutions to this problem exist<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> they do not work for standard coherence protocols. Another problem is homonyms, where the same virtual address maps to several different physical addresses. It is not possible to distinguish these mappings merely by looking at the virtual index itself, though potential solutions include: flushing the cache after a <a href="/wiki/Context_switch" title="Context switch">context switch</a>, forcing address spaces to be non-overlapping, tagging the virtual address with an address space ID (ASID). Additionally, there is a problem that virtual-to-physical mappings can change, which would require flushing cache lines, as the VAs would no longer be valid. All these issues are absent if tags use physical addresses (VIPT).</li> <li><i>Virtually indexed, physically tagged</i> (VIPT) caches use the virtual address for the index and the physical address in the tag. The advantage over PIPT is lower latency, as the cache line can be looked up in parallel with the TLB translation, however the tag cannot be compared until the physical address is available. The advantage over VIVT is that since the tag has the physical address, the cache can detect homonyms. Theoretically, VIPT requires more tags bits because some of the index bits could differ between the virtual and physical addresses (for example bit 12 and above for 4 KiB pages) and would have to be included both in the virtual index and in the physical tag. In practice this is not an issue because, in order to avoid coherency problems, VIPT caches are designed to have no such index bits (e.g., by limiting the total number of bits for the index and the block offset to 12 for 4 KiB pages); this limits the size of VIPT caches to the page size times the associativity of the cache.</li> <li><i>Physically indexed, virtually tagged</i> (PIVT) caches are often claimed in literature to be useless and non-existing.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> However, the <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <a href="/wiki/R6000" title="R6000">R6000</a> uses this cache type as the sole known implementation.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> The R6000 is implemented in <a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">emitter-coupled logic</a>, which is an extremely fast technology not suitable for large memories such as a <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a>. The R6000 solves the issue by putting the TLB memory into a reserved part of the second-level cache having a tiny, high-speed TLB "slice" on chip. The cache is indexed by the physical address obtained from the TLB slice. However, since the TLB slice only translates those virtual address bits that are necessary to index the cache and does not use any tags, false cache hits may occur, which is solved by tagging with the virtual address.</li></ul> <p>The speed of this recurrence (the <i>load latency</i>) is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM. </p><p>But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed. </p><p>Caches have historically used both virtual and physical addresses for the cache tags, although virtual tagging is now uncommon. If the TLB lookup can finish before the cache RAM lookup, then the physical address is available in time for tag compare, and there is no need for virtual tagging. Large caches, then, tend to be physically tagged, and only small, very low latency caches are virtually tagged. In recent general-purpose CPUs, virtual tagging has been superseded by vhints, as described below. </p> <div class="mw-heading mw-heading3"><h3 id="Homonym_and_synonym_problems">Homonym and synonym problems</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=22" title="Edit section: Homonym and synonym problems"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A cache that relies on virtual indexing and tagging becomes inconsistent after the same virtual address is mapped into different physical addresses (<a href="/wiki/Homonym" title="Homonym">homonym</a>), which can be solved by using physical address for tagging, or by storing the address space identifier in the cache line. However, the latter approach does not help against the <a href="/wiki/Synonym" title="Synonym">synonym</a> problem, in which several cache lines end up storing data for the same physical address. Writing to such locations may update only one location in the cache, leaving the others with inconsistent data. This issue may be solved by using non-overlapping memory layouts for different address spaces, or otherwise the cache (or a part of it) must be flushed when the mapping changes.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Virtual_tags_and_vhints">Virtual tags and vhints</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=23" title="Edit section: Virtual tags and vhints"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The great advantage of virtual tags is that, for associative caches, they allow the tag match to proceed before the virtual to physical translation is done. However, coherence probes and evictions present a physical address for action. The hardware must have some means of converting the physical addresses into a cache index, generally by storing physical tags as well as virtual tags. For comparison, a physically tagged cache does not need to keep virtual tags, which is simpler. When a virtual to physical mapping is deleted from the TLB, cache entries with those virtual addresses will have to be flushed somehow. Alternatively, if cache entries are allowed on pages not mapped by the TLB, then those entries will have to be flushed when the access rights on those pages are changed in the page table. </p><p>It is also possible for the operating system to ensure that no virtual aliases are simultaneously resident in the cache. The operating system makes this guarantee by enforcing page coloring, which is described below. Some early RISC processors (SPARC, RS/6000) took this approach. It has not been used recently, as the hardware cost of detecting and evicting virtual aliases has fallen and the software complexity and performance penalty of perfect page coloring has risen. </p><p>It can be useful to distinguish the two functions of tags in an associative cache: they are used to determine which way of the entry set to select, and they are used to determine if the cache hit or missed. The second function must always be correct, but it is permissible for the first function to guess, and get the wrong answer occasionally. </p><p>Some processors (e.g. early SPARCs) have caches with both virtual and physical tags. The virtual tags are used for way selection, and the physical tags are used for determining hit or miss. This kind of cache enjoys the latency advantage of a virtually tagged cache, and the simple software interface of a physically tagged cache. It bears the added cost of duplicated tags, however. Also, during miss processing, the alternate ways of the cache line indexed have to be probed for virtual aliases and any matches evicted. </p><p>The extra area (and some latency) can be mitigated by keeping <i>virtual hints</i> with each cache entry instead of virtual tags. These hints are a subset or hash of the virtual tag, and are used for selecting the way of the cache from which to get data and a physical tag. Like a virtually tagged cache, there may be a virtual hint match but physical tag mismatch, in which case the cache entry with the matching hint must be evicted so that cache accesses after the cache fill at this address will have just one hint match. Since virtual hints have fewer bits than virtual tags distinguishing them from one another, a virtually hinted cache suffers more conflict misses than a virtually tagged cache. </p><p>Perhaps the ultimate reduction of virtual hints can be found in the Pentium 4 (Willamette and Northwood cores). In these processors the virtual hint is effectively two bits, and the cache is four-way set associative. Effectively, the hardware maintains a simple permutation from virtual address to cache index, so that no <a href="/wiki/Content-addressable_memory" title="Content-addressable memory">content-addressable memory</a> (CAM) is necessary to select the right one of the four ways fetched. </p> <div class="mw-heading mw-heading3"><h3 id="Page_coloring">Page coloring</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=24" title="Edit section: Page coloring"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cache_coloring" title="Cache coloring">Cache coloring</a></div> <p>Large physically indexed caches (usually secondary caches) run into a problem: the operating system rather than the application controls which pages collide with one another in the cache. Differences in page allocation from one program run to the next lead to differences in the cache collision patterns, which can lead to very large differences in program performance. These differences can make it very difficult to get a consistent and repeatable timing for a benchmark run. </p><p>To understand the problem, consider a CPU with a 1 MiB physically indexed direct-mapped level-2 cache and 4 KiB virtual memory pages. Sequential physical pages map to sequential locations in the cache until after 256 pages the pattern wraps around. We can label each physical page with a color of 0–255 to denote where in the cache it can go. Locations within physical pages with different colors cannot conflict in the cache. </p><p>Programmers attempting to make maximum use of the cache may arrange their programs' access patterns so that only 1 MiB of data need be cached at any given time, thus avoiding capacity misses. But they should also ensure that the access patterns do not have conflict misses. One way to think about this problem is to divide up the virtual pages the program uses and assign them virtual colors in the same way as physical colors were assigned to physical pages before. Programmers can then arrange the access patterns of their code so that no two pages with the same virtual color are in use at the same time. There is a wide literature on such optimizations (e.g. <a href="/wiki/Loop_nest_optimization" title="Loop nest optimization">loop nest optimization</a>), largely coming from the <a href="/wiki/High_Performance_Computing" class="mw-redirect" title="High Performance Computing">High Performance Computing (HPC)</a> community. </p><p>The snag is that while all the pages in use at any given moment may have different virtual colors, some may have the same physical colors. In fact, if the operating system assigns physical pages to virtual pages randomly and uniformly, it is extremely likely that some pages will have the same physical color, and then locations from those pages will collide in the cache (this is the <a href="/wiki/Birthday_paradox" class="mw-redirect" title="Birthday paradox">birthday paradox</a>). </p><p>The solution is to have the operating system attempt to assign different physical color pages to different virtual colors, a technique called <i>page coloring</i>. Although the actual mapping from virtual to physical color is irrelevant to system performance, odd mappings are difficult to keep track of and have little benefit, so most approaches to page coloring simply try to keep physical and virtual page colors the same. </p><p>If the operating system can guarantee that each physical page maps to only one virtual color, then there are no virtual aliases, and the processor can use virtually indexed caches with no need for extra virtual alias probes during miss handling. Alternatively, the OS can flush a page from the cache whenever it changes from one virtual color to another. As mentioned above, this approach was used for some early SPARC and RS/6000 designs. </p><p>The software page coloring technique has been used to effectively partition the shared Last level Cache (LLC) in multicore processors.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> This operating system-based LLC management in multicore processors has been adopted by Intel.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Cache_hierarchy_in_a_modern_processor"><span class="anchor" id="Cache_hierarchy"></span>Cache hierarchy in a modern processor</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=25" title="Edit section: Cache hierarchy in a modern processor"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Hwloc.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/95/Hwloc.png/660px-Hwloc.png" decoding="async" width="660" height="305" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/95/Hwloc.png/990px-Hwloc.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/95/Hwloc.png/1320px-Hwloc.png 2x" data-file-width="1450" data-file-height="670" /></a><figcaption>Memory hierarchy of an AMD Bulldozer server</figcaption></figure> <p>Modern processors have multiple interacting on-chip caches. The operation of a particular cache can be completely specified by the cache size, the cache block size, the number of blocks in a set, the cache set replacement policy, and the cache write policy (write-through or write-back).<sup id="cite_ref-ccs.neu.edu_25-2" class="reference"><a href="#cite_note-ccs.neu.edu-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>While all of the cache blocks in a particular cache are the same size and have the same associativity, typically the "lower-level" caches (called Level 1 cache) have a smaller number of blocks, smaller block size, and fewer blocks in a set, but have very short access times. "Higher-level" caches (i.e. Level 2 and above) have progressively larger numbers of blocks, larger block size, more blocks in a set, and relatively longer access times, but are still much faster than main memory. </p><p>Cache entry replacement policy is determined by a <a href="/wiki/Cache_algorithm" class="mw-redirect" title="Cache algorithm">cache algorithm</a> selected to be implemented by the processor designers. In some cases, multiple algorithms are provided for different kinds of work loads. </p> <div class="mw-heading mw-heading3"><h3 id="Specialized_caches">Specialized caches</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=26" title="Edit section: Specialized caches"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Pipelined CPUs access memory from multiple points in the <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipeline</a>: instruction fetch, <a href="/wiki/Virtual_memory" title="Virtual memory">virtual-to-physical</a> address translation, and data fetch (see <a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">classic RISC pipeline</a>). The natural design is to use different physical caches for each of these points, so that no one physical resource has to be scheduled to service two points in the pipeline. Thus the pipeline naturally ends up with at least three separate caches (instruction, <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a>, and data), each specialized to its particular role. </p> <div class="mw-heading mw-heading4"><h4 id="Victim_cache">Victim cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=27" title="Edit section: Victim cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Victim_cache" title="Victim cache">Victim cache</a></div> <p>A <b>victim cache</b> is a cache used to hold blocks evicted from a CPU cache upon replacement. The victim cache lies between the main cache and its refill path, and holds only those blocks of data that were evicted from the main cache. The victim cache is usually fully associative, and is intended to reduce the number of conflict misses. Many commonly used programs do not require an associative mapping for all the accesses. In fact, only a small fraction of the memory accesses of the program require high associativity. The victim cache exploits this property by providing high associativity to only these accesses. It was introduced by <a href="/wiki/Norman_Jouppi" title="Norman Jouppi">Norman Jouppi</a> from DEC in 1990.<sup id="cite_ref-Jouppi1990_38-0" class="reference"><a href="#cite_note-Jouppi1990-38"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>Intel's <i><a href="/wiki/Crystalwell" class="mw-redirect" title="Crystalwell">Crystalwell</a></i><sup id="cite_ref-intel-ark-crystal-well_39-0" class="reference"><a href="#cite_note-intel-ark-crystal-well-39"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> variant of its <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> processors introduced an on-package 128 MiB <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> Level 4 cache which serves as a victim cache to the processors' Level 3 cache.<sup id="cite_ref-anandtech-i74950hq_40-0" class="reference"><a href="#cite_note-anandtech-i74950hq-40"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> In the <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> microarchitecture the Level 4 cache no longer works as a victim cache.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Trace_cache"><span class="anchor" id="TRACE-CACHE"></span>Trace cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=28" title="Edit section: Trace cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Trace_cache" title="Trace cache">Trace cache</a></div> <p>One of the more extreme examples of cache specialization is the <b>trace cache</b> (also known as <i>execution trace cache</i>) found in the <a href="/wiki/Intel" title="Intel">Intel</a> <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> microprocessors. A trace cache is a mechanism for increasing the instruction fetch bandwidth and decreasing power consumption (in the case of the Pentium 4) by storing traces of <a href="/wiki/Instruction_(computer_science)" class="mw-redirect" title="Instruction (computer science)">instructions</a> that have already been fetched and decoded.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> </p><p>A trace cache stores instructions either after they have been decoded, or as they are retired. Generally, instructions are added to trace caches in groups representing either individual <a href="/wiki/Basic_block" title="Basic block">basic blocks</a> or dynamic instruction traces. The Pentium 4's trace cache stores <a href="/wiki/Micro-operations" class="mw-redirect" title="Micro-operations">micro-operations</a> resulting from decoding x86 instructions, providing also the functionality of a micro-operation cache. Having this, the next time an instruction is needed, it does not have to be decoded into micro-ops again.<sup id="cite_ref-agner.org_43-0" class="reference"><a href="#cite_note-agner.org-43"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 63–68">: 63–68 </span></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Write_Coalescing_Cache_(WCC)"><span id="Write_Coalescing_Cache_.28WCC.29"></span>Write Coalescing Cache (WCC)</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=29" title="Edit section: Write Coalescing Cache (WCC)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Write Coalescing Cache<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> is a special cache that is part of L2 cache in <a href="/wiki/AMD" title="AMD">AMD</a>'s <a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer microarchitecture</a>. Stores from both L1D caches in the module go through the WCC, where they are buffered and coalesced. The WCC's task is reducing number of writes to the L2 cache. </p> <div class="mw-heading mw-heading4"><h4 id="Micro-operation_(μop_or_uop)_cache"><span id="Micro-operation_.28.CE.BCop_or_uop.29_cache"></span><span class="anchor" id="UOP-CACHE"></span>Micro-operation (μop or uop) cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=30" title="Edit section: Micro-operation (μop or uop) cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A <b>micro-operation cache</b> (<b>μop cache</b>, <b>uop cache</b> or <b>UC</b>)<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> is a specialized cache that stores <a href="/wiki/Micro-operation" title="Micro-operation">micro-operations</a> of decoded instructions, as received directly from the <a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">instruction decoders</a> or from the instruction cache. When an instruction needs to be decoded, the μop cache is checked for its decoded form which is re-used if cached; if it is not available, the instruction is decoded and then cached. </p><p>One of the early works describing μop cache as an alternative frontend for the Intel <a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6 processor family</a> is the 2001 paper <i>"Micro-Operation Cache: A Power Aware Frontend for Variable Instruction Length ISA"</i>.<sup id="cite_ref-uop-intel_46-0" class="reference"><a href="#cite_note-uop-intel-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> Later, Intel included μop caches in its <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> processors and in successive microarchitectures like <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a> and <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>.<sup id="cite_ref-agner.org_43-1" class="reference"><a href="#cite_note-agner.org-43"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 121–123">: 121–123 </span></sup><sup id="cite_ref-anandtech-haswell_47-0" class="reference"><a href="#cite_note-anandtech-haswell-47"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> AMD implemented a μop cache in their <a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen microarchitecture</a>.<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>Fetching complete pre-decoded instructions eliminates the need to repeatedly decode variable length complex instructions into simpler fixed-length micro-operations, and simplifies the process of predicting, fetching, rotating and aligning fetched instructions. A μop cache effectively offloads the fetch and decode hardware, thus decreasing <a href="/wiki/Power_consumption" class="mw-redirect" title="Power consumption">power consumption</a> and improving the frontend supply of decoded micro-operations. The μop cache also increases performance by more consistently delivering decoded micro-operations to the backend and eliminating various bottlenecks in the CPU's fetch and decode logic.<sup id="cite_ref-uop-intel_46-1" class="reference"><a href="#cite_note-uop-intel-46"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-anandtech-haswell_47-1" class="reference"><a href="#cite_note-anandtech-haswell-47"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </p><p>A μop cache has many similarities with a trace cache, although a μop cache is much simpler thus providing better power efficiency; this makes it better suited for implementations on battery-powered devices. The main disadvantage of the trace cache, leading to its power inefficiency, is the hardware complexity required for its <a href="/wiki/Heuristic" title="Heuristic">heuristic</a> deciding on caching and reusing dynamically created instruction traces.<sup id="cite_ref-tc-slides_49-0" class="reference"><a href="#cite_note-tc-slides-49"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Branch_target_instruction_cache">Branch target instruction cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=31" title="Edit section: Branch target instruction cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A <b>branch target cache</b> or <b>branch target instruction cache</b>, the name used on <a href="/wiki/ARM_microprocessors" class="mw-redirect" title="ARM microprocessors">ARM microprocessors</a>,<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> is a specialized cache which holds the first few instructions at the destination of a taken branch. This is used by low-powered processors which do not need a normal instruction cache because the memory system is capable of delivering instructions fast enough to satisfy the CPU without one. However, this only applies to consecutive instructions in sequence; it still takes several cycles of latency to restart instruction fetch at a new address, causing a few cycles of pipeline bubble after a control transfer. A branch target cache provides instructions for those few cycles avoiding a delay after most taken branches. </p><p>This allows full-speed operation with a much smaller cache than a traditional full-time instruction cache. </p> <div class="mw-heading mw-heading4"><h4 id="Smart_cache">Smart cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=32" title="Edit section: Smart cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>Smart cache</b> is a <a href="#MULTILEVEL">level 2</a> or <a href="#MULTILEVEL">level 3</a> caching method for multiple execution cores, developed by <a href="/wiki/Intel" title="Intel">Intel</a>. </p><p>Smart Cache shares the actual cache memory between the cores of a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a>. In comparison to a dedicated per-core cache, the overall <a href="/wiki/Cache_miss" class="mw-redirect" title="Cache miss">cache miss</a> rate decreases when cores do not require equal parts of the cache space. Consequently, a single core can use the full level 2 or level 3 cache while the other cores are inactive.<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> Furthermore, the shared cache makes it faster to share memory among different execution cores.<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Multi-level_caches"><span class="anchor" id="MULTILEVEL"></span>Multi-level caches</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=33" title="Edit section: Multi-level caches"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></div> <p>Another issue is the fundamental tradeoff between cache latency and hit rate. Larger caches have better hit rates but longer latency. To address this tradeoff, many computers use multiple levels of cache, with small fast caches backed up by larger, slower caches. Multi-level caches generally operate by checking the fastest cache, <i>level 1</i> (<b>L1</b>), first; if it hits, the processor proceeds at high speed. If that smaller cache misses, the next fastest cache, <i>level 2</i> (<b>L2</b>), is checked, and so on, before accessing external memory. </p><p>As the latency difference between main memory and the fastest cache has become larger, some processors have begun to utilize as many as three levels of on-chip cache. Price-sensitive designs used this to pull the entire cache hierarchy on-chip, but by the 2010s some of the highest-performance designs returned to having large off-chip caches, which is often implemented in <a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> and mounted on a <a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a>, as a fourth cache level. In rare cases, such as in the mainframe CPU <a href="/wiki/IBM_z15_(microprocessor)" class="mw-redirect" title="IBM z15 (microprocessor)">IBM z15</a> (2019), all levels down to L1 are implemented by eDRAM, replacing <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> entirely (for cache, SRAM is still used for registers). The <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM-based</a> <a href="/wiki/Apple_M1" title="Apple M1">Apple M1</a> has a 192 KiB L1 cache for each of the four high-performance cores, an unusually large amount; however the four high-efficiency cores only have 128 KiB. </p><p>The benefits of L3 and L4 caches depend on the application's access patterns. Examples of products incorporating L3 and L4 caches include the following: </p> <ul><li><a href="/wiki/Alpha_21164" title="Alpha 21164">Alpha 21164</a> (1995) had 1 to 64 MiB off-chip L3 cache.</li> <li><a href="/wiki/AMD_K6-III" title="AMD K6-III">AMD K6-III</a> (1999) had motherboard-based L3 cache.</li> <li>IBM <a href="/wiki/POWER4" title="POWER4">POWER4</a> (2001) had off-chip L3 caches of 32 MiB per processor, shared among several processors.</li> <li><a href="/wiki/Itanium_2" class="mw-redirect" title="Itanium 2">Itanium 2</a> (2003) had a 6 MiB <a href="/w/index.php?title=Unified_cache&action=edit&redlink=1" class="new" title="Unified cache (page does not exist)">unified</a> level 3 (L3) cache on-die; the <a href="/wiki/Itanium_2" class="mw-redirect" title="Itanium 2">Itanium 2</a> (2003) MX 2 module incorporated two Itanium 2 processors along with a shared 64 MiB L4 cache on a <a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a> that was pin compatible with a Madison processor.</li> <li>Intel's <a href="/wiki/Xeon" title="Xeon">Xeon</a> MP product codenamed "Tulsa" (2006) features 16 MiB of on-die L3 cache shared between two processor cores.</li> <li><a href="/wiki/AMD_Phenom" title="AMD Phenom">AMD Phenom</a> (2007) with 2 MiB of L3 cache.</li> <li>AMD <a href="/wiki/Phenom_II" title="Phenom II">Phenom II</a> (2008) has up to 6 MiB on-die unified L3 cache.</li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Intel Core i7</a> (2008) has an 8 MiB on-die unified L3 cache that is inclusive, shared by all cores.</li> <li>Intel <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> CPUs with integrated <a href="/wiki/Intel_Iris_Pro_Graphics" class="mw-redirect" title="Intel Iris Pro Graphics">Intel Iris Pro Graphics</a> have 128 MiB of eDRAM acting essentially as an L4 cache.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup></li></ul> <p>Finally, at the other end of the memory hierarchy, the CPU <a href="/wiki/Register_file" title="Register file">register file</a> itself can be considered the smallest, fastest cache in the system, with the special characteristic that it is scheduled in software—typically by a compiler, as it allocates registers to hold values retrieved from main memory for, as an example, <a href="/wiki/Loop_nest_optimization" title="Loop nest optimization">loop nest optimization</a>. However, with <a href="/wiki/Register_renaming" title="Register renaming">register renaming</a> most compiler register assignments are reallocated dynamically by hardware at runtime into a register bank, allowing the CPU to break false data dependencies and thus easing pipeline hazards. </p><p>Register files sometimes also have hierarchy: The <a href="/wiki/Cray-1" title="Cray-1">Cray-1</a> (circa 1976) had eight address "A" and eight scalar data "S" registers that were generally usable. There was also a set of 64 address "B" and 64 scalar data "T" registers that took longer to access, but were faster than main memory. The "B" and "T" registers were provided because the Cray-1 did not have a data cache. (The Cray-1 did, however, have an instruction cache.) </p> <div class="mw-heading mw-heading4"><h4 id="Multi-core_chips"><span class="anchor" id="LLC"></span>Multi-core chips</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=34" title="Edit section: Multi-core chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>When considering a chip with <a href="/wiki/Multi-core_processor" title="Multi-core processor">multiple cores</a>, there is a question of whether the caches should be shared or local to each core. Implementing shared cache inevitably introduces more wiring and complexity. But then, having one cache per <i>chip</i>, rather than <i>core</i>, greatly reduces the amount of space needed, and thus one can include a larger cache. </p><p>Typically, sharing the L1 cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single-core chip. However, for the highest-level cache, the last one called before accessing memory, having a global cache is desirable for several reasons, such as allowing a single core to use the whole cache, reducing data redundancy by making it possible for different processes or threads to share cached data, and reducing the complexity of utilized cache coherency protocols.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> For example, an eight-core chip with three levels may include an L1 cache for each core, one intermediate L2 cache for each pair of cores, and one L3 cache shared between all cores. </p><p>A shared highest-level cache, which is called before accessing memory, is usually referred to as a <i>last level cache</i> (LLC). Additional techniques are used for increasing the level of parallelism when LLC is shared between multiple cores, including slicing it into multiple pieces which are addressing certain ranges of memory addresses, and can be accessed independently.<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Separate_versus_unified">Separate versus unified</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=35" title="Edit section: Separate versus unified"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In a separate cache structure, instructions and data are cached separately, meaning that a cache line is used to cache either instructions or data, but not both; various benefits have been demonstrated with separate data and instruction <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffers</a>.<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> In a unified structure, this constraint is not present, and cache lines can be used to cache both instructions and data. </p> <div class="mw-heading mw-heading4"><h4 id="Exclusive_versus_inclusive"><span class="anchor" id="INCLUSIVE"></span><span class="anchor" id="EXCLUSIVE"></span>Exclusive versus inclusive</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=36" title="Edit section: Exclusive versus inclusive"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Multi-level caches introduce new design decisions. For instance, in some processors, all data in the L1 cache must also be somewhere in the L2 cache. These caches are called <i>strictly inclusive</i>. Other processors (like the <a href="/wiki/AMD_Athlon" class="mw-redirect" title="AMD Athlon">AMD Athlon</a>) have <i>exclusive</i> caches: data is guaranteed to be in at most one of the L1 and L2 caches, never in both. Still other processors (like the Intel <a href="/wiki/Pentium_II" title="Pentium II">Pentium II</a>, <a href="/wiki/Pentium_III" title="Pentium III">III</a>, and <a href="/wiki/Pentium_4" title="Pentium 4">4</a>) do not require that data in the L1 cache also reside in the L2 cache, although it may often do so. There is no universally accepted name for this intermediate policy;<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ispass04_58-0" class="reference"><a href="#cite_note-ispass04-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> two common names are "non-exclusive" and "partially-inclusive". </p><p>The advantage of exclusive caches is that they store more data. This advantage is larger when the exclusive L1 cache is comparable to the L2 cache, and diminishes if the L2 cache is many times larger than the L1 cache. When the L1 misses and the L2 hits on an access, the hitting cache line in the L2 is exchanged with a line in the L1. This exchange is quite a bit more work than just copying a line from L2 to L1, which is what an inclusive cache does.<sup id="cite_ref-ispass04_58-1" class="reference"><a href="#cite_note-ispass04-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> </p><p>One advantage of strictly inclusive caches is that when external devices or other processors in a multiprocessor system wish to remove a cache line from the processor, they need only have the processor check the L2 cache. In cache hierarchies which do not enforce inclusion, the L1 cache must be checked as well. As a drawback, there is a correlation between the associativities of L1 and L2 caches: if the L2 cache does not have at least as many ways as all L1 caches together, the effective associativity of the L1 caches is restricted. Another disadvantage of inclusive cache is that whenever there is an eviction in L2 cache, the (possibly) corresponding lines in L1 also have to get evicted in order to maintain inclusiveness. This is quite a bit of work, and would result in a higher L1 miss rate.<sup id="cite_ref-ispass04_58-2" class="reference"><a href="#cite_note-ispass04-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> </p><p>Another advantage of inclusive caches is that the larger cache can use larger cache lines, which reduces the size of the secondary cache tags. (Exclusive caches require both caches to have the same size cache lines, so that cache lines can be swapped on a L1 miss, L2 hit.) If the secondary cache is an order of magnitude larger than the primary, and the cache data is an order of magnitude larger than the cache tags, this tag area saved can be comparable to the incremental area needed to store the L1 cache data in the L2.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Scratchpad_memory">Scratchpad memory</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=37" title="Edit section: Scratchpad memory"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></div> <p><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a> (SPM), also known as scratchpad, scratchpad RAM or local store in computer terminology, is a high-speed internal memory used for temporary storage of calculations, data, and other work in progress. </p> <div class="mw-heading mw-heading3"><h3 id="Example:_the_K8">Example: the K8</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=38" title="Edit section: Example: the K8"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>To illustrate both specialization and multi-level caching, here is the cache hierarchy of the K8 core in the AMD <a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a> CPU.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> </p> <figure class="mw-default-size mw-halign-center" typeof="mw:File/Thumb"><a href="/wiki/File:Cache,hierarchy-example.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/11/Cache%2Chierarchy-example.svg/350px-Cache%2Chierarchy-example.svg.png" decoding="async" width="350" height="233" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/11/Cache%2Chierarchy-example.svg/525px-Cache%2Chierarchy-example.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/11/Cache%2Chierarchy-example.svg/700px-Cache%2Chierarchy-example.svg.png 2x" data-file-width="600" data-file-height="400" /></a><figcaption>Cache hierarchy of the K8 core in the AMD Athlon 64 CPU</figcaption></figure> <p>The K8 has four specialized caches: an instruction cache, an instruction <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a>, a data TLB, and a data cache. Each of these caches is specialized: </p> <ul><li>The instruction cache keeps copies of 64-byte lines of memory, and fetches 16 bytes each cycle. Each byte in this cache is stored in ten bits rather than eight, with the extra bits marking the boundaries of instructions (this is an example of predecoding). The cache has only <a href="/wiki/Parity_bit" title="Parity bit">parity</a> protection rather than <a href="/wiki/Error-correcting_code" class="mw-redirect" title="Error-correcting code">ECC</a>, because parity is smaller and any damaged data can be replaced by fresh data fetched from memory (which always has an up-to-date copy of instructions).</li> <li>The instruction TLB keeps copies of page table entries (PTEs). Each cycle's instruction fetch has its virtual address translated through this TLB into a physical address. Each entry is either four or eight bytes in memory. Because the K8 has a variable page size, each of the TLBs is split into two sections, one to keep PTEs that map 4 KiB pages, and one to keep PTEs that map 4 MiB or 2 MiB pages. The split allows the fully associative match circuitry in each section to be simpler. The operating system maps different sections of the virtual address space with different size PTEs.</li> <li>The data TLB has two copies which keep identical entries. The two copies allow two data accesses per cycle to translate virtual addresses to physical addresses. Like the instruction TLB, this TLB is split into two kinds of entries.</li> <li>The data cache keeps copies of 64-byte lines of memory. It is split into 8 banks (each storing 8 KiB of data), and can fetch two 8-byte data each cycle so long as those data are in different banks. There are two copies of the tags, because each 64-byte line is spread among all eight banks. Each tag copy handles one of the two accesses per cycle.</li></ul> <p>The K8 also has multiple-level caches. There are second-level instruction and data TLBs, which store only PTEs mapping 4 KiB. Both instruction and data caches, and the various TLBs, can fill from the large <b>unified</b> L2 cache. This cache is exclusive to both the L1 instruction and data caches, which means that any 8-byte line can only be in one of the L1 instruction cache, the L1 data cache, or the L2 cache. It is, however, possible for a line in the data cache to have a PTE which is also in one of the TLBs—the operating system is responsible for keeping the TLBs coherent by flushing portions of them when the page tables in memory are updated. </p><p>The K8 also caches information that is never stored in memory—prediction information. These caches are not shown in the above diagram. As is usual for this class of CPU, the K8 has fairly complex <a href="/wiki/Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a>, with tables that help predict whether branches are taken and other tables which predict the targets of branches and jumps. Some of this information is associated with instructions, in both the level 1 instruction cache and the unified secondary cache. </p><p>The K8 uses an interesting trick to store prediction information with instructions in the secondary cache. Lines in the secondary cache are protected from accidental data corruption (e.g. by an <a href="/wiki/Alpha_particle" title="Alpha particle">alpha particle</a> strike) by either <a href="/wiki/Error-correcting_code" class="mw-redirect" title="Error-correcting code">ECC</a> or <a href="/wiki/Parity_(telecommunication)" class="mw-redirect" title="Parity (telecommunication)">parity</a>, depending on whether those lines were evicted from the data or instruction primary caches. Since the parity code takes fewer bits than the ECC code, lines from the instruction cache have a few spare bits. These bits are used to cache branch prediction information associated with those instructions. The net result is that the branch predictor has a larger effective history table, and so has better accuracy. </p> <div class="mw-heading mw-heading3"><h3 id="More_hierarchies">More hierarchies</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=39" title="Edit section: More hierarchies"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Other processors have other kinds of predictors (e.g., the store-to-load bypass predictor in the <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">DEC</a> <a href="/wiki/Alpha_21264" title="Alpha 21264">Alpha 21264</a>), and various specialized predictors are likely to flourish in future processors. </p><p>These predictors are caches in that they store information that is costly to compute. Some of the terminology used when discussing predictors is the same as that for caches (one speaks of a <b>hit</b> in a branch predictor), but predictors are not generally thought of as part of the cache hierarchy. </p><p>The K8 keeps the instruction and data caches <b><a href="/wiki/Cache_coherency" class="mw-redirect" title="Cache coherency">coherent</a></b> in hardware, which means that a store into an instruction closely following the store instruction will change that following instruction. Other processors, like those in the Alpha and MIPS family, have relied on software to keep the instruction cache coherent. Stores are not guaranteed to show up in the instruction stream until a program calls an operating system facility to ensure coherency. </p> <div class="mw-heading mw-heading3"><h3 id="Tag_RAM">Tag RAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=40" title="Edit section: Tag RAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In computer engineering, a <i>tag RAM</i> is used to specify which of the possible memory locations is currently stored in a CPU cache.<sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> For a simple, direct-mapped design fast <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> can be used. Higher <a href="#Associativity">associative caches</a> usually employ <a href="/wiki/Content-addressable_memory" title="Content-addressable memory">content-addressable memory</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Implementation">Implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=41" title="Edit section: Implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cache_algorithms" class="mw-redirect" title="Cache algorithms">Cache algorithms</a></div> <p>Cache <b>reads</b> are the most common CPU operation that takes more than a single cycle. Program execution time tends to be very sensitive to the latency of a level-1 data cache hit. A great deal of design effort, and often power and silicon area are expended making the caches as fast as possible. </p><p>The simplest cache is a virtually indexed direct-mapped cache. The virtual address is calculated with an adder, the relevant portion of the address extracted and used to index an SRAM, which returns the loaded data. The data is byte aligned in a byte shifter, and from there is bypassed to the next operation. There is no need for any tag checking in the inner loop – in fact, the tags need not even be read. Later in the pipeline, but before the load instruction is retired, the tag for the loaded data must be read, and checked against the virtual address to make sure there was a cache hit. On a miss, the cache is updated with the requested cache line and the pipeline is restarted. </p><p>An associative cache is more complicated, because some form of tag must be read to determine which entry of the cache to select. An N-way set-associative level-1 cache usually reads all N possible tags and N data in parallel, and then chooses the data associated with the matching tag. Level-2 caches sometimes save power by reading the tags first, so that only one data element is read from the data SRAM. </p> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Cache,associative-read.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/7e/Cache%2Cassociative-read.svg/350px-Cache%2Cassociative-read.svg.png" decoding="async" width="350" height="250" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/7e/Cache%2Cassociative-read.svg/525px-Cache%2Cassociative-read.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/7e/Cache%2Cassociative-read.svg/700px-Cache%2Cassociative-read.svg.png 2x" data-file-width="744" data-file-height="531" /></a><figcaption>Read path for a 2-way associative cache</figcaption></figure> <p>The adjacent diagram is intended to clarify the manner in which the various fields of the address are used. Address bit 31 is most significant, bit 0 is least significant. The diagram shows the SRAMs, indexing, and <a href="/wiki/Multiplexing" title="Multiplexing">multiplexing</a> for a 4 KiB, 2-way set-associative, virtually indexed and virtually tagged cache with 64 byte (B) lines, a 32-bit read width and 32-bit virtual address. </p><p>Because the cache is 4 KiB and has 64 B lines, there are just 64 lines in the cache, and we read two at a time from a Tag SRAM which has 32 rows, each with a pair of 21 bit tags. Although any function of virtual address bits 31 through 6 could be used to index the tag and data SRAMs, it is simplest to use the least significant bits. </p><p>Similarly, because the cache is 4 KiB and has a 4 B read path, and reads two ways for each access, the Data SRAM is 512 rows by 8 bytes wide. </p><p>A more modern cache might be 16 KiB, 4-way set-associative, virtually indexed, virtually hinted, and physically tagged, with 32 B lines, 32-bit read width and 36-bit physical addresses. The read path recurrence for such a cache looks very similar to the path above. Instead of tags, vhints are read, and matched against a subset of the virtual address. Later on in the pipeline, the virtual address is translated into a physical address by the TLB, and the physical tag is read (just one, as the vhint supplies which way of the cache to read). Finally the physical address is compared to the physical tag to determine if a hit has occurred. </p><p>Some SPARC designs have improved the speed of their L1 caches by a few gate delays by collapsing the virtual address adder into the SRAM decoders. See <a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">sum-addressed decoder</a>. </p> <div class="mw-heading mw-heading3"><h3 id="History_2">History</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=42" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The early history of cache technology is closely tied to the invention and use of virtual memory.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2008)">citation needed</span></a></i>]</sup> Because of scarcity and cost of semi-conductor memories, early mainframe computers in the 1960s used a complex hierarchy of physical memory, mapped onto a flat virtual memory space used by programs. The memory technologies would span semi-conductor, magnetic core, drum and disc. Virtual memory seen and used by programs would be flat and caching would be used to fetch data and instructions into the fastest memory ahead of processor access. Extensive studies were done to optimize the cache sizes. Optimal values were found to depend greatly on the programming language used with Algol needing the smallest and Fortran and Cobol needing the largest cache sizes.<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Disputed_statement" class="mw-redirect" title="Wikipedia:Disputed statement"><span title="This claim has reliable sources with contradicting facts (December 2010)">disputed</span></a> – <a href="/wiki/Talk:CPU_cache#Talk:CPU_cache#Dispute_sequence_of_events_for_paging" title="Talk:CPU cache">discuss</a></i>]</sup> </p><p>In the early days of microcomputer technology, memory access was only slightly slower than <a href="/wiki/Processor_register" title="Processor register">register</a> access. But since the 1980s<sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> the performance gap between processor and memory has been growing. Microprocessors have advanced much faster than memory, especially in terms of their operating <a href="/wiki/Frequency" title="Frequency">frequency</a>, so memory became a performance <a href="/wiki/Von_Neumann_architecture#Von_Neumann_bottleneck" title="Von Neumann architecture">bottleneck</a>. While it was technically possible to have all the main memory as fast as the CPU, a more economically viable path has been taken: use plenty of low-speed memory, but also introduce a small high-speed cache memory to alleviate the performance gap. This provided an order of magnitude more capacity—for the same price—with only a slightly reduced combined performance. </p> <div class="mw-heading mw-heading4"><h4 id="First_TLB_implementations">First TLB implementations</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=43" title="Edit section: First TLB implementations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first documented uses of a TLB were on the <a href="/wiki/GE_645" title="GE 645">GE 645</a><sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/IBM" title="IBM">IBM</a> <a href="/wiki/IBM_System/360_Model_67" title="IBM System/360 Model 67">360/67</a>,<sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup> both of which used an associative memory as a TLB. </p> <div class="mw-heading mw-heading4"><h4 id="First_instruction_cache">First instruction cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=44" title="Edit section: First instruction cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first documented use of an instruction cache was on the <a href="/wiki/CDC_6600" title="CDC 6600">CDC 6600</a>.<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="First_data_cache">First data cache</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=45" title="Edit section: First data cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first documented use of a data cache was on the <a href="/wiki/IBM" title="IBM">IBM</a> System/360 Model 85.<sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="In_68k_microprocessors">In 68k microprocessors</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=46" title="Edit section: In 68k microprocessors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/68010" class="mw-redirect" title="68010">68010</a>, released in 1982, has a "loop mode" which can be considered a tiny and special-case instruction cache that accelerates loops that consist of only two instructions. The <a href="/wiki/68020" class="mw-redirect" title="68020">68020</a>, released in 1984, replaced that with a typical instruction cache of 256 bytes, being the first 68k series processor to feature true on-chip cache memory. </p><p>The <a href="/wiki/68030" class="mw-redirect" title="68030">68030</a>, released in 1987, is basically a 68020 core with an additional 256-byte data cache, an on-chip <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU), a process shrink, and added burst mode for the caches. </p><p>The <a href="/wiki/Motorola_68040" title="Motorola 68040">68040</a>, released in 1990, has split instruction and data caches of four kilobytes each. </p><p>The <a href="/wiki/68060" class="mw-redirect" title="68060">68060</a>, released in 1994, has the following: 8 KiB data cache (four-way associative), 8 KiB instruction cache (four-way associative), 96-byte FIFO instruction buffer, 256-entry branch cache, and 64-entry address translation cache MMU buffer (four-way associative). </p> <div class="mw-heading mw-heading4"><h4 id="In_x86_microprocessors">In x86 microprocessors</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=47" title="Edit section: In x86 microprocessors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Motherboard_Intel_386.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Motherboard_Intel_386.jpg/260px-Motherboard_Intel_386.jpg" decoding="async" width="260" height="174" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Motherboard_Intel_386.jpg/390px-Motherboard_Intel_386.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/d3/Motherboard_Intel_386.jpg/520px-Motherboard_Intel_386.jpg 2x" data-file-width="3753" data-file-height="2515" /></a><figcaption>Example of a motherboard with an <a href="/wiki/I386" title="I386">i386</a> microprocessor (33 MHz), 64 KiB cache (25 ns; 8 chips in the bottom left corner), 2 MiB DRAM (70 ns; 8 <a href="/wiki/SIMM" title="SIMM">SIMMs</a> to the right of the cache), and a cache controller (<a href="/wiki/Austek_Microsystems" title="Austek Microsystems">Austek</a> A38202; to the right of the processor)</figcaption></figure> <p>As the <a href="/wiki/X86" title="X86">x86</a> microprocessors reached clock rates of 20 MHz and above in the <a href="/wiki/Intel_80386" class="mw-redirect" title="Intel 80386">386</a>, small amounts of fast cache memory began to be featured in systems to improve performance. This was because the <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a> used for main memory had significant latency, up to 120 ns, as well as refresh cycles. The cache was constructed from more expensive, but significantly faster, <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> <a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">memory cells</a>, which at the time had latencies around 10–25 ns. The early caches were external to the processor and typically located on the motherboard in the form of eight or nine <a href="/wiki/Dual_in-line_package" title="Dual in-line package">DIP</a> devices placed in sockets to enable the cache as an optional extra or upgrade feature. </p><p>Some versions of the Intel 386 processor could support 16 to 256 KiB of external cache. </p><p>With the <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">486</a> processor, an 8 KiB cache was integrated directly into the CPU die. This cache was termed Level 1 or L1 cache to differentiate it from the slower on-motherboard, or Level 2 (L2) cache. These on-motherboard caches were much larger, with the most common size being 256 KiB. There were some system boards that contained sockets for the Intel 485Turbocache <a href="/wiki/Expansion_card#Daughterboard" title="Expansion card">daughtercard</a> which had either 64 or 128 Kbyte of cache memory.<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup> The popularity of on-motherboard cache continued through the <a href="/wiki/Intel_P5" class="mw-redirect" title="Intel P5">Pentium MMX</a> era but was made obsolete by the introduction of <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> and the growing disparity between bus clock rates and CPU clock rates, which caused on-motherboard cache to be only slightly faster than main memory. </p><p>The next development in cache implementation in the x86 microprocessors began with the <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a>, which brought the secondary cache onto the same package as the microprocessor, clocked at the same frequency as the microprocessor. </p><p>On-motherboard caches enjoyed prolonged popularity thanks to the <a href="/wiki/AMD_K6-2" title="AMD K6-2">AMD K6-2</a> and <a href="/wiki/AMD_K6-III" title="AMD K6-III">AMD K6-III</a> processors that still used <a href="/wiki/Socket_7" title="Socket 7">Socket 7</a>, which was previously used by Intel with on-motherboard caches. K6-III included 256 KiB on-die L2 cache and took advantage of the on-board cache as a third level cache, named L3 (motherboards with up to 2 MiB of on-board cache were produced). After the Socket 7 became obsolete, on-motherboard cache disappeared from the x86 systems. </p><p>The three-level caches were used again first with the introduction of multiple processor cores, where the L3 cache was added to the CPU die. It became common for the total cache sizes to be increasingly larger in newer processor generations, and recently (as of 2011) it is not uncommon to find Level 3 cache sizes of tens of megabytes.<sup id="cite_ref-70" class="reference"><a href="#cite_note-70"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Intel" title="Intel">Intel</a> introduced a Level 4 on-package cache with the <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a>. <i><a href="/wiki/Crystalwell" class="mw-redirect" title="Crystalwell">Crystalwell</a></i><sup id="cite_ref-intel-ark-crystal-well_39-1" class="reference"><a href="#cite_note-intel-ark-crystal-well-39"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> Haswell CPUs, equipped with the <a href="/wiki/GT3e" class="mw-redirect" title="GT3e">GT3e</a> variant of Intel's integrated Iris Pro graphics, effectively feature 128 MiB of embedded DRAM (<a href="/wiki/EDRAM" title="EDRAM">eDRAM</a>) on the same package. This L4 cache is shared dynamically between the on-die GPU and CPU, and serves as a <a href="/wiki/Victim_cache" title="Victim cache">victim cache</a> to the CPU's L3 cache.<sup id="cite_ref-anandtech-i74950hq_40-1" class="reference"><a href="#cite_note-anandtech-i74950hq-40"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="In_ARM_microprocessors">In ARM microprocessors</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=48" title="Edit section: In ARM microprocessors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Apple_M1" title="Apple M1">Apple M1</a> CPU has 128 or 192 KiB instruction L1 cache for each core (important for latency/single-thread performance), depending on core type. This is an unusually large L1 cache for any CPU type (not just for a laptop); the total cache memory size is not unusually large (the total is more important for throughput) for a laptop, and much larger total (e.g. L3 or L4) sizes are available in IBM's mainframes. </p> <div class="mw-heading mw-heading4"><h4 id="Current_research">Current research</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=49" title="Edit section: Current research"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Early cache designs focused entirely on the direct cost of cache and <a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a> and average execution speed. More recent cache designs also consider <a href="/wiki/Low-power_electronics" title="Low-power electronics">energy efficiency</a>, fault tolerance, and other goals.<sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> </p><p>There are several tools available to computer architects to help explore tradeoffs between the cache cycle time, energy, and area; the CACTI cache simulator<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> and the SimpleScalar instruction set simulator are two open-source options. </p> <div class="mw-heading mw-heading3"><h3 id="Multi-ported_cache">Multi-ported cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=50" title="Edit section: Multi-ported cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A multi-ported cache is a cache which can serve more than one request at a time. When accessing a traditional cache we normally use a single memory address, whereas in a multi-ported cache we may request N addresses at a time – where N is the number of ports that connected through the processor and the cache. The benefit of this is that a pipelined processor may access memory from different phases in its pipeline. Another benefit is that it allows the concept of super-scalar processors through different cache levels. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=51" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 30em;"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache (computing)</a></li> <li><a href="/wiki/Cache_algorithms" class="mw-redirect" title="Cache algorithms">Cache algorithms</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Cache_control_instruction" title="Cache control instruction">Cache control instructions</a></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Cache_placement_policies" title="Cache placement policies">Cache placement policies</a></li> <li><a href="/wiki/Cache_prefetching" title="Cache prefetching">Cache prefetching</a></li> <li><a href="/wiki/Dinero_(cache_simulator)" title="Dinero (cache simulator)">Dinero</a> (cache simulator by <a href="/wiki/University_of_Wisconsin_System" title="University of Wisconsin System">University of Wisconsin System</a>)</li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Locality_of_reference" title="Locality of reference">Locality of reference</a></li> <li><a href="/wiki/Memoization" title="Memoization">Memoization</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></li> <li><a href="/wiki/Micro-operation" title="Micro-operation">Micro-operation</a></li> <li><a href="/wiki/No-write_allocation" class="mw-redirect" title="No-write allocation">No-write allocation</a></li> <li><a href="/wiki/Scratchpad_RAM" class="mw-redirect" title="Scratchpad RAM">Scratchpad RAM</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=52" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text">The very first paging machine, the <a href="/wiki/Ferranti" title="Ferranti">Ferranti</a> <a href="/wiki/Atlas_Computer_(Manchester)" class="mw-redirect" title="Atlas Computer (Manchester)">Atlas</a><sup id="cite_ref-AtlasCPU_29-0" class="reference"><a href="#cite_note-AtlasCPU-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AtlasSup_30-0" class="reference"><a href="#cite_note-AtlasSup-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> had no page tables in main memory; there was an associative memory with one entry for every 512 word page frame of core.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=53" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFTorres2007" class="citation web cs1">Torres, Gabriel (September 12, 2007). <a rel="nofollow" class="external text" href="https://hardwaresecrets.com/how-the-cache-memory-works/">"How The Cache Memory Works"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=How+The+Cache+Memory+Works&rft.date=2007-09-12&rft.aulast=Torres&rft.aufirst=Gabriel&rft_id=https%3A%2F%2Fhardwaresecrets.com%2Fhow-the-cache-memory-works%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPU+cache" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSuZeng2021" class="citation journal cs1">Su, Chao; Zeng, Qingkai (2021-06-10). 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Retrieved <span class="nowrap">2023-01-29</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=HP+Labs&rft.atitle=CACTI&rft_id=https%3A%2F%2Fwww.hpl.hp.com%2Fresearch%2Fcacti%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACPU+cache" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CPU_cache&action=edit&section=54" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output .side-box-abovebelow,.mw-parser-output .side-box-text{padding:0.25em 0.9em}.mw-parser-output .side-box-image{padding:2px 0 2px 0.9em;text-align:center}.mw-parser-output .side-box-imageright{padding:2px 0.9em 2px 0;text-align:center}@media(min-width:500px){.mw-parser-output .side-box-flex{display:flex;align-items:center}.mw-parser-output .side-box-text{flex:1;min-width:0}}@media(min-width:720px){.mw-parser-output .side-box{width:238px}.mw-parser-output .side-box-right{clear:right;float:right;margin-left:1em}.mw-parser-output .side-box-left{margin-right:1em}}</style><style data-mw-deduplicate="TemplateStyles:r1237033735">@media print{body.ns-0 .mw-parser-output .sistersitebox{display:none!important}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}</style><div class="side-box side-box-right plainlinks sistersitebox"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style> <div class="side-box-flex"> <div class="side-box-image"><span class="noviewer" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/40px-Wikibooks-logo-en-noslogan.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/60px-Wikibooks-logo-en-noslogan.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/80px-Wikibooks-logo-en-noslogan.svg.png 2x" data-file-width="400" data-file-height="400" /></span></span></div> <div class="side-box-text plainlist">The Wikibook <i><a href="https://en.wikibooks.org/wiki/Microprocessor_Design" class="extiw" title="wikibooks:Microprocessor Design">Microprocessor Design</a></i> has a page on the topic of: <i><b><a href="https://en.wikibooks.org/wiki/Microprocessor_Design/Cache" class="extiw" title="wikibooks:Microprocessor Design/Cache">Cache</a></b></i></div></div> </div> <ul><li><a rel="nofollow" class="external text" href="https://lwn.net/Articles/252125/">Memory part 2: CPU caches</a> – an article on lwn.net by Ulrich Drepper describing CPU caches in detail</li> <li><a rel="nofollow" class="external text" href="https://minds.wisconsin.edu/bitstream/handle/1793/59076/TR823.pdf">Evaluating Associativity in CPU Caches</a> – Hill and Smith (1989) – introduces capacity, conflict, and compulsory classification</li> <li><a rel="nofollow" class="external text" href="http://www.cs.wisc.edu/multifacet/misc/spec2000cache-data/">Cache Performance for SPEC CPU2000 Benchmarks</a> – Hill and Cantin (2003) – This reference paper has been updated several times. It has thorough and lucidly presented simulation results for a reasonably wide set of benchmarks and cache organizations.</li> <li><a rel="nofollow" class="external text" href="http://www.sun.com/blueprints/1102/817-0742.pdf">Memory Hierarchy in Cache-Based Systems</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20090915041601/http://www.sun.com/blueprints/1102/817-0742.pdf">Archived</a> 2009-09-15 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> – by Ruud van der Pas, 2002, Sun Microsystems – introductory article to CPU memory caching</li> <li><a rel="nofollow" class="external text" href="https://www.nxp.com/docs/en/application-note/AN2663.pdf">A Cache Primer</a> – by Paul Genua, P.E., 2004, Freescale Semiconductor, another introductory article</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110718154522/http://www.zipcores.com/skin1/zipdocs/datasheets/cache_8way_set.pdf">An 8-way set-associative cache</a> – written in <a href="/wiki/VHDL" title="VHDL">VHDL</a></li> <li><a rel="nofollow" class="external text" href="https://arstechnica.com/old/content/2002/07/caching.ars">Understanding CPU caching and performance</a> – an article on Ars Technica by Jon Stokes</li> <li><a rel="nofollow" class="external text" href="http://ixbtlabs.com/articles/ibmpower4/">IBM POWER4 processor review</a> – an article on ixbtlabs by Pavel Danilov</li> <li><a rel="nofollow" class="external text" href="https://www.kivabe.in/2020/07/Cache-memory-ki.html/">What is Cache Memory and its Types!</a></li> <li><a rel="nofollow" class="external text" href="https://www.cs.princeton.edu/courses/archive/fall15/cos375/lectures/16-Cache-2x2.pdf">Memory Caching</a> – a Princeton University lecture</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist 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.navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a class="mw-selflink selflink">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of 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