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</div> </a> <ul id="toc-Design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Versions" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Versions"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Versions</span> </div> </a> <button aria-controls="toc-Versions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Versions subsection</span> </button> <ul id="toc-Versions-sublist" class="vector-toc-list"> <li id="toc-MIPS_I" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS_I"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>MIPS I</span> </div> </a> <ul id="toc-MIPS_I-sublist" class="vector-toc-list"> <li id="toc-Registers" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Registers"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.1</span> <span>Registers</span> </div> </a> <ul id="toc-Registers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_formats" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Instruction_formats"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.2</span> <span>Instruction formats</span> </div> </a> <ul id="toc-Instruction_formats-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-CPU_instructions" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#CPU_instructions"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.3</span> <span>CPU instructions</span> </div> </a> <ul id="toc-CPU_instructions-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-MIPS_II" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS_II"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>MIPS II</span> </div> </a> <ul id="toc-MIPS_II-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MIPS_III" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS_III"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>MIPS III</span> </div> </a> <ul id="toc-MIPS_III-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MIPS_IV" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS_IV"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>MIPS IV</span> </div> </a> <ul id="toc-MIPS_IV-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MIPS_V" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS_V"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>MIPS V</span> </div> </a> <ul id="toc-MIPS_V-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-MIPS32/MIPS64" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#MIPS32/MIPS64"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>MIPS32/MIPS64</span> </div> </a> <ul id="toc-MIPS32/MIPS64-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-microMIPS" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#microMIPS"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7</span> <span>microMIPS</span> </div> </a> <ul id="toc-microMIPS-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Application-specific_extensions" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Application-specific_extensions"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Application-specific extensions</span> </div> </a> <ul id="toc-Application-specific_extensions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Calling_conventions" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Calling_conventions"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Calling conventions</span> </div> </a> <ul id="toc-Calling_conventions-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Uses" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Uses"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Uses</span> </div> </a> <ul id="toc-Uses-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Simulators" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Simulators"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Simulators</span> </div> </a> <ul id="toc-Simulators-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label 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Available in 31 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-31" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">31 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B9%D9%85%D8%A7%D8%B1%D9%8A%D8%A9_%D9%85%D9%8A%D8%A8%D8%B3" title="معمارية ميبس – Arabic" lang="ar" hreflang="ar" data-title="معمارية ميبس" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Arquitectura_MIPS" title="Arquitectura MIPS – Catalan" lang="ca" hreflang="ca" data-title="Arquitectura MIPS" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cv mw-list-item"><a href="https://cv.wikipedia.org/wiki/MIPS" title="MIPS – Chuvash" lang="cv" hreflang="cv" data-title="MIPS" data-language-autonym="Чӑвашла" data-language-local-name="Chuvash" class="interlanguage-link-target"><span>Чӑвашла</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/MIPS_(architektura)" title="MIPS (architektura) – Czech" lang="cs" hreflang="cs" data-title="MIPS (architektura)" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/MIPS_(processorarkitektur)" title="MIPS (processorarkitektur) – Danish" lang="da" hreflang="da" data-title="MIPS (processorarkitektur)" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/MIPS-Architektur" title="MIPS-Architektur – German" lang="de" hreflang="de" data-title="MIPS-Architektur" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/MIPS-arhitektuur" title="MIPS-arhitektuur – Estonian" lang="et" hreflang="et" data-title="MIPS-arhitektuur" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/MIPS_(procesador)" title="MIPS (procesador) – Spanish" lang="es" hreflang="es" data-title="MIPS (procesador)" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%85%D8%B9%D9%85%D8%A7%D8%B1%DB%8C_%D9%85%DB%8C%D9%BE%D8%B3" title="معماری میپس – Persian" lang="fa" hreflang="fa" data-title="معماری میپس" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Architecture_MIPS" title="Architecture MIPS – French" lang="fr" hreflang="fr" data-title="Architecture MIPS" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/MIPS_%EC%95%84%ED%82%A4%ED%85%8D%EC%B2%98" title="MIPS 아키텍처 – Korean" lang="ko" hreflang="ko" data-title="MIPS 아키텍처" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Arsitektur_MIPS" title="Arsitektur MIPS – Indonesian" lang="id" hreflang="id" data-title="Arsitektur MIPS" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Architettura_MIPS" title="Architettura MIPS – Italian" lang="it" hreflang="it" data-title="Architettura MIPS" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%90%D7%A8%D7%9B%D7%99%D7%98%D7%A7%D7%98%D7%95%D7%A8%D7%AA_MIPS" title="ארכיטקטורת MIPS – Hebrew" lang="he" hreflang="he" data-title="ארכיטקטורת MIPS" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/MIPS_arhitekt%C5%ABra" title="MIPS arhitektūra – Latvian" lang="lv" hreflang="lv" data-title="MIPS arhitektūra" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target"><span>Latviešu</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/MIPS-architekt%C3%BAra" title="MIPS-architektúra – Hungarian" lang="hu" hreflang="hu" data-title="MIPS-architektúra" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/MIPS_(CPU)" title="MIPS (CPU) – Dutch" lang="nl" hreflang="nl" data-title="MIPS (CPU)" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/MIPS%E3%82%A2%E3%83%BC%E3%82%AD%E3%83%86%E3%82%AF%E3%83%81%E3%83%A3" title="MIPSアーキテクチャ – Japanese" lang="ja" hreflang="ja" data-title="MIPSアーキテクチャ" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/MIPS_(RISC-arkitektur)" title="MIPS (RISC-arkitektur) – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="MIPS (RISC-arkitektur)" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Architektura_MIPS" title="Architektura MIPS – Polish" lang="pl" hreflang="pl" data-title="Architektura MIPS" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Arquitetura_MIPS" title="Arquitetura MIPS – Portuguese" lang="pt" hreflang="pt" data-title="Arquitetura MIPS" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Arhitectur%C4%83_MIPS" title="Arhitectură MIPS – Romanian" lang="ro" hreflang="ro" data-title="Arhitectură MIPS" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/MIPS_(%D0%B0%D1%80%D1%85%D0%B8%D1%82%D0%B5%D0%BA%D1%82%D1%83%D1%80%D0%B0)" title="MIPS (архитектура) – Russian" lang="ru" hreflang="ru" data-title="MIPS (архитектура)" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/MIPS_architecture" title="MIPS architecture – Simple English" lang="en-simple" hreflang="en-simple" data-title="MIPS architecture" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/MIPS-arkkitehtuuri" title="MIPS-arkkitehtuuri – Finnish" lang="fi" hreflang="fi" data-title="MIPS-arkkitehtuuri" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/MIPS_(processorarkitektur)" title="MIPS (processorarkitektur) – Swedish" lang="sv" hreflang="sv" data-title="MIPS (processorarkitektur)" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/MIPS_mimarisi" title="MIPS mimarisi – Turkish" lang="tr" hreflang="tr" data-title="MIPS mimarisi" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/MIPS" title="MIPS – Ukrainian" lang="uk" hreflang="uk" data-title="MIPS" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/MIPS" title="MIPS – Vietnamese" lang="vi" hreflang="vi" data-title="MIPS" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/MIPS%E6%9E%B6%E6%9E%84" title="MIPS架构 – Wu" lang="wuu" hreflang="wuu" data-title="MIPS架构" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/MIPS%E6%9E%B6%E6%A7%8B" title="MIPS架構 – Chinese" lang="zh" hreflang="zh" data-title="MIPS架構" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q527464#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li 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.infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">MIPS</caption><tbody><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data"><a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>, <a href="/wiki/Imagination_Technologies" title="Imagination Technologies">Imagination Technologies</a></td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data"><a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64-bit</a> (32 → 64)</td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">1985<span class="noprint">; 39 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">1985</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Version</th><td class="infobox-data">MIPS32/64 Release 6 (2014)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Load%E2%80%93store" class="mw-redirect" title="Load–store">Load–store</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Fixed</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data">Compare and branch, with a 1 instruction delay after the branching condition check</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Endianness" title="Endianness">Endianness</a></th><td class="infobox-data"><a href="/wiki/Bi-endian" class="mw-redirect" title="Bi-endian">Bi</a></td></tr><tr><th scope="row" class="infobox-label">Page size</th><td class="infobox-data">4 KB</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><a href="/wiki/MDMX" title="MDMX">MDMX</a>, <a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Partly. The <a href="/wiki/R10000#R16000" title="R10000">R16000</a> processor has been on the market for more than 20 years and as such cannot be subject to patent claims. Therefore, the R16000 and older processors are fully open.</td></tr><tr><th colspan="2" class="infobox-header"><a href="/wiki/Processor_register" title="Processor register">Registers</a></th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/General-purpose_register" class="mw-redirect" title="General-purpose register">General-purpose</a></th><td class="infobox-data">32</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Floating_point" class="mw-redirect" title="Floating point">Floating point</a></th><td class="infobox-data">32</td></tr></tbody></table> <p><b>MIPS</b> (<b>Microprocessor without Interlocked Pipelined Stages</b>)<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> is a family of <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architectures</a> (ISA)<sup id="cite_ref-Price1995_2-0" class="reference"><a href="#cite_note-Price1995-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: A-1">: A-1 </span></sup><sup id="cite_ref-Sweetman1999_3-0" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 19">: 19 </span></sup> developed by MIPS Computer Systems, now <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>, based in the <a href="/wiki/United_States" title="United States">United States</a>. </p><p>There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. </p><p>The MIPS architecture has several optional extensions: <a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a>, a simple set of <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> <a href="/wiki/Instruction_set_architecture#SIMD_instruction" title="Instruction set architecture">SIMD instructions</a> dedicated to common 3D tasks;<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> <a href="/wiki/MDMX" title="MDMX">MDMX</a> (MaDMaX), a more extensive integer <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> instruction set using 64-bit floating-point registers; MIPS16e, which adds <a href="/wiki/Compressed_instructions" class="mw-redirect" title="Compressed instructions">compression to the instruction stream</a> to reduce the space programs take up;<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> and MIPS MT, which adds <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multithreading</a> capability.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a> courses in universities and technical schools often study the MIPS architecture.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> The architecture greatly influenced later RISC architectures such as <a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a>. In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company is making the transition to <a href="/wiki/RISC-V" title="RISC-V">RISC-V</a>.<sup id="cite_ref-mips-becomes-risc-v_10-0" class="reference"><a href="#cite_note-mips-becomes-risc-v-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=MIPS_architecture&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">February 2020</span>)</i></span></div></td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a></div> <p>The first version of the MIPS architecture was designed by <a href="/wiki/MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a> for its <a href="/wiki/R2000_(microprocessor)" class="mw-redirect" title="R2000 (microprocessor)">R2000</a> microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability"><span title="The material near this tag failed verification of its source citation(s). (May 2023)">failed verification</span></a></i>]</sup> When MIPS II was introduced, <i>MIPS</i> was renamed <i>MIPS I</i> to distinguish it from the new version.<sup id="cite_ref-Sweetman1999_3-1" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 32">: 32 </span></sup> </p><p><a href="/wiki/MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a>' <a href="/wiki/R6000" title="R6000">R6000</a> microprocessor (1989) was the first MIPS II implementation.<sup id="cite_ref-Sweetman1999_3-2" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 8">: 8 </span></sup> Designed for servers, the R6000 was fabricated and sold by <a href="/wiki/Bipolar_Integrated_Technology" title="Bipolar Integrated Technology">Bipolar Integrated Technology</a>, but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a> were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32 was introduced in 1999.<sup id="cite_ref-Sweetman1999_3-3" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 19">: 19 </span></sup> </p><p><a href="/wiki/MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a>' <a href="/wiki/R4000" title="R4000">R4000</a> microprocessor (1991) was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer Systems aggressively promoted the MIPS architecture and R4000, establishing the <a href="/wiki/Advanced_Computing_Environment" title="Advanced Computing Environment">Advanced Computing Environment</a> (ACE) consortium to advance its <a href="/wiki/Advanced_RISC_Computing" class="mw-redirect" title="Advanced RISC Computing">Advanced RISC Computing</a> (ARC) standard, which aimed to establish MIPS as the dominant personal computing platform. ARC found little success in personal computers, but the R4000 (and the R4400 derivative) were widely used in workstation and server computers, especially by its largest user, <a href="/wiki/Silicon_Graphics" title="Silicon Graphics">Silicon Graphics</a>. Other uses of the R4000 included high-end embedded systems and supercomputers. MIPS III was eventually implemented by a number of embedded microprocessors. <a href="/wiki/Quantum_Effect_Design" class="mw-redirect" title="Quantum Effect Design">Quantum Effect Design</a>'s <a href="/wiki/R4600" title="R4600">R4600</a> (1993) and its derivatives was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies' <a href="/wiki/R4200" title="R4200">R4200</a> (1994), was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by <a href="/wiki/NEC_Electronics" class="mw-redirect" title="NEC Electronics">NEC Electronics</a>, was used in the <a href="/wiki/Nintendo_64" title="Nintendo 64">Nintendo 64</a> game console. The Nintendo 64, along with the <a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation</a>, were among the highest volume users of MIPS architecture processors in the mid-1990s. </p><p>The first MIPS IV implementation was the MIPS Technologies <a href="/wiki/R8000" title="R8000">R8000</a> microprocessor chipset (1994). The design of the R8000 began at Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS Technologies <a href="/wiki/R10000" title="R10000">R10000</a> (1996) and the Quantum Effect Devices <a href="/wiki/R5000" title="R5000">R5000</a> (1996) and <a href="/w/index.php?title=RM7000&action=edit&redlink=1" class="new" title="RM7000 (page does not exist)">RM7000</a> (1998). The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, and Tandem Computers (among others) in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of the R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's <a href="/wiki/Emotion_Engine" title="Emotion Engine">Emotion Engine</a>, which powered its <a href="/wiki/PlayStation_2" title="PlayStation 2">PlayStation 2</a> game console. </p><p>Announced on October 21, 1996, at the Microprocessor Forum 1996 alongside the <a href="/wiki/MDMX" title="MDMX">MIPS Digital Media Extensions</a> (MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications.<sup id="cite_ref-MPR:1996-11-18_13-0" class="reference"><a href="#cite_note-MPR:1996-11-18-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999) was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single. </p><p>When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem,<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (June 2016)">citation needed</span></a></i>]</sup> and the architecture definition was changed to define a 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999.<sup id="cite_ref-mips32-and-mips64_15-0" class="reference"><a href="#cite_note-mips32-and-mips64-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V.<sup id="cite_ref-mips32-and-mips64_15-1" class="reference"><a href="#cite_note-mips32-and-mips64-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Nippon_Electric_Corporation" class="mw-redirect" title="Nippon Electric Corporation">NEC</a>, <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> and <a href="/wiki/SiByte" class="mw-redirect" title="SiByte">SiByte</a> (later acquired by <a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a>) each obtained licenses for MIPS64 as soon as it was announced. <a href="/wiki/Philips" title="Philips">Philips</a>, <a href="/wiki/LSI_Corporation" title="LSI Corporation">LSI Logic</a>, <a href="/wiki/Integrated_Device_Technology" title="Integrated Device Technology">IDT</a>, <a href="/wiki/RMI_Corporation" title="RMI Corporation">Raza Microelectronics, Inc.</a>, <a href="/wiki/Cavium" title="Cavium">Cavium</a>, <a href="/wiki/Loongson" title="Loongson">Loongson Technology</a> and <a href="/wiki/Ingenic_Semiconductor" title="Ingenic Semiconductor">Ingenic Semiconductor</a> have since joined them. MIPS32/MIPS64 Release 5 was announced on December 6, 2012.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as <a href="/wiki/Tetraphobia" title="Tetraphobia">unlucky</a> in many Asian cultures.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p><p><span class="anchor" id="Open"></span>In December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> The program was intended to open up access to the most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p><p>In March 2019, one version of the architecture was made available under a royalty-free license,<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> but later that year the program was shut down again.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> </p><p>In March 2021, Wave Computing announced that the development of the MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture.<sup id="cite_ref-mips-becomes-risc-v_10-1" class="reference"><a href="#cite_note-mips-becomes-risc-v-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> In spite of this, some licensees such as <a href="/wiki/Loongson" title="Loongson">Loongson</a> continue with new extension of MIPS-compatible ISAs on their own.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>In January 2024, Loongson won a case over rights to use MIPS architecture.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Design">Design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=2" title="Edit section: Design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=MIPS_architecture&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">February 2020</span>)</i></span></div></td></tr></tbody></table> <p>MIPS is a modular architecture supporting up to four <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a> (CP0/1/2/3). In MIPS terminology, CP0 is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), CP1 is an optional <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU) and CP2/3 are optional implementation-defined coprocessors (MIPS III removed CP3 and reused its opcodes for other purposes). For example, in the <a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation</a> video game console, CP2 is the <a href="/wiki/PlayStation_technical_specifications#Central_processing_unit_(CPU)" title="PlayStation technical specifications">Geometry Transformation Engine</a> (GTE), which accelerates the processing of geometry in 3D computer graphics. </p> <div class="mw-heading mw-heading2"><h2 id="Versions">Versions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=3" title="Edit section: Versions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="MIPS_I">MIPS I</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=4" title="Edit section: MIPS I"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS is a <a href="/wiki/Load/store_architecture" class="mw-redirect" title="Load/store architecture">load/store architecture</a> (also known as a <i>register-register architecture</i>); except for the <a href="/wiki/Load/store_instructions" class="mw-redirect" title="Load/store instructions">load/store instructions</a> used to access <a href="/wiki/Computer_memory" title="Computer memory">memory</a>, all instructions operate on the registers. </p> <div class="mw-heading mw-heading4"><h4 id="Registers">Registers</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=5" title="Edit section: Registers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register <style data-mw-deduplicate="TemplateStyles:r886049734">.mw-parser-output .monospaced{font-family:monospace,monospace}</style><span class="monospaced">$0</span> is hardwired to zero and writes to it are discarded. Register <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$31</span> is the <a href="/wiki/Link_register" title="Link register">link register</a>. For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, <i>HI</i> and <i>LO</i>, are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers. </p><p>The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries. </p> <div class="mw-heading mw-heading4"><h4 id="Instruction_formats">Instruction formats</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=6" title="Edit section: Instruction formats"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers,<sup id="cite_ref-Harris_Harris_2013_pp._294–369_27-0" class="reference"><a href="#cite_note-Harris_Harris_2013_pp._294–369-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.<sup id="cite_ref-Price1995_2-1" class="reference"><a href="#cite_note-Price1995-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: A-174">: A-174 </span></sup> </p><p>The following are the three formats used for the core instruction set: </p> <table class="wikitable"> <tbody><tr> <th>Type</th> <th colspan="6">-31-                                 format (bits)                                 -0- </th></tr> <tr align="center"> <td><b>R</b></td> <td>opcode (6)</td> <td>rs (5)</td> <td>rt (5)</td> <td>rd (5)</td> <td>shamt (5)</td> <td>funct (6) </td></tr> <tr align="center"> <td><b>I</b></td> <td>opcode (6)</td> <td>rs (5)</td> <td>rt (5)</td> <td colspan="3">immediate (16) </td></tr> <tr align="center"> <td><b>J</b></td> <td>opcode (6)</td> <td colspan="5">address (26) </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="CPU_instructions">CPU instructions</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=7" title="Edit section: CPU instructions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one <a href="/wiki/Addressing_mode" title="Addressing mode">addressing mode</a> is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load instructions source the base from the contents of a GPR (rs) and write the result to another GPR (rt). Store instructions source the base from the contents of a GPR (rs) and the store data from another GPR (rt). All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by a <a href="/wiki/Load_delay_slot" class="mw-redirect" title="Load delay slot">load delay slot</a>. The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a nop is substituted if such an instruction cannot be found. </p><p>MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs (rs and rt), and write the result to a third GPR (rd). Alternatively, addition can source one of the operands from a 16-bit immediate (which is sign-extended to 32 bits). The instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer. MIPS I has instructions to perform <a href="/wiki/Bitwise_operation" title="Bitwise operation">bitwise</a> logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write the result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate (which is zero-extended to 32 bits). The Set on <i>relation</i> instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate (which is sign-extended to 32 bits), and write the result to a third GPR. By default, the operands are interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers (even those that source an operand from the sign-extended 16-bit immediate). </p><p>The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with the Or Immediate instruction to load a 32-bit immediate into a register. </p><p>MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field). </p><p>MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to a pair of 32-bit registers called HI and LO, since they may execute separately from (and concurrently with) the other CPU instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO (respectively). For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions (Move from HI and Move from LO) is provided to copy the contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions (Move to HI or Move to LO) copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO. </p><p>All MIPS I control flow instructions are followed by a <a href="/wiki/Branch_delay_slot" class="mw-redirect" title="Branch delay slot">branch delay slot</a>. Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. MIPS I branch instructions compare the contents of a GPR (rs) against zero or another GPR (rt) as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding the 32-bit sign-extended result to the sum of the program counter (instruction address) and 8<sub>10</sub>. Jumps have two versions: absolute and register-indirect. Absolute jumps ("Jump" and "Jump and Link") compute the address to which control is transferred by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in the branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR (rs). The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link (except for "Jump and Link Register") save the return address to GPR 31. The "Jump and Link Register" instruction permits the return address to be saved to any writable GPR. </p><p>MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for the exception handler. </p><p>MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were not affected). </p><p>Single precision is denoted by the .s suffix, while double precision is denoted by the .d suffix. </p> <div class="mw-heading mw-heading3"><h3 id="MIPS_II">MIPS II</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=8" title="Edit section: MIPS II"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS II removed the load delay slot<sup id="cite_ref-Sweetman1999_3-4" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 41">: 41 </span></sup> and added several sets of instructions. For shared-memory multiprocessing, the <i>Synchronize Shared Memory</i>, <i>Load Linked Word</i>, and <i>Store Conditional Word</i> instructions were added.<sup id="cite_ref-mips-ll-sc_28-0" class="reference"><a href="#cite_note-mips-ll-sc-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given <i>branch-likely</i> versions that executed the instruction in the branch delay slot only if the branch is taken.<sup id="cite_ref-Sweetman1999_3-5" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 40">: 40 </span></sup> These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot.<sup id="cite_ref-Sweetman1999_3-6" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 212">: 212 </span></sup> Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned. </p><p>The instruction set for the floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by the instruction instead of the Floating Point Control and Status Register. </p> <div class="mw-heading mw-heading3"><h3 id="MIPS_III">MIPS III</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=9" title="Edit section: MIPS III"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS III is a <a href="/wiki/Backwards-compatible" class="mw-redirect" title="Backwards-compatible">backwards-compatible</a> extension of MIPS II that added support for <a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64-bit</a> memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between the GPRs and HI/LO registers. For shared-memory multiprocessing, the <i>Load Linked Double Word</i>, and <i>Store Conditional Double Word</i> instructions were added.<sup id="cite_ref-mips-ll-sc_28-1" class="reference"><a href="#cite_note-mips-ll-sc-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined was <i>Load Word</i>. In MIPS III it sign-extends words to 64 bits. To complement <i>Load Word</i>, a version that zero-extends was added. </p><p>The R instruction format's inability to specify the full shift distance for 64-bit shifts (its 5-bit shift amount field is too narrow to specify the shift distance for doublewords) required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version is a 64-bit version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 32<sub>10</sub> the shift amount field's value so that constant shift distances of 32–63 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR. </p><p>MIPS III added a <i>supervisor</i> privilege level in between the existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor (Coprocessor 0). </p><p>MIPS III removed the Coprocessor 3 (CP3) support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers (FGRs) were extended to 64 bits and the requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between the CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa. </p> <div class="mw-heading mw-heading3"><h3 id="MIPS_IV">MIPS IV</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=10" title="Edit section: MIPS IV"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page: A-1">: A-1 </span></sup> MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed <a href="/wiki/Addressing_mode" title="Addressing mode">addressing mode</a> (base + index, both sourced from GPRs) for FP loads and stores was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes). </p><p>MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing the total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for <a href="/wiki/Branch_predication" class="mw-redirect" title="Branch predication">partial predication</a> was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps. </p><p>MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it is implementation-defined), to exceed or meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy. </p> <div class="mw-heading mw-heading3"><h3 id="MIPS_V">MIPS V</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=11" title="Edit section: MIPS V"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS V added a new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data.<sup id="cite_ref-Sweetman1999_3-7" class="reference"><a href="#cite_note-Sweetman1999-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup class="reference nowrap"><span title="Page / location: 426–429">: 426–429 </span></sup> It was the first instruction set to exploit floating-point SIMD with existing resources.<sup id="cite_ref-MPR:1996-11-18_13-1" class="reference"><a href="#cite_note-MPR:1996-11-18-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="MIPS32/MIPS64"><span id="MIPS32.2FMIPS64"></span>MIPS32/MIPS64</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=12" title="Edit section: MIPS32/MIPS64"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The first release of MIPS32, based on MIPS II, added conditional moves, <a href="/wiki/Instruction_prefetch" class="mw-redirect" title="Instruction prefetch">prefetch instructions</a>, and other features from the R4000 and R5000 families of 64-bit processors.<sup id="cite_ref-mips32-and-mips64_15-2" class="reference"><a href="#cite_note-mips32-and-mips64-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The first release of MIPS64 adds a MIPS32 mode to run 32-bit code.<sup id="cite_ref-mips32-and-mips64_15-3" class="reference"><a href="#cite_note-mips32-and-mips64-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The MUL and MADD (<a href="/wiki/Multiply-add" class="mw-redirect" title="Multiply-add">multiply-add</a>) instructions, previously available in some implementations, were added to the MIPS32 and MIPS64 specifications, as were <a href="/wiki/Cache_control_instruction" title="Cache control instruction">cache control instructions</a>.<sup id="cite_ref-mips32-and-mips64_15-4" class="reference"><a href="#cite_note-mips32-and-mips64-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> For the purpose of cache control, both <code>SYNC</code> and <code>SYNCI</code> instructions were prepared.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p>MIPS32/MIPS64 Release 6 in 2014 added the following:<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p> <ul><li>a new family of branches with no delay slot: <ul><li>unconditional branches (BC) and branch-and-link (BALC) with a 26-bit offset,</li> <li>conditional branch on zero/non-zero with a 21-bit offset,</li> <li>full set of signed and unsigned conditional branches compare between two registers (e.g. BGTUC) or a register against zero (e.g. BGTZC),</li> <li>full set of branch-and-link which compare a register against zero (e.g. BGTZALC).</li></ul></li> <li>index jump instructions with no delay slot designed to support large absolute addresses.</li> <li>instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.</li> <li>PC-relative load instructions, as well as address generation with large (PC-relative) offsets.</li> <li>bit-reversal and byte-alignment instructions (previously only available with the DSP extension).</li> <li>multiply and divide instructions redefined so that they use a single register for their result).</li> <li>instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,</li> <li>instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.</li></ul> <p>Removed infrequently used instructions: </p> <ul><li>some conditional moves</li> <li><i>branch likely</i> instructions (deprecated in previous releases).</li> <li>integer overflow trapping instructions with 16-bit immediate</li> <li>integer accumulator instructions (together HI/LO registers, moved to the DSP Application-Specific Extension)</li> <li>unaligned load instructions (LWL and LWR), (requiring that most ordinary loads and stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))</li></ul> <p>Reorganized the instruction encoding, freeing space for future expansions. </p> <div class="mw-heading mw-heading3"><h3 id="microMIPS">microMIPS</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=13" title="Edit section: microMIPS"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace the MIPS16e ASE. A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has a corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS. </p> <div class="mw-heading mw-heading2"><h2 id="Application-specific_extensions">Application-specific extensions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=14" title="Edit section: Application-specific extensions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as <i>application-specific extensions</i> (ASEs). These ASEs provide features that improve the efficiency and performance of certain workloads, such as <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a>. </p> <dl><dt>MIPS MCU</dt> <dd>Enhancements for microcontroller applications. The MCU ASE (application-specific extension) has been developed to extend the <a href="/wiki/Interrupt" title="Interrupt">interrupt</a> controller support, reduce the interrupt latency and enhance the I/O peripheral control function typically required in microcontroller system designs.</dd></dl> <ul><li>Separate priority and vector generation</li> <li>Supports up to 256 interrupts in EIC (External Interrupt Controller) mode and eight hardware interrupt pins</li> <li>Provides 16-bit vector offset address</li> <li>Pre-fetching of the interrupt exception vector</li> <li>Automated Interrupt Prologue – adds hardware to save and update system status before the interrupt handling routine</li> <li>Automated Interrupt Epilogue – restores the system state previously stored in the stack for returning from the interrupt.</li> <li>Interrupt Chaining – supports the service of pending interrupts without the need to exit the initial interrupt routine, saving the cycles required to store and restore multiple active interrupts</li> <li>Supports speculative pre-fetching of the interrupt vector address. Reduces the number of interrupt service cycles by overlapping memory accesses with pipeline flushes and exception prioritization</li> <li>Includes atomic bit set/clear instructions which enables bits within an I/O register that are normally used to monitor or control external peripheral functions to be modified without interruption, ensuring the action is performed securely.</li></ul> <dl><dt>MIPS16</dt> <dd>MIPS16 is an Application-Specific Extension for MIPS I through to V designed by <a href="/wiki/LSI_Logic" class="mw-redirect" title="LSI Logic">LSI Logic</a> and <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>, announced on October 21, 1996, alongside its first implementation, the LSI Logic TinyRISC processor.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> MIPS16 was subsequently licensed by <a href="/wiki/NEC_Electronics" class="mw-redirect" title="NEC Electronics">NEC Electronics</a>, <a href="/wiki/Philips_Semiconductors" class="mw-redirect" title="Philips Semiconductors">Philips Semiconductors</a>, and <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> (among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> It is supported by hardware and software development tools from MIPS Technologies and other providers. MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1. MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.</dd> <dt>MIPS Digital Signal Processing (DSP)</dt> <dd>The DSP ASE is an optional extension to the MIPS32/MIPS64 Release 2 and newer instruction sets which can be used to accelerate a large range of "media" computations—particularly audio and video. The DSP module comprises a set of instructions and state in the integer pipeline and requires minimal additional logic to implement in MIPS processor cores. Revision 2 of the ASE was introduced in the second half of 2006. This revision adds extra instructions to the original ASE, but is otherwise backwards-compatible with it.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for a particular relevance to some key algorithm. Its main novel features (vs original MIPS32):<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup></dd></dl> <ul><li>Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).</li> <li>Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").</li> <li>The existing integer multiplication and multiply-accumulate instructions, which deliver results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.</li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).</li> <li>SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.</li></ul> <dl><dt>MIPS SIMD architecture (MSA)</dt> <dd>Instruction set extensions designed to accelerate multimedia.</dd></dl> <ul><li>32 vector registers of 16 x 8-bit, 8 x 16-bit, 4 x 32-bit, and 2 x 64 bit vector elements</li> <li>Efficient vector parallel arithmetic operations on integer, fixed-point and floating-point data</li> <li>Operations on absolute value operands</li> <li>Rounding and saturation options available</li> <li>Full precision multiply and multiply-add</li> <li>Conversions between integer, floating-point, and fixed-point data</li> <li>Complete set of vector-level compare and branch instructions with no condition flag</li> <li>Vector (1D) and array (2D) shuffle operations</li> <li>Typed load and store instructions for <a href="/wiki/Endianness" title="Endianness">endian</a>-independent operation</li> <li>IEEE Standard for Floating-Point Arithmetic 754-2008 compliant</li> <li>Element precise floating-point exception signaling</li> <li>Pre-defined scalable extensions for chips with more gates/transistors</li> <li>Accelerates compute-intensive applications in conjunction with leveraging generic compiler support</li> <li>Software-programmable solution for consumer electronics applications or functions not covered by dedicated hardware</li> <li>Emerging data mining, feature extraction, image and video processing, and human-computer interaction applications</li> <li>High-performance scientific computing</li></ul> <dl><dt>MIPS virtualization</dt> <dd>Hardware supported virtualization technology.</dd> <dt>MIPS multi-threading</dt> <dd>Each multi-threaded MIPS core can support up to two VPEs (Virtual Processing Elements) which share a single pipeline as well as other hardware resources. However, since each VPE includes a complete copy of the processor state as seen by the software system, each VPE appears as a complete standalone processor to an <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a> Linux operating system. For more fine-grained thread processing applications, each VPE is capable of supporting up to nine TCs allocated across two VPEs. The TCs share a common execution unit but each has its own program counter and core register files so that each can handle a thread from the software. The MIPS MT architecture also allows the allocation of processor cycles to threads, and sets the relative thread priorities with an optional Quality of Service (<a href="/wiki/Quality_of_service" title="Quality of service">QoS</a>) manager block. This enables two prioritization mechanisms that determine the flow of information across the bus. The first mechanism allows the user to prioritize one thread over another. The second mechanism is used to allocate a specified ratio of the cycles to specific threads over time. The combined use of both mechanisms allows effective allocation of bandwidth to the set of threads, and better control of latencies. In real-time systems, system-level determinism is very critical, and the QoS block facilitates improvement of the predictability of a system. Hardware designers of advanced systems may replace the standard QoS block provided by MIPS Technologies with one that is specifically tuned for their application.</dd> <dt>SmartMIPS</dt> <dd>SmartMIPS is an Application-Specific Extension (ASE) designed by <a href="/wiki/Gemplus_International" class="mw-redirect" title="Gemplus International">Gemplus International</a> and MIPS Technologies to improve performance and reduce memory consumption for <a href="/wiki/Smart_card" title="Smart card">smart card</a> software. It is supported by MIPS32 only, since smart cards do not require the capabilities of MIPS64 processors. Few smart cards use SmartMIPS.</dd> <dt><a href="/wiki/MDMX" title="MDMX">MIPS Digital Media eXtension</a> (MDMX)</dt> <dd>Multimedia application accelerations that were common in the 1990s on RISC and CISC systems.</dd> <dt><a href="/wiki/MIPS-3D" title="MIPS-3D">MIPS-3D</a></dt> <dd>Additional instructions for improving the performance of 3D graphics applications</dd></dl> <div class="mw-heading mw-heading2"><h2 id="Calling_conventions">Calling conventions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=15" title="Edit section: Calling conventions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>MIPS has had several calling conventions, especially on the 32-bit platform. </p><p>The O32 ABI is the most commonly-used ABI, owing to its status as the original <a href="/wiki/System_V" class="mw-redirect" title="System V">System V</a> <a href="/wiki/Application_binary_interface" title="Application binary interface">ABI</a> for MIPS.<sup id="cite_ref-Sweetman_37-0" class="reference"><a href="#cite_note-Sweetman-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-O32_38-0" class="reference"><a href="#cite_note-O32-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> It is strictly stack-based, with only four registers <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a0</span>-<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a3</span> available to pass arguments. Space on the stack is reserved in case the callee needs to save its arguments, but the registers are not stored there by the caller. The return value is stored in register <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v0</span>; a second return value may be stored in <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v1</span>. The ABI took shape in 1990 and was last updated in 1994. This perceived slowness, along with an antique floating-point model with only 16 registers, has encouraged the proliferation of many other calling conventions. It is only defined for 32-bit MIPS, but <a href="/wiki/GNU_compiler_collection" class="mw-redirect" title="GNU compiler collection">GCC</a> has created a 64-bit variation called O64.<sup id="cite_ref-linux-mips_39-0" class="reference"><a href="#cite_note-linux-mips-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p><p>For 64-bit, the N64 ABI by Silicon Graphics is most commonly used. The most important improvement is that eight registers are now available for argument passing; it also increases the number of floating-point registers to 32. There is also an <a href="/wiki/ILP32" class="mw-redirect" title="ILP32">ILP32</a> version called N32, which uses 32-bit pointers for smaller code, analogous to the <a href="/wiki/X32_ABI" title="X32 ABI">x32 ABI</a>. Both run under the 64-bit mode of the CPU.<sup id="cite_ref-linux-mips_39-1" class="reference"><a href="#cite_note-linux-mips-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> The N32 and N64 ABIs pass the first eight arguments to a function in the registers <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a0</span>-<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a7</span>; subsequent arguments are passed on the stack. The return value (or a pointer to it) is stored in the registers <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v0</span>; a second return value may be stored in <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v1</span>. In both the N32 and N64 ABIs all registers are considered to be 64-bits wide. </p><p>A few attempts have been made to replace O32 with a 32-bit ABI that resembles N32 more. A 1995 conference came up with MIPS EABI, for which the 32-bit version was quite similar.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> EABI inspired MIPS Technologies to propose a more radical "NUBI" ABI additionally reuse argument registers for the return value.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> MIPS EABI is supported by GCC but not LLVM, and neither supports NUBI. </p><p>For all of O32 and N32/N64, the return address is stored in a <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$ra</span> register. This is automatically set with the use of the JAL (jump and link) or JALR (jump and link register) instructions. The function prologue of a (non-leaf) MIPS subroutine pushes the return address (in <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$ra</span>) to the stack.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> </p><p>On both O32 and N32/N64 the stack grows downwards, but the N32/N64 ABIs require 64-bit alignment for all stack entries. The frame pointer (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$30</span>) is optional and in practice rarely used except when the stack allocation in a function is determined at runtime, for example, by calling <code>alloca()</code>. </p><p>For N32 and N64, the return address is typically stored 8 bytes before the <a href="/wiki/Stack_pointer" class="mw-redirect" title="Stack pointer">stack pointer</a> although this may be optional. </p><p>For the N32 and N64 ABIs, a function must preserve the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s0</span>-<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s7</span> registers, the global pointer (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$gp</span> or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$28</span>), the stack pointer (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$sp</span> or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$29</span>) and the frame pointer (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$30</span>). The O32 ABI is the same except the calling function is required to save the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$gp</span> register instead of the called function. </p><p>For multi-threaded code, the thread local storage pointer is typically stored in special hardware register <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$29</span> and is accessed by using the mfhw (move from hardware) instruction. At least one vendor is known to store this information in the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k0</span> register which is normally reserved for kernel use, but this is not standard. </p><p>The <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k0</span> and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k1</span> registers (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$26</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$27</span>) are reserved for kernel use and should not be used by applications since these registers can be changed at any time by the kernel due to interrupts, context switches or other events. </p> <table class="wikitable"> <caption>Registers for O32 calling convention </caption> <tbody><tr> <th>Name</th> <th>Number</th> <th>Use</th> <th>Callee must preserve? </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$zero</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$0</span></td> <td>constant 0</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$at</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$1</span></td> <td>assembler temporary</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v1</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$2</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$3</span></td> <td>values for function returns and expression evaluation</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a3</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$4</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$7</span></td> <td>function arguments</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t7</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$8</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$15</span></td> <td>temporaries</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s7</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$16</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$23</span></td> <td>saved temporaries</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t8</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t9</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$24</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$25</span></td> <td>temporaries</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k1</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$26</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$27</span></td> <td>reserved for OS kernel</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$gp</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$28</span></td> <td>global pointer</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes (except PIC code) </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$sp</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$29</span></td> <td><a href="/wiki/Stack-based_memory_allocation" title="Stack-based memory allocation">stack pointer</a></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$fp</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$30</span></td> <td><a href="/wiki/Frame_pointer" class="mw-redirect" title="Frame pointer">frame pointer</a></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$ra</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$31</span></td> <td><a href="/wiki/Return_statement" title="Return statement">return address</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr></tbody></table> <table class="wikitable"> <caption>Registers for N32 and N64 calling conventions<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </caption> <tbody><tr> <th>Name</th> <th>Number</th> <th>Use</th> <th>Callee must preserve? </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$zero</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$0</span></td> <td>constant 0</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$at</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$1</span></td> <td>assembler temporary</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$v1</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$2</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$3</span></td> <td>values for function returns and expression evaluation</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$a7</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$4</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$11</span></td> <td>function arguments</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t4</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t7</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$12</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$15</span></td> <td>temporaries</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s7</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$16</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$23</span></td> <td>saved temporaries</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t8</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t9</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$24</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$25</span></td> <td>temporaries</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k0</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$k1</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$26</span>–<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$27</span></td> <td>reserved for OS kernel</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$gp</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$28</span></td> <td>global pointer</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$sp</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$29</span></td> <td><a href="/wiki/Stack-based_memory_allocation" title="Stack-based memory allocation">stack pointer</a></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$s8</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$30</span></td> <td><a href="/wiki/Frame_pointer" class="mw-redirect" title="Frame pointer">frame pointer</a></td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$ra</span> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$31</span></td> <td><a href="/wiki/Return_statement" title="Return statement">return address</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr></tbody></table> <p>Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $s-registers must be saved to the stack by a procedure that needs to use them, and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$sp</span> and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$fp</span> are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$ra</span> is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call). </p><p>The userspace calling convention of position-independent code on Linux additionally requires that when a function is called the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734"><span class="monospaced">$t9</span> register must contain the address of that function.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> This convention dates back to the System V ABI supplement for MIPS.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Uses">Uses</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=16" title="Edit section: Uses"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=MIPS_architecture&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">February 2020</span>)</i></span></div></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Update plainlinks metadata ambox ambox-content ambox-Update" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/42px-Ambox_current_red_Americas.svg.png" decoding="async" width="42" height="34" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/63px-Ambox_current_red_Americas.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/84px-Ambox_current_red_Americas.svg.png 2x" data-file-width="360" data-file-height="290" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">Parts of this article (those related to 2010s) need to be <b>updated</b>.<span class="hide-when-compact"> Please help update this article to reflect recent events or newly available information.</span> <span class="date-container"><i>(<span class="date">August 2020</span>)</i></span></div></td></tr></tbody></table> <p>MIPS processors are used in <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a> such as <a href="/wiki/Residential_gateway" title="Residential gateway">residential gateways</a> and <a href="/wiki/Router_(computing)" title="Router (computing)">routers</a>. Originally, MIPS was designed for general-purpose computing. During the 1980s and 1990s, MIPS processors for <a href="/wiki/Personal_computer" title="Personal computer">personal</a>, <a href="/wiki/Workstation" title="Workstation">workstation</a>, and <a href="/wiki/Server_(computing)" title="Server (computing)">server</a> computers were used by many companies such as <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a>, <a href="/wiki/MIPS_Computer_Systems" class="mw-redirect" title="MIPS Computer Systems">MIPS Computer Systems</a>, <a href="/wiki/NEC" title="NEC">NEC</a>, <a href="/wiki/Pyramid_Technology" title="Pyramid Technology">Pyramid Technology</a>, <a href="/wiki/SiCortex" title="SiCortex">SiCortex</a>, <a href="/wiki/Siemens_Nixdorf_Informationssysteme" class="mw-redirect" title="Siemens Nixdorf Informationssysteme">Siemens Nixdorf</a>, <a href="/wiki/Silicon_Graphics" title="Silicon Graphics">Silicon Graphics</a>, and <a href="/wiki/Tandem_Computers" title="Tandem Computers">Tandem Computers</a>. </p><p>Historically, <a href="/wiki/Video_game_console" title="Video game console">video game consoles</a> such as the <a href="/wiki/Nintendo_64" title="Nintendo 64">Nintendo 64</a>, <a href="/wiki/Sony" title="Sony">Sony</a> <a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation</a>, <a href="/wiki/PlayStation_2" title="PlayStation 2">PlayStation 2</a>, and <a href="/wiki/PlayStation_Portable" title="PlayStation Portable">PlayStation Portable</a> used MIPS processors. MIPS processors also used to be popular in <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> during the 1990s, but all such systems have dropped off the <a href="/wiki/TOP500" title="TOP500">TOP500</a> list. These uses were complemented by embedded applications at first, but during the 1990s, MIPS became a major presence in the embedded processor market, and by the 2000s, most MIPS processors were for these applications. </p><p>In the mid- to late-1990s, it was estimated that one in three RISC microprocessors produced was a MIPS processor.<sup id="cite_ref-Victor_P._Rubio,_2004_47-0" class="reference"><a href="#cite_note-Victor_P._Rubio,_2004-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>By the late 2010s, MIPS machines were still commonly used in embedded markets, including automotive, wireless router, LTE modems (mainly via <a href="/wiki/MediaTek" title="MediaTek">MediaTek</a>), and microcontrollers (for example the <a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a> <a href="/wiki/PIC_microcontrollers#PIC32M_MIPS-based_line" title="PIC microcontrollers">PIC32M</a>). They have mostly faded out of the personal, server, and application space. </p> <div class="mw-heading mw-heading2"><h2 id="Simulators">Simulators</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=17" title="Edit section: Simulators"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Open Virtual Platforms (OVP)<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> includes the freely available for non-commercial use simulator <a href="/wiki/OVPsim" title="OVPsim">OVPsim</a>, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K, 34K, 74K, 1004K, 1074K, M14K, microAptiv, interAptiv, proAptiv 32-bit cores and the MIPS 64-bit 5K range of cores. These models are created and maintained by Imperas<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free for non-commercial usage, and are easy to use. OVPsim is developed and maintained by <a href="/w/index.php?title=Imperas&action=edit&redlink=1" class="new" title="Imperas (page does not exist)">Imperas</a> and is very fast (hundreds of million of instructions per second), and built to handle multicore homogeneous and heterogeneous architectures and systems. </p><p>There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called <a href="/wiki/SPIM" title="SPIM">SPIM</a> for use in education. EduMIPS64<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. </p><p>MARS<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's <i>Computer Organization and Design</i>. </p><p>WebMIPS<sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> is a browser-based MIPS simulator with visual representation of a generic, pipelined processor. This simulator is quite useful for register tracking during step by step execution. </p><p>QtMips provides a simple 5-stage pipeline visualization as well as cache principle visualization for basic computer architectures courses.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> It is available both as a <a href="/wiki/Web_application" title="Web application">web application</a> and as a downloadable program for Windows, <a href="/wiki/Linux" title="Linux">Linux</a>, and <a href="/wiki/MacOS" title="MacOS">macOS</a>. </p><p>More advanced free emulators are available from the <a href="/wiki/GXemul" title="GXemul">GXemul</a> (formerly known as the mips64emul project) and <a href="/wiki/QEMU" title="QEMU">QEMU</a> projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them. </p><p>Commercial simulators are available especially for the embedded use of MIPS processors, for example Wind River <a href="/wiki/Simics" title="Simics">Simics</a> (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000, Broadcom/Netlogic ec4400, <a href="/wiki/Cavium" title="Cavium">Cavium</a> Octeon I), <a href="/w/index.php?title=Imperas&action=edit&redlink=1" class="new" title="Imperas (page does not exist)">Imperas</a> (all MIPS32 and MIPS64 cores), VaST Systems (R3000, R4000), and <a href="/wiki/CoWare" class="mw-redirect" title="CoWare">CoWare</a> (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K). </p><p>The Creator simulator<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> is portable and allows the user to learn various assembly languages of different processors (Creator has examples with an implementation of MIPS32 and RISC-V instructions). </p><p>WepSIM<sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> is a browser-based simulator where a subset of MIPS instructions are micro-programmed. This simulator is very useful in order to learn how a CPU works (<a rel="nofollow" class="external text" href="https://wepsim.github.io/wepsim/ws_dist/?mode=ep&examples_set=Default-MIPS&example=0&simulator=microcode:control_memory&notify=false">microprogramming</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220726002649/https://wepsim.github.io/wepsim/ws_dist/?mode=ep&examples_set=Default-MIPS&example=0&simulator=microcode:control_memory&notify=false">Archived</a> July 26, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, <a rel="nofollow" class="external text" href="https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=18&simulator=assembly:registers&notify=false">MIPS routines</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220726002658/https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=18&simulator=assembly:registers&notify=false">Archived</a> July 26, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, <a rel="nofollow" class="external text" href="https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=8&simulator=assembly:registers&notify=false">interruptions</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220820181837/https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=8&simulator=assembly:registers&notify=false">Archived</a> August 20, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, <a rel="nofollow" class="external text" href="https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=9&simulator=assembly:registers&notify=false">system calls</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220726002658/https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=9&simulator=assembly:registers&notify=false">Archived</a> July 26, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>, etc.) </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=18" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/DLX" title="DLX">DLX</a></li> <li><a href="/wiki/List_of_MIPS_architecture_processors" title="List of MIPS architecture processors">List of MIPS architecture processors</a></li> <li><a href="/wiki/MIPS_architecture_processors" title="MIPS architecture processors">MIPS architecture processors</a></li> <li><a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">Pipeline (computing)</a></li> <li><a href="/wiki/Prpl_Foundation" title="Prpl Foundation">Prpl Foundation</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=19" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFPatterson2014" class="citation book cs1">Patterson, David (2014). <a rel="nofollow" class="external text" href="http://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf"><i>Computer Organization and Design</i></a> <span class="cs1-format">(PDF)</span>. Elsevier. pp. 4.16–4. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-407726-3" title="Special:BookSources/978-0-12-407726-3"><bdi>978-0-12-407726-3</bdi></a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190904223729/https://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on September 4, 2019<span class="reference-accessdate">. Retrieved <span class="nowrap">November 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Organization+and+Design&rft.pages=4.16-4&rft.pub=Elsevier&rft.date=2014&rft.isbn=978-0-12-407726-3&rft.aulast=Patterson&rft.aufirst=David&rft_id=http%3A%2F%2Fbooksite.elsevier.com%2F9780124077263%2Fdownloads%2Fhistorial%2520perspectives%2Fsection_4.16.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-Price1995-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-Price1995_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Price1995_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">Price, Charles (September 1995). <i>MIPS IV Instruction Set</i> (Revision 3.2), MIPS Technologies, Inc.</span> </li> <li id="cite_note-Sweetman1999-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-Sweetman1999_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-Sweetman1999_3-7"><sup><i><b>h</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSweetman1999" class="citation book cs1">Sweetman, Dominic (1999). <i>See MIPS Run</i>. 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Retrieved <span class="nowrap">March 11,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Wave+Computing+and+MIPS+emerge+from+chapter+11+bankruptcy&rft.date=2021-03-01&rft_id=https%3A%2F%2Fwww.prnewswire.com%2Fnews-releases%2Fwave-computing-and-mips-emerge-from-chapter-11-bankruptcy-301237051.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShilov2021" class="citation news cs1">Shilov, Anton (August 25, 2021). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/uk/news/loongson-continues-to-use-mips-code-for-loongarch-cpus">"Loongson Rips MIPS: Uses Old Code for New CPUs"</a>. <i>Tom's Hardware</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220125121447/https://www.tomshardware.com/uk/news/loongson-continues-to-use-mips-code-for-loongarch-cpus">Archived</a> from the original on January 25, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">December 1,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Loongson+Rips+MIPS%3A+Uses+Old+Code+for+New+CPUs&rft.date=2021-08-25&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fuk%2Fnews%2Floongson-continues-to-use-mips-code-for-loongarch-cpus&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFConnatser2024" class="citation web cs1">Connatser, Matthew (January 19, 2024). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/pc-components/cpus/chinese-chipmaker-loongson-wins-case-over-rights-to-mips-architecture-companys-new-cpu-architecture-heavily-resembles-existing-mips">"Chinese chipmaker Loongson wins case over rights to MIPS architecture - company's new CPU architecture heavily resembles existing MIPS"</a>. <i><a href="/wiki/Tom%27s_Hardware" title="Tom's Hardware">Tom's Hardware</a></i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240119211100/https://www.tomshardware.com/pc-components/cpus/chinese-chipmaker-loongson-wins-case-over-rights-to-mips-architecture-companys-new-cpu-architecture-heavily-resembles-existing-mips">Archived</a> from the original on January 19, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">January 19,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Chinese+chipmaker+Loongson+wins+case+over+rights+to+MIPS+architecture+-+company%27s+new+CPU+architecture+heavily+resembles+existing+MIPS&rft.date=2024-01-19&rft.aulast=Connatser&rft.aufirst=Matthew&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fpc-components%2Fcpus%2Fchinese-chipmaker-loongson-wins-case-over-rights-to-mips-architecture-companys-new-cpu-architecture-heavily-resembles-existing-mips&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-Harris_Harris_2013_pp._294–369-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-Harris_Harris_2013_pp._294–369_27-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHarrisHarris2013" class="citation book cs1">Harris, David Money; Harris, Sarah L. (2013). "Architecture". <i>Digital Design and Computer Architecture</i>. Elsevier. pp. 294–369. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1016%2Fb978-0-12-394424-5.00006-9">10.1016/b978-0-12-394424-5.00006-9</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9780123944245" title="Special:BookSources/9780123944245"><bdi>9780123944245</bdi></a>. <q>R-type is short for register-type. R-type instructions use three registers as operands: two as sources, and one as a destination.</q></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Architecture&rft.btitle=Digital+Design+and+Computer+Architecture&rft.pages=294-369&rft.pub=Elsevier&rft.date=2013&rft_id=info%3Adoi%2F10.1016%2Fb978-0-12-394424-5.00006-9&rft.isbn=9780123944245&rft.aulast=Harris&rft.aufirst=David+Money&rft.au=Harris%2C+Sarah+L.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-mips-ll-sc-28"><span class="mw-cite-backlink">^ <a href="#cite_ref-mips-ll-sc_28-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-mips-ll-sc_28-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9">"APPLICATION NOTE MIPS R4000 Synchronization Primitives"</a> <span class="cs1-format">(PDF)</span>. p. 5. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231227143936/https://www.cs.auckland.ac.nz/compsci313s2c/resources/MIPSLLSC.pdf#page=9">Archived</a> <span class="cs1-format">(PDF)</span> from the original on December 27, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">December 27,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=APPLICATION+NOTE+MIPS+R4000+Synchronization+Primitives&rft.pages=5&rft_id=https%3A%2F%2Fwww.cs.auckland.ac.nz%2Fcompsci313s2c%2Fresources%2FMIPSLLSC.pdf%23page%3D9&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="https://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf"><i>MIPS IV Instruction Set</i></a> <span class="cs1-format">(PDF)</span> (Revision 3.2 ed.). <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>. September 1995. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20221127225045/http://www.cs.cmu.edu/afs/cs/academic/class/15740-f97/public/doc/mips-isa.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on November 27, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">August 24,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=MIPS+IV+Instruction+Set&rft.edition=Revision+3.2&rft.pub=MIPS+Technologies&rft.date=1995-09&rft_id=https%3A%2F%2Fwww.cs.cmu.edu%2Fafs%2Fcs%2Facademic%2Fclass%2F15740-f97%2Fpublic%2Fdoc%2Fmips-isa.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf">"MIPS instruction set R5"</a> <span class="cs1-format">(PDF)</span>. p. 59-62. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231215041747/https://training.mips.com/basic_mips/PDF/Instruction_Set.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on December 15, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">December 15,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=MIPS+instruction+set+R5&rft.pages=59-62&rft_id=https%3A%2F%2Ftraining.mips.com%2Fbasic_mips%2FPDF%2FInstruction_Set.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf">"MIPS® Coherence Protocol Specification, Revision 01.01"</a> <span class="cs1-format">(PDF)</span>. p. 26,25,57. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180904050625/https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00605-2B-CMPCOHERE-AFP-01.01.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on September 4, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">December 15,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=MIPS%C2%AE+Coherence+Protocol+Specification%2C+Revision+01.01&rft.pages=26%2C25%2C57&rft_id=https%3A%2F%2Fs3-eu-west-1.amazonaws.com%2Fdownloads-mips%2Fdocuments%2FMD00605-2B-CMPCOHERE-AFP-01.01.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160309061723/https://imgtec.com/mips/architectures/mips32/">"MIPS – Market-leading RISC CPU IP processor solutions"</a>. <i>imgtec.com</i>. Archived from <a rel="nofollow" class="external text" href="https://imgtec.com/mips/architectures/mips32/">the original</a> on March 9, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">February 11,</span> 2016</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=imgtec.com&rft.atitle=MIPS+%E2%80%93+Market-leading+RISC+CPU+IP+processor+solutions&rft_id=https%3A%2F%2Fimgtec.com%2Fmips%2Farchitectures%2Fmips32%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-33">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1">"Silicon Graphics Introduces Compact MIPS RISC Microprocessor Code For High Performance at a Low Cost" (Press release). October 21, 1996.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Silicon+Graphics+Introduces+Compact+MIPS+RISC+Microprocessor+Code+For+High+Performance+at+a+Low+Cost&rft.date=1996-10-21&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSweetman2007" class="citation book cs1">Sweetman, Dominic (2007). <i>See MIPS Run</i> (2nd ed.). San Francisco, California: Morgan Kaufmann Publishers. pp. 425–427. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-088421-6" title="Special:BookSources/978-0-12-088421-6"><bdi>978-0-12-088421-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=See+MIPS+Run&rft.place=San+Francisco%2C+California&rft.pages=425-427&rft.edition=2nd&rft.pub=Morgan+Kaufmann+Publishers&rft.date=2007&rft.isbn=978-0-12-088421-6&rft.aulast=Sweetman&rft.aufirst=Dominic&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html">"Using the GNU Compiler Collection (GCC): MIPS DSP Built-in Functions"</a>. <i>gcc.gnu.org</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170420143138/https://gcc.gnu.org/onlinedocs/gcc/MIPS-DSP-Built-in-Functions.html">Archived</a> from the original on April 20, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=gcc.gnu.org&rft.atitle=Using+the+GNU+Compiler+Collection+%28GCC%29%3A+MIPS+DSP+Built-in+Functions&rft_id=https%3A%2F%2Fgcc.gnu.org%2Fonlinedocs%2Fgcc%2FMIPS-DSP-Built-in-Functions.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170420045837/https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE">"Instruction Set Architecture - LinuxMIPS"</a>. <i>www.linux-mips.org</i>. Archived from <a rel="nofollow" class="external text" href="https://www.linux-mips.org/wiki/Instruction_Set_Architecture#DSP_ASE">the original</a> on April 20, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.linux-mips.org&rft.atitle=Instruction+Set+Architecture+-+LinuxMIPS&rft_id=https%3A%2F%2Fwww.linux-mips.org%2Fwiki%2FInstruction_Set_Architecture%23DSP_ASE&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-Sweetman-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-Sweetman_37-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSweetman2007" class="citation book cs1">Sweetman, Dominic (2007). <i>See MIPS Run, 2nd edition</i>. Morgan Kaufmann. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12088-421-6" title="Special:BookSources/978-0-12088-421-6"><bdi>978-0-12088-421-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=See+MIPS+Run%2C+2nd+edition&rft.pub=Morgan+Kaufmann&rft.date=2007&rft.isbn=978-0-12088-421-6&rft.aulast=Sweetman&rft.aufirst=Dominic&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-O32-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-O32_38-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.mips.com/?do-download=mips32-instruction-set-quick-reference-v1-01">"MIPS32 Instruction Set Quick Reference"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220125121442/https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00565-2B-MIPS32-QRC-01.01.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on January 25, 2022<span class="reference-accessdate">. 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Retrieved <span class="nowrap">January 13,</span> 2012</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Archived+copy&rft_id=http%3A%2F%2Fwww.dii.unisi.it%2F~giorgi%2FWEBMIPS%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: archived copy as title (<a href="/wiki/Category:CS1_maint:_archived_copy_as_title" title="Category:CS1 maint: archived copy as title">link</a>)</span> (source)</span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://github.com/cvut/QtMips/">QtMips - MIPS CPU simulator for education purposes</a> on <a href="/wiki/GitHub" title="GitHub">GitHub</a></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKočí2018" class="citation thesis cs1">Kočí, Karel (2018). <a rel="nofollow" class="external text" href="https://dspace.cvut.cz/bitstream/handle/10467/76764/F3-DP-2018-Koci-Karel-diploma.pdf"><i>Graphical CPU Simulator with Cache Visualization</i></a> <span class="cs1-format">(PDF)</span> (MSc). <a href="/wiki/Czech_Technical_University_in_Prague" title="Czech Technical University in Prague">Czech Technical University in Prague</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201119140019/https://dspace.cvut.cz/bitstream/handle/10467/76764/F3-DP-2018-Koci-Karel-diploma.pdf">Archived</a> <span class="cs1-format">(PDF)</span> from the original on November 19, 2020<span class="reference-accessdate">. Retrieved <span class="nowrap">January 25,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adissertation&rft.title=Graphical+CPU+Simulator+with+Cache+Visualization&rft.inst=Czech+Technical+University+in+Prague&rft.date=2018&rft.aulast=Ko%C4%8D%C3%AD&rft.aufirst=Karel&rft_id=https%3A%2F%2Fdspace.cvut.cz%2Fbitstream%2Fhandle%2F10467%2F76764%2FF3-DP-2018-Koci-Karel-diploma.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGizopoulos2020" class="citation web cs1"><a href="/wiki/Dimitris_Gizopoulos" title="Dimitris Gizopoulos">Gizopoulos, Dimitris</a> (December 6, 2020). <a rel="nofollow" class="external text" href="https://eclass.uoa.gr/modules/document/file.php/D52/%CE%94%CE%B9%CE%B1%CF%86%CE%AC%CE%BD%CE%B5%CE%B9%CE%B5%CF%82/%CE%A4%CE%B1%20%CE%B2%CE%B1%CF%83%CE%B9%CE%BA%CE%AC%20%CF%84%CE%BF%CF%85%20QtMips-v3.pdf">"The basics of QtMips-v3"</a> <span class="cs1-format">(PDF)</span>. <a href="/wiki/National_and_Kapodistrian_University_of_Athens" title="National and Kapodistrian University of Athens">National and Kapodistrian University of Athens</a><span class="reference-accessdate">. Retrieved <span class="nowrap">January 25,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+basics+of+QtMips-v3&rft.pub=National+and+Kapodistrian+University+of+Athens&rft.date=2020-12-06&rft.aulast=Gizopoulos&rft.aufirst=Dimitris&rft_id=https%3A%2F%2Feclass.uoa.gr%2Fmodules%2Fdocument%2Ffile.php%2FD52%2F%25CE%2594%25CE%25B9%25CE%25B1%25CF%2586%25CE%25AC%25CE%25BD%25CE%25B5%25CE%25B9%25CE%25B5%25CF%2582%2F%25CE%25A4%25CE%25B1%2520%25CE%25B2%25CE%25B1%25CF%2583%25CE%25B9%25CE%25BA%25CE%25AC%2520%25CF%2584%25CE%25BF%25CF%2585%2520QtMips-v3.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span><sup class="noprint Inline-Template"><span style="white-space: nowrap;">[<i><a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot"><span title=" Dead link tagged February 2022">dead link</span></a></i><span style="visibility:hidden; color:transparent; padding-left:2px">‍</span>]</span></sup></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCamarmas-AlonsoGarcia-CarballeiraDel-Pozo-PunalMateos2024" class="citation journal cs1">Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (May 29, 2024). <a rel="nofollow" class="external text" href="https://doi.org/10.1109/ACCESS.2024.3406935">"CREATOR: An Educational Integrated Development Environment for RISC-V Programming"</a>. <i>IEEE Access</i>: 1–17. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FACCESS.2024.3406935">10.1109/ACCESS.2024.3406935</a></span>. <a href="/wiki/ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/2169-3536">2169-3536</a><span class="reference-accessdate">. Retrieved <span class="nowrap">July 24,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Access&rft.atitle=CREATOR%3A+An+Educational+Integrated+Development+Environment+for+RISC-V+Programming&rft.pages=1-17&rft.date=2024-05-29&rft_id=info%3Adoi%2F10.1109%2FACCESS.2024.3406935&rft.issn=2169-3536&rft.aulast=Camarmas-Alonso&rft.aufirst=Diego&rft.au=Garcia-Carballeira%2C+Felix&rft.au=Del-Pozo-Punal%2C+Elias&rft.au=Mateos%2C+Alejandro+Calderon&rft_id=https%3A%2F%2Fdoi.org%2F10.1109%2FACCESS.2024.3406935&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-57">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1 cs1-prop-foreign-lang-source"><a rel="nofollow" class="external text" href="https://zenodo.org/record/5130302">"CREATOR: Simulador didáctico y genérico para la programación en ensamblador"</a> (in Spanish). July 23, 2021. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210929155448/https://zenodo.org/record/5130302">Archived</a> from the original on September 29, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">September 29,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CREATOR%3A+Simulador+did%C3%A1ctico+y+gen%C3%A9rico+para+la+programaci%C3%B3n+en+ensamblador&rft.date=2021-07-23&rft_id=https%3A%2F%2Fzenodo.org%2Frecord%2F5130302&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCamarmas-AlonsoGarcia-CarballeiraDel-Pozo-PunalMateos2022" class="citation conference cs1 cs1-prop-foreign-lang-source">Camarmas-Alonso, Diego; Garcia-Carballeira, Felix; Del-Pozo-Punal, Elias; Mateos, Alejandro Calderon (August 2, 2022). <a rel="nofollow" class="external text" href="https://doi.org/10.1109/CLEI53233.2021.9640144"><i>A new generic simulator for the teaching of assembly programming</i></a>. 2021 XLVII Latin American Computing Conference (CLEI) (in Spanish). pp. 1–9. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FCLEI53233.2021.9640144">10.1109/CLEI53233.2021.9640144</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-6654-9503-5" title="Special:BookSources/978-1-6654-9503-5"><bdi>978-1-6654-9503-5</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:245387555">245387555</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 2,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+new+generic+simulator+for+the+teaching+of+assembly+programming&rft.pages=1-9&rft.date=2022-08-02&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A245387555%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FCLEI53233.2021.9640144&rft.isbn=978-1-6654-9503-5&rft.aulast=Camarmas-Alonso&rft.aufirst=Diego&rft.au=Garcia-Carballeira%2C+Felix&rft.au=Del-Pozo-Punal%2C+Elias&rft.au=Mateos%2C+Alejandro+Calderon&rft_id=https%3A%2F%2Fdoi.org%2F10.1109%2FCLEI53233.2021.9640144&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://creatorsim.github.io/creator/?example_set=default&example=e12">"CREATOR Web with MIPS32 example"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20210929155446/https://creatorsim.github.io/creator/?example_set=default&example=e12">Archived</a> from the original on September 29, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=CREATOR+Web+with+MIPS32+example&rft_id=https%3A%2F%2Fcreatorsim.github.io%2Fcreator%2F%3Fexample_set%3Ddefault%26example%3De12&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-60">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://github.com/creatorsim/creator">CREATOR source code</a> on <a href="/wiki/GitHub" title="GitHub">GitHub</a></span> </li> <li id="cite_note-61"><span class="mw-cite-backlink"><b><a href="#cite_ref-61">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=12&simulator=assembly:registers&notify=false">"WepSIM with a MIPS32 example"</a>. <i>WepSIM</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220725200132/https://wepsim.github.io/wepsim/ws_dist/wepsim-classic.html?mode=ep&examples_set=Default-MIPS&example=12&simulator=assembly:registers&notify=false">Archived</a> from the original on July 25, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">July 25,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=WepSIM&rft.atitle=WepSIM+with+a+MIPS32+example&rft_id=https%3A%2F%2Fwepsim.github.io%2Fwepsim%2Fws_dist%2Fwepsim-classic.html%3Fmode%3Dep%26examples_set%3DDefault-MIPS%26example%3D12%26simulator%3Dassembly%3Aregisters%26notify%3Dfalse&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></span> </li> <li id="cite_note-62"><span class="mw-cite-backlink"><b><a href="#cite_ref-62">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://github.com/wepsim/wepsim">WepSIM source code</a> on <a href="/wiki/GitHub" title="GitHub">GitHub</a></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=20" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1">Farquhar, Erin; Philip Bunce (1994). <i>MIPS Programmer's Handbook</i>. Morgan Kaufmann Publishers. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-55860-297-6" title="Special:BookSources/1-55860-297-6"><bdi>1-55860-297-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=MIPS+Programmer%27s+Handbook&rft.pub=Morgan+Kaufmann+Publishers&rft.date=1994&rft.isbn=1-55860-297-6&rft.aulast=Farquhar&rft.aufirst=Erin&rft.au=Philip+Bunce&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a href="/wiki/David_A._Patterson_(scientist)" class="mw-redirect" title="David A. Patterson (scientist)">Patterson, David A</a>; <a href="/wiki/John_L._Hennessy" title="John L. Hennessy">John L. Hennessy</a> (2004). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/isbn_9781558606043"><i>Computer Organization and Design: The Hardware/Software Interface</i></a></span>. <a href="/wiki/Morgan_Kaufmann_Publishers" title="Morgan Kaufmann Publishers">Morgan Kaufmann Publishers</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-55860-604-1" title="Special:BookSources/1-55860-604-1"><bdi>1-55860-604-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Organization+and+Design%3A+The+Hardware%2FSoftware+Interface&rft.pub=Morgan+Kaufmann+Publishers&rft.date=2004&rft.isbn=1-55860-604-1&rft.aulast=Patterson&rft.aufirst=David+A&rft.au=John+L.+Hennessy&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2Fisbn_9781558606043&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1">Sweetman, Dominic (1999). <i>See MIPS Run</i>. Morgan Kaufmann Publishers. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/1-55860-410-3" title="Special:BookSources/1-55860-410-3"><bdi>1-55860-410-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=See+MIPS+Run&rft.pub=Morgan+Kaufmann+Publishers&rft.date=1999&rft.isbn=1-55860-410-3&rft.aulast=Sweetman&rft.aufirst=Dominic&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1">Sweetman, Dominic (2007). <i>See MIPS Run, 2nd edition</i>. Morgan Kaufmann Publishers. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-12-088421-6" title="Special:BookSources/978-0-12-088421-6"><bdi>978-0-12-088421-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=See+MIPS+Run%2C+2nd+edition&rft.pub=Morgan+Kaufmann+Publishers&rft.date=2007&rft.isbn=978-0-12-088421-6&rft.aulast=Sweetman&rft.aufirst=Dominic&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMIPS+architecture" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=MIPS_architecture&action=edit&section=21" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output .side-box-abovebelow,.mw-parser-output .side-box-text{padding:0.25em 0.9em}.mw-parser-output .side-box-image{padding:2px 0 2px 0.9em;text-align:center}.mw-parser-output .side-box-imageright{padding:2px 0.9em 2px 0;text-align:center}@media(min-width:500px){.mw-parser-output .side-box-flex{display:flex;align-items:center}.mw-parser-output .side-box-text{flex:1;min-width:0}}@media(min-width:720px){.mw-parser-output .side-box{width:238px}.mw-parser-output .side-box-right{clear:right;float:right;margin-left:1em}.mw-parser-output .side-box-left{margin-right:1em}}</style><style data-mw-deduplicate="TemplateStyles:r1237033735">@media print{body.ns-0 .mw-parser-output .sistersitebox{display:none!important}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}</style><div class="side-box side-box-right plainlinks sistersitebox"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style> <div class="side-box-flex"> <div class="side-box-image"><span class="noviewer" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/40px-Wikibooks-logo-en-noslogan.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/60px-Wikibooks-logo-en-noslogan.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/df/Wikibooks-logo-en-noslogan.svg/80px-Wikibooks-logo-en-noslogan.svg.png 2x" data-file-width="400" data-file-height="400" /></span></span></div> <div class="side-box-text plainlist">Wikibooks has a book on the topic of: <i><b><a href="https://en.wikibooks.org/wiki/MIPS_Assembly" class="extiw" title="wikibooks:MIPS Assembly">MIPS Assembly</a></b></i></div></div> </div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1235681985"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1237033735"><div class="side-box side-box-right plainlinks sistersitebox"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"> <div class="side-box-flex"> <div class="side-box-image"><span class="noviewer" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/30px-Commons-logo.svg.png" decoding="async" width="30" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/45px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/59px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></span></span></div> <div class="side-box-text plainlist">Wikimedia Commons has media related to <span style="font-weight: bold; font-style: italic;"><a href="https://commons.wikimedia.org/wiki/Category:MIPS_microprocessors" class="extiw" title="commons:Category:MIPS microprocessors">MIPS microprocessors</a></span>.</div></div> </div> <ul><li><a rel="nofollow" class="external text" href="https://www.mips.com/products/">MIPS Processors</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220511035335/https://www.mips.com/products/">Archived</a> May 11, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130530213243/http://meld.org/library/education/mips-architectures">MIPS Architecture history diagram</a> at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived 2013-05-30)</li> <li><a rel="nofollow" class="external text" href="https://rivoire.cs.sonoma.edu/cs351/wemips/">Online MIPS emulator</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220305210932/https://rivoire.cs.sonoma.edu/cs351/wemips/">Archived</a> March 5, 2022, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li> <li><a rel="nofollow" class="external text" href="https://web.cse.ohio-state.edu/~crawfis.3/cse675-02/Slides/MIPS%20Instruction%20Set.pdf">MIPS Instructions - MIPS Instruction Set</a> <a rel="nofollow" class="external text" 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abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:MIPS_microprocessors" title="Template:MIPS microprocessors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:MIPS_microprocessors" title="Template talk:MIPS microprocessors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:MIPS_microprocessors" title="Special:EditPage/Template:MIPS microprocessors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="MIPS_microprocessors" style="font-size:114%;margin:0 4em">MIPS microprocessors</div></th></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li><a class="mw-selflink selflink">MIPS architecture</a></li> <li><a href="/wiki/MIPS_architecture_processors" title="MIPS architecture processors">MIPS architecture processors</a></li> <li><a href="/wiki/List_of_MIPS_architecture_processors" title="List of MIPS architecture processors">List of MIPS architecture processors</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">General<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="MIPS64compatible" scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_3_Series" title="Loongson">Loongson 3 Series</a> <ul><li>LS3A1000/LS3A1000-I(LS3A1000-i)</li> <li>LS3A2000/LS3A1500-I</li> <li>LS3A3000/LS3A3000-I(LS3A3000-i)</li> <li>LS3A4000/LS3A4000-I(LS3A4000-i)</li> <li>LS3B1000</li> <li>LS3B1500</li> <li>LS3B2000</li> <li>LS3B3000</li> <li>LS3B4000</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Application<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ingenic_Semiconductor" title="Ingenic Semiconductor">Ingenic XBurst</a> <ul><li>JZ4720 <ul><li><a href="/wiki/Ben_NanoNote" title="Ben NanoNote">Ben NanoNote</a></li></ul></li> <li>JZ4730 (<a href="/wiki/Skytone_Alpha-400" title="Skytone Alpha-400">Skytone Alpha-400</a>)</li> <li>JZ4740 (<a href="/wiki/Dingoo_A320" class="mw-redirect" title="Dingoo A320">Dingoo A320</a>)</li> <li>JZ4750 (<a href="/wiki/Game_Gadget" title="Game Gadget">Game Gadget</a>)</li> <li>JZ4760 <ul><li>Velocity Micro T103 Cruz</li> <li>Velocity Micro T301 Cruz</li></ul></li> <li>JZ4770 <ul><li><a href="/wiki/NOVO7" title="NOVO7">Ainol Novo7 Paladin</a></li> <li>NEOGEO-X</li> <li>GCW-Zero</li></ul></li> <li>JZ4780</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_2_Series" title="Loongson">Loongson 2 Series</a> <ul><li>LS2H</li> <li>LS2K1000/LS2K2000</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Microcontroller" title="Microcontroller">Microcontrollers</a><br />(embedded device)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">M4K</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a> <a href="/wiki/PIC_microcontrollers#PIC32MX" title="PIC microcontrollers">PIC32MX</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">4Kc/4KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>ATI/AMD/Broadcom <a href="/wiki/Xilleon" title="Xilleon">Xilleon</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1A0300</li> <li>LS1B</li> <li>LS1C300</li> <li>LS1C101</li> <li>LS1D</li> <li>LS1G</li> <li>LS1H</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Networking</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">4Kc/4KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR2313</li> <li>AR2318</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT2880</li></ul></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a>/Infineon/Lantiq <ul><li>AR7</li></ul></li> <li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>AMAZON</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">5Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Marvell_Technology_Group" class="mw-redirect" title="Marvell Technology Group">Marvell</a> <ul><li>88E6318 "Link Street"</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">24Kc/24KEc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR7240</li> <li>AR7161</li> <li>AR9132</li> <li>AR9331</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT3050</li> <li>RT3052</li> <li>RT3350</li> <li>RT5350</li> <li>RT6856</li> <li>MT7620</li> <li>MT7628</li> <li>MT7688</li></ul></li> <li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>DANUBE</li> <li>VINAX</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">34Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Lantiq" title="Lantiq">Lantiq</a> <ul><li>AR188</li> <li>VRX288</li> <li>GRX388</li></ul></li> <li><a href="/wiki/Ikanos_Communications" title="Ikanos Communications">Ikanos</a> <ul><li>Fusiv Vx175/173</li> <li>Fusiv Vx180</li> <li>Fusiv Vx185/183</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">74Kc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Qualcomm_Atheros" title="Qualcomm Atheros">Qualcomm Atheros</a> <ul><li>AR9344</li> <li>QCA9558</li></ul></li> <li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>RT3662</li> <li>RT3883</li></ul></li> <li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>BCM4706</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">1004Kc</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/MediaTek" title="MediaTek">MediaTek</a> <ul><li>MT7621</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">1074Kc</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Realtek" title="Realtek">Realtek</a> <ul><li>RTL8198C</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>various</li></ul></li> <li><a href="/wiki/Cavium" title="Cavium">Cavium</a> <ul><li>various</li></ul></li> <li>Alchemy Semiconductor <ul><li><a href="/wiki/Alchemy_(processor)" title="Alchemy (processor)">Alchemy</a></li></ul></li> <li><a href="/wiki/RMI_Corporation" title="RMI Corporation">RMI Corporation</a> <ul><li>XLR</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> <ul><li>various</li></ul></li> <li><a href="/wiki/Cavium" title="Cavium">Cavium</a> <ul><li>Octeon</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Gaming</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="various" scope="row" class="navbox-group" style="width:1%">various</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation 1</a> MIPS R3000A-compatible</li> <li><a href="/wiki/Nintendo_64" title="Nintendo 64">Nintendo 64</a> NEC VR4300</li> <li><a href="/wiki/PlayStation_Portable" title="PlayStation Portable">PlayStation Portable</a> R4000-based</li> <li><a href="/wiki/PlayStation_2" title="PlayStation 2">PlayStation 2</a> <a href="/wiki/Emotion_Engine" title="Emotion Engine">Emotion Engine</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Supercomputer" title="Supercomputer">Supercomputer</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="MIPS64compatible" scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson" title="Loongson">Loongson-based systems</a> <ul><li>LS2F/LS2F1000</li> <li>LS3A1000</li> <li>LS3B1000</li></ul></li> <li><a href="/wiki/SiCortex" title="SiCortex">SiCortex</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Aerospace</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">MIPS64<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1E0300/LS1E1000</li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">MIPS32<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Loongson#Loongson_1_Series" title="Loongson">Loongson 1 Series</a> <ul><li>LS1E04</li> <li>LS1F04/LS1F0300</li> <li>LS1J</li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Classic<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">MIPS I</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R2000_(microprocessor)" class="mw-redirect" title="R2000 (microprocessor)">R2000</a></li> <li><a href="/wiki/R3000" title="R3000">R3000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_II" class="mw-redirect" title="MIPS II">MIPS II</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R6000" title="R6000">R6000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_III" class="mw-redirect" title="MIPS III">MIPS III</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R4000" title="R4000">R4000</a> <ul><li><a href="/wiki/R4000#R4400" title="R4000">R4400</a></li></ul></li> <li><a href="/wiki/R4200" title="R4200">R4200</a> <ul><li><a href="/wiki/R4200#R4300i" title="R4200">R4300i</a></li></ul></li> <li><a href="/wiki/R4600" title="R4600">R4600</a> <ul><li><a href="/wiki/R4600#R4700" title="R4600">R4700</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_IV" class="mw-redirect" title="MIPS IV">MIPS IV</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/R5000" title="R5000">R5000</a></li> <li><a href="/wiki/R8000" title="R8000">R8000</a></li> <li><a href="/wiki/R10000" title="R10000">R10000</a> <ul><li><a href="/wiki/R10000#R12000" title="R10000">R12000</a></li> <li><a href="/wiki/R10000#R12000A" title="R10000">R12000A</a></li> <li><a href="/wiki/R10000#R14000" title="R10000">R14000</a></li> <li><a href="/wiki/R10000#R14000A" title="R10000">R14000A</a></li> <li><a href="/wiki/R10000#R16000" title="R10000">R16000</a></li> <li><a href="/wiki/R10000#R16000A" title="R10000">R16000A</a></li> <li><a href="/wiki/R10000#R18000" title="R10000">R18000</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MIPS_V" class="mw-redirect" title="MIPS V">MIPS V</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><i><a href="/wiki/MIPS_Technologies#History" title="MIPS Technologies">H1 "Beast"</a></i></li> <li><i><a href="/wiki/MIPS_Technologies#History" title="MIPS Technologies">H2 "Capitan"</a></i></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Reduced_instruction_set_computer_(RISC)_architectures" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:RISC_architectures" title="Template:RISC architectures"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:RISC_architectures" title="Template talk:RISC architectures"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:RISC_architectures" title="Special:EditPage/Template:RISC architectures"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Reduced_instruction_set_computer_(RISC)_architectures" style="font-size:114%;margin:0 4em"><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_801" title="IBM 801">IBM 801</a></li> <li><a href="/wiki/Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">In active development</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> <a href="/wiki/Blackfin" title="Blackfin">Blackfin</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/ESi-RISC" title="ESi-RISC">eSi-RISC</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a class="mw-selflink selflink">MIPS</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="/wiki/M32R" title="M32R">M32R</a>, <a href="/wiki/SuperH" title="SuperH">SuperH</a>, <a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/Sunway_(processor)" title="Sunway (processor)">Sunway</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> <a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a></li> <li><a href="/wiki/AMD_Am29000" title="AMD Am29000">AMD Am29000</a></li> <li><a href="/wiki/Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li> <li><a href="/wiki/Atmel" title="Atmel">Atmel</a> <a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16</a></li> <li><a href="/wiki/AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li> <li><a href="/wiki/DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li> <li><a href="/wiki/Intel_i860" title="Intel i860">Intel i860</a>, <a href="/wiki/Intel_i960" title="Intel i960">i960</a></li> <li><a href="/wiki/Imagination_META" title="Imagination META">META</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li><a href="/wiki/Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="/wiki/M%C2%B7CORE" title="M·CORE">M·CORE</a></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a></li> <li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <i>(active use in space exploration as <a href="/wiki/RAD750" title="RAD750">RAD750</a>)</i>, <a href="/wiki/IBM_ROMP" title="IBM ROMP">ROMP</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a class="mw-selflink selflink">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a 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