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<span>Architektura K10 (2011): Llano</span> </div> </a> <ul id="toc-Architektura_K10_(2011):_Llano-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Architektura_Bobcat_(2011):_Ontario,_Zacate,_Desna,_Hondo" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Architektura_Bobcat_(2011):_Ontario,_Zacate,_Desna,_Hondo"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1.2</span> <span>Architektura Bobcat (2011): Ontario, Zacate, Desna, Hondo</span> </div> </a> <ul id="toc-Architektura_Bobcat_(2011):_Ontario,_Zacate,_Desna,_Hondo-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Linki_zewnętrzne" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Linki_zewnętrzne"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Linki zewnętrzne</span> </div> </a> <ul id="toc-Linki_zewnętrzne-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Przypisy" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Przypisy"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Przypisy</span> </div> </a> <ul id="toc-Przypisy-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Spis treści" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Przełącz stan spisu treści" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label 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Treść dostępna w 22 językach" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-22" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">22 języki</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-af mw-list-item"><a href="https://af.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – afrikaans" lang="af" hreflang="af" data-title="AMD Fusion" data-language-autonym="Afrikaans" data-language-local-name="afrikaans" class="interlanguage-link-target"><span>Afrikaans</span></a></li><li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%88%D8%AD%D8%AF%D8%A9_%D8%AA%D8%B3%D8%B1%D9%8A%D8%B9_%D8%A7%D9%84%D9%85%D8%B9%D8%A7%D9%84%D8%AC%D8%A9" title="وحدة تسريع المعالجة – arabski" lang="ar" hreflang="ar" data-title="وحدة تسريع المعالجة" data-language-autonym="العربية" data-language-local-name="arabski" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – kataloński" lang="ca" hreflang="ca" data-title="AMD Fusion" data-language-autonym="Català" data-language-local-name="kataloński" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – czeski" lang="cs" hreflang="cs" data-title="AMD Fusion" data-language-autonym="Čeština" data-language-local-name="czeski" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – niemiecki" lang="de" hreflang="de" data-title="AMD Fusion" data-language-autonym="Deutsch" data-language-local-name="niemiecki" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/AMD_APU" title="AMD APU – estoński" lang="et" hreflang="et" data-title="AMD APU" data-language-autonym="Eesti" data-language-local-name="estoński" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-en mw-list-item"><a href="https://en.wikipedia.org/wiki/AMD_APU" title="AMD APU – angielski" lang="en" hreflang="en" data-title="AMD APU" data-language-autonym="English" data-language-local-name="angielski" class="interlanguage-link-target"><span>English</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit" title="AMD Accelerated Processing Unit – hiszpański" lang="es" hreflang="es" data-title="AMD Accelerated Processing Unit" data-language-autonym="Español" data-language-local-name="hiszpański" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%88%D8%A7%D8%AD%D8%AF_%D9%BE%D8%B1%D8%AF%D8%A7%D8%B2%D8%B4_%D8%B3%D8%B1%DB%8C%D8%B9_%D8%A7%DB%8C%E2%80%8C%D8%A7%D9%85%E2%80%8C%D8%AF%DB%8C" title="واحد پردازش سریع ای‌ام‌دی – perski" lang="fa" hreflang="fa" data-title="واحد پردازش سریع ای‌ام‌دی" data-language-autonym="فارسی" data-language-local-name="perski" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/AMD_APU" title="AMD APU – francuski" lang="fr" hreflang="fr" data-title="AMD APU" data-language-autonym="Français" data-language-local-name="francuski" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/AMD_APU" title="AMD APU – koreański" lang="ko" hreflang="ko" data-title="AMD APU" data-language-autonym="한국어" data-language-local-name="koreański" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – włoski" lang="it" hreflang="it" data-title="AMD Fusion" data-language-autonym="Italiano" data-language-local-name="włoski" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit" title="AMD Accelerated Processing Unit – węgierski" lang="hu" hreflang="hu" data-title="AMD Accelerated Processing Unit" data-language-autonym="Magyar" data-language-local-name="węgierski" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit" title="AMD Accelerated Processing Unit – japoński" lang="ja" hreflang="ja" data-title="AMD Accelerated Processing Unit" data-language-autonym="日本語" data-language-local-name="japoński" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit" title="AMD Accelerated Processing Unit – norweski (bokmål)" lang="nb" hreflang="nb" data-title="AMD Accelerated Processing Unit" data-language-autonym="Norsk bokmål" data-language-local-name="norweski (bokmål)" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pa mw-list-item"><a href="https://pa.wikipedia.org/wiki/%E0%A8%8F.%E0%A8%AA%E0%A9%80.%E0%A8%AF%E0%A9%82" title="ਏ.ਪੀ.ਯੂ – pendżabski" lang="pa" hreflang="pa" data-title="ਏ.ਪੀ.ਯੂ" data-language-autonym="ਪੰਜਾਬੀ" data-language-local-name="pendżabski" class="interlanguage-link-target"><span>ਪੰਜਾਬੀ</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/AMD_APU" title="AMD APU – rosyjski" lang="ru" hreflang="ru" data-title="AMD APU" data-language-autonym="Русский" data-language-local-name="rosyjski" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – słowacki" lang="sk" hreflang="sk" data-title="AMD Fusion" data-language-autonym="Slovenčina" data-language-local-name="słowacki" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit" title="AMD Accelerated Processing Unit – fiński" lang="fi" hreflang="fi" data-title="AMD Accelerated Processing Unit" data-language-autonym="Suomi" data-language-local-name="fiński" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/AMD_APU" title="AMD APU – ukraiński" lang="uk" hreflang="uk" data-title="AMD APU" data-language-autonym="Українська" data-language-local-name="ukraiński" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/AMD_Fusion" title="AMD Fusion – kantoński" lang="yue" hreflang="yue" data-title="AMD Fusion" data-language-autonym="粵語" data-language-local-name="kantoński" class="interlanguage-link-target"><span>粵語</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/AMD%E5%8A%A0%E9%80%9F%E5%A4%84%E7%90%86%E5%99%A8" title="AMD加速处理器 – chiński" lang="zh" hreflang="zh" data-title="AMD加速处理器" data-language-autonym="中文" data-language-local-name="chiński" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q294956#sitelinks-wikipedia" title="Edytuj linki pomiędzy wersjami językowymi" class="wbc-editpage">Edytuj linki</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Przestrzenie nazw"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon 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</div> </div> </div> </nav> </div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">Z Wikipedii, wolnej encyklopedii</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="pl" dir="ltr"><p><b>AMD Accelerated Processing Unit</b> (wcześniej jako AMD Fusion) – platforma procesorowa zaprojektowana wspólnie przez inżynierów <a href="/wiki/Advanced_Micro_Devices" title="Advanced Micro Devices">AMD</a> i dawnego <a href="/wiki/ATI_Technologies" title="ATI Technologies">ATI</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Historia">Historia</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=1" title="Edytuj sekcję: Historia" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=1" title="Edytuj kod źródłowy sekcji: Historia"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Projekt AMD Fusion rozpoczął się w 2006 roku w celu opracowania <a href="/wiki/System-on-a-chip" class="mw-redirect" title="System-on-a-chip">układu scalonego</a>, który łączy procesor z kartą graficzną na jednej matrycy. AMD uczyniło kluczowy krok w kierunku realizacji takiej wizji, kiedy w 2006 r. nabyło producenta chipsetu graficznego ATI<sup id="cite_ref-ATIacquisition_1-0" class="reference"><a href="#cite_note-ATIacquisition-1">[1]</a></sup>. Projekt wymagał trzech wewnętrznych iteracji koncepcji Fusion, aby stworzyć produkt uznany za warty wydania<sup id="cite_ref-ATIacquisition_1-1" class="reference"><a href="#cite_note-ATIacquisition-1">[1]</a></sup>. Przyczyny opóźnienia projektu obejmują trudności techniczne związane z połączeniem procesora i karty graficznej na tej samej matrycy w technologii 45 nm oraz sprzeczne poglądy na temat roli procesora i karty graficznej w projekcie<sup id="cite_ref-2" class="reference"><a href="#cite_note-2">[2]</a></sup>. </p><p>APU pierwszej generacji do komputerów stacjonarnych i laptopów o nazwie kodowej Llano ogłoszono 4 stycznia 2011 r. na wystawie <a href="/wiki/Consumer_Electronics_Show" title="Consumer Electronics Show">CES</a> w 2011 roku w Las Vegas, a wkrótce potem nastąpiło jej wydanie<sup id="cite_ref-3" class="reference"><a href="#cite_note-3">[3]</a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4">[4]</a></sup>. Platforma zawierała rdzenie procesora K10 i procesor graficzny Radeon z serii HD 6000 na tej samej matrycy w <a href="/wiki/Gniazdo_procesora" title="Gniazdo procesora">gnieździe</a> FM1. APU dla urządzeń małej mocy ogłoszono jako platformę Brazos, opartą na mikroarchitekturze Bobcat i procesorze graficznym z serii Radeon HD 6000 na tej samej matrycy<sup id="cite_ref-5" class="reference"><a href="#cite_note-5">[5]</a></sup>. </p><p>Na konferencji w styczniu 2012 r. Phil Rogers ogłosił, że AMD dokona <a href="/wiki/Rebranding" title="Rebranding">Rebrandingu</a> platformy Fusion na <i>Heterogeneous System Architecture</i> (HSA), stwierdzając: "pasowałoby, aby nazwa tej rozwijającej się architektury i platformy była reprezentatywna dla całej społeczności technicznej, która jest liderem w tym bardzo ważnym obszarze rozwoju technologii i programowania.”<sup id="cite_ref-6" class="reference"><a href="#cite_note-6">[6]</a></sup> Jednak później ujawniono, że AMD miało wytoczony proces o naruszenie znaku towarowego przez szwajcarską firmę Arctic, która używała nazwy „Fusion” dla linii <a href="/wiki/Zasilacz" title="Zasilacz">produktów zasilających</a><sup id="cite_ref-7" class="reference"><a href="#cite_note-7">[7]</a></sup>. </p><p>APU do komputerów stacjonarnych i laptopów drugiej generacji, o nazwie kodowej Trinity, zostało ogłoszone podczas Dnia Analityków Finansowych w 2010<sup id="cite_ref-8" class="reference"><a href="#cite_note-8">[8]</a></sup><sup id="cite_ref-9" class="reference"><a href="#cite_note-9">[9]</a></sup> i wydane w październiku 2012 r.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10">[10]</a></sup> Ta platforma zawierała rdzenie procesorów Piledriver i rdzenie GPU z serii Radeon HD 7000 na gnieździe FM2<sup id="cite_ref-11" class="reference"><a href="#cite_note-11">[11]</a></sup>. AMD wydało nową APU w oparciu o mikroarchitekturę Piledriver 12 marca 2013 r. (dla laptopów i telefonów komórkowych) oraz 4 czerwca 2013 r. (dla komputerów stacjonarnych), a nazwa robocza brzmiała <i>Richland</i><sup id="cite_ref-12" class="reference"><a href="#cite_note-12">[12]</a></sup>. APU drugiej generacji dla urządzeń o niskiej mocy, Brazos 2.0, używał dokładnie tego samego układu APU, ale działał z większą częstotliwością zegara i zmienił nazwę GPU na Radeon HD7000 i zastosował nowy układ kontrolera IO. </p><p>Układy półniestandardowe zostały wprowadzone w konsolach do gier Microsoft Xbox One i Sony PlayStation 4<sup id="cite_ref-13" class="reference"><a href="#cite_note-13">[13]</a></sup><sup id="cite_ref-14" class="reference"><a href="#cite_note-14">[14]</a></sup>. </p><p>Trzecia generacja technologii została wydana 14 stycznia 2014 r., oferując lepszą integrację procesora z kartą graficzną. Wersja na komputery stacjonarne i laptopy nosi nazwę kodową <i>Kaveri</i> i została oparta na architekturze <i>Steamroller</i>, natomiast warianty małej mocy, o nazwie kodowej <i>Kabini</i> i <i>Temash</i>, bazują na architekturze <i>Jaguar</i><sup id="cite_ref-15" class="reference"><a href="#cite_note-15">[15]</a></sup>. W listopadzie 2017 r. firma <a href="/wiki/Hewlett-Packard" title="Hewlett-Packard">HP</a> wydała Envy x360 z APU Ryzen 5 2500U, pierwszym APU czwartej generacji, z procesorem opartym na architekturze <i>Zen</i> i grafiką opartej na architekturze <i>Vega</i><sup id="cite_ref-16" class="reference"><a href="#cite_note-16">[16]</a></sup>. </p> <div class="mw-heading mw-heading2"><h2 id="Opis">Opis</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=2" title="Edytuj sekcję: Opis" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=2" title="Edytuj kod źródłowy sekcji: Opis"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>W skład platformy wchodzą wielordzeniowe procesory przeznaczone do: </p> <ul><li>netbooków "Ontario", "Wichita"</li> <li>subnotebooków "Zacate", "Krishna"</li> <li>notebooków i desktopów "Llano", "Trinity".</li> <li>desktopów "Bulldozer".</li></ul> <p>Łączą one w sobie tradycyjną architekturę mikroprocesora <a href="/wiki/Procesor" title="Procesor">CPU</a> oraz <a href="/wiki/Karta_graficzna" title="Karta graficzna">karty graficznej</a> <a href="/wiki/Procesor_graficzny" title="Procesor graficzny">GPU</a> w jednym <a href="/wiki/Uk%C5%82ad_scalony" title="Układ scalony">układzie scalonym</a> APU. </p><p>Mostek północny "Hudson M2" obsługuje pamięci DDR3 1600 MHz, USB 3.0, 4X PCIe, 6SATA z RAID i CIR. </p><p>Premiera miała miejsce 4 stycznia 2011 roku, nowa platforma zastąpiła starszą <a href="/wiki/AMD_Eagle" title="AMD Eagle">AMD Eagle</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Parametry_techniczne">Parametry techniczne</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=3" title="Edytuj sekcję: Parametry techniczne" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=3" title="Edytuj kod źródłowy sekcji: Parametry techniczne"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>W tabeli przedstawiono parametry techniczne jednostek APU AMD. </p> <table class="wikitable" style="font-size: 87.5%; text-align: center"> <tbody><tr> <th rowspan="10">Nazwa kodowa</th> <th rowspan="2">Serwer </th> <th>Podstawowy </th> <th colspan="4"> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Toronto</a> </th> <th colspan="4"> </th> <th style="background: #ececec;" rowspan="74"> </th> <th colspan="6"> </th></tr> <tr> <th>Micro </th> <th colspan="9"> </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Kyoto</a> </th> <th colspan="4"> </th></tr> <tr> <th rowspan="3">urządzenia stacjonarne</th> <th>Mainstream </th> <th colspan="4"> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Carrizo</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_unit_microprocessors&action=edit&redlink=1" class="new" title="List of AMD accelerated processing unit microprocessors (strona nie istnieje)">Bristol Ridge</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Raven Ridge</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Picasso</a> </th> <th> </th> <th rowspan="2" colspan="6"> </th></tr> <tr> <th>Entry </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_unit_microprocessors&action=edit&redlink=1" class="new" title="List of AMD accelerated processing unit microprocessors (strona nie istnieje)">Llano</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Trinity</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Richland</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_unit_microprocessors&action=edit&redlink=1" class="new" title="List of AMD accelerated processing unit microprocessors (strona nie istnieje)">Kaveri</a> </th> <th colspan="4"> </th></tr> <tr> <th>Podstawowy </th> <th colspan="9"> </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Kabini</a> </th> <th colspan="4"> </th></tr> <tr> <th rowspan="4">urządzenia mobilne</th> <th>Performance </th> <th colspan="8"> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Renoir</a> </th> <th rowspan="2" colspan="6"> </th></tr> <tr> <th>Mainstream </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Llano</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Trinity</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Richland</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Kaveri</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Carrizo</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Bristol Ridge</a> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Raven Ridge</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Picasso</a> </th></tr> <tr> <th>Entry </th> <th colspan="2"> </th> <th colspan="5"> </th> <th rowspan="2"><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Dalí</a> </th></tr> <tr> <th>Podstawowy </th> <th colspan="9"> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Desna, Ontario, Zacate</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Kabini, Temash</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Beema, Mullins</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Carrizo-L</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_unit_microprocessors&action=edit&redlink=1" class="new" title="List of AMD accelerated processing unit microprocessors (strona nie istnieje)">Stoney Ridge</a> </th></tr> <tr> <th colspan="2">Wbudowany </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Trinity</a> </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Bald Eagle</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Merlin Falcon</a>,<br /><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Brown Falcon</a> </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Great Horned Owl</a> </th> <th colspan="2"> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Ontario, Zacate</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Kabini</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Steppe Eagle</a>, <a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Crowned Eagle</a>,<br /> <a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">LX-Family</a> </th> <th> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Prairie Falcon</a> </th> <th><a href="/w/index.php?title=List_of_AMD_accelerated_processing_units&action=edit&redlink=1" class="new" title="List of AMD accelerated processing units (strona nie istnieje)">Banded Kestrel</a> </th></tr> <tr> <td colspan="3">Platforma</td> <td colspan="9">Wysoka, standardowa oraz niska moc</td> <td colspan="6">Niska oraz ultraniska moc </td></tr> <tr> <td colspan="3">Wydany</td> <td>sierpień 2011</td> <td>październik 2012</td> <td>czerwiec 2013</td> <td>styczeń 2014</td> <td>czerwiec 2015</td> <td>czerwiec 2016</td> <td>październik 2017</td> <td>styczeń 2019</td> <td>marzec 2020</td> <td>styczeń 2011</td> <td>Maj 2013</td> <td>Q2 2014</td> <td>Maj 2015</td> <td>luty 2016</td> <td>kwiecień 2019 </td></tr> <tr> <td colspan="3"><a href="/wiki/Mikroarchitektura_procesora" title="Mikroarchitektura procesora">mikroarchitektura</a> CPU</td> <td><a href="/w/index.php?title=AMD_10h&action=edit&redlink=1" class="new" title="AMD 10h (strona nie istnieje)">K10</a></td> <td colspan="2"><a href="/w/index.php?title=Piledriver_(microarchitecture)&action=edit&redlink=1" class="new" title="Piledriver (microarchitecture) (strona nie istnieje)">Piledriver</a></td> <td><a href="/w/index.php?title=Steamroller_(microarchitecture)&action=edit&redlink=1" class="new" title="Steamroller (microarchitecture) (strona nie istnieje)">Steamroller</a></td> <td><a href="/w/index.php?title=Excavator_(microarchitecture)&action=edit&redlink=1" class="new" title="Excavator (microarchitecture) (strona nie istnieje)">Excavator</a></td> <td>"<a href="/w/index.php?title=Excavator_(microarchitecture)&action=edit&redlink=1" class="new" title="Excavator (microarchitecture) (strona nie istnieje)">Excavator+</a>"<sup id="cite_ref-17" class="reference"><a href="#cite_note-17">[17]</a></sup></td> <td><a href="/w/index.php?title=Zen_(microarchitecture)&action=edit&redlink=1" class="new" title="Zen (microarchitecture) (strona nie istnieje)">Zen</a></td> <td><a href="/w/index.php?title=Zen%2B&action=edit&redlink=1" class="new" title="Zen+ (strona nie istnieje)">Zen+</a></td> <td><a href="/w/index.php?title=Zen_2&action=edit&redlink=1" class="new" title="Zen 2 (strona nie istnieje)">Zen 2</a></td> <td><a href="/w/index.php?title=Bobcat_(microarchitecture)&action=edit&redlink=1" class="new" title="Bobcat (microarchitecture) (strona nie istnieje)">Bobcat</a></td> <td><a href="/w/index.php?title=Jaguar_(microarchitecture)&action=edit&redlink=1" class="new" title="Jaguar (microarchitecture) (strona nie istnieje)">Jaguar</a></td> <td><a href="/w/index.php?title=Puma_(microarchitecture)&action=edit&redlink=1" class="new" title="Puma (microarchitecture) (strona nie istnieje)">Puma</a></td> <td><a href="/w/index.php?title=Puma_(microarchitecture)&action=edit&redlink=1" class="new" title="Puma (microarchitecture) (strona nie istnieje)">Puma+</a><sup id="cite_ref-18" class="reference"><a href="#cite_note-18">[18]</a></sup></td> <td>"<a href="/w/index.php?title=Excavator_(microarchitecture)&action=edit&redlink=1" class="new" title="Excavator (microarchitecture) (strona nie istnieje)">Excavator+</a>"</td> <td><a href="/w/index.php?title=Zen_(microarchitecture)&action=edit&redlink=1" class="new" title="Zen (microarchitecture) (strona nie istnieje)">Zen</a> </td></tr> <tr> <td colspan="3"><a href="/wiki/Model_programowy_procesora" class="mw-redirect" title="Model programowy procesora">Zestaw instrukcji</a> GPU</td> <td colspan="9"><a href="/wiki/X86-64" title="X86-64">x86-64</a></td> <td colspan="6">x86-64 </td></tr> <tr style="border-top:0.2em solid grey"> <td rowspan="5"><a href="/wiki/Gniazdo_procesora" title="Gniazdo procesora">Gniazdo</a></td> <td rowspan="4">urządzenia stacjonarne</td> <td><a href="/wiki/Hi-end" title="Hi-end">Hi-end</a></td> <td colspan="9">N/A</td> <td rowspan="3" colspan="6">N/A </td></tr> <tr> <td>Mainstream</td> <td colspan="4">N/A</td> <td colspan="5"><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> </td></tr> <tr> <td>Entry</td> <td><a href="/w/index.php?title=Socket_FM1&action=edit&redlink=1" class="new" title="Socket FM1 (strona nie istnieje)">FM1</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FM2&action=edit&redlink=1" class="new" title="Socket FM2 (strona nie istnieje)">FM2</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FM2%2B&action=edit&redlink=1" class="new" title="Socket FM2+ (strona nie istnieje)">FM2+</a><sup id="cite_ref-19" class="reference"><a href="#cite_note-19">[19]</a></sup></td> <td colspan="4">N/A </td></tr> <tr> <td>Podstawowy</td> <td colspan="9">N/A</td> <td>N/A</td> <td><a href="/w/index.php?title=Socket_AM1&action=edit&redlink=1" class="new" title="Socket AM1 (strona nie istnieje)">AM1</a></td> <td colspan="4">N/A </td></tr> <tr> <td colspan="2">Inne</td> <td><a href="/w/index.php?title=Socket_FS1&action=edit&redlink=1" class="new" title="Socket FS1 (strona nie istnieje)">FS1</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FS1r2&action=edit&redlink=1" class="new" title="Socket FS1r2 (strona nie istnieje)">FS1+</a>, <a href="/w/index.php?title=Socket_FP2&action=edit&redlink=1" class="new" title="Socket FP2 (strona nie istnieje)">FP2</a></td> <td><a href="/w/index.php?title=Socket_FP3&action=edit&redlink=1" class="new" title="Socket FP3 (strona nie istnieje)">FP3</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (strona nie istnieje)">FP4</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (strona nie istnieje)">FP5</a></td> <td><a href="/w/index.php?title=Socket_FP6&action=edit&redlink=1" class="new" title="Socket FP6 (strona nie istnieje)">FP6</a></td> <td><a href="/w/index.php?title=Socket_FT1&action=edit&redlink=1" class="new" title="Socket FT1 (strona nie istnieje)">FT1</a></td> <td><a href="/w/index.php?title=Socket_FT3&action=edit&redlink=1" class="new" title="Socket FT3 (strona nie istnieje)">FT3</a></td> <td colspan="2"><a href="/w/index.php?title=Socket_FT3b&action=edit&redlink=1" class="new" title="Socket FT3b (strona nie istnieje)">FT3b</a></td> <td><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (strona nie istnieje)">FP4</a></td> <td><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (strona nie istnieje)">FP5</a> </td></tr> <tr> <td colspan="3">Wersja <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a></td> <td colspan="3">2.0</td> <td colspan="6">3.0</td> <td colspan="4">2.0</td> <td colspan="2">3.0 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Technologia wykonania (<a href="/wiki/Nanometr" title="Nanometr">nm</a>)</td> <td colspan="3"><a href="/w/index.php?title=GlobalFoundries&action=edit&redlink=1" class="new" title="GlobalFoundries (strona nie istnieje)">GF</a> <a href="/w/index.php?title=32_nanometer&action=edit&redlink=1" class="new" title="32 nanometer (strona nie istnieje)">32SHP</a><br />(<a href="/w/index.php?title=HKMG&action=edit&redlink=1" class="new" title="HKMG (strona nie istnieje)">HKMG</a> <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a>)</td> <td colspan="3">GF <a href="/w/index.php?title=28_nanometer&action=edit&redlink=1" class="new" title="28 nanometer (strona nie istnieje)">28SHP</a><br />(HKMG bulk)</td> <td>GF <a href="/w/index.php?title=14_nanometer&action=edit&redlink=1" class="new" title="14 nanometer (strona nie istnieje)">14LPP</a><br />(<a href="/w/index.php?title=FinFET&action=edit&redlink=1" class="new" title="FinFET (strona nie istnieje)">FinFET</a> bulk)</td> <td>GF <a href="/w/index.php?title=12_nanometer&action=edit&redlink=1" class="new" title="12 nanometer (strona nie istnieje)">12LP</a><br />(FinFET bulk)</td> <td><a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/w/index.php?title=7_nanometer&action=edit&redlink=1" class="new" title="7 nanometer (strona nie istnieje)">N7</a><br />(FinFET bulk)</td> <td>TSMC <a href="/w/index.php?title=40_nanometer&action=edit&redlink=1" class="new" title="40 nanometer (strona nie istnieje)">N40</a><br />(bulk)</td> <td>TSMC <a href="/w/index.php?title=28_nanometer&action=edit&redlink=1" class="new" title="28 nanometer (strona nie istnieje)">N28</a><br />(HKMG bulk)</td> <td colspan="3">GF 28SHP<br />(HKMG bulk)</td> <td>GF <a href="/w/index.php?title=14_nanometer&action=edit&redlink=1" class="new" title="14 nanometer (strona nie istnieje)">14LPP</a><br />(<a href="/w/index.php?title=FinFET&action=edit&redlink=1" class="new" title="FinFET (strona nie istnieje)">FinFET</a> bulk) </td></tr> <tr> <td colspan="3">Powierzchnia matrycy (mm<sup>2</sup>)</td> <td>228</td> <td colspan="2">246</td> <td>245</td> <td>245</td> <td>250</td> <td colspan="2">210<sup id="cite_ref-20" class="reference"><a href="#cite_note-20">[20]</a></sup></td> <td>156</td> <td>75 (+ 28 <a href="/w/index.php?title=List_of_AMD_chipsets&action=edit&redlink=1" class="new" title="List of AMD chipsets (strona nie istnieje)">FCH</a>)</td> <td colspan="2">107</td> <td>?</td> <td>125</td> <td> </td></tr> <tr> <td colspan="3">Minimalna wartość <a href="/wiki/Thermal_Design_Power" title="Thermal Design Power">TDP</a> (W)</td> <td>35</td> <td colspan="3">17</td> <td colspan="4">12</td> <td>10</td> <td>4.5</td> <td>4</td> <td>3.95</td> <td>10</td> <td colspan="2">6 </td></tr> <tr> <td colspan="3">Maksymalna wartość <a href="/wiki/Thermal_Design_Power" title="Thermal Design Power">TDP</a> (W)</td> <td colspan="3">100</td> <td>95</td> <td colspan="4">65</td> <td>54</td> <td>18</td> <td colspan="5">25 </td></tr> <tr> <td colspan="3">Maksymalna częstotliwość bazowa zegara APU (GHz)</td> <td>3</td> <td>3.8</td> <td colspan="2">4.1</td> <td>3.7</td> <td>3.8</td> <td>3.6</td> <td>3.7</td> <td>3.3</td> <td>1.75</td> <td>2.2</td> <td>2</td> <td>2.2</td> <td>3.2</td> <td>3.3 </td></tr> <tr> <td colspan="3">Maksymalna liczba APU na węzeł<sup id="cite_ref-21" class="reference"><a href="#cite_note-21">[21]</a></sup></td> <td colspan="9">1</td> <td colspan="6">1 </td></tr> <tr> <td colspan="3">Maksymalna liczba <a href="/wiki/Procesor_wielordzeniowy" title="Procesor wielordzeniowy">rdzeni</a> <a href="/wiki/Procesor" title="Procesor">Procesora</a> na APU<sup id="cite_ref-22" class="reference"><a href="#cite_note-22">[22]</a></sup></td> <td colspan="8">4</td> <td>8</td> <td>2</td> <td colspan="3">4</td> <td colspan="2">2 </td></tr> <tr> <td colspan="3">Maksymalna liczba <a href="/wiki/W%C4%85tek_(informatyka)" title="Wątek (informatyka)">wątków</a> na <a href="/wiki/Procesor_wielordzeniowy" title="Procesor wielordzeniowy">rdzeń</a></td> <td colspan="6">1</td> <td colspan="3">2</td> <td colspan="5">1</td> <td>2 </td></tr> <tr> <td colspan="3">struktura całkowita</td> <td>3+3</td> <td colspan="5">2+2</td> <td colspan="2">4+2</td> <td>4+2+1</td> <td colspan="4">1+1+1+1</td> <td>2+2</td> <td>4+2 </td></tr> <tr> <td colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, CMPXCHG16B, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/w/index.php?title=Second_Level_Address_Translation&action=edit&redlink=1" class="new" title="Second Level Address Translation (strona nie istnieje)">RVI</a>, <a href="/w/index.php?title=Bit_Manipulation_Instruction_Sets&action=edit&redlink=1" class="new" title="Bit Manipulation Instruction Sets (strona nie istnieje)">ABM</a> oraz 64-bit LAHF/SAHF</td> <td colspan="9" style="background:#DFD;">Tak</td> <td rowspan="2" colspan="6" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=IOMMU&action=edit&redlink=1" class="new" title="IOMMU (strona nie istnieje)">IOMMU</a><sup id="cite_ref-23" class="reference"><a href="#cite_note-23">[23]</a></sup></td> <td rowspan="2">N/A</td> <td rowspan="2" colspan="8" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=Bit_Manipulation_Instruction_Sets&action=edit&redlink=1" class="new" title="Bit Manipulation Instruction Sets (strona nie istnieje)">BMI1</a>, <a href="/w/index.php?title=AES_instruction_set&action=edit&redlink=1" class="new" title="AES instruction set (strona nie istnieje)">AES-NI</a>, <a href="/w/index.php?title=CLMUL&action=edit&redlink=1" class="new" title="CLMUL (strona nie istnieje)">CLMUL</a> oraz <a href="/w/index.php?title=F16C&action=edit&redlink=1" class="new" title="F16C (strona nie istnieje)">F16C</a></td> <td rowspan="2">N/A</td> <td colspan="5" rowspan="2" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3">MOVBE</td> <td colspan="4" rowspan="2">N/A</td> <td rowspan="2" colspan="5" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=X86_virtualization&action=edit&redlink=1" class="new" title="X86 virtualization (strona nie istnieje)">AVIC</a>, <a href="/w/index.php?title=Bit_Manipulation_Instruction_Sets&action=edit&redlink=1" class="new" title="Bit Manipulation Instruction Sets (strona nie istnieje)">BMI2</a> and <a href="/w/index.php?title=RDRAND&action=edit&redlink=1" class="new" title="RDRAND (strona nie istnieje)">RDRAND</a></td> <td colspan="4">N/A</td> <td colspan="2" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=Intel_ADX&action=edit&redlink=1" class="new" title="Intel ADX (strona nie istnieje)">ADX</a>, <a href="/w/index.php?title=Intel_SHA_extensions&action=edit&redlink=1" class="new" title="Intel SHA extensions (strona nie istnieje)">SHA</a>, <a href="/w/index.php?title=RDSEED&action=edit&redlink=1" class="new" title="RDSEED (strona nie istnieje)">RDSEED</a>, <a href="/w/index.php?title=Supervisor_Mode_Access_Prevention&action=edit&redlink=1" class="new" title="Supervisor Mode Access Prevention (strona nie istnieje)">SMAP</a>, <a href="/w/index.php?title=Control_register&action=edit&redlink=1" class="new" title="Control register (strona nie istnieje)">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT oraz CLZERO</td> <td colspan="6">N/A</td> <td colspan="3" style="background:#DFD;">Tak</td> <td rowspan="2" colspan="5">N/A</td> <td style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3">WBNOINVD, CLWB, RDPID, RDPRU oraz MCOMMIT</td> <td colspan="8">N/A</td> <td colspan="1" style="background:#DFD;">Tak</td> <td colspan="6">N/A </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Ilość <a href="/wiki/Koprocesor" title="Koprocesor">Koprocesorów</a> na rdzeń</td> <td>1</td> <td colspan="5">0.5</td> <td colspan="3">1</td> <td colspan="4">1</td> <td>0.5</td> <td>1 </td></tr> <tr> <td colspan="3">Liczba szyn na FPU</td> <td colspan="9">2</td> <td colspan="6">2 </td></tr> <tr> <td colspan="3">Szerokość szyny FPU</td> <td colspan="8">128-bit</td> <td>256-bit</td> <td>80-bit</td> <td colspan="5">128-bit </td></tr> <tr> <td colspan="3"><a href="/wiki/Model_programowy_procesora" class="mw-redirect" title="Model programowy procesora">zestaw instrukcji</a> (poziom <a href="/wiki/SIMD" title="SIMD">SIMD</a>)</td> <td><a href="/w/index.php?title=SSE4a&action=edit&redlink=1" class="new" title="SSE4a (strona nie istnieje)">SSE4a</a></td> <td colspan="3"><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a></td> <td colspan="5"><a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a></td> <td><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a></td> <td colspan="3"><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a></td> <td colspan="2"><a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a> </td></tr> <tr> <td colspan="3"><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a></td> <td><a href="/wiki/3DNow!#3DNow_extensions" title="3DNow!">3DNow!+</a></td> <td colspan="8">N/A</td> <td colspan="6">N/A </td></tr> <tr> <td colspan="3"><a href="/wiki/3DNow!" title="3DNow!">PREFETCH/PREFETCHW</a></td> <td colspan="9" style="background:#DFD;">Tak</td> <td colspan="6" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=FMA4&action=edit&redlink=1" class="new" title="FMA4 (strona nie istnieje)">FMA4</a>, LWP, <a href="/w/index.php?title=Bit_Manipulation_Instruction_Sets&action=edit&redlink=1" class="new" title="Bit Manipulation Instruction Sets (strona nie istnieje)">TBM</a> oraz <a href="/w/index.php?title=XOP_instruction_set&action=edit&redlink=1" class="new" title="XOP instruction set (strona nie istnieje)">XOP</a></td> <td rowspan="2">N/A</td> <td colspan="5" style="background:#DFD;">Tak</td> <td colspan="3">N/A</td> <td rowspan="2" colspan="4">N/A</td> <td style="background:#DFD;">Tak</td> <td>N/A </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=FMA3&action=edit&redlink=1" class="new" title="FMA3 (strona nie istnieje)">FMA3</a></td> <td colspan="8" style="background:#DFD;">Tak</td> <td colspan="2" style="background:#DFD;">Tak </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Ilość <a href="/w/index.php?title=L1_cache&action=edit&redlink=1" class="new" title="L1 cache (strona nie istnieje)">L1</a> na rdzeń (KiB)</td> <td>64</td> <td colspan="3">16</td> <td colspan="5">32</td> <td colspan="6">32 </td></tr> <tr> <td colspan="3">Asocjatywność instrukcji <a href="/wiki/Pami%C4%99%C4%87_podr%C4%99czna_procesora" title="Pamięć podręczna procesora">L-1 cache</a></td> <td>2</td> <td colspan="3">4</td> <td colspan="5">8</td> <td colspan="6">8 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Liczba instrukcji na rdzeń (L-1)</td> <td>1</td> <td colspan="5">0.5</td> <td colspan="3">1</td> <td colspan="4">1</td> <td>0.5</td> <td>1 </td></tr> <tr> <td colspan="3">Maksymalny rozmiar instrukcji APU (L-1) (KiB)</td> <td>256</td> <td colspan="2">128</td> <td colspan="3">192</td> <td colspan="3">256</td> <td>64</td> <td colspan="3">128</td> <td>96</td> <td>128 </td></tr> <tr> <td colspan="3">Asocjatywność instrukcji <a href="/wiki/Pami%C4%99%C4%87_podr%C4%99czna_procesora" title="Pamięć podręczna procesora">L-1 cache</a></td> <td colspan="3">2</td> <td colspan="3">3</td> <td colspan="2">4</td> <td>8</td> <td colspan="4">2</td> <td>3</td> <td>4 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Ilość <a href="/w/index.php?title=L2_cache&action=edit&redlink=1" class="new" title="L2 cache (strona nie istnieje)">L-2</a> na <a href="/wiki/Procesor_wielordzeniowy" title="Procesor wielordzeniowy">rdzeń</a></td> <td>1</td> <td colspan="5">0.5</td> <td colspan="3">1</td> <td colspan="4">1</td> <td>0.5</td> <td>1 </td></tr> <tr> <td colspan="3">Maksymalny całkowity rozmiar L-2 cache APU (MiB)</td> <td colspan="4">4</td> <td colspan="4">2</td> <td>4</td> <td>1</td> <td colspan="3">2</td> <td colspan="2">1 </td></tr> <tr> <td colspan="3">Asocjatywność L-2 cache</td> <td colspan="6">16</td> <td colspan="3">8</td> <td colspan="5">16</td> <td>8 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Całkowity rozmiar APU <a href="/wiki/L-3_cache" class="mw-redirect" title="L-3 cache">L-3 cache</a> (MiB)</td> <td colspan="6" rowspan="2">N/A</td> <td colspan="2">4</td> <td>8</td> <td colspan="5" rowspan="3">N/A</td> <td>4 </td></tr> <tr> <td colspan="3">Asocjatywność APU L3 cache</td> <td colspan="3">16</td> <td>16 </td></tr> <tr> <td colspan="3">Schemat L3 cache</td> <td colspan="3"><a href="/w/index.php?title=Victim_cache&action=edit&redlink=1" class="new" title="Victim cache (strona nie istnieje)">Victim</a></td> <td colspan="3">N/A</td> <td colspan="3">Victim</td> <td>Victim </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Obsługa <a href="/wiki/Pami%C4%99%C4%87_dynamiczna_(informatyka)" title="Pamięć dynamiczna (informatyka)">DRAM</a></td> <td colspan="2"><a href="/wiki/DDR3_SDRAM" class="mw-redirect" title="DDR3 SDRAM">DDR3-1866</a></td> <td colspan="2"><a href="/wiki/DDR3_SDRAM" class="mw-redirect" title="DDR3 SDRAM">DDR3-2133</a></td> <td><a href="/wiki/DDR3_SDRAM" class="mw-redirect" title="DDR3 SDRAM">DDR3-2133</a>, <a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-2400</a></td> <td><a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-2400</a></td> <td colspan="2"><a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-2933</a></td> <td colspan="1"><a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-3200</a>, <a href="/wiki/LPDDR#LP-DDR4" title="LPDDR">LPDDR4-4266</a></td> <td><a href="/w/index.php?title=DDR3L&action=edit&redlink=1" class="new" title="DDR3L (strona nie istnieje)">DDR3L-1333</a></td> <td><a href="/w/index.php?title=DDR3L&action=edit&redlink=1" class="new" title="DDR3L (strona nie istnieje)">DDR3L-1600</a></td> <td colspan="2"><a href="/w/index.php?title=DDR3L&action=edit&redlink=1" class="new" title="DDR3L (strona nie istnieje)">DDR3L-1866</a></td> <td><a href="/wiki/DDR3_SDRAM" class="mw-redirect" title="DDR3 SDRAM">DDR3-1866</a>, <a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-2400</a></td> <td><a href="/w/index.php?title=DDR4_SDRAM&action=edit&redlink=1" class="new" title="DDR4 SDRAM (strona nie istnieje)">DDR4-2400</a> </td></tr> <tr> <td colspan="3">Maksymalna Ilość kanałów <a href="/wiki/Pami%C4%99%C4%87_dynamiczna_(informatyka)" title="Pamięć dynamiczna (informatyka)">DRAM</a> na APU</td> <td colspan="9">2</td> <td colspan="5">1</td> <td>2 </td></tr> <tr> <td colspan="3">Maksymalne pasmo przenoszenia danych <a href="/wiki/Pami%C4%99%C4%87_dynamiczna_(informatyka)" title="Pamięć dynamiczna (informatyka)">DRAM</a> (GB/s) na APU</td> <td colspan="2">29.866</td> <td colspan="2">34.132</td> <td colspan="2">38.400</td> <td colspan="2">46.932</td> <td>68.256</td> <td>10.666</td> <td>12.800</td> <td colspan="2">14.933</td> <td>19.200</td> <td>38.400 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Mikroarchitektura GPU</td> <td><a href="/w/index.php?title=TeraScale_(microarchitecture)&action=edit&redlink=1" class="new" title="TeraScale (microarchitecture) (strona nie istnieje)">TeraScale 2 (VLIW5)</a></td> <td colspan="2"><a href="/w/index.php?title=TeraScale_(microarchitecture)&action=edit&redlink=1" class="new" title="TeraScale (microarchitecture) (strona nie istnieje)">TeraScale 3 (VLIW4)</a></td> <td><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 2nd gen</a></td> <td colspan="2"><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 3rd gen</a></td> <td colspan="3"><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 5th gen</a><sup id="cite_ref-Vega_codenames_24-0" class="reference"><a href="#cite_note-Vega_codenames-24">[24]</a></sup></td> <td><a href="/w/index.php?title=TeraScale_(microarchitecture)&action=edit&redlink=1" class="new" title="TeraScale (microarchitecture) (strona nie istnieje)">TeraScale 2 (VLIW5)</a></td> <td colspan="3"><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 2nd gen</a></td> <td><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 3rd gen</a><sup id="cite_ref-Vega_codenames_24-1" class="reference"><a href="#cite_note-Vega_codenames-24">[24]</a></sup></td> <td><a href="/w/index.php?title=Graphics_Core_Next&action=edit&redlink=1" class="new" title="Graphics Core Next (strona nie istnieje)">GCN 5th gen</a> </td></tr> <tr> <td colspan="3"><a href="/wiki/Model_programowy_procesora" class="mw-redirect" title="Model programowy procesora">Zestaw instrukcji</a> GPU</td> <td colspan="3">zestaw instrukcji TeraScale</td> <td colspan="6">Zestaw instrukcji GCN</td> <td>zestaw instrukcji TeraScale</td> <td colspan="5">Zestaw instrukcji GCN </td></tr> <tr> <td colspan="3">Maksymalna częstotliwość bazowa zegara APU (MHz)</td> <td>600</td> <td>800</td> <td>844</td> <td>866</td> <td colspan="2">1108</td> <td>1250</td> <td>1400</td> <td>1750</td> <td>538</td> <td>600</td> <td>?</td> <td>847</td> <td>900</td> <td>1200 </td></tr> <tr> <td colspan="3">Maksymalna moc GPU (G<a href="/wiki/FLOPS" title="FLOPS">FLOPS</a>)<sup id="cite_ref-25" class="reference"><a href="#cite_note-25">[25]</a></sup></td> <td>480</td> <td>614.4</td> <td>648.1</td> <td>886.7</td> <td colspan="2">1134.5</td> <td>1760</td> <td>1971.2</td> <td>1792</td> <td>86</td> <td>?</td> <td>?</td> <td>?</td> <td>345.6</td> <td>460.8 </td></tr> <tr style="border-top:0.2em solid grey"> <td rowspan="2" colspan="3">Silnik 3D<sup id="cite_ref-26" class="reference"><a href="#cite_note-26">[26]</a></sup></td> <td>Up to 400:20:8</td> <td colspan="2">Up to 384:24:6</td> <td colspan="3">Up to 512:32:8</td> <td colspan="2">Up to 704:44:16<sup id="cite_ref-27" class="reference"><a href="#cite_note-27">[27]</a></sup></td> <td>Up to 512:?:?</td> <td>80:8:4</td> <td colspan="3">128:8:4</td> <td>Up to 192:?:?</td> <td>Up to 192:?:? </td></tr> <tr> <td colspan="3">IOMMUv1</td> <td colspan="5"><a href="/w/index.php?title=Heterogeneous_Memory_Management&action=edit&redlink=1" class="new" title="Heterogeneous Memory Management (strona nie istnieje)">IOMMUv2</a></td> <td></td> <td colspan="3">IOMMUv1</td> <td colspan="2">?</td> <td>IOMMUv2 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3">Dekoder Video</td> <td colspan="3"><a href="/wiki/Unified_Video_Decoder#UVD_3" title="Unified Video Decoder">UVD 3.0</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_4.2" title="Unified Video Decoder">UVD 4.2</a></td> <td colspan="2"><a href="/wiki/Unified_Video_Decoder#UVD_6" title="Unified Video Decoder">UVD 6.0</a></td> <td rowspan="2" colspan="2"><a href="/wiki/Unified_Video_Decoder#VCN_1" title="Unified Video Decoder">VCN 1.0</a><sup id="cite_ref-28" class="reference"><a href="#cite_note-28">[28]</a></sup></td> <td></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_3" title="Unified Video Decoder">UVD 3.0</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_4" title="Unified Video Decoder">UVD 4.0</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_4.2" title="Unified Video Decoder">UVD 4.2</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_6" title="Unified Video Decoder">UVD 6.0</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_6" title="Unified Video Decoder">UVD 6.3</a></td> <td rowspan="2"><a href="/wiki/Unified_Video_Decoder#VCN_1" title="Unified Video Decoder">VCN 1.0</a> </td></tr> <tr> <td colspan="3">Koder Video</td> <td>N/A</td> <td colspan="2"><a href="/w/index.php?title=Video_Coding_Engine&action=edit&redlink=1" class="new" title="Video Coding Engine (strona nie istnieje)">VCE 1.0</a></td> <td><a href="/w/index.php?title=Video_Coding_Engine&action=edit&redlink=1" class="new" title="Video Coding Engine (strona nie istnieje)">VCE 2.0</a></td> <td colspan="2"><a href="/w/index.php?title=Video_Coding_Engine&action=edit&redlink=1" class="new" title="Video Coding Engine (strona nie istnieje)">VCE 3.1</a></td> <td></td> <td>N/A</td> <td colspan="2"><a href="/w/index.php?title=Video_Coding_Engine&action=edit&redlink=1" class="new" title="Video Coding Engine (strona nie istnieje)">VCE 2.0</a></td> <td colspan="2"><a href="/w/index.php?title=Video_Coding_Engine&action=edit&redlink=1" class="new" title="Video Coding Engine (strona nie istnieje)">VCE 3.1</a> </td></tr> <tr> <td colspan="3">Technologia oszczędzania mocy GPU</td> <td><a href="/w/index.php?title=AMD_PowerPlay&action=edit&redlink=1" class="new" title="AMD PowerPlay (strona nie istnieje)">PowerPlay</a></td> <td colspan="7"><a href="/w/index.php?title=AMD_PowerTune&action=edit&redlink=1" class="new" title="AMD PowerTune (strona nie istnieje)">PowerTune</a></td> <td></td> <td><a href="/w/index.php?title=AMD_PowerPlay&action=edit&redlink=1" class="new" title="AMD PowerPlay (strona nie istnieje)">PowerPlay</a></td> <td colspan="5"><a href="/w/index.php?title=AMD_PowerTune&action=edit&redlink=1" class="new" title="AMD PowerTune (strona nie istnieje)">PowerTune</a><sup id="cite_ref-29" class="reference"><a href="#cite_note-29">[29]</a></sup> </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=AMD_TrueAudio&action=edit&redlink=1" class="new" title="AMD TrueAudio (strona nie istnieje)">TrueAudio</a></td> <td colspan="3" rowspan="2">N/A</td> <td colspan="6" style="background:#DFD;">Tak<sup id="cite_ref-30" class="reference"><a href="#cite_note-30">[30]</a></sup></td> <td rowspan="2">N/A</td> <td colspan="5" style="background:#DFD;">Tak </td></tr> <tr> <td colspan="3"><a href="/wiki/FreeSync" title="FreeSync">FreeSync</a></td> <td colspan="6" style="background:#DFD;">1<br />2</td> <td colspan="5" style="background:#DFD;">1<br />2 </td></tr> <tr> <td colspan="3"><a href="/wiki/HDCP" title="HDCP">HDCP</a><sup id="cite_ref-odtwarzanie_31-0" class="reference"><a href="#cite_note-odtwarzanie-31">[31]</a></sup></td> <td colspan="3">?</td> <td colspan="3">1.4</td> <td colspan="3">1.4<br />2.2</td> <td>?</td> <td colspan="4">1.4</td> <td>1.4<br />2.2 </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=PlayReady&action=edit&redlink=1" class="new" title="PlayReady (strona nie istnieje)">PlayReady</a><sup id="cite_ref-odtwarzanie_31-1" class="reference"><a href="#cite_note-odtwarzanie-31">[31]</a></sup><sup id="cite_ref-32" class="reference"><a href="#cite_note-32">[32]</a></sup><sup id="cite_ref-Radeon_Feature_Matrix_33-0" class="reference"><a href="#cite_note-Radeon_Feature_Matrix-33">[33]</a></sup></td> <td colspan="6">N/A</td> <td colspan="2">3.0 not yet</td> <td></td> <td colspan="5">N/A</td> <td>3.0 not yet </td></tr> <tr> <td colspan="3"><a href="/w/index.php?title=AMD_Eyefinity&action=edit&redlink=1" class="new" title="AMD Eyefinity (strona nie istnieje)">Liczba obsługiwanych monitorów</a><sup id="cite_ref-34" class="reference"><a href="#cite_note-34">[34]</a></sup><sup id="cite_ref-35" class="reference"><a href="#cite_note-35">[35]</a></sup></td> <td>2–3</td> <td colspan="3">2–4</td> <td colspan="2">3</td> <td colspan="2">3 (urządzenia stacjonarne)<br />4 (urządzenia mobilne, embedded)</td> <td>4</td> <td colspan="4">2</td> <td>3</td> <td>4 </td></tr> <tr style="border-top:0.2em solid grey"> <td colspan="3"><code>/drm/radeon</code><sup id="cite_ref-DRM-info_36-0" class="reference"><a href="#cite_note-DRM-info-36">[36]</a></sup><sup id="cite_ref-37" class="reference"><a href="#cite_note-37">[37]</a></sup><sup id="cite_ref-Radeon_Feature_Matrix_33-1" class="reference"><a href="#cite_note-Radeon_Feature_Matrix-33">[33]</a></sup></td> <td colspan="5" style="background:#DFD;">Tak</td> <td colspan="4">N/A</td> <td colspan="4" style="background:#DFD;">Tak</td> <td colspan="2">N/A </td></tr> <tr> <td colspan="3"><code>/drm/amdgpu</code><sup id="cite_ref-DRM-info_36-1" class="reference"><a href="#cite_note-DRM-info-36">[36]</a></sup><sup id="cite_ref-38" class="reference"><a href="#cite_note-38">[38]</a></sup></td> <td colspan="3">N/A</td> <td style="background:#DFD;">Tak<sup id="cite_ref-amdgpu_1.2_39-0" class="reference"><a href="#cite_note-amdgpu_1.2-39">[39]</a></sup></td> <td colspan="5" style="background:#DFD;">Tak</td> <td>N/A</td> <td colspan="3" style="background:#DFD;">Tak<sup id="cite_ref-amdgpu_1.2_39-1" class="reference"><a href="#cite_note-amdgpu_1.2-39">[39]</a></sup></td> <td colspan="2" style="background:#DFD;">Tak </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Platformy_APU">Platformy APU</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=4" title="Edytuj sekcję: Platformy APU" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=4" title="Edytuj kod źródłowy sekcji: Platformy APU"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Jednostki APU AMD mają unikalną architekturę: mają moduły CPU AMD, pamięć podręczną i dyskretny procesor graficzny, wszystkie na tej samej matrycy przy użyciu tej samej magistrali. Ta architektura pozwala na użycie akceleratorów graficznych, takich jak OpenCL, ze zintegrowanym procesorem graficznym<sup id="cite_ref-40" class="reference"><a href="#cite_note-40">[40]</a></sup>. Celem jest stworzenie „w pełni zintegrowanego” APU, który według AMD ostatecznie będzie posiadał „heterogeniczne rdzenie” zdolne do automatycznego przetwarzania zarówno CPU, jak i GPU, w zależności od wymagań obciążenia<sup id="cite_ref-41" class="reference"><a href="#cite_note-41">[41]</a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Procesory_graficzne_oparte_na_architekturze_TeraScale">Procesory graficzne oparte na architekturze TeraScale</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=5" title="Edytuj sekcję: Procesory graficzne oparte na architekturze TeraScale" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=5" title="Edytuj kod źródłowy sekcji: Procesory graficzne oparte na architekturze TeraScale"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="Architektura_K10_(2011):_Llano"><span id="Architektura_K10_.282011.29:_Llano"></span>Architektura K10 (2011): Llano</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=6" title="Edytuj sekcję: Architektura K10 (2011): Llano" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=6" title="Edytuj kod źródłowy sekcji: Architektura K10 (2011): Llano"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/Plik:AMD_A6-3650_(AD3650WNZ43GX)-top_PNr%C2%B00359.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8c/AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg/120px-AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg" decoding="async" width="120" height="119" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8c/AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg/180px-AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8c/AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg/240px-AMD_A6-3650_%28AD3650WNZ43GX%29-top_PNr%C2%B00359.jpg 2x" data-file-width="2257" data-file-height="2247" /></a><figcaption>AMD A6-3650 (Llano)</figcaption></figure> <ul><li><a href="/w/index.php?title=AMD_10h&action=edit&redlink=1" class="new" title="AMD 10h (strona nie istnieje)">AMD K10</a> - 10-rdzeniowa jednostka z rdzeniami "Stars"<sup id="cite_ref-42" class="reference"><a href="#cite_note-42">[42]</a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43">[43]</a></sup></li> <li>Zintegrowana karta graficzna na bazie Evergreen/VLIW5 (wydana pod "szyldem" Radeon HD 6000 Series)</li> <li><a href="/wiki/Mostek_p%C3%B3%C5%82nocny" title="Mostek północny">Mostek północny</a><sup id="cite_ref-AMDHSARoadmap_44-0" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-0" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup></li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a><sup id="cite_ref-AMDHSARoadmap_44-1" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-1" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup></li> <li>Kontroler pamięci <a href="/wiki/DDR3" title="DDR3">DDR3</a><sup id="cite_ref-AMDHSARoadmap_44-2" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-2" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup> do zarządzania spójnymi i niespójnymi próbami dostępu do pamięci<sup id="cite_ref-RealWorldTechFusion_46-0" class="reference"><a href="#cite_note-RealWorldTechFusion-46">[46]</a></sup>. <a href="/wiki/Pami%C4%99%C4%87_komputerowa" title="Pamięć komputerowa">Pamięć fizyczna</a> jest podzielona między procesor graficzny (do 512 MB) i procesor (pozostała część)<sup id="cite_ref-RealWorldTechFusion_46-1" class="reference"><a href="#cite_note-RealWorldTechFusion-46">[46]</a></sup>.</li> <li><a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder</a><sup id="cite_ref-AMDHSARoadmap_44-3" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-3" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup></li> <li>Technologia <a href="/wiki/Eyefinity" title="Eyefinity">Eyefinity</a> to obsługi wielu monitorów</li></ul> <p>APU pierwszej generacji, wydany w czerwcu 2011 roku, był używany zarówno na komputerach stacjonarnych, jak i laptopach. Został oparty na architekturze K10 i zbudowany w technologii 32 nm, obejmującej od dwóch do czterech rdzeni procesora o <a href="/wiki/Thermal_Design_Power" title="Thermal Design Power">wartości TDP</a> rzędu 65-100 W, oraz zintegrowaną grafikę opartą na serii Radeon HD6000 z obsługą DirectX 11, OpenGL 4.2 i OpenCL 1.2. Po porównaniu wydajności z podobnie wycenionym procesorem Intel Core i3-2105, Llano został skrytykowany za słabą wydajność procesora<sup id="cite_ref-47" class="reference"><a href="#cite_note-47">[47]</a></sup> lecz otrzymał chwały za lepszą wydajność GPU<sup id="cite_ref-48" class="reference"><a href="#cite_note-48">[48]</a></sup><sup id="cite_ref-49" class="reference"><a href="#cite_note-49">[49]</a></sup>. AMD zostało później skrytykowane zarezygnację z <a href="/wiki/Gniazdo_procesora" title="Gniazdo procesora">Socket FM1</a> po jednej generacji<sup id="cite_ref-50" class="reference"><a href="#cite_note-50">[50]</a></sup>. </p> <div class="mw-heading mw-heading4"><h4 id="Architektura_Bobcat_(2011):_Ontario,_Zacate,_Desna,_Hondo"><span id="Architektura_Bobcat_.282011.29:_Ontario.2C_Zacate.2C_Desna.2C_Hondo"></span>Architektura Bobcat (2011): Ontario, Zacate, Desna, Hondo</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=7" title="Edytuj sekcję: Architektura Bobcat (2011): Ontario, Zacate, Desna, Hondo" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=7" title="Edytuj kod źródłowy sekcji: Architektura Bobcat (2011): Ontario, Zacate, Desna, Hondo"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Procesor oparty na mikroarchitekturze <a href="/w/index.php?title=Bobcat_(microarchitecture)&action=edit&redlink=1" class="new" title="Bobcat (microarchitecture) (strona nie istnieje)">Bobcat</a></li> <li>GPU oparty na <a href="/w/index.php?title=Radeon_HD_5000_Series&action=edit&redlink=1" class="new" title="Radeon HD 5000 Series (strona nie istnieje)">Evergreen/VLIW5</a> (oznaczony jako <a href="/w/index.php?title=Radeon_HD_6000_Series&action=edit&redlink=1" class="new" title="Radeon HD 6000 Series (strona nie istnieje)">Radeon HD 6000 Series</a> oraz <a href="/w/index.php?title=Radeon_HD_7000_Series&action=edit&redlink=1" class="new" title="Radeon HD 7000 Series (strona nie istnieje)">Radeon HD 7000 Series</a>)</li> <li><a href="/wiki/Mostek_p%C3%B3%C5%82nocny" title="Mostek północny">Mostek północny</a><sup id="cite_ref-AMDHSARoadmap_44-4" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-4" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup></li> <li>Obsługa <a href="/wiki/PCIe" class="mw-redirect" title="PCIe">PCIe</a><sup id="cite_ref-AMDHSARoadmap_44-5" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-5" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup>.</li> <li>Kontroler pamięci <a href="/wiki/DDR3_SDRAM" class="mw-redirect" title="DDR3 SDRAM">DDR3 SDRAM</a><sup id="cite_ref-AMDHSARoadmap_44-6" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-6" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup> do arbitrażu między spójnymi i niespójnymi żądaniami pamięci<sup id="cite_ref-RealWorldTechFusion_46-2" class="reference"><a href="#cite_note-RealWorldTechFusion-46">[46]</a></sup>. Pamięć fizyczna jest podzielona między procesor graficzny (do 512 MB) i procesor (pozostała część)<sup id="cite_ref-RealWorldTechFusion_46-3" class="reference"><a href="#cite_note-RealWorldTechFusion-46">[46]</a></sup>.</li> <li><a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder</a> (UVD)<sup id="cite_ref-AMDHSARoadmap_44-7" class="reference"><a href="#cite_note-AMDHSARoadmap-44">[44]</a></sup><sup id="cite_ref-AnandTechFusion_45-7" class="reference"><a href="#cite_note-AnandTechFusion-45">[45]</a></sup></li></ul> <p>Platforma AMD Brazos została wprowadzona 4 stycznia 2011 r. i jest skierowana na rynki takich urządzeń jak: subnotebooki, netbooki i urządzenia o małej mocy<sup id="cite_ref-amd_fusion_release_51-0" class="reference"><a href="#cite_note-amd_fusion_release-51">[51]</a></sup> Zawiera 9-watową jednostkę APU AMD C-Series (nazwa kodowa: Ontario) dla netbooków i urządzeń o niskiej mocy, a także 18-watową jednostkę APU AMD E-Series (nazwa kodowa: Zacate) dla popularnych i cenionych notebooków, komputerów typu "All-in-one" i małych komputerów stacjonarnych. Oba APU mają jeden lub dwa rdzenie Bobcat x86 i procesor graficzny Radeon Evergreen Series z pełną obsługą DirectX11, DirectCompute i OpenCL, w tym akceleracją UVD3 dla wideo HD, w tym <a href="/wiki/1080p" title="1080p">1080p</a><sup id="cite_ref-amd_fusion_release_51-1" class="reference"><a href="#cite_note-amd_fusion_release-51">[51]</a></sup>. </p><p>AMD rozszerzyło platformę Brazos w dniu 5 czerwca 2011 r., Wprowadzając 5,9-watową jednostkę APU AMD Z-Series (nazwa kodowa: Desna) zaprojektowaną na rynek tabletów<sup id="cite_ref-amd_desna_release_52-0" class="reference"><a href="#cite_note-amd_desna_release-52">[52]</a></sup>. Desna APU oparta jest na 9-watowej jednostce APU Ontario. Oszczędności energii uzyskano poprzez obniżenie napięcia procesora, karty graficznej i mostka północnego, zmniejszenie bezczynności zegarów procesora i karty graficznej oraz wprowadzenie sprzętowego trybu kontroli termicznej<sup id="cite_ref-amd_desna_release_52-1" class="reference"><a href="#cite_note-amd_desna_release-52">[52]</a></sup>. Wprowadzono również dwukierunkowy tryb <a href="/wiki/AMD_Turbo_Core" title="AMD Turbo Core">AMD Turbo Core</a>. </p><p>AMD ogłosiło platformę Brazos-T 9 października 2012 r. Składała się z 4,5-watowej jednostki APU AMD Z-Series (o nazwie kodowej Hondo) i z <a href="/wiki/Mostek_po%C5%82udniowy" title="Mostek południowy">mostka południowego (FCH) )</a> A55T, zaprojektowanego z myślą o rynku tabletów<sup id="cite_ref-53" class="reference"><a href="#cite_note-53">[53]</a></sup><sup id="cite_ref-54" class="reference"><a href="#cite_note-54">[54]</a></sup>. Hondo APU to przeprojektowana APU Desna. AMD obniżyło zużycie energii poprzez optymalizację APU i FCH dla tabletów<sup id="cite_ref-55" class="reference"><a href="#cite_note-55">[55]</a></sup><sup id="cite_ref-56" class="reference"><a href="#cite_note-56">[56]</a></sup>. </p><p>Platforma Deccan, w tym APU Krishna i Wichita, została anulowana w 2011 r. AMD pierwotnie planowało wydać je w drugiej połowie 2012 r.<sup id="cite_ref-Deccan_57-0" class="reference"><a href="#cite_note-Deccan-57">[57]</a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Linki_zewnętrzne"><span id="Linki_zewn.C4.99trzne"></span>Linki zewnętrzne</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=8" title="Edytuj sekcję: Linki zewnętrzne" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=8" title="Edytuj kod źródłowy sekcji: Linki zewnętrzne"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="infobox noprint plainlinks" cellpadding="4" role="presentation"> <tbody><tr> <td style="vertical-align:middle; text-align:center; width:30px;"><span class="notpageimage" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/21px-Commons-logo.svg.png" decoding="async" width="21" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/31px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/4a/Commons-logo.svg/42px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></span></span> </td> <td style="line-height:normal; vertical-align:middle; text-align:center; flex:unset;"><a class="external text" href="https://commons.wikimedia.org/wiki/Category:AMD_Accelerated_Processing_Unit?uselang=pl"><strong>Zobacz multimedia</strong> związane z tematem: <em>AMD Accelerated Processing Unit</em></a> </td></tr></tbody></table> <ul><li><a rel="nofollow" class="external text" href="https://archive.is/20160404113132/http://www.amd.com/en-us/innovations/software-technologies/apu">Oficjalna strona platformy (wersja archiwalna)</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Przypisy">Przypisy</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&veaction=edit&section=9" title="Edytuj sekcję: Przypisy" class="mw-editsection-visualeditor"><span>edytuj</span></a><span class="mw-editsection-divider"> | </span><a href="/w/index.php?title=AMD_Accelerated_Processing_Unit&action=edit&section=9" title="Edytuj kod źródłowy sekcji: Przypisy"><span>edytuj kod</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="do-not-make-smaller refsection"><div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-ATIacquisition-1"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-ATIacquisition_1-0">a</a></sup> <sup><a href="#cite_ref-ATIacquisition_1-1">b</a></sup></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://arstechnica.com/business/2013/04/amd-on-ropes-from-the-top-of-the-mountain-to-the-deepest-valleys/2/">The rise and fall of AMD: A company on the ropes</a>. 23 kwietnia 2013. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><a href="#cite_ref-2">↑</a></span> <span class="reference-text"><cite class="citation web">William Van Winkle: <a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/fusion-hsa-opencl-history,3262-4.html">AMD Fusion: How It Started, Where It’s Going, And What It Means</a>. 13 sierpnia 2012. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><a href="#cite_ref-3">↑</a></span> <span class="reference-text"><cite class="citation web">AMD: <a rel="nofollow" class="external text" href="https://www.amd.com/us/press-releases/Pages/amd-fusion-apu-era-2011jan04.aspx">AMD Fusion APU Era Begins</a>. 4 stycznia 2011. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><a href="#cite_ref-4">↑</a></span> <span class="reference-text"><cite class="citation web">Jon Stokes: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100210011231/http://arstechnica.com/business/news/2010/02/amd-reveals-fusion-cpugpu-to-challege-intel-in-laptops.ars">AMD reveals Fusion CPU+GPU, to challenge Intel in laptops</a>. Ars Technica, 8 lutego, 2010. [zarchiwizowane z <a rel="nofollow" class="external text" href="https://arstechnica.com/business/news/2010/02/amd-reveals-fusion-cpugpu-to-challege-intel-in-laptops.ars">tego adresu</a> (10 lutego 2010)]. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><a href="#cite_ref-5">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://techreport.com/review/19937/a-closer-look-at-amd-brazos-platform">A closer look at AMD's Brazos platform</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><a href="#cite_ref-6">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://www.bit-tech.net/news/hardware/2012/01/19/amd-ditches-fusion-branding/1">AMD ditches Fusion branding</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><a href="#cite_ref-7">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://www.bit-tech.net/news/bits/2012/01/23/amd-arctic-fusion-brand/1">AMD targeted by Arctic over Fusion brand</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><a href="#cite_ref-8">↑</a></span> <span class="reference-text"><cite class="citation web">Cyril Kowaliski: <a rel="nofollow" class="external text" href="http://techreport.com/discussions.x/19948">AMD begins shipping Brazos, announces Bulldozer-based APUs</a>. The Tech Report, 9 listopada 2010. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><a href="#cite_ref-9">↑</a></span> <span class="reference-text"><cite class="citation web">Rick Bergman: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160118024109/http://ir.amd.com/External.File?item=UGFyZW50SUQ9Njk3NTF8Q2hpbGRJRD0tMXxUeXBlPTM=&t=1#page=27">AMD 2010 Financial Analyst Day</a>. Advanced Micro Devices, Inc., 9 listopada 2010. [zarchiwizowane z <a rel="nofollow" class="external text" href="http://ir.amd.com/External.File?item=UGFyZW50SUQ9Njk3NTF8Q2hpbGRJRD0tMXxUeXBlPTM=&t=1#page=27">tego adresu</a> (18 stycznia 2016)]. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><a href="#cite_ref-10">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20190302113624/https://www.engadget.com/2012/02/02/amd-2012-2013-roadmap-APUs-galore/">AMD reveals its 2012-2013 roadmap, promises 28 nm chips across the board by 2013</a>. Engadget, 2012-02-02. [dostęp 2020-01-03]. [zarchiwizowane z <a rel="nofollow" class="external text" href="https://www.engadget.com/2012/02/02/amd-2012-2013-roadmap-APUs-galore/">tego adresu</a> (2019-03-02)]. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><a href="#cite_ref-11">↑</a></span> <span class="reference-text"><cite class="citation web">Adrian Kingsley-Hughes: <a rel="nofollow" class="external text" href="https://www.zdnet.com/building-an-amd-trinity-desktop-pc-7000005227">Building an AMD 'Trinity' desktop PC - ZDNet</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><a href="#cite_ref-12">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130719015106/http://www.techspot.com/news/51909-amd-launches-richland-a-series-apus-slight-speed-bump-better-power-management.html"><i>AMD launches "Richland" A-Series APUs: slight speed bump, better power management - TechSpot</i></a> [online], www.techspot.com<span class="accessdate"> [dostęp 2020-01-05]</span> [zarchiwizowane z <a rel="nofollow" class="external text" href="http://www.techspot.com/news/51909-amd-launches-richland-a-series-apus-slight-speed-bump-better-power-management.html">adresu</a> 2013-07-19]<span class="Z3988" title="ctx_ver=Z39.88-2004&rft.gengre=book&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.btitle=AMD+launches+%22Richland%22+A-Series+APUs%3A+slight+speed+bump%2C+better+power+management+-+TechSpot&rft_id=http%3A%2F%2Fwww.techspot.com%2Fnews%2F51909-amd-launches-richland-a-series-apus-slight-speed-bump-better-power-management.html" style="display:none"> </span> <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-13"><span class="mw-cite-backlink"><a href="#cite_ref-13">↑</a></span> <span class="reference-text"><cite class="citation web">John Taylor: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130526191443/http://community.amd.com/community/amd-blogs/amd-unprocessed/blog/2013/02/21/amd-and-the-sony-ps4-allow-me-to-elaborate">AMD and The Sony PS4. Allow Me To Elaborate.</a>. 2013-02-21. [zarchiwizowane z <a rel="nofollow" class="external text" href="http://community.amd.com/community/amd-blogs/amd-unprocessed/blog/2013/02/21/amd-and-the-sony-ps4-allow-me-to-elaborate">tego adresu</a> (2013-05-26)]. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-14"><span class="mw-cite-backlink"><a href="#cite_ref-14">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://archive.is/20130521181315/http://www.wired.com/gadgetlab/2013/05/xbox-one/">XBox One Revealed</a>. Wired, 2013-05-21. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-15"><span class="mw-cite-backlink"><a href="#cite_ref-15">↑</a></span> <span class="reference-text"><cite class="citation web">Darren Murph: <a rel="nofollow" class="external text" href="https://www.engadget.com/2013/01/07/amd-temash-kabini-richland-kaveri-apu/">AMD announces Temash, Kabini, Richland, and Kaveri APUs at CES 2013 (video)</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><a href="#cite_ref-16">↑</a></span> <span class="reference-text"><cite class="citation web">Jacob Ridley: <a rel="nofollow" class="external text" href="https://www.pcgamesn.com/amd/amd-raven-ridge-apu">AMD Raven Ridge - Ryzen Mobile release date, specs, and performance</a>. 15 listopada 2017. [dostęp 2017-11-30]. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><a href="#cite_ref-17">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks">AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks</a>. 31 maja 2016. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><a href="#cite_ref-18">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://www.amd.com/en-us/press-releases/Pages/amd-mobile-carrizo-2014nov20.aspx">AMD urządzenia mobilne "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015</a>. 20 listopada 2014. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-19"><span class="mw-cite-backlink"><a href="#cite_ref-19">↑</a></span> <span class="reference-text">modele APU: A8-7680, A6-7480. Modele CPU: Athlon X4 845.</span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><a href="#cite_ref-20">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/">The mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD urządzenia mobilne CPU Full List</a>. TechARP.com. [dostęp 2017-12-13].</cite></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><a href="#cite_ref-21">↑</a></span> <span class="reference-text">Komputer w tym wypadku jest pojedynczym węzłem.</span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><a href="#cite_ref-22">↑</a></span> <span class="reference-text">APU to połączenie CPU i GPU. Każdy z nich posiada rdzenie.</span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><a href="#cite_ref-23">↑</a></span> <span class="reference-text">Wymagana obsługa firmware'a</span> </li> <li id="cite_note-Vega_codenames-24"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-Vega_codenames_24-0">a</a></sup> <sup><a href="#cite_ref-Vega_codenames_24-1">b</a></sup></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/">AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver</a>. VideoCardz.com. [dostęp 2017-06-06].</cite></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><a href="#cite_ref-25">↑</a></span> <span class="reference-text">Wydajność jest obliczana na podstawie bazowej (lub podwyższonej) częstotliwości taktowania rdzenia na podstawie operacji <a href="/wiki/Multiply-accumulate" title="Multiply-accumulate">FMA</a>.</span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><a href="#cite_ref-26">↑</a></span> <span class="reference-text">Zunifikowane modele modułów cieniujących, jednostki mapowania tekstur, jednostki renderujące</span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><a href="#cite_ref-27">↑</a></span> <span class="reference-text"><cite class="citation web">Ian Cutress: <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3">Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm</a>. Anandtech, 1 lutego 2018. [dostęp 2018-02-07].</cite></span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><a href="#cite_ref-28">↑</a></span> <span class="reference-text"><cite class="citation web">Michael Larabel: <a rel="nofollow" class="external text" href="https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands">Radeon VCN Encode Support Lands in Mesa 17.4 Git</a>. Phoronix, 17 listopada 2017. [dostęp 2017-11-20].</cite></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><a href="#cite_ref-29">↑</a></span> <span class="reference-text"><cite class="citation web"><span class="cite-name-before"><span class="cite-name-full">Tony</span><span class="cite-name-initials" title="Tony" style="display:none">T.</span> </span><span class="cite-lastname">Chen</span><span class="cite-name-after" style="display:none"> <span class="cite-name-full">Tony</span><span class="cite-name-initials" title="Tony">T.</span></span>, <span class="cite-name-before"><span class="cite-name-full">Jason</span><span class="cite-name-initials" title="Jason" style="display:none">J.</span> </span><span class="cite-lastname">Greaves</span><span class="cite-name-after" style="display:none"> <span class="cite-name-full">Jason</span><span class="cite-name-initials" title="Jason">J.</span></span>, <a rel="nofollow" class="external text" href="http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf"><i>AMD's Graphics Core Next (GCN) Architecture</i></a>, [w:] AMD [online]<span class="accessdate"> [dostęp 2016-08-13]</span><span class="Z3988" title="ctx_ver=Z39.88-2004&rft.gengre=bookitem&rft.aufirst=Tony&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.btitle=AMD&rft.atitle=AMD%27s+Graphics+Core+Next+%28GCN%29+Architecture&rft.aulast=Chen&rft_id=http%3A%2F%2Fmeseec.ce.rit.edu%2F551-projects%2Ffall2014%2F3-4.pdf" style="display:none"> </span>.</cite></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><a href="#cite_ref-30">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/">A technical look at AMD's Kaveri architecture</a>. Semi Accurate. [dostęp 2014-07-06].</cite></span> </li> <li id="cite_note-odtwarzanie-31"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-odtwarzanie_31-0">a</a></sup> <sup><a href="#cite_ref-odtwarzanie_31-1">b</a></sup></span> <span class="reference-text">Do odtwarzania chronionej zawartości wideo wymagana jest także obsługa karty, systemu operacyjnego, sterownika i aplikacji. Do tego potrzebny jest również kompatybilny wyświetlacz z technologią <a href="/wiki/HDCP" title="HDCP">HDCP</a>. HDCP jest obowiązkowy do odtwarzania niektórych formatów audio, co nakłada dodatkowe ograniczenia na konfigurację multimediów.</span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><a href="#cite_ref-32">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://airlied.livejournal.com/68805.html">DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33</a>. 26 listopada 2009. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-Radeon_Feature_Matrix-33"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-Radeon_Feature_Matrix_33-0">a</a></sup> <sup><a href="#cite_ref-Radeon_Feature_Matrix_33-1">b</a></sup></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://xorg.freedesktop.org/wiki/RadeonFeature/">Radeon feature matrix</a>. [w:] <i><a href="/wiki/Freedesktop.org" title="Freedesktop.org">freedesktop.org</a></i> [on-line]. [dostęp 2016-01-10].</cite></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><a href="#cite_ref-34">↑</a></span> <span class="reference-text">Aby zasilać więcej niż dwa monitory, dodatkowe panele muszą mieć natywną obsługę <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a>. Alternatywnie można zastosować przejściówki z DisplayPort na DVI / HDMI / VGA.</span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><a href="#cite_ref-35">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://support.amd.com/en-us/search/faq/154">How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?</a>. AMD. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-DRM-info-36"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-DRM-info_36-0">a</a></sup> <sup><a href="#cite_ref-DRM-info_36-1">b</a></sup></span> <span class="reference-text">DRM (<a href="/wiki/Direct_Rendering_Manager" title="Direct Rendering Manager">Direct Rendering Manager</a>) jest składnikiem jądra Linuxa. Dane zawarte w tabeli dot. obsługi najnowjszej wersji</span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><a href="#cite_ref-37">↑</a></span> <span class="reference-text"><cite class="citation web">David Airlie: <a rel="nofollow" class="external text" href="http://airlied.livejournal.com/68805.html">DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33</a>. 26 listopada 2009. [dostęp 2016-01-16].</cite></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><a href="#cite_ref-38">↑</a></span> <span class="reference-text"><cite class="citation web">Alexander Deucher: <a rel="nofollow" class="external text" href="http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf">XDC2015: AMDGPU</a>. 16 września 2015. [dostęp 2016-01-16].</cite></span> </li> <li id="cite_note-amdgpu_1.2-39"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-amdgpu_1.2_39-0">a</a></sup> <sup><a href="#cite_ref-amdgpu_1.2_39-1">b</a></sup></span> <span class="reference-text"><cite class="citation web">Michel Dänzer: <a rel="nofollow" class="external text" href="https://lists.x.org/archives/xorg-announce/2016-November/002741.html">[ANNOUNCE</a> xf86-video-amdgpu 1.2.0]. [w:] <i>lists.x.org</i> [on-line]. 17 listopada 2016.</cite></span> </li> <li id="cite_note-40"><span class="mw-cite-backlink"><a href="#cite_ref-40">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141228114707/http://phx.corporate-ir.net/External.File?item=UGFyZW50SUQ9ODUyOTR8Q2hpbGRJRD0tMXxUeXBlPTM=&t=1">APU101_Final_Jan 2011.pdf</a>. phx.corporate-ir.net. [zarchiwizowane z <a rel="nofollow" class="external text" href="http://phx.corporate-ir.net/External.File?item=UGFyZW50SUQ9ODUyOTR8Q2hpbGRJRD0tMXxUeXBlPTM=&t=1">tego adresu</a> (2014-12-28)].</cite></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><a href="#cite_ref-41">↑</a></span> <span class="reference-text"><cite class="citation web">Anand Lal Shimpi: <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/5493/amd-outlines-hsa-roadmap-unified-memory-for-cpugpu-in-2013-hsa-gpus-in-2014">AMD Outlines HSA Roadmap: Unified Memory for CPU/GPU in 2013, HSA GPUs in 2014</a>. AnandTech. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-42"><span class="mw-cite-backlink"><a href="#cite_ref-42">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="https://www.benchmark.pl/testy_i_recenzje/przeglad-cpu-w-laptopach/strona/16827.html"><i>CPU w laptopach - mobilne procesory. Mobilne APU AMD</i></a> [online], www.benchmark.pl<span class="accessdate"> [dostęp 2020-07-11]</span><span class="Z3988" title="ctx_ver=Z39.88-2004&rft.gengre=book&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.btitle=CPU+w+laptopach+-+mobilne+procesory.+Mobilne+APU+AMD&rft_id=https%3A%2F%2Fwww.benchmark.pl%2Ftesty_i_recenzje%2Fprzeglad-cpu-w-laptopach%2Fstrona%2F16827.html" style="display:none"> </span> <span class="lang-list tylko-pl">(<abbr title="Treść w języku polskim">pol.</abbr>)</span>.</cite></span> </li> <li id="cite_note-43"><span class="mw-cite-backlink"><a href="#cite_ref-43">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/Cores/Llano.html">AMD Llano core</a>. Cpu-world.com, 2014-03-17. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-AMDHSARoadmap-44"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-AMDHSARoadmap_44-0">a</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-1">b</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-2">c</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-3">d</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-4">e</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-5">f</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-6">g</a></sup> <sup><a href="#cite_ref-AMDHSARoadmap_44-7">h</a></sup></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://developer.amd.com/afds/assets/keynotes/Phil%20Rogers%20Keynote-FINAL.pdf">The programmer's guide to the APU galaxy</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-AnandTechFusion-45"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-AnandTechFusion_45-0">a</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-1">b</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-2">c</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-3">d</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-4">e</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-5">f</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-6">g</a></sup> <sup><a href="#cite_ref-AnandTechFusion_45-7">h</a></sup></span> <span class="reference-text"> <cite class="citation web"><a rel="nofollow" class="external text" href="http://www.anandtech.com/show/5493/amd-outlines-hsa-roadmap-unified-memory-for-cpugpu-in-2013-hsa-gpus-in-2014">AMD Outlines HSA Roadmap: Unified Memory for CPU/GPU in 2013, HSA GPUs in 2014</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-RealWorldTechFusion-46"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-RealWorldTechFusion_46-0">a</a></sup> <sup><a href="#cite_ref-RealWorldTechFusion_46-1">b</a></sup> <sup><a href="#cite_ref-RealWorldTechFusion_46-2">c</a></sup> <sup><a href="#cite_ref-RealWorldTechFusion_46-3">d</a></sup></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://realworldtech.com/page.cfm?ArticleID=RWT062711124854&p=2">AMD Fusion Architecture and Llano</a>. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><a href="#cite_ref-47">↑</a></span> <span class="reference-text"><cite class="citation web">Anand Lal Shimpi: <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4476/amd-a83850-review/3">The AMD A8-3850 Review: Llano on the Desktop</a>. Anandtech, 30 czerwca 2011. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><a href="#cite_ref-48">↑</a></span> <span class="reference-text"><cite class="citation web"><a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/amd-a8-3850-llano,2975-19.html">Conclusion - AMD A8-3850 Review: Llano Rocks Entry-Level Desktops</a>. 30 czerwca 2011. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><a href="#cite_ref-49">↑</a></span> <span class="reference-text"><cite class="citation web">Anand Lal Shimpi: <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4476/amd-a83850-review/5">The AMD A8-3850 Review: Llano on the Desktop</a>. AnandTech. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><a href="#cite_ref-50">↑</a></span> <span class="reference-text"><cite class="citation web">Anand Lal Shimpi: <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/6332/amd-trinity-a10-5800k-a8-5600k-review-part-1">AMD A10-5800K & A8-5600K Review: Trinity on the Desktop, Part 1</a>. AnandTech. <span class="lang-list">(<abbr title="Treść w języku angielskim (English)">ang.</abbr>)</span>.</cite></span> </li> <li id="cite_note-amd_fusion_release-51"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-amd_fusion_release_51-0">a</a></sup> <sup><a href="#cite_ref-amd_fusion_release_51-1">b</a></sup></span> <span class="reference-text"><cite class="citation web">AMD: <a rel="nofollow" class="external text" href="https://www.amd.com/us/press-releases/Pages/amd-fusion-apu-era-2011jan04.aspx">AMD Fusion APU Era Begins</a>. 4 stycznia 2011. [dostęp 2013-08-24].</cite></span> </li> <li id="cite_note-amd_desna_release-52"><span class="mw-cite-backlink">↑ <sup><a href="#cite_ref-amd_desna_release_52-0">a</a></sup> <sup><a href="#cite_ref-amd_desna_release_52-1">b</a></sup></span> <span class="reference-text"><cite class="citation web">Sorin Nita: <a rel="nofollow" class="external text" href="http://news.softpedia.com/news/AMD-Releases-More-Details-Regarding-the-Desna-Tablet-APU-203987.shtml">AMD Releases More Details Regarding the Desna Tablet APU</a>. 1 June 2011.</cite></span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><a href="#cite_ref-53">↑</a></span> <span class="reference-text"><cite class="citation web">AMD: <a rel="nofollow" class="external text" href="https://www.amd.com/us/press-releases/Pages/new-amd-z-series-apu-2012oct9.aspx">New AMD Z-Series APU for Tablets Enables Immersive Experience for Upcoming Microsoft Windows 8 Platforms</a>. 9 października 2013.</cite></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><a href="#cite_ref-54">↑</a></span> <span class="reference-text">Shvets, Anthony (10 października 2012). "AMD announces Z-60 APU for tablets".</span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><a href="#cite_ref-55">↑</a></span> <span class="reference-text"><cite class="citation web">Joel Hruska: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200923003304/https://hothardware.com/news/amds-hondo-will-challenge-intels-atom-for-windows-8-tablet-designs">AMD's Hondo Z-Series APU To Challenge Intel's Atom In Windows 8 Tablet Market</a>. 9 października 2012. [dostęp 2020-07-10]. [zarchiwizowane z <a rel="nofollow" class="external text" href="http://hothardware.com/News/AMDs-Hondo-Will-Challenge-Intels-Atom-For-Windows-8-Tablet-Designs/">tego adresu</a> (23 września 2020)].</cite></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><a href="#cite_ref-56">↑</a></span> <span class="reference-text"><cite class="citation web">Anton Shilov: <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130209024505/http://www.xbitlabs.com/news/mobile/display/20121009095121_AMD_Introduces_Its_First_Accelerated_Processing_Unit_for_Media_Tablets.html">AMD Introduces Its First Accelerated Processing Unit for Media Tablets</a>. 9 października 2012. [zarchiwizowane z <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/mobile/display/20121009095121_AMD_Introduces_Its_First_Accelerated_Processing_Unit_for_Media_Tablets.html">tego adresu</a> (9 lutego 2013)].</cite></span> </li> <li id="cite_note-Deccan-57"><span class="mw-cite-backlink"><a href="#cite_ref-Deccan_57-0">↑</a></span> <span class="reference-text"><cite class="citation web">Charlie Demerjian: <a rel="nofollow" class="external text" href="http://semiaccurate.com/2011/11/15/exclusive-amd-kills-wichita-and-krishna/">Exclusive: AMD kills Wichita and Krishna</a>. SemiAccurate.</cite></span> </li> </ol></div></div> <div class="navbox do-not-make-smaller mw-collapsible mw-collapsed" data-expandtext="pokaż" data-collapsetext="ukryj"><style data-mw-deduplicate="TemplateStyles:r74983602">.mw-parser-output .navbox{border:1px solid var(--border-color-base,#a2a9b1);margin:auto;text-align:center;padding:3px;margin-top:1em;clear:both}.mw-parser-output table.navbox:not(.pionowy){width:100%}.mw-parser-output .navbox+.navbox{border-top:0;margin-top:0}.mw-parser-output .navbox.pionowy{width:250px;float:right;clear:right;margin:0 0 0.4em 1.4em}.mw-parser-output .navbox.pionowy .before,.mw-parser-output .navbox.pionowy .after{padding:0.5em 0;text-align:center}.mw-parser-output .navbox>.caption,.mw-parser-output .navbox>tbody>tr>th{background:#ccf;text-align:center;font-weight:bold}.mw-parser-output .navbox .tnavbar{font-weight:normal;font-size:xx-small;white-space:nowrap;padding:0}.mw-parser-output .navbox>.tnavbar{margin-left:1em;float:left}.mw-parser-output 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29000">Am29000</a></li> <li><a href="/wiki/AMD_Am286" title="AMD Am286">Am286</a></li> <li><a href="/wiki/AMD_Am386" title="AMD Am386">Am386</a></li> <li><a href="/wiki/AMD_Am486" title="AMD Am486">Am486</a></li> <li><a href="/wiki/AMD_Am5x86" title="AMD Am5x86">Am5x86</a></li> <li><a href="/wiki/AMD_K5" title="AMD K5">K5</a></li> <li><a href="/wiki/AMD_K6" title="AMD K6">K6</a></li> <li><a href="/wiki/AMD_K6-2" title="AMD K6-2">K6-2</a></li> <li><a href="/wiki/AMD_K6-III" title="AMD K6-III">K6-III</a></li> <li><a href="/wiki/AMD_Duron" title="AMD Duron">Duron</a></li> <li><a href="/wiki/AMD_Athlon" title="AMD Athlon">Athlon</a></li> <li><a href="/wiki/AMD_Athlon#Athlon_XP" title="AMD Athlon">Athlon XP</a></li> <li><a href="/w/index.php?title=Geode&action=edit&redlink=1" class="new" title="Geode (strona nie istnieje)">Geode</a></li> <li><a href="/wiki/AMD_Sempron" title="AMD Sempron">Sempron</a></li> <li><a href="/wiki/AMD_Athlon" title="AMD Athlon">Athlon 64</a></li> <li><a href="/wiki/AMD_Athlon" title="AMD Athlon">Athlon 64 X2</a></li> <li><a href="/wiki/AMD_Athlon" title="AMD Athlon">Athlon X2</a></li> <li><a href="/wiki/Athlon_64_FX" title="Athlon 64 FX">Athlon 64 FX</a></li> <li><a href="/wiki/Turion_64" title="Turion 64">Turion 64</a></li> <li><a href="/wiki/Turion_64_X2" title="Turion 64 X2">Turion 64 X2</a></li> <li><a href="/wiki/AMD_Opteron" title="AMD Opteron">Opteron</a></li> <li><a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a></li> <li><a href="/wiki/Lista_procesor%C3%B3w_AMD_FX" title="Lista procesorów AMD FX">FX</a></li> <li><a href="/wiki/AMD_Athlon_Neo" title="AMD Athlon Neo">Athlon Neo</a></li></ul> </td></tr><tr class="a1_2"><th class="navbox-group opis" scope="row">Obecnie produkowane</th><td class="navbox-list spis hlist navbox-even"> <ul><li><a href="/wiki/AMD_Athlon" title="AMD Athlon">Athlon</a></li> <li><a href="/w/index.php?title=AMD_Epyc&action=edit&redlink=1" class="new" title="AMD Epyc (strona nie istnieje)">Epyc</a></li> <li><a href="/wiki/AMD_Ryzen" title="AMD Ryzen">Ryzen</a></li> <li><a href="/wiki/AMD_Ryzen" title="AMD Ryzen">Threadripper</a></li></ul> </td></tr></tbody></table></div></div><div class="tr a2 mw-collapsible mw-collapsed" data-expandtext="pokaż" data-collapsetext="ukryj"><span class="fakebar"></span><div class="navbox-group opis">Gniazda pod procesory AMD</div><div class="mw-collapsible-content"><table class="a2 inner-standard"><tbody><tr class="a2_1"><th class="navbox-group opis" scope="row">Desktopowe</th><td class="navbox-list spis hlist navbox-odd"> <ul><li><a href="/wiki/Super_Socket_7" title="Super Socket 7">Super Socket 7</a></li> <li><a href="/wiki/Slot_A" title="Slot A">Slot A</a></li> <li><a href="/wiki/Socket_A" title="Socket A">Socket A</a></li> <li><a href="/wiki/Socket_754" title="Socket 754">Socket 754</a></li> <li><a href="/wiki/Socket_939" title="Socket 939">Socket 939</a></li> <li><a href="/wiki/Socket_940" title="Socket 940">Socket 940</a></li> <li><a href="/wiki/Socket_AM2" title="Socket AM2">Socket AM2</a></li> <li><a href="/wiki/Socket_F" title="Socket F">Socket F</a></li> <li><a href="/wiki/Socket_AM2%2B" title="Socket AM2+">Socket AM2+</a></li> <li><a href="/wiki/Socket_F%2B" title="Socket F+">Socket F+</a></li> <li><a href="/wiki/Socket_AM3" title="Socket AM3">Socket AM3</a></li> <li><a href="/wiki/Socket_AM3%2B" title="Socket AM3+">Socket AM3+</a></li> <li><a href="/w/index.php?title=Socket_FM1&action=edit&redlink=1" class="new" title="Socket FM1 (strona nie istnieje)">Socket FM1</a></li> <li><a href="/w/index.php?title=Socket_FM2&action=edit&redlink=1" class="new" title="Socket FM2 (strona nie istnieje)">Socket FM2</a></li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a></li> <li><a href="/wiki/Socket_TR4" title="Socket TR4">Socket TR4</a></li> <li><a href="/wiki/Socket_sTRX4" title="Socket sTRX4">Socket sTRX4</a></li> <li><a href="/wiki/Socket_AM5" title="Socket AM5">Socket AM5</a></li></ul> </td></tr><tr class="a2_2"><th class="navbox-group opis" scope="row">Mobilne</th><td class="navbox-list spis hlist navbox-even"> <ul><li><a href="/wiki/Socket_A" title="Socket A">Socket A</a></li> <li><a href="/wiki/Socket_563" title="Socket 563">Socket 563</a></li> <li><a href="/wiki/Socket_754" title="Socket 754">Socket 754</a></li> <li><a href="/wiki/Socket_S1" title="Socket S1">Socket S1</a></li> <li><a href="/w/index.php?title=Socket_FS1&action=edit&redlink=1" class="new" title="Socket FS1 (strona nie istnieje)">Socket FS1</a></li></ul> </td></tr><tr class="a2_3"><th class="navbox-group opis" scope="row">Serwerowe</th><td class="navbox-list spis hlist navbox-odd"> <ul><li><a href="/wiki/Socket_A" title="Socket A">Socket A</a></li> <li><a href="/wiki/Socket_940" title="Socket 940">Socket 940</a></li> <li><a href="/wiki/Socket_F" title="Socket F">Socket F</a></li> <li><a href="/wiki/Socket_F%2B" title="Socket F+">Socket F+</a></li> <li><a href="/wiki/Socket_G3" title="Socket G3">Socket G3</a> (anulowany)</li> <li><a href="/w/index.php?title=Socket_G34&action=edit&redlink=1" class="new" title="Socket G34 (strona nie istnieje)">Socket G34</a></li> <li><a href="/w/index.php?title=Socket_C32&action=edit&redlink=1" class="new" title="Socket C32 (strona nie istnieje)">Socket C32</a></li> <li><a href="/wiki/Socket_SP3" title="Socket SP3">Socket SP3</a></li></ul> </td></tr></tbody></table></div></div><div class="tr a3 mw-collapsible mw-collapsed" data-expandtext="pokaż" data-collapsetext="ukryj"><span class="fakebar"></span><div class="navbox-group opis"><a href="/wiki/Procesor_graficzny" title="Procesor graficzny">Procesory graficzne</a> ATI Technologies</div><div class="mw-collapsible-content a3 hlist navbox-list spis navbox-even"> <ul><li><b>2D Chip:</b> <a href="/w/index.php?title=ATI_Mach&action=edit&redlink=1" class="new" title="ATI Mach (strona nie istnieje)">Mach</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 3–6:</b> <a href="/w/index.php?title=ATI_Rage&action=edit&redlink=1" class="new" title="ATI Rage (strona nie istnieje)">Rage</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 7:</b> <a href="/w/index.php?title=Radeon_R100&action=edit&redlink=1" class="new" title="Radeon R100 (strona nie istnieje)">Radeon R100</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 8:</b> <a href="/w/index.php?title=Radeon_R200&action=edit&redlink=1" class="new" title="Radeon R200 (strona nie istnieje)">Radeon R200</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 9:</b> <a href="/wiki/Radeon_R300" title="Radeon R300">Radeon R300</a></li> <li><a href="/w/index.php?title=Radeon_R420&action=edit&redlink=1" class="new" title="Radeon R420 (strona nie istnieje)">R420</a></li> <li><a href="/wiki/Radeon_R520" title="Radeon R520">R520</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 10:</b> <a href="/wiki/Radeon_R600" title="Radeon R600">Radeon R600</a></li> <li><a href="/wiki/Radeon_R700" title="Radeon R700">R700</a></li> <li><b><a href="/wiki/DirectX" title="DirectX">DirectX</a> 11:</b> <a href="/w/index.php?title=Radeon_R800&action=edit&redlink=1" class="new" title="Radeon R800 (strona nie istnieje)">Radeon R800</a></li></ul> </div></div><div class="tr a4 mw-collapsible mw-collapsed" data-expandtext="pokaż" data-collapsetext="ukryj"><span class="fakebar"></span><div class="navbox-group opis">Inne technologie AMD-ATI</div><div class="mw-collapsible-content"><table class="a4 inner-standard"><tbody><tr class="a4_1"><th class="navbox-group opis" scope="row"><a href="/wiki/Chipset" title="Chipset">Chipset</a></th><td class="navbox-list spis hlist navbox-odd"> <ul><li><a href="/w/index.php?title=Radeon_R100&action=edit&redlink=1" class="new" title="Radeon R100 (strona nie istnieje)">IGP3xx</a></li> <li><a href="/w/index.php?title=Radeon_R200&action=edit&redlink=1" class="new" title="Radeon R200 (strona nie istnieje)">9000/9100 IGP</a></li> <li><a href="/wiki/Xpress_200" title="Xpress 200">Xpress 200</a></li> <li><a href="/w/index.php?title=Xpress_3200&action=edit&redlink=1" class="new" title="Xpress 3200 (strona nie istnieje)">Xpress 3200</a></li> <li><a href="/w/index.php?title=AMD_580&action=edit&redlink=1" class="new" title="AMD 580 (strona nie istnieje)">580X</a></li> <li><a href="/w/index.php?title=AMD_690&action=edit&redlink=1" class="new" title="AMD 690 (strona nie istnieje)">690G</a></li> <li><a href="/w/index.php?title=AMD_700&action=edit&redlink=1" class="new" title="AMD 700 (strona nie istnieje)">790X</a></li></ul> </td></tr><tr class="a4_2"><th class="navbox-group opis" scope="row">Multi-GPU</th><td class="navbox-list spis hlist navbox-even"> <ul><li><a href="/w/index.php?title=ATI_Multi_Rendering&action=edit&redlink=1" class="new" title="ATI Multi Rendering (strona nie istnieje)">Multi-rendering</a></li> <li><a href="/wiki/CrossFire" title="CrossFire">CrossFire</a></li></ul> </td></tr><tr class="a4_3"><th class="navbox-group opis" scope="row"><a href="/wiki/Stacja_robocza" title="Stacja robocza">Stacja robocza</a> i <a href="/w/index.php?title=High_Performance_Computing&action=edit&redlink=1" class="new" title="High Performance Computing (strona nie istnieje)">HPC</a></th><td class="navbox-list spis hlist navbox-odd"> <ul><li><a href="/wiki/AMD_FirePro" title="AMD FirePro">FireGL</a></li> <li><a href="/w/index.php?title=ATI_FireMV&action=edit&redlink=1" class="new" title="ATI FireMV (strona nie istnieje)">FireMV</a></li> <li><a href="/w/index.php?title=AMD_Stream_Procesor&action=edit&redlink=1" class="new" title="AMD Stream Procesor (strona nie istnieje)">FireStream</a></li></ul> </td></tr><tr class="a4_4"><th class="navbox-group opis" scope="row"><a href="/wiki/Elektronika_u%C5%BCytkowa" title="Elektronika użytkowa">Elektronika użytkowa</a></th><td class="navbox-list spis hlist navbox-even"> <ul><li><a href="/w/index.php?title=All-In-Wonder&action=edit&redlink=1" class="new" title="All-In-Wonder (strona nie istnieje)">All-In-Wonder</a></li> <li><a href="/w/index.php?title=Imageon&action=edit&redlink=1" class="new" title="Imageon (strona nie istnieje)">Imageon</a></li> <li><a href="/w/index.php?title=Xilleon&action=edit&redlink=1" class="new" title="Xilleon (strona nie istnieje)">Xilleon</a></li></ul> </td></tr><tr class="a4_5"><th class="navbox-group opis" scope="row"><a href="/wiki/MISC" title="MISC">MISC</a></th><td class="navbox-list spis hlist navbox-odd"> <ul><li><a href="/wiki/AVIVO" title="AVIVO">AVIVO</a></li> <li><a href="/w/index.php?title=Close_to_Metal&action=edit&redlink=1" class="new" title="Close to Metal (strona nie istnieje)">CTM</a></li> <li><a href="/w/index.php?title=HLSL2GLSL&action=edit&redlink=1" class="new" title="HLSL2GLSL (strona nie istnieje)">HLSL2GLSL</a></li> <li><a href="/w/index.php?title=HyperMemory&action=edit&redlink=1" class="new" title="HyperMemory (strona nie istnieje)">HyperMemory</a></li> <li><a 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