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<button class="button is-small is-link">Go</button> </div> </div> </form> </div> </div> <ol class="breathe-horizontal" start="1"> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2109.01188">arXiv:2109.01188</a> <span> [<a href="https://arxiv.org/pdf/2109.01188">pdf</a>, <a href="https://arxiv.org/format/2109.01188">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> NVMExplorer: A Framework for Cross-Stack Comparisons of Embedded Non-Volatile Memories </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Pentecost%2C+L">Lillian Pentecost</a>, <a href="/search/cs?searchtype=author&query=Hankin%2C+A">Alexander Hankin</a>, <a href="/search/cs?searchtype=author&query=Donato%2C+M">Marco Donato</a>, <a href="/search/cs?searchtype=author&query=Hempstead%2C+M">Mark Hempstead</a>, <a href="/search/cs?searchtype=author&query=Wei%2C+G">Gu-Yeon Wei</a>, <a href="/search/cs?searchtype=author&query=Brooks%2C+D">David Brooks</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2109.01188v2-abstract-short" style="display: inline;"> Repeated off-chip memory accesses to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory (eNVM) technologies is providing many potential candidates to… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2109.01188v2-abstract-full').style.display = 'inline'; document.getElementById('2109.01188v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2109.01188v2-abstract-full" style="display: none;"> Repeated off-chip memory accesses to DRAM drive up operating power for data-intensive applications, and SRAM technology scaling and leakage power limits the efficiency of embedded memories. Future on-chip storage will need higher density and energy efficiency, and the actively expanding field of emerging, embeddable non-volatile memory (eNVM) technologies is providing many potential candidates to satisfy this need. Each technology proposal presents distinct trade-offs in terms of density, read, write, and reliability characteristics, and we present a comprehensive framework for navigating and quantifying these design trade-offs alongside realistic system constraints and application-level impacts. This work evaluates eNVM-based storage for a range of application and system contexts including machine learning on the edge, graph analytics, and general purpose cache hierarchy, in addition to describing a freely available (http://nvmexplorer.seas.harvard.edu/) set of tools for application experts, system designers, and device experts to better understand, compare, and quantify the next generation of embedded memory solutions. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2109.01188v2-abstract-full').style.display = 'none'; document.getElementById('2109.01188v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 11 January, 2022; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 2 September, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">18 pages, 14 figures, 3 tables</span> </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">ACM Class:</span> B.3; I.6 </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2106.11757">arXiv:2106.11757</a> <span> [<a href="https://arxiv.org/pdf/2106.11757">pdf</a>, <a href="https://arxiv.org/format/2106.11757">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Distributed, Parallel, and Cluster Computing">cs.DC</span> </div> </div> <p class="title is-5 mathjax"> Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Sharifi%2C+M+M">Mohammad Mehdi Sharifi</a>, <a href="/search/cs?searchtype=author&query=Pentecost%2C+L">Lillian Pentecost</a>, <a href="/search/cs?searchtype=author&query=Rajaei%2C+R">Ramin Rajaei</a>, <a href="/search/cs?searchtype=author&query=Kazemi%2C+A">Arman Kazemi</a>, <a href="/search/cs?searchtype=author&query=Lou%2C+Q">Qiuwen Lou</a>, <a href="/search/cs?searchtype=author&query=Wei%2C+G">Gu-Yeon Wei</a>, <a href="/search/cs?searchtype=author&query=Brooks%2C+D">David Brooks</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">X. Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Donato%2C+M">Marco Donato</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2106.11757v1-abstract-short" style="display: inline;"> The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device cha… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2106.11757v1-abstract-full').style.display = 'inline'; document.getElementById('2106.11757v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2106.11757v1-abstract-full" style="display: none;"> The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm^2 and sub-2ns read access latency without loss in application accuracy. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2106.11757v1-abstract-full').style.display = 'none'; document.getElementById('2106.11757v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 June, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted at ISLPED 2021</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2011.14203">arXiv:2011.14203</a> <span> [<a href="https://arxiv.org/pdf/2011.14203">pdf</a>, <a href="https://arxiv.org/format/2011.14203">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> </div> </div> <p class="title is-5 mathjax"> EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Tambe%2C+T">Thierry Tambe</a>, <a href="/search/cs?searchtype=author&query=Hooper%2C+C">Coleman Hooper</a>, <a href="/search/cs?searchtype=author&query=Pentecost%2C+L">Lillian Pentecost</a>, <a href="/search/cs?searchtype=author&query=Jia%2C+T">Tianyu Jia</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+E">En-Yu Yang</a>, <a href="/search/cs?searchtype=author&query=Donato%2C+M">Marco Donato</a>, <a href="/search/cs?searchtype=author&query=Sanh%2C+V">Victor Sanh</a>, <a href="/search/cs?searchtype=author&query=Whatmough%2C+P+N">Paul N. Whatmough</a>, <a href="/search/cs?searchtype=author&query=Rush%2C+A+M">Alexander M. Rush</a>, <a href="/search/cs?searchtype=author&query=Brooks%2C+D">David Brooks</a>, <a href="/search/cs?searchtype=author&query=Wei%2C+G">Gu-Yeon Wei</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2011.14203v5-abstract-short" style="display: inline;"> Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks. However, their hefty computational and memory demands make them challenging to deploy to resource-constrained edge platforms with strict latency requirements. We present EdgeBERT, an in-depth algorithm-hardware co-design for latency-aware energy optimi… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2011.14203v5-abstract-full').style.display = 'inline'; document.getElementById('2011.14203v5-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2011.14203v5-abstract-full" style="display: none;"> Transformer-based language models such as BERT provide significant accuracy improvement for a multitude of natural language processing (NLP) tasks. However, their hefty computational and memory demands make them challenging to deploy to resource-constrained edge platforms with strict latency requirements. We present EdgeBERT, an in-depth algorithm-hardware co-design for latency-aware energy optimization for multi-task NLP. EdgeBERT employs entropy-based early exit predication in order to perform dynamic voltage-frequency scaling (DVFS), at a sentence granularity, for minimal energy consumption while adhering to a prescribed target latency. Computation and memory footprint overheads are further alleviated by employing a calibrated combination of adaptive attention span, selective network pruning, and floating-point quantization. Furthermore, in order to maximize the synergistic benefits of these algorithms in always-on and intermediate edge computing settings, we specialize a 12nm scalable hardware accelerator system, integrating a fast-switching low-dropout voltage regulator (LDO), an all-digital phase-locked loop (ADPLL), as well as, high-density embedded non-volatile memories (eNVMs) wherein the sparse floating-point bit encodings of the shared multi-task parameters are carefully stored. Altogether, latency-aware multi-task NLP inference acceleration on the EdgeBERT hardware system generates up to 7x, 2.5x, and 53x lower energy compared to the conventional inference without early stopping, the latency-unbounded early exit approach, and CUDA adaptations on an Nvidia Jetson Tegra X2 mobile GPU, respectively. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2011.14203v5-abstract-full').style.display = 'none'; document.getElementById('2011.14203v5-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 5 September, 2021; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 28 November, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2020. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">12 pages plus references. Paper to appear at the 54th IEEE/ACM International Symposium on Microarchitecture (MICRO 2021)</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1910.01500">arXiv:1910.01500</a> <span> [<a href="https://arxiv.org/pdf/1910.01500">pdf</a>, <a href="https://arxiv.org/format/1910.01500">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Performance">cs.PF</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">stat.ML</span> </div> </div> <p class="title is-5 mathjax"> MLPerf Training Benchmark </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Mattson%2C+P">Peter Mattson</a>, <a href="/search/cs?searchtype=author&query=Cheng%2C+C">Christine Cheng</a>, <a href="/search/cs?searchtype=author&query=Coleman%2C+C">Cody Coleman</a>, <a href="/search/cs?searchtype=author&query=Diamos%2C+G">Greg Diamos</a>, <a href="/search/cs?searchtype=author&query=Micikevicius%2C+P">Paulius Micikevicius</a>, <a href="/search/cs?searchtype=author&query=Patterson%2C+D">David Patterson</a>, <a href="/search/cs?searchtype=author&query=Tang%2C+H">Hanlin Tang</a>, <a href="/search/cs?searchtype=author&query=Wei%2C+G">Gu-Yeon Wei</a>, <a href="/search/cs?searchtype=author&query=Bailis%2C+P">Peter Bailis</a>, <a href="/search/cs?searchtype=author&query=Bittorf%2C+V">Victor Bittorf</a>, <a href="/search/cs?searchtype=author&query=Brooks%2C+D">David Brooks</a>, <a href="/search/cs?searchtype=author&query=Chen%2C+D">Dehao Chen</a>, <a href="/search/cs?searchtype=author&query=Dutta%2C+D">Debojyoti Dutta</a>, <a href="/search/cs?searchtype=author&query=Gupta%2C+U">Udit Gupta</a>, <a href="/search/cs?searchtype=author&query=Hazelwood%2C+K">Kim Hazelwood</a>, <a href="/search/cs?searchtype=author&query=Hock%2C+A">Andrew Hock</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+X">Xinyuan Huang</a>, <a href="/search/cs?searchtype=author&query=Ike%2C+A">Atsushi Ike</a>, <a href="/search/cs?searchtype=author&query=Jia%2C+B">Bill Jia</a>, <a href="/search/cs?searchtype=author&query=Kang%2C+D">Daniel Kang</a>, <a href="/search/cs?searchtype=author&query=Kanter%2C+D">David Kanter</a>, <a href="/search/cs?searchtype=author&query=Kumar%2C+N">Naveen Kumar</a>, <a href="/search/cs?searchtype=author&query=Liao%2C+J">Jeffery Liao</a>, <a href="/search/cs?searchtype=author&query=Ma%2C+G">Guokai Ma</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+D">Deepak Narayanan</a> , et al. (12 additional authors not shown) </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1910.01500v3-abstract-short" style="display: inline;"> Machine learning (ML) needs industry-standard performance benchmarks to support design and competitive evaluation of the many emerging software and hardware solutions for ML. But ML training presents three unique benchmarking challenges absent from other domains: optimizations that improve training throughput can increase the time to solution, training is stochastic and time to solution exhibits h… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1910.01500v3-abstract-full').style.display = 'inline'; document.getElementById('1910.01500v3-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1910.01500v3-abstract-full" style="display: none;"> Machine learning (ML) needs industry-standard performance benchmarks to support design and competitive evaluation of the many emerging software and hardware solutions for ML. But ML training presents three unique benchmarking challenges absent from other domains: optimizations that improve training throughput can increase the time to solution, training is stochastic and time to solution exhibits high variance, and software and hardware systems are so diverse that fair benchmarking with the same binary, code, and even hyperparameters is difficult. We therefore present MLPerf, an ML benchmark that overcomes these challenges. Our analysis quantitatively evaluates MLPerf's efficacy at driving performance and scalability improvements across two rounds of results from multiple vendors. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1910.01500v3-abstract-full').style.display = 'none'; document.getElementById('1910.01500v3-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 2 March, 2020; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 2 October, 2019; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2019. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">MLSys 2020</span> </p> </li> </ol> <div class="is-hidden-tablet">  <span class="help" style="display: inline-block;"><a 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