CINXE.COM

<!DOCTYPE html> <html class="client-nojs vector-feature-language-in-header-enabled vector-feature-language-in-main-page-header-disabled vector-feature-sticky-header-disabled vector-feature-page-tools-pinned-disabled vector-feature-toc-pinned-clientpref-1 vector-feature-main-menu-pinned-disabled vector-feature-limited-width-clientpref-1 vector-feature-limited-width-content-enabled vector-feature-custom-font-size-clientpref-1 vector-feature-appearance-pinned-clientpref-1 vector-feature-night-mode-enabled skin-theme-clientpref-day vector-toc-available" lang="en" dir="ltr"> <head> <meta charset="UTF-8"> <title>Intel Core - Wikipedia</title> <script>(function(){var className="client-js vector-feature-language-in-header-enabled vector-feature-language-in-main-page-header-disabled vector-feature-sticky-header-disabled vector-feature-page-tools-pinned-disabled vector-feature-toc-pinned-clientpref-1 vector-feature-main-menu-pinned-disabled vector-feature-limited-width-clientpref-1 vector-feature-limited-width-content-enabled vector-feature-custom-font-size-clientpref-1 vector-feature-appearance-pinned-clientpref-1 vector-feature-night-mode-enabled skin-theme-clientpref-day vector-toc-available";var cookie=document.cookie.match(/(?:^|; )enwikimwclientpreferences=([^;]+)/);if(cookie){cookie[1].split('%2C').forEach(function(pref){className=className.replace(new RegExp('(^| )'+pref.replace(/-clientpref-\w+$|[^\w-]+/g,'')+'-clientpref-\\w+( |$)'),'$1'+pref+'$2');});}document.documentElement.className=className;}());RLCONF={"wgBreakFrames":false,"wgSeparatorTransformTable":["",""],"wgDigitTransformTable":["",""],"wgDefaultDateFormat":"dmy", "wgMonthNames":["","January","February","March","April","May","June","July","August","September","October","November","December"],"wgRequestId":"88a5a28a-25b3-4f93-b11c-181a247a06e5","wgCanonicalNamespace":"","wgCanonicalSpecialPageName":false,"wgNamespaceNumber":0,"wgPageName":"Intel_Core","wgTitle":"Intel Core","wgCurRevisionId":1259288623,"wgRevisionId":1259288623,"wgArticleId":24538587,"wgIsArticle":true,"wgIsRedirect":false,"wgAction":"view","wgUserName":null,"wgUserGroups":["*"],"wgCategories":["CS1 maint: unfit URL","Webarchive template wayback links","Articles with short description","Short description is different from Wikidata","Use mdy dates from October 2018","Use American English from October 2020","All Wikipedia articles written in American English","All articles with unsourced statements","Articles with unsourced statements from October 2011","Articles to be expanded from April 2014","All articles to be expanded","Articles to be expanded from January 2017", "Articles with unsourced statements from July 2018","All articles that may contain original research","Articles that may contain original research from June 2024","Articles to be expanded from October 2024","Articles with empty sections from October 2024","All articles with empty sections","Articles to be expanded from January 2023","Articles with excerpts","Intel x86 microprocessors","Computer-related introductions in 2006","64-bit microprocessors"],"wgPageViewLanguage":"en","wgPageContentLanguage":"en","wgPageContentModel":"wikitext","wgRelevantPageName":"Intel_Core","wgRelevantArticleId":24538587,"wgIsProbablyEditable":true,"wgRelevantPageIsProbablyEditable":true,"wgRestrictionEdit":[],"wgRestrictionMove":[],"wgRedirectedFrom":"Intel_Core_i7","wgNoticeProject":"wikipedia","wgCiteReferencePreviewsActive":false,"wgFlaggedRevsParams":{"tags":{"status":{"levels":1}}},"wgMediaViewerOnClick":true,"wgMediaViewerEnabledByDefault":true,"wgPopupsFlags":0,"wgVisualEditor":{"pageLanguageCode": "en","pageLanguageDir":"ltr","pageVariantFallbacks":"en"},"wgMFDisplayWikibaseDescriptions":{"search":true,"watchlist":true,"tagline":false,"nearby":true},"wgWMESchemaEditAttemptStepOversample":false,"wgWMEPageLength":300000,"wgInternalRedirectTargetUrl":"/wiki/Intel_Core#Core_i3/i5/i7/i9","wgRelatedArticlesCompat":[],"wgCentralAuthMobileDomain":false,"wgEditSubmitButtonLabelPublish":true,"wgULSPosition":"interlanguage","wgULSisCompactLinksEnabled":false,"wgVector2022LanguageInHeader":true,"wgULSisLanguageSelectorEmpty":false,"wgWikibaseItemId":"Q19481932","wgCheckUserClientHintsHeadersJsApi":["brands","architecture","bitness","fullVersionList","mobile","model","platform","platformVersion"],"GEHomepageSuggestedEditsEnableTopics":true,"wgGETopicsMatchModeEnabled":false,"wgGEStructuredTaskRejectionReasonTextInputEnabled":false,"wgGELevelingUpEnabledForUser":false};RLSTATE={"ext.globalCssJs.user.styles":"ready","site.styles":"ready","user.styles":"ready","ext.globalCssJs.user":"ready", "user":"ready","user.options":"loading","ext.cite.styles":"ready","mediawiki.page.gallery.styles":"ready","skins.vector.search.codex.styles":"ready","skins.vector.styles":"ready","skins.vector.icons":"ready","jquery.tablesorter.styles":"ready","jquery.makeCollapsible.styles":"ready","ext.wikimediamessages.styles":"ready","ext.visualEditor.desktopArticleTarget.noscript":"ready","ext.uls.interlanguage":"ready","wikibase.client.init":"ready","ext.wikimediaBadges":"ready"};RLPAGEMODULES=["mediawiki.action.view.redirect","ext.cite.ux-enhancements","mediawiki.page.media","site","mediawiki.page.ready","jquery.tablesorter","jquery.makeCollapsible","mediawiki.toc","skins.vector.js","ext.centralNotice.geoIP","ext.centralNotice.startUp","ext.gadget.ReferenceTooltips","ext.gadget.switcher","ext.urlShortener.toolbar","ext.centralauth.centralautologin","mmv.bootstrap","ext.popups","ext.visualEditor.desktopArticleTarget.init","ext.visualEditor.targetLoader","ext.echo.centralauth","ext.eventLogging", "ext.wikimediaEvents","ext.navigationTiming","ext.uls.interface","ext.cx.eventlogging.campaigns","ext.cx.uls.quick.actions","wikibase.client.vector-2022","ext.checkUser.clientHints","ext.quicksurveys.init","ext.growthExperiments.SuggestedEditSession","wikibase.sidebar.tracking"];</script> <script>(RLQ=window.RLQ||[]).push(function(){mw.loader.impl(function(){return["user.options@12s5i",function($,jQuery,require,module){mw.user.tokens.set({"patrolToken":"+\\","watchToken":"+\\","csrfToken":"+\\"}); }];});});</script> <link rel="stylesheet" href="/w/load.php?lang=en&modules=ext.cite.styles%7Cext.uls.interlanguage%7Cext.visualEditor.desktopArticleTarget.noscript%7Cext.wikimediaBadges%7Cext.wikimediamessages.styles%7Cjquery.makeCollapsible.styles%7Cjquery.tablesorter.styles%7Cmediawiki.page.gallery.styles%7Cskins.vector.icons%2Cstyles%7Cskins.vector.search.codex.styles%7Cwikibase.client.init&only=styles&skin=vector-2022"> <script async="" src="/w/load.php?lang=en&modules=startup&only=scripts&raw=1&skin=vector-2022"></script> <meta name="ResourceLoaderDynamicStyles" content=""> <link rel="stylesheet" href="/w/load.php?lang=en&modules=site.styles&only=styles&skin=vector-2022"> <meta name="generator" content="MediaWiki 1.44.0-wmf.4"> <meta name="referrer" content="origin"> <meta name="referrer" content="origin-when-cross-origin"> <meta name="robots" content="max-image-preview:standard"> <meta name="format-detection" content="telephone=no"> <meta property="og:image" content="https://upload.wikimedia.org/wikipedia/commons/2/28/Intel_Core_2023_logo.png"> <meta property="og:image:width" content="1200"> <meta property="og:image:height" content="1200"> <meta property="og:image" content="https://upload.wikimedia.org/wikipedia/commons/2/28/Intel_Core_2023_logo.png"> <meta property="og:image:width" content="800"> <meta property="og:image:height" content="800"> <meta property="og:image:width" content="640"> <meta property="og:image:height" content="640"> <meta name="viewport" content="width=1120"> <meta property="og:title" content="Intel Core - Wikipedia"> <meta property="og:type" content="website"> <link rel="preconnect" href="//upload.wikimedia.org"> <link rel="alternate" media="only screen and (max-width: 640px)" href="//en.m.wikipedia.org/wiki/Intel_Core#Core_i3/i5/i7/i9"> <link rel="alternate" type="application/x-wiki" title="Edit this page" href="/w/index.php?title=Intel_Core&action=edit"> <link rel="apple-touch-icon" href="/static/apple-touch/wikipedia.png"> <link rel="icon" href="/static/favicon/wikipedia.ico"> <link rel="search" type="application/opensearchdescription+xml" href="/w/rest.php/v1/search" title="Wikipedia (en)"> <link rel="EditURI" type="application/rsd+xml" href="//en.wikipedia.org/w/api.php?action=rsd"> <link rel="canonical" href="https://en.wikipedia.org/wiki/Intel_Core#Core_i3/i5/i7/i9"> <link rel="license" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en"> <link rel="alternate" type="application/atom+xml" title="Wikipedia Atom feed" href="/w/index.php?title=Special:RecentChanges&feed=atom"> <link rel="dns-prefetch" href="//meta.wikimedia.org" /> <link rel="dns-prefetch" href="//login.wikimedia.org"> </head> <body class="skin--responsive skin-vector skin-vector-search-vue mediawiki ltr sitedir-ltr mw-hide-empty-elt ns-0 ns-subject mw-editable page-Intel_Core rootpage-Intel_Core skin-vector-2022 action-view"><a class="mw-jump-link" href="#bodyContent">Jump to content</a> <div class="vector-header-container"> <header class="vector-header mw-header"> <div class="vector-header-start"> <nav class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-dropdown" class="vector-dropdown vector-main-menu-dropdown vector-button-flush-left vector-button-flush-right" > <input type="checkbox" id="vector-main-menu-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-main-menu-dropdown" class="vector-dropdown-checkbox " aria-label="Main menu" > <label id="vector-main-menu-dropdown-label" for="vector-main-menu-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-menu mw-ui-icon-wikimedia-menu"></span> <span class="vector-dropdown-label-text">Main menu</span> </label> <div class="vector-dropdown-content"> <div id="vector-main-menu-unpinned-container" class="vector-unpinned-container"> <div id="vector-main-menu" class="vector-main-menu vector-pinnable-element"> <div class="vector-pinnable-header vector-main-menu-pinnable-header vector-pinnable-header-unpinned" data-feature-name="main-menu-pinned" data-pinnable-element-id="vector-main-menu" data-pinned-container-id="vector-main-menu-pinned-container" data-unpinned-container-id="vector-main-menu-unpinned-container" > <div class="vector-pinnable-header-label">Main menu</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-main-menu.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-main-menu.unpin">hide</button> </div> <div id="p-navigation" class="vector-menu mw-portlet mw-portlet-navigation" > <div class="vector-menu-heading"> Navigation </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="n-mainpage-description" class="mw-list-item"><a href="/wiki/Main_Page" title="Visit the main page [z]" accesskey="z"><span>Main page</span></a></li><li id="n-contents" class="mw-list-item"><a href="/wiki/Wikipedia:Contents" title="Guides to browsing Wikipedia"><span>Contents</span></a></li><li id="n-currentevents" class="mw-list-item"><a href="/wiki/Portal:Current_events" title="Articles related to current events"><span>Current events</span></a></li><li id="n-randompage" class="mw-list-item"><a href="/wiki/Special:Random" title="Visit a randomly selected article [x]" accesskey="x"><span>Random article</span></a></li><li id="n-aboutsite" class="mw-list-item"><a href="/wiki/Wikipedia:About" title="Learn about Wikipedia and how it works"><span>About Wikipedia</span></a></li><li id="n-contactpage" class="mw-list-item"><a href="//en.wikipedia.org/wiki/Wikipedia:Contact_us" title="How to contact Wikipedia"><span>Contact us</span></a></li> </ul> </div> </div> <div id="p-interaction" class="vector-menu mw-portlet mw-portlet-interaction" > <div class="vector-menu-heading"> Contribute </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="n-help" class="mw-list-item"><a href="/wiki/Help:Contents" title="Guidance on how to use and edit Wikipedia"><span>Help</span></a></li><li id="n-introduction" class="mw-list-item"><a href="/wiki/Help:Introduction" title="Learn how to edit Wikipedia"><span>Learn to edit</span></a></li><li id="n-portal" class="mw-list-item"><a href="/wiki/Wikipedia:Community_portal" title="The hub for editors"><span>Community portal</span></a></li><li id="n-recentchanges" class="mw-list-item"><a href="/wiki/Special:RecentChanges" title="A list of recent changes to Wikipedia [r]" accesskey="r"><span>Recent changes</span></a></li><li id="n-upload" class="mw-list-item"><a href="/wiki/Wikipedia:File_upload_wizard" title="Add images or other media for use on Wikipedia"><span>Upload file</span></a></li> </ul> </div> </div> </div> </div> </div> </div> </nav> <a href="/wiki/Main_Page" class="mw-logo"> <img class="mw-logo-icon" src="/static/images/icons/wikipedia.png" alt="" aria-hidden="true" height="50" width="50"> <span class="mw-logo-container skin-invert"> <img class="mw-logo-wordmark" alt="Wikipedia" src="/static/images/mobile/copyright/wikipedia-wordmark-en.svg" style="width: 7.5em; height: 1.125em;"> <img class="mw-logo-tagline" alt="The Free Encyclopedia" src="/static/images/mobile/copyright/wikipedia-tagline-en.svg" width="117" height="13" style="width: 7.3125em; height: 0.8125em;"> </span> </a> </div> <div class="vector-header-end"> <div id="p-search" role="search" class="vector-search-box-vue vector-search-box-collapses vector-search-box-show-thumbnail vector-search-box-auto-expand-width vector-search-box"> <a href="/wiki/Special:Search" class="cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only search-toggle" title="Search Wikipedia [f]" accesskey="f"><span class="vector-icon mw-ui-icon-search mw-ui-icon-wikimedia-search"></span> <span>Search</span> </a> <div class="vector-typeahead-search-container"> <div class="cdx-typeahead-search cdx-typeahead-search--show-thumbnail cdx-typeahead-search--auto-expand-width"> <form action="/w/index.php" id="searchform" class="cdx-search-input cdx-search-input--has-end-button"> <div id="simpleSearch" class="cdx-search-input__input-wrapper" data-search-loc="header-moved"> <div class="cdx-text-input cdx-text-input--has-start-icon"> <input class="cdx-text-input__input" type="search" name="search" placeholder="Search Wikipedia" aria-label="Search Wikipedia" autocapitalize="sentences" title="Search Wikipedia [f]" accesskey="f" id="searchInput" > <span class="cdx-text-input__icon cdx-text-input__start-icon"></span> </div> <input type="hidden" name="title" value="Special:Search"> </div> <button class="cdx-button cdx-search-input__end-button">Search</button> </form> </div> </div> </div> <nav class="vector-user-links vector-user-links-wide" aria-label="Personal tools"> <div class="vector-user-links-main"> <div id="p-vector-user-menu-preferences" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <div id="p-vector-user-menu-userpage" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-dropdown" class="vector-dropdown " title="Change the appearance of the page's font size, width, and color" > <input type="checkbox" id="vector-appearance-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-appearance-dropdown" class="vector-dropdown-checkbox " aria-label="Appearance" > <label id="vector-appearance-dropdown-label" for="vector-appearance-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-appearance mw-ui-icon-wikimedia-appearance"></span> <span class="vector-dropdown-label-text">Appearance</span> </label> <div class="vector-dropdown-content"> <div id="vector-appearance-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <div id="p-vector-user-menu-notifications" class="vector-menu mw-portlet emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> <div id="p-vector-user-menu-overflow" class="vector-menu mw-portlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-sitesupport-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="https://donate.wikimedia.org/wiki/Special:FundraiserRedirector?utm_source=donate&utm_medium=sidebar&utm_campaign=C13_en.wikipedia.org&uselang=en" class=""><span>Donate</span></a> </li> <li id="pt-createaccount-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="/w/index.php?title=Special:CreateAccount&returnto=Intel+Core" title="You are encouraged to create an account and log in; however, it is not mandatory" class=""><span>Create account</span></a> </li> <li id="pt-login-2" class="user-links-collapsible-item mw-list-item user-links-collapsible-item"><a data-mw="interface" href="/w/index.php?title=Special:UserLogin&returnto=Intel+Core" title="You're encouraged to log in; however, it's not mandatory. [o]" accesskey="o" class=""><span>Log in</span></a> </li> </ul> </div> </div> </div> <div id="vector-user-links-dropdown" class="vector-dropdown vector-user-menu vector-button-flush-right vector-user-menu-logged-out" title="Log in and more options" > <input type="checkbox" id="vector-user-links-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-user-links-dropdown" class="vector-dropdown-checkbox " aria-label="Personal tools" > <label id="vector-user-links-dropdown-label" for="vector-user-links-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-ellipsis mw-ui-icon-wikimedia-ellipsis"></span> <span class="vector-dropdown-label-text">Personal tools</span> </label> <div class="vector-dropdown-content"> <div id="p-personal" class="vector-menu mw-portlet mw-portlet-personal user-links-collapsible-item" title="User menu" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-sitesupport" class="user-links-collapsible-item mw-list-item"><a href="https://donate.wikimedia.org/wiki/Special:FundraiserRedirector?utm_source=donate&utm_medium=sidebar&utm_campaign=C13_en.wikipedia.org&uselang=en"><span>Donate</span></a></li><li id="pt-createaccount" class="user-links-collapsible-item mw-list-item"><a href="/w/index.php?title=Special:CreateAccount&returnto=Intel+Core" title="You are encouraged to create an account and log in; however, it is not mandatory"><span class="vector-icon mw-ui-icon-userAdd mw-ui-icon-wikimedia-userAdd"></span> <span>Create account</span></a></li><li id="pt-login" class="user-links-collapsible-item mw-list-item"><a href="/w/index.php?title=Special:UserLogin&returnto=Intel+Core" title="You're encouraged to log in; however, it's not mandatory. [o]" accesskey="o"><span class="vector-icon mw-ui-icon-logIn mw-ui-icon-wikimedia-logIn"></span> <span>Log in</span></a></li> </ul> </div> </div> <div id="p-user-menu-anon-editor" class="vector-menu mw-portlet mw-portlet-user-menu-anon-editor" > <div class="vector-menu-heading"> Pages for logged out editors <a href="/wiki/Help:Introduction" aria-label="Learn more about editing"><span>learn more</span></a> </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="pt-anoncontribs" class="mw-list-item"><a href="/wiki/Special:MyContributions" title="A list of edits made from this IP address [y]" accesskey="y"><span>Contributions</span></a></li><li id="pt-anontalk" class="mw-list-item"><a href="/wiki/Special:MyTalk" title="Discussion about edits from this IP address [n]" accesskey="n"><span>Talk</span></a></li> </ul> </div> </div> </div> </div> </nav> </div> </header> </div> <div class="mw-page-container"> <div class="mw-page-container-inner"> <div class="vector-sitenotice-container"> <div id="siteNotice"></div> </div> <div class="vector-column-start"> <div class="vector-main-menu-container"> <div id="mw-navigation"> <nav id="mw-panel" class="vector-main-menu-landmark" aria-label="Site"> <div id="vector-main-menu-pinned-container" class="vector-pinned-container"> </div> </nav> </div> </div> <div class="vector-sticky-pinned-container"> <nav id="mw-panel-toc" aria-label="Contents" data-event-name="ui.sidebar-toc" class="mw-table-of-contents-container vector-toc-landmark"> <div id="vector-toc-pinned-container" class="vector-pinned-container"> <div id="vector-toc" class="vector-toc vector-pinnable-element"> <div class="vector-pinnable-header vector-toc-pinnable-header vector-pinnable-header-pinned" data-feature-name="toc-pinned" data-pinnable-element-id="vector-toc" > <h2 class="vector-pinnable-header-label">Contents</h2> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-toc.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-toc.unpin">hide</button> </div> <ul class="vector-toc-contents" id="mw-panel-toc-list"> <li id="toc-mw-content-text" class="vector-toc-list-item vector-toc-level-1"> <a href="#" class="vector-toc-link"> <div class="vector-toc-text">(Top)</div> </a> </li> <li id="toc-Overview" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Overview"> <div class="vector-toc-text"> <span class="vector-toc-numb">1</span> <span>Overview</span> </div> </a> <ul id="toc-Overview-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Product_lineup" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Product_lineup"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Product lineup</span> </div> </a> <button aria-controls="toc-Product_lineup-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Product lineup subsection</span> </button> <ul id="toc-Product_lineup-sublist" class="vector-toc-list"> <li id="toc-Core" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Core</span> </div> </a> <ul id="toc-Core-sublist" class="vector-toc-list"> <li id="toc-Core_Solo" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_Solo"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.1</span> <span>Core Solo</span> </div> </a> <ul id="toc-Core_Solo-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Core_Duo" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_Duo"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1.2</span> <span>Core Duo</span> </div> </a> <ul id="toc-Core_Duo-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Core 2</span> </div> </a> <ul id="toc-Core_2-sublist" class="vector-toc-list"> <li id="toc-Core_2_Solo" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_2_Solo"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.1</span> <span>Core 2 Solo</span> </div> </a> <ul id="toc-Core_2_Solo-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Core_2_Duo" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_2_Duo"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.2</span> <span>Core 2 Duo</span> </div> </a> <ul id="toc-Core_2_Duo-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Core_2_Quad" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_2_Quad"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.3</span> <span>Core 2 Quad</span> </div> </a> <ul id="toc-Core_2_Quad-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Core_2_Extreme" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Core_2_Extreme"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2.4</span> <span>Core 2 Extreme</span> </div> </a> <ul id="toc-Core_2_Extreme-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Core_i3/i5/i7/i9" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_i3/i5/i7/i9"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Core i3/i5/i7/i9</span> </div> </a> <ul id="toc-Core_i3/i5/i7/i9-sublist" class="vector-toc-list"> <li id="toc-1st_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#1st_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.1</span> <span>1st generation</span> </div> </a> <ul id="toc-1st_generation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-2nd_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#2nd_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.2</span> <span>2nd generation</span> </div> </a> <ul id="toc-2nd_generation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-3rd_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#3rd_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.3</span> <span>3rd generation</span> </div> </a> <ul id="toc-3rd_generation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-4th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#4th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.4</span> <span>4th generation</span> </div> </a> <ul id="toc-4th_generation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-5th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#5th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.5</span> <span>5th generation</span> </div> </a> <ul id="toc-5th_generation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-6th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#6th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.6</span> <span>6th generation</span> </div> </a> <ul id="toc-6th_generation-sublist" class="vector-toc-list"> <li id="toc-Broadwell_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Broadwell_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.6.1</span> <span>Broadwell microarchitecture</span> </div> </a> <ul id="toc-Broadwell_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Skylake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Skylake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.6.2</span> <span>Skylake microarchitecture</span> </div> </a> <ul id="toc-Skylake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-7th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#7th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.7</span> <span>7th generation</span> </div> </a> <ul id="toc-7th_generation-sublist" class="vector-toc-list"> <li id="toc-Skylake_microarchitecture_2" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Skylake_microarchitecture_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.7.1</span> <span>Skylake microarchitecture</span> </div> </a> <ul id="toc-Skylake_microarchitecture_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kaby_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Kaby_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.7.2</span> <span>Kaby Lake</span> </div> </a> <ul id="toc-Kaby_Lake-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-8th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#8th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8</span> <span>8th generation</span> </div> </a> <ul id="toc-8th_generation-sublist" class="vector-toc-list"> <li id="toc-Kaby_Lake_Refresh" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Kaby_Lake_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8.1</span> <span>Kaby Lake Refresh</span> </div> </a> <ul id="toc-Kaby_Lake_Refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Coffee_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8.2</span> <span>Coffee Lake microarchitecture</span> </div> </a> <ul id="toc-Coffee_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Amber_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Amber_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8.3</span> <span>Amber Lake microarchitecture</span> </div> </a> <ul id="toc-Amber_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Whiskey_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Whiskey_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8.4</span> <span>Whiskey Lake microarchitecture</span> </div> </a> <ul id="toc-Whiskey_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cannon_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Cannon_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.8.5</span> <span>Cannon Lake microarchitecture</span> </div> </a> <ul id="toc-Cannon_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-9th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#9th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.9</span> <span>9th generation</span> </div> </a> <ul id="toc-9th_generation-sublist" class="vector-toc-list"> <li id="toc-Skylake_microarchitecture_3" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Skylake_microarchitecture_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.9.1</span> <span>Skylake microarchitecture</span> </div> </a> <ul id="toc-Skylake_microarchitecture_3-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Coffee_Lake_Refresh_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Coffee_Lake_Refresh_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.9.2</span> <span>Coffee Lake Refresh microarchitecture</span> </div> </a> <ul id="toc-Coffee_Lake_Refresh_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-10th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#10th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10</span> <span>10th generation</span> </div> </a> <ul id="toc-10th_generation-sublist" class="vector-toc-list"> <li id="toc-Cascade_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Cascade_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10.1</span> <span>Cascade Lake microarchitecture</span> </div> </a> <ul id="toc-Cascade_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ice_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Ice_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10.2</span> <span>Ice Lake microarchitecture</span> </div> </a> <ul id="toc-Ice_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comet_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Comet_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10.3</span> <span>Comet Lake microarchitecture</span> </div> </a> <ul id="toc-Comet_Lake_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comet_Lake_Refresh_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Comet_Lake_Refresh_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10.4</span> <span>Comet Lake Refresh microarchitecture</span> </div> </a> <ul id="toc-Comet_Lake_Refresh_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Amber_Lake_Refresh_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Amber_Lake_Refresh_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.10.5</span> <span>Amber Lake Refresh microarchitecture</span> </div> </a> <ul id="toc-Amber_Lake_Refresh_microarchitecture-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-11th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#11th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11</span> <span>11th generation</span> </div> </a> <ul id="toc-11th_generation-sublist" class="vector-toc-list"> <li id="toc-Tiger_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Tiger_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1</span> <span>Tiger Lake</span> </div> </a> <ul id="toc-Tiger_Lake-sublist" class="vector-toc-list"> <li id="toc-Mobile_processors_(Tiger_Lake-H)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors_(Tiger_Lake-H)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1.1</span> <span>Mobile processors (Tiger Lake-H)</span> </div> </a> <ul id="toc-Mobile_processors_(Tiger_Lake-H)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mobile_processors_(Tiger_Lake-H35)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors_(Tiger_Lake-H35)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1.2</span> <span>Mobile processors (Tiger Lake-H35)</span> </div> </a> <ul id="toc-Mobile_processors_(Tiger_Lake-H35)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mobile_processors_(UP3-class)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors_(UP3-class)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1.3</span> <span>Mobile processors (UP3-class)</span> </div> </a> <ul id="toc-Mobile_processors_(UP3-class)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mobile_processors_(UP4-class)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors_(UP4-class)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1.4</span> <span>Mobile processors (UP4-class)</span> </div> </a> <ul id="toc-Mobile_processors_(UP4-class)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Desktop/tablet_processors_(Tiger_Lake-B)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Desktop/tablet_processors_(Tiger_Lake-B)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.1.5</span> <span>Desktop/tablet processors (Tiger Lake-B)</span> </div> </a> <ul id="toc-Desktop/tablet_processors_(Tiger_Lake-B)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Rocket_Lake_microarchitecture" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Rocket_Lake_microarchitecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.2</span> <span>Rocket Lake microarchitecture</span> </div> </a> <ul id="toc-Rocket_Lake_microarchitecture-sublist" class="vector-toc-list"> <li id="toc-Desktop_processors" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Desktop_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.11.2.1</span> <span>Desktop processors</span> </div> </a> <ul id="toc-Desktop_processors-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-12th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#12th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12</span> <span>12th generation</span> </div> </a> <ul id="toc-12th_generation-sublist" class="vector-toc-list"> <li id="toc-Alder_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Alder_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1</span> <span>Alder Lake</span> </div> </a> <ul id="toc-Alder_Lake-sublist" class="vector-toc-list"> <li id="toc-Desktop_processors_(Alder_Lake-S)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Desktop_processors_(Alder_Lake-S)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1.1</span> <span>Desktop processors (Alder Lake-S)</span> </div> </a> <ul id="toc-Desktop_processors_(Alder_Lake-S)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Extreme-performance_Mobile_Processors_(Alder_Lake-HX)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Extreme-performance_Mobile_Processors_(Alder_Lake-HX)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1.2</span> <span>Extreme-performance Mobile Processors (Alder Lake-HX)</span> </div> </a> <ul id="toc-Extreme-performance_Mobile_Processors_(Alder_Lake-HX)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-High-performance_Mobile_Processors_(Alder_Lake-H)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#High-performance_Mobile_Processors_(Alder_Lake-H)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1.3</span> <span>High-performance Mobile Processors (Alder Lake-H)</span> </div> </a> <ul id="toc-High-performance_Mobile_Processors_(Alder_Lake-H)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Low_Power_Performance_Mobile_Processors_(Alder_Lake-P)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Low_Power_Performance_Mobile_Processors_(Alder_Lake-P)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1.4</span> <span>Low Power Performance Mobile Processors (Alder Lake-P)</span> </div> </a> <ul id="toc-Low_Power_Performance_Mobile_Processors_(Alder_Lake-P)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Ultra_Low_Power_Mobile_Processors_(Alder_Lake-U)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Ultra_Low_Power_Mobile_Processors_(Alder_Lake-U)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.12.1.5</span> <span>Ultra Low Power Mobile Processors (Alder Lake-U)</span> </div> </a> <ul id="toc-Ultra_Low_Power_Mobile_Processors_(Alder_Lake-U)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-13th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#13th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.13</span> <span>13th generation</span> </div> </a> <ul id="toc-13th_generation-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Raptor_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.13.1</span> <span>Raptor Lake</span> </div> </a> <ul id="toc-Raptor_Lake-sublist" class="vector-toc-list"> <li id="toc-Desktop_Processors_(Raptor_Lake-S)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Desktop_Processors_(Raptor_Lake-S)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.13.1.1</span> <span>Desktop Processors (Raptor Lake-S)</span> </div> </a> <ul id="toc-Desktop_Processors_(Raptor_Lake-S)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-14th_generation" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#14th_generation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.14</span> <span>14th generation</span> </div> </a> <ul id="toc-14th_generation-sublist" class="vector-toc-list"> <li id="toc-Raptor_Lake_Refresh" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Raptor_Lake_Refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3.14.1</span> <span>Raptor Lake Refresh</span> </div> </a> <ul id="toc-Raptor_Lake_Refresh-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Core_and_Core_Ultra_3/5/7/9" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Core_and_Core_Ultra_3/5/7/9"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Core and Core Ultra 3/5/7/9</span> </div> </a> <ul id="toc-Core_and_Core_Ultra_3/5/7/9-sublist" class="vector-toc-list"> <li id="toc-Series_1" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Series_1"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1</span> <span>Series 1</span> </div> </a> <ul id="toc-Series_1-sublist" class="vector-toc-list"> <li id="toc-Meteor_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Meteor_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1.1</span> <span>Meteor Lake</span> </div> </a> <ul id="toc-Meteor_Lake-sublist" class="vector-toc-list"> <li id="toc-Process_technology" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Process_technology"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1.1.1</span> <span>Process technology</span> </div> </a> <ul id="toc-Process_technology-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mobile_processors" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1.1.2</span> <span>Mobile processors</span> </div> </a> <ul id="toc-Mobile_processors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Processors_for_Internet_of_Things_(IoT)_devices_and_embedded_systems_(Meteor_Lake-PS)" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Processors_for_Internet_of_Things_(IoT)_devices_and_embedded_systems_(Meteor_Lake-PS)"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.1.1.3</span> <span>Processors for Internet of Things (IoT) devices and embedded systems (Meteor Lake-PS)</span> </div> </a> <ul id="toc-Processors_for_Internet_of_Things_(IoT)_devices_and_embedded_systems_(Meteor_Lake-PS)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Series_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Series_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.2</span> <span>Series 2</span> </div> </a> <ul id="toc-Series_2-sublist" class="vector-toc-list"> <li id="toc-Lunar_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Lunar_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.2.1</span> <span>Lunar Lake</span> </div> </a> <ul id="toc-Lunar_Lake-sublist" class="vector-toc-list"> <li id="toc-Mobile_processors_2" class="vector-toc-list-item vector-toc-level-5"> <a class="vector-toc-link" href="#Mobile_processors_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.2.1.1</span> <span>Mobile processors</span> </div> </a> <ul id="toc-Mobile_processors_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Arrow_Lake" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#Arrow_Lake"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4.2.2</span> <span>Arrow Lake</span> </div> </a> <ul id="toc-Arrow_Lake-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Reception" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Reception"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Reception</span> </div> </a> <button aria-controls="toc-Reception-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Reception subsection</span> </button> <ul id="toc-Reception-sublist" class="vector-toc-list"> <li id="toc-Speculative_execution_CPU_vulnerabilities" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Speculative_execution_CPU_vulnerabilities"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Speculative execution CPU vulnerabilities</span> </div> </a> <ul id="toc-Speculative_execution_CPU_vulnerabilities-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Intel Core</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 32 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-32" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">32 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%86%D9%88%D8%A7%D8%A9_%D8%A5%D9%86%D8%AA%D9%84" title="نواة إنتل – Arabic" lang="ar" hreflang="ar" data-title="نواة إنتل" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/Intel_Core" title="Intel Core – Azerbaijani" lang="az" hreflang="az" data-title="Intel Core" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target"><span>Azərbaycanca</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Core_Intel" title="Core Intel – Catalan" lang="ca" hreflang="ca" data-title="Core Intel" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Intel_Core" title="Intel Core – Czech" lang="cs" hreflang="cs" data-title="Intel Core" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Intel-Core-i-Serie" title="Intel-Core-i-Serie – German" lang="de" hreflang="de" data-title="Intel-Core-i-Serie" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%A7%DB%8C%D9%86%D8%AA%D9%84_%DA%A9%D9%88%D8%B1" title="اینتل کور – Persian" lang="fa" hreflang="fa" data-title="اینتل کور" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%9D%B8%ED%85%94_%EC%BD%94%EC%96%B4" title="인텔 코어 – Korean" lang="ko" hreflang="ko" data-title="인텔 코어" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hy mw-list-item"><a href="https://hy.wikipedia.org/wiki/Intel_core" title="Intel core – Armenian" lang="hy" hreflang="hy" data-title="Intel core" data-language-autonym="Հայերեն" data-language-local-name="Armenian" class="interlanguage-link-target"><span>Հայերեն</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Intel_Core" title="Intel Core – Croatian" lang="hr" hreflang="hr" data-title="Intel Core" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-is mw-list-item"><a href="https://is.wikipedia.org/wiki/Intel_Core" title="Intel Core – Icelandic" lang="is" hreflang="is" data-title="Intel Core" data-language-autonym="Íslenska" data-language-local-name="Icelandic" class="interlanguage-link-target"><span>Íslenska</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/Intel_Core" title="Intel Core – Hebrew" lang="he" hreflang="he" data-title="Intel Core" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-jv mw-list-item"><a href="https://jv.wikipedia.org/wiki/Intel_Core" title="Intel Core – Javanese" lang="jv" hreflang="jv" data-title="Intel Core" data-language-autonym="Jawa" data-language-local-name="Javanese" class="interlanguage-link-target"><span>Jawa</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Intel_Core" title="Intel Core – Hungarian" lang="hu" hreflang="hu" data-title="Intel Core" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%87%E0%B4%A8%E0%B5%8D%E0%B4%B1%E0%B5%BD_%E0%B4%95%E0%B5%8B%E0%B5%BC" title="ഇന്റൽ കോർ – Malayalam" lang="ml" hreflang="ml" data-title="ഇന്റൽ കോർ" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Intel_Core" title="Intel Core – Dutch" lang="nl" hreflang="nl" data-title="Intel Core" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Intel_Core" title="Intel Core – Japanese" lang="ja" hreflang="ja" data-title="Intel Core" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/Intel_Core" title="Intel Core – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="Intel Core" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-uz mw-list-item"><a href="https://uz.wikipedia.org/wiki/Intel_Core" title="Intel Core – Uzbek" lang="uz" hreflang="uz" data-title="Intel Core" data-language-autonym="Oʻzbekcha / ўзбекча" data-language-local-name="Uzbek" class="interlanguage-link-target"><span>Oʻzbekcha / ўзбекча</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Intel_Core" title="Intel Core – Polish" lang="pl" hreflang="pl" data-title="Intel Core" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Intel_Core" title="Intel Core – Romanian" lang="ro" hreflang="ro" data-title="Intel Core" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Intel_Core" title="Intel Core – Russian" lang="ru" hreflang="ru" data-title="Intel Core" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/Intel_Core" title="Intel Core – Albanian" lang="sq" hreflang="sq" data-title="Intel Core" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target"><span>Shqip</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Intel_Core" title="Intel Core – Simple English" lang="en-simple" hreflang="en-simple" data-title="Intel Core" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Intel_Core" title="Intel Core – Slovak" lang="sk" hreflang="sk" data-title="Intel Core" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Intel_Core" title="Intel Core – Finnish" lang="fi" hreflang="fi" data-title="Intel Core" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Intel_Core" title="Intel Core – Swedish" lang="sv" hreflang="sv" data-title="Intel Core" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%AD%E0%B8%B4%E0%B8%99%E0%B9%80%E0%B8%97%E0%B8%A5_%E0%B8%84%E0%B8%AD%E0%B8%A3%E0%B9%8C" title="อินเทล คอร์ – Thai" lang="th" hreflang="th" data-title="อินเทล คอร์" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Intel_Core" title="Intel Core – Turkish" lang="tr" hreflang="tr" data-title="Intel Core" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Intel_Core" title="Intel Core – Ukrainian" lang="uk" hreflang="uk" data-title="Intel Core" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/Intel_Core" title="Intel Core – Vietnamese" lang="vi" hreflang="vi" data-title="Intel Core" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/%E8%8B%B1%E7%89%B9%E5%B0%94%E9%85%B7%E7%9D%BF" title="英特尔酷睿 – Wu" lang="wuu" hreflang="wuu" data-title="英特尔酷睿" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/%E9%85%B7%E7%9D%BF" title="酷睿 – Chinese" lang="zh" hreflang="zh" data-title="酷睿" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q19481932#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/Intel_Core" title="View the content page [c]" accesskey="c"><span>Article</span></a></li><li id="ca-talk" class="vector-tab-noicon mw-list-item"><a href="/wiki/Talk:Intel_Core" rel="discussion" title="Discuss improvements to the content page [t]" accesskey="t"><span>Talk</span></a></li> </ul> </div> </div> <div id="vector-variants-dropdown" class="vector-dropdown emptyPortlet" > <input type="checkbox" id="vector-variants-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-variants-dropdown" class="vector-dropdown-checkbox " aria-label="Change language variant" > <label id="vector-variants-dropdown-label" for="vector-variants-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet" aria-hidden="true" ><span class="vector-dropdown-label-text">English</span> </label> <div class="vector-dropdown-content"> <div id="p-variants" class="vector-menu mw-portlet mw-portlet-variants emptyPortlet" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> </ul> </div> </div> </div> </div> </nav> </div> <div id="right-navigation" class="vector-collapsible"> <nav aria-label="Views"> <div id="p-views" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-views" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-view" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/Intel_Core"><span>Read</span></a></li><li id="ca-edit" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=Intel_Core&action=edit" title="Edit this page [e]" accesskey="e"><span>Edit</span></a></li><li id="ca-history" class="vector-tab-noicon mw-list-item"><a href="/w/index.php?title=Intel_Core&action=history" title="Past revisions of this page [h]" accesskey="h"><span>View history</span></a></li> </ul> </div> </div> </nav> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-dropdown" class="vector-dropdown vector-page-tools-dropdown" > <input type="checkbox" id="vector-page-tools-dropdown-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-tools-dropdown" class="vector-dropdown-checkbox " aria-label="Tools" > <label id="vector-page-tools-dropdown-label" for="vector-page-tools-dropdown-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet" aria-hidden="true" ><span class="vector-dropdown-label-text">Tools</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-tools-unpinned-container" class="vector-unpinned-container"> <div id="vector-page-tools" class="vector-page-tools vector-pinnable-element"> <div class="vector-pinnable-header vector-page-tools-pinnable-header vector-pinnable-header-unpinned" data-feature-name="page-tools-pinned" data-pinnable-element-id="vector-page-tools" data-pinned-container-id="vector-page-tools-pinned-container" data-unpinned-container-id="vector-page-tools-unpinned-container" > <div class="vector-pinnable-header-label">Tools</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-page-tools.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-page-tools.unpin">hide</button> </div> <div id="p-cactions" class="vector-menu mw-portlet mw-portlet-cactions emptyPortlet vector-has-collapsible-items" title="More options" > <div class="vector-menu-heading"> Actions </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-more-view" class="selected vector-more-collapsible-item mw-list-item"><a href="/wiki/Intel_Core"><span>Read</span></a></li><li id="ca-more-edit" class="vector-more-collapsible-item mw-list-item"><a href="/w/index.php?title=Intel_Core&action=edit" title="Edit this page [e]" accesskey="e"><span>Edit</span></a></li><li id="ca-more-history" class="vector-more-collapsible-item mw-list-item"><a href="/w/index.php?title=Intel_Core&action=history"><span>View history</span></a></li> </ul> </div> </div> <div id="p-tb" class="vector-menu mw-portlet mw-portlet-tb" > <div class="vector-menu-heading"> General </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="t-whatlinkshere" class="mw-list-item"><a href="/wiki/Special:WhatLinksHere/Intel_Core" title="List of all English Wikipedia pages containing links to this page [j]" accesskey="j"><span>What links here</span></a></li><li id="t-recentchangeslinked" class="mw-list-item"><a href="/wiki/Special:RecentChangesLinked/Intel_Core" rel="nofollow" title="Recent changes in pages linked from this page [k]" accesskey="k"><span>Related changes</span></a></li><li id="t-upload" class="mw-list-item"><a href="/wiki/Wikipedia:File_Upload_Wizard" title="Upload files [u]" accesskey="u"><span>Upload file</span></a></li><li id="t-specialpages" class="mw-list-item"><a href="/wiki/Special:SpecialPages" title="A list of all special pages [q]" accesskey="q"><span>Special pages</span></a></li><li id="t-permalink" class="mw-list-item"><a href="/w/index.php?title=Intel_Core&oldid=1259288623" title="Permanent link to this revision of this page"><span>Permanent link</span></a></li><li id="t-info" class="mw-list-item"><a href="/w/index.php?title=Intel_Core&action=info" title="More information about this page"><span>Page information</span></a></li><li id="t-cite" class="mw-list-item"><a href="/w/index.php?title=Special:CiteThisPage&page=Intel_Core&id=1259288623&wpFormIdentifier=titleform" title="Information on how to cite this page"><span>Cite this page</span></a></li><li id="t-urlshortener" class="mw-list-item"><a href="/w/index.php?title=Special:UrlShortener&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FIntel_Core%23Core_i3%2Fi5%2Fi7%2Fi9"><span>Get shortened URL</span></a></li><li id="t-urlshortener-qrcode" class="mw-list-item"><a href="/w/index.php?title=Special:QrCode&url=https%3A%2F%2Fen.wikipedia.org%2Fwiki%2FIntel_Core%23Core_i3%2Fi5%2Fi7%2Fi9"><span>Download QR code</span></a></li> </ul> </div> </div> <div id="p-coll-print_export" class="vector-menu mw-portlet mw-portlet-coll-print_export" > <div class="vector-menu-heading"> Print/export </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="coll-download-as-rl" class="mw-list-item"><a href="/w/index.php?title=Special:DownloadAsPdf&page=Intel_Core&action=show-download-screen" title="Download this page as a PDF file"><span>Download as PDF</span></a></li><li id="t-print" class="mw-list-item"><a href="/w/index.php?title=Intel_Core&printable=yes" title="Printable version of this page [p]" accesskey="p"><span>Printable version</span></a></li> </ul> </div> </div> <div id="p-wikibase-otherprojects" class="vector-menu mw-portlet mw-portlet-wikibase-otherprojects" > <div class="vector-menu-heading"> In other projects </div> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="wb-otherproject-link wb-otherproject-commons mw-list-item"><a href="https://commons.wikimedia.org/wiki/Category:Intel_Core" hreflang="en"><span>Wikimedia Commons</span></a></li><li id="t-wikibase" class="wb-otherproject-link wb-otherproject-wikibase-dataitem mw-list-item"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q19481932" title="Structured data on this page hosted by Wikidata [g]" accesskey="g"><span>Wikidata item</span></a></li> </ul> </div> </div> </div> </div> </div> </div> </nav> </div> </div> </div> <div class="vector-column-end"> <div class="vector-sticky-pinned-container"> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-pinned-container" class="vector-pinned-container"> </div> </nav> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-pinned-container" class="vector-pinned-container"> <div id="vector-appearance" class="vector-appearance vector-pinnable-element"> <div class="vector-pinnable-header vector-appearance-pinnable-header vector-pinnable-header-pinned" data-feature-name="appearance-pinned" data-pinnable-element-id="vector-appearance" data-pinned-container-id="vector-appearance-pinned-container" data-unpinned-container-id="vector-appearance-unpinned-container" > <div class="vector-pinnable-header-label">Appearance</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" data-event-name="pinnable-header.vector-appearance.pin">move to sidebar</button> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-unpin-button" data-event-name="pinnable-header.vector-appearance.unpin">hide</button> </div> </div> </div> </nav> </div> </div> <div id="bodyContent" class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=Intel_Core_i7&redirect=no" class="mw-redirect" title="Intel Core i7">Intel Core i7</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Line of CPUs by Intel</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">For the 32-bit Intel Core Solo/Duo CPUs, see <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah (microprocessor)</a>.</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Intel Core</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Intel_Core_2023_logo.png" class="mw-file-description"><img alt="Intel Core logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/220px-Intel_Core_2023_logo.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/330px-Intel_Core_2023_logo.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/28/Intel_Core_2023_logo.png/440px-Intel_Core_2023_logo.png 2x" data-file-width="443" data-file-height="443" /></a></span><div class="infobox-caption">Logo since 2023</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">January 2006<span class="noprint">; 18 years ago</span><span style="display:none"> (<span class="bday dtstart published updated">2006-01</span>)</span></td></tr><tr><th scope="row" class="infobox-label">Marketed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data">Intel</td></tr><tr><th scope="row" class="infobox-label">Common manufacturers</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>Intel</li><li><a href="/wiki/TSMC" title="TSMC">TSMC</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">400 MHz to 6.2 GHz</td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">Up to 112 KB per P-core<br />96 KB per E-core or LP E-core</td></tr><tr><th scope="row" class="infobox-label">L2 cache</th><td class="infobox-data">Core and Core 2: Up to 12 MB<br />Nehalem-present: Up to 2 MB per P-core and up to 3 MB per E-core cluster</td></tr><tr><th scope="row" class="infobox-label">L3 cache</th><td class="infobox-data">Up to 36 MB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="/wiki/65_nm_process" title="65 nm process">65 nm</a> to <a href="/wiki/5_nm_process" title="5 nm process">Intel 4</a> and TSMC N5</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · ";font-weight:bold}.mw-parser-output .hlist dd:last-child::after,.mw-parser-output .hlist dt:last-child::after,.mw-parser-output .hlist li:last-child::after{content:none}.mw-parser-output .hlist dd dd:first-child::before,.mw-parser-output .hlist dd dt:first-child::before,.mw-parser-output .hlist dd li:first-child::before,.mw-parser-output .hlist dt dd:first-child::before,.mw-parser-output .hlist dt dt:first-child::before,.mw-parser-output .hlist dt li:first-child::before,.mw-parser-output .hlist li dd:first-child::before,.mw-parser-output .hlist li dt:first-child::before,.mw-parser-output .hlist li li:first-child::before{content:" (";font-weight:normal}.mw-parser-output .hlist dd dd:last-child::after,.mw-parser-output .hlist dd dt:last-child::after,.mw-parser-output .hlist dd li:last-child::after,.mw-parser-output .hlist dt dd:last-child::after,.mw-parser-output .hlist dt dt:last-child::after,.mw-parser-output .hlist dt li:last-child::after,.mw-parser-output .hlist li dd:last-child::after,.mw-parser-output .hlist li dt:last-child::after,.mw-parser-output .hlist li li:last-child::after{content:")";font-weight:normal}.mw-parser-output .hlist ol{counter-reset:listitem}.mw-parser-output .hlist ol>li{counter-increment:listitem}.mw-parser-output .hlist ol>li::before{content:" "counter(listitem)"\a0 "}.mw-parser-output .hlist dd ol>li:first-child::before,.mw-parser-output .hlist dt ol>li:first-child::before,.mw-parser-output .hlist li ol>li:first-child::before{content:" ("counter(listitem)"\a0 "}</style><div class="hlist"><ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a></li><li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a></li><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li><li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></li><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li><li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a></li><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li><li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a></li><li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a></li><li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li><li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li><li><a href="/wiki/Raptor_Cove_(microarchitecture)" class="mw-redirect" title="Raptor Cove (microarchitecture)">Raptor Cove</a></li><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li><li><a href="/w/index.php?title=Redwood_Cove_(microarchitecture)&action=edit&redlink=1" class="new" title="Redwood Cove (microarchitecture) (page does not exist)">Redwood Cove</a></li><li><a href="/w/index.php?title=Crestmont_(microarchitecture)&action=edit&redlink=1" class="new" title="Crestmont (microarchitecture) (page does not exist)">Crestmont</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-64" title="X86-64">x86-64</a></td></tr><tr><th scope="row" class="infobox-label">Instructions</th><td class="infobox-data">MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX-512, TSX, AES-NI, FMA3, AVX-VNNI</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>EIST, TXT, VT-x, VT-d, SHA, <s>SGX</s></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>P-cores: 2–10</li><li>E-cores: 4–16</li><li>Total: 1-24</li></ul></div></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></th><td class="infobox-data"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel Graphics Technology</a></td></tr><tr><th scope="row" class="infobox-label">Sockets</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></li><li><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></li><li><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></li><li><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></li><li><a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a></li><li><a href="/wiki/LGA_1151-2" class="mw-redirect" title="LGA 1151-2">LGA 1151-2</a></li><li><a href="/wiki/LGA_1200" title="LGA 1200">LGA 1200</a></li><li><a href="/wiki/LGA_1700" title="LGA 1700">LGA 1700</a></li><li><a href="/wiki/LGA_1851" title="LGA 1851">LGA 1851</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Brand names</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Core</li><li>Core 2</li><li>Core i3/i5/i7/i9</li><li>Core 3/5/7</li><li>Core Ultra 3/5/7/9</li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Variant</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Intel Processor (budget CPUs)</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/Pentium" title="Pentium">Pentium</a></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_i9-14900K.webp" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/12/Intel_i9-14900K.webp/220px-Intel_i9-14900K.webp.png" decoding="async" width="220" height="211" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/12/Intel_i9-14900K.webp/330px-Intel_i9-14900K.webp.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/12/Intel_i9-14900K.webp/440px-Intel_i9-14900K.webp.png 2x" data-file-width="600" data-file-height="575" /></a><figcaption>A flagship model, the Intel Core i9-14900K</figcaption></figure> <p><b>Intel Core</b> is a line of <a href="/wiki/Multi-core" class="mw-redirect" title="Multi-core">multi-core</a> (with the exception of Core Solo and Core 2 Solo) <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs) for <a href="/wiki/Midrange_computer" title="Midrange computer">midrange</a>, embedded, workstation, high-end and enthusiast computer markets marketed by <a href="/wiki/Intel_Corporation" class="mw-redirect" title="Intel Corporation">Intel Corporation</a>. These processors displaced the existing mid- to high-end <a href="/wiki/Pentium" title="Pentium">Pentium</a> processors at the time of their introduction, moving the Pentium to the entry level. Identical or more capable versions of Core processors are also sold as <a href="/wiki/Xeon" title="Xeon">Xeon</a> processors for the <a href="/wiki/Server_(computing)" title="Server (computing)">server</a> and <a href="/wiki/Workstation" title="Workstation">workstation</a> markets. </p><p>Core was launched in January 2006 as a mobile-only series, consisting of single- and dual-core models. It was then succeeded later in July by the Core 2 series, which included both desktop and mobile processors with up to four cores, and introduced 64-bit support. </p><p>Since 2008, Intel began introducing the Core i3, Core i5, Core i7 and Core i9 lineup of processors, succeeding Core 2. </p><p>A new naming scheme debuted in 2023, consisting of Core 3, Core 5, and Core 7 for mainstream processors, and Core Ultra 5, Core Ultra 7, and Core Ultra 9 for "premium" high-end processors. </p> <style data-mw-deduplicate="TemplateStyles:r886046785">.mw-parser-output .toclimit-2 .toclevel-1 ul,.mw-parser-output .toclimit-3 .toclevel-2 ul,.mw-parser-output .toclimit-4 .toclevel-3 ul,.mw-parser-output .toclimit-5 .toclevel-4 ul,.mw-parser-output .toclimit-6 .toclevel-5 ul,.mw-parser-output .toclimit-7 .toclevel-6 ul{display:none}</style><div class="toclimit-3"><meta property="mw:PageProp/toc" /></div> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Although Intel Core is a brand that promises no internal consistency or continuity, the processors within this family have been, for the most part, broadly similar. </p><p>The first products receiving this designation were the Core Solo and Core Duo <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a> processors for mobile from the <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a> design tree, <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> at <a href="/wiki/65_nm_process" title="65 nm process">65 nm</a> and brought to market in January 2006. These are substantially different in design than the rest of the Intel Core product group, having derived from the <a href="/wiki/Pentium_Pro" title="Pentium Pro">Pentium Pro</a> lineage that predated <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>. </p><p>The first Intel Core desktop processor—and typical family member—came from the <a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe</a> iteration, a 65 nm dual-core design brought to market in July 2006, based on the <a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Intel Core microarchitecture</a> with substantial enhancements in micro-architectural efficiency and performance, outperforming Pentium 4 across the board (or near to it), while operating at drastically lower clock rates. Maintaining high <a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">instructions per cycle</a> (IPC) on a deeply <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelined</a> and resourced <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> engine has remained a constant fixture of the Intel Core product group ever since. </p><p>The new substantial bump in microarchitecture came with the introduction of the 45 nm <a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield</a> desktop processor in November 2008 on the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem architecture</a>, whose main advantage came from redesigned I/O and memory systems featuring the new <a href="/wiki/Intel_QuickPath_Interconnect" title="Intel QuickPath Interconnect">Intel QuickPath Interconnect</a> and an integrated <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a> supporting up to three channels of <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> memory. </p><p>Subsequent performance improvements have tended toward making additions rather than profound changes, such as adding the <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (AVX) instruction set extensions to <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>, first released on 32 nm in January 2011. Time has also brought improved support for <a href="/wiki/Virtualization" title="Virtualization">virtualization</a> and a trend toward higher levels of system integration and management functionality (and along with that, increased performance) through the ongoing evolution of facilities such as <a href="/wiki/Intel_Active_Management_Technology" title="Intel Active Management Technology">Intel Active Management Technology</a> (iAMT). </p><p>As of 2017, the Core brand comprised four product lines – the entry level i3, the mainstream i5, the high-end i7, and the "enthusiast" i9. Core i7 was introduced in 2008, followed by i5 in 2009, and i3 in 2010. The first Core i9 models were released in 2017. </p><p>In 2023, Intel announced that it would drop the "i" moniker from their processor branding, making it "Core 3/5/7/9". The company would introduce the "Ultra" branding for high-end processors as well.<sup id="cite_ref-Intel_drops_I_processor_1-0" class="reference"><a href="#cite_note-Intel_drops_I_processor-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> The new naming scheme debuted with the launch of <a href="/wiki/Raptor_Lake#Raptor_Lake-U_Refresh" title="Raptor Lake">Raptor Lake-U Refresh</a> and <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> processors in 2024, using the "Core 3/5/7" branding for mainstream processors and "Core Ultra 5/7/9" branding for "premium" high-end processors.<sup id="cite_ref-Bonshor-2023a-Intel-to-Launch_2-0" class="reference"><a href="#cite_note-Bonshor-2023a-Intel-to-Launch-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Robinson-2023_3-0" class="reference"><a href="#cite_note-Robinson-2023-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable mw-collapsible mw-collapsed" style="text-align: center;"> <caption>Comparison of Intel Core microarchitectures </caption> <tbody><tr> <th scope="colgroup" colspan="4"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a> </th> <th scope="col" colspan="2"><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> </th> <th scope="col"><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> </th> <th scope="col"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> </th> <th scope="col" rowspan="2"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> </th> <th scope="col" rowspan="2"><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a> </th> <th scope="col"><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> </th> <th scope="col"><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th> <th scope="col"><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a> </th> <th scope="col"><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a> </th> <th scope="col"><b><a href="/wiki/Raptor_Cove" class="mw-redirect" title="Raptor Cove">Raptor Cove</a></b> </th></tr> <tr> <th scope="colgroup" colspan="4">Microarchitecture variants </th> <th scope="col"><a href="/wiki/Merom_(microarchitecture)" class="mw-redirect" title="Merom (microarchitecture)">Merom</a> </th> <th scope="col"><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a> </th> <th scope="col"><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a> </th> <th scope="col"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a> </th> <th scope="col"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a></li><li><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a></li><li><a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a></li></ul></div> </th> <th scope="col"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a></li><li><a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a></li></ul></div> </th> <th scope="col"><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a> </th> <th scope="col"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a></li><li><a href="/wiki/Sapphire_Rapids" title="Sapphire Rapids">Sapphire Rapids</a></li></ul></div> </th> <th scope="col"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li><a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake</a></li><li><a href="/wiki/Emerald_Rapids" title="Emerald Rapids">Emerald Rapids</a></li></ul></div> </th></tr> <tr> <th colspan="4">Generation (Core i) </th> <th>- </th> <th>- </th> <th>1st </th> <th>2nd/3rd </th> <th>4th </th> <th>5th/6th </th> <th>6th/7th/8th/9th </th> <th>10th/11th </th> <th>11th </th> <th>12th </th> <th>13th/14th </th></tr> <tr> <th colspan="4">Year of inception </th> <th>2006 </th> <th>2007 </th> <th>2010 </th> <th>2011 </th> <th>2013 </th> <th>2014 </th> <th>2015 </th> <th>2019 </th> <th>2020 </th> <th>2021 </th> <th>2022 </th></tr> <tr> <th scope="row" colspan="4"><a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">Fabrication process</a> (nm) </th> <td>65 </td> <td colspan="2">45 </td> <td>32/22 </td> <td>22 </td> <td>14 </td> <td>14+/14++/14+++ </td> <td>10 </td> <td>10SF </td> <td colspan="2">10ESF </td></tr> <tr> <th rowspan="19" scope="rowgroup"><a href="/wiki/CPU_cache" title="CPU cache">Cache</a> </th> <th scope="row" colspan="3">μop </th> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="4">1.5K μops<sup id="cite_ref-auto2_5-0" class="reference"><a href="#cite_note-auto2-5"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2">2.25K μops </td> <td colspan="2">4K μops </td></tr> <tr> <th rowspan="7">L1 </th> <th rowspan="3">Data </th> <th>Size </th> <td colspan="7">32 KB/core </td> <td colspan="4">48 KB/core </td></tr> <tr> <th scope="row">Ways </th> <td colspan="7">8 way </td> <td colspan="4">12 way </td></tr> <tr> <th>Latency </th> <td colspan="2">3 </td> <td colspan="5">4 </td> <td>3/5 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>5 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th rowspan="3">Instruction </th> <th>Size </th> <td colspan="11">32 KB/core </td></tr> <tr> <th>ways </th> <td colspan="2">8 way<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </td> <td>4 way </td> <td colspan="4">8 way </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>8 way </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Latency </th> <td colspan="3">3 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>4 </td> <td>5 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="2"><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">TLB</a> </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>142 </td> <td>144<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="2" rowspan="4">L2 </th> <th>Size </th> <td colspan="2">2-3 MB/core </td> <td colspan="5">256 KB </td> <td>512 KB </td> <td>1.25 MB </td> <td colspan="2">2 MB<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>ways </th> <td colspan="5">8 way </td> <td>4 way </td> <td>8 way </td> <td>20 way </td> <td colspan="2">10 way </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Latency </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td colspan="4">12 </td> <td>13 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>14 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>TLB </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>1024 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>1536 </td> <td>2048 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="2" rowspan="3">L3 </th> <th>Size </th> <td colspan="2" rowspan="3"> </td> <td colspan="6">2 MB </td> <td colspan="2">3 MB </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>ways </th> <td colspan="6">16 way </td> <td colspan="5">12 way<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th>Latency </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>26-37<sup id="cite_ref-auto2_5-1" class="reference"><a href="#cite_note-auto2-5"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </td> <td>30-36<sup id="cite_ref-auto2_5-2" class="reference"><a href="#cite_note-auto2-5"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </td> <td>43<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </td> <td>74 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="2" rowspan="4">L4 </th> <th>Size </th> <td colspan="4" rowspan="4">None </td> <td colspan="3">0–128 MB </td> <td rowspan="4">None </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>ways </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>16<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Latency </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Type </th> <td colspan="2">GPU Memory only </td> <td>cache </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="4">Hyper-threading </th> <td colspan="2">No </td> <td colspan="9">Yes </td></tr> <tr> <th colspan="4">OoOE window </th> <td colspan="2">96<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </td> <td>128<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </td> <td>168 </td> <td colspan="2">192 </td> <td>224<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </td> <td>352 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>512<sup id="cite_ref-chipsandchhese_15-0" class="reference"><a href="#cite_note-chipsandchhese-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="2">In-flight </th> <th>Load </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>48 </td> <td>64 </td> <td colspan="3">72 </td> <td>128 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>192 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Store </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>32 </td> <td>36 </td> <td colspan="2">42 </td> <td>56 </td> <td>72 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>114 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="2">Scheduler </th> <th>Entries </th> <td colspan="2">32 </td> <td>36 </td> <td>54 </td> <td>60 </td> <td>64 </td> <td>97 </td> <td>160<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Dispatch </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>8 way </td> <td>10 way </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="2">Register file </th> <th>Integer </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>160 </td> <td colspan="2">168 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>280<sup id="cite_ref-chipsandchhese_15-1" class="reference"><a href="#cite_note-chipsandchhese-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>280<sup id="cite_ref-chipsandchhese_15-2" class="reference"><a href="#cite_note-chipsandchhese-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Floating-point </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>144 </td> <td colspan="2">168 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>224<sup id="cite_ref-chipsandchhese_15-3" class="reference"><a href="#cite_note-chipsandchhese-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>332<sup id="cite_ref-chipsandchhese_15-4" class="reference"><a href="#cite_note-chipsandchhese-15"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="2">Queue </th> <th>Instruction </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>18/thread </td> <td>20/thread </td> <td>20/thread </td> <td>25/thread </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th>Allocation </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td colspan="2">28/thread<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2">56 </td> <td>64/thread </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="4">Decode </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td colspan="2">4 + 1 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>6 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="9">Execution Ports </th> <th>Numbers </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td colspan="2">6<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2">8<sup id="cite_ref-auto1_19-0" class="reference"><a href="#cite_note-auto1-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </td> <td>8<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </td> <td>10 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>12 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 0 </th> <td> </td> <td> </td> <td>Integer<br />FP Mul<br />Branch </td> <td>Integer<br />FP Mul<br />Branch </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 1 </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>Integer<br />FP Mul </td> <td>Integer<br />FP Mul </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 2 </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>Load<br />Address </td> <td>Load<br />Store<br />Address </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 3 </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>Store Address </td> <td>Store<br />Load<br />Address </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 4 </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>Store Data </td> <td>Store Data </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 5 </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>Integer </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 6 </th> <td colspan="4" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—<sup id="cite_ref-auto1_19-1" class="reference"><a href="#cite_note-auto1-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </td> <td colspan="2">Integer<br />Branch </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th scope="row">Port 7 </th> <td colspan="2">Store Address </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="4">AGUs </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td>2 + 1 </td> <td>2 + 2 </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td></tr> <tr> <th colspan="3" rowspan="7">Instructions </th> <th scope="row"><a href="/wiki/SSE2" title="SSE2">SSE2</a> </th> <td colspan="11" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/SSE3" title="SSE3">SSE3</a> </th> <td colspan="11" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/SSE4" title="SSE4">SSE4</a> </th> <td colspan="1" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="10" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> </th> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="8" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/AVX2" class="mw-redirect" title="AVX2">AVX2</a> </th> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA</a> </th> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="7" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <th scope="row"><a href="/wiki/AVX-512" title="AVX-512">AVX512</a> </th> <td colspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td style="background: #FFD; color:black; vertical-align: middle; text-align: center;" class="partial table-partial">Yes/No </td> <td colspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td colspan="2" style="background: #FFD; color:black; vertical-align: middle; text-align: center;" class="partial table-partial">Yes/No </td></tr> <tr> <th colspan="4">μArchitecture </th> <th><a href="/wiki/Merom_(microarchitecture)" class="mw-redirect" title="Merom (microarchitecture)">Merom</a> </th> <th><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a> </th> <th><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> </th> <th><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> </th> <th><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> </th> <th><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a> </th> <th><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> </th> <th><a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake</a> </th> <th><a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a> </th> <th><a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a> </th> <th><a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake</a> </th></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text">Rocket Lake based on <a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a> is a CPU microarchitecture, a variant of Sunny Cove microarchitecture designed for 10 nm, backported to 14 nm.</span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text">1.25 MB in client</span> </li> <li id="cite_note-17"><span class="mw-cite-backlink"><b><a href="#cite_ref-17">^</a></b></span> <span class="reference-text">56 unified in Ivy Bridge</span> </li> </ol></div></div> <table class="wikitable mw-collapsible mw-collapsed"> <caption>Overview of Intel Core microarchitectures </caption> <tbody><tr> <th rowspan="2" scope="col">Brand </th> <th colspan="4" scope="colgroup"><a href="/wiki/Desktop_computer" title="Desktop computer">Desktop</a> </th> <th colspan="4" scope="colgroup"><a href="/wiki/Laptop" title="Laptop">Mobile</a> </th></tr> <tr> <th scope="col">Codename </th> <th scope="col">Cores </th> <th scope="col">Process </th> <th scope="col">Date released </th> <th scope="col">Codename </th> <th scope="col">Cores </th> <th scope="col">Process </th> <th scope="col">Date released </th></tr> <tr> <th scope="row">Core Solo </th> <td colspan="4" rowspan="3" style="text-align:center;"><small>Desktop version not available</small> </td> <td><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a> </td> <td>1 </td> <td rowspan="2">65 nm </td> <td rowspan="2">January 2006 </td></tr> <tr style="background:white"> <th scope="row">Core Duo </th> <td><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a> </td> <td>2 </td></tr> <tr style="background:white"> <th scope="row">Core 2 Solo </th> <td><a href="/wiki/Merom_(microprocessor)#Merom-L" title="Merom (microprocessor)">Merom-L</a><br /><a href="/wiki/Penryn_(microprocessor)#Penryn" title="Penryn (microprocessor)">Penryn-L</a> </td> <td>1<br />1 </td> <td>65 nm<br />45 nm </td> <td>September 2007<br />May 2008 </td></tr> <tr style="background:white"> <th scope="row">Core 2 Duo </th> <td><a href="/wiki/Conroe_(microprocessor)#Conroe" title="Conroe (microprocessor)">Conroe</a><br /><a href="/wiki/Conroe_(microprocessor)#Allendale" title="Conroe (microprocessor)">Allendale</a><br /><a href="/wiki/Wolfdale_(microprocessor)" title="Wolfdale (microprocessor)">Wolfdale</a> </td> <td>2<br />2<br />2 </td> <td>65 nm<br />65 nm<br />45 nm </td> <td>August 2006<br />January 2007<br />January 2008 </td> <td><a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a><br /><a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn</a> </td> <td>2<br />2 </td> <td>65 nm<br />45 nm </td> <td>July 2006<br />January 2008 </td></tr> <tr style="background:white"> <th scope="row">Core 2 Quad </th> <td><a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield</a><br /><a href="/wiki/Yorkfield_(microprocessor)" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield</a> </td> <td>4<br />4 </td> <td>65 nm<br />45 nm </td> <td>January 2007<br />March 2008 </td> <td><a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn QC</a> </td> <td>4 </td> <td>45 nm </td> <td>August 2008 </td></tr> <tr style="background:white"> <th scope="row">Core 2 Extreme </th> <td><a href="/wiki/Conroe_(microprocessor)#Conroe_XE" title="Conroe (microprocessor)">Conroe XE</a><br /><a href="/wiki/Kentsfield_(microprocessor)#Kentsfield_XE" title="Kentsfield (microprocessor)">Kentsfield XE</a><br /><a href="/wiki/Yorkfield_(microprocessor)#Yorkfield_XE" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield XE</a> </td> <td>2<br />4<br />4 </td> <td>65 nm<br />65 nm<br />45 nm </td> <td>July 2006<br />November 2006<br />November 2007 </td> <td><a href="/wiki/Merom_(microprocessor)#Merom_XE" title="Merom (microprocessor)">Merom XE</a><br /><a href="/wiki/Penryn_(microprocessor)#Penryn_XE" title="Penryn (microprocessor)">Penryn XE</a><br /><a href="/wiki/Penryn_(microprocessor)#Penryn_QC" title="Penryn (microprocessor)">Penryn QC XE</a> </td> <td>2<br />2<br />4 </td> <td>65 nm<br />45 nm<br />45 nm </td> <td>July 2007<br />January 2008<br />August 2008 </td></tr> <tr style="background:white"> <th scope="row">Core M </th> <td colspan="4" rowspan="4" style="text-align:center;"><small>Desktop version not available</small> </td> <td><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a> </td> <td>2 </td> <td>14 nm </td> <td>September 2014<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </td></tr> <tr style="background:white"> <th scope="row">Core m3 </th> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake</a><br /><a href="/wiki/Amber_Lake_(microarchitecture)" class="mw-redirect" title="Amber Lake (microarchitecture)">Amber Lake</a> </td> <td>2<br />2<br />2<br />2 </td> <td>14 nm<br />14 nm<br />14 nm<br />14 nm </td> <td>August 2015<br />September 2016<br />April 2017<br />August 2018 </td></tr> <tr style="background:white"> <th scope="row">Core m5 </th> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> </td> <td>2 </td> <td>14 nm </td> <td>August 2015 </td></tr> <tr style="background:white"> <th scope="row">Core m7 </th> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> </td> <td>2 </td> <td>14 nm </td> <td>August 2015 </td></tr> <tr style="background:white"> <th scope="row">Core i3 </th> <td><a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a><br /><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a> </td> <td>2<br />2<br />2<br />2<br />2<br />2<br />4<br />4<br />4<br />4<br />4 </td> <td>32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />Intel 7<br />Intel 7 </td> <td>January 2010<br />February 2011<br />September 2012<br />September 2013<br />September 2015<br />January 2017<br />October 2017<br />Jan. & April 2019<br />April 2020<br />January 2022<br />Jan. 2023 & 2024 </td> <td><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Cannon_Lake_(microarchitecture)" class="mw-redirect" title="Cannon Lake (microarchitecture)">Cannon Lake</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Whiskey_Lake_(microarchitecture)" class="mw-redirect" title="Whiskey Lake (microarchitecture)">Whiskey Lake</a><br /><a href="/wiki/Ice_Lake_(microarchitecture)" class="mw-redirect" title="Ice Lake (microarchitecture)">Ice Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake / B</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a><br /><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> </td> <td>2<br />2<br />2<br />2<br />2<br />2<br />2<br />2<br />2<br />2<br />2<br />4<br />2<br />2<br />2<br />2-4<br />6-8<br />5-6<br />8 </td> <td>32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />10 nm<br />14 nm<br />14 nm<br />10 nm<br />14 nm<br />10 nm<br />Intel 7<br />Intel 7<br />Intel 4 </td> <td>January 2010<br />February 2011<br />June 2012<br />June 2013<br />January 2015<br />Sept. 2015 & June 2016<br />August 2016<br />November 2016<br />Jan. & June 2017<br />April 2018<br />May 2018<br />July 2018<br />August 2018<br />May & Aug. 2019<br />September 2019<br />Sept. 2020, Jan. - May 2021<br />January 2022<br />Jan. 2023 & 2024<br />April 2024 </td></tr> <tr style="background:white"> <th scope="row">Core i5 </th> <td><a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield</a><br /><a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a><br /><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a> </td> <td>4<br />2<br />4<br />2<br />2-4<br />2-4<br />4<br />4<br />4<br />6<br />6<br />6<br />6<br />6-10<br />10-14 </td> <td>45 nm<br />32 nm<br />32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />Intel 7<br />Intel 7 </td> <td>September 2009<br />January 2010<br />January 2011<br />February 2011<br />April 2012<br />June 2013<br />June 2015<br />September 2015<br />January 2017<br />October 2017<br />Oct. 2018 & Jan. 2019<br />April 2020<br />March 2021<br />Nov. 2021 & Jan. 2022<br />Jan. 2023/2024 & Oct. 2023/2024 </td> <td><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake-R</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Amber_Lake_(microarchitecture)" class="mw-redirect" title="Amber Lake (microarchitecture)">Amber Lake</a><br /><a href="/wiki/Whiskey_Lake_(microarchitecture)" class="mw-redirect" title="Whiskey Lake (microarchitecture)">Whiskey Lake</a><br /><a href="/wiki/Ice_Lake_(microarchitecture)" class="mw-redirect" title="Ice Lake (microarchitecture)">Ice Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake-H</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake-H/B</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake-H/HX</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a><br /><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> </td> <td>2<br />2<br />2<br />2<br />2<br />2<br />2<br />4<br />4<br />4<br />2<br />4<br />4<br />4<br />4<br />4<br />4-6<br />10-12<br />8-12<br />6-12<br />8-14 </td> <td>32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />10 nm<br />14 nm<br />14 nm<br />10 nm<br />10 nm<br />Intel 7<br />Intel 7<br />Intel 7<br />Intel 4 </td> <td>January 2010<br />February 2011<br />May 2012<br />June 2013<br />January 2015<br />September 2015<br />August 2016<br />January 2017<br />October 2017<br />April 2018<br />Aug. 2018 & Oct. 2018<br />Aug. 2018 & April 2019<br />May & Aug. 2019<br />September 2019<br />April 2020<br />Sept. 2020 - May 2021<br />January - September 2021<br />January 2022<br />January & May 2022<br />Jan. 2023 & 2024<br />Dec. 2023 & Apr. 2024 </td></tr> <tr style="background:white"> <th scope="row">Core i7 </th> <td><a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield</a><br /><a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield</a><br /><a href="/wiki/Gulftown_(microprocessor)" class="mw-redirect" title="Gulftown (microprocessor)">Gulftown</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E</a><br /><a href="/wiki/Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Ivy_Bridge-E" class="mw-redirect" title="Ivy Bridge-E">Ivy Bridge-E</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake_(microarchitecture)" class="mw-redirect" title="Kaby Lake (microarchitecture)">Kaby Lake</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a> </td> <td>4<br />4<br />6<br />4<br />6<br />4<br />4<br />4<br />4-6<br />4<br />4<br />4<br />6<br />8<br />8<br />8<br />12<br />16-20 </td> <td>45 nm<br />45 nm<br />32 nm<br />32 nm<br />32 nm<br />32 nm<br />22 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />Intel 7<br />Intel 7 </td> <td>November 2008<br />September 2009<br />July 2010<br />January 2011<br />November 2011<br />February 2012<br />April 2012<br />June 2013<br />September 2013<br />June 2015<br />August 2015<br />January 2017<br />October 2017<br />October 2018<br />April 2020<br />March 2021<br />Nov. 2021 & Jan. 2022<br />Jan. 2023/2024 & Oct. 2023/2024 </td> <td><a href="/wiki/Clarksfield_(microprocessor)" title="Clarksfield (microprocessor)">Clarksfield</a><br /><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a><br /><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake</a><br /><a href="/wiki/Amber_Lake_(microarchitecture)" class="mw-redirect" title="Amber Lake (microarchitecture)">Amber Lake</a><br /><a href="/wiki/Whiskey_Lake_(microarchitecture)" class="mw-redirect" title="Whiskey Lake (microarchitecture)">Whiskey Lake</a><br /><a href="/wiki/Ice_Lake_(microarchitecture)" class="mw-redirect" title="Ice Lake (microarchitecture)">Ice Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake-H</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake-H/B</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake-H/HX</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)">Raptor Lake</a><br /><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> </td> <td>4<br />2<br />4<br />2<br />2-4<br />2-4<br />2<br />4<br />2-4<br />2<br />4<br />4-6<br />2<br />4<br />4<br />4-6<br />6-8<br />4<br />4-8<br />10-14<br />10-16<br />14-20<br />12-16 </td> <td>45 nm<br />32 nm<br />32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />10 nm<br />14 nm<br />14 nm<br />10 nm<br />10 nm<br />Intel 7<br />Intel 7<br />Intel 7<br />Intel 4 </td> <td>September 2009<br />January 2010<br />January 2011<br />February 2011<br />May 2012<br />June 2013<br />January 2015<br />June 2015<br />September 2015<br />August 2016<br />January 2017<br />April 2018<br />August 2018<br />Aug. 2018 & April 2019<br />May & Aug. 2019<br />September 2019<br />April 2020<br />September 2020<br />January - September 2021<br /> January 2022<br />January & May 2022<br />January 2023 & 2024<br /> Dec. 2023 & Apr. 2024 </td></tr> <tr style="background:white"> <th scope="row">Core i7<br />Extreme </th> <td><a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield</a><br /><a href="/wiki/Gulftown_(microprocessor)" class="mw-redirect" title="Gulftown (microprocessor)">Gulftown</a><br /><a href="/wiki/Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E</a><br /><a href="/wiki/Ivy_Bridge-E" class="mw-redirect" title="Ivy Bridge-E">Ivy Bridge-E</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-E</a><br /><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell-E</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake-X</a><br /><a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake-X</a> </td> <td>4<br />6<br />6<br />6<br />8<br />10<br />6-8<br />4 </td> <td>45 nm<br />32 nm<br />32 nm<br />22 nm<br />22 nm<br />14 nm<br />14 nm<br />14 nm </td> <td>November 2008<br />March 2010<br />November 2011<br />September 2013<br />August 2014<br />May 2016<br />June 2017<br />June 2017 </td> <td><a href="/wiki/Clarksfield_(microprocessor)" title="Clarksfield (microprocessor)">Clarksfield</a><br /><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a><br /><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a><br /><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> </td> <td>4<br />4<br />4<br />4 </td> <td>45 nm<br />32 nm<br />22 nm<br />22 nm </td> <td>September 2009<br />January 2011<br />May 2012<br />June 2013 </td></tr> <tr style="background:white"> <th>Core i9 </th> <td><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake-X</a><br /><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake-X</a><br /><a href="/wiki/Cascade_Lake_(microarchitecture)" class="mw-redirect" title="Cascade Lake (microarchitecture)">Cascade Lake-X</a><br /><a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a><br /><a href="/wiki/Comet_Lake_(microprocessor)" class="mw-redirect" title="Comet Lake (microprocessor)">Comet Lake</a><br /><a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake</a><br /><a href="/wiki/Raptor_Lake_(microprocessor)" class="mw-redirect" title="Raptor Lake (microprocessor)"> Raptor Lake</a> </td> <td>10<br />12<br />14-18<br />8<br />10<br />8<br />16<br />24 </td> <td>14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />14 nm<br />Intel 7<br />Intel 7 </td> <td>June 2017<br />August 2017<br />September 2017<br />October 2018<br />April 2020<br />March 2021<br />Nov. 2021 & Jan. 2022<br />Oct. 2022 / Jan.&Oct. 2023 </td> <td><a href="/wiki/Coffee_Lake_(microarchitecture)" class="mw-redirect" title="Coffee Lake (microarchitecture)">Coffee Lake-H</a><br /><a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake-H</a><br /><a href="/wiki/Tiger_Lake_(microprocessor)" class="mw-redirect" title="Tiger Lake (microprocessor)">Tiger Lake-H</a><br /><a href="/wiki/Alder_Lake_(microprocessor)" class="mw-redirect" title="Alder Lake (microprocessor)">Alder Lake-H/HX</a><br /><a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake-H/HX</a><br /><a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake-H</a> </td> <td>6<br />8<br />8<br />14-16<br />14-24<br />16 </td> <td>14 nm<br />14 nm<br />10 nm<br />Intel 7<br />Intel 7<br />Intel 4 </td> <td>April 2018<br />April 2020<br />May 2021<br />January & May 2022<br />January 2023 & 2024<br />December 2023 </td></tr> <tr> <td colspan="9" align="center"><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">List of Intel Core processors</a> </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1248256098">@media all and (max-width:720px){.mw-parser-output .mod-gallery{width:100%!important}}.mw-parser-output .mod-gallery{display:table}.mw-parser-output .mod-gallery-default{background:transparent;margin-top:4px}.mw-parser-output .mod-gallery-center{margin-left:auto;margin-right:auto}.mw-parser-output .mod-gallery-left{float:left}.mw-parser-output .mod-gallery-right{float:right}.mw-parser-output .mod-gallery-none{float:none}.mw-parser-output .mod-gallery-collapsible{width:100%}.mw-parser-output .mod-gallery .title,.mw-parser-output .mod-gallery .main,.mw-parser-output .mod-gallery .footer{display:table-row}.mw-parser-output .mod-gallery .title>div{display:table-cell;padding:0 4px 4px;text-align:center;font-weight:bold}.mw-parser-output .mod-gallery .main>div{display:table-cell}.mw-parser-output .mod-gallery .gallery{line-height:1.35em}.mw-parser-output .mod-gallery .footer>div{display:table-cell;padding:4px;text-align:right;font-size:85%;line-height:1em}.mw-parser-output .mod-gallery .title>div *,.mw-parser-output .mod-gallery .footer>div *{overflow:visible}.mw-parser-output .mod-gallery .gallerybox img{background:none!important}.mw-parser-output .mod-gallery .bordered-images .thumb img{border:solid var(--background-color-neutral,#eaecf0)1px}.mw-parser-output .mod-gallery .whitebg .thumb{background:var(--background-color-base,#fff)!important}</style><div class="mod-gallery mod-gallery-default mod-gallery-center"><div class="title"><div>Intel Core sub-brand logos, from 2020 (coinciding with the release of its <a href="#11th_generation">11th generation</a>) to 2023</div></div><div class="main"><div><ul class="gallery mw-gallery-traditional nochecker bordered-images whitebg"> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel_Core_i3_(11th_generation,_logo).svg" class="mw-file-description" title="Intel Core i3 logo"><img alt="Intel Core i3 logo" src="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Intel_Core_i3_%2811th_generation%2C_logo%29.svg/180px-Intel_Core_i3_%2811th_generation%2C_logo%29.svg.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Intel_Core_i3_%2811th_generation%2C_logo%29.svg/270px-Intel_Core_i3_%2811th_generation%2C_logo%29.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/b/b4/Intel_Core_i3_%2811th_generation%2C_logo%29.svg/360px-Intel_Core_i3_%2811th_generation%2C_logo%29.svg.png 2x" data-file-width="512" data-file-height="512" /></a></span></div> <div class="gallerytext">Intel Core i3 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel_Core_i5_(11th_generation,_logo).svg" class="mw-file-description" title="Intel Core i5 logo"><img alt="Intel Core i5 logo" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4b/Intel_Core_i5_%2811th_generation%2C_logo%29.svg/180px-Intel_Core_i5_%2811th_generation%2C_logo%29.svg.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4b/Intel_Core_i5_%2811th_generation%2C_logo%29.svg/270px-Intel_Core_i5_%2811th_generation%2C_logo%29.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4b/Intel_Core_i5_%2811th_generation%2C_logo%29.svg/360px-Intel_Core_i5_%2811th_generation%2C_logo%29.svg.png 2x" data-file-width="512" data-file-height="512" /></a></span></div> <div class="gallerytext">Intel Core i5 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel_Core_i7_(11th_generation,_logo).svg" class="mw-file-description" title="Intel Core i7 logo"><img alt="Intel Core i7 logo" src="//upload.wikimedia.org/wikipedia/en/thumb/5/5d/Intel_Core_i7_%2811th_generation%2C_logo%29.svg/180px-Intel_Core_i7_%2811th_generation%2C_logo%29.svg.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/5/5d/Intel_Core_i7_%2811th_generation%2C_logo%29.svg/270px-Intel_Core_i7_%2811th_generation%2C_logo%29.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/5/5d/Intel_Core_i7_%2811th_generation%2C_logo%29.svg/360px-Intel_Core_i7_%2811th_generation%2C_logo%29.svg.png 2x" data-file-width="512" data-file-height="512" /></a></span></div> <div class="gallerytext">Intel Core i7 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel_Core_i9_(11th_generation,_logo).svg" class="mw-file-description" title="Intel Core i9 logo"><img alt="Intel Core i9 logo" src="//upload.wikimedia.org/wikipedia/en/thumb/0/06/Intel_Core_i9_%2811th_generation%2C_logo%29.svg/180px-Intel_Core_i9_%2811th_generation%2C_logo%29.svg.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/0/06/Intel_Core_i9_%2811th_generation%2C_logo%29.svg/270px-Intel_Core_i9_%2811th_generation%2C_logo%29.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/0/06/Intel_Core_i9_%2811th_generation%2C_logo%29.svg/360px-Intel_Core_i9_%2811th_generation%2C_logo%29.svg.png 2x" data-file-width="512" data-file-height="512" /></a></span></div> <div class="gallerytext">Intel Core i9 logo</div> </li> </ul></div></div><div class="footer"><div>The shade of blue in each logo gets darker depending on how advanced the sub-brand is.</div></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1248256098"><div class="mod-gallery mod-gallery-default mod-gallery-center"><div class="title"><div>Intel Core sub-brand logos, from 2023 to present (officially released with <a href="/wiki/Raptor_Lake#Raptor_Lake-U_Refresh" title="Raptor Lake">Raptor Lake-U Refresh</a> in early 2024)</div></div><div class="main"><div><ul class="gallery mw-gallery-traditional nochecker bordered-images whitebg"> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-3-Badge-2023.png" class="mw-file-description" title="Intel Core 3 logo"><img alt="Intel Core 3 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/14/Intel-Core-3-Badge-2023.png/180px-Intel-Core-3-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/14/Intel-Core-3-Badge-2023.png/270px-Intel-Core-3-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/14/Intel-Core-3-Badge-2023.png/360px-Intel-Core-3-Badge-2023.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div> <div class="gallerytext">Intel Core 3 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-5-Badge-2023.png" class="mw-file-description" title="Intel Core 5 logo"><img alt="Intel Core 5 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fd/Intel-Core-5-Badge-2023.png/180px-Intel-Core-5-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fd/Intel-Core-5-Badge-2023.png/270px-Intel-Core-5-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fd/Intel-Core-5-Badge-2023.png/360px-Intel-Core-5-Badge-2023.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div> <div class="gallerytext">Intel Core 5 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-7-Badge-2023.png" class="mw-file-description" title="Intel Core 7 logo"><img alt="Intel Core 7 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Intel-Core-7-Badge-2023.png/180px-Intel-Core-7-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Intel-Core-7-Badge-2023.png/270px-Intel-Core-7-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Intel-Core-7-Badge-2023.png/360px-Intel-Core-7-Badge-2023.png 2x" data-file-width="3000" data-file-height="3000" /></a></span></div> <div class="gallerytext">Intel Core 7 logo</div> </li> </ul></div></div><div class="footer"><div>The number of dots on each logo increases depending on how advanced the sub-brand is.</div></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1248256098"><div class="mod-gallery mod-gallery-default mod-gallery-center"><div class="title"><div>Intel Core Ultra sub-brand logos, from 2023 to present (officially released with <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a> in late 2023)</div></div><div class="main"><div><ul class="gallery mw-gallery-traditional nochecker bordered-images whitebg"> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-Ultra-5-Badge-2023.png" class="mw-file-description" title="Intel Core Ultra 5 logo"><img alt="Intel Core Ultra 5 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Intel-Core-Ultra-5-Badge-2023.png/180px-Intel-Core-Ultra-5-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Intel-Core-Ultra-5-Badge-2023.png/270px-Intel-Core-Ultra-5-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/b2/Intel-Core-Ultra-5-Badge-2023.png/360px-Intel-Core-Ultra-5-Badge-2023.png 2x" data-file-width="2000" data-file-height="2000" /></a></span></div> <div class="gallerytext">Intel Core Ultra 5 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-Ultra-7-Badge-2023.png" class="mw-file-description" title="Intel Core Ultra 7 logo"><img alt="Intel Core Ultra 7 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Intel-Core-Ultra-7-Badge-2023.png/180px-Intel-Core-Ultra-7-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Intel-Core-Ultra-7-Badge-2023.png/270px-Intel-Core-Ultra-7-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Intel-Core-Ultra-7-Badge-2023.png/360px-Intel-Core-Ultra-7-Badge-2023.png 2x" data-file-width="2000" data-file-height="2000" /></a></span></div> <div class="gallerytext">Intel Core Ultra 7 logo</div> </li> <li class="gallerybox" style="width: 215px"> <div class="thumb" style="width: 210px; height: 210px;"><span typeof="mw:File"><a href="/wiki/File:Intel-Core-Ultra-9-Badge-2023.png" class="mw-file-description" title="Intel Core Ultra 9 logo"><img alt="Intel Core Ultra 9 logo" src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fc/Intel-Core-Ultra-9-Badge-2023.png/180px-Intel-Core-Ultra-9-Badge-2023.png" decoding="async" width="180" height="180" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fc/Intel-Core-Ultra-9-Badge-2023.png/270px-Intel-Core-Ultra-9-Badge-2023.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fc/Intel-Core-Ultra-9-Badge-2023.png/360px-Intel-Core-Ultra-9-Badge-2023.png 2x" data-file-width="2000" data-file-height="2000" /></a></span></div> <div class="gallerytext">Intel Core Ultra 9 logo</div> </li> </ul></div></div><div class="footer"><div>The number of dots on each logo increases depending on how advanced the sub-brand is.<br />The shade of blue in every logo is darker than the standard "Intel Core" sub-brand logos.</div></div></div> <div class="mw-heading mw-heading2"><h2 id="Product_lineup">Product lineup</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=2" title="Edit section: Product lineup"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Core">Core</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=3" title="Edit section: Core"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Enhanced_Pentium_M_(microarchitecture)" class="mw-redirect" title="Enhanced Pentium M (microarchitecture)">Enhanced Pentium M (microarchitecture)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For details about the processor core, see <a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah (microprocessor)</a>.</div> <p>The original <i>Core</i> brand refers to Intel's <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> mobile <a href="/wiki/Dual-core" class="mw-redirect" title="Dual-core">dual-core</a> <a href="/wiki/X86" title="X86">x86</a> CPUs, which were derived from the <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a> branded processors. The processor family used an enhanced version of the <a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6 microarchitecture</a>. It emerged in parallel with the <a href="/wiki/NetBurst" title="NetBurst">NetBurst microarchitecture</a> (Intel P68) of the <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> brand, and was a precursor of the 64-bit <a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core microarchitecture</a> of Core 2 branded CPUs. The Core brand had two branches: the <i>Duo</i> (dual-core) and <i>Solo</i> (single-core, which replaced the Pentium M brand of single-core mobile processor). </p><p>Intel launched the Core brand on January 6, 2006, with the release of the 32-bit <i><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></i> CPU –  Intel's first dual-core mobile (low-power) processor. Its dual-core layout closely resembled two interconnected <a href="/wiki/Pentium_M" title="Pentium M">Pentium M</a> branded CPUs packaged as a single <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> (piece) silicon chip (<a href="/wiki/Integrated_circuit" title="Integrated circuit">IC</a>). Hence, the 32-bit microarchitecture of Core branded CPUs –  contrary to its name –  had more in common with Pentium M branded CPUs than with the subsequent <a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64-bit</a> Core microarchitecture of <a href="/wiki/Core_2" class="mw-redirect" title="Core 2">Core 2</a> branded CPUs. Despite a major <a href="/wiki/Rebranding" title="Rebranding">rebranding</a> effort by <a href="/wiki/Intel" title="Intel">Intel</a> starting January 2006, some companies continued to market computers with the Yonah core marked as Pentium M. </p><p>The Core series is also the first Intel processor used in an <a href="/wiki/Macintosh" class="mw-redirect" title="Macintosh">Apple Macintosh</a> computer. The Core Duo was the CPU for the first generation <a href="/wiki/MacBook_Pro" title="MacBook Pro">MacBook Pro</a>, while the Core Solo appeared in Apple's <a href="/wiki/Mac_Mini" title="Mac Mini">Mac Mini</a> line. Core Duo signified the beginning of <a href="/wiki/Mac_transition_to_Intel_processors" title="Mac transition to Intel processors">Apple's shift to Intel processors</a> across the entire Mac line. </p><p>In 2007, Intel began branding the Yonah CPUs intended for mainstream mobile computers as <i><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a></i>, not to be confused with the desktop 64-bit Core microarchitecture CPUs also branded as Pentium Dual-Core. </p><p>September 2007 and January 4, 2008 marked the discontinuation of a number of <i>Core</i> branded CPUs including several Core Solo, Core Duo, Celeron and one Core 2 Quad products.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Core_Solo">Core Solo</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=4" title="Edit section: Core Solo"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Intel Core Solo<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> (product code 80538) uses the same two-core die as the Core Duo, but features only one <i>active</i> core. Depending on demand, Intel may also simply disable one of the cores to sell the chip at the Core Solo price—this requires less effort than launching and maintaining a separate line of CPUs that physically only have one core. Intel had used the same strategy previously with the <a href="/wiki/Intel_80486" class="mw-redirect" title="Intel 80486">486</a> CPU in which early <a href="/wiki/486SX" class="mw-redirect" title="486SX">486SX</a> CPUs were in fact manufactured as <a href="/wiki/486DX" class="mw-redirect" title="486DX">486DX</a> CPUs but with the <a href="/wiki/Floating_point_unit" class="mw-redirect" title="Floating point unit">FPU</a> disabled. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <td rowspan="2"><b><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></b> </td> <td><a href="/wiki/List_of_Intel_Core_microprocessors#"Yonah"_(65_nm)" class="mw-redirect" title="List of Intel Core microprocessors">Core Solo T1xxx</a></td> <td rowspan="2">2 MB</td> <td rowspan="2"><a href="/wiki/Socket_M" title="Socket M">Socket M</a></td> <td>27–31 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_microprocessors#"Yonah"_(ultra-low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core microprocessors">Core Solo U1xxx</a></td> <td>5.5–6 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Core_Duo">Core Duo</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=5" title="Edit section: Core Duo"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Intel Core Duo<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> (product code 80539) consists of two cores on one die, a 2 <a href="/wiki/Megabyte" title="Megabyte">MB</a> L2 cache shared by both cores, and an arbiter bus that controls both L2 cache and <a href="/wiki/Front-side_bus" title="Front-side bus">FSB (front-side bus)</a> access. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <td rowspan="3"><b><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">Yonah</a></b> </td> <td><a href="/wiki/List_of_Intel_Core_microprocessors#"Yonah"_(65_nm)" class="mw-redirect" title="List of Intel Core microprocessors">Core Duo T2xxx</a></td> <td rowspan="3">2 MB</td> <td rowspan="3"><a href="/wiki/Socket_M" title="Socket M">Socket M</a></td> <td>31 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_microprocessors#"Yonah"_(low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core microprocessors">Core Duo L2xxx</a></td> <td>15 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_microprocessors#"Yonah"_(ultra-low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core microprocessors">Core Duo U2xxx</a></td> <td>9 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_2">Core 2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=6" title="Edit section: Core 2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Intel Core (microarchitecture)</a></div> <p>The successor to Core is the mobile version of the <a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2</a> line of processors based on the Core microarchitecture,<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> released on July 27, 2006. The release of the mobile version of Intel Core 2 marks the reunification of Intel's desktop and mobile product lines as Core 2 processors were released for desktops and notebooks, unlike the first Intel Core CPUs that were targeted only for notebooks (although they were used in some small form factor and all-in-one desktops, like the <a href="/wiki/IMac" title="IMac">iMac</a> and the <a href="/wiki/Mac_Mini" title="Mac Mini">Mac Mini</a>). </p><p>Unlike the original Core, Intel Core 2 is a 64-bit processor, supporting <a href="/wiki/X86-64" title="X86-64">Intel Extended Memory 64 Technology</a> (EM64T). Another difference between the original Core Duo and the new Core 2 Duo is an increase in the amount of <a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">level 2 cache</a>. The new Core 2 Duo has tripled the amount of on-board cache to 6 MB. Core 2 also introduced a quad-core performance variant to the single- and dual-core chips, branded Core 2 Quad, as well as an enthusiast variant, Core 2 Extreme. All three chips are manufactured at a 65 nm <a href="/wiki/Photolithography" title="Photolithography">lithography</a>, and in 2008, a 45 nm lithography and support front side bus speeds ranging from 533 MT/s to 1.6 GT/s. In addition, the 45 nm die shrink of the Core microarchitecture adds <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a> support to all Core 2 microprocessors manufactured at a 45 nm lithography, therefore increasing the calculation rate of the processors. </p> <div class="mw-heading mw-heading4"><h4 id="Core_2_Solo">Core 2 Solo</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=7" title="Edit section: Core 2 Solo"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Core 2 Solo,<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> introduced in September 2007, is the successor to the Core Solo and is available only as an ultra-low-power mobile processor with 5.5 Watt thermal design power. The original U2xxx series "Merom-L" used a special version of the Merom chip with <a href="/wiki/CPUID" title="CPUID">CPUID</a> number 10661 (model 22, stepping A1) that only had a single core and was also used in some Celeron processors. The later SU3xxx are part of Intel's <a href="/wiki/CULV" class="mw-redirect" title="CULV">CULV</a> range of processors in a smaller μFC-BGA 956 package but contain the same Penryn chip as the dual-core variants, with one of the cores disabled during manufacturing. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th><a href="/wiki/Merom_(microprocessor)#Merom-L" title="Merom (microprocessor)">Merom-L</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom-L"_(ultra-low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Solo U2xxx</a></td> <td>1 MB</td> <td>FCBGA</td> <td>5.5 W </td></tr> <tr> <th><a href="/wiki/Penryn_(microprocessor)#Penryn-L" title="Penryn (microprocessor)">Penryn-L</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn-L"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Solo SU3xxx</a></td> <td>3 MB</td> <td>BGA956</td> <td>5.5 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Core_2_Duo">Core 2 Duo</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=8" title="Edit section: Core 2 Duo"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Laptop-intel-core2duo-t5500.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/170px-Laptop-intel-core2duo-t5500.jpg" decoding="async" width="170" height="227" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/255px-Laptop-intel-core2duo-t5500.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/340px-Laptop-intel-core2duo-t5500.jpg 2x" data-file-width="1536" data-file-height="2048" /></a><figcaption>Inside of a Sony VAIO laptop (VGN-C140G)</figcaption></figure> <p>The majority of the desktop and mobile Core 2 processor variants are Core 2 Duo<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> with two processor cores on a single <a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a>, <a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe</a>, <a href="/wiki/Conroe_(microprocessor)#Allendale" title="Conroe (microprocessor)">Allendale</a>, <a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn</a>, or <a href="/wiki/Wolfdale_(microprocessor)" title="Wolfdale (microprocessor)">Wolfdale</a> chip. These come in a wide range of performance and power consumption, starting with the relatively slow ultra-low-power Uxxxx (10 W) and low-power Lxxxx (17 W) versions, to the more performance oriented Pxxxx (25 W) and Txxxx (35 W) mobile versions and the Exxxx (65 W) desktop models. The mobile Core 2 Duo processors with an 'S' prefix in the name are produced in a smaller μFC-BGA 956 package, which allows building more compact laptops. </p><p>Within each line, a higher number usually refers to a better performance, which depends largely on core and front-side bus clock frequency and amount of second level cache, which are model-specific. Core 2 Duo processors typically use the full L2 cache of 2, 3, 4, or 6 MB available in the specific <a href="/wiki/Core_(microarchitecture)#Steppings" class="mw-redirect" title="Core (microarchitecture)">stepping</a> of the chip, while versions with the amount of cache reduced during manufacturing are sold for the low-end consumer market as <a href="/wiki/Celeron" title="Celeron">Celeron</a> or <a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Pentium Dual-Core</a> processors. Like those processors, some low-end Core 2 Duo models disable features such as <a href="/wiki/Intel_Virtualization_Technology" class="mw-redirect" title="Intel Virtualization Technology">Intel Virtualization Technology</a>. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th rowspan="4"><a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom"_(ultra-low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo U7xxx</a></td> <td>2 MB</td> <td rowspan="2">BGA479</td> <td>10 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom"_(low-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo L7xxx</a></td> <td>4 MB</td> <td>17 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom",_"Merom-2M"_(standard-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo T5xxx</a></td> <td>2 MB</td> <td rowspan="2"><a href="/wiki/Socket_M" title="Socket M">Socket M</a><br /><a href="/wiki/Socket_P" title="Socket P">Socket P</a><br />BGA479</td> <td rowspan="2">35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom",_"Merom-2M"_(standard-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo T7xxx</a></td> <td>2–4 MB </td></tr> <tr> <th rowspan="2"><a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe and<br />Allendale</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Allendale"_(65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Duo E4xxx</a></td> <td>2 MB</td> <td rowspan="2"><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></td> <td rowspan="2">65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Conroe"_(65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Duo E6xxx</a></td> <td>2–4 MB </td></tr> <tr> <th rowspan="11"><a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo SU7xxx</a></td> <td rowspan="2">3 MB</td> <td rowspan="4">BGA956</td> <td rowspan="2">10 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn-3M"_(ultra-low-voltage,_45_nm,_Small_Form_Factor)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo SU9xxx</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(low-voltage,_45_nm,_Small_Form_Factor)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo SL9xxx</a></td> <td rowspan="2">6 MB</td> <td>17 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(medium-voltage,_45_nm,_Small_Form_Factor)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo SP9xxx</a></td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(medium-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo P7xxx</a></td> <td rowspan="2">3 MB</td> <td rowspan="6"><a href="/wiki/Socket_P" title="Socket P">Socket P</a><br />FCBGA6</td> <td rowspan="3">25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(medium-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo P8xxx</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(medium-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo P9xxx</a></td> <td>6 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo T6xxx</a></td> <td>2 MB</td> <td rowspan="3">35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo T8xxx</a></td> <td>3 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo T9xxx</a></td> <td>6 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn"_(Apple_iMac_specific,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Duo E8xxx</a></td> <td>6 MB</td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a></td> <td>35–55 W </td></tr> <tr> <th rowspan="2"><a href="/wiki/Wolfdale_(microprocessor)" title="Wolfdale (microprocessor)">Wolfdale</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Wolfdale-3M"_(45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Duo E7xxx</a></td> <td>3 MB</td> <td rowspan="2"><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></td> <td rowspan="2">65 W </td></tr> <tr> <td><a href="/wiki/E8500" class="mw-redirect" title="E8500">Core 2 Duo E8xxx</a></td> <td>6 MB </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Core_2_Quad">Core 2 Quad</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=9" title="Edit section: Core 2 Quad"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Core 2 Quad<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> processors are <a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip modules</a> consisting of two dies similar to those used in Core 2 Duo, forming a quad-core processor. This allows twice the performance of a dual-core processors at the same clock frequency in scenarios that take advantage of multi-threading. </p><p>Initially, all Core 2 Quad models were versions of Core 2 Duo desktop processors, <a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield</a> derived from Conroe and <a href="/wiki/Yorkfield_(microprocessor)" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield</a> from Wolfdale, but later <a href="/wiki/Penryn_(microprocessor)#Penryn-QC" title="Penryn (microprocessor)">Penryn-QC</a> was added as a high-end version of the mobile dual-core Penryn. </p><p>The Xeon 32xx and 33xx processors are mostly identical versions of the desktop Core 2 Quad processors and can be used interchangeably. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th><a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Kentsfield"_(65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Quad Q6xxx</a></td> <td>2×4 MB</td> <td rowspan="3"><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></td> <td>95–105 W </td></tr> <tr> <th rowspan="2"><a href="/wiki/Yorkfield_(microprocessor)" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Yorkfield-6M"_(45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Quad Q8xxx</a></td> <td>2×2 MB</td> <td rowspan="2">65–95 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Yorkfield-6M"_(45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Quad Q9xxx</a></td> <td>2×3–2×6 MB </td></tr> <tr> <th><a href="/wiki/Penryn_(microprocessor)#Penryn-QC" title="Penryn (microprocessor)">Penryn-QC</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn_QC"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Quad Q9xxx</a></td> <td>2×3–2×6 MB</td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a></td> <td>45 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Core_2_Extreme">Core 2 Extreme</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=10" title="Edit section: Core 2 Extreme"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Core 2 Extreme processors<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> are enthusiast versions of Core 2 Duo and Core 2 Quad processors, usually with a higher clock frequency and an unlocked <a href="/wiki/CPU_multiplier" title="CPU multiplier">clock multiplier</a>, which makes them especially attractive for <a href="/wiki/Overclocking" title="Overclocking">overclocking</a>. This is similar to earlier <a href="/wiki/Pentium_D" title="Pentium D">Pentium D</a> processors labeled as <a href="/wiki/Extreme_Edition" class="mw-redirect" title="Extreme Edition">Extreme Edition</a>. Core 2 Extreme processors were released at a much higher price than their regular version, often $999 or more. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>L2 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th><a href="/wiki/Merom_(microprocessor)" title="Merom (microprocessor)">Merom XE</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Merom_XE"_(standard-voltage,_65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Extreme X7xxx</a></td> <td>4 MB</td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a></td> <td>44 W </td></tr> <tr> <th><a href="/wiki/Conroe_(microprocessor)" title="Conroe (microprocessor)">Conroe XE</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Conroe_XE"_(65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Extreme X6xxx</a></td> <td>4 MB</td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></td> <td>75 W </td></tr> <tr> <th><a href="/wiki/Kentsfield_(microprocessor)" title="Kentsfield (microprocessor)">Kentsfield</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Kentsfield_XE"_(65_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Extreme QX6xxx</a></td> <td>2×4 MB</td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a></td> <td>130 W </td></tr> <tr> <th><a href="/wiki/Penryn_(microprocessor)" title="Penryn (microprocessor)">Penryn XE</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn_XE"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Extreme X9xxx</a></td> <td>6 MB</td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a></td> <td>44 W </td></tr> <tr> <th><a href="/wiki/Penryn_(microprocessor)#Penryn-QC" title="Penryn (microprocessor)">Penryn-QC XE</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Penryn_QC_XE"_(standard-voltage,_45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Mobile Core 2 Extreme QX9300</a></td> <td>2×6 MB</td> <td><a href="/wiki/Socket_P" title="Socket P">Socket P</a></td> <td>45 W </td></tr> <tr> <th><a href="/wiki/Yorkfield_(microprocessor)" class="mw-redirect" title="Yorkfield (microprocessor)">Yorkfield</a> </th> <td><a href="/wiki/List_of_Intel_Core_2_microprocessors#"Yorkfield_XE"_(45_nm)" class="mw-redirect" title="List of Intel Core 2 microprocessors">Core 2 Extreme QX9xxx</a></td> <td>2×6 MB</td> <td><a href="/wiki/LGA_775" title="LGA 775">LGA 775</a> / <a href="/wiki/LGA_771" title="LGA 771">LGA 771</a></td> <td>130–150 W </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Core_i3/i5/i7/i9"><span id="Core_i3.2Fi5.2Fi7.2Fi9"></span>Core i3/i5/i7/i9<span class="anchor" id="Core_i3"></span><span class="anchor" id="Core_i5"></span><span class="anchor" id="Core_i7"></span></h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=11" title="Edit section: Core i3/i5/i7/i9"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading4"><h4 id="1st_generation">1st generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=12" title="Edit section: 1st generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem (microarchitecture)</a></div> <p>With the release of the Nehalem microarchitecture in November 2008,<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Intel" title="Intel">Intel</a> introduced a new naming scheme for its Core processors. There are three variants, Core i3, Core i5 and Core i7, but the names no longer correspond to specific technical features like the number of cores. Instead, the brand is now divided from low-level (i3), through mid-range (i5) to high-end performance (i7),<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> which correspond to three, four and five stars in Intel's Intel Processor Rating<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> following on from the entry-level Celeron (one star) and Pentium (two stars) processors.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> Common features of all Nehalem based processors include an integrated <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> memory controller as well as <a href="/wiki/QuickPath_Interconnect" class="mw-redirect" title="QuickPath Interconnect">QuickPath Interconnect</a> or <a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> and <a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> on the processor replacing the aging quad-pumped <a href="/wiki/Front_Side_Bus" class="mw-redirect" title="Front Side Bus">Front Side Bus</a> used in all earlier Core processors. All these processors have 256 KB L2 cache per core, plus up to 12 MB shared L3 cache. Because of the new I/O interconnect, chipsets and mainboards from previous generations can no longer be used with Nehalem-based processors. </p><p>Intel intended the Core i3 as the new low end of the performance processor line from Intel, following the retirement of the <a href="/wiki/Intel_Core_2" title="Intel Core 2">Core 2</a> brand.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> </p><p>The first Core i3 processors were launched on January 7, 2010.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p><p>The first Nehalem based Core i3 was <a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a>-based, with an integrated <a href="/wiki/GPU" class="mw-redirect" title="GPU">GPU</a> and two cores.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> The same processor is also available as Core i5 and Pentium, with slightly different configurations. </p><p>The Core i3-3xxM processors are based on <a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a>, the mobile version of the Clarkdale desktop processor. They are similar to the Core i5-4xx series but running at lower clock speeds and without <a href="/wiki/Turbo_Boost" class="mw-redirect" title="Turbo Boost">Turbo Boost</a>.<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> According to an Intel <a href="/wiki/FAQ" title="FAQ">FAQ</a> they do not support <a href="/wiki/ECC_memory" title="ECC memory">Error Correction Code (ECC) memory</a>.<sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> According to motherboard manufacturer Supermicro, if a Core i3 processor is used with a server chipset platform such as Intel 3400/3420/3450, the CPU supports ECC with UDIMM.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> When asked, Intel confirmed that, although the Intel 5 series chipset supports non-ECC memory only with the Core i5 or i3 processors, using those processors on a motherboard with 3400 series chipsets it supports the ECC function of ECC memory.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> A limited number of motherboards by other companies also support ECC with Intel Core ix processors; the Asus P8B WS is an example, but it does not support ECC memory under Windows non-server operating systems.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th><a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Clarkdale"_(32_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3</a></td> <td rowspan="3">2</td> <td>4 MB</td> <td><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td>73 W</td> <td rowspan="2"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br /> Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <th rowspan="2"><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-3xxM</a></td> <td>3 MB</td> <td><a href="/wiki/Socket_G1" title="Socket G1">rPGA-988A</a></td> <td>35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-3xxUM</a></td> <td>3 MB</td> <td>BGA-1288</td> <td>18 W</td> <td> </td></tr></tbody></table> <p><a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)"><i>Lynnfield</i></a> were the first Core i5 processors using the <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> microarchitecture, introduced on September 8, 2009, as a mainstream variant of the earlier Core i7.<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> Lynnfield Core i5 processors have an 8 MB <a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a>, a DMI bus running at 2.5 <a href="/wiki/Transfer_(computing)" class="mw-redirect" title="Transfer (computing)">GT/s</a> and support for dual-channel DDR3-800/1066/1333 memory and have <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> disabled. The same processors with different sets of features (Hyper-threading and other clock frequencies) enabled are sold as <a href="/wiki/Intel_Core_i7" class="mw-redirect" title="Intel Core i7">Core i7-8xx</a> and <a href="/wiki/Xeon#3400-series_"Lynnfield"" title="Xeon">Xeon 3400-series</a> processors, which should not be confused with high-end Core i7-9xx and Xeon 3500-series processors based on <a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield</a>. A new feature called Turbo Boost Technology was introduced which maximizes speed for demanding applications, dynamically accelerating performance to match the workload. </p><p>After <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> received a 32 nm <a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a> die shrink, <a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)"><i>Arrandale</i></a>, the dual-core mobile Core i5 processors and its desktop counterpart <a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)"><i>Clarkdale</i></a> was introduced in January 2010, together with Core i7-6xx and Core i3-3xx processors based on the same architecture. Arrandale processors have integrated graphics capability. Core i3-3xx does not support for <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a>, L3 cache in Core i5-5xx processors is reduced to 3 MB, while the Core i5-6xx uses the full cache,<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> Clarkdale is sold as Core i5-6xx, along with related Core i3 and Pentium processors. It has Hyper-Threading enabled and the full 4 MB L3 cache.<sup id="cite_ref-50" class="reference"><a href="#cite_note-50"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </p><p>According to Intel "Core i5 desktop processors and desktop boards typically do not support ECC memory",<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> but information on limited ECC support in the Core i3 section also applies to Core i5 and i7.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (October 2011)">citation needed</span></a></i>]</sup> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th rowspan="2"><a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield</a> </th> <td><a href="/wiki/Core_i5-750" class="mw-redirect" title="Core i5-750">Core i5-7xx</a></td> <td rowspan="2">4</td> <td rowspan="2">8 MB</td> <td rowspan="3"><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td>95 W</td> <td rowspan="2"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> </td></tr> <tr> <td><a href="/wiki/Core_i5-750" class="mw-redirect" title="Core i5-750">Core i5-7xxS</a></td> <td>82 W </td></tr> <tr> <th><a href="/wiki/Clarkdale_(microprocessor)" title="Clarkdale (microprocessor)">Clarkdale</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Clarkdale"_(32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-6xx</a></td> <td rowspan="5">2</td> <td>4 MB</td> <td>73–87 W</td> <td rowspan="5">Direct Media Interface,<br /> Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <th rowspan="4"><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-5xxM</a></td> <td rowspan="4">3 MB</td> <td rowspan="2"><a href="/wiki/Socket_G1" title="Socket G1">rPGA-988A</a></td> <td rowspan="2">35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxM</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-5xxUM</a></td> <td rowspan="2">BGA-1288</td> <td rowspan="2">18 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxUM</a><sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <p>The Core i7 brand targets the business and high-end consumer markets for both desktop and laptop computers,<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> and is distinguished from the <a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a> (entry-level consumer), <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> (mainstream consumer), and <a href="/wiki/Xeon" title="Xeon">Xeon</a> (server and workstation) brands. </p><p>Introduced in late 2008, <a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)"><i>Bloomfield</i></a> was the first Core i7 processors based on the Nehalem architecture.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-i7_flagship_brand_57-0" class="reference"><a href="#cite_note-i7_flagship_brand-57"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> The following year, <a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)"><i>Lynnfield</i></a> desktop processors and <a href="/wiki/Clarksfield_(microprocessor)" title="Clarksfield (microprocessor)"><i>Clarksfield</i></a> mobile processors brought new quad-core Core i7 models based on the said architecture.<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </p><p>After <a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> received a 32 nm <a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a> die shrink, <a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)"><i>Arrandale</i></a> dual-core mobile processors were introduced in January 2010, followed by Core i7's first six-core desktop processor <i><a href="/wiki/Gulftown" title="Gulftown">Gulftown</a></i> on March 16, 2010. Both the regular Core i7 and the <i>Extreme Edition</i> are advertised as five stars in the Intel Processor Rating. </p><p>The first-generation Core i7 uses two different sockets; <a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a> designed for high-end desktops and servers, and <a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a> used in low- and mid-end desktops and servers. In each generation, the highest-performing Core i7 processors use the same socket and <a href="/wiki/QPI" class="mw-redirect" title="QPI">QPI</a>-based architecture as the medium-end Xeon processors of that generation, while lower-performing Core i7 processors use the same socket and PCIe/DMI/FDI architecture as the Core i5. </p><p>"Core i7" is a successor to the <a href="/wiki/Intel_Core_2" title="Intel Core 2">Intel Core 2</a> brand.<sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-i7-920_60-0" class="reference"><a href="#cite_note-i7-920-60"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-i7-940_61-0" class="reference"><a href="#cite_note-i7-940-61"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-i7-965_62-0" class="reference"><a href="#cite_note-i7-965-62"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> Intel representatives stated that they intended the <a href="/wiki/Moniker" class="mw-redirect" title="Moniker">moniker</a> <i>Core i7</i> to help consumers decide which processor to purchase as Intel releases newer Nehalem-based products in the future.<sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <tbody><tr> <th>Code name</th> <th>Brand name</th> <th>Cores</th> <th>L3 Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>Busses</th> <th>Release<br />Date </th></tr> <tr> <td rowspan="2"><a href="/wiki/Gulftown_(microprocessor)" class="mw-redirect" title="Gulftown (microprocessor)">Gulftown</a></td> <td><a href="/wiki/I7-980X" class="mw-redirect" title="I7-980X">Core i7-9xxX Extreme Edition</a></td> <td rowspan="2">6</td> <td rowspan="2">12 MB</td> <td rowspan="4"><a href="/wiki/LGA_1366" title="LGA 1366">LGA 1366</a></td> <td rowspan="4">130 W</td> <td rowspan="2"><a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">32 nm</a></td> <td rowspan="4"><a href="/wiki/QuickPath" class="mw-redirect" title="QuickPath">QPI</a>,<br /> 3 × <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a></td> <td>Mar 2010 </td></tr> <tr> <td><a href="/wiki/I7-980X" class="mw-redirect" title="I7-980X">Core i7-970</a></td> <td>Jul 2010 </td></tr> <tr> <td rowspan="2"><a href="/wiki/Bloomfield_(microprocessor)" title="Bloomfield (microprocessor)">Bloomfield</a></td> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Bloomfield"_(45_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-9xx Extreme Edition</a></td> <td rowspan="7">4</td> <td rowspan="6">8 MB</td> <td rowspan="7"><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">45 nm</a></td> <td rowspan="2">Nov 2008 </td></tr> <tr> <td><a href="/wiki/I7-920" class="mw-redirect" title="I7-920">Core i7-9xx (except Core i7-970/980)</a> </td></tr> <tr> <td rowspan="2"><a href="/wiki/Lynnfield_(microprocessor)" title="Lynnfield (microprocessor)">Lynnfield</a></td> <td><a href="/wiki/I7-860" class="mw-redirect" title="I7-860">Core i7-8xx</a></td> <td rowspan="2"><a href="/wiki/LGA_1156" title="LGA 1156">LGA 1156</a></td> <td>95 W</td> <td rowspan="5"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a>,<br /><a href="/wiki/PCI-e" class="mw-redirect" title="PCI-e">PCI-e</a>,<br /> 2 × <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a></td> <td>Sep 2009 </td></tr> <tr> <td><a href="/wiki/I7-860S" class="mw-redirect" title="I7-860S">Core i7-8xxS</a></td> <td>82 W</td> <td>Jan 2010 </td></tr> <tr> <td rowspan="3"><a href="/wiki/Clarksfield_(microprocessor)" title="Clarksfield (microprocessor)">Clarksfield</a></td> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Clarksfield"_(45_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-9xxXM Extreme Edition</a></td> <td rowspan="4"><a href="/wiki/Socket_G1" title="Socket G1">rPGA-988A</a></td> <td>55 W</td> <td rowspan="3">Sep 2009 </td></tr> <tr> <td><a href="/wiki/I7-820QM" class="mw-redirect" title="I7-820QM">Core i7-8xxQM</a></td> <td rowspan="2">45 W </td></tr> <tr> <td><a href="/wiki/I7-720QM" class="mw-redirect" title="I7-720QM">Core i7-7xxQM</a></td> <td>6 MB </td></tr> <tr> <td rowspan="3"><a href="/wiki/Arrandale_(microprocessor)" class="mw-redirect" title="Arrandale (microprocessor)">Arrandale</a></td> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-6xxM</a></td> <td rowspan="3">2</td> <td rowspan="3">4 MB</td> <td>35 W</td> <td rowspan="3"><a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">32 nm</a></td> <td rowspan="3"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">DMI</a>,<br /><a href="/wiki/PCI-e" class="mw-redirect" title="PCI-e">PCI-e</a>,<br /> <a href="/wiki/Flexible_Display_Interface" title="Flexible Display Interface">FDI</a>,<br /> 2 × <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a></td> <td rowspan="3">Jan 2010 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-6xxLM</a></td> <td rowspan="2">BGA-1288</td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Arrandale"_(MCP,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-6xxUM</a></td> <td>18 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="2nd_generation">2nd generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=13" title="Edit section: 2nd generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a></div> <p>In early 2011, Intel introduced a new microarchitecture named <i>Sandy Bridge</i>. This is the second generation of the Core processor microarchitecture. It kept all the existing brands from Nehalem, including Core i3/i5/i7, and introduced new model numbers. The initial set of Sandy Bridge processors includes dual- and quad-core variants, all of which use a single 32 nm die for both the CPU and integrated GPU cores, unlike the earlier microarchitectures. All Core i3/i5/i7 processors with the Sandy Bridge microarchitecture have a four-digit model number. With the mobile version, the <a href="/wiki/Thermal_design_power" title="Thermal design power">thermal design power</a> can no longer be determined from a one- or two-letter suffix but is encoded into the CPU number. Starting with Sandy Bridge, Intel no longer distinguishes the code names of the processor based on number of cores, socket or intended usage; they all use the same code name as the microarchitecture itself. </p><p><a href="/wiki/Ivy_Bridge_(microprocessor)" class="mw-redirect" title="Ivy Bridge (microprocessor)">Ivy Bridge</a> is the codename for Intel's 22 nm die shrink of the Sandy Bridge microarchitecture based on tri-gate ("3D") transistors, introduced in April 2012. </p><p><span class="anchor" id="SB_Core_i3"></span> Released on January 20, 2011, the Core i3-2xxx line of desktop and mobile processors is a direct replacement of the 2010 "Clarkdale" Core i3-5xx and "Arrandale" Core i3-3xxM models, based on the new microarchitecture. While they require new sockets and chipsets, the user-visible features of the Core i3 are largely unchanged, including the lack of support for <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a> and <a href="/wiki/AES-NI" class="mw-redirect" title="AES-NI">AES-NI</a>. Unlike the Sandy Bridge-based Celeron and Pentium processors, the Core i3 line does support the new <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a>. This particular processor is the entry-level processor of this new series of Intel processors. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th rowspan="2"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-21xx</a></td> <td rowspan="4">2</td> <td rowspan="4">3 MB</td> <td rowspan="2"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>65 W</td> <td rowspan="4"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-21xxT</a></td> <td rowspan="2">35 W </td></tr> <tr> <th rowspan="2"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Sandy_Bridge"_(32_nm)_2" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-2xx0M</a></td> <td>rPGA-988B<br />BGA-1023 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Sandy_Bridge"_(32_nm)_2" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-2xx7M</a></td> <td>BGA-1023</td> <td>17 W </td></tr></tbody></table> <p><span class="anchor" id="SB_Core_i5"></span> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Core_i5-2500k_7754.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i5-2500k_7754.jpg/220px-Intel_Core_i5-2500k_7754.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i5-2500k_7754.jpg/330px-Intel_Core_i5-2500k_7754.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/87/Intel_Core_i5-2500k_7754.jpg/440px-Intel_Core_i5-2500k_7754.jpg 2x" data-file-width="2000" data-file-height="2000" /></a><figcaption>A Core i5-2500K. The K suffix indicates an unlocked clock multiplier, which allows for easier <a href="/wiki/Overclocking" title="Overclocking">overclocking</a>.</figcaption></figure> <p>In January 2011, Intel released new quad-core Core i5 processors based on the "Sandy Bridge" microarchitecture at CES 2011. New dual-core mobile processors and desktop processors arrived in February 2011. </p><p>The Core i5-2xxx line of desktop processors are mostly quad-core chips, with the exception of the dual-core Core i5-2390T, and include integrated graphics, combining the key features of the earlier Core i5-6xx and Core i5-7xx lines. The suffix after the four-digit model number designates unlocked multiplier (K), low-power (S) and ultra-low-power (T). </p><p>The desktop CPUs now all have four non-<a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a> cores (like the i5-750), with the exception of the i5-2390T. The DMI bus runs at 5 GT/s. </p><p>The mobile Core i5-2xxxM processors are all dual-core and hyper-threaded chips like the previous Core i5-5xxM series, and share most of the features with that product line. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th rowspan="4"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(quad-core,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-2xxx<br />Core i5-2xxxK</a></td> <td rowspan="3">4</td> <td rowspan="3">6 MB</td> <td rowspan="4"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>95 W</td> <td rowspan="6"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(quad-core,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-2xxxS</a></td> <td>65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(quad-core,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-25xxT</a></td> <td>45 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(dual-core,_32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-23xxT</a></td> <td rowspan="3">2</td> <td rowspan="3">3 MB</td> <td rowspan="2">35 W </td></tr> <tr> <th rowspan="2"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-2xxxM</a></td> <td>rPGA-988B<br />BGA-1023 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-2xx7M</a></td> <td>BGA-1023</td> <td>17 W </td></tr> </tbody></table> <p><span class="anchor" id="SB_Core_i7"></span> The Core i7 brand was the high-end for Intel's desktop and mobile processors, until the announcement of the i9 in 2017. Its Sandy Bridge models feature the largest amount of L3 cache and the highest clock frequency. Most of these models are very similar to their smaller Core i5 siblings. The quad-core mobile Core i7-2xxxQM/XM processors follow the previous "Clarksfield" Core i7-xxxQM/XM processors, but now also include integrated graphics. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <th rowspan="3"><a href="/wiki/Sandy_Bridge-E" class="mw-redirect" title="Sandy Bridge-E">Sandy Bridge-E (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge-E"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-39xxX</a></td> <td rowspan="2">6</td> <td>15 MB</td> <td rowspan="3"><a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a></td> <td rowspan="3">130 W</td> <td rowspan="11"><a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">32 nm</a></td> <td rowspan="3"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a></td> <td rowspan="3">November 2011 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge-E"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-39xxK</a></td> <td>12 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge-E"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-38xx</a></td> <td rowspan="6">4</td> <td>10 MB </td></tr> <tr> <th rowspan="2"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xxxK, i7-2xxx</a></td> <td rowspan="4">8 MB</td> <td rowspan="2"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>95 W</td> <td rowspan="8"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></td> <td rowspan="5">January 2011 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xxxS</a></td> <td>65 W </td></tr> <tr> <th rowspan="6"><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge_(quad-core)"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xxxXM</a></td> <td rowspan="4">rPGA-988B<br />BGA-1023</td> <td>55 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge_(quad-core)"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-28xxQM</a></td> <td rowspan="2">45 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge_(quad-core)"_(32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xxxQE, i7-26xxQM, i7-27xxQM</a></td> <td>6 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge"_(dual-core,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xx0M</a></td> <td rowspan="3">2</td> <td rowspan="3">4 MB</td> <td>35 W</td> <td rowspan="3">February 2011 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge"_(dual-core,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xx9M</a></td> <td rowspan="2">BGA-1023</td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Sandy_Bridge"_(dual-core,_32_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-2xx7M</a></td> <td>17 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="3rd_generation">3rd generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=14" title="Edit section: 3rd generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (microarchitecture)</a></div> <p>Ivy Bridge is the codename for a "third generation" line of processors based on the 22 nm manufacturing process developed by Intel. Mobile versions of the CPU were released in April 2012 following with desktop versions in September 2012. </p> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">April 2014</span>)</i></span></div></td></tr></tbody></table> <p><span class="anchor" id="Ivy_Bridge_Core_i3"></span> </p><p>The Ivy Bridge-based Core-i3-3xxx line is a minor upgrade to 22 nm process technology and better graphics. </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3<br />Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th rowspan="2"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-32xx</a></td> <td rowspan="5">2</td> <td rowspan="5">3 MB</td> <td rowspan="2"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>55 W</td> <td rowspan="5"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-32xxT</a></td> <td rowspan="2">35 W </td></tr> <tr> <th rowspan="3"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Ivy_Bridge"_(22_nm)_2" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-3xx0M</a></td> <td>rPGA-988B<br />BGA-1023 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Ivy_Bridge"_(22_nm)_2" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-3xx7U</a></td> <td rowspan="2">BGA-1023</td> <td>17 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Ivy_Bridge"_(22_nm)_2" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-3xx9Y</a></td> <td>13 W </td></tr></tbody></table> <p><span class="anchor" id="Ivy_BridgeCore_i5"></span> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3<br />Cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>I/O Bus </th></tr> <tr> <th rowspan="4"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-3xxx<br />Core i5-3xxxK</a></td> <td rowspan="3">4</td> <td rowspan="3">6 MB</td> <td rowspan="4"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>77 W</td> <td rowspan="7"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-3xxxS</a></td> <td>65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-35xxT</a></td> <td>45 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-34xxT</a></td> <td rowspan="4">2</td> <td rowspan="4">3 MB</td> <td rowspan="2">35 W </td></tr> <tr> <th rowspan="3"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-3xx0M</a></td> <td>rPGA-988B<br />BGA-1023 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-3xx7U</a></td> <td rowspan="2">BGA-1023</td> <td>17 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-3xx9Y</a></td> <td>13 W </td></tr></tbody></table> <p><span class="anchor" id="Ivy_BridgeCore_i7"></span> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <th rowspan="3"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge-E (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge-E"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4960X</a></td> <td rowspan="2">6</td> <td>15 MB</td> <td rowspan="3"><a href="/wiki/LGA_2011" title="LGA 2011">LGA 2011</a></td> <td rowspan="3">130 W</td> <td rowspan="14"><a href="/wiki/22_nanometer" class="mw-redirect" title="22 nanometer">22 nm</a></td> <td rowspan="3"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a></td> <td rowspan="3">September 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge-E"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4930K</a></td> <td>12 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge-E"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4820K</a></td> <td rowspan="8">4</td> <td>10 MB </td></tr> <tr> <th rowspan="3"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-37xx, i7-37xxK</a></td> <td rowspan="5">8 MB</td> <td rowspan="11"><a href="/wiki/LGA_1155" title="LGA 1155">LGA 1155</a></td> <td>77 W</td> <td rowspan="11"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></td> <td rowspan="10">April 2012 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-37xxS</a></td> <td>65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-37xxT</a></td> <td>45 W </td></tr> <tr> <th rowspan="8"><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge_(quad-core)"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xxxXM</a></td> <td>55 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge_(quad-core)"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-38xxQM</a></td> <td rowspan="2">45 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge_(quad-core)"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-36x0QM, i7-3xx0QE, i7-36x5QM,<br /> i7-3xx5QE, i7-37xxQM</a></td> <td rowspan="2">6 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge_(quad-core)"_(22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xx2QM, i7-3xx2QE</a></td> <td rowspan="2">35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xxxM</a></td> <td rowspan="4">2</td> <td rowspan="4">4 MB </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xxxLE</a></td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xx7U, i7-3xx7UE</a></td> <td>17 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Ivy_Bridge"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-3xx9Y</a></td> <td>13 W</td> <td>January 2013 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="4th_generation">4th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=15" title="Edit section: 4th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell (microarchitecture)</a></div> <p>Haswell is the fourth generation Core processor microarchitecture, and was released in 2013. </p><p><span class="anchor" id="Haswell_Core_i3"></span> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <th rowspan="4"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-DT (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-DT"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-43xx</a></td> <td rowspan="10">2</td> <td rowspan="2">4 MB</td> <td rowspan="2">HD 4600</td> <td rowspan="4"><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></td> <td>54 W</td> <td rowspan="10"><a href="/wiki/22_nanometer" class="mw-redirect" title="22 nanometer">22 nm</a></td> <td rowspan="10"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></td> <td rowspan="7">September 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-DT"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-43xxT, Core i3-4xxxTE</a></td> <td>35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-DT"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-41xx</a></td> <td rowspan="8">3 MB</td> <td rowspan="2">HD 4400</td> <td>54 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-DT"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-41xxT</a></td> <td>35 W </td></tr> <tr> <th rowspan="6"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-MB (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-H"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xx2E</a></td> <td rowspan="3">HD 4600</td> <td rowspan="2">BGA 1364</td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-H"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xx0E</a></td> <td rowspan="2">37 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-MB"_(22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xxxM</a></td> <td>Socket G3 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-ULT"_(SiP,_22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xx8U</a></td> <td>Iris 5100</td> <td rowspan="3">BGA 1168</td> <td>28 W</td> <td rowspan="3">June 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-ULT"_(SiP,_22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xx0U, Core i3-4xx5U</a></td> <td>HD 4400</td> <td>15 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_microprocessors#"Haswell-ULX"_(SiP,_22_nm)" class="mw-redirect" title="List of Intel Core i3 microprocessors">Core i3-4xxxY</a></td> <td>HD 4200</td> <td>11.5 W </td></tr></tbody></table> <p><span class="anchor" id="Haswell_Core_i5"></span> </p> <table class="wikitable"> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release Date </th></tr> <tr> <th rowspan="5"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-DT (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-DT"_(quad-core,_22_nm,_4th_generation)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxx, i5-46xxK</a></td> <td rowspan="3">4</td> <td rowspan="3">6 MB</td> <td rowspan="5">HD 4600</td> <td rowspan="5"><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></td> <td>84 W</td> <td rowspan="14"><a href="/wiki/22_nanometer" class="mw-redirect" title="22 nanometer">22 nm</a></td> <td rowspan="14"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></td> <td rowspan="6">June 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-DT"_(quad-core,_22_nm,_4th_generation)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxxS</a></td> <td>65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-DT"_(quad-core,_22_nm,_4th_generation)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-46xxT</a></td> <td>45 W </td></tr> <tr> <td rowspan="2"><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-DT"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-45xxT, Core i5-45xxTE</a></td> <td rowspan="2">2</td> <td rowspan="2">4 MB</td> <td>35 W </td></tr> <tr> <td>65 W </td></tr> <tr> <th><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-H (MCP)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxxR</a> </td> <td>4 </td> <td>4 MB </td> <td>Iris Pro 5200 </td> <td rowspan="4">BGA 1364 </td> <td>65 W </td></tr> <tr> <th rowspan="8"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-MB (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-H"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxxH</a></td> <td rowspan="8">2</td> <td rowspan="8">3 MB</td> <td rowspan="4">HD 4600</td> <td>47 W</td> <td rowspan="4">September 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-H"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xx2E</a></td> <td>25 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-H"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xx0E</a></td> <td rowspan="2">37 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-MB"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxxM</a></td> <td>Socket G3 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xx8U</a></td> <td>Iris 5100</td> <td rowspan="4">BGA1168</td> <td>28 W</td> <td rowspan="4">June 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4x50U</a></td> <td>HD 5000</td> <td rowspan="2">15 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4x00U</a></td> <td>HD 4400 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i5_microprocessors#"Haswell-ULX"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i5 microprocessors">Core i5-4xxxY</a></td> <td>HD 4200</td> <td>11.5 W </td></tr></tbody></table> <p><span class="anchor" id="Haswell_Core_i7"></span> </p> <table class="wikitable"> <caption> </caption> <tbody><tr> <th>Codename</th> <th>Brand name (list)</th> <th>Cores</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <th rowspan="3"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-E (Desktop)</a><sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> </th> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/82930/Intel-Core-i7-5960X-Processor-Extreme-Edition-20M-Cache-up-to-3_50-GHz">Core i7-5960X</a> </td> <td>8 </td> <td>20 MB </td> <td rowspan="3">N/A </td> <td rowspan="3">LGA 2011-3 </td> <td rowspan="3">140 W </td> <td rowspan="17">22 nm </td> <td rowspan="3"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> </td> <td rowspan="3">September 2014 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/82931/Intel-Core-i7-5930K-Processor-15M-Cache-up-to-3_70-GHz">Core i7-5930K</a> </td> <td rowspan="2">6 </td> <td rowspan="2">15 MB </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/82932/Intel-Core-i7-5820K-Processor-15M-Cache-up-to-3_60-GHz">Core i7-5820K</a> </td></tr> <tr> <th rowspan="5"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-DT (Desktop)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-DT"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47xx, i7-47xxK</a></td> <td rowspan="9">4</td> <td rowspan="4">8 MB</td> <td rowspan="4">HD 4600</td> <td rowspan="4"><a href="/wiki/LGA_1150" title="LGA 1150">LGA 1150</a></td> <td>84 W</td> <td rowspan="14"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></td> <td rowspan="9">June 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-DT"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47xxS</a></td> <td>65 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-DT"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47x0T</a></td> <td>45 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-DT"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47x5T</a></td> <td>35 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-H"_(MCP,_quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47xxR</a></td> <td rowspan="4">6 MB</td> <td rowspan="2">Iris Pro 5200</td> <td rowspan="3">BGA 1364</td> <td>65 W </td></tr> <tr> <th rowspan="9"><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell-MB (Mobile)</a> </th> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-H"_(MCP,_quad-core,_22_nm)_2" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4x50HQ, Core i7-4x60HQ<br />Core i7-4x50EQ, Core i7-4x60EQ</a></td> <td>47 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-H"_(MCP,_quad-core,_22_nm)_2" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47x2HQ, Core i7-47x2EQ<br />Core i7-470xHQ, Core i7-470xEQ</a></td> <td rowspan="4">HD 4600</td> <td>37 W<br />47 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-MB"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-47x2MQ<br />Core i7-470xMQ</a></td> <td rowspan="3">Socket G3</td> <td>37 W<br />47 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-MB"_(quad-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-49xxMQ, Core i7-4xxxXM</a></td> <td>8 MB</td> <td>57 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-MB"_(dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4xxxM</a></td> <td rowspan="5">2</td> <td rowspan="5">4 MB</td> <td>35 W</td> <td>September 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4xx8U</a></td> <td>Iris 5100</td> <td rowspan="4">BGA 1168</td> <td>28 W</td> <td rowspan="4">June 2013 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4x50U</a></td> <td>HD 5000</td> <td rowspan="2">15 W </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-ULT"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4x00U</a></td> <td>HD 4400 </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i7_microprocessors#"Haswell-ULX"_(SiP,_dual-core,_22_nm)" class="mw-redirect" title="List of Intel Core i7 microprocessors">Core i7-4xxxY</a></td> <td>HD 4200</td> <td>11.5 W </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="5th_generation">5th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=16" title="Edit section: 5th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell (microarchitecture)</a></div> <p>Broadwell is the fifth generation Core processor microarchitecture, and was released by Intel on September 6, 2014, and began shipping in late 2014. It is the first to use a 14 nm chip.<sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> Additionally, mobile processors were launched in January 2015<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> and Desktop Core i5 and i7 processors were released in June 2015.<sup id="cite_ref-TechReportBroadwell_67-0" class="reference"><a href="#cite_note-TechReportBroadwell-67"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup> </p><p><b>Desktop processor (DT-Series)</b> </p> <table class="wikitable"> <tbody><tr> <th>Processor branding</th> <th>Model (list)</th> <th>Cores <br /> (Threads)</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/88040/Intel-Core-i7-5775C-Processor-6M-Cache-up-to-3_70-GHz">5775C</a> </td> <td rowspan="2">4 (8) </td> <td rowspan="2">6 MB </td> <td rowspan="5">Iris 6200 </td> <td rowspan="5">LGA 1150 </td> <td rowspan="5">65 W </td> <td rowspan="5">14 nm </td> <td rowspan="5"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>, <p>Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </p> </td> <td rowspan="5">June 2015 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/87718/Intel-Core-i7-5775R-Processor-6M-Cache-up-to-3_80-GHz">5775R</a> </td></tr> <tr> <td rowspan="3">Core i5 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/88095/Intel-Core-i5-5675C-Processor-4M-Cache-up-to-3_60-GHz">5675C</a> </td> <td rowspan="3">4 (4) </td> <td rowspan="3">4 MB </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/87715/Intel-Core-i5-5675R-Processor-4M-Cache-up-to-3_60-GHz">5675R</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/87714/Intel-Core-i5-5575R-Processor-4M-Cache-up-to-3_30-GHz">5575R</a> </td></tr></tbody></table> <p><b>Mobile processors (U-Series)</b> </p> <table class="wikitable"> <tbody><tr> <th>Processor branding</th> <th>Model (list)</th> <th>Cores <br /> (Threads)</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <td rowspan="3">Core i7 </td> <td>5xx7U </td> <td rowspan="3">2 (4)</td> <td rowspan="3">4 MB</td> <td>Iris 6100</td> <td rowspan="9">BGA 1168</td> <td>28 W </td> <td rowspan="9">14 nm</td> <td rowspan="9"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td> <td rowspan="9">January 2015 </td></tr> <tr> <td>5x50U</td> <td>HD 6000</td> <td rowspan="2">15 W </td></tr> <tr> <td>5x00U</td> <td>HD 5500 </td></tr> <tr> <td rowspan="3">Core i5 </td> <td>5xx7U</td> <td rowspan="6">2 (2)</td> <td rowspan="6">3 MB</td> <td>Iris 6100</td> <td>28 W </td></tr> <tr> <td>5x50U</td> <td>HD 6000</td> <td rowspan="2">15 W </td></tr> <tr> <td>5x00U</td> <td>HD 5500 </td></tr> <tr> <td rowspan="3">Core i3 </td> <td>5xx7U</td> <td>Iris 6100</td> <td>28 W </td></tr> <tr> <td>5xx5U </td> <td rowspan="2">HD 5500 </td> <td rowspan="2">15 W </td></tr> <tr> <td>5xx0U </td></tr></tbody></table> <p><b>Mobile Processors (Y-Series)</b> </p> <table class="wikitable"> <tbody><tr> <th>Processor branding </th> <th>Model (list) </th> <th>Cores <br /> (Threads) </th> <th>L3 cache </th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a> </th> <th>Socket </th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th>Process </th> <th>I/O Bus </th> <th>Release<br />Date </th></tr> <tr> <td>Core M </td> <td>5Yxx </td> <td>2 (2) </td> <td>4 MB </td> <td>HD 5300 </td> <td>BGA 1234 </td> <td>4.5 W </td> <td>14 nm </td> <td><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>,<br />Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </td> <td>September 2014 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="6th_generation">6th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=17" title="Edit section: 6th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Broadwell_microarchitecture">Broadwell microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=18" title="Edit section: Broadwell microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <tbody><tr> <th>Processor branding</th> <th>Model (list)</th> <th>Cores (Threads)</th> <th>L3 cache</th> <th><a href="/wiki/Intel_HD_Graphics" class="mw-redirect" title="Intel HD Graphics">GPU Model</a></th> <th>Socket</th> <th><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a></th> <th>Process</th> <th>I/O Bus</th> <th>Release<br />Date </th></tr> <tr> <td rowspan="4">Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/94189/Intel-Core-i7-6800K-Processor-15M-Cache-up-to-3_60-GHz">6800K</a> </td> <td rowspan="2">6 (12) </td> <td rowspan="2">15 MB </td> <td rowspan="4">N/A </td> <td rowspan="4">LGA 2011-3 </td> <td rowspan="4">140 W </td> <td rowspan="4">14 nm </td> <td rowspan="4"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> </td> <td rowspan="4">Q2'16 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/94188/Intel-Core-i7-6850K-Processor-15M-Cache-up-to-3_80-GHz">6850K</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/94196/Intel-Core-i7-6900K-Processor-20M-Cache-up-to-3_70-GHz">6900K</a> </td> <td>8 (16) </td> <td>20 MB </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/94456/Intel-Core-i7-6950X-Processor-Extreme-Edition-25M-Cache-up-to-3_50-GHz">6950X</a> </td> <td>10 (20) </td> <td>25 MB </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Skylake_microarchitecture">Skylake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=19" title="Edit section: Skylake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake (microarchitecture)</a></div> <p>Skylake is the sixth generation Core processor microarchitecture, and was launched in August 2015. Being the successor to the Broadwell line, it is a redesign using the same 14 nm manufacturing process technology; however the redesign has better CPU and GPU performance and reduced power consumption. Intel also disabled overclocking non -K processors. </p> <table class="wikitable"> <caption>Desktop processors (DT-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>L3 cache </th> <th>GPU Model </th> <th>Socket </th> <th>TDP </th> <th>Process </th> <th>I/O Bus </th> <th>Release Date </th></tr> <tr> <td rowspan="4">Core i7 </td> <td>6700K </td> <td rowspan="4">4/8 </td> <td rowspan="4">8 MB </td> <td rowspan="3">HD 530 </td> <td rowspan="17">LGA 1151 </td> <td>91 W </td> <td rowspan="17">14 nm </td> <td rowspan="17"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>, <p>Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </p> </td> <td>August 2015 </td></tr> <tr> <td>6700 </td> <td>65 W </td> <td rowspan="2">September 2015 </td></tr> <tr> <td>6700T </td> <td>35 W </td></tr> <tr> <td>6785R </td> <td>Iris Pro 580 </td> <td>65 W </td> <td>May 2016 </td></tr> <tr> <td rowspan="7">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/88191/Intel-Core-i5-6600K-Processor-6M-Cache-up-to-3_90-GHz">6600K</a> </td> <td rowspan="7">4/4 </td> <td rowspan="7">6 MB </td> <td rowspan="4">HD 530 </td> <td>91 W </td> <td rowspan="4">September 2015 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/88188/Intel-Core-i5-6600-Processor-6M-Cache-up-to-3_90-GHz">6600</a> </td> <td rowspan="4">65 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/88184/Intel-Core-i5-6500-Processor-6M-Cache-up-to-3_60-GHz">6500</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/88185/Intel-Core-i5-6400-Processor-6M-Cache-up-to-3_30-GHz">6400</a> </td></tr> <tr> <td>6402P </td> <td>HD 510 </td> <td>December 2015 </td></tr> <tr> <td>6xx0R </td> <td rowspan="2">HD 530 </td> <td rowspan="2">35 W </td> <td>June 2016 </td></tr> <tr> <td>6xx0T </td> <td rowspan="6">September 2015 </td></tr> <tr> <td rowspan="6">Core i3 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/90733/Intel-Core-i3-6320-Processor-4M-Cache-3_90-GHz">6320</a> </td> <td rowspan="6">2/4 </td> <td rowspan="3">4 MB </td> <td rowspan="3">HD 530 </td> <td rowspan="2">51 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/90731/Intel-Core-i3-6300-Processor-4M-Cache-3_80-GHz">6300</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/90728/Intel-Core-i3-6300T-Processor-4M-Cache-3_30-GHz">6300T</a> </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/90729/Intel-Core-i3-6100-Processor-3M-Cache-3_70-GHz">6100</a> </td> <td rowspan="3">3 MB </td> <td rowspan="2">HD 530 </td> <td>51 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/90734/Intel-Core-i3-6100T-Processor-3M-Cache-3_20-GHz">6100T</a> </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/93366/Intel-Core-i3-6098P-Processor-3M-Cache-3_60-GHz">6098P</a> </td> <td>HD 510 </td> <td>54 W </td> <td>December 2015 </td></tr></tbody></table> <table class="wikitable"> <caption>Mobile processors (H-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>L3 cache </th> <th>GPU Model </th> <th>Socket </th> <th>TDP </th> <th>Process </th> <th>I/O Bus </th> <th>Release Date </th></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/89063/Intel-Core-i3-6100H-Processor-3M-Cache-2_70-GHz">6100H</a> </td> <td>2/4 </td> <td>3 MB </td> <td>HD 530 </td> <td>FBGA 1356 </td> <td>35 W </td> <td>14 nm </td> <td><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>, <p>Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </p> </td> <td>September 2015 </td></tr> </tbody></table> <table class="wikitable"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>L3 cache </th> <th>GPU Model </th> <th>Socket </th> <th>TDP </th> <th>Process </th> <th>I/O Bus </th> <th>Release Date </th></tr> <tr> <td rowspan="5">Core i7 </td> <td>6650U </td> <td rowspan="13">2/4 </td> <td rowspan="9">4 MB </td> <td>Iris 540 </td> <td rowspan="13">FCBGA 1356 </td> <td>15 W </td> <td rowspan="13">14 nm </td> <td rowspan="13"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a>, <p>Integrated <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </p> </td> <td rowspan="12">September 2015 </td></tr> <tr> <td>6600U </td> <td>HD 520 </td> <td>25 W </td></tr> <tr> <td>6567U </td> <td>Iris 550 </td> <td>28 W </td></tr> <tr> <td>6x60U </td> <td>Iris 540 </td> <td rowspan="2">15 W </td></tr> <tr> <td>6x00U </td> <td>HD 520 </td></tr> <tr> <td rowspan="5">Core i5 </td> <td>62x7U </td> <td>Iris 550 </td> <td>28 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91156/intel-core-i5-6360u-processor-4m-cache-up-to-3-10-ghz.html">6360U</a> </td> <td>Iris 540 </td> <td>9.5 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88190/intel-core-i5-6300u-processor-3m-cache-up-to-3-00-ghz.html">6300U</a> </td> <td>HD 520 </td> <td rowspan="3">15 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91160/intel-core-i5-6260u-processor-4m-cache-up-to-2-90-ghz.html">6260U</a> </td> <td>Iris 540 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/88193/intel-core-i5-6200u-processor-3m-cache-up-to-2-80-ghz.html">6200U</a> </td> <td rowspan="4">3 MB </td> <td>HD 520 </td></tr> <tr> <td rowspan="3">Core i3 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/91154/Intel-Core-i3-6167U-Processor-3M-Cache-2_70-GHz">6167U</a> </td> <td>HD 550 </td> <td>28 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/88180/Intel-Core-i3-6100U-Processor-3M-Cache-2_30-GHz">6100U</a> </td> <td>HD 520 </td> <td rowspan="2">15 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/91157/intel-core-i3-6006u-processor-3m-cache-2-00-ghz.html">6006U</a> </td> <td>HD 520 </td> <td>November 2016 </td></tr> </tbody></table> <div class="mw-heading mw-heading4"><h4 id="7th_generation">7th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=20" title="Edit section: 7th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Skylake_microarchitecture_2">Skylake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=21" title="Edit section: Skylake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable"> <caption>High-end Desktop processors (X-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>L3 cache </th> <th>Socket </th> <th>TDP </th> <th>Process </th> <th>I/O Bus </th> <th>Price </th></tr> <tr> <td rowspan="5">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/126699/intel-core-i97980xe-extreme-edition-processor-24-75m-cache-up-to-4-20-ghz/specifications.html">7980XE</a> </td> <td>18/36 </td> <td>24.75 MB </td> <td rowspan="7">LGA 2066 </td> <td rowspan="3">165 W </td> <td rowspan="7">14 nm </td> <td rowspan="7"><a href="/wiki/Direct_Media_Interface" title="Direct Media Interface">Direct Media Interface</a> </td> <td>$1999 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/126697/intel-core-i97960x-xseries-processor-22m-cache-up-to-4-20-ghz/specifications.html">7960X</a> </td> <td>16/32 </td> <td>22 MB </td> <td>$1699 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/126695/intel-core-i97940x-xseries-processor-19-25m-cache-up-to-4-30-ghz/specifications.html">7940X</a> </td> <td>14/28 </td> <td>19.25 MB </td> <td>$1399 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/126240/intel-core-i97920x-xseries-processor-16-5m-cache-up-to-4-30-ghz/specifications.html">7920X</a> </td> <td>12/24 </td> <td>16.5 MB </td> <td rowspan="4">140 W </td> <td>$1199 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/123613/intel-core-i97900x-xseries-processor-13-75m-cache-up-to-4-30-ghz/specifications.html">7900X</a> </td> <td>10/20 </td> <td>13.75 MB </td> <td>$999 </td></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/123767/intel-core-i77820x-xseries-processor-11m-cache-up-to-4-30-ghz/specifications.html">7820X</a> </td> <td>8/16 </td> <td>11 MB </td> <td>$599 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/products/sku/123589/intel-core-i77800x-xseries-processor-8-25m-cache-up-to-4-00-ghz/specifications.html">7800X</a> </td> <td>6/12 </td> <td>8.25 MB </td> <td>$389 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Kaby_Lake">Kaby Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=22" title="Edit section: Kaby Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">January 2017</span>)</i></span></div></td></tr></tbody></table> <p>Kaby Lake is the codename for the seventh generation Core processor, and was launched in October 2016 (mobile chips)<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> and January 2017 (desktop chips).<sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> With the latest generation of microarchitecture, Intel decided to produce Kaby Lake processors without using their "<a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">tick–tock</a>" manufacturing and design model.<sup id="cite_ref-ArsKabyDetails_70-0" class="reference"><a href="#cite_note-ArsKabyDetails-70"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> Kaby Lake features the same Skylake microarchitecture and is fabricated using Intel's <a href="/wiki/14_nanometer" class="mw-redirect" title="14 nanometer">14 nanometer</a> manufacturing process technology.<sup id="cite_ref-ArsKabyDetails_70-1" class="reference"><a href="#cite_note-ArsKabyDetails-70"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> </p><p>Built on an improved 14 nm process (14FF+), Kaby Lake features faster CPU clock speeds and <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> frequencies. Beyond these process and clock speed changes, little of the CPU architecture has changed from <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>, resulting in identical <a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">IPC</a>. </p><p>Kaby Lake features a new graphics architecture to improve performance in <a href="/wiki/3D_computer_graphics" title="3D computer graphics">3D graphics</a> and <a href="/wiki/4K_resolution" title="4K resolution">4K video</a> playback. It adds native <a href="/wiki/High-bandwidth_Digital_Content_Protection" title="High-bandwidth Digital Content Protection">High-bandwidth Digital Content Protection</a> 2.2 support, along with fixed function decode of <a href="/wiki/H.264/MPEG-4_AVC" class="mw-redirect" title="H.264/MPEG-4 AVC">H.264/MPEG-4 AVC</a>, <a href="/wiki/High_Efficiency_Video_Coding" title="High Efficiency Video Coding">High Efficiency Video Coding</a> Main and Main10/10-bit, and <a href="/wiki/VP9" title="VP9">VP9</a> 10-bit and 8-bit video. Hardware encode is supported for H.264/MPEG-4 AVC, <a href="/wiki/High_Efficiency_Video_Coding" title="High Efficiency Video Coding">HEVC</a> Main10/10-bit, and VP9 8-bit video. VP9 10-bit encode is not supported in hardware. <a href="/wiki/OpenCL" title="OpenCL">OpenCL 2.1</a> is now supported. </p><p>Kaby Lake is the first Core architecture to support <a href="/wiki/Hyper-threading" title="Hyper-threading">hyper-threading</a> for the Pentium-branded desktop CPU SKU. Kaby Lake also features the first overclocking-enabled i3-branded CPU. </p><p>Features common to desktop Kaby Lake CPUs: </p> <ul><li><a href="/wiki/LGA_1151" title="LGA 1151">LGA 1151</a> socket</li> <li><a href="/wiki/DMI_3.0" class="mw-redirect" title="DMI 3.0">DMI 3.0</a> and <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a> interfaces</li> <li>Dual channel memory support in the following configurations: DDR3L-1600 1.35 V (32 GiB maximum) or DDR4-2400 1.2 V (64 GiB maximum)</li> <li>A total of 16 PCIe lanes</li> <li>The Core-branded processors support the AVX2 instruction set. The Celeron and Pentium-branded ones support only SSE4.1/4.2</li> <li>350 MHz base graphics clock rate</li> <li>No L4 cache (eDRAM).</li> <li>A release date of January 3, 2017</li></ul> <table class="wikitable sortable"> <caption>Desktop processors (S-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores (threads) </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th colspan="3">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2"><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU model</a> </th> <th rowspan="2">Maximum <p>GPU clock rate </p> </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Price (USD) </th></tr> <tr> <th>Single core </th> <th>Dual core </th> <th>Quad core </th></tr> <tr> <td rowspan="3">Core i7 </td> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97129/">7700K</a></b> </td> <td rowspan="3">4 (8) </td> <td>4.2 GHz </td> <td>4.5 GHz </td> <td>4.4 GHz </td> <td>4.4 GHz </td> <td rowspan="18">HD 630 </td> <td rowspan="5">1150 MHz </td> <td rowspan="3">8 MB </td> <td>91 W </td> <td>$350 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97128">7700</a> </td> <td>3.6 GHz </td> <td>4.2 GHz </td> <td>4.1 GHz </td> <td>4.0 GHz </td> <td>65 W </td> <td rowspan="2">$312 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97122">7700T</a> </td> <td>2.9 GHz </td> <td>3.8 GHz </td> <td>3.7 GHz </td> <td>3.6 GHz </td> <td>35 W </td></tr> <tr> <td rowspan="7">Core i5 </td> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97144/">7600K</a></b> </td> <td rowspan="7">4 (4) </td> <td>3.8 GHz </td> <td>4.2 GHz </td> <td>4.1 GHz </td> <td>4.0 GHz </td> <td rowspan="7">6 MB </td> <td>91 W </td> <td>$243 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97150">7600</a> </td> <td>3.5 GHz </td> <td>4.1 GHz </td> <td>4.0 GHz </td> <td>3.9 GHz </td> <td>65 W </td> <td rowspan="2">$224 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97183">7600T</a> </td> <td>2.8 GHz </td> <td>3.7 GHz </td> <td>3.6 GHz </td> <td>3.5 GHz </td> <td rowspan="3">1100 MHz </td> <td>35 W </td></tr> <tr> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97123">7500</a></b> </td> <td>3.4 GHz </td> <td>3.8 GHz </td> <td>3.7 GHz </td> <td>3.6 GHz </td> <td>65 W </td> <td rowspan="2">$202 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97121">7500T</a> </td> <td>2.7 GHz </td> <td>3.3 GHz </td> <td>3.2 GHz </td> <td>3.1 GHz </td> <td>35 W </td></tr> <tr> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97147">7400</a></b> </td> <td>3.0 GHz </td> <td>3.5 GHz </td> <td>3.4 GHz </td> <td>3.3 GHz </td> <td rowspan="2">1000 MHz </td> <td>65 W </td> <td>$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97184">7400T</a> </td> <td>2.4 GHz </td> <td>3.0 GHz </td> <td>2.9 GHz </td> <td>2.7 GHz </td> <td>35 W </td> <td>$187 </td></tr> <tr> <td rowspan="8">Core i3 </td> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97527">7350K</a></b> </td> <td rowspan="8">2 (4) </td> <td>4.2 GHz </td> <td colspan="3" rowspan="8">N/A </td> <td rowspan="3">1150 MHz </td> <td rowspan="4">4 MB </td> <td>60 W </td> <td>$179 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97484">7320</a> </td> <td>4.1 GHz </td> <td rowspan="2">51 W </td> <td>$157 </td></tr> <tr> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97458">7300</a></b> </td> <td>4.0 GHz </td> <td rowspan="2">$147 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97457/Intel-Core-i3-7300T-Processor-4M-Cache-3_50-GHz">7300T</a> </td> <td>3.5 GHz </td> <td rowspan="5">1100 MHz </td> <td>35 W </td></tr> <tr> <td><b><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97455">7100</a></b> </td> <td>3.9 GHz </td> <td rowspan="4">3 MB </td> <td>51 W </td> <td rowspan="4">$117 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97485/Intel-Core-i3-7100T-Processor-3M-Cache-3_40-GHz">7100T</a> </td> <td>3.4 GHz </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97130/Intel-Core-i3-7101E-Processor-3M-Cache-3_90-GHz">7101E</a> </td> <td>3.9 GHz </td> <td>54 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97125/Intel-Core-i3-7101TE-Processor-3M-Cache-3_40-GHz">7101TE</a> </td> <td>3.4 GHz </td> <td>35 W </td></tr></tbody></table> <table class="wikitable sortable"> <caption>Mobile Processors (H-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores (threads) </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th colspan="3">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">Max. PCIe lanes </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price (USD) </th></tr> <tr> <th>Single core </th> <th>Dual core </th> <th>Quad core </th> <th>Base </th> <th>Max. </th> <th>Up </th> <th>Down </th></tr> <tr> <td rowspan="4">Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97462/">7920HQ</a> </td> <td rowspan="4">4 (8) </td> <td>3.1 GHz </td> <td>4.1 GHz </td> <td>3.9 GHz </td> <td>3.7 GHz </td> <td rowspan="7">HD 630 </td> <td rowspan="7">350 MHz </td> <td rowspan="4">1100 MHz </td> <td rowspan="3">8 MB </td> <td rowspan="7">16 </td> <td rowspan="6">45 W </td> <td rowspan="7">N/A </td> <td rowspan="6">35 W </td> <td rowspan="7">Q1 2017 </td> <td>$568 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97496/">7820HQ</a> </td> <td rowspan="2">2.9 GHz </td> <td rowspan="2">3.9 GHz </td> <td rowspan="2">3.7 GHz </td> <td rowspan="2">3.5 GHz </td> <td rowspan="3">$378 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97464/">7820HK</a> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97185/">7700HQ</a> </td> <td rowspan="2">2.8 GHz </td> <td rowspan="2">3.8 GHz </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">3.4 GHz </td> <td rowspan="3">6 MB </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97459/">7440HQ</a> </td> <td rowspan="2">4 (4) </td> <td rowspan="2">1000 MHz </td> <td rowspan="2">$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97456/">7300HQ</a> </td> <td>2.5 GHz </td> <td>3.5 GHz </td> <td>3.3 GHz </td> <td>3.1 GHz </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97126/Intel-Core-i3-7100H-Processor-3M-Cache-3_00-GHz">7100H</a> </td> <td>2 (4) </td> <td>3.0 GHz </td> <td colspan="3">N/A </td> <td>950 MHz </td> <td>3 MB </td> <td>35 W </td> <td>N/A </td> <td>$225 </td></tr></tbody></table> <table class="wikitable sortable"> <caption>Mobile Processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th colspan="2">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">L4 <p>cache </p> </th> <th rowspan="2">Max. PCIe lanes </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price (USD) </th></tr> <tr> <th>Single core </th> <th>Dual core </th> <th>Base </th> <th>Max. </th> <th>Up </th> <th>Down </th></tr> <tr> <td rowspan="5">Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97537/">7660U</a> </td> <td rowspan="13">2 (4) </td> <td>2.5 GHz </td> <td>4.0 GHz </td> <td rowspan="13">? </td> <td>Iris Plus 640 </td> <td rowspan="13">300 MHz </td> <td>1100 MHz </td> <td rowspan="5">4 MB </td> <td>64 MB </td> <td rowspan="5">12 </td> <td rowspan="2">15 W </td> <td>N/A </td> <td>9.5 W </td> <td rowspan="4">Q1 2017 </td> <td>? </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97466/">7600U</a> </td> <td>2.8 GHz </td> <td>3.9 GHz </td> <td>HD 620 </td> <td rowspan="2">1150 MHz </td> <td>N/A </td> <td>25 W </td> <td>7.5 W </td> <td>$393 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97541/">7567U</a> </td> <td>3.5 GHz </td> <td>4.0 GHz </td> <td>Iris Plus 650 </td> <td rowspan="2">64 MB </td> <td>28 W </td> <td rowspan="2">N/A </td> <td>23 W </td> <td rowspan="2">? </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97540/">7560U</a> </td> <td>2.4 GHz </td> <td>3.8 GHz </td> <td>Iris Plus 640 </td> <td rowspan="2">1050 MHz </td> <td rowspan="2">15 W </td> <td>9.5 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95451/Intel-Core-i7-7500U-Processor-4M-Cache-up-to-3_50-GHz-">7500U</a> </td> <td>2.7 GHz </td> <td>3.5 GHz </td> <td>HD 620 </td> <td>N/A </td> <td>25 W </td> <td>7.5 W </td> <td>Q3 2016 </td> <td>$393 </td></tr> <tr> <td rowspan="6">Core i5 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97535/">7360U</a> </td> <td>2.3 GHz </td> <td>3.6 GHz </td> <td>Iris Plus 640 </td> <td>1000 MHz </td> <td>4 MB </td> <td>64 MB </td> <td>12 </td> <td>15 W </td> <td>N/A </td> <td>9.5 W </td> <td rowspan="5">Q1 2017 </td> <td>? </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97472">7300U</a> </td> <td>2.6 GHz </td> <td>3.5 GHz </td> <td>HD 620 </td> <td rowspan="2">1100 MHz </td> <td>3 MB </td> <td>N/A </td> <td rowspan="5">12 </td> <td>15 W </td> <td>25 W </td> <td>7.5 W </td> <td>$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97531/">7287U</a> </td> <td>3.3 GHz </td> <td>3.7 GHz </td> <td rowspan="2">Iris Plus 650 </td> <td rowspan="3">4 MB </td> <td rowspan="3">64 MB </td> <td rowspan="2">28 W </td> <td rowspan="3">N/A </td> <td rowspan="2">23 W </td> <td rowspan="3">? </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97528/">7267U</a> </td> <td>3.1 GHz </td> <td>3.5 GHz </td> <td>1050 MHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97539/">7260U</a> </td> <td>2.2 GHz </td> <td>3.4 GHz </td> <td>Iris Plus 640 </td> <td>950 MHz </td> <td rowspan="2">15 W </td> <td>9.5 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95443/Intel-Core-i5-7200U-Processor-3M-Cache-up-to-3_10-GHz">7200U</a> </td> <td>2.5 GHz </td> <td>3.1 GHz </td> <td>HD 620 </td> <td>1000 MHz </td> <td>3 MB </td> <td>N/A </td> <td>25 W </td> <td>7.5 W </td> <td>Q3 2016 </td> <td>$281 </td></tr> <tr> <td rowspan="2">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97666/Intel-Core-i3-7167U-Processor-3M-Cache-2_80-GHz">7167U</a> </td> <td>2.8 GHz </td> <td rowspan="2">N/A </td> <td>Iris Plus 650 </td> <td rowspan="2">1000 MHz </td> <td rowspan="2">3 MB </td> <td>64 MB </td> <td rowspan="2">12 </td> <td>28 W </td> <td rowspan="2">N/A </td> <td>23 W </td> <td>Q1 2017 </td> <td>? </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95442/Intel-Core-i3-7100U-Processor-3M-Cache-2_40-GHz-">7100U</a> </td> <td>2.4 GHz </td> <td>HD 620 </td> <td>N/A </td> <td>15 W </td> <td>7.5 W </td> <td>Q3 2016 </td> <td>$281 </td></tr> </tbody></table> <table class="wikitable sortable"> <caption>Mobile Processors (Y-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th colspan="2">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">Max. PCIe lanes </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price (USD) </th></tr> <tr> <th>Single core </th> <th>Dual core </th> <th>Base </th> <th>Max. </th> <th>Up </th> <th>Down </th></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95441/Intel-Core-m7-7Y75-Processor-4M-Cache-up-to-3_60-GHz">7Y75</a> </td> <td rowspan="5">2 (4) </td> <td>1.3 GHz </td> <td>3.6 GHz </td> <td>3.4 GHz </td> <td rowspan="5">HD 615 </td> <td rowspan="5">300 MHz </td> <td>1050 MHz </td> <td rowspan="5">4 MB </td> <td rowspan="5">10 </td> <td rowspan="5">4.5 W </td> <td rowspan="5">7 W </td> <td rowspan="5">3.5 W </td> <td>Q3 2016 </td> <td>$393 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/97461">7Y57</a> </td> <td rowspan="2">1.2 GHz </td> <td>3.3 GHz </td> <td>2.9 GHz </td> <td rowspan="2">950 MHz </td> <td>Q1 2017 </td> <td rowspan="4">$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95452/Intel-Core-m5-7Y54-Processor-4M-Cache-up-to-3_20-GHz">7Y54</a> </td> <td>3.2 GHz </td> <td>2.8 GHz </td> <td rowspan="2">Q3 2016 </td></tr> <tr> <td rowspan="2">Core i3 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/95449/Intel-Core-m3-7Y30-Processor-4M-Cache-2_60-GHz-">7Y30</a> </td> <td>1.0 GHz </td> <td>2.6 GHz </td> <td rowspan="2">? </td> <td rowspan="2">900 MHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/97538/Intel-Core-m3-7Y32-Processor-4M-Cache-up-to-3_00-GHz">7Y32</a> </td> <td>1.1 GHz </td> <td>3.0 GHz </td> <td>Q2 2017 </td></tr></tbody></table><p>Kaby Lake-X processors are modified versions of Kaby Lake-S processors that fit into the LGA 2066 socket. However, they can't take advantage of the unique features of the platform. </p><table class="wikitable sortable"> <caption>High-end Desktop processors (X-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores (threads) </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th colspan="3">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Price (USD) </th></tr> <tr> <th>Single core </th> <th>Dual core </th> <th>Quad core </th></tr> <tr> <td>Core i7 </td> <td>7740X </td> <td>4 (8) </td> <td>4.3 GHz </td> <td>4.5 GHz </td> <td>4.4 GHz </td> <td>4.4 GHz </td> <td>8 MB </td> <td rowspan="2">112 W </td> <td>$339 </td></tr> <tr> <td>Core i5 </td> <td>7640X </td> <td>4 (4) </td> <td>4.0 GHz </td> <td>4.2 GHz </td> <td>4.1 GHz </td> <td>4.0 GHz </td> <td>6 MB </td> <td>$242 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="8th_generation">8th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=23" title="Edit section: 8th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Kaby_Lake_Refresh">Kaby Lake Refresh</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=24" title="Edit section: Kaby Lake Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th rowspan="2">Cores<br />(threads) </th> <th rowspan="2">CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock<br />rate</a> </th> <th colspan="3">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3<br />cache </th> <th rowspan="2">L4<br />cache </th> <th rowspan="2">Max.<br />PCIe<br />lanes </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Release<br />date </th> <th rowspan="2">Price<br />(USD) </th></tr> <tr> <th>Single<br />core </th> <th>Dual<br />core </th> <th>Quad<br />core </th> <th>Base </th> <th>Max. </th> <th>Up </th> <th>Down </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/124968/Intel-Core-i7-8650U-Processor-8M-Cache-up-to-4_20-GHz">8650U</a> </td> <td rowspan="4">4 (8) </td> <td>1.9 GHz </td> <td colspan="2">4.2 GHz </td> <td>3.9 GHz </td> <td rowspan="4">UHD 620 </td> <td rowspan="4">300 MHz </td> <td rowspan="2">1150 MHz </td> <td rowspan="2">8 MB </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">12 </td> <td rowspan="4">15 W </td> <td rowspan="4">25 W </td> <td rowspan="4">10 W </td> <td rowspan="4">Q3 2017 </td> <td rowspan="2">$409 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/122589/Intel-Core-i7-8550U-Processor-8M-Cache-up-to-4_00-GHz">8550U</a> </td> <td>1.8 GHz </td> <td colspan="2">4.0 GHz </td> <td>3.7 GHz </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/124969/Intel-Core-i5-8350U-Processor-6M-Cache-up-to-3_60-GHz">8350U</a> </td> <td>1.7 GHz </td> <td colspan="3">3.6 GHz </td> <td rowspan="2">1100 MHz </td> <td rowspan="2">6 MB </td> <td rowspan="2">$297 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://ark.intel.com/products/124967/Intel-Core-i5-8250U-Processor-6M-Cache-up-to-3_40-GHz">8250U</a> </td> <td>1.6 GHz </td> <td colspan="3">3.4 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Coffee_Lake_microarchitecture">Coffee Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=25" title="Edit section: Coffee Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a></div> <p><b>Coffee Lake</b> is a codename for the eighth generation Intel Core family and was launched in October 2017. For the first time in the ten-year history of Intel Core processors, the Coffee Lake generation features an increase in core counts across the desktop lineup of processors, a significant driver of improved performance versus previous generations despite similar per-clock performance. </p> <table class="wikitable"> <caption>Increase in number of CPU cores in desktop Coffee Lake processors </caption> <tbody><tr> <th> </th> <th>Kaby Lake<br />(7th Generation) </th> <th>Coffee Lake<br />(8th Generation) </th></tr> <tr> <th> </th> <th>Cores / Threads </th> <th>Cores / Threads </th></tr> <tr> <th>Core i3 </th> <td>2 / 4<span style="visibility:hidden;color:transparent;">0</span> </td> <td>4 / 4<span style="visibility:hidden;color:transparent;">0</span> </td></tr> <tr> <th>Core i5 </th> <td>4 / 4<span style="visibility:hidden;color:transparent;">0</span> </td> <td>6 / 6<span style="visibility:hidden;color:transparent;">0</span> </td></tr> <tr> <th>Core i7 </th> <td>4 / 8<span style="visibility:hidden;color:transparent;">0</span> </td> <td>6 / 12 </td></tr></tbody></table> <p><i><small>* Intel <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> capabilities allow an enabled processor to execute two threads per physical core</small></i> </p><p>Coffee Lake features largely the same CPU core and performance per MHz as Skylake/Kaby Lake.<sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> Features specific to Coffee Lake include: </p> <ul><li>Following similar refinements to the 14 nm process in Skylake and Kaby Lake, Coffee Lake is the third 14 nm process refinement ("14nm++") and features increased transistor gate pitch for a lower current density and higher leakage transistors which allows higher peak power and higher frequency at the expense of die area and idle power.</li> <li>Coffee Lake will be used in conjunction with the 300-series chipset and is incompatible with the older 100- and 200-series chipsets.<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-74" class="reference"><a href="#cite_note-74"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup></li> <li>Increased L3 cache in accordance to the number of cores</li> <li>Increased turbo clock speeds across i5 and i7 CPUs models (increased by up to 200 MHz)</li> <li>Increased iGPU clock speeds by 50 MHz</li> <li>DDR4 memory support updated for 2666 MHz (for i5 and i7 parts) and 2400 MHz (for i3 parts); DDR3 memory is no longer supported</li></ul> <table class="wikitable" style="text-align: center;"> <caption>Desktop processors (S-Series) </caption> <tbody><tr> <th rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </p> </th> <th rowspan="3">Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="6"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate<sup id="cite_ref-anand12945_75-0" class="reference"><a href="#cite_note-anand12945-75"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> [GHz] </th> <th rowspan="3"><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th rowspan="3">max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th rowspan="3">L3<br />cache </th> <th rowspan="3">TDP </th> <th rowspan="3">Memory<br />support </th> <th rowspan="3">Price<br />(USD) </th></tr> <tr> <th colspan="6">Number of cores used </th></tr> <tr> <th>1 </th> <th>2 </th> <th>3 </th> <th>4 </th> <th>5 </th> <th>6 </th></tr> <tr> <td rowspan="4">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/148263">8086K</a> </td> <td rowspan="4">6 (12) </td> <td>4.0 GHz </td> <td>5.0 </td> <td rowspan="2">4.6 </td> <td rowspan="2">4.5 </td> <td colspan="2" rowspan="2">4.4 </td> <td rowspan="2">4.3 </td> <td rowspan="16"><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td rowspan="4">1.20 GHz </td> <td rowspan="4">12 MB </td> <td rowspan="2">95 W </td> <td rowspan="11">DDR4 <p>2666 </p> </td> <td>$425 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126684">8700K</a> </td> <td>3.7 GHz </td> <td>4.7 </td> <td>$359 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126686">8700</a> </td> <td>3.2 GHz </td> <td>4.6 </td> <td>4.5 </td> <td>4.4 </td> <td colspan="3">4.3 </td> <td>65 W </td> <td rowspan="2">$303 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129948">8700T</a> </td> <td>2.4 GHz </td> <td colspan="1">4.0 </td> <td>4.0 </td> <td colspan="2">3.9 </td> <td colspan="2">3.8 </td> <td>35 W </td></tr> <tr> <td rowspan="7">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126685">8600K</a> </td> <td rowspan="7">6 (6) </td> <td>3.6 GHz </td> <td rowspan="2">4.3 </td> <td colspan="3" rowspan="2">4.2 </td> <td colspan="2" rowspan="2">4.1 </td> <td rowspan="3">1.15 GHz </td> <td rowspan="7">9 MB </td> <td>95 W </td> <td>$257 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129937">8600</a> </td> <td>3.1 GHz </td> <td>65 W </td> <td rowspan="2">$213 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129938">8600T</a> </td> <td>2.3 GHz </td> <td>3.7 </td> <td colspan="3">3.6 </td> <td colspan="2">3.5 </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129939">8500</a> </td> <td>3.0 GHz </td> <td>4.1 </td> <td colspan="3">4.0 </td> <td colspan="2">3.9 </td> <td rowspan="2">1.10 GHz </td> <td>65 W </td> <td rowspan="2">$192 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129941">8500T</a> </td> <td>2.1 GHz </td> <td>3.5 </td> <td>3.4 </td> <td colspan="2">3.3 </td> <td colspan="2">3.2 </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126687">8400</a> </td> <td>2.8 GHz </td> <td>4.0 </td> <td colspan="3">3.9 </td> <td colspan="2">3.8 </td> <td rowspan="2">1.05 GHz </td> <td>65 W </td> <td rowspan="2">$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129940">8400T</a> </td> <td>1.7 GHz </td> <td>3.3 </td> <td>3.2 </td> <td colspan="2">3.1 </td> <td colspan="2">3.0 </td> <td>35 W </td></tr> <tr> <td rowspan="5">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126689">8350K</a> </td> <td rowspan="5">4 (4) </td> <td>4.0 GHz </td> <td colspan="6" rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">1.15 GHz </td> <td rowspan="3">8 MB </td> <td>91 W </td> <td rowspan="5">DDR4 <p>2400 </p> </td> <td>$168 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129942">8300</a> </td> <td>3.7 GHz </td> <td>62 W </td> <td rowspan="2">$138 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129943">8300T</a> </td> <td>3.2 GHz </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/126688">8100</a> </td> <td>3.6 GHz </td> <td rowspan="2">1.10 GHz </td> <td rowspan="2">6 MB </td> <td>65 W </td> <td rowspan="2">$117 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/129944">8100T</a> </td> <td>3.1 GHz </td> <td>35 W </td></tr></tbody></table> <p>* Processors Core i3-8100 and Core i3-8350K with stepping B0 actually belong to "<a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake-S</a>" family </p> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (H-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th rowspan="2">Max. <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> <p>clock rate </p> </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price <p>(USD) </p> </th></tr> <tr> <th>Base </th> <th>Max. </th> <th>Down </th> <th>Up </th></tr> <tr> <td rowspan="3">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134899/Intel-Core-i7-8850H-Processor-9M-Cache-up-to-4_30-GHz">8850H</a> </td> <td rowspan="3">6 (12) </td> <td>2.6 GHz </td> <td>4.3 GHz </td> <td rowspan="8">UHD 630 </td> <td rowspan="8">350 MHz </td> <td>1.15 GHz </td> <td rowspan="2">9 MB </td> <td rowspan="2">45 W </td> <td rowspan="8">35 W </td> <td rowspan="8">N/A </td> <td rowspan="2">$395 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134906/Intel-Core-i7-8750H-Processor-9M-Cache-up-to-4_10-GHz">8750H</a> </td> <td>2.2 GHz </td> <td>4.1 GHz </td> <td>1.10 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134905/Intel-Core-i7-8700B-Processor-12M-Cache-up-to-4_60-GHz">8700B</a> </td> <td>3.2 GHz </td> <td>4.6 GHz </td> <td>1.20 GHz </td> <td>12 MB </td> <td rowspan="3">65 W </td> <td>$303 </td></tr> <tr> <td rowspan="4">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134892/Intel-Core-i5-8500B-Processor-9M-Cache-up-to-4_10-GHz">8500B</a> </td> <td rowspan="2">6 (6) </td> <td>3.0 GHz </td> <td>4.1 GHz </td> <td>1.10 GHz </td> <td rowspan="2">9 MB </td> <td>$192 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134888/Intel-Core-i5-8400B-Processor-9M-Cache-up-to-4_00-GHz">8400B</a> </td> <td>2.8 GHz </td> <td>4.0 GHz </td> <td>1.05 GHz </td> <td>$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134877/Intel-Core-i5-8400H-Processor-8M-Cache-up-to-4_20-GHz">8400H</a> </td> <td rowspan="2">4 (8) </td> <td>2.5 GHz </td> <td>4.2 GHz </td> <td>1.10 GHz </td> <td rowspan="2">8 MB </td> <td rowspan="3">45 W </td> <td>$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134876/Intel-Core-i5-8300H-Processor-8M-Cache-up-to-4_00-GHz">8300H</a> </td> <td>2.3 GHz </td> <td>4.0 GHz </td> <td rowspan="2">1.00 GHz </td> <td>$250 </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/149160/Intel-Core-i3-8100H-Processor-6M-Cache-3_00-GHz">8100H</a> </td> <td>4 (4) </td> <td>3.0 GHz </td> <td>N/A </td> <td>6 MB </td> <td>$225 </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock</a> <a href="/wiki/Clock_rate" title="Clock rate">rate</a> </p> </th> <th rowspan="2">Max. <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> <p>clock rate </p> </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">L4 cache <p>(eDRAM) </p> </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price <p>(USD) </p> </th></tr> <tr> <th>Base </th> <th>Max. </th> <th>Down </th> <th>Up </th></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/137979/Intel-Core-i7-8559U-Processor-8M-Cache-up-to-4_50-GHz">8559U</a> </td> <td rowspan="3">4 (8) </td> <td>2.7 GHz </td> <td>4.5 GHz </td> <td rowspan="3">Iris Plus 655 </td> <td rowspan="4">300 MHz </td> <td>1.20 GHz </td> <td>8 MB </td> <td rowspan="2">128 MB </td> <td rowspan="4">28 W </td> <td rowspan="4">20 W </td> <td rowspan="4">N/A </td> <td>$431 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/137980/Intel-Core-i5-8269U-Processor-6M-Cache-up-to-4_20-GHz">8269U</a> </td> <td>2.6 GHz </td> <td>4.2 GHz </td> <td>1.10 GHz </td> <td rowspan="2">6 MB </td> <td>$320 </td></tr> <tr> <td> <p><a rel="nofollow" class="external text" href="https://ark.intel.com/products/135935/Intel-Core-i5-8259U-Processor-6M-Cache-up-to-3_80-GHz">8259U</a> </p> </td> <td>2.3 GHz </td> <td>3.8 GHz </td> <td>1.05 GHz </td> <td rowspan="2">N/A </td> <td> </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/135936/Intel-Core-i3-8109U-Processor-4M-Cache-up-to-3_60-GHz">8109U</a> </td> <td>2 (4) </td> <td>3.0 GHz </td> <td>3.6 GHz </td> <td>UHD 630 </td> <td>1.10 GHz </td> <td>4 MB </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Amber_Lake_microarchitecture">Amber Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=26" title="Edit section: Amber Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Amber Lake is a refinement over the low power Mobile Kaby Lake CPUs. </p> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile Processors (Y-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="2">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th rowspan="2">GPU </th> <th rowspan="2">Max GPU <p>clock rate </p> </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price </th></tr> <tr> <th>Base </th> <th>Max <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">turbo</a> </th> <th>Up </th> <th>Down </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194698/intel-core-i7-8510y-processor-4m-cache-up-to-4-30-ghz.html">8510Y</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200728232331/https://ark.intel.com/content/www/us/en/ark/products/194698/intel-core-i7-8510y-processor-4m-cache-up-to-4-30-ghz.html">Archived</a> July 28, 2020, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </td> <td rowspan="6">2 (4) </td> <td>1.8 GHz </td> <td>3.9 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD 617</a> </td> <td rowspan="4">1050 MHz </td> <td rowspan="6">4 MB </td> <td>7 W </td> <td colspan="2">N/A </td> <td>$393 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/185281/Intel-Core-i7-8500Y-Processor-4M-Cache-up-to-4_20-GHz">8500Y</a> </td> <td>1.5 GHz </td> <td>4.2 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD 615</a> </td> <td>5 W </td> <td>7 W </td> <td>3.5 W </td> <td>$393 </td></tr> <tr> <td rowspan="3">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/194697/intel-core-i5-8310y-processor-4m-cache-up-to-3-90-ghz.html">8310Y</a> </td> <td rowspan="2">1.6 GHz </td> <td>3.9 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD 617</a> </td> <td rowspan="2">7 W </td> <td colspan="2" rowspan="2">N/A </td> <td rowspan="2">$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/189912/Intel-Core-i5-8210Y-Processor-4M-Cache-up-to-3-60-GHz">8210Y</a> </td> <td>3.6 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/185280/Intel-Core-i5-8200Y-Processor-4M-Cache-up-to-3_90-GHz">8200Y</a> </td> <td>1.3 GHz </td> <td>3.9 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD 615</a> </td> <td>950 MHz </td> <td rowspan="2">5 W </td> <td>7 W </td> <td>3.5 W </td> <td>$291 </td></tr> <tr> <td>Core m3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/185282/Intel-Core-m3-8100Y-Processor-4M-Cache-up-to-3_40-GHz">8100Y</a> </td> <td>1.1 GHz </td> <td>3.4 GHz </td> <td>900 MHz </td> <td>8 W </td> <td>4.5 W </td> <td>$281 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Whiskey_Lake_microarchitecture">Whiskey Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=27" title="Edit section: Whiskey Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Whiskey_Lake" title="Whiskey Lake">Whiskey Lake</a></div> <p><b>Whiskey Lake</b> is <a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Intel's codename</a> for the third 14 nm <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> process-refinement, following <a href="/wiki/Kaby_Lake_Refresh" class="mw-redirect" title="Kaby Lake Refresh">Kaby Lake Refresh</a> and <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a>. Intel announced low power mobile Whiskey Lake CPUs availability on August 28, 2018.<sup id="cite_ref-76" class="reference"><a href="#cite_note-76"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AnandWhiskey_77-0" class="reference"><a href="#cite_note-AnandWhiskey-77"><span class="cite-bracket">[</span>74<span class="cite-bracket">]</span></a></sup> It has not yet been advertised whether this CPU architecture contains hardware mitigations for <a href="/wiki/Meltdown_(security_vulnerability)" title="Meltdown (security vulnerability)">Meltdown</a>/<a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a> class vulnerabilities—various sources contain conflicting information.<sup id="cite_ref-78" class="reference"><a href="#cite_note-78"><span class="cite-bracket">[</span>75<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-79" class="reference"><a href="#cite_note-79"><span class="cite-bracket">[</span>76<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AnandWhiskey_77-1" class="reference"><a href="#cite_note-AnandWhiskey-77"><span class="cite-bracket">[</span>74<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-80" class="reference"><a href="#cite_note-80"><span class="cite-bracket">[</span>77<span class="cite-bracket">]</span></a></sup> Unofficially it was announced that Whiskey Lake has hardware mitigations against Meltdown and L1TF while Spectre V2 requires software mitigations as well as microcode/firmware update.<sup id="cite_ref-81" class="reference"><a href="#cite_note-81"><span class="cite-bracket">[</span>78<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-82" class="reference"><a href="#cite_note-82"><span class="cite-bracket">[</span>79<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-83" class="reference"><a href="#cite_note-83"><span class="cite-bracket">[</span>80<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-84" class="reference"><a href="#cite_note-84"><span class="cite-bracket">[</span>81<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </p> </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock GHz <p>Num of cores </p> </th> <th rowspan="2">GPU </th> <th rowspan="2">Max GPU <p>clock rate </p> </th> <th rowspan="2">L3 <p>cache </p> </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Memory </th> <th rowspan="2">Price </th></tr> <tr> <th>1 </th> <th>2 </th> <th>4 </th> <th>Up </th> <th>Down </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193563/intel-core-i7-8665u-processor-8m-cache-up-to-4-80-ghz.html">8665U</a> </td> <td rowspan="4">4 (8) </td> <td>1.9 GHz </td> <td>4.8 </td> <td> </td> <td> </td> <td rowspan="5"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD<br />620</a> </td> <td rowspan="2">1150 MHz </td> <td rowspan="2">8 MB </td> <td rowspan="5">25 W </td> <td rowspan="5">10 W </td> <td rowspan="5">DDR4-2400 <p>LPDDR3-2133 </p> </td> <td>$409 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/149091/Intel-Core-i7-8565U-Processor-8M-Cache-up-to-4_60-GHz">8565U</a> </td> <td>1.8 GHz </td> <td>4.6 </td> <td>4.5 </td> <td>4.1 </td> <td>$409 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/193555/intel-core-i5-8365u-processor-6m-cache-up-to-4-10-ghz.html">8365U</a> </td> <td rowspan="2">1.6 GHz </td> <td>4.1 </td> <td> </td> <td> </td> <td rowspan="2">1100 MHz </td> <td rowspan="2">6 MB </td> <td>$297 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/149088/Intel-Core-i5-8265U-Processor-6M-Cache-up-to-3_90-GHz">8265U</a> </td> <td>3.9 </td> <td>3.9 </td> <td>3.7 </td> <td>$297 </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/149090/Intel-Core-i3-8145U-Processor-4M-Cache-up-to-3_90-GHz">8145U</a> </td> <td>2 (4) </td> <td>2.1 GHz </td> <td>3.9 </td> <td>3.7 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1000 MHz </td> <td>4 MB </td> <td>$281 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Cannon_Lake_microarchitecture">Cannon Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=28" title="Edit section: Cannon Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake (microprocessor)</a></div> <p><b>Cannon Lake</b> (formerly <b>Skymont</b>) is <a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Intel's codename</a> for the <a href="/wiki/10_nanometer" class="mw-redirect" title="10 nanometer">10-nanometer</a> <a href="/wiki/Die_shrink" title="Die shrink">die shrink</a> of the <a href="/wiki/Kaby_Lake" title="Kaby Lake">Kaby Lake</a> <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a>. As a die shrink, Cannon Lake is a new process in Intel's "<a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">process–architecture–optimization</a>" execution plan as the next step in semiconductor fabrication.<sup id="cite_ref-wccftech_85-0" class="reference"><a href="#cite_note-wccftech-85"><span class="cite-bracket">[</span>82<span class="cite-bracket">]</span></a></sup> Cannon Lake are the first mainstream CPUs to include the <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a> instruction set. In comparison to the previous generation <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX2</a> (AVX-256), the new generation AVX-512 most notably provides double the width of data registers and double the number of registers. These enhancements would allow for twice the number of floating point operations per register due to the increased width in addition to doubling the overall <i>number</i> of registers, resulting in theoretical performance improvements of up to four times the performance of AVX2.<sup id="cite_ref-86" class="reference"><a href="#cite_note-86"><span class="cite-bracket">[</span>83<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-87" class="reference"><a href="#cite_note-87"><span class="cite-bracket">[</span>84<span class="cite-bracket">]</span></a></sup> </p><p>At <a href="/wiki/Consumer_Electronics_Show#2018" title="Consumer Electronics Show">CES 2018</a>, Intel announced that they had started shipping mobile Cannon Lake CPUs at the end of 2017 and that they would ramp up production in 2018.<sup id="cite_ref-88" class="reference"><a href="#cite_note-88"><span class="cite-bracket">[</span>85<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-89" class="reference"><a href="#cite_note-89"><span class="cite-bracket">[</span>86<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-90" class="reference"><a href="#cite_note-90"><span class="cite-bracket">[</span>87<span class="cite-bracket">]</span></a></sup> No further details were disclosed. </p> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th rowspan="2">CPU <p><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </p> </th> <th rowspan="2">CPU <a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> <p>clock rate </p> </th> <th rowspan="2">GPU </th> <th colspan="2">GPU clock rate </th> <th rowspan="2">L3 <p>cache </p> </th> <th rowspan="2">TDP </th> <th><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price <p>(USD) </p> </th></tr> <tr> <th>Base </th> <th>Max. </th> <th>Down </th></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz">8121U</a><sup id="cite_ref-91" class="reference"><a href="#cite_note-91"><span class="cite-bracket">[</span>88<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-92" class="reference"><a href="#cite_note-92"><span class="cite-bracket">[</span>89<span class="cite-bracket">]</span></a></sup> </td> <td>2 (4) </td> <td>2.2 GHz </td> <td>3.2 GHz </td> <td colspan="3">N/A </td> <td>4 MB </td> <td>15 W </td> <td>N/A </td> <td>? </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="9th_generation">9th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=29" title="Edit section: 9th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Skylake_microarchitecture_3">Skylake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=30" title="Edit section: Skylake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The 9th generation Coffee Lake CPUs are updated versions of previous Skylake X-Series CPUs with clockspeed improvements. </p> <table class="wikitable"> <caption>High-end Desktop processors (X-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>Base Clock </th> <th>Single Core Turbo Clock </th> <th>L3 cache </th> <th>TDP </th> <th>Price </th></tr> <tr> <td rowspan="6">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189126/intel-core-i9-9980xe-extreme-edition-processor-24-75m-cache-up-to-4-50-ghz.html">9980XE</a> </td> <td>18/36 </td> <td>3.0 GHz </td> <td rowspan="5">4.5 GHz </td> <td>24.75 MB </td> <td rowspan="7">165 W </td> <td>$1979 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189123/intel-core-i9-9960x-x-series-processor-22m-cache-up-to-4-50-ghz.html">9960X</a> </td> <td>16/32 </td> <td>3.1 GHz </td> <td>22 MB </td> <td>$1684 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189125/intel-core-i9-9940x-x-series-processor-19-25m-cache-up-to-4-50-ghz.html">9940X</a> </td> <td>14/28 </td> <td>3.3 GHz </td> <td rowspan="3">19.25 MB </td> <td>$1387 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189127/intel-core-i9-9920x-x-series-processor-19-25m-cache-up-to-4-50-ghz.html">9920X</a> </td> <td>12/24 </td> <td rowspan="2">3.5 GHz </td> <td>$1189 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189124/intel-core-i9-9900x-x-series-processor-19-25m-cache-up-to-4-50-ghz.html">9900X</a> </td> <td rowspan="2">10/20 </td> <td>$989 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189121/intel-core-i9-9820x-x-series-processor-16-5m-cache-up-to-4-20-ghz.html">9820X</a> </td> <td>3.3 GHz </td> <td>4.2 GHz </td> <td rowspan="2">16.5 MB </td> <td>$889 </td></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/189122/intel-core-i7-9800x-x-series-processor-16-5m-cache-up-to-4-50-ghz.html">9800X</a> </td> <td>8/16 </td> <td>3.8 GHz </td> <td>4.5 GHz </td> <td>$589 </td></tr> </tbody></table> <div class="mw-heading mw-heading5"><h5 id="Coffee_Lake_Refresh_microarchitecture">Coffee Lake Refresh microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=31" title="Edit section: Coffee Lake Refresh microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The 9th generation <a href="/wiki/Coffee_Lake" title="Coffee Lake">Coffee Lake</a> CPUs were released in the fourth quarter of 2018. They include <a href="/wiki/Transient_execution_CPU_vulnerability#Vulnerabilities_and_mitigations_summary" title="Transient execution CPU vulnerability">hardware mitigations</a> against certain <a href="/wiki/Meltdown_(security_vulnerability)" title="Meltdown (security vulnerability)">Meltdown</a>/<a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a> vulnerabilities.<sup id="cite_ref-93" class="reference"><a href="#cite_note-93"><span class="cite-bracket">[</span>90<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-94" class="reference"><a href="#cite_note-94"><span class="cite-bracket">[</span>91<span class="cite-bracket">]</span></a></sup> </p><p>For the first time in Intel consumer CPU history, these CPUs support up to 128 GB RAM.<sup id="cite_ref-95" class="reference"><a href="#cite_note-95"><span class="cite-bracket">[</span>92<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <caption>Increase in number of CPU cores in desktop 9th Generation processors </caption> <tbody><tr> <th> </th> <th>8th Generation </th> <th>9th Generation </th></tr> <tr> <th> </th> <th>Cores / Threads </th> <th>Cores / Threads </th></tr> <tr> <th>Core i3 </th> <td>4 / 4<span style="visibility:hidden;color:transparent;">0</span> </td> <td>4 / 4<span style="visibility:hidden;color:transparent;">0</span> </td></tr> <tr> <th>Core i5 </th> <td>6 / 6<span style="visibility:hidden;color:transparent;">0</span> </td> <td>6 / 6<span style="visibility:hidden;color:transparent;">0</span> </td></tr> <tr> <th>Core i7 </th> <td>6 / 12 </td> <td>8 / 8 </td></tr> <tr> <th>Core i9 </th> <td>6 / 12 </td> <td>8 / 16 </td></tr></tbody></table> <p><i><small>* Intel <a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a> capabilities allow an enabled processor to execute two threads per physical core</small></i> </p><p>Even though the F suffix CPUs lack an integrated GPU, Intel set the same price for these CPUs as their featureful counterparts.<sup id="cite_ref-96" class="reference"><a href="#cite_note-96"><span class="cite-bracket">[</span>93<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center;"> <caption>Desktop processors (S-Series) </caption> <tbody><tr> <th rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th rowspan="3">Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="8"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock rate<sup id="cite_ref-9gAT_97-0" class="reference"><a href="#cite_note-9gAT-97"><span class="cite-bracket">[</span>94<span class="cite-bracket">]</span></a></sup> [GHz] </th> <th rowspan="3"><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th rowspan="3">max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th rowspan="3">L3<br />cache </th> <th rowspan="3">TDP </th> <th rowspan="3">Memory <p>support </p> </th> <th rowspan="3">Price<br />(USD) </th></tr> <tr> <th colspan="8">Number of cores used </th></tr> <tr> <th>1 </th> <th>2 </th> <th>3 </th> <th>4 </th> <th>5 </th> <th>6 </th> <th>7 </th> <th>8 </th></tr> <tr> <td rowspan="3">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192943/intel-core-i9-9900ks-processor-16m-cache-up-to-5-00-ghz.html">9900KS</a> </td> <td rowspan="3">8 (16) </td> <td>4.0 GHz </td> <td colspan="8">5.0 </td> <td rowspan="2"><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td rowspan="2">1.20 GHz </td> <td rowspan="3">16 MB </td> <td>127 W * </td> <td rowspan="9">DDR4-2666 </td> <td>$524 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/186605/">9900K</a> </td> <td rowspan="2">3.6 GHz </td> <td colspan="2" rowspan="2">5.0 </td> <td colspan="2" rowspan="2">4.8 </td> <td colspan="4" rowspan="2">4.7 </td> <td rowspan="2">95 W * </td> <td rowspan="2">$488 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/190887/Intel-Core-i9-9900KF-Processor-16M-Cache-up-to-5-00-GHz-">9900KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/186604/">9700K</a> </td> <td rowspan="2">8 (8) </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">4.9 </td> <td rowspan="2">4.8 </td> <td colspan="2" rowspan="2">4.7 </td> <td colspan="4" rowspan="2">4.6 </td> <td><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td>1.20 GHz </td> <td rowspan="2">12 MB </td> <td rowspan="4">95 W </td> <td rowspan="2">$374 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/190885/Intel-Core-i7-9700KF-Processor-12M-Cache-up-to-4-90-GHz-">9700KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="4">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134896/">9600K</a> </td> <td rowspan="4">6 (6) </td> <td rowspan="2">3.7 GHz </td> <td rowspan="2">4.6 </td> <td rowspan="2">4.5 </td> <td colspan="2" rowspan="2">4.4 </td> <td colspan="2" rowspan="2">4.3 </td> <td colspan="2" rowspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td>1.15 GHz </td> <td rowspan="4">9 MB </td> <td rowspan="2">$262 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/190884/Intel-Core-i5-9600KF-Processor-9M-Cache-up-to-4-60-GHz-">9600KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/134898">9400</a> </td> <td rowspan="2">2.9 GHz </td> <td rowspan="2">4.1 </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td>1.05 GHz </td> <td rowspan="2">65 W </td> <td rowspan="2">$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/190883/Intel-Core-i5-9400F-Processor-9M-Cache-up-to-4-10-GHz-">9400F</a> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td rowspan="3">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/products/191126/Intel-Core-i3-9350KF-Processor-8M-Cache-up-to-4-60-GHz-">9350KF</a> </td> <td rowspan="3">4 (4) </td> <td>4.0 GHz </td> <td>4.6 </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>8 MB </td> <td>91 W </td> <td rowspan="3">DDR4-2400 </td> <td>$173 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/190886/intel-core-i3-9100f-processor-6m-cache-up-to-4-20-ghz.html">9100F</a> </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">4.2 </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">6 MB </td> <td rowspan="2">65 W </td> <td rowspan="2">$122 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134870/intel-core-i3-9100-processor-6m-cache-up-to-4-20-ghz.html">9100</a> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td> </td> <td><a href="/wiki/Intel_HD_and_Iris_Graphics#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" class="mw-redirect" title="Intel HD and Iris Graphics">UHD 630</a> </td> <td>1.1 GHz </td></tr></tbody></table> <p>* various reviews show that the Core i9 9900K CPU may consume over 140 W under load. The Core i9 9900KS may consume even more.<sup id="cite_ref-98" class="reference"><a href="#cite_note-98"><span class="cite-bracket">[</span>95<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-99" class="reference"><a href="#cite_note-99"><span class="cite-bracket">[</span>96<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-100" class="reference"><a href="#cite_note-100"><span class="cite-bracket">[</span>97<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-101" class="reference"><a href="#cite_note-101"><span class="cite-bracket">[</span>98<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center;"> <caption>Mobile processors (H-Series) </caption> <tbody><tr> <th>Processor<br />branding </th> <th>Model </th> <th><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th>Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Single Core Turbo</a> clock rate [GHz] </th> <th><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th>Max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th>L3<br />cache </th> <th>TDP </th> <th>Memory<br />support </th> <th>Price<br />(USD) </th></tr> <tr> <td rowspan="2">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192990/intel-core-i9-9980hk-processor-16m-cache-up-to-5-00-ghz.html">9980HK</a> </td> <td rowspan="2">8 (16) </td> <td>2.4 GHz </td> <td>5.0 </td> <td rowspan="6">HD 630 </td> <td>1.25 GHz </td> <td rowspan="2">16 MB </td> <td rowspan="6">45 W </td> <td rowspan="6">DDR4-2666 </td> <td>$583 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/192987/intel-core-i9-9880h-processor-16m-cache-up-to-4-80-ghz.html">9880H</a> </td> <td>2.3 GHz </td> <td>4.8 </td> <td>1.20 GHz </td> <td>$556 </td></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191047/intel-core-i7-9850h-processor-12m-cache-up-to-4-60-ghz.html">9850H</a> </td> <td rowspan="2">6 (12) </td> <td rowspan="2">2.6 GHz </td> <td>4.6 </td> <td rowspan="2">1.15 GHz </td> <td rowspan="2">12 MB </td> <td rowspan="2">$395 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191045/intel-core-i7-9750h-processor-12m-cache-up-to-4-50-ghz.html">9750H</a> </td> <td>4.5 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191078/intel-core-i5-9400h-processor-8m-cache-up-to-4-30-ghz.html">9400H</a> </td> <td rowspan="2">4 (8) </td> <td>2.5 GHz </td> <td>4.3 </td> <td>1.10 GHz </td> <td rowspan="2">8 MB </td> <td rowspan="2">$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/191075/intel-core-i5-9300h-processor-8m-cache-up-to-4-10-ghz.html">9300H</a> </td> <td>2.4 GHz </td> <td>4.1 </td> <td>1.05 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="10th_generation">10th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=32" title="Edit section: 10th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Cascade_Lake_microarchitecture">Cascade Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=33" title="Edit section: Cascade Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Cascade Lake X-Series CPUs are the 10th generation versions of the previous Skylake X-Series CPUs. They offer minor clockspeed improvements and a highly reduced price. </p> <table class="wikitable"> <caption>High-end Desktop processors (X-Series) </caption> <tbody><tr> <th>Processor branding </th> <th>Model </th> <th>Cores/Threads </th> <th>Base Clock </th> <th>Single Core Turbo Clock </th> <th>All Core Turbo Clock </th> <th>L3 cache </th> <th>TDP </th> <th>Price </th></tr> <tr> <td rowspan="4">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/198017/intel-core-i9-10980xe-extreme-edition-processor-24-75m-cache-3-00-ghz.html">10980XE</a> </td> <td>18/36 </td> <td>3.0 GHz </td> <td rowspan="3">4.8 GHz </td> <td>3.8 GHz </td> <td>24.75 MB </td> <td rowspan="4">165 W </td> <td>$979 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/198014/intel-core-i9-10940x-x-series-processor-19-25m-cache-3-30-ghz.html">10940X</a> </td> <td>14/28 </td> <td>3.3 GHz </td> <td>4.1 GHz </td> <td rowspan="3">19.25 MB </td> <td>$784 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/198012/intel-core-i9-10920x-x-series-processor-19-25m-cache-3-50-ghz.html">10920X</a> </td> <td>12/24 </td> <td>3.5 GHz </td> <td rowspan="2">4.3 GHz </td> <td>$689 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/198019/intel-core-i9-10900x-x-series-processor-19-25m-cache-3-70-ghz.html">10900X</a> </td> <td>10/20 </td> <td>3.7 GHz </td> <td>4.7 GHz </td> <td>$590 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Ice_Lake_microarchitecture">Ice Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=34" title="Edit section: Ice Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ice_Lake_(microprocessor)" title="Ice Lake (microprocessor)">Ice Lake (microprocessor)</a></div> <p><b>Ice Lake</b> is codename for Intel's 10th generation Intel Core processors, representing an enhancement of the 'architecture' of the preceding generation Kaby Lake/Cannon Lake processors (as specified in Intel's <a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization" class="mw-redirect" title="Process–architecture–optimization">process–architecture–optimization</a> execution plan). As the successor to Cannon Lake, Ice Lake uses Intel's newer 10 nm+ fabrication process, and is powered by the <a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove microarchitecture</a>. </p><p>Ice Lake are the first Intel CPUs to feature in-silicon mitigations for the hardware vulnerabilities discovered in 2017, <a href="/wiki/Meltdown_(security_vulnerability)" title="Meltdown (security vulnerability)">Meltdown</a> and <a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a>. These <a href="/wiki/Side-channel_attack" title="Side-channel attack">side-channel attacks</a> exploit <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction's</a> use of <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>. These exploits may cause the CPU to reveal cached private information which the exploiting process is not intended to be able to access as a form of <a href="/wiki/Timing_attack" title="Timing attack">timing attack</a>.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (July 2018)">citation needed</span></a></i>]</sup> </p> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th rowspan="2">Cores<br />(threads) </th> <th rowspan="2">Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock GHz <p>Num of cores </p> </th> <th colspan="3">GPU </th> <th rowspan="2">L3<br />cache </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price </th></tr> <tr> <th>1 </th> <th>2 </th> <th>4 </th> <th>Series </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max clock<br />rate </th> <th>Up </th> <th>Down </th></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196597/intel-core-i7-1065g7-processor-8m-cache-up-to-3-90-ghz.html">1065G7</a> </td> <td rowspan="4">4 (8) </td> <td>1.3 GHz </td> <td>3.9 </td> <td> </td> <td>3.5 </td> <td rowspan="3"><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">Iris Plus</a> </td> <td rowspan="2">64 </td> <td>1.1 GHz </td> <td>8 MiB </td> <td>15 W </td> <td>25 W </td> <td>12 W </td> <td>$426 </td></tr> <tr> <td rowspan="3">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196592/intel-core-i5-1035g7-processor-6m-cache-up-to-3-70-ghz.html">1035G7</a> </td> <td>1.2 GHz </td> <td rowspan="2">3.7 </td> <td> </td> <td rowspan="3">3.3 </td> <td rowspan="3">1.05 GHz </td> <td rowspan="3">6 MiB </td> <td rowspan="3">15 W </td> <td rowspan="3">25 W </td> <td rowspan="2">12 W </td> <td>$320 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196591/intel-core-i5-1035g4-processor-6m-cache-up-to-3-70-ghz.html">1035G4</a> </td> <td>1.1 GHz </td> <td> </td> <td>48 </td> <td>$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196603/intel-core-i5-1035g1-processor-6m-cache-up-to-3-60-ghz.html">1035G1</a> </td> <td>1.0 GHz </td> <td>3.6 </td> <td> </td> <td><a href="/wiki/Intel_Graphics_Technology#Ice_Lake" title="Intel Graphics Technology">UHD</a> </td> <td>32 </td> <td>13 W </td> <td>$297 </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196588/intel-core-i3-1005g1-processor-4m-cache-up-to-3-40-ghz.html">1005G1</a> </td> <td>2 (4) </td> <td>1.2 GHz </td> <td colspan="2">3.4 </td> <td> </td> <td>UHD </td> <td>32 </td> <td>0.9 GHz </td> <td>4 MiB </td> <td>15 W </td> <td>25 W </td> <td>13 W </td> <td>$281 </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (Y-Series) </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th rowspan="2">Cores<br />(threads) </th> <th rowspan="2">Base CPU<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> clock GHz <p>Num of cores </p> </th> <th colspan="3">GPU </th> <th rowspan="2">L3<br />cache </th> <th rowspan="2">TDP </th> <th colspan="2"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2">Price </th></tr> <tr> <th>1 </th> <th>2 </th> <th>4 </th> <th>Series </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max clock<br />rate </th> <th>Up </th> <th>Down </th></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197120/intel-core-i7-1060g7-processor-8m-cache-up-to-3-80-ghz.html">1060G7</a> </td> <td rowspan="3">4 (8) </td> <td>1.0 GHz </td> <td>3.8 </td> <td> </td> <td>3.4 </td> <td>Iris Plus </td> <td>64 </td> <td rowspan="3">1.1 GHz </td> <td>8 MiB </td> <td>9 W </td> <td>12 W </td> <td> </td> <td> </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197119/intel-core-i5-1030g7-processor-6m-cache-up-to-3-50-ghz.html">1030G7</a> </td> <td>0.8 GHz </td> <td rowspan="2">3.5 </td> <td> </td> <td rowspan="2">3.2 </td> <td rowspan="2">Iris Plus </td> <td>64 </td> <td rowspan="2">6 MiB </td> <td rowspan="2">9 W </td> <td rowspan="2">12 W </td> <td> </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197121/intel-core-i5-1030g4-processor-6m-cache-up-to-3-50-ghz.html">1030G4</a> </td> <td>0.7 GHz </td> <td> </td> <td>48 </td> <td> </td> <td> </td></tr> <tr> <td rowspan="3">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196586/intel-core-i3-1000ng4-processor-4m-cache-up-to-3-20-ghz.html">1000NG4</a> </td> <td rowspan="3">2 (4) </td> <td rowspan="3">1.1 GHz </td> <td colspan="2" rowspan="3">3.2 </td> <td rowspan="3"> </td> <td rowspan="2">Iris Plus </td> <td rowspan="2">48 </td> <td rowspan="3">0.9 GHz </td> <td rowspan="3">4 MiB </td> <td rowspan="3">9 W </td> <td> </td> <td> </td> <td> </td></tr> <tr> <td> <p><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197123/intel-core-i3-1000g4-processor-4m-cache-up-to-3-20-ghz.html">1000G4</a> </p> </td> <td rowspan="2">12 W </td> <td> </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197122/intel-core-i3-1000g1-processor-4m-cache-up-to-3-20-ghz.html">1000G1</a> </td> <td>UHD </td> <td>32 </td> <td> </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Comet_Lake_microarchitecture">Comet Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=35" title="Edit section: Comet Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Comet_Lake" title="Comet Lake">Comet Lake</a></div> <p><b>Comet Lake</b> is <a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Intel's codename</a> for the fourth 14 nm <a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> process-refinement, following <a href="/wiki/Whiskey_Lake_(microarchitecture)" class="mw-redirect" title="Whiskey Lake (microarchitecture)">Whiskey Lake</a>. Intel announced low power mobile Comet Lake CPUs availability on August 21, 2019.<sup id="cite_ref-102" class="reference"><a href="#cite_note-102"><span class="cite-bracket">[</span>99<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <caption>Increase in number of CPU cores in desktop 10th generation processors </caption> <tbody><tr> <th> </th> <th>9th generation </th> <th>10th generation </th></tr> <tr> <th> </th> <th>Cores / threads </th> <th>Cores / threads </th></tr> <tr> <th>Core i3 </th> <td>4 / 4 </td> <td>4 / 8 </td></tr> <tr> <th>Core i5 </th> <td>6 / 6 </td> <td>6 / 12 </td></tr> <tr> <th>Core i7 </th> <td>8 / 8 </td> <td>8 / 16 </td></tr> <tr> <th>Core i9 </th> <td>8 / 16 </td> <td>10 / 20 </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Desktop processors (S-Series) </caption> <tbody><tr> <th rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th colspan="4">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> (GHz) </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">GPU</a> </th> <th rowspan="3">Smart<br />cache <p>(MB) </p> </th> <th colspan="2" rowspan="2">TDP </th> <th rowspan="3">Memory<br />support </th> <th rowspan="3">Price<br />(USD) </th></tr> <tr> <th rowspan="2">Base </th> <th rowspan="2">All-Core <p>Turbo </p> </th> <th rowspan="2">Turbo <p>Boost 2.0 </p> </th> <th rowspan="2">Turbo Boost <p>Max 3.0 </p> </th> <th rowspan="2">Model </th> <th rowspan="2">max <p>clock </p><p>rate </p><p>(GHz) </p> </th></tr> <tr> <th>Down </th> <th>Base </th></tr> <tr> <td rowspan="7"><a href="/wiki/List_of_Intel_Core_i9_microprocessors" class="mw-redirect" title="List of Intel Core i9 microprocessors">Core i9</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199332/intel-core-i9-10900k-processor-20m-cache-up-to-5-30-ghz.html">10900K</a> </td> <td rowspan="7">10 (20) </td> <td rowspan="2">3.7 </td> <td rowspan="2">4.8 </td> <td rowspan="2">5.1 </td> <td rowspan="2">5.2 </td> <td><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD</a> <p><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">630</a> </p> </td> <td>1.20 </td> <td rowspan="7">20 </td> <td rowspan="3">95 </td> <td rowspan="3">125 </td> <td rowspan="12">DDR4-2933 <p>2-channel </p><p>up to 128 GB </p> </td> <td>$488 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199331/intel-core-i9-10900kf-processor-20m-cache-up-to-5-30-ghz.html">10900KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$472 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/204448/intel-core-i9-10910-processor-20m-cache-up-to-5-00-ghz.html">10910</a> </td> <td>3.6 </td> <td>4.7 </td> <td rowspan="3">5.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">UHD <p>630 </p> </td> <td rowspan="2">1.20 </td> <td>OEM </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199328/intel-core-i9-10900-processor-20m-cache-up-to-5-20-ghz.html">10900</a> </td> <td rowspan="2">2.8 </td> <td rowspan="2">4.5 </td> <td rowspan="2">5.1 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$438 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199329/intel-core-i9-10900f-processor-20m-cache-up-to-5-20-ghz.html">10900F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$422 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199324/intel-core-i9-10900t-processor-20m-cache-up-to-4-60-ghz.html">10900T</a> </td> <td>1.9 </td> <td>3.7 </td> <td>4.5 </td> <td>4.6 </td> <td rowspan="3">UHD <p>630 </p> </td> <td rowspan="3">1.20 </td> <td>25 </td> <td>35 </td> <td>$438 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/205904/intel-core-i9-10850k-processor-20m-cache-up-to-5-20-ghz.html">10850K</a> </td> <td>3.6 </td> <td rowspan="3">4.7 </td> <td rowspan="3">5.0 </td> <td rowspan="3">5.1 </td> <td rowspan="3">95 </td> <td rowspan="3">125 </td> <td>$453 </td></tr> <tr> <td rowspan="5"><a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199335/intel-core-i7-10700k-processor-16m-cache-up-to-5-00-ghz.html">10700K</a> </td> <td rowspan="5">8 (16) </td> <td rowspan="2">3.8 </td> <td rowspan="5">16 </td> <td>$374 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199325/intel-core-i7-10700kf-processor-16m-cache-up-to-5-00-ghz.html">10700KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$349 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199316/intel-core-i7-10700-processor-16m-cache-up-to-4-80-ghz.html">10700</a> </td> <td rowspan="2">2.9 </td> <td rowspan="2">4.6 </td> <td rowspan="2">4.7 </td> <td rowspan="2">4.8 </td> <td>UHD <p>630 </p> </td> <td>1.20 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$323 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199318/intel-core-i7-10700f-processor-16m-cache-up-to-4-80-ghz.html">10700F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$298 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199314/intel-core-i7-10700t-processor-16m-cache-up-to-4-40-ghz.html">10700T</a> </td> <td>2.0 </td> <td>3.7 </td> <td>4.4 </td> <td>4.5 </td> <td rowspan="2">UHD <p>630 </p> </td> <td rowspan="2">1.20 </td> <td>25 </td> <td>35 </td> <td>$325 </td></tr> <tr> <td rowspan="9"><a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199311/intel-core-i5-10600k-processor-12m-cache-up-to-4-80-ghz.html">10600K</a> </td> <td rowspan="9">6 (12) </td> <td rowspan="2">4.1 </td> <td rowspan="2">4.5 </td> <td rowspan="2">4.8 </td> <td rowspan="15" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="9">12 </td> <td rowspan="2">95 </td> <td rowspan="2">125 </td> <td rowspan="15">DDR4-2666 <p>2-channel </p><p>up to 128 GB </p> </td> <td>$262 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199315/intel-core-i5-10600kf-processor-12m-cache-up-to-4-80-ghz.html">10600KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$237 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199273/intel-core-i5-10600-processor-12m-cache-up-to-4-80-ghz.html">10600</a> </td> <td>3.3 </td> <td>4.4 </td> <td>4.8 </td> <td rowspan="5">UHD <p>630 </p> </td> <td rowspan="2">1.20 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>65 </td> <td rowspan="2">$213 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199279/intel-core-i5-10600t-processor-12m-cache-up-to-4-00-ghz.html">10600T</a> </td> <td>2.4 </td> <td>3.7 </td> <td>4.0 </td> <td>25 </td> <td>35 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199277/intel-core-i5-10500-processor-12m-cache-up-to-4-50-ghz.html">10500</a> </td> <td>3.1 </td> <td>4.2 </td> <td>4.5 </td> <td rowspan="2">1.15 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>65 </td> <td rowspan="2">$192 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199275/intel-core-i5-10500t-processor-12m-cache-up-to-3-80-ghz.html">10500T</a> </td> <td>2.3 </td> <td>3.5 </td> <td>3.8 </td> <td>25 </td> <td>35 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199271/intel-core-i5-10400-processor-12m-cache-up-to-4-30-ghz.html">10400</a> </td> <td rowspan="2">2.9 </td> <td rowspan="2">4.0 </td> <td rowspan="2">4.3 </td> <td>1.10 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199278/intel-core-i5-10400f-processor-12m-cache-up-to-4-30-ghz.html">10400F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$157 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199276/intel-core-i5-10400t-processor-12m-cache-up-to-3-60-ghz.html">10400T</a> </td> <td>2.0 </td> <td>3.2 </td> <td>3.6 </td> <td rowspan="5">UHD <p>630 </p> </td> <td>1.10 </td> <td>25 </td> <td>35 </td> <td>$182 </td></tr> <tr> <td rowspan="6"><a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199280/intel-core-i3-10320-processor-8m-cache-up-to-4-60-ghz.html">10320</a> </td> <td rowspan="6">4 (8) </td> <td>3.8 </td> <td>4.4 </td> <td>4.6 </td> <td rowspan="2">1.15 </td> <td rowspan="3">8 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$154 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199281/intel-core-i3-10300-processor-8m-cache-up-to-4-40-ghz.html">10300</a> </td> <td>3.7 </td> <td>4.2 </td> <td>4.4 </td> <td rowspan="2">$143 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199282/intel-core-i3-10300t-processor-8m-cache-up-to-3-90-ghz.html">10300T</a> </td> <td>3.0 </td> <td>3.6 </td> <td>3.9 </td> <td rowspan="2">1.10 </td> <td>25 </td> <td>35 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199283/intel-core-i3-10100-processor-6m-cache-up-to-4-30-ghz.html">10100</a> </td> <td rowspan="2">3.6 </td> <td rowspan="2">4.1 </td> <td rowspan="2">4.3 </td> <td rowspan="3">6 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$122 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203473/intel-core-i3-10100f-processor-6m-cache-up-to-4-30-ghz.html">10100F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$79 - $97 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/199284/intel-core-i3-10100t-processor-6m-cache-up-to-3-80-ghz.html">10100T</a> </td> <td>3.0 </td> <td>3.5 </td> <td>3.8 </td> <td>UHD <p>630 </p> </td> <td>1.10 </td> <td>25 </td> <td>35 </td> <td>p </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (H-Series) </caption> <tbody><tr> <th rowspan="3">Processor <p>branding </p> </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th colspan="2">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock speed</a> (GHz) </th> <th colspan="2"><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th rowspan="3">Smart <p>cache </p><p>(MB) </p> </th> <th colspan="3" rowspan="2">TDP <p>(W) </p> </th> <th rowspan="3"><a href="/wiki/Random-access_memory" title="Random-access memory">Memory</a> <p>support </p> </th> <th rowspan="3">Price <p>(USD) </p> </th></tr> <tr> <th rowspan="2">Base </th> <th rowspan="2">Max. <p><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Max. <p>freq. </p><p>(GHz) </p> </th></tr> <tr> <th>Down </th> <th>Base </th> <th>Up </th></tr> <tr> <td rowspan="2">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201838/intel-core-i9-10980hk-processor-16m-cache-up-to-5-30-ghz.html">10980HK</a> </td> <td rowspan="4">8 (16) </td> <td rowspan="2">2.4 </td> <td rowspan="2">5.3 </td> <td rowspan="9"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 630</a> </td> <td rowspan="2">1.25 </td> <td rowspan="4">16 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="10">45 </td> <td>65 </td> <td rowspan="10">DDR4-2933 <p>2-channel </p><p>up to 128 GB </p> </td> <td>$583 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203682/intel-core-i9-10885h-processor-16m-cache-up-to-5-30-ghz.html">10885H</a> </td> <td rowspan="9">35 </td> <td rowspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$556 </td></tr> <tr> <td rowspan="4">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/202329/intel-core-i7-10875h-processor-16m-cache-up-to-5-10-ghz.html">10875H</a> </td> <td>2.3 </td> <td>5.1 </td> <td rowspan="2">1.20 </td> <td>$450 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208018/intel-core-i7-10870h-processor-16m-cache-up-to-5-00-ghz.html">10870H</a> </td> <td>2.2 </td> <td>5.0 </td> <td>$417 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201897/intel-core-i7-10850h-processor-12m-cache-up-to-5-10-ghz.html">10850H</a> </td> <td rowspan="3">6 (12) </td> <td>2.7 </td> <td>5.1 </td> <td rowspan="2">1.15 </td> <td rowspan="3">12 </td> <td rowspan="2">$395 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201837/intel-core-i7-10750h-processor-12m-cache-up-to-5-00-ghz.html">10750H</a> </td> <td>2.6 </td> <td>5.0 </td></tr> <tr> <td rowspan="4">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201905/intel-core-i5-10500h-processor-12m-cache-up-to-4-50-ghz.html">10500H</a> </td> <td>2.5 </td> <td>4.5 </td> <td>1.05 </td> <td rowspan="4">$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201895/intel-core-i5-10400h-processor-8m-cache-up-to-4-60-ghz.html">10400H</a> </td> <td rowspan="3">4 (8) </td> <td>2.6 </td> <td>4.6 </td> <td>1.10 </td> <td rowspan="3">8 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201839/intel-core-i5-10300h-processor-8m-cache-up-to-4-50-ghz.html">10300H</a> </td> <td>2.5 </td> <td>4.5 </td> <td rowspan="2">1.05 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208016/intel-core-i5-10200h-processor-8m-cache-up-to-4-10-ghz.html">10200H</a> </td> <td>2.4 </td> <td>4.1 </td> <td rowspan="1"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD 610</a> </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Mobile processors (U-Series) </caption> <tbody><tr> <th rowspan="3">Processor <p>branding </p> </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th colspan="2">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock speed</a> (GHz) </th> <th colspan="2"><a href="/wiki/Intel_HD_and_Iris_Graphics" class="mw-redirect" title="Intel HD and Iris Graphics">GPU</a> </th> <th rowspan="3">L3 <p>cache </p><p>(MB) </p> </th> <th colspan="3" rowspan="2">TDP </th> <th rowspan="3"><a href="/wiki/Random-access_memory" title="Random-access memory">Memory</a> <p>support </p> </th> <th rowspan="3">Price <p>(USD) </p> </th></tr> <tr> <th rowspan="2">Base </th> <th rowspan="2">Max. <p><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Max. <p>freq. </p> </th></tr> <tr> <th>Down </th> <th>Base </th> <th>Up </th></tr> <tr> <td rowspan="4">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201888/intel-core-i7-10810u-processor-12m-cache-up-to-4-90-ghz.html">10810U</a> </td> <td rowspan="2">6 (12) </td> <td rowspan="2">1.1 </td> <td>4.9 </td> <td rowspan="7"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD</a> <p><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">620</a> </p> </td> <td rowspan="5">1.15 </td> <td rowspan="2">12 </td> <td rowspan="2">12.5 </td> <td rowspan="7">15 </td> <td rowspan="7">25 </td> <td rowspan="7">DDR4-2666 <p>LPDDR3-2133 </p> </td> <td rowspan="2">$443 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196448/intel-core-i7-10710u-processor-12m-cache-up-to-4-7-ghz.html">10710U</a> </td> <td>4.7 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201896/intel-core-i7-10610u-processor-8m-cache-up-to-4-90-ghz.html">10610U</a> </td> <td rowspan="4">4 (8) </td> <td rowspan="2">1.8 </td> <td rowspan="2">4.9 </td> <td rowspan="2">8 </td> <td rowspan="5">10 </td> <td rowspan="2">$409 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196449/intel-core-i7-10510u-processor-8m-cache-up-to-4-80-ghz.html">10510U</a> </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201892/intel-core-i5-10310u-processor-6m-cache-up-to-4-40-ghz.html">10310U</a> </td> <td>1.7 </td> <td>4.4 </td> <td rowspan="2">6 </td> <td rowspan="2">$297 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/195436/intel-core-i5-10210u-processor-6m-cache-up-to-4-10-ghz.html">10210U</a> </td> <td>1.6 </td> <td>4.2 </td> <td>1.10 </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196451/intel-core-i3-10110u-processor-4m-cache-up-to-4-10-ghz.html">10110U</a> </td> <td>2 (4) </td> <td>2.1 </td> <td>4.1 </td> <td>1.00 </td> <td>4 </td> <td>$281 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Comet_Lake_Refresh_microarchitecture">Comet Lake Refresh microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=36" title="Edit section: Comet Lake Refresh microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th rowspan="3">Processor<br />branding </th> <th rowspan="3">Model </th> <th rowspan="3"><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th colspan="3">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> (GHz) </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">GPU</a> </th> <th rowspan="3">Smart<br />cache <p>(MB) </p> </th> <th colspan="2" rowspan="2">TDP </th> <th rowspan="3">Memory<br />support </th> <th rowspan="3">Price<br />(USD) </th></tr> <tr> <th rowspan="2">Base </th> <th rowspan="2">All-Core <p>Turbo </p> </th> <th rowspan="2">Turbo <p>Boost 2.0 </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Max. <p>freq. </p> </th></tr> <tr> <th>Down </th> <th>Base </th></tr> <tr> <td>Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201891/intel-core-i510505-processor-12m-cache-up-to-4-60-ghz.html">10505</a> </td> <td>6 (12) </td> <td>3.2 </td> <td>4.3 </td> <td>4.6 </td> <td rowspan="5">UHD <p>630 </p> </td> <td>1.2 </td> <td>12 </td> <td>N/A </td> <td>65 </td> <td rowspan="7">DDR4-2666 <p>2-channel </p><p>up to 128 GB </p> </td> <td>$192 </td></tr> <tr> <td rowspan="6"><a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201889/intel-core-i3-10325-processor-8m-cache-up-to-4-70-ghz.html">10325</a> </td> <td rowspan="6">4 (8) </td> <td>3.9 </td> <td>4.5 </td> <td>4.7 </td> <td rowspan="2">1.15 </td> <td rowspan="3">8 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$154 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201893/intel-core-i3-10305-processor-8m-cache-up-to-4-50-ghz.html">10305</a> </td> <td>3.8 </td> <td>4.3 </td> <td>4.5 </td> <td rowspan="2">$143 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201898/intel-core-i3-10305t-processor-8m-cache-up-to-4-00-ghz.html">10305T</a> </td> <td>3.0 </td> <td>3.7 </td> <td>4.0 </td> <td rowspan="2">1.10 </td> <td>25 </td> <td>35 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201894/intel-core-i3-10105-processor-6m-cache-up-to-4-40-ghz.html">10105</a> </td> <td rowspan="2">3.7 </td> <td rowspan="2">4.2 </td> <td rowspan="2">4.4 </td> <td rowspan="3">6 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">65 </td> <td>$122 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/203474/intel-core-i3-10105f-processor-6m-cache-up-to-4-40-ghz.html">10105F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$97 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/201890/intel-core-i3-10105t-processor-6m-cache-up-to-3-90-ghz.html">10105T</a> </td> <td>3.0 </td> <td>3.6 </td> <td>3.9 </td> <td>UHD <p>630 </p> </td> <td>1.10 </td> <td>25 </td> <td>35 </td> <td>$122 </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Amber_Lake_Refresh_microarchitecture">Amber Lake Refresh microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=37" title="Edit section: Amber Lake Refresh microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable mw-collapsible" style="text-align: center;"> <caption>List of Amber Lake Refresh Y-series processors </caption> <tbody><tr> <th rowspan="2" scope="col">Processor branding </th> <th rowspan="2" scope="col">Model </th> <th rowspan="2" scope="col"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Hyper-threading" title="Hyper-threading">threads</a>) </th> <th rowspan="2" scope="col">CPU <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="3" scope="colgroup"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a> clock rate </th> <th rowspan="2" scope="col"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="2" scope="col"><abbr title="Maximum">Max</abbr> GPU clock rate </th> <th rowspan="2" scope="col"><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> </th> <th rowspan="2" scope="col">TDP </th> <th colspan="2" scope="colgroup"><a href="/wiki/CTDP" class="mw-redirect" title="CTDP">cTDP</a> </th> <th rowspan="2" scope="col"><a href="/wiki/Random-access_memory" title="Random-access memory">Memory</a> </th> <th rowspan="2" scope="col">Price </th></tr> <tr> <th scope="col">1 core </th> <th scope="col">2 cores </th> <th scope="col">4 cores </th> <th scope="col">Up </th> <th scope="col">Down </th></tr> <tr> <th scope="row">Core i7 </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/196452/intel-core-i7-10510y-processor-8m-cache-up-to-4-50-ghz.html">10510Y</a> </td> <td rowspan="3">4 (8) </td> <td><span class="nowrap">1.2 GHz</span> </td> <td><span class="nowrap">4.5 GHz</span> </td> <td> </td> <td><span class="nowrap">3.2 GHz</span> </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Kaby_Lake_Refresh_/_Amber_Lake_/_Coffee_Lake_/_Coffee_Lake_Refresh_/_Whiskey_Lake_/_Comet_Lake" title="Intel Graphics Technology">UHD for 10th Gen Processors</a> </td> <td><span class="nowrap">1150 MHz</span> </td> <td><span class="nowrap">8 MB</span> </td> <td rowspan="4"><span class="nowrap">7 W</span> </td> <td rowspan="4"><span class="nowrap">9 W</span> </td> <td><span class="nowrap">4.5 W</span> </td> <td rowspan="4"><a href="/wiki/LPDDR3" class="mw-redirect" title="LPDDR3">LPDDR3-2133</a> </td> <td><span style="white-space: nowrap">US$403</span> </td></tr> <tr> <th rowspan="2" scope="row">Core i5 </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/196453/intel-core-i5-10310y-processor-6m-cache-up-to-4-10-ghz.html">10310Y</a> </td> <td><span class="nowrap">1.1 GHz</span> </td> <td><span class="nowrap">4.1 GHz</span> </td> <td> </td> <td><span class="nowrap">2.8 GHz</span> </td> <td rowspan="2"><span class="nowrap">1050 MHz</span> </td> <td rowspan="2"><span class="nowrap">6 MB</span> </td> <td><span class="nowrap">5.5 W</span> </td> <td rowspan="2"><span style="white-space: nowrap">US$292</span> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/196454/intel-core-i5-10210y-processor-6m-cache-up-to-4-00-ghz.html">10210Y</a> </td> <td rowspan="2"><span class="nowrap">1.0 GHz</span> </td> <td rowspan="2"><span class="nowrap">4.0 GHz</span> </td> <td> </td> <td><span class="nowrap">2.7 GHz</span> </td> <td><span class="nowrap">4.5 W</span> </td></tr> <tr> <th scope="row">Core i3 </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/es/es/ark/products/196455/intel-core-i3-10110y-processor-4m-cache-up-to-4-00ghz.html">10110Y</a> </td> <td>2 (4) </td> <td><span class="nowrap">3.7 GHz</span> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><span class="nowrap">1000 MHz</span> </td> <td><span class="nowrap">4 MB</span> </td> <td><span class="nowrap">5.5 W</span> </td> <td><span style="white-space: nowrap">US$287</span> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="11th_generation">11th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=38" title="Edit section: 11th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Tiger_Lake">Tiger Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=39" title="Edit section: Tiger Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Tiger_Lake" title="Tiger Lake">Tiger Lake</a></div> <p>Launched on September 2, 2020. </p> <ul><li>All models support DDR4-3200 memory</li> <li>All models support 20 reconfigurable PCI Express 4.0 lanes, allowing x16 Gen 4 link for discrete GPU and x4 Gen 4 link for M.2 SSDs</li></ul> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors_(Tiger_Lake-H)"><span id="Mobile_processors_.28Tiger_Lake-H.29"></span>Mobile processors (Tiger Lake-H)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=40" title="Edit section: Mobile processors (Tiger Lake-H)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="3">Base freq at TDP </th> <th colspan="4">Max Turbo freq, active cores </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD Graphics</a> </th> <th rowspan="2">Smart <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Price </th></tr> <tr style="line-height:110%;"> <th>@35 W </th> <th>@45 W </th> <th>@65 W </th> <th>1 or 2 </th> <th>4 </th> <th>6 </th> <th>All </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max freq </th></tr> <tr> <td rowspan="3">Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213800/intel-core-i9-11980hk-processor-24m-cache-up-to-4-90-ghz.html">11980HK</a> </td> <td rowspan="5">8 (16) </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">2.6 GHz </td> <td>3.3 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">4.9 GHz </td> <td rowspan="2">4.7 GHz </td> <td rowspan="2">4.5 GHz </td> <td rowspan="6">32 </td> <td rowspan="7">1.45 GHz </td> <td rowspan="5">24 MB </td> <td>45-65 W </td> <td>$583 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213798/intel-core-i9-11950h-processor-24m-cache-up-to-4-90-ghz.html">11950H</a> vPro </td> <td rowspan="3">2.1 GHz </td> <td rowspan="7">N/A </td> <td rowspan="7">35-45 W </td> <td>$556 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213801/intel-core-i9-11900h-processor-24m-cache-up-to-4-80-ghz.html">11900H</a> </td> <td rowspan="2">2.5 GHz </td> <td>4.9 GHz </td> <td>4.8 GHz </td> <td>4.6 GHz </td> <td>4.4 GHz </td> <td>$546 </td></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213799/intel-core-i7-11850h-processor-24m-cache-up-to-4-80-ghz.html">11850H</a> vPro </td> <td>4.8 GHz </td> <td>4.8 GHz </td> <td>4.6 GHz </td> <td>4.3 GHz </td> <td rowspan="2">$395 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213803/intel-core-i7-11800h-processor-24m-cache-up-to-4-60-ghz.html">11800H</a> </td> <td>1.9 GHz </td> <td>2.3 GHz </td> <td>4.6 GHz </td> <td>4.5 GHz </td> <td>4.4 GHz </td> <td>4.2 GHz </td></tr> <tr> <td rowspan="3">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213804/intel-core-i5-11500h-processor-12m-cache-up-to-4-60-ghz.html">11500H</a> vPro </td> <td rowspan="3">6 (12) </td> <td>2.4 GHz </td> <td>2.9 GHz </td> <td>4.6 GHz </td> <td>4.4 GHz </td> <td colspan="2">4.2 GHz </td> <td rowspan="3">12 MB </td> <td rowspan="3">$250 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213805/intel-core-i5-11400h-processor-12m-cache-up-to-4-50-ghz.html">11400H</a> </td> <td>2.2 GHz </td> <td>2.7 GHz </td> <td>4.5 GHz </td> <td>4.3 GHz </td> <td colspan="2">4.1 GHz </td> <td rowspan="2">16 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/213806/intel-core-i5-11260h-processor-12m-cache-up-to-4-40-ghz.html">11260H</a> </td> <td>2.1 GHz </td> <td>2.6 GHz </td> <td>4.4 GHz </td> <td>4.2 GHz </td> <td colspan="2">4.0 GHz </td> <td>1.40 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors_(Tiger_Lake-H35)"><span id="Mobile_processors_.28Tiger_Lake-H35.29"></span>Mobile processors (Tiger Lake-H35)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=41" title="Edit section: Mobile processors (Tiger Lake-H35)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All models support DDR4-3200 or LPDDR4X-4267 memory</li></ul> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="2">Base freq at TDP </th> <th colspan="3">Max Turbo freq <p>active cores </p> </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Iris Xe Graphics</a> </th> <th rowspan="2">Smart <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Price </th></tr> <tr style="line-height:110%;"> <th>@28 W </th> <th>@35 W </th> <th>1 </th> <th>2 </th> <th>All </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max freq </th></tr> <tr> <td rowspan="3">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217182/intel-core-i711390h-processor-12m-cache-up-to-5-00-ghz-with-ipu.html">11390H</a> </td> <td rowspan="5">4 (8) </td> <td>2.9 GHz </td> <td>3.4 GHz </td> <td colspan="2">5.0 GHz </td> <td>4.6 GHz </td> <td rowspan="4">96 </td> <td>1.40 GHz </td> <td rowspan="3">12 MB </td> <td rowspan="5">28-35 W </td> <td>$426 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/197384/intel-core-i7-11375h-processor-12m-cache-up-to-5-00-ghz-with-ipu.html">11375H</a> </td> <td rowspan="2">3.0 GHz </td> <td rowspan="2">3.3 GHz </td> <td>5.0 GHz </td> <td>4.8 GHz </td> <td rowspan="3">4.3 GHz </td> <td rowspan="3">1.35 GHz </td> <td>$482 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196655/intel-core-i7-11370h-processor-12m-cache-up-to-4-80-ghz-with-ipu.html">11370H</a> </td> <td colspan="2">4.8 GHz </td> <td>$426 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217183/intel-core-i511320h-processor-8m-cache-up-to-4-50-ghz-with-ipu.html">11320H</a> </td> <td>2.5 GHz </td> <td>3.2 GHz </td> <td colspan="2">4.5 GHz </td> <td rowspan="2">8 MB </td> <td rowspan="2">$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/196656/intel-core-i5-11300h-processor-8m-cache-up-to-4-40-ghz-with-ipu.html">11300H</a> </td> <td>2.6 GHz </td> <td>3.1 GHz </td> <td colspan="2">4.4 GHz </td> <td>4.0 GHz </td> <td>80 </td> <td>1.30 GHz </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors_(UP3-class)"><span id="Mobile_processors_.28UP3-class.29"></span>Mobile processors (UP3-class)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=42" title="Edit section: Mobile processors (UP3-class)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="3">Base freq at TDP </th> <th colspan="2">Max Turbo freq </th> <th colspan="3">GPU </th> <th rowspan="2">Smart <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Memory <p>support </p> </th> <th rowspan="2">Price </th></tr> <tr style="line-height:110%;"> <th>@12 W </th> <th>@15 W </th> <th>@28 W </th> <th>1 Core </th> <th>All Cores </th> <th>Series </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max freq </th></tr> <tr> <td rowspan="3">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217181/intel-core-i7-1195g7-processor-12m-cache-up-to-5-00-ghz-with-ipu.html">1195G7</a> </td> <td rowspan="7">4 (8) </td> <td>1.3 GHz </td> <td> </td> <td>2.9 GHz </td> <td>5.0 GHz </td> <td>4.6 GHz </td> <td rowspan="6">Iris Xe </td> <td rowspan="3">96 </td> <td>1.40 GHz </td> <td rowspan="3">12 MB </td> <td rowspan="8">12-28 W </td> <td rowspan="6">DDR4-3200 <p>LPDDR4X-4267 </p> </td> <td rowspan="3">$426 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208664/intel-core-i7-1185g7-processor-12m-cache-up-to-4-80-ghz-with-ipu.html">1185G7</a> vPro </td> <td>1.2 GHz </td> <td>1.8 GHz<sup id="cite_ref-:0_103-0" class="reference"><a href="#cite_note-:0-103"><span class="cite-bracket">[</span>100<span class="cite-bracket">]</span></a></sup> </td> <td>3.0 GHz </td> <td>4.8 GHz </td> <td>4.3 GHz </td> <td>1.35 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208921/intel-core-i7-1165g7-processor-12m-cache-up-to-4-70-ghz-with-ipu.html">1165G7</a> </td> <td>1.2 GHz </td> <td>1.7 GHz </td> <td>2.8 GHz </td> <td>4.7 GHz </td> <td>4.1 GHz </td> <td>1.30 GHz </td></tr> <tr> <td rowspan="3">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/217184/intel-core-i5-1155g7-processor-8m-cache-up-to-4-50-ghz-with-ipu.html">1155G7</a> </td> <td>1.0 GHz </td> <td> </td> <td>2.5 GHz </td> <td>4.5 GHz </td> <td>4.3 GHz </td> <td rowspan="3">80 </td> <td>1.35 GHz </td> <td rowspan="4">8 MB </td> <td rowspan="3">$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208660/intel-core-i5-1145g7-processor-8m-cache-up-to-4-40-ghz-with-ipu.html">1145G7</a> vPro </td> <td>1.1 GHz </td> <td><abbr title="based on the embedded model data (intel does not disclose this spec publicly)">1.5 GHz</abbr> </td> <td>2.6 GHz </td> <td>4.4 GHz </td> <td>3.8 GHz </td> <td rowspan="2">1.30 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208922/intel-core-i5-1135g7-processor-8m-cache-up-to-4-20-ghz-with-ipu.html">1135G7</a> </td> <td rowspan="2"><abbr title="900 MHz">0.9 GHz</abbr> </td> <td>1.4 GHz </td> <td>2.4 GHz </td> <td>4.2 GHz </td> <td>3.8 GHz </td></tr> <tr> <td rowspan="2">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/209735/intel-core-i3-1125g4-processor-8m-cache-up-to-3-70-ghz-with-ipu.html">1125G4</a> </td> <td> </td> <td>2.0 GHz </td> <td>3.7 GHz </td> <td>3.3 GHz </td> <td rowspan="2">UHD </td> <td rowspan="2">48 </td> <td rowspan="2">1.25 GHz </td> <td rowspan="2">DDR4-3200 <p>LPDDR4X-3733 </p> </td> <td rowspan="2">$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208920/intel-core-i3-1115g4-processor-6m-cache-up-to-4-10-ghz-with-ipu.html">1115G4</a> </td> <td>2 (4) </td> <td>1.7 GHz </td> <td><abbr title="based on the embedded model data (intel does not disclose this spec publicly)">2.2 GHz</abbr> </td> <td>3.0 GHz </td> <td colspan="2">4.1 GHz </td> <td>6 MB </td></tr></tbody></table> <table class="wikitable sortable" style="text-align: center;"> <caption>Embedded mobile processors (UP3-class) </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="3">Base freq at TDP </th> <th rowspan="2">Max <p>Turbo freq </p> </th> <th colspan="3">GPU </th> <th rowspan="2">Smart <p>cache </p> </th> <th rowspan="2">TDP </th> <th colspan="2">Memory support </th> <th rowspan="2">Price </th></tr> <tr style="line-height:110%;"> <th>@12 W </th> <th>@15 W </th> <th>@28 W </th> <th>Series </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max freq </th> <th>Type </th> <th>ECC </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208082/intel-core-i7-1185gre-processor-12m-cache-up-to-4-40-ghz.html">1185GRE</a> vPro </td> <td rowspan="4">4 (8) </td> <td rowspan="2">1.2 GHz </td> <td rowspan="2">1.8 GHz </td> <td rowspan="2">2.8 GHz </td> <td rowspan="2">4.4 GHz </td> <td rowspan="4">Iris Xe </td> <td rowspan="2">96 </td> <td rowspan="2">1.35 GHz </td> <td rowspan="2">12 MB </td> <td rowspan="6">15 W </td> <td rowspan="4">DDR4-3200 <p>LPDDR4X-4267 </p> </td> <td>Yes </td> <td>$490 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208076/intel-core-i7-1185g7e-processor-12m-cache-up-to-4-40-ghz.html">1185G7E</a> vPro </td> <td>No </td> <td>$431 </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208078/intel-core-i5-1145gre-processor-8m-cache-up-to-4-10-ghz.html">1145GRE</a> vPro </td> <td rowspan="2">1.1 GHz </td> <td rowspan="2">1.5 GHz </td> <td rowspan="2">2.6 GHz </td> <td rowspan="2">4.1 GHz </td> <td rowspan="2">80 </td> <td rowspan="2">1.30 GHz </td> <td rowspan="2">8 MB </td> <td>Yes </td> <td>$362 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208081/intel-core-i5-1145g7e-processor-8m-cache-up-to-4-10-ghz.html">1145G7E</a> vPro </td> <td>No </td> <td>$312 </td></tr> <tr> <td rowspan="2">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208074/intel-core-i3-1115gre-processor-6m-cache-up-to-3-90-ghz.html">1115GRE</a> </td> <td rowspan="2">2 (4) </td> <td rowspan="2">1.7 GHz </td> <td rowspan="2">2.2 GHz </td> <td rowspan="2">3.0 GHz </td> <td rowspan="2">3.9 GHz </td> <td rowspan="2">UHD </td> <td rowspan="2">48 </td> <td rowspan="2">1.25 GHz </td> <td rowspan="2">6 MB </td> <td rowspan="2">DDR4-3200 <p>LPDDR4X-3733 </p> </td> <td>Yes </td> <td>$338 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208079/intel-core-i3-1115g4e-processor-6m-cache-up-to-3-90-ghz.html">1115G4E</a> </td> <td>No </td> <td>$285 </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors_(UP4-class)"><span id="Mobile_processors_.28UP4-class.29"></span>Mobile processors (UP4-class)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=43" title="Edit section: Mobile processors (UP4-class)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th rowspan="2">Cores <p>(threads) </p> </th> <th colspan="3">Base freq at TDP </th> <th colspan="2">Max Turbo freq </th> <th colspan="3">GPU </th> <th rowspan="2">Smart <p>cache </p> </th> <th rowspan="2">TDP </th> <th rowspan="2">Memory <p>support </p> </th> <th rowspan="2">Price </th></tr> <tr style="line-height:110%;"> <th>@7 W </th> <th>@9 W </th> <th>@15 W </th> <th>1 Core </th> <th>All Cores </th> <th>Series </th> <th><a href="/wiki/Execution_unit" title="Execution unit">EUs</a> </th> <th>Max freq </th></tr> <tr> <td rowspan="2">Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208663/intel-core-i7-1180g7-processor-12m-cache-up-to-4-60-ghz-with-ipu.html">1180G7</a> vPro </td> <td rowspan="5">4 (8) </td> <td rowspan="2"><abbr title="900 MHz">0.9 GHz</abbr> </td> <td> </td> <td>2.2 GHz </td> <td>4.6 GHz </td> <td> </td> <td rowspan="4">Iris Xe </td> <td rowspan="2">96 </td> <td rowspan="6">1.10 GHz </td> <td rowspan="2">12 MB </td> <td rowspan="6">7-15 W </td> <td rowspan="6">LPDDR4X-4267 </td> <td rowspan="2">$426 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208661/intel-core-i7-1160g7-processor-12m-cache-up-to-4-40-ghz-with-ipu.html">1160G7</a> </td> <td>1.2 GHz </td> <td>2.1 GHz </td> <td>4.4 GHz </td> <td>3.6 GHz </td></tr> <tr> <td rowspan="2">Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208659/intel-core-i5-1140g7-processor-8m-cache-up-to-4-20-ghz-with-ipu.html">1140G7</a> vPro </td> <td rowspan="3"><abbr title="800 MHz">0.8 GHz</abbr> </td> <td> </td> <td rowspan="2">1.8 GHz </td> <td>4.2 GHz </td> <td> </td> <td rowspan="2">80 </td> <td rowspan="3">8 MB </td> <td rowspan="2">$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208657/intel-core-i5-1130g7-processor-8m-cache-up-to-4-00-ghz-with-ipu.html">1130G7</a> </td> <td rowspan="2">1.1 GHz </td> <td>4.0 GHz </td> <td>3.4 GHz </td></tr> <tr> <td rowspan="2">Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/209736/intel-core-i3-1120g4-processor-8m-cache-up-to-3-70-ghz-with-ipu.html">1120G4</a> </td> <td>1.5 GHz </td> <td>3.5 GHz </td> <td>3.0 GHz </td> <td rowspan="2">UHD </td> <td rowspan="2">48 </td> <td rowspan="2">$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/208651/intel-core-i3-1110g4-processor-6m-cache-up-to-3-90-ghz-with-ipu.html">1110G4</a> </td> <td>2 (4) </td> <td>1.5 GHz </td> <td>1.8 GHz </td> <td>2.5 GHz </td> <td colspan="2">3.9 GHz </td> <td>6 MB </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Desktop/tablet_processors_(Tiger_Lake-B)"><span id="Desktop.2Ftablet_processors_.28Tiger_Lake-B.29"></span>Desktop/tablet processors (Tiger Lake-B)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=44" title="Edit section: Desktop/tablet processors (Tiger Lake-B)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Socket: FCBGA1787, a <a href="/wiki/Ball_grid_array" title="Ball grid array">BGA</a> socket, thus <a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/compare.html?productIds=215570,128915,128916,215569">these CPUs</a> are meant only for system integrators</li> <li>Intel Xe UHD Graphics</li> <li>Up to 128 GB DDR4-3200 memory</li> <li>Was initially incorrectly listed as having a 5.3 GHz TVB boost frequency.<sup id="cite_ref-104" class="reference"><a href="#cite_note-104"><span class="cite-bracket">[</span>101<span class="cite-bracket">]</span></a></sup></li></ul> <table class="wikitable"> <tbody><tr> <th>Processor <p>branding </p> </th> <th>Model </th> <th>Cores <p>(threads) </p> </th> <th>Base / Boost Clocks (GHz) </th> <th>L3 cache <p>(MB) </p> </th> <th>TDP </th> <th>GPU <p>EU </p> </th> <th>GPU <p>Max freq </p> </th> <th>Price </th></tr> <tr> <td>Core i9 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/215570/intel-core-i9-11900kb-processor-24m-cache-up-to-4-90-ghz.html">11900 KB</a> </td> <td rowspan="2">8 (16) </td> <td>3.3 / 4.9 </td> <td rowspan="2">24 </td> <td rowspan="4">65 W </td> <td rowspan="3">32 </td> <td rowspan="3">1.45 GHz </td> <td>$539 </td></tr> <tr> <td>Core i7 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/128915/intel-core-i7-11700b-processor-24m-cache-up-to-4-80-ghz.html">11700B</a> </td> <td>3.2 / 4.8 </td> <td> </td></tr> <tr> <td>Core i5 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/128916/intel-core-i5-11500b-processor-12m-cache-up-to-4-60-ghz.html">11500B</a> </td> <td>6 (12) </td> <td>3.3 / 4.6 </td> <td rowspan="2">12 </td> <td> </td></tr> <tr> <td>Core i3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/215569/intel-core-i3-11100b-processor-12m-cache-3-60-ghz.html">11100B</a> </td> <td>4 (8) </td> <td>3.6 / 4.4 </td> <td>16 </td> <td>1.4 GHz </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Rocket_Lake_microarchitecture">Rocket Lake microarchitecture</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=45" title="Edit section: Rocket Lake microarchitecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Rocket_Lake" title="Rocket Lake">Rocket Lake</a></div> <p>Rocket Lake is a codename for Intel's desktop x86 chip family based on the new <a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a> microarchitecture, a variant of Sunny Cove (used by Intel's Ice Lake mobile processors) backported to the older 14 nm process.<sup id="cite_ref-auto6_105-0" class="reference"><a href="#cite_note-auto6-105"><span class="cite-bracket">[</span>102<span class="cite-bracket">]</span></a></sup> The chips are marketed as "Intel 11th generation Core". Launched March 30, 2021. </p> <div class="mw-heading mw-heading6"><h6 id="Desktop_processors">Desktop processors</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=46" title="Edit section: Desktop processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All CPUs listed below support DDR4-3200 natively. The Core i9 K/KF processors enable a 1:1 ratio of DRAM to memory controller by default at DDR4-3200, whereas the Core i9 non K/KF and all other CPUs listed below enable a 2:1 ratio of DRAM to memory controller by default at DDR4-3200 and a 1:1 ratio by default at DDR4-2933.<sup id="cite_ref-106" class="reference"><a href="#cite_note-106"><span class="cite-bracket">[</span>103<span class="cite-bracket">]</span></a></sup></li> <li>All CPUs support up to 128 GiB of RAM in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual channel mode</a></li> <li>Core i9 CPUs (except 11900T) support Intel Thermal Velocity Boost technology</li></ul> <table class="wikitable sortable" style="text-align: center;"> <tbody><tr> <th>Processor<br />branding </th> <th>Model </th> <th><a href="/wiki/CPU_core" class="mw-redirect" title="CPU core">Cores</a> <p>(<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </p> </th> <th>Base <p><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </p> </th> <th>All-Core <p>Turbo </p> </th> <th>Turbo <p>Boost 2.0 </p> </th> <th>Turbo Boost <p>Max 3.0 </p> </th> <th><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">GPU</a> </th> <th>max <a href="/wiki/Graphics_processing_unit#Integrated_graphics" title="Graphics processing unit">GPU</a><br />clock rate </th> <th>Smart<br />cache </th> <th>TDP </th> <th>Price<br />(USD) </th></tr> <tr> <th rowspan="5"><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">Core i9</a> </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212325/intel-core-i9-11900k-processor-16m-cache-up-to-5-30-ghz.html">11900K</a> </td> <td rowspan="10">8 (16) </td> <td rowspan="2">3.5 GHz </td> <td rowspan="2">4.8 GHz </td> <td rowspan="2">5.1 GHz </td> <td rowspan="2">5.2 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td>1.3 GHz </td> <td rowspan="10">16 MiB </td> <td rowspan="2">125 W </td> <td>$539 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212321/intel-core-i9-11900kf-processor-16m-cache-up-to-5-30-ghz.html">11900KF</a> </td> <td colspan="2">- </td> <td>$513 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212252/intel-core-i9-11900-processor-16m-cache-up-to-5-20-ghz.html">11900</a> </td> <td rowspan="2">2.5 GHz </td> <td rowspan="2">4.7 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">5.1 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td>1.3 GHz </td> <td rowspan="2">65 W </td> <td>$439 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212254/intel-core-i9-11900f-processor-16m-cache-up-to-5-20-ghz.html">11900F</a> </td> <td colspan="2">- </td> <td>$422 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212256/intel-core-i9-11900t-processor-16m-cache-up-to-4-90-ghz.html">11900T</a> </td> <td>1.5 GHz </td> <td>3.7 GHz </td> <td>4.8 GHz </td> <td>4.9 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td rowspan="2">1.3 GHz </td> <td>35 W </td> <td>$439 </td></tr> <tr> <th rowspan="5"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212047/intel-core-i7-11700k-processor-16m-cache-up-to-5-00-ghz.html">11700K</a> </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">4.6 GHz </td> <td rowspan="2">4.9 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">125W </td> <td>$399 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212048/intel-core-i7-11700kf-processor-16m-cache-up-to-5-00-ghz.html">11700KF</a> </td> <td colspan="2">- </td> <td>$374 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212279/intel-core-i7-11700-processor-16m-cache-up-to-4-90-ghz.html">11700</a> </td> <td rowspan="2">2.5 GHz </td> <td rowspan="2">4.4 GHz </td> <td rowspan="2">4.8 GHz </td> <td rowspan="2">4.9 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td>1.3 GHz </td> <td rowspan="2">65W </td> <td>$323 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212280/intel-core-i7-11700f-processor-16m-cache-up-to-4-90-ghz.html">11700F</a> </td> <td colspan="2">- </td> <td>$298 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212251/intel-core-i7-11700t-processor-16m-cache-up-to-4-60-ghz.html">11700T</a> </td> <td>1.4 GHz </td> <td>3.6 GHz </td> <td>4.5 GHz </td> <td>4.6 GHz </td> <td rowspan="2"><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td rowspan="2">1.3 GHz </td> <td>35 W </td> <td>$323 </td></tr> <tr> <th rowspan="9"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </th> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212275/intel-core-i5-11600k-processor-12m-cache-up-to-4-90-ghz.html">11600K</a> </td> <td rowspan="9">6 (12) </td> <td rowspan="2">3.9 GHz </td> <td rowspan="2">4.6 GHz </td> <td rowspan="2">4.9 GHz </td> <td rowspan="9">N/A </td> <td rowspan="9">12 MiB </td> <td rowspan="2">125 W </td> <td>$262 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212276/intel-core-i5-11600kf-processor-12m-cache-up-to-4-90-ghz.html">11600KF</a> </td> <td colspan="2">- </td> <td>$237 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212274/intel-core-i5-11600-processor-12m-cache-up-to-4-80-ghz.html">11600</a> </td> <td>2.8 GHz </td> <td>4.3 GHz </td> <td>4.8 GHz </td> <td rowspan="4"><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 750</a> </td> <td rowspan="3">1.3 GHz </td> <td>65 W </td> <td rowspan="2">$213 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212278/intel-core-i5-11600t-processor-12m-cache-up-to-4-10-ghz.html">11600T</a> </td> <td>1.7 GHz </td> <td>3.5 GHz </td> <td>4.1 GHz </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212277/intel-core-i5-11500-processor-12m-cache-up-to-4-60-ghz.html">11500</a> </td> <td>2.7 GHz </td> <td>4.2 GHz </td> <td>4.6 GHz </td> <td>65 W </td> <td rowspan="2">$192 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212272/intel-core-i5-11500t-processor-12m-cache-up-to-3-90-ghz.html">11500T</a> </td> <td>1.5 GHz </td> <td>3.4 GHz </td> <td>3.9 GHz </td> <td>1.2 GHz </td> <td>35 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212270/intel-core-i5-11400-processor-12m-cache-up-to-4-40-ghz.html">11400</a> </td> <td rowspan="2">2.6 GHz </td> <td rowspan="2">4.2 GHz </td> <td rowspan="2">4.4 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 730</a> </td> <td>1.3 GHz </td> <td rowspan="2">65 W </td> <td>$182 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212271/intel-core-i5-11400f-processor-12m-cache-up-to-4-40-ghz.html">11400F</a> </td> <td colspan="2">- </td> <td>$157 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/212273/intel-core-i5-11400t-processor-12m-cache-up-to-3-70-ghz.html">11400T</a> </td> <td>1.3 GHz </td> <td>3.3 GHz </td> <td>3.7 GHz </td> <td><a href="/wiki/Intel_Graphics_Technology#Integrated" title="Intel Graphics Technology">UHD 730</a> </td> <td>1.2 GHz </td> <td>35 W </td> <td>$182 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="12th_generation">12th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=47" title="Edit section: 12th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Alder_Lake">Alder Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=48" title="Edit section: Alder Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Alder_Lake" title="Alder Lake">Alder Lake</a></div> <p>Alder Lake is Intel's codename for the 12th generation of Intel Core processors based on a hybrid architecture utilizing Golden Cove high-performance cores and Gracemont power-efficient cores.<sup id="cite_ref-107" class="reference"><a href="#cite_note-107"><span class="cite-bracket">[</span>104<span class="cite-bracket">]</span></a></sup> <br /> It is fabricated using Intel's <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a> process, previously referred to as Intel 10 nm Enhanced SuperFin (10ESF). <br /> Intel officially announced 12th Gen Intel Core CPUs on October 27, 2021, and was launched to the market on November 4, 2021.<sup id="cite_ref-108" class="reference"><a href="#cite_note-108"><span class="cite-bracket">[</span>105<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading6"><h6 id="Desktop_processors_(Alder_Lake-S)"><span id="Desktop_processors_.28Alder_Lake-S.29"></span>Desktop processors (Alder Lake-S)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=49" title="Edit section: Desktop processors (Alder Lake-S)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All the CPUs support up to 128 GB of DDR4-3200 or DDR5-4800 RAM in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual channel mode</a>.<sup id="cite_ref-:2_109-0" class="reference"><a href="#cite_note-:2-109"><span class="cite-bracket">[</span>106<span class="cite-bracket">]</span></a></sup></li> <li>Some models feature integrated <a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD Graphics 770</a>, <a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD Graphics 730</a> or <a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD Graphics 710</a> GPU with 32/24/16 EUs and base frequency of 300 MHz.</li> <li>By default Alder Lake CPUs are configured to run at Turbo Power at all times and Base Power is only guaranteed when P-Cores/E-cores do <i>not</i> exceed the base clock rate.<sup id="cite_ref-:1_110-0" class="reference"><a href="#cite_note-:1-110"><span class="cite-bracket">[</span>107<span class="cite-bracket">]</span></a></sup></li> <li>Max Turbo Power: the maximum sustained (> 1 s) power dissipation of the processor as limited by current and/or temperature controls. Instantaneous power may exceed Maximum Turbo Power for short durations (≤ 10 ms). Maximum Turbo Power is configurable by system vendor and can be system specific.</li> <li>CPUs in <b>bold</b> below feature <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a> support only when paired with a motherboard based on the W680 chipset.<sup id="cite_ref-111" class="reference"><a href="#cite_note-111"><span class="cite-bracket">[</span>108<span class="cite-bracket">]</span></a></sup></li></ul> <p>*By default, Core i9 12900KS achieves 5.5 GHz only when using Thermal Velocity Boost<sup id="cite_ref-112" class="reference"><a href="#cite_note-112"><span class="cite-bracket">[</span>109<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable sortable" style="text-align:center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor <br />branding </th> <th rowspan="2">Model </th> <th colspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <br />(<a href="/wiki/Threads_(computer_science)" class="mw-redirect" title="Threads (computer science)">threads</a>) </th> <th colspan="2">Base <br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo<br />Boost</a> 2.0 </th> <th>Turbo <br />Max 3.0 </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">GPU</a> </th> <th rowspan="2">Smart <br />cache </th> <th colspan="2">Power </th> <th rowspan="2">Price <br />(USD) </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th>Model </th> <th>Max. <br />clock rate </th> <th>Base </th> <th>Turbo </th></tr> <tr> <td rowspan="6"><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">Core i9</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/225916/intel-core-i912900ks-processor-30m-cache-up-to-5-50-ghz.html"><b>12900KS</b></a> </td> <td rowspan="11">8 (16) </td> <td rowspan="6">8 (8) </td> <td>3.4 GHz </td> <td>2.5 GHz </td> <td>5.2 GHz </td> <td>4.0 GHz </td> <td>5.3 GHz </td> <td rowspan="2">UHD 770 </td> <td rowspan="2">1.55 GHz </td> <td rowspan="6">30 MB </td> <td>150 W </td> <td rowspan="3">241 W </td> <td>$739 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134599/intel-core-i912900k-processor-30m-cache-up-to-5-20-ghz.html"><b>12900K</b></a> </td> <td rowspan="2">3.2 GHz </td> <td rowspan="2">2.4 GHz </td> <td rowspan="2">5.1 GHz </td> <td rowspan="2">3.9 GHz </td> <td rowspan="2">5.2 GHz </td> <td rowspan="2">125 W </td> <td>$589 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134600/intel-core-i912900kf-processor-30m-cache-up-to-5-20-ghz.html">12900KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$564 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134597/intel-core-i912900-processor-30m-cache-up-to-5-10-ghz.html"><b>12900</b></a> </td> <td rowspan="2">2.4 GHz </td> <td rowspan="2">1.8 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">3.8 GHz </td> <td rowspan="2">5.1 GHz </td> <td>UHD 770 </td> <td>1.55 GHz </td> <td rowspan="2">65 W </td> <td rowspan="2">202 W </td> <td>$489 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134598/intel-core-i912900f-processor-30m-cache-up-to-5-10-ghz.html">12900F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$464 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134601/intel-core-i912900t-processor-30m-cache-up-to-4-90-ghz.html"><b>12900T</b></a> </td> <td>1.4 GHz </td> <td>1.0 GHz </td> <td>4.8 GHz </td> <td>3.6 GHz </td> <td>4.9 GHz </td> <td rowspan="2">UHD 770 </td> <td>1.55 GHz </td> <td>35 W </td> <td>106 W </td> <td>$489 </td></tr> <tr> <td rowspan="5"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134594/intel-core-i712700k-processor-25m-cache-up-to-5-00-ghz.html"><b>12700K</b></a> </td> <td rowspan="7">4 (4) </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">2.7 GHz </td> <td rowspan="2">4.9 GHz </td> <td rowspan="2">3.8 GHz </td> <td rowspan="2">5.0 GHz </td> <td>1.50 GHz </td> <td rowspan="5">25 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">190 W </td> <td>$409 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134595/intel-core-i712700kf-processor-25m-cache-up-to-5-00-ghz.html">12700KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$384 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134591/intel-core-i712700-processor-25m-cache-up-to-4-90-ghz.html"><b>12700</b></a> </td> <td rowspan="2">2.1 GHz </td> <td rowspan="2">1.6 GHz </td> <td rowspan="2">4.8 GHz </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2">4.9 GHz </td> <td>UHD 770 </td> <td>1.50 GHz </td> <td rowspan="2">65 W </td> <td rowspan="2">180 W </td> <td>$339 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134592/intel-core-i712700f-processor-25m-cache-up-to-4-90-ghz.html">12700F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$314 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134596/intel-core-i712700t-processor-25m-cache-up-to-4-70-ghz.html"><b>12700T</b></a> </td> <td>1.4 GHz </td> <td>1.0 GHz </td> <td>4.6 GHz </td> <td>3.4 GHz </td> <td>4.7 GHz </td> <td rowspan="2">UHD 770 </td> <td>1.50 GHz </td> <td>35 W </td> <td>99 W </td> <td>$339 </td></tr> <tr> <td rowspan="10"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134589/intel-core-i512600k-processor-20m-cache-up-to-4-90-ghz.html"><b>12600K</b></a> </td> <td rowspan="10">6 (12) </td> <td rowspan="2">3.7 GHz </td> <td rowspan="2">2.8 GHz </td> <td rowspan="2">4.9 GHz </td> <td rowspan="2">3.6 GHz </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1.45 GHz </td> <td rowspan="2">20 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">150 W </td> <td>$289 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134590/intel-core-i512600kf-processor-20m-cache-up-to-4-90-ghz.html">12600KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$264 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96149/intel-core-i512600-processor-18m-cache-up-to-4-80-ghz.html"><b>12600</b></a> </td> <td rowspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>3.3 GHz </td> <td rowspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4.8 GHz </td> <td colspan="2" rowspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">UHD 770 </td> <td rowspan="4">1.45 GHz </td> <td rowspan="4">18 MB </td> <td>65 W </td> <td>117 W </td> <td rowspan="2">$223 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96150/intel-core-i512600t-processor-18m-cache-up-to-4-60-ghz.html"><b>12600T</b></a> </td> <td>2.1 GHz </td> <td rowspan="2">4.6 GHz </td> <td>35 W </td> <td>74 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96144/intel-core-i512500-processor-18m-cache-up-to-4-60-ghz.html"><b>12500</b></a> </td> <td>3.0 GHz </td> <td>65 W </td> <td>117 W </td> <td rowspan="2">$202 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96140/intel-core-i512500t-processor-18m-cache-up-to-4-40-ghz.html"><b>12500T</b></a> </td> <td>2.0 GHz </td> <td>4.4 GHz </td> <td>35 W </td> <td>74 W </td></tr> <tr> <td>12490F<sup id="cite_ref-113" class="reference"><a href="#cite_note-113"><span class="cite-bracket">[</span>110<span class="cite-bracket">]</span></a></sup> </td> <td>3.0 GHz </td> <td>4.6 GHz </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>20 MB </td> <td rowspan="3">65 W </td> <td rowspan="3">117 W </td> <td>China<br />exclusive </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134586/intel-core-i512400-processor-18m-cache-up-to-4-40-ghz.html">12400</a> </td> <td rowspan="2">2.5 GHz </td> <td rowspan="2">4.4 GHz </td> <td>UHD 730 </td> <td>1.45 GHz </td> <td rowspan="3">18 MB </td> <td>$192 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134587/intel-core-i512400f-processor-18m-cache-up-to-4-40-ghz.html">12400F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$167 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223094/intel-core-i512400t-processor-18m-cache-up-to-4-20-ghz.html">12400T</a> </td> <td>1.8 GHz </td> <td>4.2 GHz </td> <td rowspan="4">UHD 730 </td> <td rowspan="3">1.45 GHz </td> <td>35 W </td> <td>74 W </td> <td>$192 </td></tr> <tr> <td rowspan="5"><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223095/intel-core-i312300-processor-12m-cache-up-to-4-40-ghz.html">12300</a> </td> <td rowspan="5">4 (8) </td> <td>3.5 GHz </td> <td>4.4 GHz </td> <td rowspan="5">12 MB </td> <td>60 W </td> <td>89 W </td> <td rowspan="2">$143 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223096/intel-core-i312300t-processor-12m-cache-up-to-4-20-ghz.html">12300T</a> </td> <td>2.3 GHz </td> <td>4.2 GHz </td> <td>35 W </td> <td>69 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/134584/intel-core-i312100-processor-12m-cache-up-to-4-30-ghz.html">12100</a> </td> <td rowspan="2">3.3 GHz </td> <td rowspan="2">4.3 GHz </td> <td>1.40 GHz </td> <td>60 W </td> <td rowspan="2">89 W </td> <td>$122 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132223/intel-core-i312100f-processor-12m-cache-up-to-4-30-ghz.html">12100F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>58 W </td> <td>$97 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/223097/intel-core-i312100t-processor-12m-cache-up-to-4-10-ghz.html">12100T</a> </td> <td>2.2 GHz </td> <td>4.1 GHz </td> <td>UHD 730 </td> <td>1.40 GHz </td> <td>35 W </td> <td>69 W </td> <td>$122 </td></tr> </tbody></table> <div class="mw-heading mw-heading6"><h6 id="Extreme-performance_Mobile_Processors_(Alder_Lake-HX)"><span id="Extreme-performance_Mobile_Processors_.28Alder_Lake-HX.29"></span>Extreme-performance Mobile Processors (Alder Lake-HX)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=50" title="Edit section: Extreme-performance Mobile Processors (Alder Lake-HX)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b>Bold</b> indicates ECC memory support</li></ul> <table class="wikitable sortable" style="text-align:center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor <br />branding </th> <th rowspan="2">Model </th> <th colspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <br />(<a href="/wiki/Threads_(computer_science)" class="mw-redirect" title="Threads (computer science)">threads</a>) </th> <th colspan="2">Base <br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo<br />Boost</a> 2.0 </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">UHD Graphics</a> </th> <th rowspan="2">Smart <br />cache </th> <th colspan="2">Power </th> <th rowspan="2">Price <br />(USD) </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th>EUs </th> <th>Max. freq. </th> <th>Base </th> <th>Turbo </th></tr> <tr> <td rowspan="2"><a href="/wiki/Core_i9" class="mw-redirect" title="Core i9">Core i9</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228439/intel-core-i912950hx-processor-30m-cache-up-to-5-00-ghz.html"><b>12950HX</b></a> </td> <td rowspan="4">8 (16) </td> <td rowspan="6">8 (8) </td> <td rowspan="2">2.3 GHz </td> <td rowspan="2">1.7 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">3.6 GHz </td> <td rowspan="6">32 </td> <td rowspan="2">1.55 GHz </td> <td rowspan="2">30 MB </td> <td rowspan="7">55 W </td> <td rowspan="7">157 W </td> <td>$590 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228441/intel-core-i912900hx-processor-30m-cache-up-to-5-00-ghz.html">12900HX</a> </td> <td>$606 </td></tr> <tr> <td rowspan="3"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228442/intel-core-i712850hx-processor-25m-cache-up-to-4-80-ghz.html"><b>12850HX</b></a> </td> <td>2.1 GHz </td> <td rowspan="3">1.5 GHz </td> <td rowspan="2">4.8 GHz </td> <td rowspan="2">3.4 GHz </td> <td rowspan="3">1.45 GHz </td> <td rowspan="2">25 MB </td> <td>$428 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226058/intel-core-i712800hx-processor-25m-cache-up-to-4-80-ghz.html">12800HX</a> </td> <td rowspan="2">2.0 GHz </td> <td>$457 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228795/intel-core-i712650hx-processor-24m-cache-up-to-4-70-ghz.html">12650HX</a> </td> <td>6 (12) </td> <td>4.7 GHz </td> <td rowspan="2">3.3 GHz </td> <td>24 MB </td> <td> </td></tr> <tr> <td rowspan="2"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228438/intel-core-i512600hx-processor-18m-cache-up-to-4-60-ghz.html"><b>12600HX</b></a> </td> <td rowspan="2">4 (8) </td> <td>2.5 GHz </td> <td rowspan="2">1.8 GHz </td> <td>4.6 GHz </td> <td>1.35 GHz </td> <td>18 MB </td> <td>$284 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/228794/intel-core-i512450hx-processor-12m-cache-up-to-4-40-ghz.html">12450HX</a> </td> <td>4 (4) </td> <td>2.4 GHz </td> <td>4.4 GHz </td> <td>3.1 GHz </td> <td>16 </td> <td>1.30 GHz </td> <td>12 MB </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="High-performance_Mobile_Processors_(Alder_Lake-H)"><span id="High-performance_Mobile_Processors_.28Alder_Lake-H.29"></span>High-performance Mobile Processors (Alder Lake-H)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=51" title="Edit section: High-performance Mobile Processors (Alder Lake-H)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="2"> <p><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a><br />(<a href="/wiki/Threads_(computer_science)" class="mw-redirect" title="Threads (computer science)">threads</a>) </p> </th> <th colspan="2">Base<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo<br />Boost</a> 2.0 </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Iris Xe Graphics</a> </th> <th rowspan="2">Smart<br />cache </th> <th rowspan="2">Base <p>Power </p> </th> <th rowspan="2">Turbo<br />power </th> <th rowspan="2">Price<br />(USD) </th></tr> <tr> <th><abbr title="Performance-cores">P-cores</abbr> </th> <th><abbr title="Efficient-cores">E-cores</abbr> </th> <th>P-cores </th> <th>E-cores </th> <th>P-cores </th> <th>E-cores </th> <th>EUs </th> <th>Max freq </th></tr> <tr> <td rowspan="2"><a href="/wiki/Core_i9" class="mw-redirect" title="Core i9">Core i9</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132215/intel-core-i912900hk-processor-24m-cache-up-to-5-00-ghz.html">12900HK</a> </td> <td rowspan="5">6 (12) </td> <td rowspan="4">8 (8) </td> <td rowspan="2">2.5 GHz </td> <td rowspan="3">1.8 GHz </td> <td rowspan="2">5.0 GHz </td> <td rowspan="2">3.8 GHz </td> <td rowspan="4">96 </td> <td rowspan="2">1.45 GHz </td> <td rowspan="5">24 MB </td> <td rowspan="8">45 W </td> <td rowspan="5">115 W </td> <td>$635 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132214/intel-core-i912900h-processor-24m-cache-up-to-5-00-ghz.html">12900H</a> </td> <td>$617 </td></tr> <tr> <td rowspan="3"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226059/intel-core-i712800h-processor-24m-cache-up-to-4-80-ghz.html">12800H</a> </td> <td>2.4 GHz </td> <td>4.8 GHz </td> <td>3.7 GHz </td> <td rowspan="4">1.4 GHz </td> <td rowspan="3">$457 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132228/intel-core-i712700h-processor-24m-cache-up-to-4-70-ghz.html">12700H</a> </td> <td rowspan="2">2.3 GHz </td> <td rowspan="2">1.7 GHz </td> <td rowspan="2">4.7 GHz </td> <td rowspan="2">3.5 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226066/intel-core-i712650h-processor-24m-cache-up-to-4-70-ghz.html">12650H</a> </td> <td>4 (4) </td> <td>64 </td></tr> <tr> <td rowspan="3"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96156/intel-core-i512600h-processor-18m-cache-up-to-4-50-ghz.html">12600H</a> </td> <td rowspan="3">4 (8) </td> <td rowspan="2">8 (8) </td> <td>2.7 GHz </td> <td>2.0 GHz </td> <td rowspan="2">4.5 GHz </td> <td rowspan="3">3.3 GHz </td> <td rowspan="2">80 </td> <td rowspan="2">18 MB </td> <td rowspan="3">95 W </td> <td rowspan="3">$311 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/96141/intel-core-i512500h-processor-18m-cache-up-to-4-50-ghz.html">12500H</a> </td> <td>2.5 GHz </td> <td>1.8 GHz </td> <td>1.3 GHz </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132222/intel-core-i512450h-processor-12m-cache-up-to-4-40-ghz.html">12450H</a> </td> <td>4 (4) </td> <td>2.0 GHz </td> <td>1.5 GHz </td> <td>4.4 GHz </td> <td>48 </td> <td>1.2 GHz </td> <td>12 MB </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Low_Power_Performance_Mobile_Processors_(Alder_Lake-P)"><span id="Low_Power_Performance_Mobile_Processors_.28Alder_Lake-P.29"></span>Low Power Performance Mobile Processors (Alder Lake-P)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=52" title="Edit section: Low Power Performance Mobile Processors (Alder Lake-P)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="2"> <p><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a><br />(<a href="/wiki/Threads_(computer_science)" class="mw-redirect" title="Threads (computer science)">threads</a>) </p> </th> <th colspan="2">Base<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo<br />Boost</a> 2.0 </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Iris Xe Graphics</a> </th> <th rowspan="2">Smart<br />cache </th> <th rowspan="2">Base <p>Power </p> </th> <th rowspan="2">Turbo<br />power </th> <th rowspan="2">Price<br />(USD) </th></tr> <tr> <th><abbr title="Performance-cores">P-cores</abbr> </th> <th><abbr title="Efficient-cores">E-cores</abbr> </th> <th>P-cores </th> <th>E-cores </th> <th>P-cores </th> <th>E-cores </th> <th>EUs </th> <th>Max freq </th></tr> <tr> <td rowspan="3"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226253/intel-core-i71280p-processor-24m-cache-up-to-4-80-ghz.html">1280P</a> </td> <td>6 (12) </td> <td rowspan="6">8 (8) </td> <td>1.8 GHz </td> <td>1.3 GHz </td> <td rowspan="2">4.8 GHz </td> <td>3.6 GHz </td> <td rowspan="3">96 </td> <td>1.45 GHz </td> <td>24 MB </td> <td rowspan="6">28 W </td> <td rowspan="6">64 W </td> <td>$482 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226255/intel-core-i71270p-processor-18m-cache-up-to-4-80-ghz.html">1270P</a> </td> <td rowspan="4">4 (8) </td> <td>2.2 GHz </td> <td>1.6 GHz </td> <td>3.5 GHz </td> <td rowspan="3">1.40 GHz </td> <td rowspan="2">18 MB </td> <td rowspan="2">$438 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226254/intel-core-i71260p-processor-18m-cache-up-to-4-70-ghz.html">1260P</a> </td> <td>2.1 GHz </td> <td>1.5 GHz </td> <td>4.7 GHz </td> <td>3.4 GHz </td></tr> <tr> <td rowspan="2"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226256/intel-core-i51250p-processor-12m-cache-up-to-4-40-ghz.html">1250P</a> </td> <td rowspan="2">1.7 GHz </td> <td rowspan="2">1.2 GHz </td> <td rowspan="3">4.4 GHz </td> <td rowspan="3">3.3 GHz </td> <td rowspan="2">80 </td> <td rowspan="3">12 MB </td> <td rowspan="2">$320 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/132221/intel-core-i51240p-processor-12m-cache-up-to-4-40-ghz.html">1240P</a> </td> <td>1.30 GHz </td></tr> <tr> <td><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226257/intel-core-i31220p-processor-12m-cache-up-to-4-40-ghz.html">1220P</a> </td> <td>2 (4) </td> <td>1.5 GHz </td> <td>1.1 GHz </td> <td>64 </td> <td>1.10 GHz </td> <td>$281 </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Ultra_Low_Power_Mobile_Processors_(Alder_Lake-U)"><span id="Ultra_Low_Power_Mobile_Processors_.28Alder_Lake-U.29"></span>Ultra Low Power Mobile Processors (Alder Lake-U)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=53" title="Edit section: Ultra Low Power Mobile Processors (Alder Lake-U)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align: center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="2"> <p><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a><br />(<a href="/wiki/Threads_(computer_science)" class="mw-redirect" title="Threads (computer science)">threads</a>) </p> </th> <th colspan="2">Base<br /><a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo<br />Boost</a> 2.0 </th> <th colspan="2"><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Iris Xe Graphics</a> </th> <th rowspan="2">Smart<br />cache </th> <th rowspan="2">Base <p>power </p> </th> <th rowspan="2">Turbo<br />power </th> <th rowspan="2">Price<br />(USD) </th></tr> <tr> <th><abbr title="Performance-cores">P-cores</abbr> </th> <th><abbr title="Efficient-cores">E-cores</abbr> </th> <th>P-cores </th> <th>E-cores </th> <th>P-cores </th> <th>E-cores </th> <th>EUs </th> <th>Max freq </th></tr> <tr> <td rowspan="4"><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226258/intel-core-i71265u-processor-12m-cache-up-to-4-80-ghz.html">1265U</a> </td> <td rowspan="10">2 (4) </td> <td rowspan="8">8 (8) </td> <td>1.8 GHz </td> <td>1.3 GHz </td> <td>4.8 GHz </td> <td>3.6 GHz </td> <td rowspan="4">96 </td> <td>1.25 GHz </td> <td rowspan="8">12 MB </td> <td>15 W </td> <td>55 W </td> <td>$426 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226455/intel-core-i71260u-processor-12m-cache-up-to-4-70-ghz.html">1260U</a> </td> <td>1.1 GHz </td> <td>0.8 GHz </td> <td rowspan="3">4.7 GHz </td> <td rowspan="3">3.5 GHz </td> <td>0.9 GHz </td> <td>9 W </td> <td>29 W </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226259/intel-core-i71255u-processor-12m-cache-up-to-4-70-ghz.html">1255U</a> </td> <td>1.7 GHz </td> <td>1.2 GHz </td> <td>1.25 GHz </td> <td>15 W </td> <td>55 W </td> <td>$426 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226454/intel-core-i71250u-processor-12m-cache-up-to-4-70-ghz.html">1250U</a> </td> <td>1.1 GHz </td> <td>0.8 GHz </td> <td>0.9 GHz </td> <td>9 W </td> <td>29 W </td></tr> <tr> <td rowspan="4"><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226260/intel-core-i51245u-processor-12m-cache-up-to-4-40-ghz.html">1245U</a> </td> <td>1.6 GHz </td> <td>1.2 GHz </td> <td rowspan="6">4.4 GHz </td> <td rowspan="6">3.3 GHz </td> <td rowspan="4">80 </td> <td>1.2 GHz </td> <td>15 W </td> <td>55 W </td> <td>$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226452/intel-core-i51240u-processor-12m-cache-up-to-4-40-ghz.html">1240U</a> </td> <td>1.1 GHz </td> <td>0.8 GHz </td> <td>0.9 GHz </td> <td>9 W </td> <td>29 W </td> <td> </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226261/intel-core-i51235u-processor-12m-cache-up-to-4-40-ghz.html">1235U</a> </td> <td>1.3 GHz </td> <td>0.9 GHz </td> <td>1.2 GHz </td> <td>15 W </td> <td>55 W </td> <td>$309 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226453/intel-core-i51230u-processor-12m-cache-up-to-4-40-ghz.html">1230U</a> </td> <td>1.0 GHz </td> <td>0.7 GHz </td> <td>0.9 GHz </td> <td>9 W </td> <td>29 W </td></tr> <tr> <td rowspan="2"><a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226263/intel-core-i31215u-processor-10m-cache-up-to-4-40-ghz.html">1215U</a> </td> <td rowspan="2">4 (4) </td> <td>1.2 GHz </td> <td>1.2 GHz </td> <td rowspan="2">64 </td> <td>1.1 GHz </td> <td rowspan="2">10 MB </td> <td>15 W </td> <td>55 W </td> <td>$281 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/226451/intel-core-i31210u-processor-10m-cache-up-to-4-40-ghz.html">1210U</a> </td> <td>1.0 GHz </td> <td>0.7 GHz </td> <td>0.85 GHz </td> <td>9 W </td> <td>29 W </td> <td> </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="13th_generation">13th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=54" title="Edit section: 13th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Raptor_Lake">Raptor Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=55" title="Edit section: Raptor Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Raptor_Lake" title="Raptor Lake">Raptor Lake</a></div> <p>Raptor Lake is Intel's codename for the 13th generation of Intel Core processors and the second generation based on a hybrid architecture.<sup id="cite_ref-114" class="reference"><a href="#cite_note-114"><span class="cite-bracket">[</span>111<span class="cite-bracket">]</span></a></sup> <br /> It is fabricated using an improved version of Intel's <a href="/wiki/7_nm_process" title="7 nm process">Intel 7</a> process.<sup id="cite_ref-115" class="reference"><a href="#cite_note-115"><span class="cite-bracket">[</span>112<span class="cite-bracket">]</span></a></sup> Intel launched Raptor Lake on October 22, 2022. </p> <div class="mw-heading mw-heading6"><h6 id="Desktop_Processors_(Raptor_Lake-S)"><span id="Desktop_Processors_.28Raptor_Lake-S.29"></span>Desktop Processors (Raptor Lake-S)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=56" title="Edit section: Desktop Processors (Raptor Lake-S)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>All CPUs support up to DDR5 4800 and 192 GiB of RAM <ul><li>13600 and better support DDR5 5600</li> <li>13500 and lower support DDR5 4800</li></ul></li> <li>Intel 600 and 700 chipset support with LGA 1700 <ul><li>Intel 600 Series chipsets require BIOS update to achieve support for Raptor Lake-S</li></ul></li> <li>First 6 GHz processor (13900KS)*</li></ul> <p>*By default, Core i9 13900KS achieves 6.0 GHz only when using Thermal Velocity Boost with sufficient power and cooling. </p> <table class="wikitable sortable" style="text-align: center;"> <caption> </caption> <tbody><tr> <th rowspan="2">Processor <p>branding </p> </th> <th rowspan="2">Model </th> <th colspan="2">Cores <p>(Threads) </p> </th> <th colspan="2">Base <p>clock rate </p> </th> <th colspan="2">Turbo <p>Boost 2.0 </p> </th> <th>Turbo <p>Boost 3.0 </p> </th> <th colspan="2">Iris Xe Graphics </th> <th rowspan="2">Smart <p>cache </p> </th> <th colspan="2">Power </th> <th rowspan="2">Price <p>(USD) </p> </th></tr> <tr> <th>P-core </th> <th>E-core </th> <th>P-core </th> <th>E-core </th> <th>P-core </th> <th>E-core </th> <th>P-core </th> <th>EUs </th> <th>Max freq </th> <th>Base </th> <th>Turbo </th></tr> <tr> <td rowspan="6"><a href="/wiki/Core_i9" class="mw-redirect" title="Core i9">Core i9</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/232167/intel-core-i913900ks-processor-36m-cache-up-to-6-00-ghz.html">13900KS</a> </td> <td rowspan="11">8 (16) </td> <td rowspan="6">16 (16) </td> <td>3.2 GHz </td> <td>2.4 GHz </td> <td rowspan="3">5.4 GHz </td> <td rowspan="3">4.3 GHz </td> <td>5.8 GHz </td> <td rowspan="2">32 </td> <td rowspan="2">1.65 GHz </td> <td rowspan="6">36 MB </td> <td>150 W </td> <td rowspan="3">253 W </td> <td>$689 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230496/intel-core-i913900k-processor-36m-cache-up-to-5-80-ghz.html">13900K</a> </td> <td rowspan="2">3.0 GHz </td> <td rowspan="2">2.2 GHz </td> <td rowspan="2">5.7 GHz </td> <td rowspan="2">125 W </td> <td>$589 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230497/intel-core-i913900kf-processor-36m-cache-up-to-5-80-ghz.html">13900KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$564 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230499/intel-core-i913900-processor-36m-cache-up-to-5-60-ghz.html">13900</a> </td> <td rowspan="2">2.0 GHz </td> <td rowspan="2">1.5 GHz </td> <td rowspan="2">5.2 GHz </td> <td rowspan="2">4.2 GHz </td> <td rowspan="2">5.5 GHz </td> <td>32 </td> <td>1.65 GHz </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td> <td>$549 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230502/intel-core-i913900f-processor-36m-cache-up-to-5-60-ghz.html">13900F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$524 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230498/intel-core-i913900t-processor-36m-cache-up-to-5-30-ghz.html">13900T</a> </td> <td>1.1 GHz </td> <td>0.8 GHz </td> <td>5.1 GHz </td> <td>3.9 GHz </td> <td>5.3 GHz </td> <td rowspan="2">32 </td> <td>1.65 GHz </td> <td>35 W </td> <td>106 W </td> <td>$549 </td></tr> <tr> <td rowspan="5"><a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230500/intel-core-i713700k-processor-30m-cache-up-to-5-40-ghz.html">13700K</a> </td> <td rowspan="11">8 (8) </td> <td rowspan="2">3.4 GHz </td> <td rowspan="2">2.5 GHz </td> <td rowspan="2">5.3 GHz </td> <td rowspan="2">4.2 GHz </td> <td rowspan="2">5.4 GHz </td> <td>1.60 GHz </td> <td rowspan="5">30 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">253 W </td> <td>$409 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230489/intel-core-i713700kf-processor-30m-cache-up-to-5-40-ghz.html">13700KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">$384 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230490/intel-core-i713700-processor-30m-cache-up-to-5-20-ghz.html">13700</a> </td> <td rowspan="2">2.1 GHz </td> <td rowspan="2">1.5 GHz </td> <td rowspan="2">5.1 GHz </td> <td rowspan="2">4.1 GHz </td> <td rowspan="2">5.2 GHz </td> <td>32 </td> <td>1.60 GHz </td> <td rowspan="2">65 W </td> <td rowspan="2">219 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230491/intel-core-i713700f-processor-30m-cache-up-to-5-20-ghz.html">13700F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$359 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230492/intel-core-i713700t-processor-30m-cache-up-to-4-90-ghz.html">13700T</a> </td> <td>1.4 GHz </td> <td>1.0 GHz </td> <td>4.8 GHz </td> <td>3.6 GHz </td> <td>4.9 GHz </td> <td rowspan="2">32 </td> <td>1.60 GHz </td> <td>35 W </td> <td>106 W </td> <td>$384 </td></tr> <tr> <td rowspan="9"><a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230493/intel-core-i513600k-processor-24m-cache-up-to-5-10-ghz.html">13600K</a> </td> <td rowspan="9">6 (12) </td> <td rowspan="2">3.5 GHz </td> <td rowspan="2">2.6 GHz </td> <td rowspan="2">5.1 GHz </td> <td rowspan="2">3.9 GHz </td> <td rowspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1.50 GHz </td> <td rowspan="6">24 MB </td> <td rowspan="2">125 W </td> <td rowspan="2">181 W </td> <td>$319 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230494/intel-core-i513600kf-processor-24m-cache-up-to-5-10-ghz.html">13600KF</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$294 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230574/intel-core-i513600-processor-24m-cache-up-to-5-00-ghz.html">13600</a> </td> <td>2.7 GHz </td> <td>2.0 GHz </td> <td>5.0 GHz </td> <td>3.7 GHz </td> <td rowspan="4">32 </td> <td rowspan="5">1.55 GHz </td> <td>65 W </td> <td>154 W </td> <td rowspan="2">$255 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230573/intel-core-i513600t-processor-24m-cache-up-to-4-80-ghz.html">13600T</a> </td> <td>1.8 GHz </td> <td>1.3 GHz </td> <td rowspan="2">4.8 GHz </td> <td>3.4 GHz </td> <td>35 W </td> <td>92 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230580/intel-core-i513500-processor-24m-cache-up-to-4-80-ghz.html">13500</a> </td> <td>2.5 GHz </td> <td>1.8 GHz </td> <td>3.5 GHz </td> <td>65 W </td> <td>154 W </td> <td rowspan="2">$232 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230578/intel-core-i513500t-processor-24m-cache-up-to-4-60-ghz.html">13500T</a> </td> <td>1.6 GHz </td> <td>1.2 GHz </td> <td rowspan="3">4.6 GHz </td> <td>3.2 GHz </td> <td>35 W </td> <td>92 W </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230495/intel-core-i513400-processor-20m-cache-up-to-4-60-ghz.html">13400</a> </td> <td rowspan="3">4 (4) </td> <td rowspan="2">2.5 GHz </td> <td rowspan="2">1.8 GHz </td> <td rowspan="2">3.3 GHz </td> <td>24 </td> <td rowspan="3">20 MB </td> <td rowspan="2">65 W </td> <td rowspan="2">148 W </td> <td>$221 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230501/intel-core-i513400f-processor-20m-cache-up-to-4-60-ghz.html">13400F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>$196 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230577/intel-core-i513400t-processor-20m-cache-up-to-4-40-ghz.html">13400T</a> </td> <td>1.3 GHz </td> <td>1.0 GHz </td> <td>4.4 GHz </td> <td>3.0 GHz </td> <td rowspan="2">24 </td> <td>1.55 GHz </td> <td>35 W </td> <td>82 W </td> <td>$221 </td></tr> <tr> <td rowspan="3"><a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a> </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230575/intel-core-i313100-processor-12m-cache-up-to-4-50-ghz.html">13100</a> </td> <td rowspan="3">4 (8) </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">3.4 GHz </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">4.5 GHz </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1.50 GHz </td> <td rowspan="3">12 MB </td> <td>60 W </td> <td rowspan="2">89 W </td> <td>$134 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230576/intel-core-i313100f-processor-12m-cache-up-to-4-50-ghz.html">13100F</a> </td> <td colspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>58 W </td> <td>$109 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/230579/intel-core-i313100t-processor-12m-cache-up-to-4-20-ghz.html">13100T</a> </td> <td>2.5 GHz </td> <td>4.2 GHz </td> <td>24 </td> <td>1.50 GHz </td> <td>35 W </td> <td>69 W </td> <td>$134 </td></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="14th_generation">14th generation</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=57" title="Edit section: 14th generation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading5"><h5 id="Raptor_Lake_Refresh">Raptor Lake Refresh</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=58" title="Edit section: Raptor Lake Refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Raptor_Lake#Raptor_Lake-S_Refresh" title="Raptor Lake">Raptor Lake Refresh</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/List_of_Intel_processors#13th_and_14th_generation_Core" title="List of Intel processors">List of Intel processors § 13th and 14th generation Core</a></div> <p>Raptor Lake Refresh is Intel's codename for the 14th generation of Intel Core processors. It is a refresh and based on the same architecture of the 13th generation with clock speeds of up to 6.2 GHz on the Core i9 14900KS, 6 GHz on the Core i9 14900K and 14900KF, 5.6 GHz on the Core i7 14700K and 14700KF, and 5.3 GHz on the Core i5 14600K and 13400KF as well as UHD Graphics 770 on non-F processors. They are still based on the Intel 7 process node.<sup id="cite_ref-:6_116-0" class="reference"><a href="#cite_note-:6-116"><span class="cite-bracket">[</span>113<span class="cite-bracket">]</span></a></sup> Introduced on October 17, 2023, these CPUs are designed for the LGA 1700 socket, which allows for compatibility with 600 and 700 series motherboards.<sup id="cite_ref-117" class="reference"><a href="#cite_note-117"><span class="cite-bracket">[</span>114<span class="cite-bracket">]</span></a></sup> It is the last generation CPUs to use the Intel Core i3, i5, i7 and i9 naming scheme as Intel announced that they will be dropping the "i" prefix for future Intel Core processors in 2023.<sup id="cite_ref-Intel_drops_I_processor_1-1" class="reference"><a href="#cite_note-Intel_drops_I_processor-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p>The 14th generation CPU does not feature any major architectural changes over Raptor Lake, but does feature some minor improvements.<sup id="cite_ref-:7_118-0" class="reference"><a href="#cite_note-:7-118"><span class="cite-bracket">[</span>115<span class="cite-bracket">]</span></a></sup> The 14th generation CPU was widely criticized<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:No_original_research" title="Wikipedia:No original research"><span title="The material near this tag possibly contains original research. (June 2024)">original research?</span></a></i>]</sup> as a last-ditch effort to beat AMD's <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> with 3D V-Cache<sup id="cite_ref-119" class="reference"><a href="#cite_note-119"><span class="cite-bracket">[</span>116<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-120" class="reference"><a href="#cite_note-120"><span class="cite-bracket">[</span>117<span class="cite-bracket">]</span></a></sup> Intel's desktop version of the next generation architecture, <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a>, was cancelled and the <a href="/wiki/Arrow_Lake_(microprocessor)" title="Arrow Lake (microprocessor)">Arrow Lake</a> architecture was not yet ready for release.<sup id="cite_ref-121" class="reference"><a href="#cite_note-121"><span class="cite-bracket">[</span>118<span class="cite-bracket">]</span></a></sup> </p><p>In addition to the Raptor Lake-S Refresh desktop processors, Intel also launched 14th gen Raptor Lake-HX Refresh mobile processors in January 2024.<sup id="cite_ref-122" class="reference"><a href="#cite_note-122"><span class="cite-bracket">[</span>119<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Core_and_Core_Ultra_3/5/7/9"><span id="Core_and_Core_Ultra_3.2F5.2F7.2F9"></span>Core and Core Ultra 3/5/7/9</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=59" title="Edit section: Core and Core Ultra 3/5/7/9"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Starting with the Meteor Lake mobile series launched in December 2023 (with the exception of Raptor Lake-HX Refresh),<sup id="cite_ref-coreultra-series1_123-0" class="reference"><a href="#cite_note-coreultra-series1-123"><span class="cite-bracket">[</span>120<span class="cite-bracket">]</span></a></sup> Intel introduced a new naming system for its new and upcoming processors. The numbers 3, 5, 7 and 9 which denote tiers are still used, but the letter 'i' is dropped, and there is a new "Core Ultra" sub-brand. Like AMD with their <a href="/wiki/Ryzen#Mobile_6" title="Ryzen">Ryzen 7000 mobile series</a> and later processors, Intel now refreshes older architectures to be sold as more affordable mainstream processors while the latest architectures are released as "premium" products, under the Core Ultra brand.<sup id="cite_ref-core-series1_124-0" class="reference"><a href="#cite_note-core-series1-124"><span class="cite-bracket">[</span>121<span class="cite-bracket">]</span></a></sup> </p><p>This new naming system also cuts the number of model number digits down from 4-5 to 3-4, e.g. Core 1xx series instead of Core 8xxx or 14xxx series. </p><p>Intel no longer refers to iterations of product series under "<i>n</i>th generation" anymore, instead using "Series <i>n</i>". Otherwise the latest series launched in December 2023 would be called 15th generation.<sup id="cite_ref-125" class="reference"><a href="#cite_note-125"><span class="cite-bracket">[</span>122<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Series_1">Series 1</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=60" title="Edit section: Series 1"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The Series 1 of Core processors consists of the Raptor Lake-U Refresh mobile series released January 2024 under the Core brand,<sup id="cite_ref-core-series1_124-1" class="reference"><a href="#cite_note-core-series1-124"><span class="cite-bracket">[</span>121<span class="cite-bracket">]</span></a></sup> and the Meteor Lake-U/H mobile series released December 2023 under the Core Ultra brand.<sup id="cite_ref-coreultra-series1_123-1" class="reference"><a href="#cite_note-coreultra-series1-123"><span class="cite-bracket">[</span>120<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable" style="text-align: center;"> <caption>Overview of mobile Core Series 1 models </caption> <tbody><tr> <th>Model line </th> <th>Codename </th> <th><a href="/wiki/Microarchitecture" title="Microarchitecture">Architecture</a> </th> <th>P-core count </th> <th>E-core count </th> <th>Integrated graphics </th></tr> <tr> <td style="text-align: left;"><a href="/wiki/List_of_Intel_Core_processors#Meteor_Lake-H" title="List of Intel Core processors"><i>Core Ultra 5/7/9 1xxH</i></a> </td> <td>Meteor Lake-H </td> <td rowspan="2"><a href="/w/index.php?title=Redwood_Cove_(microarchitecture)&action=edit&redlink=1" class="new" title="Redwood Cove (microarchitecture) (page does not exist)">Redwood Cove</a> (P-cores)<br /><a href="/w/index.php?title=Crestmont_(microarchitecture)&action=edit&redlink=1" class="new" title="Crestmont (microarchitecture) (page does not exist)">Crestmont</a> (E- and LP E-cores) </td> <td>4–6 </td> <td>8 </td> <td>Arc (<a href="/wiki/Arc_Alchemist" class="mw-redirect" title="Arc Alchemist">Alchemist</a>), up to 8 Xe-cores </td></tr> <tr> <td style="text-align: left;"><a href="/wiki/List_of_Intel_Core_processors#Meteor_Lake-U" title="List of Intel Core processors"><i>Core Ultra 5/7 1xxU</i></a> </td> <td>Meteor Lake-U </td> <td rowspan="2">2 </td> <td rowspan="2">4–8 </td> <td>Intel Graphics (Alchemist), up to 4 Xe-cores </td></tr> <tr> <td style="text-align: left;"><a href="/wiki/List_of_Intel_Core_processors#Raptor_Lake-U_Refresh" title="List of Intel Core processors"><i>Core 3/5/7 1xxU</i></a> </td> <td>Raptor Lake-U Refresh </td> <td><a href="/wiki/Raptor_Cove_(microarchitecture)" class="mw-redirect" title="Raptor Cove (microarchitecture)">Raptor Cove</a> (P-cores)<br /><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a> (E-cores) </td> <td>Intel Graphics (<a href="/wiki/Intel_Graphics_Technology#Xe-LP_architecture_(Gen12)" title="Intel Graphics Technology">Xe-LP</a>), up to 96 EU </td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Meteor_Lake">Meteor Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=61" title="Edit section: Meteor Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Meteor_Lake" title="Meteor Lake">Meteor Lake</a></div> <p><b>Meteor Lake</b> is Intel's <a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">codename</a> for the first generation of Intel Core Ultra mobile processors,<sup id="cite_ref-Gomes-2022_126-0" class="reference"><a href="#cite_note-Gomes-2022-126"><span class="cite-bracket">[</span>123<span class="cite-bracket">]</span></a></sup> and was officially launched on December 14, 2023.<sup id="cite_ref-Intel-AI-PC-2023_127-0" class="reference"><a href="#cite_note-Intel-AI-PC-2023-127"><span class="cite-bracket">[</span>124<span class="cite-bracket">]</span></a></sup> It is the first generation of Intel mobile processors to use a <a href="/wiki/Chiplet" title="Chiplet">chiplet</a> architecture which means that the processor is a multi-chip module.<sup id="cite_ref-Gomes-2022_126-1" class="reference"><a href="#cite_note-Gomes-2022-126"><span class="cite-bracket">[</span>123<span class="cite-bracket">]</span></a></sup> Tim Wilson led the <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a> development for this generation microprocessor.<sup id="cite_ref-Intel-Corporation-SoC-40-years-2004_128-0" class="reference"><a href="#cite_note-Intel-Corporation-SoC-40-years-2004-128"><span class="cite-bracket">[</span>125<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading6"><h6 id="Process_technology">Process technology</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=62" title="Edit section: Process technology"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Due to its <a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-Chip Module (MCM)</a> construction, Meteor Lake can take advantage of different process nodes that are best suited to the use case. Meteor Lake is built using four different fabrication nodes, including both Intel's own nodes and external nodes outsourced to fabrication competitor <a href="/wiki/TSMC" title="TSMC">TSMC</a>. The "Intel 4" process used for the CPU tile is the first process node in which Intel is utilising <a href="/wiki/Extreme_ultraviolet_lithography" title="Extreme ultraviolet lithography">extreme ultraviolet (EUV)</a> lithography, which is necessary for creating nodes 7nm and smaller. The interposer base tile is fabricated on Intel's 22FFL, or "Intel 16", process.<sup id="cite_ref-129" class="reference"><a href="#cite_note-129"><span class="cite-bracket">[</span>126<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-130" class="reference"><a href="#cite_note-130"><span class="cite-bracket">[</span>127<span class="cite-bracket">]</span></a></sup> The 22FFL <a href="/wiki/Fin_field-effect_transistor" title="Fin field-effect transistor">Fin Field-Effect Transistor (FinFET)</a> Low-power node, first announced in March 2017, was designed for inexpensive low power operation.<sup id="cite_ref-131" class="reference"><a href="#cite_note-131"><span class="cite-bracket">[</span>128<span class="cite-bracket">]</span></a></sup> The interposer base tile is designed to connect tiles together and allow for die-to-die communication which does not require the most advanced, expensive nodes so an older, inexpensive node can be used instead. </p> <table class="wikitable plainrowheaders" style="text-align: left;"> <tbody><tr> <th>Tile </th> <th>Node </th> <th>EUV </th> <th>Die size </th> <th><style data-mw-deduplicate="TemplateStyles:r1038841319">.mw-parser-output .tooltip-dotted{border-bottom:1px dotted;cursor:help}</style><span class="rt-commentedText tooltip tooltip-dotted" title="Reference(s)">Ref.</span> </th></tr> <tr> <th scope="row">Compute tile </th> <td><a href="/wiki/5_nm_process" title="5 nm process">Intel 4</a> (7nm EUV) </td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2"><span typeof="mw:File"><span title="Yes"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></span></span> </td> <td>69.67<span class="nowrap"> </span>mm<sup>2</sup> </td> <td rowspan="5" style="text-align: center;"><sup id="cite_ref-132" class="reference"><a href="#cite_note-132"><span class="cite-bracket">[</span>129<span class="cite-bracket">]</span></a></sup><br /><sup id="cite_ref-Alcorn_2023-09-19_133-0" class="reference"><a href="#cite_note-Alcorn_2023-09-19-133"><span class="cite-bracket">[</span>130<span class="cite-bracket">]</span></a></sup><br /><sup id="cite_ref-Zuhair_134-0" class="reference"><a href="#cite_note-Zuhair-134"><span class="cite-bracket">[</span>131<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th scope="row">Graphics tile </th> <td><a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/5_nm_process" title="5 nm process">N5</a> </td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2"><span typeof="mw:File"><span title="Yes"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></span></span> </td> <td>44.25<span class="nowrap"> </span>mm<sup>2</sup> </td></tr> <tr> <th scope="row">SoC tile </th> <td rowspan="2"><a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">N6</a> </td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2"><span typeof="mw:File"><span title="Yes"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></span></span> </td> <td>100.15<span class="nowrap"> </span>mm<sup>2</sup> </td></tr> <tr> <th scope="row">I/O extender tile </th> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2"><span typeof="mw:File"><span title="Yes"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></span></span> </td> <td>27.42<span class="nowrap"> </span>mm<sup>2</sup> </td></tr> <tr> <th scope="row">Foveros interposer base tile </th> <td><a href="/wiki/22_nm_process" title="22 nm process">Intel 16</a> (22FFL) </td> <td data-sort-value="No" style="background: #FFE3E3; color:black; vertical-align: middle; text-align: center;" class="table-no2"><span typeof="mw:File"><span title="No"><img alt="No" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/13px-Dark_Red_x.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/20px-Dark_Red_x.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/26px-Dark_Red_x.svg.png 2x" data-file-width="600" data-file-height="600" /></span></span> </td> <td>265.65<span class="nowrap"> </span>mm<sup>2</sup> </td></tr></tbody></table> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors">Mobile processors</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=63" title="Edit section: Mobile processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>Meteor Lake-H</b> </p><p>155H, 165H, and 185H support P-core Turbo Boost 3.0 running at the same frequency as Turbo Boost 2.0. </p> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="3"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="3">Base <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a><br />(GHz) </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a><br />(GHz) </th> <th colspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a> graphics </th> <th rowspan="2"><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">Smart</a><br /><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">cache</a> </th> <th colspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price<br />(USD)<sup id="cite_ref-RCP_135-0" class="reference"><a href="#cite_note-RCP-135"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th>Xe-cores<br />(<abbr title="Xe Vector Engines">XVEs</abbr>) </th> <th>Max. freq.<br />(GHz) </th> <th>Base </th> <th><abbr title="Configurable TDP">cTDP</abbr> </th> <th>Turbo </th></tr> <tr> <td>Core Ultra 9 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236849/intel-core-ultra-9-processor-185h-24m-cache-up-to-5-10-ghz.html">185H</a></abbr> </td> <td rowspan="3">6 (12) </td> <td rowspan="5">8 (8) </td> <td rowspan="5">2 (2) </td> <td>2.3 </td> <td>1.8 </td> <td>1.0 </td> <td>5.1 </td> <td rowspan="3">3.8 </td> <td rowspan="5">2.5 </td> <td rowspan="4">8 (128) </td> <td>2.35 </td> <td rowspan="3">24 MB </td> <td>45 W </td> <td>35–65 W </td> <td rowspan="5">115 W </td> <td>Q4'23 </td> <td>$640 </td></tr> <tr> <td rowspan="2">Core Ultra 7 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236851/intel-core-ultra-7-processor-165h-24m-cache-up-to-5-00-ghz.html">165H</a></abbr> </td> <td rowspan="2">1.4 </td> <td rowspan="2">0.9 </td> <td rowspan="4">0.7 </td> <td>5.0 </td> <td>2.3 </td> <td rowspan="4">28 W </td> <td rowspan="4">20–65 W </td> <td>Q4'23 </td> <td>$460 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236847/intel-core-ultra-7-processor-155h-24m-cache-up-to-4-80-ghz.html">155H</a> </td> <td>4.8 </td> <td>2.25 </td> <td>Q4'23 </td> <td>$503 </td></tr> <tr> <td rowspan="2">Core Ultra 5 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236850/intel-core-ultra-5-processor-135h-18m-cache-up-to-4-60-ghz.html">135H</a></abbr> </td> <td rowspan="2">4 (8) </td> <td>1.7 </td> <td>1.2 </td> <td>4.6 </td> <td rowspan="2">3.6 </td> <td rowspan="2">2.2 </td> <td rowspan="2">18 MB </td> <td>Q4'23 </td> <td>$342 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/236848/intel-core-ultra-5-processor-125h-18m-cache-up-to-4-50-ghz.html">125H</a> </td> <td>1.2 </td> <td>0.7 </td> <td>4.5 </td> <td>7 (112) </td> <td>Q4'23 </td> <td>$375 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-RCP-135"><span class="mw-cite-backlink"><b><a href="#cite_ref-RCP_135-0">^</a></b></span> <span class="reference-text">Price is Recommended Customer Price (RCP) at launch. RCP is the trade price that processors are sold by Intel to retailers and OEMs. Actual MSRP for consumers is higher</span> </li> </ol></div></div> <p><b>Meteor Lake-U</b> </p><p>The integrated GPU is branded as "Intel Graphics" but still use the same GPU microarchitecture as "Intel Arc Graphics" on the H series models. </p><p>All models support DDR5 memory except 134U and 164U. </p> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="3"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="3">Base <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a><br />(GHz) </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a><br />(GHz) </th> <th colspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Graphics</a> </th> <th rowspan="2"><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">Smart</a><br /><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">cache</a> </th> <th colspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price<br />(USD)<sup id="cite_ref-RCP_136-0" class="reference"><a href="#cite_note-RCP-136"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th>Xe-cores<br />(<abbr title="Xe Vector Engines">XVEs</abbr>) </th> <th>Max. freq.<br />(GHz) </th> <th>Base </th> <th><abbr title="Configurable TDP">cTDP</abbr> </th> <th>Turbo </th></tr> <tr> <th colspan="19">Low power (MTL-U15) </th></tr> <tr> <td rowspan="2">Core Ultra 7 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237329/intel-core-ultra-7-processor-165u-12m-cache-up-to-4-90-ghz.html">165U</a></abbr> </td> <td rowspan="5">2 (4) </td> <td rowspan="4">8 (8) </td> <td rowspan="5">2 (2) </td> <td rowspan="2">1.7 </td> <td rowspan="2">1.2 </td> <td rowspan="5">0.7 </td> <td>4.9 </td> <td rowspan="2">3.8 </td> <td rowspan="5">2.1 </td> <td rowspan="4">4 (64) </td> <td>2.0 </td> <td rowspan="4">12 MB </td> <td rowspan="5">15 W </td> <td rowspan="5">12–28 W </td> <td rowspan="5">57 W </td> <td>Q4'23 </td> <td>$448 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237327/intel-core-ultra-7-processor-155u-12m-cache-up-to-4-80-ghz.html">155U</a> </td> <td>4.8 </td> <td>1.95 </td> <td>Q4'23 </td> <td>$490 </td></tr> <tr> <td rowspan="3">Core Ultra 5 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237328/intel-core-ultra-5-processor-135u-12m-cache-up-to-4-40-ghz.html">135U</a></abbr> </td> <td>1.6 </td> <td>1.1 </td> <td>4.4 </td> <td rowspan="2">3.6 </td> <td>1.9 </td> <td>Q4'23 </td> <td>$332 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237330/intel-core-ultra-5-processor-125u-12m-cache-up-to-4-30-ghz.html">125U</a> </td> <td>1.3 </td> <td>0.8 </td> <td>4.3 </td> <td>1.85 </td> <td>Q4'23 </td> <td>$363 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237505/intel-core-ultra-5-processor-115u-10m-cache-up-to-4-20-ghz.html">115U</a> </td> <td>4 (4) </td> <td>1.5 </td> <td>1.0 </td> <td>4.2 </td> <td>3.5 </td> <td>3 (48) </td> <td>1.8 </td> <td>10 MB </td> <td>Q4'23 </td> <td>unspecified </td></tr> <tr> <th colspan="19">Ultra low power (MTL-U9) </th></tr> <tr> <td>Core Ultra 7 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237508/intel-core-ultra-7-processor-164u-12m-cache-up-to-4-80-ghz.html">164U</a></abbr> </td> <td rowspan="2">2 (4) </td> <td rowspan="2">8 (8) </td> <td rowspan="2">2 (2) </td> <td>1.1 </td> <td>0.7 </td> <td rowspan="2">0.4 </td> <td>4.8 </td> <td>3.8 </td> <td rowspan="2">2.1 </td> <td rowspan="2">4 (64) </td> <td>1.8 </td> <td rowspan="2">12 MB </td> <td rowspan="2">9 W </td> <td rowspan="2">9–15 W </td> <td rowspan="2">30 W </td> <td>Q4'23 </td> <td>$448 </td></tr> <tr> <td>Core Ultra 5 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/237507/intel-core-ultra-5-processor-134u-12m-cache-up-to-4-40-ghz.html">134U</a></abbr> </td> <td>0.7 </td> <td>0.5 </td> <td>4.4 </td> <td>3.6 </td> <td>1.75 </td> <td>Q4'23 </td> <td>$332 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-RCP-136"><span class="mw-cite-backlink"><b><a href="#cite_ref-RCP_136-0">^</a></b></span> <span class="reference-text">Price is Recommended Customer Price (RCP) at launch. RCP is the trade price that processors are sold by Intel to retailers and OEMs. Actual MSRP for consumers is higher</span> </li> </ol></div></div> <div class="mw-heading mw-heading6"><h6 id="Processors_for_Internet_of_Things_(IoT)_devices_and_embedded_systems_(Meteor_Lake-PS)"><span id="Processors_for_Internet_of_Things_.28IoT.29_devices_and_embedded_systems_.28Meteor_Lake-PS.29"></span>Processors for Internet of Things (IoT) devices and embedded systems (Meteor Lake-PS)</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=64" title="Edit section: Processors for Internet of Things (IoT) devices and embedded systems (Meteor Lake-PS)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>High-power</b> </p><p>155HL and 165HL support P-core Turbo Boost 3.0 running at the same frequency as Turbo Boost 2.0. </p> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="3"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="3">Base <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a><br />(GHz) </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a><br />(GHz) </th> <th colspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a> graphics </th> <th rowspan="2"><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">Smart</a><br /><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">cache</a> </th> <th colspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price<br />(USD)<sup id="cite_ref-RCP_137-0" class="reference"><a href="#cite_note-RCP-137"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th>Xe-cores<br />(<abbr title="Xe Vector Engines">XVEs</abbr>) </th> <th>Max. freq.<br />(GHz) </th> <th>Base </th> <th><abbr title="Configurable TDP">cTDP</abbr> </th> <th>Turbo </th></tr> <tr> <td rowspan="2">Core Ultra 7 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239788/intel-core-ultra-7-processor-165hl-24m-cache-up-to-5-00-ghz.html">165HL</a></abbr> </td> <td rowspan="2">6 (12) </td> <td rowspan="4">8 (8) </td> <td rowspan="4">2 (2) </td> <td rowspan="2">1.4 </td> <td rowspan="2">0.9 </td> <td rowspan="4">0.7 </td> <td>5.0 </td> <td rowspan="2">3.8 </td> <td rowspan="4">2.5 </td> <td rowspan="3">8 (128) </td> <td>2.3 </td> <td rowspan="2">24 MB </td> <td rowspan="4">45 W </td> <td rowspan="4">20–65 W </td> <td rowspan="4">115 W </td> <td>Q2'24 </td> <td>$459 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239786/intel-core-ultra-7-processor-155hl-24m-cache-up-to-4-80-ghz.html">155HL</a> </td> <td>4.8 </td> <td>2.25 </td> <td>Q2'24 </td> <td>$438 </td></tr> <tr> <td rowspan="2">Core Ultra 5 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239784/intel-core-ultra-5-processor-135hl-18m-cache-up-to-4-60-ghz.html">135HL</a></abbr> </td> <td rowspan="2">4 (8) </td> <td>1.7 </td> <td>1.2 </td> <td>4.6 </td> <td rowspan="2">3.6 </td> <td rowspan="2">2.2 </td> <td rowspan="2">18 MB </td> <td>Q2'24 </td> <td>$341 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239782/intel-core-ultra-5-processor-125hl-18m-cache-up-to-4-50-ghz.html">125HL</a> </td> <td>1.2 </td> <td>0.7 </td> <td>4.5 </td> <td>7 (112) </td> <td>Q2'24 </td> <td>$325 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-RCP-137"><span class="mw-cite-backlink"><b><a href="#cite_ref-RCP_137-0">^</a></b></span> <span class="reference-text">Price is Recommended Customer Price (RCP) at launch. RCP is the trade price that processors are sold by Intel to retailers and OEMs. Actual MSRP for consumers is higher</span> </li> </ol></div></div> <p><b>Low-power</b> </p><p>The integrated GPU is branded as "Intel Graphics" but still use the same GPU microarchitecture as "Intel Arc Graphics" on the high-power models. </p> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th rowspan="2">Processor<br />branding </th> <th rowspan="2">Model </th> <th colspan="3"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="3">Base <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a><br />(GHz) </th> <th colspan="3"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo Boost</a><br />(GHz) </th> <th colspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Intel Graphics</a> </th> <th rowspan="2"><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">Smart</a><br /><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">cache</a> </th> <th colspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2">Price<br />(USD)<sup id="cite_ref-RCP_138-0" class="reference"><a href="#cite_note-RCP-138"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th><abbr title="Performance-">P</abbr> </th> <th><abbr title="Efficient-">E</abbr> </th> <th><abbr title="Low Power Efficient-">LP-E</abbr> </th> <th>Xe-cores<br />(<abbr title="Xe Vector Engines">XVEs</abbr>) </th> <th>Max. freq.<br />(GHz) </th> <th>Base </th> <th><abbr title="Configurable TDP">cTDP</abbr> </th> <th>Turbo </th></tr> <tr> <td rowspan="2">Core Ultra 7 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239802/intel-core-ultra-7-processor-165ul-12m-cache-up-to-4-90-ghz.html">165UL</a></abbr> </td> <td rowspan="5">2 (4) </td> <td rowspan="4">8 (8) </td> <td rowspan="5">2 (2) </td> <td rowspan="2">1.7 </td> <td rowspan="2">1.2 </td> <td rowspan="5">0.7 </td> <td>4.9 </td> <td rowspan="2">3.8 </td> <td rowspan="5">2.1 </td> <td rowspan="4">4 (64) </td> <td>2.0 </td> <td rowspan="4">12 MB </td> <td rowspan="5">15 W </td> <td rowspan="5">12–28 W </td> <td rowspan="5">57 W </td> <td>Q2'24 </td> <td>$447 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239787/intel-core-ultra-7-processor-155ul-12m-cache-up-to-4-80-ghz.html">155UL</a> </td> <td>4.8 </td> <td>1.95 </td> <td>Q2'24 </td> <td>$426 </td></tr> <tr> <td rowspan="2">Core Ultra 5 </td> <td><abbr title="vPro Enterprise"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239785/intel-core-ultra-5-processor-135ul-12m-cache-up-to-4-40-ghz.html">135UL</a></abbr> </td> <td>1.6 </td> <td>1.1 </td> <td>4.4 </td> <td rowspan="2">3.6 </td> <td>1.9 </td> <td>Q2'24 </td> <td>$331 </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239783/intel-core-ultra-5-processor-125ul-12m-cache-up-to-4-30-ghz.html">125UL</a> </td> <td>1.3 </td> <td>0.8 </td> <td>4.3 </td> <td>1.85 </td> <td>Q2'24 </td> <td>$309 </td></tr> <tr> <td>Core Ultra 3 </td> <td><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/239781/intel-core-ultra-3-processor-105ul-10m-cache-up-to-4-20-ghz.html">105UL</a> </td> <td>4 (4) </td> <td>1.5 </td> <td>1.0 </td> <td>4.2 </td> <td>3.5 </td> <td>3 (48) </td> <td>1.8 </td> <td>10 MB </td> <td>Q2'24 </td> <td>$295 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-RCP-138"><span class="mw-cite-backlink"><b><a href="#cite_ref-RCP_138-0">^</a></b></span> <span class="reference-text">Price is Recommended Customer Price (RCP) at launch. RCP is the trade price that processors are sold by Intel to retailers and OEMs. Actual MSRP for consumers is higher</span> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Series_2">Series 2</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=65" title="Edit section: Series 2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2024</span>)</i></span></div></td></tr></tbody></table> <div class="mw-heading mw-heading5"><h5 id="Lunar_Lake">Lunar Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=66" title="Edit section: Lunar Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Lunar_Lake" title="Lunar Lake">Lunar Lake</a></div> <div class="mw-heading mw-heading6"><h6 id="Mobile_processors_2">Mobile processors</h6><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=67" title="Edit section: Mobile processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align:center; white-space:nowrap; font-size:95%"> <tbody><tr> <th rowspan="3">Branding </th> <th rowspan="3">SKU </th> <th colspan="2" rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <br /> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="3"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (GHz) </th> <th colspan="2" rowspan="2"><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a> Graphics </th> <th rowspan="3"><a href="/wiki/AI_accelerator" title="AI accelerator">NPU</a> <br /> (TOPS) </th> <th rowspan="3"><a href="/wiki/Smart_cache" class="mw-redirect" title="Smart cache">Smart <br /> cache</a><sup id="cite_ref-140" class="reference"><a href="#cite_note-140"><span class="cite-bracket">[</span>i<span class="cite-bracket">]</span></a></sup> </th> <th rowspan="3">RAM </th> <th colspan="3" rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2">Base </th> <th colspan="2"><a href="/wiki/Intel_Turbo_Boost" title="Intel Turbo Boost">Turbo</a> </th></tr> <tr> <th style="width:3em;"><abbr title="Performance">P</abbr> </th> <th style="width:3em;"><abbr title="Low Power Efficient">LP-E</abbr> </th> <th style="width:3em;"><abbr title="Performance">P</abbr> </th> <th style="width:3em;"><abbr title="Low Power Efficient">LP-E</abbr> </th> <th>X<sup>e</sup> cores<br />(<abbr title="X<sup>e</sup> Vector Engines">XVEs</abbr>) </th> <th>Max. freq.<br />(GHz) </th> <th>Base </th> <th>Turbo </th> <th><abbr title="Configurable TDP">cTDP</abbr> </th></tr> <tr> <th>Core Ultra 9 </th> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240961/intel-core-ultra-9-processor-288v-12m-cache-up-to-5-10-ghz.html">288V</a> </th> <td rowspan="9">4 (4) </td> <td rowspan="9">4 (4) </td> <td>3.3 </td> <td>5.1 </td> <td rowspan="5">3.7 </td> <td rowspan="5">8 (64) </td> <td>2.05 </td> <td rowspan="3">48 </td> <td rowspan="5">12 MB </td> <td>32 GB </td> <td>30 W </td> <td rowspan="9">37 W </td> <td>17-37 W </td> <td rowspan="9"><span data-sort-value="000000002024-09-24-0000" style="white-space:nowrap">Sep 24, 2024</span> </td></tr> <tr> <th rowspan="4">Core Ultra 7 </th> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240958/intel-core-ultra-7-processor-268v-12m-cache-up-to-5-00-ghz.html">268V</a> </th> <td rowspan="4">2.2 </td> <td rowspan="2">5.0 </td> <td rowspan="2">2.0 </td> <td>32 GB </td> <td rowspan="8">17 W </td> <td rowspan="8">8-37 W </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240956/intel-core-ultra-7-processor-266v-12m-cache-up-to-5-00-ghz.html">266V</a> </th> <td>16 GB </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240957/intel-core-ultra-7-processor-258v-12m-cache-up-to-4-80-ghz.html">258V</a> </th> <td rowspan="2">4.8 </td> <td rowspan="2">1.95 </td> <td rowspan="2">47 </td> <td>32 GB </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240954/intel-core-ultra-7-processor-256v-12m-cache-up-to-4-80-ghz.html">256V</a> </th> <td>16 GB </td></tr> <tr> <th rowspan="4">Core Ultra 5 </th> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240951/intel-core-ultra-5-processor-238v-8m-cache-up-to-4-70-ghz.html">238V</a> </th> <td rowspan="4">2.1 </td> <td rowspan="2">4.7 </td> <td rowspan="4">3.5 </td> <td rowspan="4">7 (56) </td> <td rowspan="4">1.85 </td> <td rowspan="4">40 </td> <td rowspan="4">8 MB </td> <td>32 GB </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240959/intel-core-ultra-5-processor-236v-8m-cache-up-to-4-70-ghz.html">236V</a> </th> <td>16 GB </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240955/intel-core-ultra-5-processor-228v-8m-cache-up-to-4-50-ghz.html">228V</a> </th> <td rowspan="2">4.5 </td> <td>32 GB </td></tr> <tr> <th><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/240960/intel-core-ultra-5-processor-226v-8m-cache-up-to-4-50-ghz.html">226V</a> </th> <td>16 GB </td></tr> </tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-140"><span class="mw-cite-backlink"><b><a href="#cite_ref-140">^</a></b></span> <span class="reference-text">Only the P-cores can access this L3 cache<sup id="cite_ref-139" class="reference"><a href="#cite_note-139"><span class="cite-bracket">[</span>132<span class="cite-bracket">]</span></a></sup></span> </li> </ol></div></div> <div class="mw-heading mw-heading5"><h5 id="Arrow_Lake">Arrow Lake</h5><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=68" title="Edit section: Arrow Lake"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Arrow_Lake_(microprocessor)" title="Arrow Lake (microprocessor)">Arrow Lake (microprocessor)</a></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Empty_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span"><b>This section is empty.</b> You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">October 2024</span>)</i></span></div></td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="Reception">Reception</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=69" title="Edit section: Reception"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Expand_section plainlinks metadata ambox mbox-small-left ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><span typeof="mw:File"><a href="/wiki/File:Wiki_letter_w_cropped.svg" class="mw-file-description"><img alt="[icon]" src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/20px-Wiki_letter_w_cropped.svg.png" decoding="async" width="20" height="14" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/30px-Wiki_letter_w_cropped.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1c/Wiki_letter_w_cropped.svg/40px-Wiki_letter_w_cropped.svg.png 2x" data-file-width="44" data-file-height="31" /></a></span></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs expansion</b>. You can help by <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&action=edit&section=">adding to it</a>. <span class="date-container"><i>(<span class="date">January 2023</span>)</i></span></div></td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Speculative_execution_CPU_vulnerabilities">Speculative execution CPU vulnerabilities</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=70" title="Edit section: Speculative execution CPU vulnerabilities"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="excerpt-block"><style data-mw-deduplicate="TemplateStyles:r1066933788">.mw-parser-output .excerpt-hat .mw-editsection-like{font-style:normal}</style><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable dablink excerpt-hat selfref">This section is an excerpt from <a href="/wiki/Transient_execution_CPU_vulnerability" title="Transient execution CPU vulnerability">Transient execution CPU vulnerability</a>.<span class="mw-editsection-like plainlinks"><span class="mw-editsection-bracket">[</span><a class="external text" href="https://en.wikipedia.org/w/index.php?title=Transient_execution_CPU_vulnerability&action=edit">edit</a><span class="mw-editsection-bracket">]</span></span></div><div class="excerpt"> <a href="/wiki/Transient_execution_CPU_vulnerability" title="Transient execution CPU vulnerability">Transient execution CPU vulnerabilities</a> are <a href="/wiki/Vulnerability_(computing)" class="mw-redirect" title="Vulnerability (computing)">vulnerabilities</a> in which instructions, most often optimized using <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>, are executed temporarily by a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a>, without committing their results due to a misprediction or error, resulting in leaking secret data to an unauthorized party. The archetype is <a href="/wiki/Spectre_(security_vulnerability)" title="Spectre (security vulnerability)">Spectre</a>, and transient execution attacks like Spectre belong to the cache-attack category, one of several categories of <a href="/wiki/Side-channel_attacks" class="mw-redirect" title="Side-channel attacks">side-channel attacks</a>. Since January 2018 many different cache-attack vulnerabilities have been identified.</div></div> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=71" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Intel Core (microarchitecture)</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">List of Intel graphics processing units</a></li> <li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">List of Intel processors</a></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">List of Intel Core processors</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">List of Intel chipsets</a></li> <li><a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></li> <li><a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen (microarchitecture)</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=72" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-Intel_drops_I_processor-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-Intel_drops_I_processor_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Intel_drops_I_processor_1-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFCao2023" class="citation web cs1">Cao, Peter (June 15, 2023). <a rel="nofollow" class="external text" href="https://www.engadget.com/intel-drops-i-processor-branding-after-15-years-introduces-ultra-for-higher-end-chips-130100277.html">"Intel drops 'i' processor branding after 15 years, introduces 'Ultra' for higher-end chips"</a>. <i>Engadget</i><span class="reference-accessdate">. Retrieved <span class="nowrap">June 17,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Engadget&rft.atitle=Intel+drops+%27i%27+processor+branding+after+15+years%2C+introduces+%27Ultra%27+for+higher-end+chips&rft.date=2023-06-15&rft.aulast=Cao&rft.aufirst=Peter&rft_id=https%3A%2F%2Fwww.engadget.com%2Fintel-drops-i-processor-branding-after-15-years-introduces-ultra-for-higher-end-chips-130100277.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Bonshor-2023a-Intel-to-Launch-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-Bonshor-2023a-Intel-to-Launch_2-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBonshor2023" class="citation web cs1">Bonshor, Gavin (June 15, 2023). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/18911/intel-new-core-branding-for-meteor-lake-no-i-new-ultra-tier">"Intel To Launch New Core Processor Branding for Meteor Lake: Drop the i, Add Ultra Tier"</a>. <i>AnandTech</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240405141541/https://www.anandtech.com/show/18911/intel-new-core-branding-for-meteor-lake-no-i-new-ultra-tier">Archived</a> from the original on April 5, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">April 5,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Intel+To+Launch+New+Core+Processor+Branding+for+Meteor+Lake%3A+Drop+the+i%2C+Add+Ultra+Tier&rft.date=2023-06-15&rft.aulast=Bonshor&rft.aufirst=Gavin&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F18911%2Fintel-new-core-branding-for-meteor-lake-no-i-new-ultra-tier&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Robinson-2023-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-Robinson-2023_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRobinson2023" class="citation web cs1">Robinson, Cliff (June 15, 2023). <a rel="nofollow" class="external text" href="https://www.servethehome.com/intel-overhauls-core-branding-with-meteor-lake/">"Intel Overhauls Core Branding with Meteor Lake"</a>. <i>ServeTheHome</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240405141541/https://www.servethehome.com/intel-overhauls-core-branding-with-meteor-lake/">Archived</a> from the original on April 5, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">April 5,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ServeTheHome&rft.atitle=Intel+Overhauls+Core+Branding+with+Meteor+Lake&rft.date=2023-06-15&rft.aulast=Robinson&rft.aufirst=Cliff&rft_id=https%3A%2F%2Fwww.servethehome.com%2Fintel-overhauls-core-branding-with-meteor-lake%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-auto2-5"><span class="mw-cite-backlink">^ <a href="#cite_ref-auto2_5-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-auto2_5-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-auto2_5-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation web cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14664/testing-intel-ice-lake-10nm">"The Ice Lake Benchmark Preview: Inside Intel's 10nm"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=The+Ice+Lake+Benchmark+Preview%3A+Inside+Intel%27s+10nm&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14664%2Ftesting-intel-ice-lake-10nm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.hardware.fr/articles/733-4/hierarchie-caches.html">"Hiérarchie des caches - L'architecture Intel Nehalem - HardWare.fr"</a>. <i>www.hardware.fr</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.hardware.fr&rft.atitle=Hi%C3%A9rarchie+des+caches+-+L%27architecture+Intel+Nehalem+-+HardWare.fr&rft_id=https%3A%2F%2Fwww.hardware.fr%2Farticles%2F733-4%2Fhierarchie-caches.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKanter" class="citation web cs1">Kanter, David. <a rel="nofollow" class="external text" href="https://www.realworldtech.com/sandy-bridge/3/">"Intel's Sandy Bridge Microarchitecture"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">October 24,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%27s+Sandy+Bridge+Microarchitecture&rft.aulast=Kanter&rft.aufirst=David&rft_id=https%3A%2F%2Fwww.realworldtech.com%2Fsandy-bridge%2F3%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/intel/microarchitectures/willow_cove">"Willow Cove - Microarchitectures - Intel - WikiChip"</a>. <i>en.wikichip.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=en.wikichip.org&rft.atitle=Willow+Cove+-+Microarchitectures+-+Intel+-+WikiChip&rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2Fintel%2Fmicroarchitectures%2Fwillow_cove&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutressFrumusanu" class="citation web cs1">Cutress, Ian; Frumusanu, Andrei. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen">"Intel's Tiger Lake 11th Gen Core i7-1185G7 Review and Deep Dive: Baskin' for the Exotic"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 8,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel%27s+Tiger+Lake+11th+Gen+Core+i7-1185G7+Review+and+Deep+Dive%3A+Baskin%27+for+the+Exotic&rft.aulast=Cutress&rft.aufirst=Ian&rft.au=Frumusanu%2C+Andrei&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16084%2Fintel-tiger-lake-review-deep-dive-core-11th-gen&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Core_i7/Intel-Core%20i7-5775C.html">"Intel Core i7-5775C - CM8065802483301 / BX80658I75775C"</a>. <i>www.cpu-world.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 6,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.cpu-world.com&rft.atitle=Intel+Core+i7-5775C+-+CM8065802483301+%2F+BX80658I75775C&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FCore_i7%2FIntel-Core%2520i7-5775C.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-12"><span class="mw-cite-backlink"><b><a href="#cite_ref-12">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.hardware.fr/articles/733-6/noyau-suite.html">"Noyau (suite) - L'architecture Intel Nehalem - HardWare.fr"</a>. <i>www.hardware.fr</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.hardware.fr&rft.atitle=Noyau+%28suite%29+-+L%27architecture+Intel+Nehalem+-+HardWare.fr&rft_id=https%3A%2F%2Fwww.hardware.fr%2Farticles%2F733-6%2Fnoyau-suite.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-13"><span class="mw-cite-backlink"><b><a href="#cite_ref-13">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/File:broadwell_buffer_window.png">"File:broadwell buffer window.png - WikiChip"</a>. <i>en.wikichip.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=en.wikichip.org&rft.atitle=File%3Abroadwell+buffer+window.png+-+WikiChip&rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2FFile%3Abroadwell_buffer_window.png&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-14"><span class="mw-cite-backlink"><b><a href="#cite_ref-14">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/File:sunny_cove_buffer_capacities.png">"File:sunny cove buffer capacities.png - WikiChip"</a>. <i>en.wikichip.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 23,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=en.wikichip.org&rft.atitle=File%3Asunny+cove+buffer+capacities.png+-+WikiChip&rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2FFile%3Asunny_cove_buffer_capacities.png&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-chipsandchhese-15"><span class="mw-cite-backlink">^ <a href="#cite_ref-chipsandchhese_15-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-chipsandchhese_15-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-chipsandchhese_15-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-chipsandchhese_15-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-chipsandchhese_15-4"><sup><i><b>e</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://chipsandcheese.com/2021/12/02/popping-the-hood-on-golden-cove/">"Popping the Hood on Golden Cove"</a>. <i>chipsandcheese.com</i>. December 2, 2021<span class="reference-accessdate">. Retrieved <span class="nowrap">April 12,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=chipsandcheese.com&rft.atitle=Popping+the+Hood+on+Golden+Cove&rft.date=2021-12-02&rft_id=https%3A%2F%2Fchipsandcheese.com%2F2021%2F12%2F02%2Fpopping-the-hood-on-golden-cove%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-16"><span class="mw-cite-backlink"><b><a href="#cite_ref-16">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/intel/microarchitectures/sunny_cove">"Sunny Cove - Microarchitectures - Intel - WikiChip"</a>. <i>en.wikichip.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 4,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=en.wikichip.org&rft.atitle=Sunny+Cove+-+Microarchitectures+-+Intel+-+WikiChip&rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2Fintel%2Fmicroarchitectures%2Fsunny_cove&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-18"><span class="mw-cite-backlink"><b><a href="#cite_ref-18">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKanter" class="citation web cs1">Kanter, David. <a rel="nofollow" class="external text" href="https://www.realworldtech.com/sandy-bridge/6/">"Intel's Sandy Bridge Microarchitecture"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">November 9,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%27s+Sandy+Bridge+Microarchitecture&rft.aulast=Kanter&rft.aufirst=David&rft_id=https%3A%2F%2Fwww.realworldtech.com%2Fsandy-bridge%2F6%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-auto1-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-auto1_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-auto1_19-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShimpi" class="citation web cs1">Shimpi, Anand Lal. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/6355/intels-haswell-architecture">"Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 9,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel%27s+Haswell+Architecture+Analyzed%3A+Building+a+New+PC+and+a+New+Intel&rft.aulast=Shimpi&rft.aufirst=Anand+Lal&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F6355%2Fintels-haswell-architecture&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-20"><span class="mw-cite-backlink"><b><a href="#cite_ref-20">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation web cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14514/examining-intels-ice-lake-microarchitecture-and-sunny-cove">"Examining Intel's Ice Lake Processors: Taking a Bite of the Sunny Cove Microarchitecture"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 9,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Examining+Intel%27s+Ice+Lake+Processors%3A+Taking+a+Bite+of+the+Sunny+Cove+Microarchitecture&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F14514%2Fexamining-intels-ice-lake-microarchitecture-and-sunny-cove&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2014/09/intels-launches-three-core-m-cpus-promises-more-broadwell-early-2015/">"Intel launches three Core M CPUs, promises more Broadwell "early 2015"<span class="cs1-kern-right"></span>"</a>. <i>Ars Technica</i>. September 5, 2014. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150105212016/http://arstechnica.com/gadgets/2014/09/intels-launches-three-core-m-cpus-promises-more-broadwell-early-2015/">Archived</a> from the original on January 5, 2015.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Ars+Technica&rft.atitle=Intel+launches+three+Core+M+CPUs%2C+promises+more+Broadwell+%22early+2015%22&rft.date=2014-09-05&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2014%2F09%2Fintels-launches-three-core-m-cpus-promises-more-broadwell-early-2015%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070913123702/http://www.tgdaily.com/content/view/33752/135/">"Intel already phasing out first quad-core CPU"</a>. TG Daily. Archived from <a rel="nofollow" class="external text" href="http://www.tgdaily.com/content/view/33752/135/">the original</a> on September 13, 2007<span class="reference-accessdate">. Retrieved <span class="nowrap">September 7,</span> 2007</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+already+phasing+out+first+quad-core+CPU&rft.pub=TG+Daily&rft_id=http%3A%2F%2Fwww.tgdaily.com%2Fcontent%2Fview%2F33752%2F135%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-23"><span class="mw-cite-backlink"><b><a href="#cite_ref-23">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20071102195746/http://www.tgdaily.com/content/view/34115/122/">"Intel to discontinue older Centrino CPUs in Q1 08"</a>. TG Daily. Archived from <a rel="nofollow" class="external text" href="http://www.tgdaily.com/content/view/34115/122/">the original</a> on November 2, 2007<span class="reference-accessdate">. Retrieved <span class="nowrap">October 1,</span> 2007</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+to+discontinue+older+Centrino+CPUs+in+Q1+08&rft.pub=TG+Daily&rft_id=http%3A%2F%2Fwww.tgdaily.com%2Fcontent%2Fview%2F34115%2F122%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-24"><span class="mw-cite-backlink"><b><a href="#cite_ref-24">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100419025302/http://www.intel.com/support/processors/mobile/coresolo/">"Support for the Intel Core Solo processor"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/coresolo/">the original</a> on April 19, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Support+for+the+Intel+Core+Solo+processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fmobile%2Fcoresolo%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-25"><span class="mw-cite-backlink"><b><a href="#cite_ref-25">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100417062512/http://www.intel.com/support/processors/mobile/coreduo/">"Support for the Intel Core Duo Processor"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/mobile/coreduo/">the original</a> on April 17, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Support+for+the+Intel+Core+Duo+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fmobile%2Fcoreduo%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-26"><span class="mw-cite-backlink"><b><a href="#cite_ref-26">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090612020454/http://www.intel.com/technology/architecture-silicon/core/">"Intel Microarchitecture"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/technology/architecture-silicon/core/">the original</a> on June 12, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Microarchitecture&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Ftechnology%2Farchitecture-silicon%2Fcore%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110926153231/http://www.intel.com/products/processor/core2solo/">"Intel Core2 Solo Mobile Processor –  Overview"</a>. Intel. Archived from the original on September 26, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Solo+Mobile+Processor+%26ndash%3B%26%2332%3B+Overview&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2solo%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-28"><span class="mw-cite-backlink"><b><a href="#cite_ref-28">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110107025301/http://www.intel.com/products/processor/core2duo/">"Intel Core2 Duo Processor: Upgrade Today"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/products/processor/core2duo/">the original</a> on January 7, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Duo+Processor%3A+Upgrade+Today&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2duo%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090403205413/http://www.intel.com/products/processor/core2duo/mobile/">"Intel Core2 Duo Mobile Processor"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/products/processor/core2duo/mobile/">the original</a> on April 3, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Duo+Mobile+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2duo%2Fmobile%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110306110804/http://www.intel.com/products/processor/core2quad/">"Intel Core2 Quad Processor Overview"</a>. Intel. Archived from the original on March 6, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Quad+Processor+Overview&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2quad%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150506065928/http://www.intel.com/products/processor/core2quad/mobile/">"Intel Core2 Quad Mobile Processors –  Overview"</a>. Intel. Archived from the original on May 6, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Quad+Mobile+Processors+%26ndash%3B%26%2332%3B+Overview&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2quad%2Fmobile%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100316030917/http://www.intel.com/support/processors/core2extreme/">"Support for the Intel Core2 Extreme Processor"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/core2extreme/">the original</a> on March 16, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Support+for+the+Intel+Core2+Extreme+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fcore2extreme%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-33">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110221204224/http://www.intel.com/products/processor/core2xe/">"Intel Core2 Extreme Processor"</a>. Intel. Archived from the original on February 21, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core2+Extreme+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fproducts%2Fprocessor%2Fcore2xe%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span><span class="cs1-maint citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_web" title="Template:Cite web">cite web</a>}}</code>: CS1 maint: unfit URL (<a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">link</a>)</span></span> </li> <li id="cite_note-34"><span class="mw-cite-backlink"><b><a href="#cite_ref-34">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100722163629/http://www.intel.com/technology/architecture-silicon/next-gen/">"Intel Microarchitecture Codenamed Nehalem"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/technology/architecture-silicon/next-gen/">the original</a> on July 22, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Microarchitecture+Codenamed+Nehalem&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Ftechnology%2Farchitecture-silicon%2Fnext-gen%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-35"><span class="mw-cite-backlink"><b><a href="#cite_ref-35">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20090205223024/http://download.intel.com/products/roadmap/roadmap.pdf">"Public Roadmap Desktop, Mobile & Data Center"</a> <span class="cs1-format">(PDF)</span>. Intel. Archived from <a rel="nofollow" class="external text" href="http://download.intel.com/products/roadmap/roadmap.pdf">the original</a> <span class="cs1-format">(PDF)</span> on February 5, 2009<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Public+Roadmap+Desktop%2C+Mobile+%26+Data+Center&rft.pub=Intel&rft_id=http%3A%2F%2Fdownload.intel.com%2Fproducts%2Froadmap%2Froadmap.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-36"><span class="mw-cite-backlink"><b><a href="#cite_ref-36">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110415165433/http://www.intel.com/consumer/products/processors/ratings.htm">"Intel Processor Ratings"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/consumer/products/processors/ratings.htm">the original</a> on April 15, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">July 21,</span> 2011</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Processor+Ratings&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fconsumer%2Fproducts%2Fprocessors%2Fratings.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110101190307/http://www.intel.com/consumer/products/processors/ratings.htm">"Processor Ratings"</a>. Intel. July 9, 2010. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/consumer/products/processors/ratings.htm">the original</a> on January 1, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Processor+Ratings&rft.pub=Intel&rft.date=2010-07-09&rft_id=http%3A%2F%2Fwww.intel.com%2Fconsumer%2Fproducts%2Fprocessors%2Fratings.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-38">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585">"Intel Quietly Announces Core i5 and Core i3 Branding"</a>. AnandTech. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100323175932/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3585">Archived</a> from the original on March 23, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Quietly+Announces+Core+i5+and+Core+i3+Branding&rft.pub=AnandTech&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fcpuchipsets%2Fshowdoc.aspx%3Fi%3D3585&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-39"><span class="mw-cite-backlink"><b><a href="#cite_ref-39">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110907040112/http://apcmag.com/intel-confirms-core-i3-as-entry-level-nehalem-chip.htm">"Intel confirms Core i3 as 'entry-level' Nehalem chip"</a>. Apcmag.com. September 14, 2009. Archived from <a rel="nofollow" class="external text" href="http://apcmag.com/intel-confirms-core-i3-as-entry-level-nehalem-chip.htm">the original</a> on September 7, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+confirms+Core+i3+as+%27entry-level%27+Nehalem+chip&rft.pub=Apcmag.com&rft.date=2009-09-14&rft_id=http%3A%2F%2Fapcmag.com%2Fintel-confirms-core-i3-as-entry-level-nehalem-chip.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-40"><span class="mw-cite-backlink"><b><a href="#cite_ref-40">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120112151345/http://hardware.slashdot.org/story/10/01/04/0754250/Core-i5-and-i3-CPUs-With-On-Chip-GPUs-Launched?art_pos=3">"Core i5 and i3 CPUs With On-Chip GPUs Launched"</a>. Hardware.slashdot.org. January 4, 2010. Archived from <a rel="nofollow" class="external text" href="http://hardware.slashdot.org/story/10/01/04/0754250/Core-i5-and-i3-CPUs-With-On-Chip-GPUs-Launched?art_pos=3">the original</a> on January 12, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Core+i5+and+i3+CPUs+With+On-Chip+GPUs+Launched&rft.pub=Hardware.slashdot.org&rft.date=2010-01-04&rft_id=http%3A%2F%2Fhardware.slashdot.org%2Fstory%2F10%2F01%2F04%2F0754250%2FCore-i5-and-i3-CPUs-With-On-Chip-GPUs-Launched%3Fart_pos%3D3&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/cpu/display/20090813091122_Intel_May_Unveil_Microprocessors_with_Integrated_Graphics_Cores_at_Consumer_Electronics_Show.html">"Intel May Unveil Microprocessors with Integrated Graphics Cores at Consumer Electronics Show"</a>. Xbitlabs.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101030120826/http://www.xbitlabs.com/news/cpu/display/20090813091122_Intel_May_Unveil_Microprocessors_with_Integrated_Graphics_Cores_at_Consumer_Electronics_Show.html">Archived</a> from the original on October 30, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+May+Unveil+Microprocessors+with+Integrated+Graphics+Cores+at+Consumer+Electronics+Show&rft.pub=Xbitlabs.com&rft_id=http%3A%2F%2Fwww.xbitlabs.com%2Fnews%2Fcpu%2Fdisplay%2F20090813091122_Intel_May_Unveil_Microprocessors_with_Integrated_Graphics_Cores_at_Consumer_Electronics_Show.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-42"><span class="mw-cite-backlink"><b><a href="#cite_ref-42">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.digitimes.com/news/a20091113PD209.html">"Intel to launch four Arrandale CPUs for mainstream notebooks in January 2010"</a>. Digitimes.com. November 13, 2009. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101207042202/http://www.digitimes.com/news/a20091113PD209.html">Archived</a> from the original on December 7, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+to+launch+four+Arrandale+CPUs+for+mainstream+notebooks+in+January+2010&rft.pub=Digitimes.com&rft.date=2009-11-13&rft_id=http%3A%2F%2Fwww.digitimes.com%2Fnews%2Fa20091113PD209.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-43"><span class="mw-cite-backlink"><b><a href="#cite_ref-43">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei3/sb/CS-031175.htm#?iid=subhdr+dnlds">"Intel Core i3 Desktop Processor — Frequently Asked Questions"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110925062014/http://www.intel.com/support/processors/corei3/sb/CS-031175.htm#?iid=subhdr+dnlds">Archived</a> from the original on September 25, 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+Core+i3+Desktop+Processor+%E2%80%94+Frequently+Asked+Questions&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fcorei3%2Fsb%2FCS-031175.htm%23%3Fiid%3Dsubhdr%2Bdnlds&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-44"><span class="mw-cite-backlink"><b><a href="#cite_ref-44">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170702070428/http://www.supermicro.com/support/faqs/faq.cfm?faq=10712">"FAQ Entry –  Online Support –  Support –  Super Micro Computer, Inc"</a>. <i>www.Supermicro.com</i>. Archived from <a rel="nofollow" class="external text" href="http://www.supermicro.com/support/faqs/faq.cfm?faq=10712">the original</a> on July 2, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">January 5,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.Supermicro.com&rft.atitle=FAQ+Entry+%26ndash%3B%26%2332%3B+Online+Support+%26ndash%3B%26%2332%3B+Support+%26ndash%3B%26%2332%3B+Super+Micro+Computer%2C+Inc.&rft_id=http%3A%2F%2Fwww.supermicro.com%2Fsupport%2Ffaqs%2Ffaq.cfm%3Ffaq%3D10712&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-45"><span class="mw-cite-backlink"><b><a href="#cite_ref-45">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120105202008/http://www.silentpcreview.com/forums/viewtopic.php?f=13&t=60512&start=60">"SPCR • View topic –  ECC Support (offshoot of Silent Server Build)"</a>. <i>silentpcreview.com</i>. Archived from <a rel="nofollow" class="external text" href="http://www.silentpcreview.com/forums/viewtopic.php?f=13&t=60512&start=60">the original</a> on January 5, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">September 26,</span> 2011</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=silentpcreview.com&rft.atitle=SPCR+%E2%80%A2+View+topic+%26ndash%3B%26%2332%3B+ECC+Support+%28offshoot+of+Silent+Server+Build%29&rft_id=http%3A%2F%2Fwww.silentpcreview.com%2Fforums%2Fviewtopic.php%3Ff%3D13%26t%3D60512%26start%3D60&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-46"><span class="mw-cite-backlink"><b><a href="#cite_ref-46">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.asus.com/Motherboards/Intel_Socket_1155/P8B_WS/#specifications">Asus P8B WS specification</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110925190151/http://www.asus.com/Motherboards/Intel_Socket_1155/P8B_WS">Archived</a> September 25, 2011, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a>: supports "ECC, Non-ECC, un-buffered Memory", but "Non-ECC, un-buffered memory only support for client OS (Windows 7, Vista and XP)."</span> </li> <li id="cite_note-47"><span class="mw-cite-backlink"><b><a href="#cite_ref-47">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20100411220631/http://www.intel.com/support/processors/corei5/">"Support for the Intel Core i5 Processor"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei5/">the original</a> on April 11, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Support+for+the+Intel+Core+i5+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fcorei5%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-48"><span class="mw-cite-backlink"><b><a href="#cite_ref-48">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAnand_Lal_Shimpi" class="citation cs2">Anand Lal Shimpi, <a rel="nofollow" class="external text" href="http://anandtech.com/cpuchipsets/showdoc.aspx?i=3634"><i>Intel's Core i7 870 & i5 750, Lynnfield: Harder, Better, Faster Stronger</i></a>, anandtech.com, <a rel="nofollow" class="external text" href="http://archive.wikiwix.com/cache/20110722084232/http://anandtech.com/cpuchipsets/showdoc.aspx?i=3634">archived</a> from the original on July 22, 2011</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Intel%27s+Core+i7+870+%26+i5+750%2C+Lynnfield%3A+Harder%2C+Better%2C+Faster+Stronger&rft.pub=anandtech.com&rft.au=Anand+Lal+Shimpi&rft_id=http%3A%2F%2Fanandtech.com%2Fcpuchipsets%2Fshowdoc.aspx%3Fi%3D3634&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-49"><span class="mw-cite-backlink"><b><a href="#cite_ref-49">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.digitimes.com/news/a20091113PD209.html">"Login to Digitimes archive & research"</a>. <i>www.digitimes.com</i>. November 13, 2009. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160320180835/http://www.digitimes.com/news/a20091113PD209.html">Archived</a> from the original on March 20, 2016<span class="reference-accessdate">. Retrieved <span class="nowrap">May 7,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.digitimes.com&rft.atitle=Login+to+Digitimes+archive+%26+research&rft.date=2009-11-13&rft_id=http%3A%2F%2Fwww.digitimes.com%2Fnews%2Fa20091113PD209.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-50"><span class="mw-cite-backlink"><b><a href="#cite_ref-50">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20111009175145/http://publish.it168.com/2009/0810/20090810015301.shtml">"Intel 奔腾双核 E5300(盒) 资讯-CPU 资讯-新奔腾同现身多款Core i5、i3正式确认-IT168 diy硬件"</a>. <i>it168.com</i>. Archived from <a rel="nofollow" class="external text" href="http://publish.it168.com/2009/0810/20090810015301.shtml">the original</a> on October 9, 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=it168.com&rft.atitle=Intel+%E5%A5%94%E8%85%BE%E5%8F%8C%E6%A0%B8+E5300%28%E7%9B%92%29+%E8%B5%84%E8%AE%AF-CPU+%E8%B5%84%E8%AE%AF-%E6%96%B0%E5%A5%94%E8%85%BE%E5%90%8C%E7%8E%B0%E8%BA%AB+%E5%A4%9A%E6%AC%BECore+i5%E3%80%81i3%E6%AD%A3%E5%BC%8F%E7%A1%AE%E8%AE%A4-IT168+diy%E7%A1%AC%E4%BB%B6&rft_id=http%3A%2F%2Fpublish.it168.com%2F2009%2F0810%2F20090810015301.shtml&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-51"><span class="mw-cite-backlink"><b><a href="#cite_ref-51">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/support/processors/corei5/sb/CS-032468.htm">"Intel Core i5 Desktop Processor — Integration, Compatibility, and Memory FAQ"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120211075531/http://www.intel.com/support/processors/corei5/sb/CS-032468.htm">Archived</a> from the original on February 11, 2012.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+Core+i5+Desktop+Processor+%E2%80%94+Integration%2C+Compatibility%2C+and+Memory+FAQ&rft_id=http%3A%2F%2Fwww.intel.com%2Fsupport%2Fprocessors%2Fcorei5%2Fsb%2FCS-032468.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-52"><span class="mw-cite-backlink"><b><a href="#cite_ref-52">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/CPUs/Core_i5/Intel-Core%20i5%20Mobile%20I5-430UM%20CN80617006042AE.html">"Intel Core i5-430UM Mobile processor –  CN80617006042AE"</a>. <i>cpu-world.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110812033407/http://www.cpu-world.com/CPUs/Core_i5/Intel-Core%20i5%20Mobile%20I5-430UM%20CN80617006042AE.html">Archived</a> from the original on August 12, 2011.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=cpu-world.com&rft.atitle=Intel+Core+i5-430UM+Mobile+processor+%26ndash%3B%26%2332%3B+CN80617006042AE&rft_id=http%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FCore_i5%2FIntel-Core%2520i5%2520Mobile%2520I5-430UM%2520CN80617006042AE.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-53"><span class="mw-cite-backlink"><b><a href="#cite_ref-53">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.intel.com/p/en_US/support/highlights/processors/corei7">"Support for the Intel Core i7 Processor"</a>. Intel. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101129064426/http://www.intel.com/p/en_US/support/highlights/processors/corei7">Archived</a> from the original on November 29, 2010<span class="reference-accessdate">. Retrieved <span class="nowrap">December 13,</span> 2010</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Support+for+the+Intel+Core+i7+Processor&rft.pub=Intel&rft_id=http%3A%2F%2Fwww.intel.com%2Fp%2Fen_US%2Fsupport%2Fhighlights%2Fprocessors%2Fcorei7&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-54"><span class="mw-cite-backlink"><b><a href="#cite_ref-54">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFModine2008" class="citation web cs1">Modine, Austin (November 18, 2008). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2008/11/18/intel_core_i7_launch_event/">"Intel celebrates Core i7 launch with Dell and Gateway"</a>. The Register. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20081220105745/http://www.theregister.co.uk/2008/11/18/intel_core_i7_launch_event/">Archived</a> from the original on December 20, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">December 6,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+celebrates+Core+i7+launch+with+Dell+and+Gateway&rft.pub=The+Register&rft.date=2008-11-18&rft.aulast=Modine&rft.aufirst=Austin&rft_id=https%3A%2F%2Fwww.theregister.co.uk%2F2008%2F11%2F18%2Fintel_core_i7_launch_event%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-55"><span class="mw-cite-backlink"><b><a href="#cite_ref-55">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://archive.today/20240525193424/https://www.webcitation.org/66HWXymtB?url=http://www.tgdaily.com/business/38828-idf-fall-2008-intel-un-retires-craig-barrett-amd-sets-up-anti-idf-camp">"IDF Fall 2008: Intel un-retires Craig Barrett, AMD sets up anti-IDF camp"</a>. Tigervision Media. August 11, 2008. Archived from <a rel="nofollow" class="external text" href="http://www.tgdaily.com/content/view/38828/118/">the original</a> on May 25, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">August 11,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=IDF+Fall+2008%3A+Intel+un-retires+Craig+Barrett%2C+AMD+sets+up+anti-IDF+camp&rft.pub=Tigervision+Media&rft.date=2008-08-11&rft_id=http%3A%2F%2Fwww.tgdaily.com%2Fcontent%2Fview%2F38828%2F118%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://blogs.intel.com/technology/authors#bill_calder">"Meet the Bloggers"</a>. Intel Corporation. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20120202032927/http://blogs.intel.com/technology/authors/#bill_calder">Archived</a> from the original on February 2, 2012<span class="reference-accessdate">. Retrieved <span class="nowrap">August 11,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Meet+the+Bloggers&rft.pub=Intel+Corporation&rft_id=http%3A%2F%2Fblogs.intel.com%2Ftechnology%2Fauthors%23bill_calder&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-i7_flagship_brand-57"><span class="mw-cite-backlink"><b><a href="#cite_ref-i7_flagship_brand_57-0">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://blogs.intel.com/technology/2008/08/getting_to_the_core_intels_new.php">"Getting to the Core –  Intel's new flagship client brand"</a>. Intel Corporation. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20080818154903/http://blogs.intel.com/technology/2008/08/getting_to_the_core_intels_new.php">Archived</a> from the original on August 18, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">August 11,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Getting+to+the+Core+%26ndash%3B%26%2332%3B+Intel%27s+new+flagship+client+brand&rft.pub=Intel+Corporation&rft_id=http%3A%2F%2Fblogs.intel.com%2Ftechnology%2F2008%2F08%2Fgetting_to_the_core_intels_new.php&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-58"><span class="mw-cite-backlink"><b><a href="#cite_ref-58">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://en.expreview.com/2008/06/10/intel-roadmap-update-nehalem-to-enter-mainstream-market/">"[Intel Roadmap update] Nehalem to enter mainstream market"</a>. ExpReview. June 10, 2008. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20111211170942/http://en.expreview.com/2008/06/10/intel-roadmap-update-nehalem-to-enter-mainstream-market">Archived</a> from the original on December 11, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">August 11,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=%5BIntel+Roadmap+update%5D+Nehalem+to+enter+mainstream+market&rft.pub=ExpReview&rft.date=2008-06-10&rft_id=http%3A%2F%2Fen.expreview.com%2F2008%2F06%2F10%2Fintel-roadmap-update-nehalem-to-enter-mainstream-market%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-59"><span class="mw-cite-backlink"><b><a href="#cite_ref-59">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20091006181323/http://www.intel.com/pressroom/archive/releases/20080811comp.htm">"Intel Details Upcoming New Processor Generations"</a> (Press release). Intel Corporate. August 11, 2008. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/pressroom/archive/releases/20080811comp.htm">the original</a> on October 6, 2009.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Details+Upcoming+New+Processor+Generations&rft.pub=Intel+Corporate&rft.date=2008-08-11&rft_id=http%3A%2F%2Fwww.intel.com%2Fpressroom%2Farchive%2Freleases%2F20080811comp.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-i7-920-60"><span class="mw-cite-backlink"><b><a href="#cite_ref-i7-920_60-0">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/products/37147/">"Intel Core i7-920 Processor (8M Cache, 2.66 GHz, 4.80 GT/s Intel QPI)"</a>. Intel. <a rel="nofollow" class="external text" href="http://archive.wikiwix.com/cache/20081208083516/http://ark.intel.com/products/37147/">Archived</a> from the original on December 8, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">December 6,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core+i7-920+Processor+%288M+Cache%2C+2.66+GHz%2C+4.80+GT%2Fs+Intel+QPI%29&rft.pub=Intel&rft_id=http%3A%2F%2Fark.intel.com%2Fproducts%2F37147%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-i7-940-61"><span class="mw-cite-backlink"><b><a href="#cite_ref-i7-940_61-0">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/products/37148/">"Intel Core i7-940 Processor (8M Cache, 2.93 GHz, 4.80 GT/s Intel QPI)"</a>. Intel. <a rel="nofollow" class="external text" href="http://archive.wikiwix.com/cache/20081206020839/http://ark.intel.com/products/37148/">Archived</a> from the original on December 6, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">December 6,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core+i7-940+Processor+%288M+Cache%2C+2.93+GHz%2C+4.80+GT%2Fs+Intel+QPI%29&rft.pub=Intel&rft_id=http%3A%2F%2Fark.intel.com%2Fproducts%2F37148%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-i7-965-62"><span class="mw-cite-backlink"><b><a href="#cite_ref-i7-965_62-0">^</a></b></span> <span class="reference-text"> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/products/37149/">"Intel Core i7-965 Processor Extreme Edition (8M Cache, 3.20 GHz, 6.40 GT/s Intel QPI)"</a>. Intel. <a rel="nofollow" class="external text" href="http://archive.wikiwix.com/cache/20081207155232/http://ark.intel.com/products/37149/">Archived</a> from the original on December 7, 2008<span class="reference-accessdate">. Retrieved <span class="nowrap">December 6,</span> 2008</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Core+i7-965+Processor+Extreme+Edition+%288M+Cache%2C+3.20+GHz%2C+6.40+GT%2Fs+Intel+QPI%29&rft.pub=Intel&rft_id=http%3A%2F%2Fark.intel.com%2Fproducts%2F37149%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-63"><span class="mw-cite-backlink"><b><a href="#cite_ref-63">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080818154903/http://blogs.intel.com/technology/2008/08/getting_to_the_core_intels_new.php">"Getting to the Core –  Intel's new flagship client brand"</a>. <i>Technology@Intel</i>. Archived from <a rel="nofollow" class="external text" href="http://blogs.intel.com/technology/2008/08/getting_to_the_core_intels_new.php">the original</a> on August 18, 2008.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Technology%40Intel&rft.atitle=Getting+to+the+Core+%26ndash%3B%26%2332%3B+Intel%27s+new+flagship+client+brand&rft_id=http%3A%2F%2Fblogs.intel.com%2Ftechnology%2F2008%2F08%2Fgetting_to_the_core_intels_new.php&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-64"><span class="mw-cite-backlink"><b><a href="#cite_ref-64">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://wccftech.com/intel-haswelle-core-i7-5960x-core-i7-5930k-core-i7-5820k-specifications-unveiled-flagship-8-core-boost-33-ghz/">"Intel Haswell-E Core i7-5960X, Core i7-5930K, Core i7-5820K Specifications Unveiled –  Flagship 8 Core To Boost Up To 3.3 GHz"</a>. May 27, 2014. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150613212842/http://wccftech.com/intel-haswelle-core-i7-5960x-core-i7-5930k-core-i7-5820k-specifications-unveiled-flagship-8-core-boost-33-ghz/">Archived</a> from the original on June 13, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">June 12,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Haswell-E+Core+i7-5960X%2C+Core+i7-5930K%2C+Core+i7-5820K+Specifications+Unveiled+%26ndash%3B%26%2332%3B+Flagship+8+Core+To+Boost+Up+To+3.3+GHz&rft.date=2014-05-27&rft_id=http%3A%2F%2Fwccftech.com%2Fintel-haswelle-core-i7-5960x-core-i7-5930k-core-i7-5820k-specifications-unveiled-flagship-8-core-boost-33-ghz%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-65"><span class="mw-cite-backlink"><b><a href="#cite_ref-65">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140826120102/http://newsroom.intel.com/community/intel_newsroom/blog/2014/08/11/intel-discloses-newest-microarchitecture-and-14-nanometer-manufacturing-process-technical-details">"Intel Discloses Newest Microarchitecture and 14 Nanometer Manufacturing Process Technical Details"</a>. <i>Intel</i>. Intel Corporation. August 11, 2014. Archived from <a rel="nofollow" class="external text" href="http://newsroom.intel.com/community/intel_newsroom/blog/2014/08/11/intel-discloses-newest-microarchitecture-and-14-nanometer-manufacturing-process-technical-details">the original</a> on August 26, 2014<span class="reference-accessdate">. Retrieved <span class="nowrap">September 6,</span> 2014</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+Discloses+Newest+Microarchitecture+and+14+Nanometer+Manufacturing+Process+Technical+Details&rft.date=2014-08-11&rft_id=http%3A%2F%2Fnewsroom.intel.com%2Fcommunity%2Fintel_newsroom%2Fblog%2F2014%2F08%2F11%2Fintel-discloses-newest-microarchitecture-and-14-nanometer-manufacturing-process-technical-details&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-66"><span class="mw-cite-backlink"><b><a href="#cite_ref-66">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2015/2015011001_Intel_launched_U-series_Broadwell_processors.html">"Intel launched U-series Broadwell processors"</a>. January 10, 2015. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150215191602/http://www.cpu-world.com/news_2015/2015011001_Intel_launched_U-series_Broadwell_processors.html">Archived</a> from the original on February 15, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">February 15,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+launched+U-series+Broadwell+processors&rft.date=2015-01-10&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fnews_2015%2F2015011001_Intel_launched_U-series_Broadwell_processors.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-TechReportBroadwell-67"><span class="mw-cite-backlink"><b><a href="#cite_ref-TechReportBroadwell_67-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://techreport.com/review/28379/intel-broadwell-goes-broad-with-new-desktop-mobile-server-variants">"Intel's Broadwell goes broad with new desktop, mobile, server variants –  The Tech Report –  Page 1"</a>. <i>techreport.com</i>. June 2, 2015. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150612234805/http://techreport.com/review/28379/intel-broadwell-goes-broad-with-new-desktop-mobile-server-variants">Archived</a> from the original on June 12, 2015<span class="reference-accessdate">. Retrieved <span class="nowrap">June 11,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=techreport.com&rft.atitle=Intel%27s+Broadwell+goes+broad+with+new+desktop%2C+mobile%2C+server+variants+%26ndash%3B%26%2332%3B+The+Tech+Report+%26ndash%3B%26%2332%3B+Page+1&rft.date=2015-06-02&rft_id=http%3A%2F%2Ftechreport.com%2Freview%2F28379%2Fintel-broadwell-goes-broad-with-new-desktop-mobile-server-variants&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-68"><span class="mw-cite-backlink"><b><a href="#cite_ref-68">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://techreport.com/news/30417/intel-begins-shipping-kaby-lake-cpus-to-manufacturers">"Intel begins shipping Kaby Lake CPUs to manufacturers"</a>. <i>The Tech Report</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170126133107/https://techreport.com/news/30417/intel-begins-shipping-kaby-lake-cpus-to-manufacturers">Archived</a> from the original on January 26, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">January 21,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Tech+Report&rft.atitle=Intel+begins+shipping+Kaby+Lake+CPUs+to+manufacturers&rft_id=https%3A%2F%2Ftechreport.com%2Fnews%2F30417%2Fintel-begins-shipping-kaby-lake-cpus-to-manufacturers&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-69"><span class="mw-cite-backlink"><b><a href="#cite_ref-69">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2017/01/intel-pushes-out-the-rest-of-its-kaby-lake-processors-for-2017s-pcs/">"Intel pushes out the rest of its Kaby Lake processors for 2017's PCs"</a>. <i>Ars Technica</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170121092433/http://arstechnica.com/gadgets/2017/01/intel-pushes-out-the-rest-of-its-kaby-lake-processors-for-2017s-pcs/">Archived</a> from the original on January 21, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">January 21,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Ars+Technica&rft.atitle=Intel+pushes+out+the+rest+of+its+Kaby+Lake+processors+for+2017%27s+PCs&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2017%2F01%2Fintel-pushes-out-the-rest-of-its-kaby-lake-processors-for-2017s-pcs%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-ArsKabyDetails-70"><span class="mw-cite-backlink">^ <a href="#cite_ref-ArsKabyDetails_70-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ArsKabyDetails_70-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://arstechnica.co.uk/gadgets/2016/08/intel-kaby-lake-7th-gen-details-release-date/">"Intel Kaby Lake details: The first post-"tick-tock" CPU architecture"</a>. <i>Ars Technica UK</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170106050930/http://arstechnica.co.uk/gadgets/2016/08/intel-kaby-lake-7th-gen-details-release-date/">Archived</a> from the original on January 6, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">January 21,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Ars+Technica+UK&rft.atitle=Intel+Kaby+Lake+details%3A+The+first+post-%22tick-tock%22+CPU+architecture&rft_id=http%3A%2F%2Farstechnica.co.uk%2Fgadgets%2F2016%2F08%2Fintel-kaby-lake-7th-gen-details-release-date%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-71"><span class="mw-cite-backlink"><b><a href="#cite_ref-71">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2017/10/intel-coffee-lake-8700k-review/">"Intel Coffee Lake Core i7-8700K review: The best gaming CPU you can buy"</a>. <i>Ars Technica</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171005132309/https://arstechnica.com/gadgets/2017/10/intel-coffee-lake-8700k-review/">Archived</a> from the original on October 5, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">October 5,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Ars+Technica&rft.atitle=Intel+Coffee+Lake+Core+i7-8700K+review%3A+The+best+gaming+CPU+you+can+buy&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2017%2F10%2Fintel-coffee-lake-8700k-review%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-72"><span class="mw-cite-backlink"><b><a href="#cite_ref-72">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.techspot.com/review/1497-intel-core-i7-8700k/page5.html">"Intel Core i7-8700K Review: The New Gaming King"</a>. <i>TechSpot</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171005203105/https://www.techspot.com/review/1497-intel-core-i7-8700k/page5.html">Archived</a> from the original on October 5, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">October 5,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=TechSpot&rft.atitle=Intel+Core+i7-8700K+Review%3A+The+New+Gaming+King&rft_id=https%3A%2F%2Fwww.techspot.com%2Freview%2F1497-intel-core-i7-8700k%2Fpage5.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-73"><span class="mw-cite-backlink"><b><a href="#cite_ref-73">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.kitguru.net/components/motherboard/paul-taylor/intel-300-series-chipsets-to-provide-usb-3-1-gen2-and-gigabit-wi-fi/">"Intel 300-series chipsets to provide USB 3.1 Gen2 and Gigabit Wi-Fi | KitGuru"</a>. <i>www.kitguru.net</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170506072213/http://www.kitguru.net/components/motherboard/paul-taylor/intel-300-series-chipsets-to-provide-usb-3-1-gen2-and-gigabit-wi-fi/">Archived</a> from the original on May 6, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">April 29,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.kitguru.net&rft.atitle=Intel+300-series+chipsets+to+provide+USB+3.1+Gen2+and+Gigabit+Wi-Fi+%7C+KitGuru&rft_id=http%3A%2F%2Fwww.kitguru.net%2Fcomponents%2Fmotherboard%2Fpaul-taylor%2Fintel-300-series-chipsets-to-provide-usb-3-1-gen2-and-gigabit-wi-fi%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-74"><span class="mw-cite-backlink"><b><a href="#cite_ref-74">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/11859/the-anandtech-coffee-lake-review-8700k-and-8400-initial-numbers/3">"The AnandTech Coffee Lake Review: Initial Numbers on the Core i7-8700K and Core i5-8400"</a>. p. 3. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20171005202422/https://www.anandtech.com/show/11859/the-anandtech-coffee-lake-review-8700k-and-8400-initial-numbers/3">Archived</a> from the original on October 5, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">October 6,</span> 2017</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=The+AnandTech+Coffee+Lake+Review%3A+Initial+Numbers+on+the+Core+i7-8700K+and+Core+i5-8400&rft.pages=3&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F11859%2Fthe-anandtech-coffee-lake-review-8700k-and-8400-initial-numbers%2F3&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-anand12945-75"><span class="mw-cite-backlink"><b><a href="#cite_ref-anand12945_75-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2018" class="citation news cs1">Cutress, Ian (June 11, 2018). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/12945/the-intel-core-i7-8086k-review">"The Intel Core i7-8086K Review"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=The+Intel+Core+i7-8086K+Review&rft.date=2018-06-11&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F12945%2Fthe-intel-core-i7-8086k-review&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-76"><span class="mw-cite-backlink"><b><a href="#cite_ref-76">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://newsroom.intel.com/news/new-8th-gen-intel-core-processors-optimized-connectivity-great-performance-long-battery-life-laptops/">"New 8th Gen Intel Core Processors Optimize Connectivity, Great Performance, Battery Life for Laptops | Intel Newsroom"</a>. <i>Intel Newsroom</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Intel+Newsroom&rft.atitle=New+8th+Gen+Intel+Core+Processors+Optimize+Connectivity%2C+Great+Performance%2C+Battery+Life+for+Laptops+%7C+Intel+Newsroom&rft_id=https%3A%2F%2Fnewsroom.intel.com%2Fnews%2Fnew-8th-gen-intel-core-processors-optimized-connectivity-great-performance-long-battery-life-laptops%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-AnandWhiskey-77"><span class="mw-cite-backlink">^ <a href="#cite_ref-AnandWhiskey_77-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-AnandWhiskey_77-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13275/intel-launches-whiskey-lake-amber-lake">"Intel Launches Whiskey Lake-U and Amber Lake-Y: New MacBook CPUs?"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Intel+Launches+Whiskey+Lake-U+and+Amber+Lake-Y%3A+New+MacBook+CPUs%3F&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13275%2Fintel-launches-whiskey-lake-amber-lake&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-78"><span class="mw-cite-backlink"><b><a href="#cite_ref-78">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.notebookcheck.net/Intel-launches-Whiskey-Lake-U-and-Amber-Lake-Y-CPUs-with-focus-on-enhanced-mobile-connectivity.325710.0.html">"Intel launches Whiskey Lake-U and Amber Lake-Y CPUs with focus on enhanced mobile connectivity"</a>. <i>Notebookcheck</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Notebookcheck&rft.atitle=Intel+launches+Whiskey+Lake-U+and+Amber+Lake-Y+CPUs+with+focus+on+enhanced+mobile+connectivity&rft_id=https%3A%2F%2Fwww.notebookcheck.net%2FIntel-launches-Whiskey-Lake-U-and-Amber-Lake-Y-CPUs-with-focus-on-enhanced-mobile-connectivity.325710.0.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-79"><span class="mw-cite-backlink"><b><a href="#cite_ref-79">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2018/08/intel-launches-whiskey-and-amber-lakes-kaby-lake-with-better-wi-fi-usb/">"Intel launches Whiskey and Amber Lakes: Kaby Lake with better Wi-Fi, USB"</a>. <i>Ars Technica</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Ars+Technica&rft.atitle=Intel+launches+Whiskey+and+Amber+Lakes%3A+Kaby+Lake+with+better+Wi-Fi%2C+USB&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2018%2F08%2Fintel-launches-whiskey-and-amber-lakes-kaby-lake-with-better-wi-fi-usb%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-80"><span class="mw-cite-backlink"><b><a href="#cite_ref-80">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-whiskey-lake-amber-lake,37704.html">"Intel Launches Whiskey Lake And Amber Lake CPUs for Laptops"</a>. <i>Tom's Hardware</i>. August 28, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">August 28,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+Launches+Whiskey+Lake+And+Amber+Lake+CPUs+for+Laptops&rft.date=2018-08-28&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-whiskey-lake-amber-lake%2C37704.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-81"><span class="mw-cite-backlink"><b><a href="#cite_ref-81">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://twitter.com/Ashraf__Eassa/status/1034848491791691776">"Ashraf Eassa on Twitter"</a>. <i>Twitter</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 29,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Twitter&rft.atitle=Ashraf+Eassa+on+Twitter&rft_id=https%3A%2F%2Ftwitter.com%2FAshraf__Eassa%2Fstatus%2F1034848491791691776&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-82"><span class="mw-cite-backlink"><b><a href="#cite_ref-82">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://twitter.com/IanCutress/status/1034686289663197184">"Ian Cutress on Twitter"</a>. <i>Twitter</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 29,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Twitter&rft.atitle=Ian+Cutress+on+Twitter&rft_id=https%3A%2F%2Ftwitter.com%2FIanCutress%2Fstatus%2F1034686289663197184&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-83"><span class="mw-cite-backlink"><b><a href="#cite_ref-83">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2018" class="citation web cs1">Cutress, Ian (August 30, 2018). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13301/spectre-and-meltdown-in-hardware-intel-clarifies-whiskey-lake-and-amber-lake">"Spectre and Meltdown in Hardware: Intel Clarifies Whiskey Lake and Amber Lake"</a>. <i>anadtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 4,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=anadtech.com&rft.atitle=Spectre+and+Meltdown+in+Hardware%3A+Intel+Clarifies+Whiskey+Lake+and+Amber+Lake&rft.date=2018-08-30&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13301%2Fspectre-and-meltdown-in-hardware-intel-clarifies-whiskey-lake-and-amber-lake&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-84"><span class="mw-cite-backlink"><b><a href="#cite_ref-84">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2018" class="citation web cs1">Alcorn, Paul (August 30, 2018). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/whiskey-lake-mitigations-in-silicon-intel,37723.html">"Intel's Whiskey Lake Brings In-Silicon Meltdown and Foreshadow Fixes"</a>. <i>Tom's Hardware</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel%27s+Whiskey+Lake+Brings+In-Silicon+Meltdown+and+Foreshadow+Fixes&rft.date=2018-08-30&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fwhiskey-lake-mitigations-in-silicon-intel%2C37723.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-wccftech-85"><span class="mw-cite-backlink"><b><a href="#cite_ref-wccftech_85-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141006085749/http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/">"Intel's Cannonlake 10nm Microarchitecture is Due For 2016 - Compatible On Union Bay With Union Point PCH"</a>. <i>WCCFTech</i>. June 6, 2014. Archived from <a rel="nofollow" class="external text" href="http://wccftech.com/intels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch/">the original</a> on October 6, 2014<span class="reference-accessdate">. Retrieved <span class="nowrap">September 24,</span> 2014</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=WCCFTech&rft.atitle=Intel%27s+Cannonlake+10nm+Microarchitecture+is+Due+For+2016+-+Compatible+On+Union+Bay+With+Union+Point+PCH&rft.date=2014-06-06&rft_id=http%3A%2F%2Fwccftech.com%2Fintels-cannonlake-10nm-microarchitecture-due-2016-compatible-union-bay-union-point-pch%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-86"><span class="mw-cite-backlink"><b><a href="#cite_ref-86">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/architecture-and-technology/avx-512-overview.html">"Intel Advanced Vector Extensions 512 (Intel AVX-512) Overview"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180302164658/https://www.intel.com/content/www/us/en/architecture-and-technology/avx-512-overview.html">Archived</a> from the original on March 2, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">March 2,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+Advanced+Vector+Extensions+512+%28Intel+AVX-512%29+Overview&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Farchitecture-and-technology%2Favx-512-overview.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-87"><span class="mw-cite-backlink"><b><a href="#cite_ref-87">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.prowesscorp.com/what-is-intel-avx-512-and-why-does-it-matter/">"What Is Intel AVX-512 and Why Does It Matter? | Prowess Consulting"</a>. <i>www.prowesscorp.com</i>. January 10, 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180302225345/http://www.prowesscorp.com/what-is-intel-avx-512-and-why-does-it-matter/">Archived</a> from the original on March 2, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">March 2,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.prowesscorp.com&rft.atitle=What+Is+Intel+AVX-512+and+Why+Does+It+Matter%3F+%7C+Prowess+Consulting&rft.date=2018-01-10&rft_id=http%3A%2F%2Fwww.prowesscorp.com%2Fwhat-is-intel-avx-512-and-why-does-it-matter%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-88"><span class="mw-cite-backlink"><b><a href="#cite_ref-88">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/12271/intel-mentions-10nm-briefly">"Intel Mentions 10nm, Briefly"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180110014405/https://www.anandtech.com/show/12271/intel-mentions-10nm-briefly">Archived</a> from the original on January 10, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">January 10,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Intel+Mentions+10nm%2C+Briefly&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F12271%2Fintel-mentions-10nm-briefly&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-89"><span class="mw-cite-backlink"><b><a href="#cite_ref-89">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://www.tomshardware.com/news/intel-ces-10nm-processor,36289.html">"Intel Announces 10nm Cannon Lake Is Shipping"</a>. <i>Tom's Hardware</i>. January 9, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">January 10,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+Announces+10nm+Cannon+Lake+Is+Shipping&rft.date=2018-01-09&rft_id=http%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-ces-10nm-processor%2C36289.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-90"><span class="mw-cite-backlink"><b><a href="#cite_ref-90">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAnandTech2018" class="citation cs2">AnandTech (January 9, 2018), <a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=KoBfKooUDb0&t=515"><i>Intel at CES 2018: 10nm [@8:35]</i></a>, <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180427043229/https://www.youtube.com/watch?v=KoBfKooUDb0&t=515">archived</a> from the original on April 27, 2018<span class="reference-accessdate">, retrieved <span class="nowrap">January 10,</span> 2018</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Intel+at+CES+2018%3A+10nm+%5B%408%3A35%5D&rft.date=2018-01-09&rft.au=AnandTech&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3DKoBfKooUDb0%26t%3D515&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-91"><span class="mw-cite-backlink"><b><a href="#cite_ref-91">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.notebookcheck.net/Intel-Core-i3-8121U-SoC-Benchmarks-and-Specs.303400.0.html">"Intel Core i3-8121U SoC –  Benchmarks and Specs"</a>. <i>Notebookcheck</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 14,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Notebookcheck&rft.atitle=Intel+Core+i3-8121U+SoC+%26ndash%3B%26%2332%3B+Benchmarks+and+Specs&rft_id=https%3A%2F%2Fwww.notebookcheck.net%2FIntel-Core-i3-8121U-SoC-Benchmarks-and-Specs.303400.0.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-92"><span class="mw-cite-backlink"><b><a href="#cite_ref-92">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKampman2018" class="citation news cs1">Kampman, Jeff (May 15, 2018). <a rel="nofollow" class="external text" href="https://techreport.com/news/33645/cannon-lake-core-i3-8121u-appears-in-intel-ark-database">"Cannon Lake Core i3-8121U appears in Intel's ARK database"</a>. Tech Report<span class="reference-accessdate">. Retrieved <span class="nowrap">May 15,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Cannon+Lake+Core+i3-8121U+appears+in+Intel%27s+ARK+database&rft.date=2018-05-15&rft.aulast=Kampman&rft.aufirst=Jeff&rft_id=https%3A%2F%2Ftechreport.com%2Fnews%2F33645%2Fcannon-lake-core-i3-8121u-appears-in-intel-ark-database&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-93"><span class="mw-cite-backlink"><b><a href="#cite_ref-93">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-9th-generation-coffee-lake-refresh,37898.html">"Intel Announces 9th Generation Core CPUs, Eight-Core Core i9-9900K"</a>. <i>Tom's Hardware</i>. October 8, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">October 9,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+Announces+9th+Generation+Core+CPUs%2C+Eight-Core+Core+i9-9900K&rft.date=2018-10-08&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-9th-generation-coffee-lake-refresh%2C37898.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-94"><span class="mw-cite-backlink"><b><a href="#cite_ref-94">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.theverge.com/2018/10/8/17950968/intel-9th-gen-core-chips-2018-desktop-processors-8-core-i9-9900k">"Intel announces its latest 9th Gen chips, including its 'best gaming processor' Core i9"</a>. <i>The Verge</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 9,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=The+Verge&rft.atitle=Intel+announces+its+latest+9th+Gen+chips%2C+including+its+%27best+gaming+processor%27+Core+i9&rft_id=https%3A%2F%2Fwww.theverge.com%2F2018%2F10%2F8%2F17950968%2Fintel-9th-gen-core-chips-2018-desktop-processors-8-core-i9-9900k&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-95"><span class="mw-cite-backlink"><b><a href="#cite_ref-95">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13473/intel-to-support-128gb-of-ddr4-on-core-9th-gen-desktop-processors">"Intel to Support 128GB of DDR4 on Core 9th Gen Desktop Processors"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">October 15,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Intel+to+Support+128GB+of+DDR4+on+Core+9th+Gen+Desktop+Processors&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13473%2Fintel-to-support-128gb-of-ddr4-on-core-9th-gen-desktop-processors&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-96"><span class="mw-cite-backlink"><b><a href="#cite_ref-96">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13865/intels-graphics-free-chips-are-also-savings-free-same-price-fewer-features">"Intel's Graphics-Free Chips Are Also Savings-Free: Same Price, Fewer Features"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">January 16,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Intel%27s+Graphics-Free+Chips+Are+Also+Savings-Free%3A+Same+Price%2C+Fewer+Features&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13865%2Fintels-graphics-free-chips-are-also-savings-free-same-price-fewer-features&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-9gAT-97"><span class="mw-cite-backlink"><b><a href="#cite_ref-9gAT_97-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCuttress2018" class="citation web cs1">Cuttress, Ian (October 8, 2018). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13401/intel-9th-gen-cpus-9900k-9700k-9600k">"Intel Announced 9th Gen Core CPUs: Core i9-9900K (8-Core), i7-9700K, & i5-9600K"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 8,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=Intel+Announced+9th+Gen+Core+CPUs%3A+Core+i9-9900K+%288-Core%29%2C+i7-9700K%2C+%26+i5-9600K&rft.date=2018-10-08&rft.aulast=Cuttress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13401%2Fintel-9th-gen-cpus-9900k-9700k-9600k&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-98"><span class="mw-cite-backlink"><b><a href="#cite_ref-98">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20181020094958/https://www.guru3d.com/articles_pages/intel_core_i9_9900k_processor_review,24.html">"Intel Core i9 9900K processor review"</a>. <i>Guru3D.com</i>. Archived from <a rel="nofollow" class="external text" href="https://www.guru3d.com/articles_pages/intel_core_i9_9900k_processor_review,24.html">the original</a> on October 20, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">October 19,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Guru3D.com&rft.atitle=Intel+Core+i9+9900K+processor+review&rft_id=https%3A%2F%2Fwww.guru3d.com%2Farticles_pages%2Fintel_core_i9_9900k_processor_review%2C24.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-99"><span class="mw-cite-backlink"><b><a href="#cite_ref-99">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation news cs1">Cutress, Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/13400/intel-9th-gen-core-i9-9900k-i7-9700k-i5-9600k-review/21">"The Intel 9th Gen Review: Core i9-9900K, Core i7-9700K and Core i5-9600K Tested"</a><span class="reference-accessdate">. Retrieved <span class="nowrap">October 19,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=The+Intel+9th+Gen+Review%3A+Core+i9-9900K%2C+Core+i7-9700K+and+Core+i5-9600K+Tested&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13400%2Fintel-9th-gen-core-i9-9900k-i7-9700k-i5-9600k-review%2F21&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-100"><span class="mw-cite-backlink"><b><a href="#cite_ref-100">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/reviews/Intel/Core_i9_9900K/16.html">"Intel Core i9-9900K Review"</a>. <i>TechPowerUp</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 19,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=TechPowerUp&rft.atitle=Intel+Core+i9-9900K+Review&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Freviews%2FIntel%2FCore_i9_9900K%2F16.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-101"><span class="mw-cite-backlink"><b><a href="#cite_ref-101">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="https://www.tomshardware.com/reviews/intel-core-i9-9900k-9th-gen-cpu,5847-11.html">"Power Consumption –  Intel Core i9-9900K 9th Gen CPU Review: Fastest Gaming Processor Ever"</a>. <i>Tom's Hardware</i>. October 19, 2018<span class="reference-accessdate">. Retrieved <span class="nowrap">October 21,</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Tom%27s+Hardware&rft.atitle=Power+Consumption+%26ndash%3B%26%2332%3B+Intel+Core+i9-9900K+9th+Gen+CPU+Review%3A+Fastest+Gaming+Processor+Ever&rft.date=2018-10-19&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Freviews%2Fintel-core-i9-9900k-9th-gen-cpu%2C5847-11.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-102"><span class="mw-cite-backlink"><b><a href="#cite_ref-102">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://newsroom.intel.com/news/intel-expands-10th-gen-intel-core-mobile-processor-family-offering-double-digit-performance-gains/">"Intel Expands 10th Gen Intel Core Mobile Processor Family, Offering Double Digit Performance Gains"</a>. <i>Intel Newsroom</i><span class="reference-accessdate">. Retrieved <span class="nowrap">August 21,</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel+Newsroom&rft.atitle=Intel+Expands+10th+Gen+Intel+Core+Mobile+Processor+Family%2C+Offering+Double+Digit+Performance+Gains&rft_id=https%3A%2F%2Fnewsroom.intel.com%2Fnews%2Fintel-expands-10th-gen-intel-core-mobile-processor-family-offering-double-digit-performance-gains%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-:0-103"><span class="mw-cite-backlink"><b><a href="#cite_ref-:0_103-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutressFrumusanu" class="citation web cs1">Cutress, Ian; Frumusanu, Andrei. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16084/intel-tiger-lake-review-deep-dive-core-11th-gen">"Intel's Tiger Lake 11th Gen Core i7-1185G7 Review and Deep Dive: Baskin' for the Exotic"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">September 17,</span> 2020</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel%27s+Tiger+Lake+11th+Gen+Core+i7-1185G7+Review+and+Deep+Dive%3A+Baskin%27+for+the+Exotic&rft.aulast=Cutress&rft.aufirst=Ian&rft.au=Frumusanu%2C+Andrei&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16084%2Fintel-tiger-lake-review-deep-dive-core-11th-gen&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-104"><span class="mw-cite-backlink"><b><a href="#cite_ref-104">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFOlšan2021" class="citation web cs1">Olšan, Jan (August 6, 2021). <a rel="nofollow" class="external text" href="https://www.cnews.cz/intel-10nm-procesory-pro-desktop-core-i9-11900kb-zrejme-bga-tiger-lake-h/">"Intel potichu uvedl 10nm procesory pro desktop, BGA verze Tiger Lake-H (Update: takty boostu vyjasněné)"</a>. <i>cnews.cz</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 11,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=cnews.cz&rft.atitle=Intel+potichu+uvedl+10nm+procesory+pro+desktop%2C+BGA+verze+Tiger+Lake-H+%28Update%3A+takty+boostu+vyjasn%C4%9Bn%C3%A9%29&rft.date=2021-08-06&rft.aulast=Ol%C5%A1an&rft.aufirst=Jan&rft_id=https%3A%2F%2Fwww.cnews.cz%2Fintel-10nm-procesory-pro-desktop-core-i9-11900kb-zrejme-bga-tiger-lake-h%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-auto6-105"><span class="mw-cite-backlink"><b><a href="#cite_ref-auto6_105-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16205/intels-11th-gen-core-rocket-lake-detailed-ice-lake-core-with-xe-graphics">"Intel's 11th Gen Core Rocket Lake Detailed: Ice Lake Core with Xe Graphics"</a>. AnandTech. October 29, 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel%27s+11th+Gen+Core+Rocket+Lake+Detailed%3A+Ice+Lake+Core+with+Xe+Graphics&rft.pub=AnandTech&rft.date=2020-10-29&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16205%2Fintels-11th-gen-core-rocket-lake-detailed-ice-lake-core-with-xe-graphics&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-106"><span class="mw-cite-backlink"><b><a href="#cite_ref-106">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation web cs1">Cutress, Dr Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16523/intel-core-11th-gen-rocket-lake-core-i9-core-i7-core-i5">"Intel Launches Rocket Lake 11th Gen Core i9, Core i7, and Core i5"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 17,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel+Launches+Rocket+Lake+11th+Gen+Core+i9%2C+Core+i7%2C+and+Core+i5&rft.aulast=Cutress&rft.aufirst=Dr+Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16523%2Fintel-core-11th-gen-rocket-lake-core-i9-core-i7-core-i5&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-107"><span class="mw-cite-backlink"><b><a href="#cite_ref-107">^</a></b></span> <span class="reference-text">Cutress, Ian <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/15979/intel-alder-lake-confirmed-x86-hybrid-with-golden-cove-and-gracemont-for-2021">"Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021"</a>. www.anandtech.com. Retrieved 2021-02-15.</span> </li> <li id="cite_note-108"><span class="mw-cite-backlink"><b><a href="#cite_ref-108">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress" class="citation web cs1">Cutress, Dr Ian. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/16959/intel-innovation-alder-lake-november-4th">"Intel 12th Gen Core Alder Lake for Desktops: Top SKUs Only, Coming November 4th"</a>. <i>www.anandtech.com</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel+12th+Gen+Core+Alder+Lake+for+Desktops%3A+Top+SKUs+Only%2C+Coming+November+4th&rft.aulast=Cutress&rft.aufirst=Dr+Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F16959%2Fintel-innovation-alder-lake-november-4th&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-:2-109"><span class="mw-cite-backlink"><b><a href="#cite_ref-:2_109-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/ark/products/codename/147470/products-formerly-alder-lake.html">"Products formerly Alder Lake"</a>. <i>www.intel.com</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.intel.com&rft.atitle=Products+formerly+Alder+Lake&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fark%2Fproducts%2Fcodename%2F147470%2Fproducts-formerly-alder-lake.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-:1-110"><span class="mw-cite-backlink"><b><a href="#cite_ref-:1_110-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutressFrumusanu2021" class="citation web cs1">Cutress, Ian; Frumusanu, Andrei (November 4, 2021). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/17047/the-intel-12th-gen-core-i912900k-review-hybrid-performance-brings-hybrid-complexity/2">"The Intel 12th Gen Core i9-12900K Review: Hybrid Performance Brings Hybrid Complexity"</a>. <i>AnandTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 4,</span> 2021</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=The+Intel+12th+Gen+Core+i9-12900K+Review%3A+Hybrid+Performance+Brings+Hybrid+Complexity&rft.date=2021-11-04&rft.aulast=Cutress&rft.aufirst=Ian&rft.au=Frumusanu%2C+Andrei&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F17047%2Fthe-intel-12th-gen-core-i912900k-review-hybrid-performance-brings-hybrid-complexity%2F2&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-111"><span class="mw-cite-backlink"><b><a href="#cite_ref-111">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBonshor" class="citation web cs1">Bonshor, Gavin. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/17308/the-intel-w680-chipset-overview-ecc-for-alder-lake-workstations">"The Intel W680 Chipset Overview: Alder Lake Workstations Get ECC Memory and Overclocking Support"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">April 14,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=The+Intel+W680+Chipset+Overview%3A+Alder+Lake+Workstations+Get+ECC+Memory+and+Overclocking+Support&rft.aulast=Bonshor&rft.aufirst=Gavin&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F17308%2Fthe-intel-w680-chipset-overview-ecc-for-alder-lake-workstations&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-112"><span class="mw-cite-backlink"><b><a href="#cite_ref-112">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/12th-gen-intel-core-i9-12900ks-worlds-fastest-desktop-processor.html">"12th Gen Intel Core i9-12900KS Launches as World's Fastest Desktop..."</a> <i>Intel</i><span class="reference-accessdate">. Retrieved <span class="nowrap">March 28,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=12th+Gen+Intel+Core+i9-12900KS+Launches+as+World%27s+Fastest+Desktop...&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fnews%2F12th-gen-intel-core-i9-12900ks-worlds-fastest-desktop-processor.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-113"><span class="mw-cite-backlink"><b><a href="#cite_ref-113">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://videocardz.com/newz/intel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache">"Intel Core i5-12490F is China exclusive 6-core Alder Lake desktop CPU with 20MB L3 cache"</a>. <i>VideoCardz</i>. February 28, 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220228060444/https://videocardz.com/newz/intel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache">Archived</a> from the original on February 28, 2022<span class="reference-accessdate">. Retrieved <span class="nowrap">February 28,</span> 2022</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VideoCardz&rft.atitle=Intel+Core+i5-12490F+is+China+exclusive+6-core+Alder+Lake+desktop+CPU+with+20MB+L3+cache&rft.date=2022-02-28&rft_id=https%3A%2F%2Fvideocardz.com%2Fnewz%2Fintel-core-i5-12490f-is-china-exclusive-6-core-alder-lake-desktop-cpu-with-20mb-l3-cache&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span> <a rel="nofollow" class="external text" href="https://www.techpowerup.com/cpu-specs/core-i5-12490f.c2599">Alt URL</a></span> </li> <li id="cite_note-114"><span class="mw-cite-backlink"><b><a href="#cite_ref-114">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://videocardz.com/newz/intel-showcases-13th-gen-core-raptor-lake-cpu-with-24-cores-and-32-threads">"Intel showcases 13th Gen Core "Raptor Lake" CPU with 24 cores and 32 threads"</a>. <i>VideoCardz</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VideoCardz&rft.atitle=Intel+showcases+13th+Gen+Core+%22Raptor+Lake%22+CPU+with+24+cores+and+32+threads&rft_id=https%3A%2F%2Fvideocardz.com%2Fnewz%2Fintel-showcases-13th-gen-core-raptor-lake-cpu-with-24-cores-and-32-threads&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-115"><span class="mw-cite-backlink"><b><a href="#cite_ref-115">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake">"Raptor Lake - Microarchitectures - Intel - WikiChip"</a>. <i>en.wikichip.org</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 25,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=en.wikichip.org&rft.atitle=Raptor+Lake+-+Microarchitectures+-+Intel+-+WikiChip&rft_id=https%3A%2F%2Fen.wikichip.org%2Fwiki%2Fintel%2Fmicroarchitectures%2Fraptor_lake&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-:6-116"><span class="mw-cite-backlink"><b><a href="#cite_ref-:6_116-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ark.intel.com/content/www/us/en/products/sku/codename/215599/products-formerly-raptor-lake.html">"Products formerly Raptor Lake"</a>. <i>www.intel.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.intel.com&rft.atitle=Products+formerly+Raptor+Lake&rft_id=https%3A%2F%2Fark.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fproducts%2Fsku%2Fcodename%2F215599%2Fproducts-formerly-raptor-lake.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-117"><span class="mw-cite-backlink"><b><a href="#cite_ref-117">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBonshor" class="citation web cs1">Bonshor, Gavin. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/21096/intel-announces-14th-gen-core-series-for-desktop-core-i9-14900k-core-i7-14700k-and-core-i5-14600k">"Intel Announces 14th Gen Core Series For Desktop: Core i9-14900K, Core i7-14700K and Core i5-14600K"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">October 27,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel+Announces+14th+Gen+Core+Series+For+Desktop%3A+Core+i9-14900K%2C+Core+i7-14700K+and+Core+i5-14600K&rft.aulast=Bonshor&rft.aufirst=Gavin&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F21096%2Fintel-announces-14th-gen-core-series-for-desktop-core-i9-14900k-core-i7-14700k-and-core-i5-14600k&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-:7-118"><span class="mw-cite-backlink"><b><a href="#cite_ref-:7_118-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCunningham2023" class="citation web cs1">Cunningham, Andrew (October 17, 2023). <a rel="nofollow" class="external text" href="https://arstechnica.com/gadgets/2023/10/intels-14th-gen-desktop-cpus-are-a-tiny-update-even-by-modern-standards/">"Intel's 14th-gen desktop CPUs are a tiny update even by modern standards"</a>. <i>Ars Technica</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 6,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Ars+Technica&rft.atitle=Intel%27s+14th-gen+desktop+CPUs+are+a+tiny+update+even+by+modern+standards&rft.date=2023-10-17&rft.aulast=Cunningham&rft.aufirst=Andrew&rft_id=https%3A%2F%2Farstechnica.com%2Fgadgets%2F2023%2F10%2Fintels-14th-gen-desktop-cpus-are-a-tiny-update-even-by-modern-standards%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-119"><span class="mw-cite-backlink"><b><a href="#cite_ref-119">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=2MvvCr-thM8"><i>Intel's 300W Core i9-14900K: CPU Review, Benchmarks, Gaming, & Power</i></a>, October 18, 2023<span class="reference-accessdate">, retrieved <span class="nowrap">November 6,</span> 2023</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Intel%27s+300W+Core+i9-14900K%3A+CPU+Review%2C+Benchmarks%2C+Gaming%2C+%26+Power&rft.date=2023-10-18&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3D2MvvCr-thM8&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-120"><span class="mw-cite-backlink"><b><a href="#cite_ref-120">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=0oALfgsyOg4"><i>Intel Core i9-14900K, Core i7-14700K & Core i5-14600K Review, Gaming Benchmarks</i></a>, October 17, 2023<span class="reference-accessdate">, retrieved <span class="nowrap">November 6,</span> 2023</span></cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Intel+Core+i9-14900K%2C+Core+i7-14700K+%26+Core+i5-14600K+Review%2C+Gaming+Benchmarks&rft.date=2023-10-17&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3D0oALfgsyOg4&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-121"><span class="mw-cite-backlink"><b><a href="#cite_ref-121">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBonshor" class="citation web cs1">Bonshor, Gavin. <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/21076/intel-meteor-lake-soc-is-not-coming-to-desktops-well-not-technically">"Intel Meteor Lake SoC is NOT Coming to Desktops: Well, Not Technically"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">November 6,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel+Meteor+Lake+SoC+is+NOT+Coming+to+Desktops%3A+Well%2C+Not+Technically&rft.aulast=Bonshor&rft.aufirst=Gavin&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F21076%2Fintel-meteor-lake-soc-is-not-coming-to-desktops-well-not-technically&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-122"><span class="mw-cite-backlink"><b><a href="#cite_ref-122">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLiu2024" class="citation web cs1">Liu, Zhiye (January 8, 2024). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/pc-components/cpus/intel-unleashes-14th-gen-raptor-lake-refresh-hx-series-laptops-cpus-refreshed-chips-with-up-to-24-cores-58-ghz-boost-clock-and-192gb-ddr5-support">"Intel unleashes 14th Gen Raptor Lake Refresh HX-series CPUs — refreshed chips with up to 24 cores, 5.8 GHz boost clock, and 192GB DDR5 support"</a>. <i>Tom's Hardware</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 12,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+unleashes+14th+Gen+Raptor+Lake+Refresh+HX-series+CPUs+%E2%80%94+refreshed+chips+with+up+to+24+cores%2C+5.8+GHz+boost+clock%2C+and+192GB+DDR5+support&rft.date=2024-01-08&rft.aulast=Liu&rft.aufirst=Zhiye&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fpc-components%2Fcpus%2Fintel-unleashes-14th-gen-raptor-lake-refresh-hx-series-laptops-cpus-refreshed-chips-with-up-to-24-cores-58-ghz-boost-clock-and-192gb-ddr5-support&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-coreultra-series1-123"><span class="mw-cite-backlink">^ <a href="#cite_ref-coreultra-series1_123-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-coreultra-series1_123-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNorem2023" class="citation web cs1">Norem, Josh (December 14, 2023). <a rel="nofollow" class="external text" href="https://www.extremetech.com/computing/intel-officially-launches-meteor-lake-core-ultra-cpus">"Intel Officially Launches Meteor Lake 'Core Ultra' CPUs"</a>. <i>ExtremeTech</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 12,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ExtremeTech&rft.atitle=Intel+Officially+Launches+Meteor+Lake+%27Core+Ultra%27+CPUs&rft.date=2023-12-14&rft.aulast=Norem&rft.aufirst=Josh&rft_id=https%3A%2F%2Fwww.extremetech.com%2Fcomputing%2Fintel-officially-launches-meteor-lake-core-ultra-cpus&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-core-series1-124"><span class="mw-cite-backlink">^ <a href="#cite_ref-core-series1_124-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-core-series1_124-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith2024" class="citation web cs1">Smith, Ryan (January 8, 2024). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/21216/intel-intros-core-series-1-useries-mobile-chips-raptor-lake-refreshed-for-thin-light">"Intel Intros Core (Series 1) U-Series Mobile Chips: Raptor Lake Refreshed for Thin & Light"</a>. <i>www.anandtech.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 12,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.anandtech.com&rft.atitle=Intel+Intros+Core+%28Series+1%29+U-Series+Mobile+Chips%3A+Raptor+Lake+Refreshed+for+Thin+%26+Light&rft.date=2024-01-08&rft.aulast=Smith&rft.aufirst=Ryan&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F21216%2Fintel-intros-core-series-1-useries-mobile-chips-raptor-lake-refreshed-for-thin-light&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-125"><span class="mw-cite-backlink"><b><a href="#cite_ref-125">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRoach2023" class="citation web cs1">Roach, Jacob (December 14, 2023). <a rel="nofollow" class="external text" href="https://www.digitaltrends.com/computing/intel-core-ultra-naming-explained/">"Confused about Core Ultra? We were too, so we asked Intel"</a>. <i>Digital Trends</i><span class="reference-accessdate">. Retrieved <span class="nowrap">May 12,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Digital+Trends&rft.atitle=Confused+about+Core+Ultra%3F+We+were+too%2C+so+we+asked+Intel&rft.date=2023-12-14&rft.aulast=Roach&rft.aufirst=Jacob&rft_id=https%3A%2F%2Fwww.digitaltrends.com%2Fcomputing%2Fintel-core-ultra-naming-explained%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Gomes-2022-126"><span class="mw-cite-backlink">^ <a href="#cite_ref-Gomes-2022_126-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Gomes-2022_126-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGomesMorganPhelpsWilson2022" class="citation book cs1">Gomes, Wilfred; Morgan, Slade; Phelps, Boyd; Wilson, Tim; Hallnor, Erik (2022). "Meteor Lake and Arrow Lake Intel Next-Gen 3D Client Architecture Platform with Foveros". <i>2022 IEEE Hot Chips 34 Symposium (HCS)</i>. pp. 1–40. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FHCS55958.2022.9895532">10.1109/HCS55958.2022.9895532</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-6654-6028-6" title="Special:BookSources/978-1-6654-6028-6"><bdi>978-1-6654-6028-6</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:252551808">252551808</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=Meteor+Lake+and+Arrow+Lake+Intel+Next-Gen+3D+Client+Architecture+Platform+with+Foveros&rft.btitle=2022+IEEE+Hot+Chips+34+Symposium+%28HCS%29&rft.pages=1-40&rft.date=2022&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A252551808%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FHCS55958.2022.9895532&rft.isbn=978-1-6654-6028-6&rft.aulast=Gomes&rft.aufirst=Wilfred&rft.au=Morgan%2C+Slade&rft.au=Phelps%2C+Boyd&rft.au=Wilson%2C+Tim&rft.au=Hallnor%2C+Erik&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Intel-AI-PC-2023-127"><span class="mw-cite-backlink"><b><a href="#cite_ref-Intel-AI-PC-2023_127-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/core-ultra-client-computing-news-1.html">"Intel Core Ultra Ushers in the Age of the AI PC"</a>. <i>Intel</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231214150505/https://www.intel.com/content/www/us/en/newsroom/news/core-ultra-client-computing-news-1.html">Archived</a> from the original on December 14, 2023<span class="reference-accessdate">. Retrieved <span class="nowrap">December 14,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Intel&rft.atitle=Intel+Core+Ultra+Ushers+in+the+Age+of+the+AI+PC&rft_id=https%3A%2F%2Fwww.intel.com%2Fcontent%2Fwww%2Fus%2Fen%2Fnewsroom%2Fnews%2Fcore-ultra-client-computing-news-1.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Intel-Corporation-SoC-40-years-2004-128"><span class="mw-cite-backlink"><b><a href="#cite_ref-Intel-Corporation-SoC-40-years-2004_128-0">^</a></b></span> <span class="reference-text">Intel Corporation, "<a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/newsroom/news/blank-sheet-opens-intels-new-soc-design.html">The 'Blank Sheet' that Delivered Intel's Most Significant SoC Design Change in 40 Years</a>", January, 17, 2004.</span> </li> <li id="cite_note-129"><span class="mw-cite-backlink"><b><a href="#cite_ref-129">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFTemsamani2022" class="citation web cs1">Temsamani, Fahd (August 24, 2022). <a rel="nofollow" class="external text" href="https://www.club386.com/intel-reveals-key-details-about-3d-foveros-chip-design-on-meteor-lake/">"Intel reveals key details about 3D Foveros chip design on Meteor Lake"</a>. <i>Club386</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240523145155/https://www.club386.com/intel-reveals-key-details-about-3d-foveros-chip-design-on-meteor-lake/">Archived</a> from the original on May 23, 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Club386&rft.atitle=Intel+reveals+key+details+about+3D+Foveros+chip+design+on+Meteor+Lake&rft.date=2022-08-24&rft.aulast=Temsamani&rft.aufirst=Fahd&rft_id=https%3A%2F%2Fwww.club386.com%2Fintel-reveals-key-details-about-3d-foveros-chip-design-on-meteor-lake%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-130"><span class="mw-cite-backlink"><b><a href="#cite_ref-130">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDeutscher2022" class="citation web cs1">Deutscher, Maria (July 25, 2022). <a rel="nofollow" class="external text" href="https://siliconangle.com/2022/07/25/intel-produce-chips-mediatek-part-new-partnership/">"Intel to produce chips for MediaTek as part of new partnership"</a>. <i>Silicon Angle</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240716124232/https://siliconangle.com/2022/07/25/intel-produce-chips-mediatek-part-new-partnership/">Archived</a> from the original on July 16, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Silicon+Angle&rft.atitle=Intel+to+produce+chips+for+MediaTek+as+part+of+new+partnership&rft.date=2022-07-25&rft.aulast=Deutscher&rft.aufirst=Maria&rft_id=https%3A%2F%2Fsiliconangle.com%2F2022%2F07%2F25%2Fintel-produce-chips-mediatek-part-new-partnership%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-131"><span class="mw-cite-backlink"><b><a href="#cite_ref-131">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMehta2019" class="citation web cs1">Mehta, Rich (February 5, 2019). <a rel="nofollow" class="external text" href="https://www.semiconductor-digest.com/intel-announces-tweaks-to-22ffl-process-for-rf-mram-at-iedm18/">"Intel announces tweaks to 22FFL process for RF, MRAM at IEDM18"</a>. <i>Semiconductor Digest</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240716124233/https://www.semiconductor-digest.com/intel-announces-tweaks-to-22ffl-process-for-rf-mram-at-iedm18/">Archived</a> from the original on July 16, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Semiconductor+Digest&rft.atitle=Intel+announces+tweaks+to+22FFL+process+for+RF%2C+MRAM+at+IEDM18&rft.date=2019-02-05&rft.aulast=Mehta&rft.aufirst=Rich&rft_id=https%3A%2F%2Fwww.semiconductor-digest.com%2Fintel-announces-tweaks-to-22ffl-process-for-rf-mram-at-iedm18%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-132"><span class="mw-cite-backlink"><b><a href="#cite_ref-132">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2023" class="citation web cs1">Alcorn, Paul (April 27, 2023). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intels-meteor-lake-begins-production-launches-this-year-on-intel-4-process">"Intel's Meteor Lake, Its First PC Chips With TSMC Tech, Launch This Year"</a>. <i>Tom's Hardware</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240716124233/https://www.tomshardware.com/news/intels-meteor-lake-begins-production-launches-this-year-on-intel-4-process">Archived</a> from the original on July 16, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel%27s+Meteor+Lake%2C+Its+First+PC+Chips+With+TSMC+Tech%2C+Launch+This+Year&rft.date=2023-04-27&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintels-meteor-lake-begins-production-launches-this-year-on-intel-4-process&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Alcorn_2023-09-19-133"><span class="mw-cite-backlink"><b><a href="#cite_ref-Alcorn_2023-09-19_133-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2023" class="citation web cs1">Alcorn, Paul (September 19, 2023). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14">"Intel Details Core Ultra 'Meteor Lake' Architecture, Launches December 14"</a>. <i>Tom's Hardware</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240608203738/https://www.tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14">Archived</a> from the original on June 8, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=Intel+Details+Core+Ultra+%27Meteor+Lake%27+Architecture%2C+Launches+December+14&rft.date=2023-09-19&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Fintel-details-core-ultra-meteor-lake-architecture-launches-december-14&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-Zuhair-134"><span class="mw-cite-backlink"><b><a href="#cite_ref-Zuhair_134-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFZuhair2023" class="citation web cs1">Zuhair, Muhammad (August 28, 2023). <a rel="nofollow" class="external text" href="https://wccftech.com/intel-could-dish-out-an-estimated-365000-next-gen-meteor-lake-cpu-tiles-per-month/">"Intel Could Dish Out An Estimated 365,000 Next-Gen Meteor Lake CPU Tiles Per Month"</a>. <i>Wccftech</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240405142059/https://wccftech.com/intel-could-dish-out-an-estimated-365000-next-gen-meteor-lake-cpu-tiles-per-month/">Archived</a> from the original on April 5, 2024<span class="reference-accessdate">. Retrieved <span class="nowrap">May 23,</span> 2024</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Wccftech&rft.atitle=Intel+Could+Dish+Out+An+Estimated+365%2C000+Next-Gen+Meteor+Lake+CPU+Tiles+Per+Month&rft.date=2023-08-28&rft.aulast=Zuhair&rft.aufirst=Muhammad&rft_id=https%3A%2F%2Fwccftech.com%2Fintel-could-dish-out-an-estimated-365000-next-gen-meteor-lake-cpu-tiles-per-month%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIntel+Core" class="Z3988"></span></span> </li> <li id="cite_note-139"><span class="mw-cite-backlink"><b><a href="#cite_ref-139">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external free" href="https://chipsandcheese.com/2024/09/27/lion-cove-intels-p-core-roars/">https://chipsandcheese.com/2024/09/27/lion-cove-intels-p-core-roars/</a></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Intel_Core&action=edit&section=73" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output .side-box-abovebelow,.mw-parser-output .side-box-text{padding:0.25em 0.9em}.mw-parser-output .side-box-image{padding:2px 0 2px 0.9em;text-align:center}.mw-parser-output .side-box-imageright{padding:2px 0.9em 2px 0;text-align:center}@media(min-width:500px){.mw-parser-output .side-box-flex{display:flex;align-items:center}.mw-parser-output .side-box-text{flex:1;min-width:0}}@media(min-width:720px){.mw-parser-output .side-box{width:238px}.mw-parser-output .side-box-right{clear:right;float:right;margin-left:1em}.mw-parser-output .side-box-left{margin-right:1em}}</style><style data-mw-deduplicate="TemplateStyles:r1237033735">@media print{body.ns-0 .mw-parser-output .sistersitebox{display:none!important}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}</style><div class="side-box side-box-right plainlinks sistersitebox"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"> <div class="side-box-flex"> <div class="side-box-image"><span class="noviewer" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/30px-Commons-logo.svg.png" decoding="async" width="30" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/45px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/59px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></span></span></div> <div class="side-box-text plainlist">Wikimedia Commons has media related to <wbr /><i><b><a href="https://commons.wikimedia.org/wiki/Category:Intel_Core_2_Duo" class="extiw" title="commons:Category:Intel Core 2 Duo">Intel Core 2 Duo</a></b></i>, <wbr /><i><b><a href="https://commons.wikimedia.org/wiki/Category:Intel_Core_2_Quad" class="extiw" title="commons:Category:Intel Core 2 Quad">Intel Core 2 Quad</a></b></i>, <wbr /><i><b><a href="https://commons.wikimedia.org/wiki/Category:Intel_Core_i5" class="extiw" title="commons:Category:Intel Core i5">Intel Core i5</a></b></i> and <wbr /><i><b><a href="https://commons.wikimedia.org/wiki/Category:Intel_Core_i7" class="extiw" title="commons:Category:Intel Core i7">Intel Core i7</a></b></i>.</div></div> </div> <ul><li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070809234956/http://balusc.xs4all.nl/srv/har-cpu-int-c1.php">Intel Core technical specifications</a> at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> (archived August 9, 2007)</li> <li><a rel="nofollow" class="external text" href="http://www.techpowerup.com/cpudb/">CPU Database</a>. TechPowerUp.</li> <li><a rel="nofollow" class="external text" href="http://www.anandtech.com/show/1900">Intel Core Duo (Yonah) Performance Preview – Part II</a> vs AMD 64 X2 and Intel Pentium M. Anandtech.</li> <li><a rel="nofollow" class="external text" href="http://www.hardinfo-benchmark.com/compare/CPU-Processor/73/intel-core-i7-3960x-cpu-330ghz-review">Intel Core i7-3960X CPU Performance Comparison</a></li> <li><a rel="nofollow" class="external text" href="http://www.intel.com/technology/itj/2006/volume10issue02/index.htm">Intel Centrino Duo Mobile Technology papers</a>. Intel.</li> <li><a rel="nofollow" class="external text" href="http://ark.intel.com/#@Processors">Intel Product Information</a>, providing a list of various processor generations</li></ul> <table class="wikitable succession-box noprint" style="margin:0.5em auto; font-size:small;clear:both;"> <tbody><tr style="text-align:center;"> <td style="width:30%;" rowspan="1">Preceded by<div style="font-weight: bold"><a href="/wiki/Pentium" title="Pentium">Pentium</a></div> </td> <td style="width: 40%; text-align: center;" rowspan="1"><b> Intel Core </b><br />2006–present </td></tr></tbody></table> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1236075235">.mw-parser-output .navbox{box-sizing:border-box;border:1px solid #a2a9b1;width:100%;clear:both;font-size:88%;text-align:center;padding:1px;margin:1em auto 0}.mw-parser-output .navbox .navbox{margin-top:0}.mw-parser-output .navbox+.navbox,.mw-parser-output .navbox+.navbox-styles+.navbox{margin-top:-1px}.mw-parser-output .navbox-inner,.mw-parser-output .navbox-subgroup{width:100%}.mw-parser-output .navbox-group,.mw-parser-output .navbox-title,.mw-parser-output .navbox-abovebelow{padding:0.25em 1em;line-height:1.5em;text-align:center}.mw-parser-output .navbox-group{white-space:nowrap;text-align:right}.mw-parser-output .navbox,.mw-parser-output .navbox-subgroup{background-color:#fdfdfd}.mw-parser-output .navbox-list{line-height:1.5em;border-color:#fdfdfd}.mw-parser-output .navbox-list-with-group{text-align:left;border-left-width:2px;border-left-style:solid}.mw-parser-output tr+tr>.navbox-abovebelow,.mw-parser-output tr+tr>.navbox-group,.mw-parser-output tr+tr>.navbox-image,.mw-parser-output tr+tr>.navbox-list{border-top:2px solid #fdfdfd}.mw-parser-output .navbox-title{background-color:#ccf}.mw-parser-output .navbox-abovebelow,.mw-parser-output .navbox-group,.mw-parser-output .navbox-subgroup .navbox-title{background-color:#ddf}.mw-parser-output .navbox-subgroup .navbox-group,.mw-parser-output .navbox-subgroup .navbox-abovebelow{background-color:#e6e6ff}.mw-parser-output .navbox-even{background-color:#f7f7f7}.mw-parser-output .navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Intel_processors" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Intel_processors" title="Template:Intel processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel_processors" title="Template talk:Intel processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel_processors" title="Special:EditPage/Template:Intel processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel_processors" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a class="mw-selflink selflink">Core</a> <ul><li><a class="mw-selflink-fragment" href="#10th_generation">10th gen</a></li> <li><a class="mw-selflink-fragment" href="#11th_generation">11th gen</a></li> <li><a class="mw-selflink-fragment" href="#12th_generation">12th gen</a></li> <li><a class="mw-selflink-fragment" href="#13th_generation">13th gen</a></li> <li><a class="mw-selflink-fragment" href="#14th_generation">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a href="/wiki/I486" title="I486">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a class="mw-selflink selflink">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a class="mw-selflink selflink">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a class="mw-selflink-fragment" href="#1st_generation">1st gen</a></li> <li><a class="mw-selflink-fragment" href="#2nd_generation">2nd gen</a></li> <li><a class="mw-selflink-fragment" href="#3rd_generation">3rd gen</a></li> <li><a class="mw-selflink-fragment" href="#4th_generation">4th gen</a></li> <li><a class="mw-selflink-fragment" href="#5th_generation">5th gen</a></li> <li><a class="mw-selflink-fragment" href="#6th_generation">6th gen</a></li> <li><a class="mw-selflink-fragment" href="#7th_generation">7th gen</a></li> <li><a class="mw-selflink-fragment" href="#8th_generation">8th gen</a></li> <li><a class="mw-selflink-fragment" href="#9th_generation">9th gen</a></li> <li><a class="mw-selflink-fragment" href="#10th_generation">10th gen</a></li> <li><a class="mw-selflink-fragment" href="#11th_generation">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" href="https://en.wikipedia.org/w/index.php?title=Intel_Core&oldid=1259288623#Core_i3/i5/i7/i9">https://en.wikipedia.org/w/index.php?title=Intel_Core&oldid=1259288623#Core_i3/i5/i7/i9</a>"</div></div> <div id="catlinks" class="catlinks" data-mw="interface"><div id="mw-normal-catlinks" class="mw-normal-catlinks"><a href="/wiki/Help:Category" title="Help:Category">Categories</a>: <ul><li><a href="/wiki/Category:Intel_x86_microprocessors" title="Category:Intel x86 microprocessors">Intel x86 microprocessors</a></li><li><a href="/wiki/Category:Computer-related_introductions_in_2006" title="Category:Computer-related introductions in 2006">Computer-related introductions in 2006</a></li><li><a href="/wiki/Category:64-bit_microprocessors" title="Category:64-bit microprocessors">64-bit microprocessors</a></li></ul></div><div id="mw-hidden-catlinks" class="mw-hidden-catlinks mw-hidden-cats-hidden">Hidden categories: <ul><li><a href="/wiki/Category:CS1_maint:_unfit_URL" title="Category:CS1 maint: unfit URL">CS1 maint: unfit URL</a></li><li><a href="/wiki/Category:Webarchive_template_wayback_links" title="Category:Webarchive template wayback links">Webarchive template wayback links</a></li><li><a href="/wiki/Category:Articles_with_short_description" title="Category:Articles with short description">Articles with short description</a></li><li><a href="/wiki/Category:Short_description_is_different_from_Wikidata" title="Category:Short description is different from Wikidata">Short description is different from Wikidata</a></li><li><a href="/wiki/Category:Use_mdy_dates_from_October_2018" title="Category:Use mdy dates from October 2018">Use mdy dates from October 2018</a></li><li><a href="/wiki/Category:Use_American_English_from_October_2020" title="Category:Use American English from October 2020">Use American English from October 2020</a></li><li><a href="/wiki/Category:All_Wikipedia_articles_written_in_American_English" title="Category:All Wikipedia articles written in American English">All Wikipedia articles written in American English</a></li><li><a href="/wiki/Category:All_articles_with_unsourced_statements" title="Category:All articles with unsourced statements">All articles with unsourced statements</a></li><li><a href="/wiki/Category:Articles_with_unsourced_statements_from_October_2011" title="Category:Articles with unsourced statements from October 2011">Articles with unsourced statements from October 2011</a></li><li><a href="/wiki/Category:Articles_to_be_expanded_from_April_2014" title="Category:Articles to be expanded from April 2014">Articles to be expanded from April 2014</a></li><li><a href="/wiki/Category:All_articles_to_be_expanded" title="Category:All articles to be expanded">All articles to be expanded</a></li><li><a href="/wiki/Category:Articles_to_be_expanded_from_January_2017" title="Category:Articles to be expanded from January 2017">Articles to be expanded from January 2017</a></li><li><a href="/wiki/Category:Articles_with_unsourced_statements_from_July_2018" title="Category:Articles with unsourced statements from July 2018">Articles with unsourced statements from July 2018</a></li><li><a href="/wiki/Category:All_articles_that_may_contain_original_research" title="Category:All articles that may contain original research">All articles that may contain original research</a></li><li><a href="/wiki/Category:Articles_that_may_contain_original_research_from_June_2024" title="Category:Articles that may contain original research from June 2024">Articles that may contain original research from June 2024</a></li><li><a href="/wiki/Category:Articles_to_be_expanded_from_October_2024" title="Category:Articles to be expanded from October 2024">Articles to be expanded from October 2024</a></li><li><a href="/wiki/Category:Articles_with_empty_sections_from_October_2024" title="Category:Articles with empty sections from October 2024">Articles with empty sections from October 2024</a></li><li><a href="/wiki/Category:All_articles_with_empty_sections" title="Category:All articles with empty sections">All articles with empty sections</a></li><li><a href="/wiki/Category:Articles_to_be_expanded_from_January_2023" title="Category:Articles to be expanded from January 2023">Articles to be expanded from January 2023</a></li><li><a href="/wiki/Category:Articles_with_excerpts" title="Category:Articles with excerpts">Articles with excerpts</a></li></ul></div></div> </div> </main> </div> <div class="mw-footer-container"> <footer id="footer" class="mw-footer" > <ul id="footer-info"> <li id="footer-info-lastmod"> This page was last edited on 24 November 2024, at 10:20<span class="anonymous-show"> (UTC)</span>.</li> <li id="footer-info-copyright">Text is available under the <a href="/wiki/Wikipedia:Text_of_the_Creative_Commons_Attribution-ShareAlike_4.0_International_License" title="Wikipedia:Text of the Creative Commons Attribution-ShareAlike 4.0 International License">Creative Commons Attribution-ShareAlike 4.0 License</a>; additional terms may apply. By using this site, you agree to the <a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Terms_of_Use" class="extiw" title="foundation:Special:MyLanguage/Policy:Terms of Use">Terms of Use</a> and <a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Privacy_policy" class="extiw" title="foundation:Special:MyLanguage/Policy:Privacy policy">Privacy Policy</a>. Wikipedia® is a registered trademark of the <a rel="nofollow" class="external text" href="https://wikimediafoundation.org/">Wikimedia Foundation, Inc.</a>, a non-profit organization.</li> </ul> <ul id="footer-places"> <li id="footer-places-privacy"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Privacy_policy">Privacy policy</a></li> <li id="footer-places-about"><a href="/wiki/Wikipedia:About">About Wikipedia</a></li> <li id="footer-places-disclaimers"><a href="/wiki/Wikipedia:General_disclaimer">Disclaimers</a></li> <li id="footer-places-contact"><a href="//en.wikipedia.org/wiki/Wikipedia:Contact_us">Contact Wikipedia</a></li> <li id="footer-places-wm-codeofconduct"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Universal_Code_of_Conduct">Code of Conduct</a></li> <li id="footer-places-developers"><a href="https://developer.wikimedia.org">Developers</a></li> <li id="footer-places-statslink"><a href="https://stats.wikimedia.org/#/en.wikipedia.org">Statistics</a></li> <li id="footer-places-cookiestatement"><a href="https://foundation.wikimedia.org/wiki/Special:MyLanguage/Policy:Cookie_statement">Cookie statement</a></li> <li id="footer-places-mobileview"><a href="//en.m.wikipedia.org/w/index.php?title=Intel_Core&mobileaction=toggle_view_mobile#Core_i3/i5/i7/i9" class="noprint stopMobileRedirectToggle">Mobile view</a></li> </ul> <ul id="footer-icons" class="noprint"> <li id="footer-copyrightico"><a href="https://wikimediafoundation.org/" class="cdx-button cdx-button--fake-button cdx-button--size-large cdx-button--fake-button--enabled"><img src="/static/images/footer/wikimedia-button.svg" width="84" height="29" alt="Wikimedia Foundation" loading="lazy"></a></li> <li id="footer-poweredbyico"><a href="https://www.mediawiki.org/" class="cdx-button cdx-button--fake-button cdx-button--size-large cdx-button--fake-button--enabled"><img src="/w/resources/assets/poweredby_mediawiki.svg" alt="Powered by MediaWiki" width="88" height="31" loading="lazy"></a></li> </ul> </footer> </div> </div> </div> <div class="vector-settings" id="p-dock-bottom"> <ul></ul> </div><script>(RLQ=window.RLQ||[]).push(function(){mw.config.set({"wgHostname":"mw-web.codfw.main-cc877b49b-8992z","wgBackendResponseTime":238,"wgPageParseReport":{"limitreport":{"cputime":"2.132","walltime":"2.422","ppvisitednodes":{"value":15693,"limit":1000000},"postexpandincludesize":{"value":399210,"limit":2097152},"templateargumentsize":{"value":13223,"limit":2097152},"expansiondepth":{"value":20,"limit":100},"expensivefunctioncount":{"value":37,"limit":500},"unstrip-depth":{"value":1,"limit":20},"unstrip-size":{"value":510865,"limit":5000000},"entityaccesscount":{"value":0,"limit":400},"timingprofile":["100.00% 1780.409 1 -total"," 43.44% 773.341 7 Template:Reflist"," 29.22% 520.175 96 Template:Cite_web"," 7.34% 130.672 1 Template:Infobox_CPU"," 6.95% 123.706 1 Template:Infobox"," 6.50% 115.731 1 Template:Short_description"," 5.85% 104.168 26 Template:Cite_news"," 4.37% 77.855 4 Template:Navbox"," 4.19% 74.666 1 Template:Intel_processors"," 4.17% 74.253 86 Template:Abbr"]},"scribunto":{"limitreport-timeusage":{"value":"1.046","limit":"10.000"},"limitreport-memusage":{"value":8471731,"limit":52428800},"limitreport-profile":[["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::callParserFunction","320","30.8"],["?","160","15.4"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::find","120","11.5"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::getExpandedArgument","60","5.8"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::gsub","60","5.8"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::sub","40","3.8"],["dataWrapper \u003Cmw.lua:672\u003E","40","3.8"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::getExpensiveData","40","3.8"],["chunk \u003CModule:Citation/CS1\u003E","40","3.8"],["MediaWiki\\Extension\\Scribunto\\Engines\\LuaSandbox\\LuaSandboxCallback::match","20","1.9"],["[others]","140","13.5"]]},"cachereport":{"origin":"mw-web.eqiad.main-5dc468848-qr567","timestamp":"20241124102020","ttl":567586,"transientcontent":true}}});});</script> <script type="application/ld+json">{"@context":"https:\/\/schema.org","@type":"Article","name":"Intel Core","url":"https:\/\/en.wikipedia.org\/wiki\/Intel_Core#Core_i3\/i5\/i7\/i9","sameAs":"http:\/\/www.wikidata.org\/entity\/Q19481932","mainEntity":"http:\/\/www.wikidata.org\/entity\/Q19481932","author":{"@type":"Organization","name":"Contributors to Wikimedia projects"},"publisher":{"@type":"Organization","name":"Wikimedia Foundation, Inc.","logo":{"@type":"ImageObject","url":"https:\/\/www.wikimedia.org\/static\/images\/wmf-hor-googpub.png"}},"datePublished":"2009-10-01T14:41:06Z","dateModified":"2024-11-24T10:20:07Z","image":"https:\/\/upload.wikimedia.org\/wikipedia\/commons\/2\/28\/Intel_Core_2023_logo.png","headline":"processor brand by Intel"}</script> </body> </html>