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Designing a Cyclic Redundancy Checker-8 for 32 Bit Input Using VHDL
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Most of the modern communication protocols use some error detection algorithms in digital networks and storage devices to detect accidental changes to raw data between transmission and reception. Cyclic Redundancy Check, or CRC, is the most popular one among these error detection codes. CRC properties are defined by the generator polynomial length and coefficients. The aim of this project is to implement an efficient FPGA based CRC-8 that accepts a 32 bit input, taking into consideration optimal chip area and high performance, using VHDL. The proposed architecture is implemented on Xilinx ISE Simulator. It is designed while keeping in mind the hardware design, complexity and cost factor. <iframe src="https://publications.waset.org/abstracts/10861.pdf" style="width:100%; height:400px;" frameborder="0"></iframe> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=cyclic%20redundancy%20checker" title="cyclic redundancy checker">cyclic redundancy checker</a>, <a href="https://publications.waset.org/abstracts/search?q=CRC-8" title=" CRC-8"> CRC-8</a>, <a href="https://publications.waset.org/abstracts/search?q=32-bit%20input" title=" 32-bit input"> 32-bit input</a>, <a href="https://publications.waset.org/abstracts/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/abstracts/search?q=VHDL" title=" VHDL"> VHDL</a>, <a href="https://publications.waset.org/abstracts/search?q=ModelSim" title=" ModelSim"> ModelSim</a>, <a href="https://publications.waset.org/abstracts/search?q=Xilinx" title=" Xilinx"> Xilinx</a> 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