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is-small is-link">Go</button> </div> </div> </form> </div> </div> <ol class="breathe-horizontal" start="1"> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.12592">arXiv:2408.12592</a> <span> [<a href="https://arxiv.org/pdf/2408.12592">pdf</a>, <a href="https://arxiv.org/format/2408.12592">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Exposing Shadow Branches </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Pepi%2C+C">Chrysanthos Pepi</a>, <a href="/search/cs?searchtype=author&query=Godala%2C+B+R">Bhargav Reddy Godala</a>, <a href="/search/cs?searchtype=author&query=Tibrewala%2C+K">Krishnam Tibrewala</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=Jim%C3%A9nez%2C+D+A">Daniel A. Jim茅nez</a>, <a href="/search/cs?searchtype=author&query=Pokam%2C+G+A">Gilles A. Pokam</a>, <a href="/search/cs?searchtype=author&query=August%2C+D+I">David I. August</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.12592v1-abstract-short" style="display: inline;"> Modern processors implement a decoupled front-end in the form of Fetch Directed Instruction Prefetching (FDIP) to avoid front-end stalls. FDIP is driven by the Branch Prediction Unit (BPU), relying on the BPU's accuracy and branch target tracking structures to speculatively fetch instructions into the Instruction Cache (L1I). As data center applications become more complex, their code footprints a… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.12592v1-abstract-full').style.display = 'inline'; document.getElementById('2408.12592v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.12592v1-abstract-full" style="display: none;"> Modern processors implement a decoupled front-end in the form of Fetch Directed Instruction Prefetching (FDIP) to avoid front-end stalls. FDIP is driven by the Branch Prediction Unit (BPU), relying on the BPU's accuracy and branch target tracking structures to speculatively fetch instructions into the Instruction Cache (L1I). As data center applications become more complex, their code footprints also grow, resulting in an increase in Branch Target Buffer (BTB) misses. FDIP can alleviate L1I cache misses, but when it encounters a BTB miss, the BPU may not identify the current instruction as a branch to FDIP. This can prevent FDIP from prefetching or cause it to speculate down the wrong path, further polluting the L1I cache. We observe that the vast majority, 75%, of BTB-missing, unidentified branches are actually present in instruction cache lines that FDIP has previously fetched but, these missing branches have not yet been decoded and inserted into the BTB. This is because the instruction line is decoded from an entry point (which is the target of the previous taken branch) till an exit point (the taken branch). Branch instructions present in the ignored portion of the cache line we call them "Shadow Branches". Here we present Skeia, a novel shadow branch decoding technique that identifies and decodes unused bytes in cache lines fetched by FDIP, inserting them into a Shadow Branch Buffer (SBB). The SBB is accessed in parallel with the BTB, allowing FDIP to speculate despite a BTB miss. With a minimal storage state of 12.25KB, Skeia delivers a geomean speedup of ~5.7% over an 8K-entry BTB (78KB) and ~2% versus adding an equal amount of state to the BTB across 16 front-end bound applications. Since many branches stored in the SBB are unique compared to those in a similarly sized BTB, we consistently observe greater performance gains with Skeia across all examined sizes until saturation. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.12592v1-abstract-full').style.display = 'none'; document.getElementById('2408.12592v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 22 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">13 pages, 16 figures, Submitted to ASPLOS 2025</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.05912">arXiv:2408.05912</a> <span> [<a href="https://arxiv.org/pdf/2408.05912">pdf</a>, <a href="https://arxiv.org/format/2408.05912">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Correct Wrong Path </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Godala%2C+B+R">Bhargav Reddy Godala</a>, <a href="/search/cs?searchtype=author&query=Ramesh%2C+S+P">Sankara Prasad Ramesh</a>, <a href="/search/cs?searchtype=author&query=Tibrewala%2C+K">Krishnam Tibrewala</a>, <a href="/search/cs?searchtype=author&query=Pepi%2C+C">Chrysanthos Pepi</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Kanev%2C+S">Svilen Kanev</a>, <a href="/search/cs?searchtype=author&query=Pokam%2C+G+A">Gilles A. Pokam</a>, <a href="/search/cs?searchtype=author&query=Jim%C3%A9nez%2C+D+A">Daniel A. Jim茅nez</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=August%2C+D+I">David I. August</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.05912v1-abstract-short" style="display: inline;"> Modern OOO CPUs have very deep pipelines with large branch misprediction recovery penalties. Speculatively executed instructions on the wrong path can significantly change cache state, depending on speculation levels. Architects often employ trace-driven simulation models in the design exploration stage, which sacrifice precision for speed. Trace-driven simulators are orders of magnitude faster th… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.05912v1-abstract-full').style.display = 'inline'; document.getElementById('2408.05912v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.05912v1-abstract-full" style="display: none;"> Modern OOO CPUs have very deep pipelines with large branch misprediction recovery penalties. Speculatively executed instructions on the wrong path can significantly change cache state, depending on speculation levels. Architects often employ trace-driven simulation models in the design exploration stage, which sacrifice precision for speed. Trace-driven simulators are orders of magnitude faster than execution-driven models, reducing the often hundreds of thousands of simulation hours needed to explore new micro-architectural ideas. Despite this strong benefit of trace-driven simulation, these often fail to adequately model the consequences of wrong path because obtaining them is nontrivial. Prior works consider either a positive or negative impact of wrong path but not both. Here, we examine wrong path execution in simulation results and design a set of infrastructure for enabling wrong-path execution in a trace driven simulator. Our analysis shows the wrong path affects structures on both the instruction and data sides extensively, resulting in performance variations ranging from $-3.05$\% to $20.9$\% when ignoring wrong path. To benefit the research community and enhance the accuracy of simulators, we opened our traces and tracing utility in the hopes that industry can provide wrong-path traces generated by their internal simulators, enabling academic simulation without exposing industry IP. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.05912v1-abstract-full').style.display = 'none'; document.getElementById('2408.05912v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 11 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">5 pages, 7 Figures, Submited to Computer Architecture Letters</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2210.14324">arXiv:2210.14324</a> <span> [<a href="https://arxiv.org/pdf/2210.14324">pdf</a>, <a href="https://arxiv.org/format/2210.14324">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> The Championship Simulator: Architectural Simulation for Education and Competition </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Gober%2C+N">Nathan Gober</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+L">Lei Wang</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=Jimenez%2C+D+A">Daniel A. Jimenez</a>, <a href="/search/cs?searchtype=author&query=Teran%2C+E">Elvira Teran</a>, <a href="/search/cs?searchtype=author&query=Pugsley%2C+S">Seth Pugsley</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+J">Jinchun Kim</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2210.14324v1-abstract-short" style="display: inline;"> Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their par… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.14324v1-abstract-full').style.display = 'inline'; document.getElementById('2210.14324v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2210.14324v1-abstract-full" style="display: none;"> Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their particular expertise as black boxes. Second, with increasing complexity, the field becomes decreasingly accessible to new students of the field. When learning core microarchitecture, new students must first learn the big picture of how the system works in order to understand how the pieces all fit together. The tools used to study microarchitecture experience a similar struggle. As with the microarchitectures they simulate, an increase in complexity reduces accessibility to new users. In this work, we present ChampSim. ChampSim uses a modular design and configurable structure to achieve a low barrier to entry into the field of microarchitecural simulation. ChampSim has shown itself to be useful in multiple areas of research, competition, and education. In this way, we seek to promote access and inclusion despite the increasing complexity of the field of computer architecture. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.14324v1-abstract-full').style.display = 'none'; document.getElementById('2210.14324v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 October, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2210.00058">arXiv:2210.00058</a> <span> [<a href="https://arxiv.org/pdf/2210.00058">pdf</a>, <a href="https://arxiv.org/format/2210.00058">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Cryptography and Security">cs.CR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Chacon%2C+G+A">Gino A. Chacon</a>, <a href="/search/cs?searchtype=author&query=Williams%2C+C">Charles Williams</a>, <a href="/search/cs?searchtype=author&query=Knechtel%2C+J">Johann Knechtel</a>, <a href="/search/cs?searchtype=author&query=Sinanoglu%2C+O">Ozgur Sinanoglu</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2210.00058v1-abstract-short" style="display: inline;"> As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify dat… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.00058v1-abstract-full').style.display = 'inline'; document.getElementById('2210.00058v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2210.00058v1-abstract-full" style="display: none;"> As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify data in memory that was never touched and is not owned by the chiplet which contains the Trojan. Further, the Trojan need not even be physically between the victim and the memory controller to attack the victim's memory transactions. Here, we explore the fundamental attack vectors possible in chiplet-based systems and provide an example Trojan implementation capable of directly modifying victim data in memory. This work aims to highlight the need for developing mechanisms that can protect and secure the coherence scheme from these forms of attacks. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.00058v1-abstract-full').style.display = 'none'; document.getElementById('2210.00058v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 30 September, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2105.02917">arXiv:2105.02917</a> <span> [<a href="https://arxiv.org/pdf/2105.02917">pdf</a>, <a href="https://arxiv.org/format/2105.02917">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Cryptography and Security">cs.CR</span> </div> </div> <p class="title is-5 mathjax"> Coherence Attacks and Countermeasures in Interposer-Based Systems </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Mandal%2C+T">Tapojyoti Mandal</a>, <a href="/search/cs?searchtype=author&query=Knechtel%2C+J">Johann Knechtel</a>, <a href="/search/cs?searchtype=author&query=Sinanoglu%2C+O">Ozgur Sinanoglu</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P">Paul Gratz</a>, <a href="/search/cs?searchtype=author&query=Soteriou%2C+V">Vassos Soteriou</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2105.02917v2-abstract-short" style="display: inline;"> Industry is moving towards large-scale systems where processor cores, memories, accelerators, etc.\ are bundled via 2.5D integration. These various components are fabricated separately as chiplets and then integrated using an interconnect carrier, a so-called interposer. This new design style provides benefits in terms of yield as well as economies of scale, as chiplets may come from various third… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2105.02917v2-abstract-full').style.display = 'inline'; document.getElementById('2105.02917v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2105.02917v2-abstract-full" style="display: none;"> Industry is moving towards large-scale systems where processor cores, memories, accelerators, etc.\ are bundled via 2.5D integration. These various components are fabricated separately as chiplets and then integrated using an interconnect carrier, a so-called interposer. This new design style provides benefits in terms of yield as well as economies of scale, as chiplets may come from various third-party vendors, and be integrated into one sophisticated system. The benefits of this approach, however, come at the cost of new challenges for the system's security and integrity when many third-party component chiplets, some from not fully trusted vendors, are integrated. Here, we explore these challenges, but also promises, for modern interposer-based systems of cache-coherent, multi-core chiplets. First, we introduce a new, coherence-based attack, GETXspy, wherein a single compromised chiplet can expose a high-bandwidth side/covert-channel in an ostensibly secure system. We further show that prior art is insufficient to stop this new attack. Second, we propose using an active interposer as generic, secure-by-construction platform that forms a physical root of trust for modern 2.5D systems. Our scheme has limited overhead, restricted to the active interposer, allowing the chiplets and the coherence system to remain untouched. We show that our scheme prevents a wide range of attacks, including but not limited to our GETXspy attack, with little overhead on system performance, $\sim$4\%. This overhead reduces as workloads increase, ensuring scalability of the scheme. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2105.02917v2-abstract-full').style.display = 'none'; document.getElementById('2105.02917v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 January, 2022; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 6 May, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2021. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1805.06864">arXiv:1805.06864</a> <span> [<a href="https://arxiv.org/pdf/1805.06864">pdf</a>, <a href="https://arxiv.org/ps/1805.06864">ps</a>, <a href="https://arxiv.org/format/1805.06864">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computer Science and Game Theory">cs.GT</span> </div> </div> <p class="title is-5 mathjax"> Resource allocation under uncertainty: an algebraic and qualitative treatment </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Camacho%2C+F">Franklin Camacho</a>, <a href="/search/cs?searchtype=author&query=Chac%C3%B3n%2C+G">Gerardo Chac贸n</a>, <a href="/search/cs?searchtype=author&query=Per%C3%A9z%2C+R+P">Ram贸n Pino Per茅z</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1805.06864v1-abstract-short" style="display: inline;"> We use an algebraic viewpoint, namely a matrix framework to deal with the problem of resource allocation under uncertainty in the context of a qualitative approach. Our basic qualitative data are a plausibility relation over the resources, a hierarchical relation over the agents and of course the preference that the agents have over the resources. With this data we propose a qualitative binary rel… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1805.06864v1-abstract-full').style.display = 'inline'; document.getElementById('1805.06864v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1805.06864v1-abstract-full" style="display: none;"> We use an algebraic viewpoint, namely a matrix framework to deal with the problem of resource allocation under uncertainty in the context of a qualitative approach. Our basic qualitative data are a plausibility relation over the resources, a hierarchical relation over the agents and of course the preference that the agents have over the resources. With this data we propose a qualitative binary relation $\unrhd$ between allocations such that $\mathcal{F}\unrhd \mathcal{G}$ has the following intended meaning: the allocation $\mathcal{F}$ produces more or equal social welfare than the allocation $\mathcal{G}$. We prove that there is a family of allocations which are maximal with respect to $\unrhd$. We prove also that there is a notion of simple deal such that optimal allocations can be reached by sequences of simple deals. Finally, we introduce some mechanism for discriminating {optimal} allocations. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1805.06864v1-abstract-full').style.display = 'none'; document.getElementById('1805.06864v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 May, 2018; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2018. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">MSC Class:</span> 90A80; 68T; 68T37; 68E; 90A06 </p> </li> </ol> <div class="is-hidden-tablet">  <span class="help" style="display: inline-block;"><a href="https://github.com/arXiv/arxiv-search/releases">Search v0.5.6 released 2020-02-24</a>  </span> </div> </div> </main> <footer> <div class="columns is-desktop" role="navigation" aria-label="Secondary">  <div class="column"> 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