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id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Hardware description language</div> <p> <b>VHDL-AMS</b> is a derivative of the <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> <a href="/wiki/VHDL" title="VHDL">VHDL</a> (IEEE 1076-2002). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-2017). </p><p>The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p>VHDL-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and <a href="/wiki/Radio_frequency" title="Radio frequency">radio frequency</a> integrated circuits. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Code_example">Code example</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL-AMS&action=edit&section=1" title="Edit section: Code example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In VHDL-AMS, a design consists at a minimum of an <i>entity</i> which describes the interface and an <i>architecture</i> which contains the actual implementation. In addition, most designs import library modules. Some designs also contain multiple architectures and <i>configurations</i>. </p><p>A simple ideal <a href="/wiki/Diode" title="Diode">diode</a> in VHDL-AMS would look something like this: </p> <div class="mw-highlight mw-highlight-lang-vhdl mw-content-ltr" dir="ltr"><pre><span></span><span class="k">library</span><span class="w"> </span><span class="nn">IEEE</span><span class="p">;</span> <span class="k">use</span><span class="w"> </span><span class="nn">IEEE.math_real.</span><span class="k">all</span><span class="p">;</span> <span class="k">use</span><span class="w"> </span><span class="nn">IEEE.electrical_systems.</span><span class="k">all</span><span class="p">;</span> <span class="c1">-- this is the entity</span> <span class="k">entity</span><span class="w"> </span><span class="nc">DIODE</span><span class="w"> </span><span class="k">is</span> <span class="w"> </span><span class="k">generic</span><span class="w"> </span><span class="p">(</span><span class="n">iss</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">current</span><span class="w"> </span><span class="o">:=</span><span class="w"> </span><span class="mi">1</span><span class="p">.</span><span class="mi">0</span><span class="n">e</span><span class="o">-</span><span class="mi">14</span><span class="p">);</span><span class="w"> </span> <span class="w"> </span><span class="k">port</span><span class="w"> </span><span class="p">(</span><span class="n">terminal</span><span class="w"> </span><span class="n">anode</span><span class="p">,</span><span class="w"> </span><span class="n">cathode</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">electrical</span><span class="p">);</span><span class="w"> </span> <span class="k">end</span><span class="w"> </span><span class="k">entity</span><span class="w"> </span><span class="nc">DIODE</span><span class="p">;</span> <span class="k">architecture</span><span class="w"> </span><span class="nc">IDEAL</span><span class="w"> </span><span class="k">of</span><span class="w"> </span><span class="nc">DIODE</span><span class="w"> </span><span class="k">is</span> <span class="w"> </span><span class="n">quantity</span><span class="w"> </span><span class="n">v</span><span class="w"> </span><span class="n">across</span><span class="w"> </span><span class="n">i</span><span class="w"> </span><span class="n">through</span><span class="w"> </span><span class="n">anode</span><span class="w"> </span><span class="k">to</span><span class="w"> </span><span class="n">cathode</span><span class="p">;</span> <span class="w"> </span><span class="k">constant</span><span class="w"> </span><span class="n">vt</span><span class="w"> </span><span class="o">:</span><span class="w"> </span><span class="n">voltage</span><span class="w"> </span><span class="o">:=</span><span class="w"> </span><span class="mi">0</span><span class="p">.</span><span class="mi">0258</span><span class="p">;</span><span class="w"> </span> <span class="k">begin</span> <span class="w"> </span><span class="n">i</span><span class="w"> </span><span class="o">==</span><span class="w"> </span><span class="n">iss</span><span class="w"> </span><span class="o">*</span><span class="w"> </span><span class="p">(</span><span class="n">exp</span><span class="p">(</span><span class="n">v</span><span class="o">/</span><span class="n">vt</span><span class="p">)</span><span class="w"> </span><span class="o">-</span><span class="w"> </span><span class="mi">1</span><span class="p">.</span><span class="mi">0</span><span class="p">);</span> <span class="k">end</span><span class="w"> </span><span class="k">architecture</span><span class="w"> </span><span class="nc">IDEAL</span><span class="p">;</span> </pre></div> <div class="mw-heading mw-heading2"><h2 id="VHDL-AMS_Simulators">VHDL-AMS Simulators</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL-AMS&action=edit&section=2" title="Edit section: VHDL-AMS Simulators"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/ANSYS" class="mw-redirect" title="ANSYS">ANSYS</a> Simplorer</li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a> Virtuoso AMS Designer</li> <li><a href="/wiki/Dolphin_Integration" title="Dolphin Integration">Dolphin Integration</a> SMASH</li> <li><a href="/wiki/Mentor_Graphics" title="Mentor Graphics">Mentor Graphics</a> Questa ADMS</li> <li>Mentor Graphics SystemVision</li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a> SaberRD</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL-AMS&action=edit&section=3" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text">Christen E., Bakalar K.,"VHDL-AMS-a hardware description language for analog and mixed-signal applications", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on] Volume 46, Issue 10, Oct. 1999, pp. 1263 - 1272.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=VHDL-AMS&action=edit&section=4" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">Verilog-AMS</a>, the Analog and Mixed Signal derivative of the <a href="/wiki/Verilog" title="Verilog">Verilog</a> hardware description language</li> <li><a href="/wiki/VHSIC_hardware_description_language" class="mw-redirect" title="VHSIC hardware description language">VHDL</a></li> <li><a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a></li> <li><a href="/wiki/Very-large-scale_integration" title="Very-large-scale integration">Very-large-scale integration</a></li> <li><a href="/wiki/Modelica" title="Modelica">Modelica</a>, a language for modeling physical systems</li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline 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array">FPGA</a> <ul><li><a href="/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a class="mw-selflink selflink">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" 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