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Unsourced material may be challenged and removed.<br /><small><span class="plainlinks"><i>Find sources:</i> <a rel="nofollow" class="external text" href="https://www.google.com/search?as_eq=wikipedia&q=%22High-level+synthesis%22">"High-level synthesis"</a> – <a rel="nofollow" class="external text" href="https://www.google.com/search?tbm=nws&q=%22High-level+synthesis%22+-wikipedia&tbs=ar:1">news</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?&q=%22High-level+synthesis%22&tbs=bkt:s&tbm=bks">newspapers</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?tbs=bks:1&q=%22High-level+synthesis%22+-wikipedia">books</a> <b>·</b> <a rel="nofollow" class="external text" href="https://scholar.google.com/scholar?q=%22High-level+synthesis%22">scholar</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.jstor.org/action/doBasicSearch?Query=%22High-level+synthesis%22&acc=on&wc=on">JSTOR</a></span></small></span> <span class="date-container"><i>(<span class="date">October 2016</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444"><table class="box-Unbalanced plainlinks metadata ambox ambox-content ambox-unbalanced" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span class="skin-invert" typeof="mw:File"><span><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Unbalanced_scales.svg/45px-Unbalanced_scales.svg.png" decoding="async" width="45" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Unbalanced_scales.svg/68px-Unbalanced_scales.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fe/Unbalanced_scales.svg/90px-Unbalanced_scales.svg.png 2x" data-file-width="400" data-file-height="354" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>may be <a href="/wiki/Wikipedia:Neutral_point_of_view#Undue_weight" title="Wikipedia:Neutral point of view">unbalanced</a> toward certain viewpoints</b>.<span class="hide-when-compact"> Please <a class="external text" href="https://en.wikipedia.org/w/index.php?title=High-level_synthesis&action=edit">improve the article</a> by adding information on neglected viewpoints, or discuss the issue on the <a href="/wiki/Talk:High-level_synthesis" title="Talk:High-level synthesis">talk page</a>.</span> <span class="date-container"><i>(<span class="date">April 2011</span>)</i></span></div></td></tr></tbody></table> </div> </div><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p><b>High-level synthesis</b> (<b>HLS</b>), sometimes referred to as <b>C synthesis</b>, <b>electronic system-level (ESL) synthesis</b>, <b>algorithmic synthesis</b>, or <b>behavioral synthesis</b>, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior.<sup id="cite_ref-Springer_Book_1-0" class="reference"><a href="#cite_note-Springer_Book-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as <a href="/wiki/Clock_signal" title="Clock signal">clock</a>-level timing. Early HLS explored a variety of input specification languages,<sup id="cite_ref-Martin09_4-0" class="reference"><a href="#cite_note-Martin09-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> although recent research and commercial applications generally accept synthesizable subsets of <a href="/wiki/ANSI_C" title="ANSI C">ANSI C</a>/<a href="/wiki/C%2B%2B" title="C++">C++</a>/<a href="/wiki/SystemC" title="SystemC">SystemC</a>/<a href="/wiki/MATLAB" title="MATLAB">MATLAB</a>. The code is analyzed, architecturally constrained, and scheduled to <a href="/wiki/Transcompile" class="mw-redirect" title="Transcompile">transcompile</a> from a <a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">transaction-level model</a> (TLM) into a <a href="/wiki/Register-transfer_level" title="Register-transfer level">register-transfer level</a> (RTL) design in a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL), which is in turn commonly synthesized to the <a href="/wiki/Logic_gate" title="Logic gate">gate level</a> by the use of a <a href="/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a> tool. </p><p>The goal of HLS is to let hardware designers efficiently build and verify hardware, by giving them better control over optimization of their design architecture, and through the nature of allowing the designer to describe the design at a higher level of abstraction while the tool does the RTL implementation. Verification of the RTL is an important part of the process.<sup id="cite_ref-eetimes_5-0" class="reference"><a href="#cite_note-eetimes-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>Hardware can be designed at varying levels of abstraction. The commonly used levels of abstraction are <a href="/wiki/Digital_electronics" title="Digital electronics">gate level</a>, <a href="/wiki/Register-transfer_level" title="Register-transfer level">register-transfer level</a> (RTL), and <a href="/wiki/Algorithm" title="Algorithm">algorithmic</a> level. </p><p>While <a href="/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a> uses an RTL description of the design, high-level synthesis works at a higher level of abstraction, starting with an algorithmic description in a high-level language such as SystemC and ANSI C/C++. The designer typically develops the module functionality and the interconnect protocol. The high-level synthesis tools handle the micro-architecture and transform untimed or partially timed functional code into fully timed RTL implementations, automatically creating cycle-by-cycle detail for hardware implementation.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> The (RTL) implementations are then used directly in a conventional logic synthesis flow to create a gate-level implementation. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Early academic work extracted scheduling, allocation, and binding as the basic steps for high-level-synthesis. Scheduling partitions the algorithm in control steps that are used to define the states in the <a href="/wiki/Finite-state_machine" title="Finite-state machine">finite-state machine</a>. Each control step contains one small section of the algorithm that can be performed in a single clock cycle in the hardware. Allocation and binding maps the instructions and variables to the hardware components, multiplexers, registers and wires of the data path. </p><p>First generation behavioral synthesis was introduced by <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a> in 1994 as Behavioral Compiler<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> and used <a href="/wiki/Verilog" title="Verilog">Verilog</a> or <a href="/wiki/VHDL" title="VHDL">VHDL</a> as input languages. The abstraction level used was partially timed (clocked) processes. Tools based on behavioral Verilog or VHDL were not widely adopted in part because neither languages nor the partially timed abstraction were well suited to modeling behavior at a high level. 10 years later, in early 2004, Synopsys <a href="/wiki/End-of-life_(product)" class="mw-redirect" title="End-of-life (product)">end-of-lifed</a> Behavioral Compiler.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>In 1998, <a href="/wiki/Forte_Design_Systems" title="Forte Design Systems">Forte Design Systems</a> introduced its Cynthesizer tool which used SystemC as an entry language instead of Verilog or VHDL. Cynthesizer was adopted by many Japanese companies in 2000 as Japan had a very mature SystemC user community. The first high-level synthesis tapeout was achieved in 2001 by <a href="/wiki/Sony" title="Sony">Sony</a> using Cynthesizer. Adoption in the United States started in earnest in 2008.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2023)">citation needed</span></a></i>]</sup> </p><p>In 2006, an efficient and scalable "SDC modulo scheduling" technique was developed on control and data flow graphs <sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> and was later extended to pipeline scheduling.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> This technique uses the integer linear programming formulation. But it shows that the underlying constraint matrix is <a href="/wiki/Unimodular_matrix#Total_unimodularity" title="Unimodular matrix">totally unimodular</a> (after approximating the resource constraints). Thus, the problem can be solved in polynomial time optimally using a linear programming solver in polynomial time. This work was inducted to the FPGA and Reconfigurable Computing Hall of Fame 2022.<sup id="cite_ref-:0_11-0" class="reference"><a href="#cite_note-:0-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>The SDC scheduling algorithm was implemented in the xPilot HLS system<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> developed at UCLA,<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> and later licensed to the AutoESL Design Technologies, a spin-off from UCLA. AutoESL was acquired by Xilinx (now part of AMD) in 2011,<sup id="cite_ref-:0_11-1" class="reference"><a href="#cite_note-:0-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> and the HLS tool developed by AutoESL became the base of Xilinx HLS solutions, Vivado HLS and Vitis HLS, widely used for FPGA designs. </p> <div class="mw-heading mw-heading2"><h2 id="Source_input">Source input</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=2" title="Edit section: Source input"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The most common source inputs for high-level synthesis are based on standard languages such as <a href="/wiki/ANSI_C" title="ANSI C">ANSI C</a>/<a href="/wiki/C%2B%2B" title="C++">C++</a>, <a href="/wiki/SystemC" title="SystemC">SystemC</a> and <a href="/wiki/MATLAB" title="MATLAB">MATLAB</a>. </p><p>High-level synthesis typically also includes a bit-accurate executable specification as input, since to derive an efficient hardware implementation, additional information is needed on what is an acceptable Mean-Square Error or Bit-Error Rate etc. For example, if the designer starts with an FIR filter written using the "double" floating type, before he can derive an efficient hardware implementation, they need to perform numerical refinement to arrive at a fixed-point implementation. The refinement requires additional information on the level of quantization noise that can be tolerated, the valid input ranges etc. This bit-accurate specification makes the high level synthesis source specification functionally complete.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> Normally the tools infer from the high level code a Finite State Machine and a Datapath that implement arithmetic operations. </p> <div class="mw-heading mw-heading2"><h2 id="Process_stages">Process stages</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=3" title="Edit section: Process stages"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The high-level synthesis process consists of a number of activities. Various high-level synthesis tools perform these activities in different orders using different algorithms. Some high-level synthesis tools combine some of these activities or perform them iteratively to converge on the desired solution.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Lexical processing</li> <li>Algorithm optimization</li> <li>Control/Dataflow analysis</li> <li>Library processing</li> <li>Resource allocation</li> <li>Scheduling</li> <li>Functional unit binding</li> <li>Register binding</li> <li>Output processing</li> <li>Input Rebundling</li></ul> <div class="mw-heading mw-heading2"><h2 id="Functionality">Functionality</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=4" title="Edit section: Functionality"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In general, an algorithm can be performed over many clock cycles with few hardware resources, or over fewer clock cycles using a larger number of ALUs, registers and memories. Correspondingly, from one algorithmic description, a variety of hardware microarchitectures can be generated by an HLS compiler according to the directives given to the tool. This is the same trade off of execution speed for hardware complexity as seen when a given program is run on conventional processors of differing performance, yet all running at roughly the same clock frequency. </p> <div class="mw-heading mw-heading3"><h3 id="Architectural_constraints">Architectural constraints</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=5" title="Edit section: Architectural constraints"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Synthesis constraints for the architecture can automatically be applied based on the design analysis.<sup id="cite_ref-eetimes_5-1" class="reference"><a href="#cite_note-eetimes-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> These constraints can be broken into </p> <ul><li>Hierarchy</li> <li>Interface</li> <li>Memory</li> <li>Loop</li> <li>Low-level timing constraints</li> <li>Iteration</li></ul> <div class="mw-heading mw-heading3"><h3 id="Interface_synthesis">Interface synthesis</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=6" title="Edit section: Interface synthesis"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Interface Synthesis refers to the ability to accept pure C/C++ description as its input, then use automated interface synthesis technology to control the timing and communications protocol on the design interface. This enables interface analysis and exploration of a full range of hardware interface options such as streaming, single- or dual-port RAM plus various handshaking mechanisms. With interface synthesis the designer does not embed interface protocols in the source description. Examples might be: direct connection, one line, 2 line handshake, FIFO.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Vendors">Vendors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=7" title="Edit section: Vendors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Data reported on recent Survey<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p> <table class="wikitable"> <tbody><tr> <th>Status </th> <th><a href="/wiki/Compiler" title="Compiler">Compiler</a> </th> <th>Owner </th> <th><a href="/wiki/Software_license" title="Software license">License</a> </th> <th><a href="/wiki/Input/output" title="Input/output">Input</a> </th> <th><a href="/wiki/Input/output" title="Input/output">Output</a> </th> <th>Year </th> <th>Domain </th> <th>Test<br />bench </th> <th>FP </th> <th>FixP </th></tr> <tr> <th rowspan="28">In use </th> <td><a rel="nofollow" class="external text" href="https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/synthesis/stratus-high-level-synthesis.html">Stratus HLS</a> </td> <td><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence Design Systems</a> </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>–<a href="/wiki/C%2B%2B" title="C++">C++</a> <a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td>RTL </td> <td>2015 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://tima.imag.fr/sls/research-projects/augh/">AUGH</a> </td> <td>TIMA Lab. </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2012 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.yxi.com">eXCite</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20190917062628/http://www.yxi.com/">Archived</a> 2019-09-17 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </td> <td>Y Explorations </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2001 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://panda.dei.polimi.it/?page_id=81">Bambu</a> </td> <td>PoliMi </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2012 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a href="/wiki/Bluespec" title="Bluespec">Bluespec</a> </td> <td>BlueSpec, Inc. </td> <td><a href="/wiki/BSD_licenses" title="BSD licenses">BSD</a>-3 </td> <td><a href="/wiki/Bluespec" title="Bluespec">Bluespec</a> <a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a><br />(<a href="/wiki/Haskell" title="Haskell">Haskell</a>) </td> <td><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> </td> <td>2007 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://cacheq.com/">QCC</a> </td> <td><a rel="nofollow" class="external text" href="https://cacheq.com/">CacheQ Systems, Inc.</a> </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a>, <a href="/wiki/Fortran" title="Fortran">Fortran</a> </td> <td>Host executable + <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> bit file (SystemVerilog is intermediate) </td> <td>2018 </td> <td>All - multi-core and heterogeneous compute </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes (C++) </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>CHC </td> <td>Altium </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2008 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>CoDeveloper </td> <td>Impulse Accelerated </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>Impulse-C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2003 </td> <td>Image<br />streaming </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.mathworks.com/products/hdl-coder.html">HDL Coder</a> </td> <td><a href="/wiki/MathWorks" title="MathWorks">MathWorks</a> </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/MATLAB" title="MATLAB">MATLAB</a>, <a href="/wiki/Simulink" title="Simulink">Simulink</a>, <a href="/wiki/Stateflow" title="Stateflow">Stateflow</a>, Simscape </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>, Verilog </td> <td>2003 </td> <td>Control systems, signal processing, wireless, radar, communications, image and computer vision </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.cyberworkbench.com">CyberWorkBench</a> </td> <td>NEC </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C, BDL, <a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2004 </td> <td>All </td> <td>Cycle,<br />formal </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://eda.sw.siemens.com/en-US/ic/catapult-high-level-synthesis">Catapult</a> </td> <td>Siemens EDA </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>–<a href="/wiki/C%2B%2B" title="C++">C++</a> <a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2004 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>DWARV </td> <td>TU. Delft </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2012 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.gaut.fr">GAUT</a> </td> <td><a href="/wiki/University_of_Western_Brittany" title="University of Western Brittany">University of Western Brittany</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2010 </td> <td>DSP </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://hastlayer.com/">Hastlayer</a> </td> <td>Lombiq Technologies </td> <td><a href="/wiki/BSD_licenses" title="BSD licenses">BSD</a>-3 </td> <td><a href="/wiki/C_Sharp_(programming_language)" title="C Sharp (programming language)">C#</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a>, <a href="/wiki/F_Sharp_(programming_language)" title="F Sharp (programming language)">F#</a>, ...<br />(<a href="/wiki/.NET" title=".NET">.NET</a>) </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2015 </td> <td><a href="/wiki/.NET" title=".NET">.NET</a> </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.fpga-cores.com/instant-soc/">Instant SoC</a> </td> <td>FPGA Cores </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2019 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html">Intel High Level Synthesis Compiler</a> </td> <td>Intel FPGA (Formerly Altera) </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2017 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://www.legupcomputing.com">LegUp HLS</a> </td> <td>LegUp Computing </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2015 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://legup.eecg.utoronto.ca">LegUp</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200724081231/http://legup.eecg.utoronto.ca/">Archived</a> 2020-07-24 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </td> <td><a href="/wiki/University_of_Toronto" title="University of Toronto">University of Toronto</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2010 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>MaxCompiler </td> <td>Maxeler </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>MaxJ </td> <td>RTL </td> <td>2010 </td> <td><a href="/wiki/Data-flow_analysis" title="Data-flow analysis">Data-flow analysis</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://roccc.cs.ucr.edu/">ROCCC</a> </td> <td>Jacquard Comp. </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2010 </td> <td>Streaming </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>Symphony C </td> <td>Synopsys </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>, <a href="/wiki/C%2B%2B" title="C++">C++</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a>,<br /><a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td>2010 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.xilinx.com/products/design-tools/vivado/">VivadoHLS</a><br />(formerly AutoPilot<br />from AutoESL<sup id="cite_ref-autoeslxilinx_18-0" class="reference"><a href="#cite_note-autoeslxilinx-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup>) </td> <td>Xilinx </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/C_(programming_language)" title="C (programming language)">C</a>–<a href="/wiki/C%2B%2B" title="C++">C++</a> <a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a>,<br /><a href="/wiki/SystemC" title="SystemC">SystemC</a> </td> <td>2013 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.cl.cam.ac.uk/research/srg/han/hprls/orangepath/kiwic.html">Kiwi</a> </td> <td><a href="/wiki/University_of_Cambridge" title="University of Cambridge">University of Cambridge</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C# </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2008 </td> <td><a href="/wiki/.NET" title=".NET">.NET</a> </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>CHiMPS </td> <td><a href="/wiki/University_of_Washington" title="University of Washington">University of Washington</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2008 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>gcc2verilog </td> <td><a href="/wiki/Korea_University" title="Korea University">Korea University</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2011 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td><a rel="nofollow" class="external text" href="http://www.nkavvadias.com/hercules/">HercuLeS</a> </td> <td>Ajax Compilers </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C/NAC </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2012 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a rel="nofollow" class="external text" href="https://github.com/etherzhhb/Shang">Shang</a> </td> <td><a href="/wiki/University_of_Illinois_Urbana-Champaign" title="University of Illinois Urbana-Champaign">University of Illinois Urbana-Champaign</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2013 </td> <td>All </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td>? </td> <td>? </td></tr> <tr> <td>Trident </td> <td>Los Alamos NL </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2007 </td> <td>Scientific </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <th rowspan="11">Aban-<br />doned </th> <td>AccelDSP </td> <td>Xilinx </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td><a href="/wiki/MATLAB" title="MATLAB">MATLAB</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2006 </td> <td>DSP </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>C2H </td> <td>Altera </td> <td><a href="/wiki/Commercial_software" title="Commercial software">Commercial</a> </td> <td>C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2006 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>CtoVerilog </td> <td><a href="/wiki/University_of_Haifa" title="University of Haifa">University of Haifa</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>2008 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>DEFACTO </td> <td>University South Cailf. </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td>RTL </td> <td>1999 </td> <td>DSE </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>Garp </td> <td><a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C subset </td> <td>bitstream </td> <td>2000 </td> <td>Loop </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>MATCH </td> <td><a href="/wiki/Northwest_University_(United_States)" title="Northwest University (United States)">Northwest University</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td><a href="/wiki/MATLAB" title="MATLAB">MATLAB</a> </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2000 </td> <td>Image </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>Napa-C </td> <td>Sarnoff Corp. </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C subset </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a>–<a href="/wiki/Verilog" title="Verilog">Verilog</a> </td> <td>1998 </td> <td>Loop </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>PipeRench </td> <td><a href="/wiki/Carnegie_Mellon_University" title="Carnegie Mellon University">Carnegie Mellon University</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>DIL </td> <td>bistream </td> <td>2000 </td> <td>Stream </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>SA-C </td> <td><a href="/wiki/University_of_Colorado" title="University of Colorado">University of Colorado</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>SA-C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2003 </td> <td>Image </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>SeaCucumber </td> <td><a href="/wiki/Brigham_Young_University" title="Brigham Young University">Brigham Young University</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td><a href="/wiki/Java_(programming_language)" title="Java (programming language)">Java</a> </td> <td>EDIF </td> <td>2002 </td> <td>All </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>SPARK </td> <td><a href="/wiki/University_of_California,_Irvine" title="University of California, Irvine">University of California, Irvine</a> </td> <td><a href="/wiki/Academic_Free_License" title="Academic Free License">Academic</a> </td> <td>C </td> <td><a href="/wiki/VHDL" title="VHDL">VHDL</a> </td> <td>2003 </td> <td>Control </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr></tbody></table> <ul><li><a rel="nofollow" class="external text" href="https://dynamatic.epfl.ch/">Dynamatic</a> from <a href="/wiki/%C3%89cole_Polytechnique_F%C3%A9d%C3%A9rale_de_Lausanne" title="École Polytechnique Fédérale de Lausanne">EPFL</a>/<a href="/wiki/ETH_Zurich" title="ETH Zurich">ETH Zurich</a></li> <li><a href="/wiki/MATLAB" title="MATLAB">MATLAB</a> HDL Coder <a rel="nofollow" class="external autonumber" href="https://www.mathworks.com/products/hdl-coder.html">[1]</a> from <a href="/wiki/Mathworks" class="mw-redirect" title="Mathworks">Mathworks</a><sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></li> <li>HLS-QSP from CircuitSutra Technologies<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></li> <li>C-to-Silicon from <a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence Design Systems</a></li> <li>Concurrent Acceleration from Concurrent EDA</li> <li>Symphony C Compiler from <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li>QuickPlay from PLDA<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></li> <li>PowerOpt from ChipVision<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup></li> <li>Cynthesizer from <a href="/wiki/Forte_Design_Systems" title="Forte Design Systems">Forte Design Systems</a> (now Stratus HLS from <a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence Design Systems</a>)</li> <li><a href="/wiki/Catapult_C" title="Catapult C">Catapult C</a> from Calypto Design Systems, part of <a href="/wiki/Mentor_Graphics" title="Mentor Graphics">Mentor Graphics</a> as of 2015, September 16. In November 2016 Siemens announced plans to acquire Mentor Graphics, Mentor Graphics became styled as "Mentor, a Siemens Business". In January 2021, the legal merger of Mentor Graphics with Siemens was completed - merging into the Siemens Industry Software Inc legal entity. Mentor Graphics' name was changed to Siemens EDA, a division of <a href="/wiki/Siemens_Digital_Industries_Software" title="Siemens Digital Industries Software">Siemens Digital Industries Software</a>.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></li> <li>PipelineC <a rel="nofollow" class="external autonumber" href="https://github.com/JulianKemmerer/PipelineC">[2]</a></li> <li>CyberWorkBench from <a href="/wiki/NEC" title="NEC">NEC</a><sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup></li> <li>Mega Hardware <sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup></li> <li>C2R from CebaTech<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></li> <li>CoDeveloper from Impulse Accelerated Technologies</li> <li>HercuLeS by Nikolaos Kavvadias<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup></li> <li>Program In/Code Out (PICO) from Synfora, acquired by Synopsys in June 2010<sup id="cite_ref-synfora_28-0" class="reference"><a href="#cite_note-synfora-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></li> <li>xPilot from University of California, Los Angeles<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></li> <li>Vsyn from vsyn.ru<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>ngDesign from SynFlow<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=8" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a> (EDA)</li> <li><a href="/wiki/Electronic_system-level" class="mw-redirect" title="Electronic system-level">Electronic system-level</a> (ESL)</li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/High-level_verification" title="High-level verification">High-level verification</a> (HLV)</li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=9" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-Springer_Book-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-Springer_Book_1-0">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFCoussyMorawiec2008" class="citation book cs1">Coussy, Philippe; Morawiec, Adam, eds. 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Retrieved <span class="nowrap">2016-10-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Synopsys+buys+Synfora+assets&rft.pub=EE+Times&rft_id=http%3A%2F%2Fwww.eetimes.com%2Felectronics-news%2F4200083%2FSynopsys-buys-Synfora-assets&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></span> </li> <li id="cite_note-29"><span class="mw-cite-backlink"><b><a href="#cite_ref-29">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://cadlab.cs.ucla.edu/soc/">"The xPilot System"</a>. <i>Cadlab.cs.ucla.edu</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2016-10-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Cadlab.cs.ucla.edu&rft.atitle=The+xPilot+System&rft_id=http%3A%2F%2Fcadlab.cs.ucla.edu%2Fsoc%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></span> </li> <li id="cite_note-30"><span class="mw-cite-backlink"><b><a href="#cite_ref-30">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20160630171129/http://www.vsyn.ru/">"vSyn.ru"</a>. <i>vSyn.ru</i>. 2016-06-16. Archived from <a rel="nofollow" class="external text" href="http://www.vsyn.ru">the original</a> on 2016-06-30<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-10-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=vSyn.ru&rft.atitle=vSyn.ru&rft.date=2016-06-16&rft_id=http%3A%2F%2Fwww.vsyn.ru&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.synflow.com/">"Hardware design for all"</a>. Synflow<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-10-03</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Hardware+design+for+all&rft.pub=Synflow&rft_id=https%3A%2F%2Fwww.synflow.com%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=High-level_synthesis&action=edit&section=10" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees Vissers, Zhiru Zhang.  FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Transactions on Reconfigurable Technology and Systems, Volume 15, Issue 4, Article No. 5, pp 1–42, December 2022, <a rel="nofollow" class="external free" href="https://doi.org/10.1145/3530775">https://doi.org/10.1145/3530775</a>.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFMichael_Fingeroff2010" class="citation book cs1">Michael Fingeroff (2010). <i>High-Level Synthesis Blue Book</i>. Xlibris<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Verifiability#Self-published_sources" title="Wikipedia:Verifiability"><span title="The material near this tag may rely on a self-published source. (January 2018)">self-published source</span></a></i>]</sup> Corporation. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4500-9724-6" title="Special:BookSources/978-1-4500-9724-6"><bdi>978-1-4500-9724-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=High-Level+Synthesis+Blue+Book&rft.pub=XlibrisCategory%3AAll+articles+with+self-published+sourcesCategory%3AArticles+with+self-published+sources+from+January+2018%3Csup+class%3D%22noprint+Inline-Template+%22+style%3D%22white-space%3Anowrap%3B%22%3E%26%2391%3B%3Ci%3E%3Cspan+title%3D%22The+material+near+this+tag+may+rely+on+a+self-published+source.%26%2332%3B%28January+2018%29%22%3Eself-published+source%3C%2Fspan%3E%3C%2Fi%3E%26%2393%3B%3C%2Fsup%3E+Corporation&rft.date=2010&rft.isbn=978-1-4500-9724-6&rft.au=Michael+Fingeroff&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCoussyGajskiMeredithTakach2009" class="citation journal cs1">Coussy, P.; Gajski, D. D.; Meredith, M.; Takach, A. (2009). "An Introduction to High-Level Synthesis". <i>IEEE Design & Test of Computers</i>. <b>26</b> (4): 8–17. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMDT.2009.69">10.1109/MDT.2009.69</a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:52870966">52870966</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Design+%26+Test+of+Computers&rft.atitle=An+Introduction+to+High-Level+Synthesis&rft.volume=26&rft.issue=4&rft.pages=8-17&rft.date=2009&rft_id=info%3Adoi%2F10.1109%2FMDT.2009.69&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A52870966%23id-name%3DS2CID&rft.aulast=Coussy&rft.aufirst=P.&rft.au=Gajski%2C+D.+D.&rft.au=Meredith%2C+M.&rft.au=Takach%2C+A.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFEwout_S._J._MartensGeorges_Gielen2008" class="citation book cs1">Ewout S. J. Martens; Georges Gielen (2008). <i>High-level modeling and synthesis of analog integrated systems</i>. Springer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4020-6801-0" title="Special:BookSources/978-1-4020-6801-0"><bdi>978-1-4020-6801-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=High-level+modeling+and+synthesis+of+analog+integrated+systems&rft.pub=Springer&rft.date=2008&rft.isbn=978-1-4020-6801-0&rft.au=Ewout+S.+J.+Martens&rft.au=Georges+Gielen&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSaraju_MohantyN._RanganathanE._KougianosP._Patra2008" class="citation book cs1"><a href="/wiki/Saraju_Mohanty" title="Saraju Mohanty">Saraju Mohanty</a>; N. Ranganathan; E. Kougianos & P. Patra (2008). <i>Low-Power High-Level Synthesis for Nanoscale CMOS Circuits</i>. Springer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0387764733" title="Special:BookSources/978-0387764733"><bdi>978-0387764733</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Low-Power+High-Level+Synthesis+for+Nanoscale+CMOS+Circuits&rft.pub=Springer&rft.date=2008&rft.isbn=978-0387764733&rft.au=Saraju+Mohanty&rft.au=N.+Ranganathan&rft.au=E.+Kougianos&rft.au=P.+Patra&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlice_C._ParkerYosef_Tirat-GefenSuhrid_A._Wadekar2007" class="citation book cs1"><a href="/wiki/Alice_C._Parker" title="Alice C. Parker">Alice C. Parker</a>; Yosef Tirat-Gefen; Suhrid A. Wadekar (2007). "System-Level Design". In Wai-Kai Chen (ed.). <i>The VLSI handbook</i> (2nd ed.). CRC Press. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-8493-4199-1" title="Special:BookSources/978-0-8493-4199-1"><bdi>978-0-8493-4199-1</bdi></a>. chapter 76.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=System-Level+Design&rft.btitle=The+VLSI+handbook&rft.edition=2nd&rft.pub=CRC+Press&rft.date=2007&rft.isbn=978-0-8493-4199-1&rft.au=Alice+C.+Parker&rft.au=Yosef+Tirat-Gefen&rft.au=Suhrid+A.+Wadekar&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFShahrzad_MirkhaniZainalabedin_Navabi2007" class="citation book cs1">Shahrzad Mirkhani; Zainalabedin Navabi (2007). "System Level Design Languages". In Wai-Kai Chen (ed.). <i>The VLSI handbook</i> (2nd ed.). CRC Press. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-8493-4199-1" title="Special:BookSources/978-0-8493-4199-1"><bdi>978-0-8493-4199-1</bdi></a>. chapter 86.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=System+Level+Design+Languages&rft.btitle=The+VLSI+handbook&rft.edition=2nd&rft.pub=CRC+Press&rft.date=2007&rft.isbn=978-0-8493-4199-1&rft.au=Shahrzad+Mirkhani&rft.au=Zainalabedin+Navabi&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span> covers the use of C/C++, SystemC, TML and even UML</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLiming_Xiu2007" class="citation book cs1">Liming Xiu (2007). <i>VLSI circuit design methodology demystified: a conceptual taxonomy</i>. Wiley-IEEE. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-470-12742-1" title="Special:BookSources/978-0-470-12742-1"><bdi>978-0-470-12742-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=VLSI+circuit+design+methodology+demystified%3A+a+conceptual+taxonomy&rft.pub=Wiley-IEEE&rft.date=2007&rft.isbn=978-0-470-12742-1&rft.au=Liming+Xiu&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJohn_P._Elliott1999" class="citation book cs1">John P. Elliott (1999). <i>Understanding behavioral synthesis: a practical guide to high-level design</i>. Springer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-7923-8542-4" title="Special:BookSources/978-0-7923-8542-4"><bdi>978-0-7923-8542-4</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Understanding+behavioral+synthesis%3A+a+practical+guide+to+high-level+design&rft.pub=Springer&rft.date=1999&rft.isbn=978-0-7923-8542-4&rft.au=John+P.+Elliott&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNaneSimaPilatoChoi2016" class="citation journal cs1">Nane, Razvan; Sima, Vlad-Mihai; Pilato, Christian; Choi, Jongsok; Fort, Blair; Canis, Andrew; Chen, Yu Ting; Hsiao, Hsuan; Brown, Stephen; Ferrandi, Fabrizio; Anderson, Jason; Bertels, Koen (2016). "A Survey and Evaluation of FPGA High-Level Synthesis Tools". <i>IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems</i>. <b>35</b> (10): 1591–1604. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FTCAD.2015.2513673">10.1109/TCAD.2015.2513673</a>. <a href="/wiki/Hdl_(identifier)" class="mw-redirect" title="Hdl (identifier)">hdl</a>:<span class="id-lock-free" title="Freely accessible"><a rel="nofollow" class="external text" href="https://hdl.handle.net/11311%2F998432">11311/998432</a></span>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:8749577">8749577</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=IEEE+Transactions+on+Computer-Aided+Design+of+Integrated+Circuits+and+Systems&rft.atitle=A+Survey+and+Evaluation+of+FPGA+High-Level+Synthesis+Tools&rft.volume=35&rft.issue=10&rft.pages=1591-1604&rft.date=2016&rft_id=info%3Ahdl%2F11311%2F998432&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A8749577%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1109%2FTCAD.2015.2513673&rft.aulast=Nane&rft.aufirst=Razvan&rft.au=Sima%2C+Vlad-Mihai&rft.au=Pilato%2C+Christian&rft.au=Choi%2C+Jongsok&rft.au=Fort%2C+Blair&rft.au=Canis%2C+Andrew&rft.au=Chen%2C+Yu+Ting&rft.au=Hsiao%2C+Hsuan&rft.au=Brown%2C+Stephen&rft.au=Ferrandi%2C+Fabrizio&rft.au=Anderson%2C+Jason&rft.au=Bertels%2C+Koen&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGuptaBrewer2008" class="citation book cs1">Gupta, Rajesh; Brewer, Forrest (2008). "High-Level Synthesis: A Retrospective". <i>"High-level Synthesis: A Retrospective"</i>. Springer. pp. 13–28. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2F978-1-4020-8588-8_2">10.1007/978-1-4020-8588-8_2</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-4020-8587-1" title="Special:BookSources/978-1-4020-8587-1"><bdi>978-1-4020-8587-1</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=bookitem&rft.atitle=High-Level+Synthesis%3A+A+Retrospective&rft.btitle=%22High-level+Synthesis%3A+A+Retrospective%22&rft.pages=13-28&rft.pub=Springer&rft.date=2008&rft_id=info%3Adoi%2F10.1007%2F978-1-4020-8588-8_2&rft.isbn=978-1-4020-8587-1&rft.aulast=Gupta&rft.aufirst=Rajesh&rft.au=Brewer%2C+Forrest&rfr_id=info%3Asid%2Fen.wikipedia.org%3AHigh-level+synthesis" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 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title="Digital signal processor">Digital signal processing</a></li> <li><a href="/wiki/Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generation</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">Artificial intelligence</a></li> <li><a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">Cryptography</a> <ul><li><a href="/wiki/TLS_acceleration" title="TLS acceleration">TLS</a></li></ul></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Machine vision</a></li> <li><a href="/wiki/Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a> <ul><li><a href="/wiki/Scrypt" title="Scrypt">scrypt</a></li></ul></li> <li><a href="/wiki/Network_processor" title="Network processor">Networking</a></li> <li><a href="/wiki/Data_processing_unit" title="Data processing unit">Data</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">High-level synthesis</a> <ul><li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li></ul></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> <ul><li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered</a></li> <li><a href="/wiki/Multicore" class="mw-redirect" title="Multicore">Multicore</a></li> <li><a href="/wiki/Manycore" class="mw-redirect" title="Manycore">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory computing</a></li> <li><a href="/wiki/Systolic_array" title="Systolic array">Systolic array</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Programmable_logic" class="mw-redirect" title="Programmable logic">Programmable logic</a></li> <li><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor</a> <ul><li><a href="/wiki/Processor_design" title="Processor design">design</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li></ul></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Virtualization" title="Virtualization">Virtualization</a> <ul><li><a href="/wiki/Hardware_emulation" title="Hardware emulation">Hardware emulation</a></li></ul></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Embedded_system" title="Embedded system">Embedded systems</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Digital_electronics" title="Template:Digital electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Digital_electronics" title="Template talk:Digital electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Digital_electronics" title="Special:EditPage/Template:Digital electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Digital_electronics" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a class="mw-selflink selflink">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=0" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" 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