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id="toc-Lynx:_"Llano"_(2011)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Virgo:_"Trinity"_(2012)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Virgo:_"Trinity"_(2012)"> <div class="vector-toc-text"> 3.1.2 Virgo: "Trinity" (2012) </div> </a> <ul id="toc-Virgo:_"Trinity"_(2012)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Richland"_(2013)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Richland"_(2013)"> <div class="vector-toc-text"> 3.1.3 "Richland" (2013) </div> </a> <ul id="toc-"Richland"_(2013)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kabini"_(2013,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kabini"_(2013,_SoC)"> <div class="vector-toc-text"> 3.1.4 "Kabini" (2013, SoC) </div> </a> <ul id="toc-"Kabini"_(2013,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kaveri"_(2014)_&_"Godavari"_(2015)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kaveri"_(2014)_&_"Godavari"_(2015)"> <div class="vector-toc-text"> 3.1.5 "Kaveri" (2014) & "Godavari" (2015) </div> </a> <ul id="toc-"Kaveri"_(2014)_&_"Godavari"_(2015)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Carrizo"_(2016)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Carrizo"_(2016)"> <div class="vector-toc-text"> 3.1.6 "Carrizo" (2016) </div> </a> <ul id="toc-"Carrizo"_(2016)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Bristol_Ridge"_(2016)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Bristol_Ridge"_(2016)"> <div class="vector-toc-text"> 3.1.7 "Bristol Ridge" (2016) </div> </a> <ul id="toc-"Bristol_Ridge"_(2016)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Raven_Ridge"_(2018)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Raven_Ridge"_(2018)"> <div class="vector-toc-text"> 3.1.8 "Raven Ridge" (2018) </div> </a> <ul id="toc-"Raven_Ridge"_(2018)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Picasso"_(2019)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Picasso"_(2019)"> <div class="vector-toc-text"> 3.1.9 "Picasso" (2019) </div> </a> <ul id="toc-"Picasso"_(2019)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Renoir"_(2020)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Renoir"_(2020)"> <div class="vector-toc-text"> 3.1.10 "Renoir" (2020) </div> </a> <ul id="toc-"Renoir"_(2020)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Cezanne"_(2021)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Cezanne"_(2021)"> <div class="vector-toc-text"> 3.1.11 "Cezanne" (2021) </div> </a> <ul id="toc-"Cezanne"_(2021)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Non_APU_or_Radeon_Graphics_branded" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Non_APU_or_Radeon_Graphics_branded"> <div class="vector-toc-text"> 3.2 Non APU or Radeon Graphics branded </div> </a> <ul id="toc-Non_APU_or_Radeon_Graphics_branded-sublist" class="vector-toc-list"> <li id="toc-"Raphael"_(2022)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Raphael"_(2022)"> <div class="vector-toc-text"> 3.2.1 "Raphael" (2022) </div> </a> <ul id="toc-"Raphael"_(2022)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Phoenix"_(2024)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Phoenix"_(2024)"> <div class="vector-toc-text"> 3.2.2 "Phoenix" (2024) </div> </a> <ul id="toc-"Phoenix"_(2024)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Server_APUs" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Server_APUs"> <div class="vector-toc-text"> 4 Server APUs </div> </a> <button aria-controls="toc-Server_APUs-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Server APUs subsection </button> <ul id="toc-Server_APUs-sublist" class="vector-toc-list"> <li id="toc-Opteron_X2100-series_"Kyoto"_(2013)_&_"Steppe_Eagle"_(2016)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Opteron_X2100-series_"Kyoto"_(2013)_&_"Steppe_Eagle"_(2016)"> <div class="vector-toc-text"> 4.1 Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016) </div> </a> <ul id="toc-Opteron_X2100-series_"Kyoto"_(2013)_&_"Steppe_Eagle"_(2016)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Opteron_X3000-series_"Toronto"_(2017)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Opteron_X3000-series_"Toronto"_(2017)"> <div class="vector-toc-text"> 4.2 Opteron X3000-series "Toronto" (2017) </div> </a> <ul id="toc-Opteron_X3000-series_"Toronto"_(2017)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Mobile_processors_with_3D_graphics" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Mobile_processors_with_3D_graphics"> <div class="vector-toc-text"> 5 Mobile processors with 3D graphics </div> </a> <button aria-controls="toc-Mobile_processors_with_3D_graphics-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Mobile processors with 3D graphics subsection </button> <ul id="toc-Mobile_processors_with_3D_graphics-sublist" class="vector-toc-list"> <li id="toc-APU_or_Radeon_Graphics_branded_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#APU_or_Radeon_Graphics_branded_2"> <div class="vector-toc-text"> 5.1 APU or Radeon Graphics branded </div> </a> <ul id="toc-APU_or_Radeon_Graphics_branded_2-sublist" class="vector-toc-list"> <li id="toc-Sabine:_"Llano"_(2011)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Sabine:_"Llano"_(2011)"> <div class="vector-toc-text"> 5.1.1 Sabine: "Llano" (2011) </div> </a> <ul id="toc-Sabine:_"Llano"_(2011)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Comal:_"Trinity"_(2012)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comal:_"Trinity"_(2012)"> <div class="vector-toc-text"> 5.1.2 Comal: "Trinity" (2012) </div> </a> <ul id="toc-Comal:_"Trinity"_(2012)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Richland"_(2013)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Richland"_(2013)_2"> <div class="vector-toc-text"> 5.1.3 "Richland" (2013) </div> </a> <ul id="toc-"Richland"_(2013)_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kaveri"_(2014)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kaveri"_(2014)"> <div class="vector-toc-text"> 5.1.4 "Kaveri" (2014) </div> </a> <ul id="toc-"Kaveri"_(2014)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Carrizo"_(2015)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Carrizo"_(2015)"> <div class="vector-toc-text"> 5.1.5 "Carrizo" (2015) </div> </a> <ul id="toc-"Carrizo"_(2015)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Bristol_Ridge"_(2016)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Bristol_Ridge"_(2016)_2"> <div class="vector-toc-text"> 5.1.6 "Bristol Ridge" (2016) </div> </a> <ul id="toc-"Bristol_Ridge"_(2016)_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Raven_Ridge"_(2017)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Raven_Ridge"_(2017)"> <div class="vector-toc-text"> 5.1.7 "Raven Ridge" (2017) </div> </a> <ul id="toc-"Raven_Ridge"_(2017)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Picasso"_(2019)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Picasso"_(2019)_2"> <div class="vector-toc-text"> 5.1.8 "Picasso" (2019) </div> </a> <ul id="toc-"Picasso"_(2019)_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Renoir"_(2020)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Renoir"_(2020)_2"> <div class="vector-toc-text"> 5.1.9 "Renoir" (2020) </div> </a> <ul id="toc-"Renoir"_(2020)_2-sublist" class="vector-toc-list"> <li id="toc-U" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#U"> <div class="vector-toc-text"> 5.1.9.1 U </div> </a> <ul id="toc-U-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-H" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#H"> <div class="vector-toc-text"> 5.1.9.2 H </div> </a> <ul id="toc-H-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-"Lucienne"_(2021)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Lucienne"_(2021)"> <div class="vector-toc-text"> 5.1.10 "Lucienne" (2021) </div> </a> <ul id="toc-"Lucienne"_(2021)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Cezanne"_(2021)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Cezanne"_(2021)_2"> <div class="vector-toc-text"> 5.1.11 "Cezanne" (2021) </div> </a> <ul id="toc-"Cezanne"_(2021)_2-sublist" class="vector-toc-list"> <li id="toc-U_2" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#U_2"> <div class="vector-toc-text"> 5.1.11.1 U </div> </a> <ul id="toc-U_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-H_2" class="vector-toc-list-item vector-toc-level-4"> <a class="vector-toc-link" href="#H_2"> <div class="vector-toc-text"> 5.1.11.2 H </div> </a> <ul id="toc-H_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-"Barceló"_(2022)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Barceló"_(2022)"> <div class="vector-toc-text"> 5.1.12 "Barceló" (2022) </div> </a> <ul id="toc-"Barceló"_(2022)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Rembrandt"_(2022)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Rembrandt"_(2022)"> <div class="vector-toc-text"> 5.1.13 "Rembrandt" (2022) </div> </a> <ul id="toc-"Rembrandt"_(2022)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Phoenix"_(2023)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Phoenix"_(2023)"> <div class="vector-toc-text"> 5.1.14 "Phoenix" (2023) </div> </a> <ul id="toc-"Phoenix"_(2023)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Dragon_Range"_(2023)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Dragon_Range"_(2023)"> <div class="vector-toc-text"> 5.1.15 "Dragon Range" (2023) </div> </a> <ul id="toc-"Dragon_Range"_(2023)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Ultra-mobile_APUs" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Ultra-mobile_APUs"> <div class="vector-toc-text"> 6 Ultra-mobile APUs </div> </a> <button aria-controls="toc-Ultra-mobile_APUs-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Ultra-mobile APUs subsection </button> <ul id="toc-Ultra-mobile_APUs-sublist" class="vector-toc-list"> <li id="toc-Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)"> <div class="vector-toc-text"> 6.1 Brazos: "Desna", "Ontario", "Zacate" (2011) </div> </a> <ul id="toc-Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Brazos_2.0:_"Ontario",_"Zacate"_(2012)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Brazos_2.0:_"Ontario",_"Zacate"_(2012)"> <div class="vector-toc-text"> 6.2 Brazos 2.0: "Ontario", "Zacate" (2012) </div> </a> <ul id="toc-Brazos_2.0:_"Ontario",_"Zacate"_(2012)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Brazos-T:_"Hondo"_(2012)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Brazos-T:_"Hondo"_(2012)"> <div class="vector-toc-text"> 6.3 Brazos-T: "Hondo" (2012) </div> </a> <ul id="toc-Brazos-T:_"Hondo"_(2012)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kabini",_"Temash"_(2013)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Kabini",_"Temash"_(2013)"> <div class="vector-toc-text"> 6.4 "Kabini", "Temash" (2013) </div> </a> <ul id="toc-"Kabini",_"Temash"_(2013)-sublist" class="vector-toc-list"> <li id="toc-Temash,_Elite_Mobility_APU" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Temash,_Elite_Mobility_APU"> <div class="vector-toc-text"> 6.4.1 Temash, Elite Mobility APU </div> </a> <ul id="toc-Temash,_Elite_Mobility_APU-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Kabini,_Mainstream_APU" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Kabini,_Mainstream_APU"> <div class="vector-toc-text"> 6.4.2 Kabini, Mainstream APU </div> </a> <ul id="toc-Kabini,_Mainstream_APU-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-"Beema",_"Mullins"_(2014)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Beema",_"Mullins"_(2014)"> <div class="vector-toc-text"> 6.5 "Beema", "Mullins" (2014) </div> </a> <ul id="toc-"Beema",_"Mullins"_(2014)-sublist" class="vector-toc-list"> <li id="toc-Mullins,_Tablet/2-in-1_APU" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Mullins,_Tablet/2-in-1_APU"> <div class="vector-toc-text"> 6.5.1 Mullins, Tablet/2-in-1 APU </div> </a> <ul id="toc-Mullins,_Tablet/2-in-1_APU-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Beema,_Notebook_APU" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Beema,_Notebook_APU"> <div class="vector-toc-text"> 6.5.2 Beema, Notebook APU </div> </a> <ul id="toc-Beema,_Notebook_APU-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-"Carrizo-L"_(2015)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Carrizo-L"_(2015)"> <div class="vector-toc-text"> 6.6 "Carrizo-L" (2015) </div> </a> <ul id="toc-"Carrizo-L"_(2015)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Stoney_Ridge"_(2016)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Stoney_Ridge"_(2016)"> <div class="vector-toc-text"> 6.7 "Stoney Ridge" (2016) </div> </a> <ul id="toc-"Stoney_Ridge"_(2016)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Dalí"_(2020)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Dalí"_(2020)"> <div class="vector-toc-text"> 6.8 "Dalí" (2020) </div> </a> <ul id="toc-"Dalí"_(2020)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Pollock"_(2020)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Pollock"_(2020)"> <div class="vector-toc-text"> 6.9 "Pollock" (2020) </div> </a> <ul id="toc-"Pollock"_(2020)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Mendocino"_(2022)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#"Mendocino"_(2022)"> <div class="vector-toc-text"> 6.10 "Mendocino" (2022) </div> </a> <ul id="toc-"Mendocino"_(2022)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Embedded_APUs" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Embedded_APUs"> <div class="vector-toc-text"> 7 Embedded APUs </div> </a> <button aria-controls="toc-Embedded_APUs-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Embedded APUs subsection </button> <ul id="toc-Embedded_APUs-sublist" class="vector-toc-list"> <li id="toc-G-Series" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#G-Series"> <div class="vector-toc-text"> 7.1 G-Series </div> </a> <ul id="toc-G-Series-sublist" class="vector-toc-list"> <li id="toc-Brazos:_"Ontario"_and_"Zacate"_(2011)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Brazos:_"Ontario"_and_"Zacate"_(2011)"> <div class="vector-toc-text"> 7.1.1 Brazos: "Ontario" and "Zacate" (2011) </div> </a> <ul id="toc-Brazos:_"Ontario"_and_"Zacate"_(2011)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Kabini"_(2013,_SoC)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Kabini"_(2013,_SoC)_2"> <div class="vector-toc-text"> 7.1.2 "Kabini" (2013, SoC) </div> </a> <ul id="toc-"Kabini"_(2013,_SoC)_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Steppe_Eagle"_(2014,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Steppe_Eagle"_(2014,_SoC)"> <div class="vector-toc-text"> 7.1.3 "Steppe Eagle" (2014, SoC) </div> </a> <ul id="toc-"Steppe_Eagle"_(2014,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Crowned_Eagle"_(2014,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Crowned_Eagle"_(2014,_SoC)"> <div class="vector-toc-text"> 7.1.4 "Crowned Eagle" (2014, SoC) </div> </a> <ul id="toc-"Crowned_Eagle"_(2014,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-LX-Family_(2016,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#LX-Family_(2016,_SoC)"> <div class="vector-toc-text"> 7.1.5 LX-Family (2016, SoC) </div> </a> <ul id="toc-LX-Family_(2016,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-I-Family:_"Brown_Falcon"_(2016,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#I-Family:_"Brown_Falcon"_(2016,_SoC)"> <div class="vector-toc-text"> 7.1.6 I-Family: "Brown Falcon" (2016, SoC) </div> </a> <ul id="toc-I-Family:_"Brown_Falcon"_(2016,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-J-Family:_"Prairie_Falcon"_(2016,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#J-Family:_"Prairie_Falcon"_(2016,_SoC)"> <div class="vector-toc-text"> 7.1.7 J-Family: "Prairie Falcon" (2016, SoC) </div> </a> <ul id="toc-J-Family:_"Prairie_Falcon"_(2016,_SoC)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-R-Series" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#R-Series"> <div class="vector-toc-text"> 7.2 R-Series </div> </a> <ul id="toc-R-Series-sublist" class="vector-toc-list"> <li id="toc-Comal:_"Trinity"_(2012)_2" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Comal:_"Trinity"_(2012)_2"> <div class="vector-toc-text"> 7.2.1 Comal: "Trinity" (2012) </div> </a> <ul id="toc-Comal:_"Trinity"_(2012)_2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Bald_Eagle"_(2014)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Bald_Eagle"_(2014)"> <div class="vector-toc-text"> 7.2.2 "Bald Eagle" (2014) </div> </a> <ul id="toc-"Bald_Eagle"_(2014)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-"Merlin_Falcon"_(2015,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#"Merlin_Falcon"_(2015,_SoC)"> <div class="vector-toc-text"> 7.2.3 "Merlin Falcon" (2015, SoC) </div> </a> <ul id="toc-"Merlin_Falcon"_(2015,_SoC)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-1000-Series" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#1000-Series"> <div class="vector-toc-text"> 7.3 1000-Series </div> </a> <ul id="toc-1000-Series-sublist" class="vector-toc-list"> <li id="toc-V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)"> <div class="vector-toc-text"> 7.3.1 V1000-Family: "Great Horned Owl" (2018, SoC) </div> </a> <ul id="toc-V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-R1000-Family:_"Banded_Kestrel"_(2019,_SoC)" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#R1000-Family:_"Banded_Kestrel"_(2019,_SoC)"> <div class="vector-toc-text"> 7.3.2 R1000-Family: "Banded Kestrel" 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id="toc-R2000-Family:_"River_Hawk"_(2022,_SoC)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-Custom_APUs" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Custom_APUs"> <div class="vector-toc-text"> 8 Custom APUs </div> </a> <ul id="toc-Custom_APUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 9 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> 10 Notes </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 11 References </div> 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Processing Unit) product series. <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Features_overview">Features overview</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=1" title="Edit section: Features overview">edit</a>]</div> The following table shows features of <a href="/wiki/AMD" title="AMD">AMD</a>'s processors with 3D graphics, including <a href="/wiki/AMD_APU" title="AMD APU">APUs</a>. <div style="clear:both;" class=""></div><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output 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abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist" style="position: relative; bottom: -11px;">[ <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Template:Features_of_AMD_Processors_with_3D_Graphics&veaction=edit">VisualEditor</a> ] <ul class="navbar-brackets"><li class="nv-view"><a href="/wiki/Template:Features_of_AMD_Processors_with_3D_Graphics" title="Template:Features of AMD Processors with 3D Graphics">view</a></li><li class="nv-talk"><a href="/wiki/Template_talk:Features_of_AMD_Processors_with_3D_Graphics" title="Template talk:Features of AMD Processors with 3D Graphics">talk</a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Features_of_AMD_Processors_with_3D_Graphics" title="Special:EditPage/Template:Features of AMD Processors with 3D Graphics">edit</a></li></ul></div> <table class="wikitable" style="font-size: 85%; text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Platform </th> <th colspan="14">High, standard and low power </th> <th colspan="9">Low and ultra-low power </th></tr> <tr> <th rowspan="11" style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Codename</th> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="2">Server </th> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic </th> <th colspan="5"> </th> <th><a class="mw-selflink-fragment" href="#Opteron_X3000-series_"Toronto"_(2017)">Toronto</a> </th> <th colspan="8"> </th> <th colspan="9"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Micro </th> <th colspan="14"> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#Opteron_X2100-series_"Kyoto"_(2013)">Kyoto</a> </th> <th colspan="7"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Desktop </th> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance </th> <th colspan="12"> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Raphael"_(2022)">Raphael</a> </th> <th rowspan="3"><a class="mw-selflink-fragment" href="#"Phoenix"_(2024)">Phoenix</a> </th> <th colspan="9" rowspan="3"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#Lynx:_"Llano"_(2011)">Llano</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#Virgo:_"Trinity"_(2012)">Trinity</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Richland"_(2013)">Richland</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Kaveri"_(2014)">Kaveri</a> </th> <th rowspan="2"><a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Kaveri Refresh (Godavari)</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Carrizo"_(2016)">Carrizo</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Bristol_Ridge"_(2016)">Bristol Ridge</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Raven_Ridge"_(2018)">Raven Ridge</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Picasso"_(2019)">Picasso</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Renoir"_(2020)">Renoir</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Cezanne"_(2021)">Cezanne</a> </th> <th> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry </th> <th colspan="2"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic </th> <th colspan="14"> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#"Kabini"_(2013,_SoC)">Kabini</a> </th> <th colspan="3"> </th> <th><a class="mw-selflink-fragment" href="#"Dalí"_(2020)">Dalí</a> </th> <th colspan="3"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Mobile</th> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance </th> <th colspan="9"> </th> <th><a class="mw-selflink-fragment" href="#H">Renoir</a> </th> <th><a class="mw-selflink-fragment" href="#H_2">Cezanne</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Rembrandt"_(2022)">Rembrandt</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Dragon_Range"_(2023)">Dragon Range</a> </th> <th> </th> <th rowspan="2" colspan="9"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#Sabine:_"Llano"_(2011)">Llano</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#Comal:_"Trinity"_(2012)">Trinity</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Richland"_(2013)_2">Richland</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Kaveri"_(2014)_2">Kaveri</a> </th> <th rowspan="2"> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Carrizo"_(2015)">Carrizo</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Bristol_Ridge"_(2016)_2">Bristol Ridge</a> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Raven_Ridge"_(2017)">Raven Ridge</a> </th> <th><a class="mw-selflink-fragment" href="#"Picasso"_(2019)_2">Picasso</a> </th> <th><a class="mw-selflink-fragment" href="#U">Renoir</a> <a class="mw-selflink-fragment" href="#"Lucienne"_(2021)">Lucienne</a> </th> <th><a class="mw-selflink-fragment" href="#U_2">Cezanne</a> <a class="mw-selflink-fragment" href="#"Barceló"_(2022)">Barceló</a> </th> <th><a class="mw-selflink-fragment" href="#"Phoenix"_(2023)">Phoenix</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry </th> <th colspan="6"> </th> <th colspan="5"> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Dalí"_(2020)">Dalí</a> </th> <th colspan="2"> </th> <th rowspan="2"><a class="mw-selflink-fragment" href="#"Mendocino"_(2022)">Mendocino</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic </th> <th colspan="14"> </th> <th><a class="mw-selflink-fragment" href="#Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)">Desna, Ontario, Zacate</a> </th> <th><a class="mw-selflink-fragment" href="#"Kabini",_"Temash"_(2013)">Kabini, Temash</a> </th> <th><a class="mw-selflink-fragment" href="#"Beema",_"Mullins"_(2014)">Beema, Mullins</a> </th> <th><a class="mw-selflink-fragment" href="#"Carrizo-L"_(2015)">Carrizo-L</a> </th> <th><a class="mw-selflink-fragment" href="#"Stoney_Ridge"_(2016)">Stoney Ridge</a> </th> <th><a class="mw-selflink-fragment" href="#"Pollock"_(2020)">Pollock</a> </th> <th> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="2">Embedded </th> <th> </th> <th><a class="mw-selflink-fragment" href="#Comal:_"Trinity"_(2012)_2">Trinity</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#"Bald_Eagle"_(2014)">Bald Eagle</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#"Merlin_Falcon"_(2015,_SoC)">Merlin Falcon</a>, <a class="mw-selflink-fragment" href="#I-Family:_"Brown_Falcon"_(2016,_SoC)">Brown Falcon</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)">Great Horned Owl</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#V2000-Family:_"Grey_Hawk"_(2020,_SoC)">Grey Hawk</a> </th> <th colspan="4"> </th> <th><a class="mw-selflink-fragment" href="#Brazos:_"Ontario"_and_"Zacate"_(2011)">Ontario, Zacate</a> </th> <th><a class="mw-selflink-fragment" href="#"Kabini"_(2013,_SoC)_2">Kabini</a> </th> <th><a class="mw-selflink-fragment" href="#"Steppe_Eagle"_(2014,_SoC)">Steppe Eagle</a>, <a class="mw-selflink-fragment" href="#"Crowned_Eagle"_(2014,_SoC)">Crowned Eagle</a>, <a class="mw-selflink-fragment" href="#LX-Family_(2016,_SoC)">LX-Family</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#J-Family:_"Prairie_Falcon"_(2016,_SoC)">Prairie Falcon</a> </th> <th><a class="mw-selflink-fragment" href="#R1000-Family:_"Banded_Kestrel"_(2019,_SoC)">Banded Kestrel</a> </th> <th> </th> <th><a class="mw-selflink-fragment" href="#R2000-Family:_"River_Hawk"_(2022,_SoC)">River Hawk</a> </th> <th> </th></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Released</td> <td>Aug 2011</td> <td>Oct 2012</td> <td>Jun 2013</td> <td>Jan 2014 </td> <td>2015</td> <td>Jun 2015</td> <td>Jun 2016</td> <td>Oct 2017</td> <td>Jan 2019</td> <td>Mar 2020 </td> <td>Jan 2021</td> <td>Jan 2022</td> <td>Sep 2022</td> <td>Jan 2023</td> <td>Jan 2011</td> <td>May 2013</td> <td>Apr 2014</td> <td>May 2015</td> <td>Feb 2016</td> <td>Apr 2019</td> <td>Jul 2020</td> <td>Jun 2022</td> <td>Nov 2022 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">CPU <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> </td> <td><a href="/wiki/AMD_10h" title="AMD 10h">K10</a> </td> <td colspan="2"><a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a> </td> <td colspan="2"><a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a> </td> <td><a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> </td> <td>"<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>"<a href="#cite_note-1">[1]</a> </td> <td><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> </td> <td><a href="/wiki/Zen%2B" title="Zen+">Zen+</a> </td> <td><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> </td> <td><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> </td> <td><a href="/wiki/Zen_3%2B" class="mw-redirect" title="Zen 3+">Zen 3+</a> </td> <td colspan="2"><a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> </td> <td><a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat</a> </td> <td><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a> </td> <td><a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a> </td> <td><a href="/wiki/Puma_(microarchitecture)#Puma+" title="Puma (microarchitecture)">Puma+</a><a href="#cite_note-2">[2]</a> </td> <td>"<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>" </td> <td colspan="2"><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> </td> <td><a href="/wiki/Zen%2B" title="Zen+">Zen+</a> </td> <td>"<a href="/wiki/Zen_2" title="Zen 2">Zen 2+</a>" </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">ISA</a></td> <td><a href="/wiki/X86-64" title="X86-64">x86-64</a> v1</td> <td colspan="4"><a href="/wiki/X86-64" title="X86-64">x86-64</a> v2</td> <td colspan="7"><a href="/wiki/X86-64" title="X86-64">x86-64</a> v3</td> <td colspan="2"><a href="/wiki/X86-64" title="X86-64">x86-64</a> v4</td> <td><a href="/wiki/X86-64" title="X86-64">x86-64</a> v1</td> <td colspan="3"><a href="/wiki/X86-64" title="X86-64">x86-64</a> v2</td> <td colspan="5"><a href="/wiki/X86-64" title="X86-64">x86-64</a> v3 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="5"><a href="/wiki/Template:AMD_CPU_sockets" title="Template:AMD CPU sockets">Socket</a> </td> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="4">Desktop </td> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Performance </td> <td colspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2"><a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3" colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Mainstream </td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="6"><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <th data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </th></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Entry </td> <td><a href="/wiki/Socket_FM1" title="Socket FM1">FM1</a> </td> <td colspan="2"><a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a> </td> <td colspan="2"><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a> </td> <td><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a><a href="#cite_note-3">[a]</a>, <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> </td> <td colspan="5"><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> </td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Basic </td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/wiki/Socket_AM1" title="Socket AM1">AM1</a> </td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> </td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="2">Other </td> <td><a href="/wiki/Socket_FS1" title="Socket FS1">FS1</a> </td> <td colspan="2"><a href="/wiki/Socket_FS1r2" class="mw-redirect" title="Socket FS1r2">FS1+</a>, <a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a> </td> <td colspan="2"><a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a> </td> <td colspan="2"><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a> </td> <td colspan="2"><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> </td> <td colspan="2"><a href="/w/index.php?title=Socket_FP6&action=edit&redlink=1" class="new" title="Socket FP6 (page does not exist)">FP6</a> </td> <td><a href="/w/index.php?title=Socket_FP7&action=edit&redlink=1" class="new" title="Socket FP7 (page does not exist)">FP7</a> </td> <td>FL1 </td> <td>FP7 FP7r2 FP8 </td> <td><a href="/wiki/Socket_FT1" title="Socket FT1">FT1</a> </td> <td><a href="/wiki/Socket_FT3" title="Socket FT3">FT3</a> </td> <td colspan="2"><a href="/wiki/Socket_FT3b" class="mw-redirect" title="Socket FT3b">FT3b</a> </td> <td><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a> </td> <td><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> </td> <td><a href="/w/index.php?title=Socket_FT5&action=edit&redlink=1" class="new" title="Socket FT5 (page does not exist)">FT5</a> </td> <td><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> </td> <td><a href="/w/index.php?title=Socket_FT6&action=edit&redlink=1" class="new" title="Socket FT6 (page does not exist)">FT6</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> version </td> <td colspan="3">2.0 </td> <td colspan="8">3.0 </td> <td>4.0 </td> <td>5.0 </td> <td>4.0 </td> <td colspan="4">2.0 </td> <td colspan="5">3.0 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Compute_Express_Link" title="Compute Express Link">CXL</a></td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab.</a> (<a href="/wiki/Nanometre" title="Nanometre">nm</a>) </td> <td colspan="3"><a href="/wiki/GlobalFoundries" title="GlobalFoundries">GF</a> <a href="/wiki/32_nm_process" title="32 nm process">32SHP</a> (<a href="/wiki/HKMG" class="mw-redirect" title="HKMG">HKMG</a> <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a>) </td> <td colspan="4">GF <a href="/wiki/32_nm_process" title="32 nm process">28SHP</a> (HKMG bulk) </td> <td>GF <a href="/wiki/14_nm_process" title="14 nm process">14LPP</a> (<a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> bulk) </td> <td>GF <a href="/wiki/14_nm_process" title="14 nm process">12LP</a> (FinFET bulk) </td> <td colspan="2"><a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">N7</a> (FinFET bulk) </td> <td>TSMC <a href="/wiki/7_nm_process" title="7 nm process">N6</a> (FinFET bulk) </td> <td>CCD: TSMC <a href="/wiki/5_nm_process" title="5 nm process">N5</a> (FinFET bulk) cIOD: TSMC <a href="/wiki/7_nm_process" title="7 nm process">N6</a> (FinFET bulk) </td> <td>TSMC <a href="/wiki/5_nm_process" title="5 nm process">4nm</a> (FinFET bulk) </td> <td>TSMC <a href="/wiki/45_nm_process" title="45 nm process">N40</a> (bulk) </td> <td>TSMC <a href="/wiki/32_nm_process" title="32 nm process">N28</a> (HKMG bulk) </td> <td colspan="3">GF 28SHP (HKMG bulk) </td> <td colspan="2">GF <a href="/wiki/14_nm_process" title="14 nm process">14LPP</a> (<a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> bulk) </td> <td>GF <a href="/wiki/14_nm_process" title="14 nm process">12LP</a> (FinFET bulk) </td> <td>TSMC <a href="/wiki/7_nm_process" title="7 nm process">N6</a> (FinFET bulk) </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> area (mm2)</td> <td>228</td> <td colspan="2">246</td> <td colspan="2">245</td> <td>245</td> <td>250</td> <td colspan="2">210<a href="#cite_note-4">[3]</a></td> <td>156 </td> <td>180</td> <td>210</td> <td>CCD: (2x) 70 cIOD: 122 </td> <td>178</td> <td>75 (+ 28 <a href="/wiki/List_of_AMD_chipsets#Fusion_controller_hubs_(FCH)" title="List of AMD chipsets">FCH</a>)</td> <td colspan="2">107</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td>125</td> <td>149</td> <td></td> <td></td> <td>~100 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Min <a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a> (W)</td> <td>35</td> <td colspan="4">17</td> <td colspan="4">12</td> <td colspan="2">10</td> <td>15</td> <td>65</td> <td>35</td> <td>4.5</td> <td>4</td> <td>3.95</td> <td>10</td> <td colspan="3">6</td> <td>12</td> <td>8 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APU <a href="/wiki/Thermal_Design_Power" class="mw-redirect" title="Thermal Design Power">TDP</a> (W)</td> <td colspan="3">100</td> <td colspan="2">95</td> <td colspan="6">65</td> <td>45</td> <td>170</td> <td>54</td> <td>18</td> <td colspan="5">25</td> <td>6</td> <td>54</td> <td>15 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock APU base clock (GHz)</td> <td>3</td> <td>3.8</td> <td>4.1</td> <td colspan="2">4.1</td> <td>3.7</td> <td>3.8</td> <td>3.6</td> <td>3.7</td> <td>3.8</td> <td>4.0</td> <td>3.3</td> <td>4.7</td> <td>4.3</td> <td>1.75</td> <td>2.2</td> <td>2</td> <td>2.2</td> <td>3.2</td> <td>2.6</td> <td>1.2</td> <td>3.35</td> <td>2.8 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APUs per node<a href="#cite_note-nodedef-5">[b]</a></td> <td colspan="14">1</td> <td colspan="9">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max core dies per CPU</td> <td colspan="12">1</td> <td>2</td> <td>1</td> <td colspan="9">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max CCX per core die</td> <td colspan="9">1</td> <td>2</td> <td colspan="4">1</td> <td colspan="9">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max cores per CCX</td> <td colspan="10">4</td> <td colspan="4">8</td> <td>2</td> <td colspan="3">4</td> <td colspan="3">2</td> <td colspan="2">4 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a><a href="#cite_note-apudef-6">[c]</a> <a href="/wiki/Multi-core_processor" title="Multi-core processor">cores</a> per APU</td> <td colspan="9">4</td> <td colspan="3">8</td> <td>16</td> <td>8</td> <td>2</td> <td colspan="3">4</td> <td colspan="3">2</td> <td colspan="2">4 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> per CPU core</td> <td colspan="7">1</td> <td colspan="7">2</td> <td colspan="5">1</td> <td colspan="4">2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Integer pipeline structure</td> <td>3+3</td> <td colspan="6">2+2</td> <td colspan="2">4+2</td> <td>4+2+1</td> <td colspan="4">1+3+3+1+2</td> <td colspan="4">1+1+1+1</td> <td>2+2</td> <td colspan="3">4+2</td> <td>4+2+1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">i386, i486, i586, CMOV, NOPL, i686, <a href="/wiki/Physical_Address_Extension" title="Physical Address Extension">PAE</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, CMPXCHG16B, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/Second_Level_Address_Translation#RVI" title="Second Level Address Translation">RVI</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, and 64-bit LAHF/SAHF</td> <td colspan="14" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="9" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/IOMMU" class="mw-redirect" title="IOMMU">IOMMU</a><a href="#cite_note-iommubios-7">[d]</a></td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="13">v2</td> <td colspan="2">v1</td> <td colspan="7">v2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES-NI</a>, <a href="/wiki/CLMUL" class="mw-redirect" title="CLMUL">CLMUL</a>, and <a href="/wiki/F16C" title="F16C">F16C</a> </td> <td colspan="13" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="9" rowspan="2" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">MOVBE</td> <td colspan="5" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="2" colspan="9" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/X86_virtualization#Interrupt_virtualization_(AMD_AVIC_and_Intel_APICv)" title="X86 virtualization">AVIC</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2_(Bit_Manipulation_Instruction_Set_2))" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, and MWAITX/MONITORX </td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="5" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/w/index.php?title=AMD_SME&action=edit&redlink=1" class="new" title="AMD SME (page does not exist)">SME</a><a href="#cite_note-firmware-8">[e]</a>, <a href="/w/index.php?title=TSME&action=edit&redlink=1" class="new" title="TSME (page does not exist)">TSME</a><a href="#cite_note-firmware-8">[e]</a>, <a href="/wiki/Intel_ADX" title="Intel ADX">ADX</a>, <a href="/wiki/Intel_SHA_extensions" class="mw-redirect" title="Intel SHA extensions">SHA</a>, <a href="/wiki/RDSEED" class="mw-redirect" title="RDSEED">RDSEED</a>, <a href="/wiki/Supervisor_Mode_Access_Prevention" title="Supervisor Mode Access Prevention">SMAP</a>, <a href="/wiki/Control_register#SMEP" title="Control register">SMEP</a>, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing</td> <td colspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="7" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Second_Level_Address_Translation#Mode_Based_Execution_Control" title="Second Level Address Translation">GMET</a>, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="5" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="8" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Memory_protection#Protection_keys" title="Memory protection">MPK</a>, <a href="/w/index.php?title=VAES&action=edit&redlink=1" class="new" title="VAES (page does not exist)">VAES</a></td> <td colspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Software_Guard_Extensions" title="Software Guard Extensions">SGX</a></td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a> per <a href="/wiki/Multi-core_processor" title="Multi-core processor">core</a></td> <td>1</td> <td colspan="6">0.5</td> <td colspan="7">1</td> <td colspan="4">1</td> <td>0.5</td> <td colspan="4">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Pipes per FPU</td> <td colspan="14">2</td> <td colspan="9">2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">FPU pipe width</td> <td colspan="9">128-bit</td> <td colspan="5">256-bit</td> <td>80-bit</td> <td colspan="7">128-bit</td> <td>256-bit </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">CPU <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> level</td> <td><a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a><a href="#cite_note-sse4a-9">[f]</a></td> <td colspan="4"><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> </td> <td colspan="7"><a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a></td> <td colspan="2"><a href="/wiki/AVX-512" title="AVX-512">AVX-512</a></td> <td><a href="/wiki/SSSE3" title="SSSE3">SSSE3</a></td> <td colspan="3"><a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a></td> <td colspan="5"><a href="/wiki/Advanced_Vector_Extensions#Advanced_Vector_Extensions_2" title="Advanced Vector Extensions">AVX2</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/3DNow!" title="3DNow!">3DNow!</a></td> <td><a href="/wiki/3DNow!#3DNow_extensions" title="3DNow!">3DNow!+</a></td> <td colspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/PREFETCHW" class="mw-redirect" title="PREFETCHW">PREFETCH/PREFETCHW</a></td> <td colspan="14" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="9" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/w/index.php?title=GFNI&action=edit&redlink=1" class="new" title="GFNI (page does not exist)">GFNI</a></td> <td colspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="2" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td rowspan="2" colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/Advanced_Matrix_Extensions" title="Advanced Matrix Extensions">AMX</a></td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/FMA4" class="mw-redirect" title="FMA4">FMA4</a>, LWP, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, and <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a></td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="6" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></td> <td colspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/FMA3" class="mw-redirect" title="FMA3">FMA3</a></td> <td colspan="13" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="5" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/AMD_XDNA" title="AMD XDNA">AMD XDNA</a></td> <td colspan="13" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> data cache per core (KiB)</td> <td>64</td> <td colspan="4">16</td> <td colspan="9">32</td> <td colspan="9">32 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 data cache <a href="/wiki/Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td> <td>2</td> <td colspan="4">4</td> <td colspan="9">8</td> <td colspan="9">8 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 instruction caches per <a href="/wiki/Multi-core_processor" title="Multi-core processor">core</a></td> <td>1</td> <td colspan="6">0.5</td> <td colspan="7">1 </td> <td colspan="4">1</td> <td>0.5</td> <td colspan="4">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APU total L1 instruction cache (KiB)</td> <td>256</td> <td colspan="2">128</td> <td colspan="4">192</td> <td colspan="5">256</td> <td>512</td> <td>256 </td> <td colspan="2">64</td> <td colspan="2">128 </td> <td>96 </td> <td colspan="4">128 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L1 instruction cache <a href="/wiki/Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td> <td colspan="3">2</td> <td colspan="4">3</td> <td colspan="2">4</td> <td colspan="5">8 </td> <td colspan="4">2 </td> <td>3 </td> <td colspan="3">4 </td> <td>8 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2 caches</a> per <a href="/wiki/Multi-core_processor" title="Multi-core processor">core</a></td> <td>1</td> <td colspan="6">0.5</td> <td colspan="7">1</td> <td colspan="4">1</td> <td>0.5</td> <td colspan="4">1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max APU total L2 cache (MiB)</td> <td colspan="5">4</td> <td colspan="4">2</td> <td colspan="3">4</td> <td>16</td> <td></td> <td>1</td> <td colspan="3">2</td> <td colspan="3">1</td> <td colspan="2">2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L2 cache <a href="/wiki/Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td> <td colspan="7">16</td> <td colspan="7">8</td> <td colspan="5">16</td> <td colspan="4">8 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max on--die <a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per CCX (MiB)</td> <td colspan="7" rowspan="8" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="3">4</td> <td colspan="2">16</td> <td>32</td> <td></td> <td colspan="6" rowspan="8" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4">4 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max 3D V-Cache per CCD (MiB)</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>64</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max total in-CCD <a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td> <td colspan="2">4</td> <td>8</td> <td colspan="2">16</td> <td>64</td> <td></td> <td colspan="4">4 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. total 3D V-Cache per APU (MiB)</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>64</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. board <a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td> <td colspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max total <a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3 cache</a> per APU (MiB)</td> <td colspan="2">4</td> <td>8</td> <td colspan="2">16</td> <td>128</td> <td></td> <td colspan="4">4 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">APU L3 cache <a href="/wiki/Cache_placement_policies#Set-associative_cache" title="Cache placement policies">associativity</a> (ways)</td> <td colspan="7">16</td> <td colspan="4">16 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">L3 cache scheme</td> <td colspan="7"><a href="/wiki/Victim_cache" title="Victim cache">Victim</a></td> <td colspan="4"><a href="/wiki/Victim_cache" title="Victim cache">Victim</a> </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max. <a href="/wiki/L4_cache" class="mw-redirect" title="L4 cache">L4 cache</a></td> <td colspan="14" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> support</td> <td colspan="2"><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a>-1866</td> <td colspan="3">DDR3-2133</td> <td>DDR3-2133, <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-2400</td> <td>DDR4-2400</td> <td colspan="2">DDR4-2933</td> <td colspan="2">DDR4-3200, <a href="/wiki/LPDDR#LPDDR4" title="LPDDR">LPDDR4</a>-4266</td> <td><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-4800, <a href="/wiki/LPDDR#LPDDR5" title="LPDDR">LPDDR5</a>-6400</td> <td><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-5200</td> <td><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-5600, <a href="/wiki/LPDDR#LPDDR5x" title="LPDDR">LPDDR5x</a>-7500</td> <td><a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1333</td> <td>DDR3L-1600</td> <td colspan="2">DDR3L-1866</td> <td>DDR3-1866, <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-2400</td> <td>DDR4-2400</td> <td>DDR4-1600</td> <td>DDR4-3200</td> <td>LPDDR5-5500 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> channels per APU</td> <td colspan="14">2</td> <td colspan="5">1</td> <td>2</td> <td>1</td> <td colspan="2">2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> (GB/s) per APU</td> <td colspan="2">29.866</td> <td colspan="3">34.132</td> <td colspan="2">38.400</td> <td colspan="2">46.932</td> <td colspan="2">68.256</td> <td>102.400</td> <td>83.200</td> <td>120.000 </td> <td>10.666</td> <td>12.800</td> <td colspan="2">14.933</td> <td>19.200</td> <td>38.400</td> <td>12.800</td> <td>51.200</td> <td>88.000 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a></td> <td><a href="/wiki/TeraScale_(microarchitecture)#TeraScale_2_"Evergreen"-family" title="TeraScale (microarchitecture)">TeraScale 2 (VLIW5)</a></td> <td colspan="2"><a href="/wiki/TeraScale_(microarchitecture)#TeraScale_3_"Northern_Islands"-family" title="TeraScale (microarchitecture)">TeraScale 3 (VLIW4)</a></td> <td colspan="2"><a href="/wiki/Graphics_Core_Next#GCN_2nd_generation" title="Graphics Core Next">GCN 2nd gen</a></td> <td colspan="2"><a href="/wiki/Graphics_Core_Next#GCN_3rd_generation" title="Graphics Core Next">GCN 3rd gen</a></td> <td colspan="4"><a href="/wiki/Graphics_Core_Next#GCN_5th_generation" title="Graphics Core Next">GCN 5th gen</a><a href="#cite_note-Vega_codenames-10">[4]</a></td> <td colspan="2"><a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a></td> <td><a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a></td> <td><a href="/wiki/TeraScale_(microarchitecture)#TeraScale_2_"Evergreen"-family" title="TeraScale (microarchitecture)">TeraScale 2 (VLIW5)</a></td> <td colspan="3"><a href="/wiki/Graphics_Core_Next#GCN_2nd_generation" title="Graphics Core Next">GCN 2nd gen</a></td> <td><a href="/wiki/Graphics_Core_Next#GCN_3rd_generation" title="Graphics Core Next">GCN 3rd gen</a><a href="#cite_note-Vega_codenames-10">[4]</a></td> <td colspan="3"><a href="/wiki/Graphics_Core_Next#GCN_5th_generation" title="Graphics Core Next">GCN 5th gen</a></td> <td><a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a></td> <td colspan="3"><a href="/wiki/TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a> instruction set</td> <td colspan="8"><a href="/wiki/Graphics_Core_Next#Instruction_set" title="Graphics Core Next">GCN instruction set</a></td> <td colspan="3"><a href="/wiki/RDNA_(microarchitecture)#Instruction_set" title="RDNA (microarchitecture)">RDNA instruction set</a></td> <td><a href="/wiki/TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a> instruction set</td> <td colspan="7"><a href="/wiki/Graphics_Core_Next#Instruction_set" title="Graphics Core Next">GCN instruction set</a></td> <td><a href="/wiki/RDNA_(microarchitecture)#Instruction_set" title="RDNA (microarchitecture)">RDNA instruction set</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock GPU base clock (MHz)</td> <td>600</td> <td>800</td> <td>844</td> <td colspan="2">866</td> <td colspan="2">1108</td> <td>1250</td> <td>1400</td> <td colspan="2">2100</td> <td>2400</td> <td>400</td> <td> </td> <td>538</td> <td>600</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td>847</td> <td>900</td> <td>1200</td> <td>600</td> <td>1300</td> <td>1900 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Max stock GPU base <a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-11">[g]</a></td> <td>480</td> <td>614.4</td> <td>648.1</td> <td colspan="2">886.7</td> <td colspan="2">1134.5</td> <td>1760</td> <td>1971.2</td> <td colspan="2">2150.4</td> <td>3686.4</td> <td>102.4</td> <td> </td> <td>86</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td>345.6</td> <td>460.8</td> <td>230.4</td> <td>1331.2</td> <td>486.4 </td></tr> <tr style="border-top:0.2em solid grey"> <td rowspan="2" style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">3D engine<a href="#cite_note-12">[h]</a></td> <td>Up to 400:20:8</td> <td colspan="2">Up to 384:24:6</td> <td colspan="4">Up to 512:32:8</td> <td colspan="2">Up to 704:44:16<a href="#cite_note-13">[5]</a></td> <td colspan="2">Up to 512:32:8</td> <td>768:48:8</td> <td>128:8:4</td> <td></td> <td>80:8:4</td> <td colspan="3">128:8:4</td> <td>Up to 192:12:8</td> <td>Up to 192:12:4</td> <td>192:12:4</td> <td>Up to 512:?:?</td> <td>128:?:? </td></tr> <tr> <td colspan="3">IOMMUv1</td> <td colspan="11"><a href="/wiki/Heterogeneous_Memory_Management" class="mw-redirect" title="Heterogeneous Memory Management">IOMMUv2</a></td> <td colspan="2">IOMMUv1</td> <td colspan="2" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td colspan="5">IOMMUv2 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Video decoder</td> <td colspan="3"><a href="/wiki/Unified_Video_Decoder#UVD_3" title="Unified Video Decoder">UVD 3.0</a></td> <td colspan="2"><a href="/wiki/Unified_Video_Decoder#UVD_4.2" title="Unified Video Decoder">UVD 4.2</a></td> <td colspan="2"><a href="/wiki/Unified_Video_Decoder#UVD_6" title="Unified Video Decoder">UVD 6.0</a></td> <td rowspan="2" colspan="2"><a href="/wiki/Video_Core_Next" title="Video Core Next">VCN</a> 1.0<a href="#cite_note-14">[6]</a></td> <td rowspan="2">VCN 2.1<a href="#cite_note-wccftechCezanne-15">[7]</a> </td> <td rowspan="2">VCN 2.2<a href="#cite_note-wccftechCezanne-15">[7]</a></td> <td colspan="2" rowspan="2">VCN 3.1</td> <td rowspan="2" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td><a href="/wiki/Unified_Video_Decoder#UVD_3" title="Unified Video Decoder">UVD 3.0</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_4" title="Unified Video Decoder">UVD 4.0</a></td> <td colspan="2"><a href="/wiki/Unified_Video_Decoder#UVD_4.2" title="Unified Video Decoder">UVD 4.2</a></td> <td><a href="/wiki/Unified_Video_Decoder#UVD_6" title="Unified Video Decoder">UVD 6.2</a></td> <td rowspan="2" colspan="3"><a href="/wiki/Video_Core_Next" title="Video Core Next">VCN 1.0</a></td> <td rowspan="2">VCN 3.1 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">Video encoder</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="2"><a href="/wiki/Video_Coding_Engine#VCE_1.0" title="Video Coding Engine">VCE 1.0</a></td> <td colspan="2"><a href="/wiki/Video_Coding_Engine#VCE_2.0" title="Video Coding Engine">VCE 2.0</a></td> <td colspan="2"><a href="/wiki/Video_Coding_Engine#VCE_3.0" title="Video Coding Engine">VCE 3.1</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="3"><a href="/wiki/Video_Coding_Engine#VCE_2.0" title="Video Coding Engine">VCE 2.0</a></td> <td><a href="/wiki/Video_Coding_Engine#VCE_3.0" title="Video Coding Engine">VCE 3.4</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">AMD Fluid Motion </td> <td colspan="3" data-sort-value="No" style="background: #FFE3E3; color:black; vertical-align: middle; text-align: center;" class="skin-invert table-no2"><img alt="No" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/13px-Dark_Red_x.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/20px-Dark_Red_x.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/26px-Dark_Red_x.svg.png 2x" data-file-width="600" data-file-height="600" /> </td> <td colspan="4" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="7" data-sort-value="No" style="background: #FFE3E3; color:black; vertical-align: middle; text-align: center;" class="skin-invert table-no2"><img alt="No" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/13px-Dark_Red_x.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/20px-Dark_Red_x.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/26px-Dark_Red_x.svg.png 2x" data-file-width="600" data-file-height="600" /> </td> <td colspan="2" data-sort-value="No" style="background: #FFE3E3; color:black; vertical-align: middle; text-align: center;" class="skin-invert table-no2"><img alt="No" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/13px-Dark_Red_x.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/20px-Dark_Red_x.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/26px-Dark_Red_x.svg.png 2x" data-file-width="600" data-file-height="600" /> </td> <td colspan="3" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td colspan="4" data-sort-value="No" style="background: #FFE3E3; color:black; vertical-align: middle; text-align: center;" class="skin-invert table-no2"><img alt="No" src="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/13px-Dark_Red_x.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/20px-Dark_Red_x.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/48/Dark_Red_x.svg/26px-Dark_Red_x.svg.png 2x" data-file-width="600" data-file-height="600" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3">GPU power saving</td> <td><a href="/wiki/AMD_PowerPlay" title="AMD PowerPlay">PowerPlay</a></td> <td colspan="13"><a href="/wiki/AMD_PowerTune" title="AMD PowerTune">PowerTune</a></td> <td><a href="/wiki/AMD_PowerPlay" title="AMD PowerPlay">PowerPlay</a></td> <td colspan="8"><a href="/wiki/AMD_PowerTune" title="AMD PowerTune">PowerTune</a><a href="#cite_note-16">[8]</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a></td> <td colspan="3" rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="7" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /><a href="#cite_note-17">[9]</a></td> <td colspan="4" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">? </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="8" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/FreeSync" title="FreeSync">FreeSync</a></td> <td colspan="11" style="background:#DFD">1 2 </td> <td colspan="88" style="background:#DFD">1 2 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/HDCP" class="mw-redirect" title="HDCP">HDCP</a><a href="#cite_note-DRM-18">[i]</a></td> <td colspan="3" style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td colspan="4">1.4</td> <td colspan="4">2.2</td> <td colspan="3">2.3</td> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">?</td> <td colspan="4">1.4</td> <td colspan="3">2.2</td> <td>2.3 </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/PlayReady" title="PlayReady">PlayReady</a><a href="#cite_note-DRM-18">[i]</a></td> <td colspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="7">3.0 not yet</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="4">3.0 not yet </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">Supported displays</a><a href="#cite_note-20">[j]</a></td> <td>2–3</td> <td colspan="4">2–4</td> <td colspan="2">3</td> <td colspan="2">3 (desktop) 4 (mobile, embedded)</td> <td colspan="5">4</td> <td colspan="4">2</td> <td>3</td> <td>4</td> <td></td> <td colspan="2">4 </td></tr> <tr style="border-top:0.2em solid grey"> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><code>/drm/radeon</code><a href="#cite_note-drm-21">[k]</a><a href="#cite_note-22">[11]</a><a href="#cite_note-Radeon_Feature_Matrix-23">[12]</a></td> <td colspan="6" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></td> <td colspan="8" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td colspan="4" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /></td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" colspan="3"><code>/drm/amdgpu</code><a href="#cite_note-drm-21">[k]</a><a href="#cite_note-24">[13]</a></td> <td colspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="11" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /><a href="#cite_note-amdgpu_1.2-25">[14]</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="8" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /><a href="#cite_note-amdgpu_1.2-25">[14]</a> </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-3"><a href="#cite_ref-3">^</a> For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845. </li> <li id="cite_note-nodedef-5"><a href="#cite_ref-nodedef_5-0">^</a> A PC would be one node. </li> <li id="cite_note-apudef-6"><a href="#cite_ref-apudef_6-0">^</a> An APU combines a CPU and a GPU. Both have cores. </li> <li id="cite_note-iommubios-7"><a href="#cite_ref-iommubios_7-0">^</a> Requires firmware support. </li> <li id="cite_note-firmware-8">^ <a href="#cite_ref-firmware_8-0">a</a> <a href="#cite_ref-firmware_8-1">b</a> Requires firmware support. </li> <li id="cite_note-sse4a-9"><a href="#cite_ref-sse4a_9-0">^</a> No SSE4. No SSSE3. </li> <li id="cite_note-SFLOPS-11"><a href="#cite_ref-SFLOPS_11-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> <li id="cite_note-12"><a href="#cite_ref-12">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> </li> <li id="cite_note-DRM-18">^ <a href="#cite_ref-DRM_18-0">a</a> <a href="#cite_ref-DRM_18-1">b</a> To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup. </li> <li id="cite_note-20"><a href="#cite_ref-20">^</a> To feed more than two displays, the additional panels must have native <a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a> support.<a href="#cite_note-19">[10]</a> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed. </li> <li id="cite_note-drm-21">^ <a href="#cite_ref-drm_21-0">a</a> <a href="#cite_ref-drm_21-1">b</a> DRM (<a href="/wiki/Direct_Rendering_Manager" title="Direct Rendering Manager">Direct Rendering Manager</a>) is a component of the Linux kernel. Support in this table refers to the most current version. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Graphics_API_overview">Graphics API overview</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=2" title="Edit section: Graphics API overview">edit</a>]</div> The following table shows the graphics and compute <a href="/wiki/API" title="API">APIs</a> support across ATI/AMD GPU microarchitectures. Note that a branding series might include older generation chips. <div style="clear:both;" class=""></div><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist" style="position: relative; bottom: -11px;">[ <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Template:AMD_graphics_API_support&veaction=edit">VisualEditor</a> ] <ul class="navbar-brackets"><li class="nv-view"><a href="/wiki/Template:AMD_graphics_API_support" title="Template:AMD graphics API support">view</a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_graphics_API_support" title="Template talk:AMD graphics API support">talk</a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_graphics_API_support" title="Special:EditPage/Template:AMD graphics API support">edit</a></li></ul></div> <table class="wikitable" style="font-size: 85%; text-align: center;"> <tbody><tr> <th rowspan="3">Chip series </th> <th rowspan="3">Microarchitecture </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="5">Supported <a href="/wiki/API" title="API">APIs</a> </th> <th rowspan="3">AMD support </th> <th rowspan="3">Year introduced </th> <th rowspan="3">Introduced with </th></tr> <tr> <th colspan="3"><a href="/wiki/Rendering_(computer_graphics)" title="Rendering (computer graphics)">Rendering</a> </th> <th colspan="2">Computing / <a href="/wiki/ROCm" title="ROCm">ROCm</a> </th></tr> <tr> <th style="width:10em;"><a href="/wiki/Vulkan" title="Vulkan">Vulkan</a><a href="#cite_note-26">[15]</a> </th> <th style="width:10em;"><a href="/wiki/OpenGL" title="OpenGL">OpenGL</a><a href="#cite_note-27">[16]</a> </th> <th style="width:10em;"><a href="/wiki/Direct3D" title="Direct3D">Direct3D</a> </th> <th style="width:10em;"><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">HSA</a> </th> <th style="width:10em;"><a href="/wiki/OpenCL" title="OpenCL">OpenCL</a> </th></tr> <tr> <th><a href="/wiki/ATI_Wonder" title="ATI Wonder">Wonder</a> </th> <td rowspan="6">Fixed-pipeline<a href="#cite_note-r100_shader-28">[a]</a> </td> <td>1000 nm 800 nm </td> <td rowspan="15" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="15" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="18" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">Ended </td> <td>1986 </td> <td style="text-align:left;">Graphics Solutions </td></tr> <tr> <th><a href="/wiki/ATI_Mach_series" class="mw-redirect" title="ATI Mach series">Mach</a> </th> <td>800 nm 600 nm </td> <td>1991 </td> <td style="text-align:left;">Mach8 </td></tr> <tr> <th><a href="/wiki/ATI_Rage_series" class="mw-redirect" title="ATI Rage series">3D Rage</a> </th> <td>500 nm </td> <td>5.0 </td> <td>1996 </td> <td style="text-align:left;">3D Rage </td></tr> <tr> <th><a href="/wiki/ATI_Rage_series" class="mw-redirect" title="ATI Rage series">Rage Pro</a> </th> <td>350 nm </td> <td>1.1 </td> <td rowspan="2">6.0 </td> <td>1997 </td> <td style="text-align:left;">Rage Pro </td></tr> <tr> <th><a href="/wiki/ATI_Rage_series" class="mw-redirect" title="ATI Rage series">Rage 128</a> </th> <td>250 nm </td> <td>1.2 </td> <td>1998 </td> <td style="text-align:left;">Rage 128 GL/VR </td></tr> <tr> <th><a href="/wiki/Radeon_R100_series" title="Radeon R100 series">R100</a> </th> <td>180 nm 150 nm </td> <td rowspan="2">1.3 </td> <td rowspan="1">7.0 </td> <td>2000 </td> <td style="text-align:left;">Radeon </td></tr> <tr> <th><a href="/wiki/Radeon_R200_series" title="Radeon R200 series">R200</a> </th> <td rowspan="4">Programmable pixel & vertex pipelines </td> <td rowspan="1">150 nm </td> <td>8.1 </td> <td>2001 </td> <td style="text-align:left">Radeon 8500 </td></tr> <tr> <th><a href="/wiki/Radeon_R300_series" title="Radeon R300 series">R300</a> </th> <td rowspan="1">150 nm 130 nm 110 nm </td> <td rowspan="3">2.0<a href="#cite_note-nonpot-29">[b]</a> </td> <td rowspan="1">9.0 11 (<a href="/wiki/Direct3D_feature_level" class="mw-redirect" title="Direct3D feature level">FL 9_2</a>) </td> <td>2002 </td> <td style="text-align:left;">Radeon 9700 </td></tr> <tr> <th><a href="/wiki/Radeon_R400_series" title="Radeon R400 series">R420</a> </th> <td>130 nm 110 nm </td> <td>9.0b 11 (FL 9_2) </td> <td>2004 </td> <td style="text-align:left;">Radeon X800 </td></tr> <tr> <th><a href="/wiki/Radeon_X1000_series" title="Radeon X1000 series">R520</a> </th> <td>90 nm 80 nm </td> <td>9.0c 11 (FL 9_3) </td> <td>2005 </td> <td style="text-align:left">Radeon X1800 </td></tr> <tr> <th><a href="/wiki/Radeon_HD_2000_series" title="Radeon HD 2000 series">R600</a> </th> <td rowspan="3"><a href="/wiki/TeraScale_(microarchitecture)#TeraScale_1" title="TeraScale (microarchitecture)">TeraScale 1</a> </td> <td>80 nm 65 nm </td> <td rowspan="3">3.3 </td> <td>10.0 11 (FL 10_0) </td> <td><a href="/wiki/Close_to_Metal" title="Close to Metal">ATI Stream</a> </td> <td rowspan="2">2007 </td> <td style="text-align:left;">Radeon HD 2900 XT </td></tr> <tr> <th><a href="/wiki/Radeon_HD_3000_series" title="Radeon HD 3000 series">RV670</a> </th> <td rowspan="1">55 nm </td> <td rowspan="2">10.1 11 (FL 10_1) </td> <td><a href="/wiki/AMD_APP_SDK" title="AMD APP SDK">ATI Stream APP</a><a href="#cite_note-30">[17]</a> </td> <td style="text-align:left">Radeon HD 3850/3870 </td></tr> <tr> <th><a href="/wiki/Radeon_HD_4000_series" title="Radeon HD 4000 series">RV770</a> </th> <td rowspan="1">55 nm 40 nm </td> <td>1.0 </td> <td>2008 </td> <td style="text-align:left;">Radeon HD 4850/4870 </td></tr> <tr> <th><a href="/wiki/Radeon_HD_5000_series" title="Radeon HD 5000 series">Evergreen</a> </th> <td><a href="/wiki/TeraScale_(microarchitecture)#TeraScale_2" title="TeraScale (microarchitecture)">TeraScale 2</a> </td> <td rowspan="2">40 nm </td> <td rowspan="2">4.5 (Linux 4.2) <a href="#cite_note-31">[18]</a><a href="#cite_note-32">[19]</a><a href="#cite_note-33">[20]</a><a href="#cite_note-nofp64-34">[c]</a> </td> <td rowspan="2">11 (FL 11_0) </td> <td rowspan="2">1.2 </td> <td>2009 </td> <td style="text-align:left;">Radeon HD 5850/5870 </td></tr> <tr> <th><a href="/wiki/Radeon_HD_6000_series" title="Radeon HD 6000 series">Northern Islands</a> </th> <td>TeraScale 2 <a href="/wiki/TeraScale_(microarchitecture)#TeraScale_3" title="TeraScale (microarchitecture)">TeraScale 3</a> </td> <td>2010 </td> <td style="text-align:left;">Radeon HD 6850/6870 Radeon HD 6950/6970 </td></tr> <tr> <th><a href="/wiki/Radeon_HD_7000_series" title="Radeon HD 7000 series">Southern Islands</a> </th> <td><a href="/wiki/Graphics_Core_Next#first" title="Graphics Core Next">GCN 1st gen</a> </td> <td rowspan="3">28 nm </td> <td rowspan="1">1.0 </td> <td rowspan="9">4.6 </td> <td>11 (FL 11_1) 12 (FL11_1) </td> <td rowspan="9" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert"><img alt="Yes" src="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/13px-Check-green.svg.png" decoding="async" width="13" height="13" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/20px-Check-green.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/26/Check-green.svg/26px-Check-green.svg.png 2x" data-file-width="512" data-file-height="512" /> </td> <td>1.2 2.0 possible </td> <td>2012 </td> <td style="text-align:left;">Radeon HD 7950/7970 </td></tr> <tr> <th><a href="/wiki/Radeon_200_series" title="Radeon 200 series">Sea Islands</a> </th> <td><a href="/wiki/Graphics_Core_Next#second" title="Graphics Core Next">GCN 2nd gen</a> </td> <td rowspan="2">1.2 </td> <td rowspan="4">11 (FL 12_0) 12 (FL 12_0) </td> <td rowspan="8">2.0 (1.2 in MacOS, Linux) 2.1 Beta in Linux ROCm 2.2 possible </td> <td>2013 </td> <td style="text-align:left;">Radeon HD 7790 </td></tr> <tr> <th><a href="/wiki/Radeon_300_series" title="Radeon 300 series">Volcanic Islands</a> </th> <td><a href="/wiki/Graphics_Core_Next#third" title="Graphics Core Next">GCN 3rd gen</a> </td> <td>2014 </td> <td style="text-align:left;">Radeon R9 285 </td></tr> <tr> <th><a href="/wiki/Radeon_400_series" title="Radeon 400 series">Arctic Islands</a> </th> <td rowspan="2"><a href="/wiki/Graphics_Core_Next#fourth" title="Graphics Core Next">GCN 4th gen</a> </td> <td rowspan="2">28 nm 14 nm </td> <td rowspan="2">1.2 1.3 (GCN 4) </td> <td rowspan="6" data-sort-value="Yes" style="background: #DFD; color:black; vertical-align: middle; text-align: center;" class="table-yes2 skin-invert">Supported </td> <td>2016 </td> <td style="text-align:left">Radeon RX 480 </td></tr> <tr> <th><a href="/wiki/Radeon_500_series" title="Radeon 500 series">Polaris</a> </th> <td>2017 </td> <td style="text-align:left">Radeon 520/530 Radeon RX 530/550/570/580 </td></tr> <tr> <th><a href="/wiki/Radeon_RX_Vega_series" title="Radeon RX Vega series">Vega</a> </th> <td><a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th gen</a> </td> <td>14 nm 7 nm </td> <td rowspan="4">1.3 </td> <td rowspan="2">11 (FL 12_1) 12 (FL 12_1) </td> <td>2017 </td> <td style="text-align:left;">Radeon Vega Frontier Edition </td></tr> <tr> <th><a href="/wiki/Radeon_RX_5000_series" title="Radeon RX 5000 series">Navi</a> </th> <td><a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a> </td> <td>7 nm </td> <td>2019 </td> <td style="text-align:left;">Radeon RX 5700 (XT) </td></tr> <tr> <th><a href="/wiki/Radeon_RX_6000_series" title="Radeon RX 6000 series">Navi 2X</a> </th> <td><a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> </td> <td>7 nm 6 nm </td> <td rowspan="2">11 (FL 12_1) 12 (FL 12_2) </td> <td>2020 </td> <td style="text-align:left;">Radeon RX 6800 (XT) </td></tr> <tr> <th><a href="/wiki/Radeon_RX_7000_series" title="Radeon RX 7000 series">Navi 3X</a> </th> <td><a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a> </td> <td>6 nm 5 nm </td> <td>2022 </td> <td style="text-align:left;">Radeon RX 7900 XT(X) </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-r100_shader-28"><a href="#cite_ref-r100_shader_28-0">^</a> Radeon 7000 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on <a href="/wiki/Radeon_R100_series#R100's_pixel_shaders" title="Radeon R100 series">R100's pixel shaders</a>. </li> <li id="cite_note-nonpot-29"><a href="#cite_ref-nonpot_29-0">^</a> These series do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power-of-two (NPOT) textures. </li> <li id="cite_note-nofp64-34"><a href="#cite_ref-nofp64_34-0">^</a> OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware. </li> </ol></div></div> <a href="#cite_note-THWGCN-35">[21]</a><a href="#cite_note-THW_radeon_8000_plans-36">[22]</a><a href="#cite_note-Radeon_VEGA_Frontier_Edition-37">[23]</a> <div class="mw-heading mw-heading2"><h2 id="Desktop_processors_with_3D_graphics">Desktop processors with 3D graphics</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=3" title="Edit section: Desktop processors with 3D graphics">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="APU_or_Radeon_Graphics_branded">APU or Radeon Graphics branded</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=4" title="Edit section: APU or Radeon Graphics branded">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Lynx:_"Llano"_(2011)">Lynx: "Llano" (2011)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=5" title="Edit section: Lynx: "Llano" (2011)">edit</a>]</div> <ul><li>Socket <a href="/wiki/Socket_FM1" title="Socket FM1">FM1</a></li> <li>CPU: <a href="/wiki/AMD_10h" title="AMD 10h">K10</a> (also Husky or K10.5) cores with an upgraded Stars architecture, no L3 cache <ul><li>L1 cache: 64 KB Data per core and 64 KB Instruction cache per core</li> <li>L2 cache: 512 KB on dual-core, 1 MB on tri- and quad-core models</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/3DNow!" title="3DNow!">Enhanced 3DNow!</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/Amd64" class="mw-redirect" title="Amd64">AMD64</a>, <a href="/wiki/Cool%27n%27Quiet" title="Cool'n'Quiet">Cool'n'Quiet</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li></ul></li> <li>GPU: <a href="/wiki/TeraScale_2" class="mw-redirect" title="TeraScale 2">TeraScale 2 (Evergreen)</a>; all A and E series models feature Redwood-class integrated graphics on die (BeaverCreek for the dual-core variants and WinterPark for the quad-core variants). Sempron and Athlon models exclude integrated graphics.<a href="#cite_note-athlon-38">[24]</a></li> <li><a href="/wiki/List_of_AMD_graphics_processing_units#IGP_(HD_6000)" title="List of AMD graphics processing units">List of embedded GPU's</a></li> <li>Support for up to four <a href="/wiki/DIMM" title="DIMM">DIMMs</a> of up to <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>-1866 memory</li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a> <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a> process; <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 228 mm2, with 1.178 billion transistors<a href="#cite_note-39">[25]</a><a href="#cite_note-AnandTech_TrinityReview-40">[26]</a></li> <li>5 GT/s <a href="/wiki/UMI_AMD" class="mw-redirect" title="UMI AMD">UMI</a></li> <li>Integrated <a href="/wiki/PCIE#PCI_Express_2.0" class="mw-redirect" title="PCIE">PCIe 2.0</a> controller</li> <li>Select models support Turbo Core technology for faster CPU operation when the thermal specification permits</li> <li>Select models support Hybrid Graphics technology to assist a discrete Radeon HD 6450, 6570, or 6670 discrete graphics card. This is similar to the Hybrid CrossFireX technology available in the AMD 700 and 800 chipset series</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model<a href="#cite_note-fn_4-41">[note 1]</a> </th> <th rowspan="3">Released </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th rowspan="3"><a href="/wiki/Stepping_level" title="Stepping level">Step.</a> </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-43">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-44">[b]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Sempron X2 198 </th> <td>2012 </td> <td rowspan="21">32 nm SOI </td> <td rowspan="21">LN-B0 </td> <td rowspan="2">2 (2) </td> <td>2.5 </td> <td rowspan="12" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="21">64 KB inst. 64 KB data per core </td> <td rowspan="2">2×512 KB </td> <td rowspan="8" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">1600 </td> <td rowspan="3">65 </td> <td>SD198XOJGXBOX </td> <td>SD198XOJZ22GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon II X2 221 </th> <td>2012 </td> <td>2.8 </td> <td>AD221XOJGXBOX </td> <td>AD221XOJZ22GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="2">Athlon II X4 631 </th> <td>2012 </td> <td rowspan="6">4 (4) </td> <td rowspan="2">2.6 </td> <td rowspan="6">4×1 MB </td> <td rowspan="6">1866 </td> <td>AD631XOJGXBOX </td> <td>AD631XOJZ43GX </td></tr> <tr> <td>Aug 15, 2011 </td> <td>100 </td> <td>AD631XOJGXBOX </td> <td>AD631XWNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon II X4 638 </th> <td>Feb 8, 2012 </td> <td>2.7 </td> <td>65 </td> <td>AD638XOJGXBOX </td> <td>AD638XOJZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon II X4 641 </th> <td>Feb 8, 2012 </td> <td>2.8 </td> <td rowspan="3">100 </td> <td>AD641XWNGXBOX </td> <td>AD641XWNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon II X4 651 </th> <td>Nov 14, 2011 </td> <td rowspan="2">3.0 </td> <td>AD651XWNGXBOX </td> <td>AD651XWNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon II X4 651K </th> <td>2012 </td> <td>AD651KWNGXBOX </td> <td>AD651KWNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><style data-mw-deduplicate="TemplateStyles:r1238216509">.mw-parser-output .vanchor>:target~.vanchor-text{background-color:#b1d2ff}@media screen{html.skin-theme-clientpref-night .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}</style><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907124402/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=13">E2-3200</a> </th> <td>2011 </td> <td rowspan="4">2 (2) </td> <td>2.4 </td> <td rowspan="4">2×512 KB </td> <td>HD 6370D </td> <td rowspan="4">160:8:4 </td> <td rowspan="2">443 </td> <td rowspan="2">141.7 </td> <td rowspan="4">1600 </td> <td rowspan="7">65 </td> <td>ED3200OJGXBOX </td> <td>ED3200OJZ22GX ED3200OJZ22HX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122452/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=20">A4-3300</a> </th> <td>Sep 7, 2011 </td> <td>2.5 </td> <td rowspan="3">HD 6410D </td> <td>AD3300OJGXBOX AD3300OJHXBOX </td> <td>AD3300OJZ22GX AD3300OJZ22HX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122409/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=14">A4-3400</a> </th> <td>Sep 7, 2011 </td> <td>2.7 </td> <td rowspan="2">600 </td> <td rowspan="2">192 </td> <td>AD3400OJGXBOX AD3400OJHXBOX </td> <td>AD3400OJZ22GX AD3400OJZ22HX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A4-3420 </th> <td>Dec 20, 2011 </td> <td>2.8 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>AD3420OJZ22HX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907124555/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=19">A6-3500</a> </th> <td>Aug 17, 2011 </td> <td>3 (3) </td> <td rowspan="2">2.1 </td> <td rowspan="2">2.4 </td> <td>3×1 MB </td> <td rowspan="5">HD 6530D </td> <td rowspan="5">320:16:8 </td> <td rowspan="5">443 </td> <td rowspan="5">283.5 </td> <td rowspan="9">1866 </td> <td>AD3500OJGXBOX </td> <td>AD3500OJZ33GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907142851/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=15">A6-3600</a> </th> <td>Aug 17, 2011 </td> <td rowspan="8">4 (4) </td> <td rowspan="8">4×1 MB </td> <td>AD3600OJGXBOX </td> <td>AD3600OJZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907125445/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=33">A6-3620</a> </th> <td>Dec 20, 2011 </td> <td>2.2 </td> <td>2.5 </td> <td>AD3620OJGXBOX </td> <td>AD3620OJZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907124308/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=16">A6-3650</a> </th> <td>Jun 30, 2011 </td> <td>2.6 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">100 </td> <td>AD3650WNGXBOX </td> <td>AD3650WNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20121230193335/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=31">A6-3670K</a> </th> <td>Dec 20, 2011 </td> <td>2.7 </td> <td>AD3670WNGXBOX </td> <td>AD3670WNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907124946/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=17">A8-3800</a> </th> <td>Aug 17, 2011 </td> <td>2.4 </td> <td>2.7 </td> <td rowspan="4">HD 6550D </td> <td rowspan="4">400:20:8 </td> <td rowspan="4">600 </td> <td rowspan="4">480 </td> <td rowspan="2">65 </td> <td>AD3800OJGXBOX </td> <td>AD3800OJZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122837/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=32">A8-3820</a> </th> <td>Dec 20, 2011 </td> <td>2.5 </td> <td>2.8 </td> <td>AD3820OJGXBOX </td> <td>AD3820OJZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907124843/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=18">A8-3850</a> </th> <td>Jun 30, 2011 </td> <td>2.9 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">100 </td> <td>AD3850WNGXBOX </td> <td>AD3850WNZ43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20121230194834/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=30">A8-3870K</a> </th> <td>Dec 20, 2011 </td> <td>3.0 </td> <td>AD3870WNGXBOX </td> <td>AD3870WNZ43GX </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-43"><a href="#cite_ref-kib_43-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-44"><a href="#cite_ref-SFLOPS_44-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-fn_4-41"><a href="#cite_ref-fn_4_41-0">^</a> Models with "K" suffixes feature an unlocked multiplier and overclockable GPU. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Virgo:_"Trinity"_(2012)">Virgo: "Trinity" (2012)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=6" title="Edit section: Virgo: "Trinity" (2012)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on GlobalFoundries SOI process</li> <li>Socket <a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a></li> <li>CPU: <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a> <ul><li>L1 Cache: 16 KB Data per core and 64 KB Instructions per module</li></ul></li> <li>GPU <a href="/wiki/TeraScale_3" class="mw-redirect" title="TeraScale 3">TeraScale 3</a> (VLIW4)</li> <li>Die Size: 246 mm2, 1.303 Billion transistors<a href="#cite_note-45">[28]</a></li> <li>Support for up to four DIMMs of up to DDR3-1866 memory</li> <li>5 GT/s UMI</li> <li>GPU (based on VLIW4 architecture) instruction support: <a href="/wiki/DirectX" title="DirectX">DirectX</a> 11, <a href="/wiki/Opengl" class="mw-redirect" title="Opengl">Opengl</a> 4.2, <a href="/wiki/DirectCompute" title="DirectCompute">DirectCompute</a>, <a href="/wiki/Pixel_Shader" class="mw-redirect" title="Pixel Shader">Pixel Shader</a> 5.0, <a href="/wiki/Blu-ray_3D" class="mw-redirect" title="Blu-ray 3D">Blu-ray 3D</a>, <a href="/wiki/OpenCL" title="OpenCL">OpenCL</a> 1.2, <a href="/wiki/AMD_Stream" class="mw-redirect" title="AMD Stream">AMD Stream</a>, <a href="/wiki/UVD" class="mw-redirect" title="UVD">UVD</a>3</li> <li>Integrated <a href="/wiki/PCIE#PCI_Express_2.0" class="mw-redirect" title="PCIE">PCIe 2.0</a> controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>,<a href="#cite_note-auto-46">[29]</a> <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a></li> <li>Sempron and Athlon models exclude integrated graphics</li> <li>Select models support Hybrid Graphics technology to assist a Radeon HD 7350, 7450, 7470, 7550, 7570, 7670 discrete graphics card.<a href="#cite_note-47">[30]</a><a href="#cite_note-48">[31]</a> However, it has been found that this does not always improve 3D accelerated graphics performance.<a href="#cite_note-49">[32]</a><a href="#cite_note-50">[33]</a></li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number<a href="#cite_note-51">[34]</a> </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-52">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-53">[b]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Sempron X2 240<a href="#cite_note-amdsemproncpulist-54">[35]</a> </th> <td> </td> <td rowspan="17">32 nm </td> <td rowspan="17">TN-A1 </td> <td rowspan="2">[1]2 </td> <td>2.9 </td> <td>3.3 </td> <td rowspan="17">64 KB inst. per module 16 KB data per core </td> <td rowspan="2">1 MB </td> <td rowspan="5" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">1600 </td> <td rowspan="4">65 </td> <td> </td> <td>SD240XOKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X2 340<a href="#cite_note-AX2_340-55">[36]</a> </th> <td>Oct 2012 </td> <td>3.2 </td> <td>3.6 </td> <td> </td> <td>AD340XOKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X4 730 </th> <td>Oct 1, 2012 </td> <td rowspan="5">[2]4 </td> <td>2.8 </td> <td>3.2 </td> <td rowspan="5">2×2 MB </td> <td rowspan="5">1866 </td> <td> </td> <td>AD730XOKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/740/80">Athlon X4 740</a> </th> <td rowspan="2">Oct 2012 </td> <td>3.2 </td> <td>3.7 </td> <td>AD740XOKHJBOX </td> <td>AD740XOKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750K/81">Athlon X4 750K</a> </th> <td>3.4 </td> <td>4.0 </td> <td>100 </td> <td>AD750KWOHJBOX </td> <td>AD750KWOA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130728035554/http://products.amd.com/en-us/WorkstationAPUDetail.aspx?id=54&f1=&f2=&f3=&f4=4&f5=&f6=&">FirePro A300</a> </th> <td rowspan="2">Aug 7, 2012 </td> <td>3.4 </td> <td>4.0 </td> <td rowspan="2">FirePro </td> <td rowspan="2">384:24:8 6 CU </td> <td>760 </td> <td>583.6 </td> <td>65 </td> <td> </td> <td>AWA300OKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130728035549/http://products.amd.com/pages/workstationapudetail.aspx?id=53&f1=&f2=&f3=&f4=4&f5=&f6=&&AspxAutoDetectCookieSupport=1">FirePro A320</a> </th> <td>3.8 </td> <td>4.2 </td> <td>800 </td> <td>614.4 </td> <td>100 </td> <td> </td> <td>AWA320WOA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619200306/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=49">A4-5300</a> </th> <td>Oct 1, 2012 </td> <td rowspan="4">[1]2 </td> <td rowspan="2">3.4 </td> <td rowspan="2">3.6 </td> <td rowspan="4">1 MB </td> <td rowspan="2">HD 7480D </td> <td rowspan="2">128:8:4 2 CU </td> <td rowspan="2">723 </td> <td rowspan="2">185 </td> <td rowspan="2">1600 </td> <td rowspan="6">65 </td> <td>AD5300OKHJBOX </td> <td>AD5300OKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619201302/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=60">A4-5300B</a> </th> <td>Oct 2012 </td> <td> </td> <td>AD530BOKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619215923/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=48">A6-5400K</a> </th> <td>Oct 1, 2012 </td> <td rowspan="2">3.6 </td> <td rowspan="2">3.8 </td> <td rowspan="2">HD 7540D </td> <td rowspan="2">192:12:4 3 CU </td> <td rowspan="2">760 </td> <td rowspan="2">291.8 </td> <td rowspan="8">1866 </td> <td>AD540KOKHJBOX </td> <td>AD540KOKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619201551/http://products.amd.com/en-us/DesktopAPUDetail.aspx?detailId=59">A6-5400B</a> </th> <td>Oct 2012 </td> <td> </td> <td>AD540BOKA23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619200311/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=47">A8-5500</a> </th> <td>Oct 1, 2012 </td> <td rowspan="6">[2]4 </td> <td rowspan="2">3.2 </td> <td rowspan="2">3.7 </td> <td rowspan="6">2×2 MB </td> <td rowspan="3">HD 7560D </td> <td rowspan="3">256:16:8 4 CU </td> <td rowspan="3">760 </td> <td rowspan="3">389.1 </td> <td>AD5500OKHJBOX </td> <td>AD5500OKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619201548/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=58">A8-5500B</a> </th> <td>Oct 2012 </td> <td> </td> <td>AD550BOKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619215737/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=46">A8-5600K</a> </th> <td rowspan="3">Oct 1, 2012 </td> <td>3.6 </td> <td>3.9 </td> <td>100 </td> <td>AD560KWOHJBOX </td> <td>AD560KWOA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619202309/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=45">A10-5700</a> </th> <td>3.4 </td> <td>4.0 </td> <td rowspan="3">HD 7660D </td> <td rowspan="3">384:24:8 6 CU </td> <td>760 </td> <td>583.6 </td> <td>65 </td> <td>AD5700OKHJBOX </td> <td>AD5700OKA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619202621/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=44">A10-5800K</a> </th> <td rowspan="2">3.8 </td> <td rowspan="2">4.2 </td> <td rowspan="2">800 </td> <td rowspan="2">614.4 </td> <td rowspan="2">100 </td> <td>AD580KWOHJBOX </td> <td>AD580KWOA44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619201449/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=57">A10-5800B</a> </th> <td>Oct 2012 </td> <td> </td> <td>AD580BWOA44HJ </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-52"><a href="#cite_ref-kib_52-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-53"><a href="#cite_ref-SFLOPS_53-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Richland"_(2013)">"Richland" (2013)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=7" title="Edit section: "Richland" (2013)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on GlobalFoundries SOI process</li> <li>Socket <a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a></li> <li>Two or four CPU cores based on the <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a> microarchitecture <ul><li>Die Size: 246 mm2, 1.303 Billion transistors<a href="#cite_note-56">[37]</a></li> <li>L1 Cache: 16 KB Data per core and 64 KB Instructions per module</li> <li>MMX, SSE, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, SSSE3, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, SSE4.1, SSE4.2, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, AVX1.1, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, Turbo Core 3.0, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/PowerNow!" title="PowerNow!">PowerNow!</a></li></ul></li> <li>GPU <ul><li><a href="/wiki/TeraScale_3" class="mw-redirect" title="TeraScale 3">TeraScale 3</a> architecture</li> <li>HD Media Accelerator, <a href="/wiki/AMD_Hybrid_Graphics" title="AMD Hybrid Graphics">AMD Hybrid Graphics</a></li></ul></li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-57">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-58">[b]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Sempron X2 250<a href="#cite_note-amdsemproncpulist-54">[35]</a> </th> <td> </td> <td rowspan="28">32 nm </td> <td rowspan="28">RL-A1 </td> <td rowspan="3">[1]2 </td> <td>3.2 </td> <td>3.6 </td> <td rowspan="28">64 KB inst. per module 16 KB data per core </td> <td rowspan="3">1 MB </td> <td rowspan="6" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td> </td> <td rowspan="4">65 </td> <td> </td> <td>SD250XOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X2 350<a href="#cite_note-amdcpulist-59">[38]</a> </th> <td> </td> <td>3.5 </td> <td>3.9 </td> <td rowspan="5">1866 </td> <td> </td> <td>AD350XOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X2 370K </th> <td>Jun 2013 </td> <td>4.0 </td> <td>4.2 </td> <td>AD370KOKHLBOX </td> <td>AD370KOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750/143">Athlon X4 750</a> </th> <td>Oct 2013 </td> <td rowspan="3">[2]4 </td> <td>3.4 </td> <td>4.0 </td> <td rowspan="3">2×2 MB </td> <td> </td> <td>AD750XOKA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/760K/83">Athlon X4 760K</a> </th> <td>Jun 2013 </td> <td>3.8 </td> <td>4.1 </td> <td>100 </td> <td>AD760KWOHLBOX </td> <td>AD760KWOA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">FX-670K<a href="#cite_note-60">[39]</a> </th> <td>Mar 2014 (OEM) </td> <td>3.7 </td> <td>4.3 </td> <td rowspan="13">65 </td> <td> </td> <td>FD670KOKA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20130619180848/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=84">A4-4000</a> </th> <td>May 2013 </td> <td rowspan="12">[1]2 </td> <td>3.0 </td> <td>3.2 </td> <td rowspan="12">1 MB </td> <td rowspan="2">HD 7480D </td> <td rowspan="6">128:8:4 2 CU </td> <td rowspan="2">720 </td> <td rowspan="2">184.3 </td> <td rowspan="2">1333 </td> <td>AD4000OKHLBOX </td> <td>AD4000OKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619203039/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=104">A4-4020</a> </th> <td>Jan 2014 </td> <td>3.2 </td> <td>3.4 </td> <td>AD4020OKHLBOX </td> <td>AD4020OKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A4-6300 </th> <td rowspan="2">Jul 2013 </td> <td rowspan="2">3.7 </td> <td rowspan="2">3.9 </td> <td rowspan="4">HD 8370D </td> <td rowspan="4">760 </td> <td rowspan="4">194.5 </td> <td rowspan="6">1600 </td> <td>AD6300OKHLBOX </td> <td>AD6300OKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150619215735/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=95">A4-6300B</a> </th> <td> </td> <td>AD630BOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Desktops/A4-6320-with-Radeon%E2%84%A2-HD-8370D/28">A4-6320</a> </th> <td>Dec 2013 </td> <td rowspan="4">3.8 </td> <td rowspan="4">4.0 </td> <td>AD6320OKHLBOX </td> <td>AD6320OKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141129185732/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=138">A4-6320B</a> </th> <td>Mar 2014 </td> <td> </td> <td>AD632BOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Desktops/A4-7300-with-Radeon%E2%84%A2-HD-8470D/30">A4-7300</a> </th> <td rowspan="2">Aug 2014 </td> <td rowspan="6">HD 8470D </td> <td rowspan="6">192:12:4 3 CU </td> <td rowspan="6">800 </td> <td rowspan="6">307.2 </td> <td> </td> <td>AD7300OKA23HL </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20141129185558/http://products.amd.com/en-us/DesktopAPUDetail.aspx?id=136">A4 Pro-7300B</a> </td> <td> </td> <td>AD730BOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Dual-Core-A6-Series-APU-for-Desktops/A6-6400B-with-Radeon%E2%84%A2-HD-8470D/72">A6-6400B</a> </th> <td rowspan="2">Jun 4, 2013 </td> <td rowspan="2">3.9 </td> <td rowspan="2">4.1 </td> <td rowspan="12">1866 </td> <td> </td> <td>AD640BOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-6400K-with-Radeon%E2%84%A2-HD-8470D/44">A6-6400K</a> </th> <td>AD640KOKHLBOX </td> <td>AD640KOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Dual-Core-A6-Series-APU-for-Desktops/A6-6420B-with-Radeon%E2%84%A2-HD-8470D/73">A6-6420B</a> </th> <td rowspan="2">Jan 2014 </td> <td rowspan="2">4.0 </td> <td rowspan="2">4.2 </td> <td> </td> <td>AD642BOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-6420K-with-Radeon%E2%84%A2-HD-8470D/45">A6-6420K</a> </th> <td>AD642KOKHLBOX </td> <td>AD642KOKA23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6500T-with-Radeon%E2%84%A2-HD-8550D/60">A8-6500T</a> </th> <td>Sep 18, 2013 </td> <td rowspan="10">[2]4 </td> <td>2.1 </td> <td>3.1 </td> <td rowspan="10">2×2 MB </td> <td>HD 8550D </td> <td rowspan="4">256:16:8 4 CU </td> <td>720 </td> <td>368.6 </td> <td>45 </td> <td>AD650TYHHLBOX </td> <td>AD650TYHA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6500-with-Radeon%E2%84%A2-HD-8570D/59">A8-6500</a> </th> <td rowspan="3">Jun 4, 2013 </td> <td rowspan="2">3.5 </td> <td rowspan="2">4.1 </td> <td rowspan="3">HD 8570D </td> <td rowspan="2">800 </td> <td rowspan="2">409.6 </td> <td rowspan="2">65 </td> <td>AD6500OKHLBOX </td> <td>AD6500OKA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-Business-Class---Quad-Core-A8-Series-APU-for-Desktops/A8-6500B-with-Radeon%E2%84%A2-HD-8570D/75">A8-6500B</a> </th> <td> </td> <td>AD650BOKA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-6600K-with-Radeon%E2%84%A2-HD-8570D/61">A8-6600K</a> </th> <td>3.9 </td> <td>4.2 </td> <td>844 </td> <td>432.1 </td> <td>100 </td> <td>AD660KWOHLBOX </td> <td>AD660KWOA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6700T-with-Radeon%E2%84%A2-HD-8650D/5">A10-6700T</a> </th> <td>Sep 18, 2013 </td> <td>2.5 </td> <td>3.5 </td> <td>HD 8650D </td> <td rowspan="6">384:24:8 6 CU </td> <td>720 </td> <td>552.9 </td> <td>45 </td> <td>AD670TYHHLBOX </td> <td>AD670TYHA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6700-with-Radeon%E2%84%A2-HD-8670D/4">A10-6700</a> </th> <td>Jun 4, 2013 </td> <td>3.7 </td> <td rowspan="3">4.3 </td> <td rowspan="5">HD 8670D </td> <td rowspan="5">844 </td> <td rowspan="5">648.1 </td> <td>65 </td> <td>AD6700OKHLBOX </td> <td>AD6700OKA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A-Series-A10-APU-for-Desktops/A10-6790B-with-Radeon%E2%84%A2-HD-8670D/110">A10-6790B</a> </th> <td>Oct 29, 2013 </td> <td rowspan="2">4.0 </td> <td rowspan="4">100 </td> <td>AD679KWOHLBOX </td> <td>AD679KWOA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6790K-with-Radeon%E2%84%A2-HD-8670D/6">A10-6790K</a> </th> <td>Oct 28, 2013 </td> <td> </td> <td>AD679BWOA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Desktops/A10-6800K-with-Radeon%E2%84%A2-HD-8670D/7">A10-6800K</a> </th> <td rowspan="2">Jun 4, 2013 </td> <td rowspan="2">4.1 </td> <td rowspan="2">4.4 </td> <td rowspan="2">2133 </td> <td>AD680KWOHLBOX </td> <td>AD680KWOA44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A-Series-A10-APU-for-Desktops/A10-6800B-with-Radeon%E2%84%A2-HD-8670D/109">A10-6800B</a> </th> <td> </td> <td>AD680BWOA44HL </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-57"><a href="#cite_ref-kib_57-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-58"><a href="#cite_ref-SFLOPS_58-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Kabini"_(2013,_SoC)">"Kabini" (2013, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=8" title="Edit section: "Kabini" (2013, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li><a href="/wiki/Socket_AM1" title="Socket AM1">Socket AM1</a>, aka Socket FS1b (AM1 platform)</li> <li>2 to 4 CPU Cores (<a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar (microarchitecture)</a>)</li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">Gb</a>/s) controllers</li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN)</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-61">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-62">[b]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20530%20-%20AD530XJAH44HM.html">Athlon X4 530</a> </th> <td rowspan="2"> </td> <td rowspan="7">28 nm </td> <td rowspan="7">KB-A1 </td> <td rowspan="2">4 (4) </td> <td>2.00 </td> <td rowspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="7">32 KB inst. 32 KB data per core </td> <td rowspan="2">2 MB </td> <td rowspan="2" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">1600 single-channel </td> <td rowspan="7">25 </td> <td> </td> <td>AD530XJAH44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20550%20-%20AD550XJAH44HM.html">Athlon X4 550</a> </th> <td>2.20 </td> <td> </td> <td>AD550XJAH44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-Sempron%E2%84%A2-APUs/AMD-Sempron%E2%84%A2-Dual-Core-APU/Sempron%E2%84%A2-2650-APU-with-Radeon%E2%84%A2-R3-Series/119">Sempron 2650</a> </th> <td rowspan="4">Apr 9, 2014 </td> <td>2 (2) </td> <td>1.45 </td> <td>1 MB </td> <td>R3 (HD 8240) </td> <td rowspan="5">128:8:4 2 CU </td> <td>400 </td> <td>102.4 </td> <td>1333 single-channel </td> <td>SD2650JAHMBOX </td> <td>SD2650JAH23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-Sempron%E2%84%A2-APUs/AMD-Sempron%E2%84%A2-Quad-Core-APU/Sempron%E2%84%A2-3850-APU-with-Radeon%E2%84%A2-R3-Series/120">Sempron 3850</a> </th> <td rowspan="4">4 (4) </td> <td>1.30 </td> <td rowspan="4">2 MB </td> <td>R3 (HD 8280) </td> <td>450 </td> <td>115.2 </td> <td rowspan="4">1600 single-channel </td> <td>SD3850JAHMBOX </td> <td>SD3850JAH44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5150-APU-with-Radeon%E2%84%A2-R3-Series/76">Athlon 5150</a> </th> <td>1.60 </td> <td rowspan="3">R3 (HD 8400) </td> <td rowspan="3">600 </td> <td rowspan="3">153.6 </td> <td>AD5150JAHMBOX </td> <td>AD5150JAH44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5350-APU-with-Radeon%E2%84%A2-R3-Series/77">Athlon 5350</a> </th> <td>2.05 </td> <td>AD5350JAHMBOX </td> <td>AD5350JAH44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5370-APU-with-Radeon%E2%84%A2-R3-Series/182">Athlon 5370</a> </th> <td>Feb 2016 </td> <td>2.20 </td> <td> </td> <td>AD5370JAH44HM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-61"><a href="#cite_ref-kib_61-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-62"><a href="#cite_ref-SFLOPS_62-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Kaveri"_(2014)_&_"Godavari"_(2015)">"Kaveri" (2014) & "Godavari" (2015)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=9" title="Edit section: "Kaveri" (2014) & "Godavari" (2015)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a>.</li> <li><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">Socket FM2+</a>,<a href="#cite_note-63">[40]</a> support for <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a>.</li> <li>Two or four CPU cores based on the <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a> microarchitecture. <ul><li>Kaveri refresh models have codename Godavari.<a href="#cite_note-64">[41]</a></li></ul></li> <li>Die Size: 245 mm2, 2.41 Billion transistors.<a href="#cite_note-65">[42]</a></li> <li>L1 Cache: 16 KB Data per core and 96 KB Instructions per module.</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Three to eight Compute Units (CUs) based on <a href="/wiki/Graphics_Core_Next_2" class="mw-redirect" title="Graphics Core Next 2">GCN 2nd gen</a> microarchitecture;<a href="#cite_note-wccftech-66">[43]</a> 1 Compute Unit (CU) consists of 64 <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shader Processors</a> : 4 <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> (TMUs) : 1 <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Unit</a> (ROPs).</li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous System Architecture</a>-enabled <a href="/wiki/Zero-copy" title="Zero-copy">zero-copy</a> through <a href="/wiki/Pointer_(computer_programming)" title="Pointer (computer programming)">pointer</a> passing.</li> <li><a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">SIP blocks</a>: <a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder</a>, <a href="/wiki/Video_Coding_Engine" title="Video Coding Engine">Video Coding Engine</a>, <a href="/wiki/AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a>.<a href="#cite_note-SemiAccurate-67">[44]</a></li> <li>Dual-channel (2× 64 Bit) <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> memory controller.</li> <li>Integrated custom <a href="/wiki/ARM_Cortex-A5" title="ARM Cortex-A5">ARM Cortex-A5</a> co-processor<a href="#cite_note-arstechnica.com-68">[45]</a> with <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> Security Extensions<a href="#cite_note-technewspedia.com-69">[46]</a> in select APU models, except the Performance APU models.<a href="#cite_note-ps-philgeps.gov.ph_carrizo-70">[47]</a></li> <li>Select models support Hybrid Graphics technology by using a Radeon R7 240 or R7 250 discrete graphics card.<a href="#cite_note-71">[48]</a></li> <li><a href="/wiki/Display_controller" class="mw-redirect" title="Display controller">Display controller</a>: <a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">AMD Eyefinity</a> 2, 4K Ultra HD support, DisplayPort 1.2 Support.<a href="#cite_note-72">[49]</a></li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-73">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-74">[b]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X2 450<a href="#cite_note-amdcpulist-59">[38]</a> </th> <td>Jul 31, 2014 </td> <td rowspan="30">28 nm </td> <td rowspan="3">KV-A1 </td> <td>[1]2 </td> <td>3.5 </td> <td>3.9 </td> <td rowspan="30">96 KB inst. per module 16 KB data per core </td> <td>1 MB </td> <td rowspan="8" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1866 </td> <td rowspan="4">65 </td> <td> </td> <td>AD450XYBI23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Bulldozer/AMD-Athlon%20X4%20830%20-%20AD830XYBI44JA.html">Athlon X4 830</a> </th> <td>2018 </td> <td rowspan="7">[2]4 </td> <td>3.0 </td> <td>3.4 </td> <td rowspan="7">2×2 MB </td> <td rowspan="7">2133 </td> <td> </td> <td>AD830XYBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X4 840<a href="#cite_note-amdcpulist-59">[38]</a> </th> <td>Aug 2014 </td> <td>3.1 </td> <td>3.8 </td> <td>AD840XYBJABOX </td> <td>AD840XYBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/850.html">Athlon X4 850</a> </th> <td>2015 </td> <td>GV-A1 </td> <td>3.2 </td> <td> </td> <td> </td> <td>AD835XACI43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/860K-with-New-Thermal-Solution/133">Athlon X4 860K</a> </th> <td>Aug 2014 </td> <td>KV-A1 </td> <td>3.7 </td> <td>4.0 </td> <td rowspan="3">95 </td> <td>AD860KXBJABOX AD860KWOHLBOX AD860KXBJASBX </td> <td>AD860KXBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/870K-with-New-Thermal-Solution/132">Athlon X4 870K</a> </th> <td>Dec 2015 </td> <td rowspan="2">GV-A1 </td> <td>3.9 </td> <td>4.1 </td> <td>AD870KXBJCSBX </td> <td>AD870KXBI44JC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/880K-with-Near-Silent-Thermal-Solution/138">Athlon X4 880K</a> </th> <td>Mar 1, 2016 </td> <td>4.0 </td> <td>4.2 </td> <td>AD880KXBJCSBX </td> <td> </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">FX-770K<a href="#cite_note-75">[50]</a> </th> <td>Dec 2014 </td> <td rowspan="5">KV-A1 </td> <td>3.5 </td> <td>3.9 </td> <td rowspan="10">65 </td> <td> </td> <td>FD770KYBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-ca/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Desktops/A4-PRO-7350B-with-Radeon%E2%84%A2-R5-Graphics/114">A4 Pro-7350B</a> </th> <td>Jul 31, 2014 </td> <td rowspan="6">[1]2 </td> <td>3.4 </td> <td>3.8 </td> <td rowspan="6">1 MB </td> <td rowspan="6">R5 </td> <td>192:12:8 3 CU </td> <td>514 </td> <td>197.3 </td> <td rowspan="4">1866 </td> <td> </td> <td>AD735BYBI23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://products.amd.com/en-ca/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Desktops/6th-Gen-AMD-PRO-A4-8350B-APU/160">Pro A4-8350B</a> </th> <td>Sep 29, 2015 </td> <td>3.5 </td> <td>3.9 </td> <td rowspan="5">256:16:8 4 CU </td> <td>757 </td> <td>387.5 </td> <td> </td> <td>AD835BYBI23JC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-7400K-with-Radeon%E2%84%A2-R5-Series/46">A6-7400K</a> </th> <td rowspan="2">Jul 31, 2014 </td> <td rowspan="2">3.5 </td> <td rowspan="2">3.9 </td> <td rowspan="2">756 </td> <td rowspan="2">387 </td> <td>AD740KYBJABOX </td> <td>AD740KYBI23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Desktops/A6-PRO-7400B-with-Radeon%E2%84%A2-R5-Graphics/115">A6 Pro-7400B</a> </th> <td> </td> <td>AD740BYBI23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-7470K-with-Radeon%E2%84%A2-R5-Series/181">A6-7470K</a> </th> <td>Feb 2, 2016 </td> <td rowspan="2">GV-A1 </td> <td rowspan="2">3.7 </td> <td rowspan="2">4.0 </td> <td rowspan="2">800 </td> <td rowspan="2">409.6 </td> <td rowspan="18">2133 </td> <td>AD747KYBJCBOX </td> <td>AD747KYBI23JC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://products.amd.com/de-de/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Desktops/6th-Gen-AMD-PRO-A6-8550B-APU/159">Pro A6-8550B</a> </th> <td>Sep 29, 2015 </td> <td> </td> <td>AD855BYBI23JC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A8-7500<a href="#cite_note-76">[51]</a><a href="#cite_note-77">[52]</a> </th> <td>2014 </td> <td rowspan="4">KV-A1 </td> <td rowspan="16">[2]4 </td> <td>3.0 </td> <td>3.7 </td> <td rowspan="16">2×2 MB </td> <td rowspan="16">R7 </td> <td rowspan="7">384:24:8 6 CU </td> <td rowspan="4">720 </td> <td rowspan="4">552.9 </td> <td> </td> <td>AD7500YBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Desktops/A8-7600-with-Radeon%E2%84%A2-R7-Series/62">A8-7600</a> </th> <td rowspan="2">Jul 31, 2014 </td> <td rowspan="2">3.1 </td> <td rowspan="3">3.8 </td> <td>AD7600YBJABOX </td> <td>AD7600YBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Desktops/A8-PRO-7600B-with-Radeon%E2%84%A2-R7-Graphics/117">A8 Pro-7600B</a> </th> <td> </td> <td>AD760BYBI44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" 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class="external text" href="https://products.amd.com/en-gb/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Desktops/6th-Gen-AMD-PRO-A10-8850B-APU/156">Pro A10-8850B</a> </th> <td>3.9 </td> <td>4.1 </td> <td>800 </td> <td>819.2 </td> <td>95 </td> <td> </td> <td>AD885BXBI44JC </td></tr> <tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th rowspan="2">[Modules/FPUs] Cores/threads </th> <th>Base </th> <th>Boost </th> <th>L1 </th> <th>L2 </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (GFLOPS)<a href="#cite_note-SFLOPS-74">[b]</a> </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number </th> <th rowspan="3">Part number </th></tr> <tr> <th colspan="2">Clock rate (GHz) </th> <th colspan="2">Cache<a href="#cite_note-kib-73">[a]</a> </th></tr> <tr> <th colspan="5">CPU </th> <th colspan="4">GPU </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-73">^ <a href="#cite_ref-kib_73-0">a</a> <a href="#cite_ref-kib_73-1">b</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-74">^ <a href="#cite_ref-SFLOPS_74-0">a</a> <a href="#cite_ref-SFLOPS_74-1">b</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Carrizo"_(2016)">"Carrizo" (2016)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=10" title="Edit section: "Carrizo" (2016)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a>: 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket <a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a> or <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a>, support for <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a></li> <li>Two or four CPU cores based on the <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> microarchitecture</li> <li>Die size: 250.04 mm2, 3.1 billion transistors<a href="#cite_note-78">[53]</a></li> <li>L1 cache: 32 KB data per core and 96 KB instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Single- or dual-channel DDR3 or <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li>Third generation <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">GCN</a>-based GPU (<a href="/wiki/Radeon_300_series" title="Radeon 300 series">Radeon M300</a>)</li> <li>Integrated custom <a href="/wiki/ARM_Cortex-A5" title="ARM Cortex-A5">ARM Cortex-A5</a> coprocessor<a href="#cite_note-arstechnica.com-68">[45]</a> with <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security extensions<a href="#cite_note-technewspedia.com-69">[46]</a><a href="#cite_note-ps-philgeps.gov.ph_carrizo-70">[47]</a></li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th rowspan="3">Socket </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number<a href="#cite_note-box-79">[a]</a> </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-80">[b]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-81">[c]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/835.html">Athlon X4 835</a> </th> <td> </td> <td rowspan="10">28 nm </td> <td rowspan="10">CZ-A1 </td> <td rowspan="4">FM2+ </td> <td rowspan="2">[2]4 </td> <td>3.1 </td> <td> </td> <td rowspan="10">96 KB inst. per module 32 KB data per core </td> <td rowspan="2">2×1 MB </td> <td rowspan="2" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">DDR3-2133 </td> <td rowspan="4">65 </td> <td> </td> <td>AD835XACI43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/cpu/845-near-silent-thermal-solution">Athlon X4 845</a> </th> <td>Feb 2, 2016 </td> <td rowspan="3">3.5 </td> <td rowspan="3">3.8 </td> <td>AD845XYBJCSBX AD845XACKASBX </td> <td>AD845XACI43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A6-7480<a href="#cite_note-82">[54]</a> </th> <td rowspan="2">Oct 2018 </td> <td>[1]2 </td> <td>1 MB </td> <td>R5 </td> <td rowspan="2">384:24:8 6 CU </td> <td rowspan="2">900 </td> <td rowspan="2">691.2 </td> <td>AD7480ACABBOX </td> <td>AD7480ACI23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A8-7680<a href="#cite_note-83">[55]</a> </th> <td>[2]4 </td> <td>2×1 MB </td> <td>R7 </td> <td>AD7680ACABBOX </td> <td>AD7680ACI43AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6156">Pro A6-8570E</a> </th> <td rowspan="6">Oct 2016 </td> <td rowspan="6">AM4 </td> <td rowspan="2">[1]2 </td> <td>3.0 </td> <td>3.4 </td> <td rowspan="2">1 MB </td> <td rowspan="2">R5 </td> <td>256:16:4 4 CU </td> <td>800 </td> <td>409.6 </td> <td rowspan="6">DDR4-2400 </td> <td>35 </td> <td> </td> <td>AD857BAHM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6151">Pro A6-8570</a> </th> <td>3.5 </td> <td>3.8 </td> <td rowspan="3">384:24:6 6 CU </td> <td>1029 </td> <td>790.2 </td> <td>65 </td> <td> </td> <td>AD857BAGM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6241">Pro A10-8770E</a> </th> <td rowspan="4">[2]4 </td> <td>2.8 </td> <td>3.5 </td> <td rowspan="4">2×1 MB </td> <td rowspan="4">R7 </td> <td>847 </td> <td>650.4 </td> <td>35 </td> <td> </td> <td>AD877BAHM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6236">Pro A10-8770</a> </th> <td>3.5 </td> <td rowspan="2">3.8 </td> <td>1029 </td> <td>790.2 </td> <td>65 </td> <td> </td> <td>AD877BAGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6146">Pro A12-8870E</a> </th> <td>2.9 </td> <td rowspan="2">512:32:8 8 CU </td> <td>900 </td> <td>921.6 </td> <td>35 </td> <td> </td> <td>AD887BAHM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6231">Pro A12-8870</a> </th> <td>3.7 </td> <td>4.2 </td> <td>1108 </td> <td>1134.5 </td> <td>65 </td> <td> </td> <td>AD887BAUM44AB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-box-79"><a href="#cite_ref-box_79-0">^</a> With cooler if available. </li> <li id="cite_note-kib-80"><a href="#cite_ref-kib_80-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-81"><a href="#cite_ref-SFLOPS_81-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Bristol_Ridge"_(2016)">"Bristol Ridge" (2016)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=11" title="Edit section: "Bristol Ridge" (2016)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a>, support for <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">PCIe 3.0</a></li> <li>Two or four "<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>" CPU cores</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)</li> <li><a href="/wiki/PCI_Express" title="PCI Express">PCI Express</a> 3.0 x4 as link to optional external chipset</li> <li>4x <a href="/wiki/USB_3.1" class="mw-redirect" title="USB 3.1">USB 3.1</a> Gen 1</li> <li>Storage: 2x <a href="/wiki/SATA" title="SATA">SATA</a> and 2x <a href="/wiki/NVMe" class="mw-redirect" title="NVMe">NVMe</a> or 2x PCI Express</li> <li>Third Generation <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">GCN</a> based GPU<a href="#cite_note-84">[56]</a> with hybrid <a href="/wiki/VP9" title="VP9">VP9</a> decoding</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR4 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Box number<a href="#cite_note-box-85">[a]</a> </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-86">[b]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-87">[c]</a> </th></tr> <tr> <th>Base </th> <th>Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X4 940<a href="#cite_note-88">[57]</a> </th> <td rowspan="3">Jul 27, 2017 </td> <td rowspan="19">28 nm </td> <td rowspan="19">BR-A1 </td> <td rowspan="3">[2]4 </td> <td>3.2 </td> <td>3.6 </td> <td rowspan="19">96 KB inst. per module 32 KB data per core </td> <td rowspan="3">2×1 MB </td> <td rowspan="3" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="19">2400 </td> <td rowspan="4">65 </td> <td>AD940XAGABBOX </td> <td>AD940XAGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X4 950<a href="#cite_note-89">[58]</a> </th> <td>3.5 </td> <td>3.8 </td> <td>AD950XAGABBOX </td> <td>AD950XAGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Athlon X4 970<a href="#cite_note-90">[59]</a> </th> <td>3.8 </td> <td>4.0 </td> <td>AD970XAUABBOX </td> <td>AD970XAUM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A6-9400<a href="#cite_note-91">[60]</a> </th> <td>Mar 16, 2019 </td> <td rowspan="6">[1]2 </td> <td>3.4 </td> <td>3.7 </td> <td rowspan="6">1 MB </td> <td rowspan="6">R5 </td> <td>192:12:4 3 CU </td> <td>720 </td> <td>276.4 </td> <td>AD9400AGABBOX </td> <td>AD9400AGM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A6-9500E<a href="#cite_note-92">[61]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.0 </td> <td rowspan="2">3.4 </td> <td rowspan="2">256:16:4 4 CU </td> <td rowspan="2">800 </td> <td rowspan="2">409.6 </td> <td rowspan="2">35 </td> <td>AD9500AHABBOX </td> <td>AD9500AHM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A6-9500E<a href="#cite_note-93">[62]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD950BAHM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A6-9500<a href="#cite_note-94">[63]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.5 </td> <td rowspan="2">3.8 </td> <td rowspan="2">384:24:6 6 CU </td> <td rowspan="2">1029 </td> <td rowspan="2">790.2 </td> <td rowspan="5">65 </td> <td>AD9500AGABBOX </td> <td>AD9500AGM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A6-9500<a href="#cite_note-95">[64]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD950BAGM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A6-9550<a href="#cite_note-96">[65]</a> </th> <td>Jul 27, 2017 </td> <td>3.8 </td> <td>4.0 </td> <td>256:16:4 4 CU </td> <td>800 </td> <td>409.6 </td> <td>AD9550AGABBOX </td> <td>AD9550AGM23AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A8-9600<a href="#cite_note-97">[66]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="10">[2]4 </td> <td rowspan="2">3.1 </td> <td rowspan="2">3.4 </td> <td rowspan="10">2×1 MB </td> <td rowspan="10">R7 </td> <td rowspan="6">384:24:6 6 CU </td> <td rowspan="2">900 </td> <td rowspan="2">691.2 </td> <td>AD9600AGABBOX </td> <td>AD9600AGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A8-9600<a href="#cite_note-98">[67]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD960BAGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A10-9700E<a href="#cite_note-99">[68]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.0 </td> <td rowspan="2">3.5 </td> <td rowspan="2">847 </td> <td rowspan="2">650.4 </td> <td rowspan="2">35 </td> <td>AD9700AHABBOX </td> <td>AD9700AHM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A10-9700E<a href="#cite_note-100">[69]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD970BAHM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A10-9700<a href="#cite_note-101">[70]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.5 </td> <td rowspan="2">3.8 </td> <td rowspan="2">1029 </td> <td rowspan="2">790.2 </td> <td rowspan="2">65 </td> <td>AD9700AGABBOX </td> <td>AD9700AGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A10-9700<a href="#cite_note-102">[71]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD970BAGM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A12-9800E<a href="#cite_note-103">[72]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.1 </td> <td rowspan="2">3.8 </td> <td rowspan="4">512:32:8<a href="#cite_note-104">[73]</a> 8 CU </td> <td rowspan="2">900 </td> <td rowspan="2">921.6 </td> <td rowspan="2">35 </td> <td>AD9800AHABBOX </td> <td>AD9800AUM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A12-9800E<a href="#cite_note-105">[74]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD980BAHM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A12-9800<a href="#cite_note-106">[75]</a> </th> <td>Sep 5, 2016 </td> <td rowspan="2">3.8 </td> <td rowspan="2">4.2 </td> <td rowspan="2">1108 </td> <td rowspan="2">1134.5 </td> <td rowspan="2">65 </td> <td>AD9800AUABBOX </td> <td>AD9800AUM44AB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Pro A12-9800<a href="#cite_note-107">[76]</a> </th> <td>Oct 3, 2016 </td> <td> </td> <td>AD980BAUM44AB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-box-85"><a href="#cite_ref-box_85-0">^</a> With cooler if available. </li> <li id="cite_note-kib-86"><a href="#cite_ref-kib_86-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-87"><a href="#cite_ref-SFLOPS_87-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Raven_Ridge"_(2018)">"Raven Ridge" (2018)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=12" title="Edit section: "Raven Ridge" (2018)">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li><a href="/wiki/Transistor" title="Transistor">Transistors</a>: 4.94 billion</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 210 mm²</li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a></li> <li><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> CPU cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li>Fifth generation <a href="/wiki/Graphics_Core_Next#GCN_5th_Generation_(Vega)" title="Graphics Core Next">GCN</a> based GPU</li> <li><a href="/wiki/Unified_Video_Decoder#VCN_1" title="Unified Video Decoder">Video Core Next</a> (VCN) 1.0</li></ul> Common features of <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> based Raven Ridge desktop APUs: <ul><li>Socket: <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a>.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-2666 (DDR4-2933 Ryzen) in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a> <a href="/wiki/14_nm_process" title="14 nm process">14LP</a>.</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/List_price" title="List price">Release price</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-108">[i]</a> </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-109">[ii]</a> </th></tr> <tr> <th><style data-mw-deduplicate="TemplateStyles:r1038841319">.mw-parser-output .tooltip-dotted{border-bottom:1px dotted;cursor:help}</style>Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8206">Athlon 200GE</a> </th> <td rowspan="10">2 (4) </td> <td rowspan="2">3.2 </td> <td rowspan="10" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="18">4 MB </td> <td rowspan="10">Vega 3 </td> <td rowspan="10">192:12:4 3 CU </td> <td rowspan="4">1000 </td> <td rowspan="4">384 </td> <td rowspan="12">35 W </td> <td rowspan="2">Sep 6, 2018 </td> <td>US $55<a href="#cite_note-110">[77]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8211">Athlon Pro 200GE</a> </th> <td>OEM </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8326">Athlon 220GE</a> </th> <td>3.4 </td> <td rowspan="2">Dec 21, 2018 </td> <td>US $65<a href="#cite_note-AnandTech220G-111">[78]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8331">Athlon 240GE</a> </th> <td>3.5 </td> <td>US $75<a href="#cite_note-AnandTech220G-111">[78]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8986">Athlon 300GE</a> </th> <td rowspan="2">3.4 </td> <td rowspan="5">1100 </td> <td rowspan="5">424.4 </td> <td>Jul 7, 2019 </td> <td rowspan="3">OEM </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8896">Athlon Pro 300GE</a> </th> <td>Sep 30, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10136">Athlon 320GE</a> </th> <td rowspan="2">3.5 </td> <td>Jul 7, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8956">Athlon 3000G</a> </th> <td>Nov 19, 2019 </td> <td>US $49<a href="#cite_note-112">[79]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10236">Athlon Silver 3050GE</a> </th> <td>3.4 </td> <td>Jul 21, 2020 </td> <td rowspan="4">OEM </td></tr> <tr> <th style="text-align:left;">Ryzen 3 Pro 2100GE<a href="#cite_note-113">[80]</a> </th> <td rowspan="3">3.2 </td> <td>1000 </td> <td>384 </td> <td>2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7646">Ryzen 3 2200GE</a> </th> <td rowspan="4">4 (4) </td> <td rowspan="2">3.6 </td> <td rowspan="4">Vega 8 </td> <td rowspan="4">512:32:16 8 CU </td> <td rowspan="4">1100 </td> <td rowspan="4">1126 </td> <td>Apr 19, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7781">Ryzen 3 Pro 2200GE</a> </th> <td>May 10, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7226">Ryzen 3 2200G</a> </th> <td rowspan="2">3.5 </td> <td rowspan="2">3.7 </td> <td rowspan="2">65 W </td> <td>Feb 12, 2018 </td> <td>US $99<a href="#cite_note-release_2000G-114">[81]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7776">Ryzen 3 Pro 2200G</a> </th> <td>May 10, 2018 </td> <td rowspan="3">OEM </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7651">Ryzen 5 2400GE</a> </th> <td rowspan="4">4 (8) </td> <td rowspan="2">3.2 </td> <td rowspan="2">3.8 </td> <td>RX Vega 11 </td> <td rowspan="4">704:44:16 11 CU </td> <td rowspan="4">1250 </td> <td rowspan="4">1760 </td> <td rowspan="2">35 W </td> <td>Apr 19, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7786">Ryzen 5 Pro 2400GE</a> </th> <td>Vega 11 </td> <td>May 10, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7221">Ryzen 5 2400G</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">3.9 </td> <td>RX Vega 11 </td> <td rowspan="2">65 W </td> <td>Feb 12, 2018 </td> <td>US $169<a href="#cite_note-release_2000G-114">[81]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7771">Ryzen 5 Pro 2400G</a> </th> <td>Vega 11 </td> <td>May 10, 2018 </td> <td>OEM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Zen_based_desktop_APUs" title="Template:AMD Zen based desktop APUs"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Zen_based_desktop_APUs" title="Template talk:AMD Zen based desktop APUs"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Zen_based_desktop_APUs" title="Special:EditPage/Template:AMD Zen based desktop APUs"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-108"><a href="#cite_ref-cconfig_108-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units (CU)</a> </li> <li id="cite_note-SFLOPS-109"><a href="#cite_ref-SFLOPS_109-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Picasso"_(2019)">"Picasso" (2019)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=13" title="Edit section: "Picasso" (2019)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 12 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li><a href="/wiki/Transistor" title="Transistor">Transistors</a>: 4.94 billion</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 210 mm²</li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a></li> <li><a href="/wiki/Zen%2B" title="Zen+">Zen+</a> CPU cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li>Fifth generation <a href="/wiki/Graphics_Core_Next#GCN_5th_Generation_(Vega)" title="Graphics Core Next">GCN</a> based GPU</li> <li><a href="/wiki/Unified_Video_Decoder#VCN_1" title="Unified Video Decoder">Video Core Next</a> (VCN) 1.0</li></ul> Common features of <a href="/wiki/Zen%2B" title="Zen+">Zen+</a> based desktop APUs: <ul><li>Socket: <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a>.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-2933 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode, while Athlon Pro 300GE and Athlon Silver Pro 3125GE support only DDR4-2666.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a> <a href="/wiki/14_nm_process" title="14 nm process">12LP</a>.</li></ul> <style data-mw-deduplicate="TemplateStyles:r1232966811">.mw-parser-output .hover-highlight tr:hover,.mw-parser-output .mw-datatable tr:hover{background-color:var(--background-color-progressive-subtle,#eaf3ff);color:var(--color-base,#333)}.mw-parser-output .mw-datatable{background-color:var(--background-color-base,#fff);color:var(--color-base,#333)}</style> <table class="wikitable hover-highlight" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th colspan="4"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/List_price" title="List price">Release price</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Model<a href="#cite_note-VegaiGPU-118">[i]</a> </th> <th rowspan="2">Config<a href="#cite_note-cconfig-119">[ii]</a> </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-120">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8896">Athlon Pro 300GE</a> </th> <td rowspan="2">2 (4) </td> <td rowspan="2">3.4 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="16">4 MB </td> <td>Vega 3 </td> <td rowspan="6">192:12:4 3 CU </td> <td rowspan="6">1100 </td> <td rowspan="6">424.4 </td> <td rowspan="4">35 W </td> <td>Sep 30, 2019 </td> <td rowspan="8">OEM </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10291">Athlon Silver Pro 3125GE</a> </th> <td rowspan="5">Radeon Graphics </td> <td rowspan="5">Jul 21, 2020 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10231">Athlon Gold 3150GE</a> </th> <td rowspan="9">4 (4) </td> <td rowspan="2">3.3 </td> <td rowspan="2">3.8 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10286">Athlon Gold Pro 3150GE</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10226">Athlon Gold 3150G</a> </th> <td rowspan="2">3.5 </td> <td rowspan="2">3.9 </td> <td rowspan="2">65 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10281">Athlon Gold Pro 3150G</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8996">Ryzen 3 3200GE</a> </th> <td rowspan="2">3.3 </td> <td rowspan="2">3.8 </td> <td rowspan="4">Vega 8 </td> <td rowspan="4">512:32:16 8 CU </td> <td rowspan="2">1200 </td> <td rowspan="2">1228.8 </td> <td rowspan="2">35 W </td> <td>Jul 7, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8891">Ryzen 3 Pro 3200GE</a> </th> <td>Sep 30, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8481">Ryzen 3 3200G</a> </th> <td rowspan="2">3.6 </td> <td rowspan="2">4.0 </td> <td rowspan="2">1250 </td> <td rowspan="2">1280 </td> <td rowspan="2">65 W </td> <td>Jul 7, 2019 </td> <td>US $99<a href="#cite_note-AnandTech3200G-121">[85]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8881">Ryzen 3 Pro 3200G</a> </th> <td>Sep 30, 2019 </td> <td rowspan="5">OEM </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10276">Ryzen 5 Pro 3350GE</a> </th> <td>3.3 </td> <td>3.9 </td> <td rowspan="2">Radeon Graphics </td> <td rowspan="2">640:40:16 10 CU </td> <td>1200 </td> <td>1536 </td> <td>35 W </td> <td rowspan="2">Jul 21, 2020 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10271">Ryzen 5 Pro 3350G</a> </th> <td rowspan="5">4 (8) </td> <td>3.6 </td> <td rowspan="3">4.0 </td> <td rowspan="3">1300 </td> <td rowspan="3">1830.4 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8991">Ryzen 5 3400GE</a> </th> <td rowspan="2">3.3 </td> <td rowspan="2">Vega 11 </td> <td rowspan="4">704:44:16 11 CU </td> <td rowspan="2">35 W </td> <td>Jul 7, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8886">Ryzen 5 Pro 3400GE</a> </th> <td>Sep 30, 2019 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8476">Ryzen 5 3400G</a> </th> <td rowspan="2">3.7 </td> <td rowspan="2">4.2 </td> <td>RX Vega 11 </td> <td rowspan="2">1400 </td> <td rowspan="2">1971.2 </td> <td rowspan="2">65 W </td> <td>Jul 7, 2019 </td> <td>US $149<a href="#cite_note-AnandTech3200G-121">[85]</a> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8876">Ryzen 5 Pro 3400G</a> </th> <td>Vega 11 </td> <td>Sep 30, 2019 </td> <td>OEM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Zen%2B_based_desktop_APUs" title="Template:AMD Zen+ based desktop APUs"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Zen%2B_based_desktop_APUs" title="Template talk:AMD Zen+ based desktop APUs"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Zen%2B_based_desktop_APUs" title="Special:EditPage/Template:AMD Zen+ based desktop APUs"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-VegaiGPU-118"><a href="#cite_ref-VegaiGPU_118-0">^</a> Starting with 2020 releases, <a href="/wiki/AMD" title="AMD">AMD</a> stopped referring to integrated graphics as "Vega", therefore all <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">Vega</a> based <a href="/wiki/Graphics_processing_unit#Integrated_graphics_processing_unit" title="Graphics processing unit">iGPUs</a> are branded as AMD Radeon Graphics (instead Radeon Vega 3 or Radeon Vega 10).<a href="#cite_note-115">[82]</a><a href="#cite_note-116">[83]</a><a href="#cite_note-117">[84]</a> </li> <li id="cite_note-cconfig-119"><a href="#cite_ref-cconfig_119-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units (CU)</a> </li> <li id="cite_note-SFLOPS-120"><a href="#cite_ref-SFLOPS_120-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Renoir"_(2020)">"Renoir" (2020)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=14" title="Edit section: "Renoir" (2020)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a></li> <li>Up to eight <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> CPU cores</li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li></ul> Common features of Ryzen 4000 desktop APUs: <ul><li>Socket: <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a>.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 24 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">7FF</a>.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/List_price" title="List price">Release price</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">L3 cache</a> (total) </th> <th rowspan="2">Core Config<a href="#cite_note-coreconfig-122">[i]</a> </th> <th rowspan="2" class="unsortable">Model </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-123">[ii]</a> </th> <th rowspan="2">Processing power<a href="#cite_note-SFLOPS-124">[iii]</a> (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>) </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="2">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-7-4700g.html">4700G</a><a href="#cite_note-PRO-125">[a]</a> </th> <td rowspan="2">8 (16) </td> <td>3.6 </td> <td>4.4 </td> <td rowspan="4">8 MB </td> <td rowspan="2">2 × 4 </td> <td rowspan="6">Radeon Graphics<a href="#cite_note-gpumodel-126">[b]</a> </td> <td>2.1 </td> <td rowspan="2">512:32:16 8 CU </td> <td>2150.4 </td> <td>65 W </td> <td rowspan="2">Jul 21, 2020 </td> <td rowspan="2">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-7-4700ge.html">4700GE</a><a href="#cite_note-PRO-125">[a]</a> </th> <td>3.1 </td> <td>4.3 </td> <td>2.0 </td> <td>2048 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-5-4600g.html">4600G</a><a href="#cite_note-PRO-125">[a]</a><a href="#cite_note-127">[86]</a> </th> <td rowspan="2">6 (12) </td> <td>3.7 </td> <td rowspan="2">4.2 </td> <td rowspan="2">2 × 3 </td> <td rowspan="2">1.9 </td> <td rowspan="2">448:28:14 7 CU </td> <td rowspan="2">1702.4 </td> <td>65 W </td> <td>Jul 21, 2020 (OEM) / Apr 4, 2022 (retail) </td> <td>OEM / US $154 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-5-4600ge.html">4600GE</a><a href="#cite_note-PRO-125">[a]</a> </th> <td>3.3 </td> <td>35 W </td> <td rowspan="3">Jul 21, 2020 </td> <td rowspan="3">OEM </td></tr> <tr> <th rowspan="2">Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-3-4300g.html">4300G</a><a href="#cite_note-PRO-125">[a]</a> </th> <td rowspan="2">4 (8) </td> <td>3.8 </td> <td rowspan="2">4.0 </td> <td rowspan="2">4 MB </td> <td rowspan="2">1 × 4 </td> <td rowspan="2">1.7 </td> <td rowspan="2">384:24:12 6 CU </td> <td rowspan="2">1305.6 </td> <td>65 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-4000-series/amd-ryzen-3-4300ge.html">4300GE</a><a href="#cite_note-PRO-125">[a]</a> </th> <td>3.5 </td> <td>35 W </td></tr> </tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_4000G_series" title="Template:AMD Ryzen 4000G series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_4000G_series" title="Template talk:AMD Ryzen 4000G series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_4000G_series" title="Special:EditPage/Template:AMD Ryzen 4000G series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-122"><a href="#cite_ref-coreconfig_122-0">^</a> Core complexes (CCXs) × cores per CCX </li> <li id="cite_note-gpuconfig-123"><a href="#cite_ref-gpuconfig_123-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units (CU)</a> </li> <li id="cite_note-SFLOPS-124"><a href="#cite_ref-SFLOPS_124-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-PRO-125">^ <a href="#cite_ref-PRO_125-0">a</a> <a href="#cite_ref-PRO_125-1">b</a> <a href="#cite_ref-PRO_125-2">c</a> <a href="#cite_ref-PRO_125-3">d</a> <a href="#cite_ref-PRO_125-4">e</a> <a href="#cite_ref-PRO_125-5">f</a> Model also available as PRO version as 4350GE,<a href="#cite_note-128">[87]</a> 4350G,<a href="#cite_note-129">[88]</a> 4650GE,<a href="#cite_note-130">[89]</a> 4650G,<a href="#cite_note-131">[90]</a> 4750GE,<a href="#cite_note-132">[91]</a> 4750G,<a href="#cite_note-133">[92]</a> released on July 21, 2020 for OEM only.<a href="#cite_note-134">[93]</a> </li> <li id="cite_note-gpumodel-126"><a href="#cite_ref-gpumodel_126-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Cezanne"_(2021)">"Cezanne" (2021)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=15" title="Edit section: "Cezanne" (2021)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">Socket AM4</a></li> <li>Up to eight <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> CPU cores</li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li></ul> Common features of Ryzen 5000 desktop APUs: <ul><li>Socket: <a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a>.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 24 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">7FF</a>.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="3"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a><a href="#cite_note-gpumodel-135">[a]</a> </th> <th rowspan="3">Thermal solution </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/List_price" title="List price">MSRP</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-136">[i]</a> </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-137">[ii]</a> </th> <th rowspan="2">Processing power<a href="#cite_note-SFLOPS-138">[iii]</a> (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>) </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="2">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-7-5700g.html">5700G</a><a href="#cite_note-PRO-139">[b]</a> </th> <td rowspan="2">8 (16) </td> <td>3.8 </td> <td rowspan="3">4.6 </td> <td rowspan="6">16 MB </td> <td rowspan="2">1 × 8 </td> <td rowspan="2">2000 </td> <td rowspan="2">512:32:8 8 CU </td> <td rowspan="2">2048 </td> <td rowspan="6"><a href="/wiki/AMD_Wraith" title="AMD Wraith">Wraith Stealth</a> </td> <td>65 W </td> <td>Apr 13, 2021 (OEM), Aug 5, 2021 (retail) </td> <td>US $359 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-7-5700ge.html">5700GE</a><a href="#cite_note-PRO-139">[b]</a> </th> <td>3.2 </td> <td>35 W </td> <td>Apr 13, 2021 </td> <td>OEM </td></tr> <tr> <th rowspan="4">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-5-5600gt.html">5600GT</a> </th> <td rowspan="4">6 (12) </td> <td>3.6 </td> <td rowspan="4">1 × 6 </td> <td rowspan="4">1900 </td> <td rowspan="4">448:28:8 7 CU </td> <td rowspan="4">1702.4 </td> <td rowspan="2">65 W </td> <td>Jan 31, 2024<a href="#cite_note-Jan2024-140">[94]</a> </td> <td>US $140 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-5-5600g.html">5600G</a><a href="#cite_note-PRO-139">[b]</a> </th> <td>3.9 </td> <td rowspan="3">4.4 </td> <td>Apr 13, 2021 (OEM), Aug 5, 2021 (retail) </td> <td>US $259 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-5-5600ge.html">5600GE</a><a href="#cite_note-PRO-139">[b]</a> </th> <td>3.4 </td> <td>35 W </td> <td>Apr 13, 2021 </td> <td>OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-5-5500gt.html">5500GT</a> </th> <td>3.6 </td> <td rowspan="2">65 W </td> <td>Jan 31, 2024<a href="#cite_note-Jan2024-140">[94]</a> </td> <td>US $125 </td></tr> <tr> <th rowspan="2">Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-3-5300g.html">5300G</a><a href="#cite_note-PRO-139">[b]</a> </th> <td rowspan="2">4 (8) </td> <td>4.0 </td> <td rowspan="2">4.2 </td> <td rowspan="2">8 MB </td> <td rowspan="2">1 × 4 </td> <td rowspan="2">1700 </td> <td rowspan="2">384:24:8 6 CU </td> <td rowspan="2">1305.6 </td> <td rowspan="2">OEM </td> <td rowspan="2">Apr 13, 2021 </td> <td rowspan="2">OEM </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen/ryzen-5000-series/amd-ryzen-3-5300ge.html">5300GE</a><a href="#cite_note-PRO-139">[b]</a> </th> <td>3.6 </td> <td>35 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: -5px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_5000_desktop_APUs" title="Template:AMD Ryzen 5000 desktop APUs"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_5000_desktop_APUs" title="Template talk:AMD Ryzen 5000 desktop APUs"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_5000_desktop_APUs" title="Special:EditPage/Template:AMD Ryzen 5000 desktop APUs"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-136"><a href="#cite_ref-coreconfig_136-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-137"><a href="#cite_ref-gpuconfig_137-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-138"><a href="#cite_ref-SFLOPS_138-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-135"><a href="#cite_ref-gpumodel_135-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> <li id="cite_note-PRO-139">^ <a href="#cite_ref-PRO_139-0">a</a> <a href="#cite_ref-PRO_139-1">b</a> <a href="#cite_ref-PRO_139-2">c</a> <a href="#cite_ref-PRO_139-3">d</a> <a href="#cite_ref-PRO_139-4">e</a> <a href="#cite_ref-PRO_139-5">f</a> Model also available as PRO version as 5350GE,<a href="#cite_note-141">[95]</a> 5350G,<a href="#cite_note-142">[96]</a> 5650GE,<a href="#cite_note-143">[97]</a> 5650G,<a href="#cite_note-144">[98]</a> 5750GE,<a href="#cite_note-145">[99]</a> 5750G,<a href="#cite_note-146">[100]</a> released June 1, 2021.<a href="#cite_note-147">[101]</a> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Non_APU_or_Radeon_Graphics_branded">Non APU or Radeon Graphics branded</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=16" title="Edit section: Non APU or Radeon Graphics branded">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id=""Raphael"_(2022)">"Raphael" (2022)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=17" title="Edit section: "Raphael" (2022)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 5 nm (CCD) and 6 nm (cIOD) by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li><a href="/wiki/Socket_AM5" title="Socket AM5">Socket AM5</a></li> <li>Up to sixteen <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> CPU cores</li> <li>Dual-channel <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> memory controller</li></ul> <ul><li>Basic <a href="/wiki/IGPU" class="mw-redirect" title="IGPU">iGPU</a></li></ul> Common features of Ryzen 7000 desktop CPUs: <ul><li>Socket: <a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a>.</li> <li>All the CPUs support <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-5200 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 1 MB per core.</li> <li>All the CPUs support 28 <a href="/wiki/PCI_Express#PCI_Express_5.0" title="PCI Express">PCIe 5.0</a> lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>Includes integrated <a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> GPU on the <a href="/wiki/Input/output" title="Input/output">I/O</a> die with 2 CUs and clock speeds of 400 MHz (base), 2.2 GHz (boost).<a href="#cite_note-148">[i]</a> Models with "F" suffixes are without iGPUs.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/5_nm_process" title="5 nm process">N5</a> <a href="/wiki/Fin_field-effect_transistor" title="Fin field-effect transistor">FinFET</a> (N6 FinFET for the I/O die).</li></ul> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1232966811"> <table class="wikitable sortable hover-highlight" style="text-align: center;"> <tbody><tr> <th colspan="2" rowspan="2">Branding and model </th> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Thermal solution </th> <th rowspan="2"><a href="/wiki/Multi-chip_module" title="Multi-chip module">Chiplets</a> </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-149">[ii]</a> </th> <th rowspan="2"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="2">Release date </th> <th rowspan="2"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th>Base </th> <th>Boost </th></tr> <tr> <th rowspan="6">Ryzen 9 </th> <th style="text-align: left" data-sort-value="sku15"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-9-7950x3d.html">7950X3D</a> </th> <td rowspan="2">16 (32) </td> <td>4.2 </td> <td rowspan="2">5.7 </td> <td data-sort-value="128"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">128 MB<a href="#cite_note-3D-VCache-152">[iii]</a> </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="6">2 × <abbr title="Core Complex Die">CCD</abbr> 1 × <abbr title="Input/Output Die">I/OD</abbr> </td> <td rowspan="2">2 × 8 </td> <td>120 W </td> <td>Feb 28, 2023 </td> <td rowspan="2">US $699 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku14"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-9-7950x.html">7950X</a> </th> <td>4.5 </td> <td data-sort-value="64"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">64 MB </td> <td style="text-align: right">170 W </td> <td>Sep 27, 2022 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku13"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-9-7900x3d.html">7900X3D</a> </th> <td rowspan="4">12 (24) </td> <td>4.4 </td> <td rowspan="2">5.6 </td> <td data-sort-value="128"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">128 MB<a href="#cite_note-3D-VCache-152">[iii]</a> </td> <td rowspan="4">2 × 6 </td> <td style="text-align: right">120 W </td> <td>Feb 28, 2023 </td> <td>US $599 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku12"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-9-7900x.html">7900X</a> </th> <td>4.7 </td> <td rowspan="3" data-sort-value="64"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">64 MB </td> <td style="text-align: right">170 W </td> <td>Sep 27, 2022 </td> <td>US $549 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku11"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-9-7900.html">7900</a> </th> <td rowspan="2">3.7 </td> <td rowspan="2">5.4 </td> <td><a href="/wiki/AMD_Wraith#Wraith_Prism" title="AMD Wraith">Wraith Prism</a> </td> <td rowspan="2" style="text-align: right">65 W </td> <td>Jan 10, 2023 </td> <td>US $429<a href="#cite_note-non-x-msrp-153">[104]</a> </td></tr> <tr> <th style="text-align: left" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-pro/ryzen-pro-7000-series/amd-ryzen-9-pro-7945.html">PRO 7945</a> </th> <td><a href="/wiki/AMD_Wraith#Wraith_Spire" title="AMD Wraith">Wraith Spire</a> </td> <td>Jun 13, 2023 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th rowspan="4">Ryzen 7 </th> <th style="text-align: left" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-7-7800x3d.html">7800X3D</a> </th> <td rowspan="4">8 (16) </td> <td>4.2 </td> <td>5.0 </td> <td data-sort-value="96"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">96 MB </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="10">1 × <abbr title="Core Complex Die">CCD</abbr> 1 × <abbr title="Input/Output Die">I/OD</abbr> </td> <td rowspan="4">1 × 8 </td> <td style="text-align: right">120 W </td> <td>Apr 6, 2023 </td> <td>US $449 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-7-7700x.html">7700X</a> </th> <td>4.5 </td> <td>5.4 </td> <td rowspan="3" data-sort-value="32">32 MB </td> <td style="text-align: right">105 W </td> <td>Sep 27, 2022 </td> <td>US $399 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-7-7700.html">7700</a> </th> <td rowspan="2">3.8 </td> <td rowspan="2">5.3 </td> <td>Wraith Prism </td> <td rowspan="3" style="text-align: right">65 W </td> <td>Jan 10, 2023 </td> <td>US $329<a href="#cite_note-non-x-msrp-153">[104]</a> </td></tr> <tr> <th style="text-align: left" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-pro/ryzen-pro-7000-series/amd-ryzen-7-pro-7745.html">PRO 7745</a> </th> <td>Wraith Spire </td> <td>Jun 13, 2023 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th rowspan="6">Ryzen 5 </th> <th style="text-align: left" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7600x3d.html">7600X3D</a><a href="#cite_note-toms7600x3d-154">[105]</a><a href="#cite_note-toms7600x3deurope-155">[106]</a> </th> <td rowspan="6">6 (12) </td> <td>4.1 </td> <td>4.7 </td> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">96 MB </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="6">1 × 6 </td> <td>Aug 31, 2024<a href="#cite_note-156">[iv]</a> </td> <td rowspan="2">US $299 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7600x.html">7600X</a> </th> <td>4.7 </td> <td>5.3 </td> <td rowspan="5">32 MB </td> <td style="text-align: right">105 W </td> <td>Sep 27, 2022 </td></tr> <tr> <th style="text-align: left" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7600.html">7600</a> </th> <td rowspan="2">3.8 </td> <td rowspan="2">5.1 </td> <td><a href="/wiki/AMD_Wraith#Wraith_Stealth" title="AMD Wraith">Wraith Stealth</a> </td> <td rowspan="4" style="text-align: right">65 W </td> <td>Jan 10, 2023 </td> <td>US $229<a href="#cite_note-non-x-msrp-153">[104]</a> </td></tr> <tr> <th style="text-align: left" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/support/downloads/drivers.html/processors/ryzen-pro/ryzen-pro-7000-series/amd-ryzen-5-pro-7645.html">PRO 7645</a> </th> <td>Wraith Spire </td> <td>Jun 13, 2023 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">OEM </td></tr> <tr> <th style="text-align: left" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7500f.html">7500F</a> </th> <td rowspan="2">3.7 </td> <td>5.0 </td> <td rowspan="2">Wraith Stealth </td> <td>Jul 22, 2023 </td> <td>US $179<a href="#cite_note-157">[107]</a> </td></tr> <tr> <th style="text-align: left" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/7000-series/amd-ryzen-5-7400f.html">7400F</a> </th> <td>4.7 </td> <td>Jan 9, 2025 </td> <td> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float:left; position:relative; top:-15px; right:-0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_7000_Series" title="Template:AMD Ryzen 7000 Series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_7000_Series" title="Template talk:AMD Ryzen 7000 Series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_7000_Series" title="Special:EditPage/Template:AMD Ryzen 7000 Series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-148"><a href="#cite_ref-148">^</a> Self identifies as "AMD Radeon Graphics". See <a href="/wiki/RDNA_2#Integrated_graphics_processors_(iGPs)" title="RDNA 2">RDNA 2 § Integrated graphics processors (iGPs)</a>. </li> <li id="cite_note-coreconfig-149"><a href="#cite_ref-coreconfig_149-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-3D-VCache-152">^ <a href="#cite_ref-3D-VCache_152-0">a</a> <a href="#cite_ref-3D-VCache_152-1">b</a> Only one of the two CCXes has additional 64 MB 3D V-Cache.<a href="#cite_note-150">[102]</a> Only the CCX without 3D V-Cache will be able to reach the maximum boost clocks. The CCX with 3D V-Cache will clock lower.<a href="#cite_note-151">[103]</a> </li> <li id="cite_note-156"><a href="#cite_ref-156">^</a> Release date for US, where it is only sold though MicroCenter.<a href="#cite_note-toms7600x3d-154">[105]</a> In Europe it is only available in Germany, and only through MindFactory, which released it on September 5, 2024.<a href="#cite_note-toms7600x3deurope-155">[106]</a> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Phoenix"_(2024)">"Phoenix" (2024)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=18" title="Edit section: "Phoenix" (2024)">edit</a>]</div> Common features of Ryzen 8000G desktop APUs: <ul><li>Socket: <a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a>.</li> <li>All the CPUs support <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-5200 RAM in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode in 2x1R and 2x2R configuration, but only DDR5-3600 for 4x1R and 4x2R.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 1 MB per core.</li> <li>Models with <a href="/wiki/Zen_4#Zen_4c" title="Zen 4">Zen 4c</a> cores (codenamed Phoenix 2) support 14 <a href="/wiki/PCI_Express#PCI_Express_4.0" title="PCI Express">PCIe 4.0</a> lanes, while models without them support 20 lanes. 4 of the lanes are reserved as link to the chipset.</li> <li>Includes integrated <a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a> GPU.</li> <li>Includes XDNA AI Engine (Ryzen AI) on models without Zen 4c cores.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/5_nm_process" title="5 nm process">4 nm</a> FinFET.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="7"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="3"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/AI_accelerator" class="mw-redirect" title="AI accelerator">NPU</a> </th> <th rowspan="3">Thermal solution </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/MSRP" class="mw-redirect" title="MSRP">MSRP</a> </th></tr> <tr> <th colspan="3"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-158">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Core config<a href="#cite_note-Core_config-159">[b]</a><a href="#cite_note-Stream_processors-160">[c]</a> </th> <th rowspan="2">Clock (GHz) </th></tr> <tr> <th>Total </th> <th><a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> </th> <th><a href="/wiki/Zen_4c" class="mw-redirect" title="Zen 4c">Zen 4c</a> </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="2">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-7-8700g.html">8700G</a><a href="#cite_note-PRO-161">[d]</a> </th> <td rowspan="2">8 (16) </td> <td rowspan="2">8 (16) </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>4.2 </td> <td rowspan="2">5.1 </td> <td rowspan="6">16 MB </td> <td rowspan="2">1 × 8 </td> <td rowspan="2">780M </td> <td rowspan="2">12 CUs 768:48:24:12 </td> <td>2.9 </td> <td rowspan="4" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes"><a href="/wiki/Ryzen_AI" class="mw-redirect" title="Ryzen AI">Ryzen AI</a> Up to 16 TOPS </td> <td><a href="/wiki/AMD_Wraith#Wraith_Spire" title="AMD Wraith">Wraith Spire</a> </td> <td>65 W </td> <td>Jan 31, 2024<a href="#cite_note-Anandtech-8000G-162">[108]</a> </td> <td>US $329 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-7-pro-8700ge.html">PRO 8700GE</a> </th> <td>3.6 </td> <td>2.7 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>35 W </td> <td>Apr 16, 2024[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] </td> <td>US $299 </td></tr> <tr> <th rowspan="4">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-5-8600g.html">8600G</a><a href="#cite_note-PRO-161">[d]</a> </th> <td rowspan="4">6 (12) </td> <td rowspan="2">6 (12) </td> <td>4.3 </td> <td rowspan="2">5.0 </td> <td rowspan="2">1 × 6 </td> <td rowspan="2">760M </td> <td rowspan="2">8 CUs 512:32:16:8 </td> <td>2.8 </td> <td><a href="/wiki/AMD_Wraith#Wraith_Stealth" title="AMD Wraith">Wraith Stealth</a> </td> <td>65 W </td> <td>Jan 31, 2024<a href="#cite_note-Anandtech-8000G-162">[108]</a> </td> <td>US $229 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-5-pro-8600ge.html">PRO 8600GE</a> </th> <td>3.9 </td> <td>2.6 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>35 W </td> <td>Apr 16, 2024[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] </td> <td>?? </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-5-8500g.html">8500G</a><a href="#cite_note-PRO-161">[d]</a> </th> <td rowspan="2">2 (4) </td> <td rowspan="2">4 (8) </td> <td>4.1 / 3.2<a href="#cite_note-zen4c-base-163">[e]</a> </td> <td rowspan="2">5.0 / 3.7<a href="#cite_note-zen4c-boost-164">[f]</a> </td> <td rowspan="2">2 + 4 </td> <td rowspan="4">740M </td> <td rowspan="4">4 CUs 256:16:8:4 </td> <td rowspan="2">2.8 </td> <td rowspan="4" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td> <td><a href="/wiki/AMD_Wraith#Wraith_Stealth" title="AMD Wraith">Wraith Stealth</a> </td> <td>65 W </td> <td>Jan 31, 2024 </td> <td>US $179 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-5-8500ge.html">8500GE</a><a href="#cite_note-PRO-161">[d]</a> </th> <td>3.9 / 3.1<a href="#cite_note-zen4c-base-163">[e]</a> </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>35 W </td> <td>Apr 16, 2024[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] </td> <td>?? </td></tr> <tr> <th rowspan="2">Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-3-8300g.html">8300G</a><a href="#cite_note-PRO-161">[d]</a> </th> <td rowspan="2">4 (8) </td> <td rowspan="2">1 (2) </td> <td rowspan="2">3 (6) </td> <td rowspan="2">4.0 / 3.2<a href="#cite_note-zen4c-base-163">[e]</a> </td> <td rowspan="2">4.9 / 3.6<a href="#cite_note-zen4c-boost-164">[f]</a> </td> <td rowspan="2">8 MB </td> <td rowspan="2">1 + 3 </td> <td rowspan="2">2.6 </td> <td><a href="/wiki/AMD_Wraith#Wraith_Stealth" title="AMD Wraith">Wraith Stealth</a> </td> <td>65 W </td> <td>Jan 2024 (OEM) / Q1 2024 (retail) </td> <td>OEM / TBA </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen/8000-series/amd-ryzen-3-8300ge.html">8300GE</a><a href="#cite_note-PRO-161">[d]</a> </th> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>35 W </td> <td>Apr 16, 2024[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] </td> <td>?? </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_8000_desktop_APUs" title="Template:AMD Ryzen 8000 desktop APUs"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_8000_desktop_APUs" title="Template talk:AMD Ryzen 8000 desktop APUs"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_8000_desktop_APUs" title="Special:EditPage/Template:AMD Ryzen 8000 desktop APUs"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-158"><a href="#cite_ref-158">^</a> Core Complexes (CCX) × cores per CCX, or Zen 4 + Zen 4c cores </li> <li id="cite_note-Core_config-159"><a href="#cite_ref-Core_config_159-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> : <a href="/wiki/Ray_tracing_(graphics)" title="Ray tracing (graphics)">Ray accelerators</a> : <a href="/wiki/AI_accelerator" class="mw-redirect" title="AI accelerator">AI accelerators</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units</a> (CU) </li> <li id="cite_note-Stream_processors-160"><a href="#cite_ref-Stream_processors_160-0">^</a> GPUs based on <a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a> have dual-issue stream processors so that up to two shader instructions can be executed per <a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">clock cycle</a> under certain <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">parallelism</a> conditions. </li> <li id="cite_note-PRO-161">^ <a href="#cite_ref-PRO_161-0">a</a> <a href="#cite_ref-PRO_161-1">b</a> <a href="#cite_ref-PRO_161-2">c</a> <a href="#cite_ref-PRO_161-3">d</a> <a href="#cite_ref-PRO_161-4">e</a> <a href="#cite_ref-PRO_161-5">f</a> Model also available as PRO version as 8300G<a href="#cite_note-165">[109]</a>, 8300GE<a href="#cite_note-166">[110]</a>, 8500G<a href="#cite_note-167">[111]</a>, 8500GE<a href="#cite_note-168">[112]</a>, 8600G<a href="#cite_note-169">[113]</a>, 8700G<a href="#cite_note-170">[114]</a>. </li> <li id="cite_note-zen4c-base-163">^ <a href="#cite_ref-zen4c-base_163-0">a</a> <a href="#cite_ref-zen4c-base_163-1">b</a> <a href="#cite_ref-zen4c-base_163-2">c</a> Zen 4 cores' base frequency / Zen 4c cores' base frequency </li> <li id="cite_note-zen4c-boost-164">^ <a href="#cite_ref-zen4c-boost_164-0">a</a> <a href="#cite_ref-zen4c-boost_164-1">b</a> Zen 4 cores' boost frequency / Zen 4c cores' boost frequency </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Server_APUs">Server APUs</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=19" title="Edit section: Server APUs">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="Opteron_X2100-series_"Kyoto"_(2013)_&_"Steppe_Eagle"_(2016)">Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=20" title="Edit section: Opteron X2100-series "Kyoto" (2013) & "Steppe Eagle" (2016)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/wiki/Socket_FT3" title="Socket FT3">FT3</a> (BGA)</li> <li>4 CPU Cores (<a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a> & <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a> microarchitecture)</li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>Single-channel <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> memory controller</li> <li>Turbo Dock Technology, C6 and CC6 low power states</li> <li>GPU based on 2nd generation <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) architecture</li></ul> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th> <th rowspan="3">Release price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a><a href="#cite_note-kib-171">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-172">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="text-align: left"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/1566">X1150</a><a href="#cite_note-173">[115]</a> </th> <td rowspan="2">May 29, 2013<a href="#cite_note-174">[116]</a> </td> <td rowspan="3">28 nm </td> <td rowspan="2"> </td> <td rowspan="3">4 (4) </td> <td>2.0 </td> <td rowspan="3">32 KB inst. 32 KB data per core </td> <td rowspan="3">2 MB </td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">1600 </td> <td>9–17 </td> <td>OX1150IPJ44HM </td> <td>$64 </td></tr> <tr> <th style="text-align: left"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150621165854/http://products.amd.com/en-us/WorkstationAPUDetail.aspx?id=78">X2150</a> </th> <td>1.9 </td> <td>R3 (HD 8400) </td> <td rowspan="2">128:8:4 2 CU </td> <td>266–600 </td> <td>28.9 </td> <td>11–22 </td> <td>OX2150IAJ44HM </td> <td>$99 </td></tr> <tr> <th style="text-align: left"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170103141209/https://www.amd.com/en-us/products/server/opteron-x/x2170">X2170</a> </th> <td>Sep 1, 2016 </td> <td> </td> <td>2.4 </td> <td>R5 </td> <td>655–800 </td> <td>153.6 </td> <td>1866 </td> <td>11–25 </td> <td>OX2170IXJ44JB </td> <td> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-171"><a href="#cite_ref-kib_171-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-172"><a href="#cite_ref-SFLOPS_172-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Opteron_X3000-series_"Toronto"_(2017)">Opteron X3000-series "Toronto" (2017)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=21" title="Edit section: Opteron X3000-series "Toronto" (2017)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a> (BGA)</li> <li>Two or Four CPU cores based on the <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> microarchitecture<a href="#cite_note-175">[117]</a><a href="#cite_note-OpteronX3000-176">[118]</a></li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li>GPU based on 3rd generation <a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_3" title="Graphics Core Next">Graphics Core Next</a> (GCN) architecture</li></ul> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR4 memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th> <th rowspan="3">Release price (<a href="/wiki/United_States_dollar" title="United States dollar">USD</a>) </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-177">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-178">[b]</a> </th></tr> <tr> <th>Base </th> <th><a href="/wiki/AMD_Turbo_Core" title="AMD Turbo Core">Boost</a> </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="text-align: left">X3216<a href="#cite_note-OpteronX3000-176">[118]</a><a href="#cite_note-179">[119]</a> </th> <td>June 2017 </td> <td rowspan="3">28 nm </td> <td rowspan="3">01h </td> <td>[1]2 </td> <td>1.6 </td> <td>3.0 </td> <td rowspan="3">96 KB inst. per module 32 KB data per core </td> <td>1 MB </td> <td>R5 </td> <td>256:16:4 4 CU </td> <td rowspan="3">800 </td> <td>409.6 </td> <td>1600 </td> <td>12–15 </td> <td>OX3216AAY23KA </td> <td rowspan="3">OEM for HP </td></tr> <tr> <th style="text-align: left">X3418<a href="#cite_note-OpteronX3000-176">[118]</a><a href="#cite_note-180">[120]</a> </th> <td> </td> <td rowspan="2">[2]4 </td> <td>1.8 </td> <td>3.2 </td> <td rowspan="2">2 MB </td> <td>R6 </td> <td>384:24:6 6 CU </td> <td>614.4 </td> <td rowspan="2">2400 </td> <td rowspan="2">12–35 </td> <td>OX3418AAY43KA </td></tr> <tr> <th style="text-align: left">X3421<a href="#cite_note-OpteronX3000-176">[118]</a><a href="#cite_note-181">[121]</a> </th> <td>June 2017 </td> <td>2.1 </td> <td>3.4 </td> <td>R7 </td> <td>512:32:8 8 CU </td> <td>819.2 </td> <td>OX3421AAY43KA </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-177"><a href="#cite_ref-kib_177-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-178"><a href="#cite_ref-SFLOPS_178-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Mobile_processors_with_3D_graphics">Mobile processors with 3D graphics</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=22" title="Edit section: Mobile processors with 3D graphics">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="APU_or_Radeon_Graphics_branded_2">APU or Radeon Graphics branded</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=23" title="Edit section: APU or Radeon Graphics branded">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Sabine:_"Llano"_(2011)">Sabine: "Llano" (2011)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=24" title="Edit section: Sabine: "Llano" (2011)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a> <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a> process</li> <li>Socket <a href="/wiki/Socket_FS1" title="Socket FS1">FS1</a></li> <li>Upgraded Stars (AMD 10h architecture) codenamed Husky CPU cores (K10.5) with no L3 cache, and with Redwood-class integrated graphics on die</li> <li>L1 Cache: 64 KB Data per core and 64 KB Instructions per core(BeaverCreek for the dual-core variants and WinterPark for the quad-core variants)</li> <li>Integrated <a href="/wiki/PCIE#PCI_Express_2.0" class="mw-redirect" title="PCIE">PCIe 2.0</a> controller</li> <li>GPU: <a href="/wiki/TeraScale_2" class="mw-redirect" title="TeraScale 2">TeraScale 2</a></li> <li>Select models support Turbo Core technology for faster CPU operation when the thermal specification permits</li> <li>Support for 1.35 V <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1333 memory, in addition to regular 1.5 V DDR3 memory specified</li> <li>2.5 GT/s UMI</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/3DNow!" title="3DNow!">Enhanced 3DNow!</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li> <li><a href="/wiki/PowerNow!" title="PowerNow!">PowerNow!</a></li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-182">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-183">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121951/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=5">E2-3000M</a> </th> <td>2011 6/14 </td> <td rowspan="19">32 nm </td> <td rowspan="19">B0 </td> <td rowspan="8">2 (2) </td> <td>1.8 </td> <td>2.4 </td> <td rowspan="19">64 KB inst. 64 KB data per core </td> <td>2× 512KB </td> <td rowspan="19" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>HD 6380G </td> <td>160:8:4 </td> <td>400 </td> <td>128 </td> <td rowspan="10">1333 </td> <td>35 </td> <td>EM3000DDX22GX </td></tr> <tr> <th colspan="2"></th> <th colspan="2"></th> <th></th> <th colspan="4"></th> <th colspan="2"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095843/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=6">A4-3300M</a> </th> <td>2011 6/14 </td> <td rowspan="2">1.9 </td> <td rowspan="3">2.5 </td> <td>2× 1MB </td> <td rowspan="6">HD 6480G </td> <td>240:12:4 </td> <td>444 </td> <td>213.1 </td> <td rowspan="2">35 </td> <td>AM3300DDX23GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100032/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=29">A4-3305M</a> </th> <td>December 7, 2011 </td> <td>2× 512KB </td> <td>160:8:4 </td> <td>593 </td> <td>189.7 </td> <td>AM3305DDX22GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122040/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=7">A4-3310MX</a> </th> <td>2011 6/14 </td> <td>2.1 </td> <td rowspan="3">2× 1MB </td> <td rowspan="3">240:12:4 </td> <td rowspan="3">444 </td> <td rowspan="3">213.1 </td> <td>45 </td> <td>AM3310HLX23GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122036/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=28">A4-3320M</a> </th> <td rowspan="2">December 7, 2011 </td> <td>2.0 </td> <td rowspan="3">2.6 </td> <td>35 </td> <td>AM3320DDX23GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121957/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=27">A4-3330MX</a> </th> <td>2.2 </td> <td rowspan="2">45 </td> <td>AM3330HLX23GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620113825/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=88">A4-3330MX</a> </th> <td> </td> <td>2.3 </td> <td>2× 512KB </td> <td>160:8:4 </td> <td>593 </td> <td>189.7 </td> <td>AM3330HLX23HX </td></tr> <tr> <th colspan="2"></th> <th colspan="3"></th> <th></th> <th colspan="4"></th> <th colspan="2"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122119/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=8">A6-3400M</a> </th> <td rowspan="2">2011 6/14 </td> <td rowspan="10">4 (4) </td> <td>1.4 </td> <td rowspan="2">2.3 </td> <td rowspan="10">4× 1MB </td> <td rowspan="4">HD 6520G </td> <td rowspan="4">320:16:8 </td> <td rowspan="4">400 </td> <td rowspan="4">256 </td> <td>35 </td> <td>AM3400DDX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095836/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=9">A6-3410MX</a> </th> <td>1.6 </td> <td>1600 </td> <td>45 </td> <td>AM3410HLX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620120654/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=26">A6-3420M</a> </th> <td rowspan="2">December 7, 2011 </td> <td>1.5 </td> <td rowspan="2">2.4 </td> <td>1333 </td> <td>35 </td> <td>AM3420DDX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122042/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=25">A6-3430MX</a> </th> <td>1.7 </td> <td>1600 </td> <td>45 </td> <td>AM3430HLX43GX </td></tr> <tr> <th colspan="2"></th> <th colspan="2"></th> <th colspan="7"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095838/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=10">A8-3500M</a> </th> <td rowspan="2">2011 6/14 </td> <td>1.5 </td> <td>2.4 </td> <td rowspan="5">HD 6620G </td> <td rowspan="5">400:20:8 </td> <td rowspan="5">444 </td> <td rowspan="5">355.2 </td> <td>1333 </td> <td>35 </td> <td>AM3500DDX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122121/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=11">A8-3510MX</a> </th> <td>1.8 </td> <td rowspan="2">2.5 </td> <td>1600 </td> <td>45 </td> <td>AM3510HLX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095840/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=24">A8-3520M</a> </th> <td>December 7, 2011 </td> <td>1.6 </td> <td>1333 </td> <td>35 </td> <td>AM3520DDX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100034/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=12">A8-3530MX</a> </th> <td>2011 6/14 </td> <td>1.9 </td> <td>2.6 </td> <td rowspan="2">1600 </td> <td rowspan="2">45 </td> <td>AM3530HLX43GX </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100109/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=23">A8-3550MX</a> </th> <td>December 7, 2011 </td> <td>2.0 </td> <td>2.7 </td> <td>AM3550HLX43GX </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-182"><a href="#cite_ref-kib_182-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-183"><a href="#cite_ref-SFLOPS_183-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Comal:_"Trinity"_(2012)">Comal: "Trinity" (2012)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=25" title="Edit section: Comal: "Trinity" (2012)">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_(AM4600DEC44HJ)_APU_PNr%C2%B00810.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg/220px-AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg" decoding="async" width="220" height="257" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg/330px-AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bb/AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg/440px-AMD_FS1_CPU_Socket-top_closed_-_with_AMD_A10-4600M_%28AM4600DEC44HJ%29_APU_PNr%C2%B00810.jpg 2x" data-file-width="2524" data-file-height="2951" /></a><figcaption>An AMD A10-4600M APU</figcaption></figure> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on GlobalFoundries SOI process</li> <li>Socket <a href="/wiki/Socket_FS1" title="Socket FS1">FS1r2</a>, <a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a></li> <li>Based on the <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver architecture</a></li> <li>L1 Cache: 16 KB Data per core and 64 KB Instructions per module</li> <li>GPU: <a href="/wiki/TeraScale_3" class="mw-redirect" title="TeraScale 3">TeraScale 3</a> (VLIW4)</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Memory support: 1.35 V <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 memory, in addition to regular 1.5 V DDR3 memory specified (Dual-channel)</li> <li>2.5 GT/s UMI</li> <li>Transistors: 1.303 billion</li> <li>Die size: 246 mm²</li></ul> <div style="clear:both;" class=""></div> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th rowspan="3">Socket </th> <th colspan="5">CPU </th> <th colspan="5">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-184">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-fn_2-185">[note 1]</a> </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-186">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095759/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=51">A4-4355M</a> </th> <td>September 27, 2012 </td> <td rowspan="11">32 nm </td> <td rowspan="11">TN-A1 </td> <td rowspan="6">FP2 </td> <td rowspan="2">[1]2 </td> <td>1.9 </td> <td>2.4 </td> <td rowspan="11">64 KB inst. per module 16 KB data per core </td> <td>1 </td> <td>HD 7400G </td> <td>192:12:4 3 CU </td> <td rowspan="2">327 </td> <td rowspan="3">424 </td> <td>125.5 </td> <td rowspan="3">1333 </td> <td rowspan="2">17 </td> <td>AM4355SHE23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122201/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=38">A6-4455M</a> </th> <td>May 15, 2012 </td> <td>2.1 </td> <td>2.8 </td> <td>2 </td> <td>HD 7500G </td> <td>256:16:8 4 CU </td> <td>167.4 </td> <td>AM4455SHE24HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122330/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=50">A8-4555M</a> </th> <td>September 27, 2012 </td> <td rowspan="4">[2]4 </td> <td>1.6 </td> <td>2.4 </td> <td rowspan="4">2× 2MB </td> <td>HD 7600G </td> <td>384:24:8 6 CU </td> <td>320 </td> <td>245.7 </td> <td>19 </td> <td>AM4555SHE44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A8-4557M<a href="#cite_note-CPUWorldA8-187">[122]</a> </th> <td>Mar 2013 </td> <td>1.9 </td> <td>2.8 </td> <td>HD 7000 </td> <td>256:16:8 4 CU </td> <td>497 </td> <td>655 </td> <td>254.4 </td> <td>(L)1600 </td> <td>35 </td> <td>AM4557DFE44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122244/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=37">A10-4655M</a> </th> <td>May 15, 2012 </td> <td>2.0 </td> <td>2.8 </td> <td>HD 7620G </td> <td rowspan="2">384:24:8 6 CU </td> <td>360 </td> <td>496 </td> <td>276.4 </td> <td>1333 </td> <td>25 </td> <td>AM4655SIE44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A10-4657M<a href="#cite_note-CPUWorldA8-187">[122]</a> </th> <td>Mar 2013 </td> <td>2.3 </td> <td>3.2 </td> <td>HD 7000 </td> <td>497 </td> <td>686 </td> <td>381.6 </td> <td>(L)1600 </td> <td rowspan="6">35 </td> <td>AM4657DFE44HJ </td></tr> <tr> <th colspan="2"></th> <th colspan="4"></th> <th></th> <th colspan="6"> </th> <th> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095950/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=43">A4-4300M</a> </th> <td rowspan="4">May 15, 2012 </td> <td rowspan="4">FS1r2 </td> <td rowspan="2">[1]2 </td> <td>2.5 </td> <td>3.0 </td> <td rowspan="2">1 </td> <td>HD 7420G </td> <td>128:8:4 2 CU </td> <td>480 </td> <td>655 </td> <td>122.8 </td> <td rowspan="4">1600 </td> <td>AM4300DEC23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095638/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=36">A6-4400M</a> </th> <td>2.7 </td> <td>3.2 </td> <td>HD 7520G </td> <td>192:12:4 3 CU </td> <td rowspan="3">496 </td> <td rowspan="3">685 </td> <td>190.4 </td> <td>AM4400DEC23HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121821/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=35">A8-4500M</a> </th> <td rowspan="2">[2]4 </td> <td>1.9 </td> <td>2.8 </td> <td rowspan="2">2× 2MB </td> <td>HD 7640G </td> <td>256:16:8 4 CU </td> <td>253.9 </td> <td>AM4500DEC44HJ </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121647/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=34">A10-4600M</a> </th> <td>2.3 </td> <td>3.2 </td> <td>HD 7660G </td> <td>384:24:8 6 CU </td> <td>380.9 </td> <td>AM4600DEC44HJ </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-184"><a href="#cite_ref-kib_184-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-186"><a href="#cite_ref-SFLOPS_186-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-fn_2-185"><a href="#cite_ref-fn_2_185-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shader processors</a> (USPs): <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> (TMUs): <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Richland"_(2013)_2">"Richland" (2013)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=26" title="Edit section: "Richland" (2013)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm on GlobalFoundries SOI process</li> <li>Socket <a href="/wiki/Socket_FS1" title="Socket FS1">FS1r2</a>, <a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a></li> <li>Elite Performance APU.<a href="#cite_note-188">[123]</a><a href="#cite_note-189">[124]</a></li> <li>CPU: <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver architecture</a> <ul><li>L1 Cache: 16 KB Data per core and 64 KB Instructions per module</li></ul></li> <li>GPU: <a href="/wiki/TeraScale_3" class="mw-redirect" title="TeraScale 3">TeraScale 3</a> (VLIW4)</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th rowspan="3">Socket </th> <th colspan="5">CPU </th> <th colspan="5">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-190">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-fn_2-191">[note 1]</a> </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-192">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620114958/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=77">A4-5145M</a> </th> <td rowspan="4">2013/5 </td> <td rowspan="12">32 nm </td> <td rowspan="12">RL-A1 </td> <td rowspan="4">FP2 </td> <td rowspan="2">[1]2 </td> <td>2.0 </td> <td>2.6 </td> <td rowspan="12">64 KB inst. per module 16 KB data per core </td> <td rowspan="2">1 </td> <td>HD 8310G </td> <td>128:8:4 2 CU </td> <td>424 </td> <td>554 </td> <td>108.5 </td> <td rowspan="4">(L)1333 </td> <td rowspan="2">17 </td> <td>AM5145SIE44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122123/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=76">A6-5345M</a> </th> <td>2.2 </td> <td>2.8 </td> <td>HD 8410G </td> <td>192:12:4 3 CU </td> <td rowspan="2">450 </td> <td>600 </td> <td>172.8 </td> <td>AM5345SIE44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620115406/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=75">A8-5545M</a> </th> <td rowspan="2">[2]4 </td> <td>1.7 </td> <td>2.7 </td> <td rowspan="2">4 </td> <td>HD 8510G </td> <td rowspan="2">384:28:8 6 CU </td> <td>554 </td> <td>345.6 </td> <td>19 </td> <td>AM5545SIE44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620124410/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=74">A10-5745M</a> </th> <td>2.1 </td> <td>2.9 </td> <td>HD 8610G </td> <td>533 </td> <td>626 </td> <td>409.3 </td> <td>25 </td> <td>AM5745SIE44HL </td></tr> <tr> <th colspan="2"> </th> <th colspan="4"></th> <th></th> <th colspan="8"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620113911/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=65">A4-5150M</a> </th> <td rowspan="2">2013 Q1 </td> <td rowspan="2">FS1r2 </td> <td rowspan="3">[1]2 </td> <td>2.7 </td> <td>3.3 </td> <td rowspan="3">1 </td> <td>HD 8350G </td> <td>128:8:4 2 CU </td> <td rowspan="3">533 </td> <td rowspan="7">720 </td> <td>136.4 </td> <td rowspan="2">1600 </td> <td rowspan="7">35 </td> <td>AM5150DEC23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122246/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=64">A6-5350M</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">3.5 </td> <td rowspan="2">HD 8450G </td> <td rowspan="2">192:12:4 3 CU </td> <td rowspan="2">204.6 </td> <td>AM5350DEC23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620125650/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=73">A6-5357M</a> </th> <td>2013/5 </td> <td>FP2 </td> <td>(L)1600 </td> <td>AM5357DFE23HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620122653/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=63">A8-5550M</a> </th> <td>2013 Q1 </td> <td>FS1r2 </td> <td rowspan="4">[2]4 </td> <td rowspan="2">2.1 </td> <td rowspan="2">3.1 </td> <td rowspan="4">4 </td> <td rowspan="2">HD 8550G </td> <td rowspan="2">256:16:8 4 CU </td> <td>515 </td> <td>263.6 </td> <td>1600 </td> <td>AM5550DEC44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620114809/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=72">A8-5557M</a> </th> <td>2013/5 </td> <td>FP2 </td> <td>554 </td> <td>283.6 </td> <td>(L)1600 </td> <td>AM5557DFE44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620121303/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=62">A10-5750M</a> </th> <td>2013 Q1 </td> <td>FS1r2 </td> <td rowspan="2">2.5 </td> <td rowspan="2">3.5 </td> <td rowspan="2">HD 8650G </td> <td rowspan="2">384:24:8 6 CU </td> <td>533 </td> <td>409.3 </td> <td>1866 </td> <td>AM5750DEC44HL </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620124215/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=71">A10-5757M</a> </th> <td>2013/5 </td> <td>FP2 </td> <td>600 </td> <td>460.8 </td> <td>(L)1600 </td> <td>AM5757DFE44HL </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-190"><a href="#cite_ref-kib_190-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-192"><a href="#cite_ref-SFLOPS_192-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-fn_2-191"><a href="#cite_ref-fn_2_191-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shader processors</a> (USPs): <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> (TMUs): <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Kaveri"_(2014)">"Kaveri" (2014)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=27" title="Edit section: "Kaveri" (2014)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a></li> <li>Up to 4 <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a> x86 CPU cores with 4 MB of L2 cache.<a href="#cite_note-193">[125]</a></li> <li>L1 Cache: 16 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Three to eight Compute Units (CUs) based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN)<a href="#cite_note-wccftech-66">[43]</a> microarchitecture; 1 Compute Unit (CU) consists of 64 <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shader Processors</a> : 4 <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> (TMUs) : 1 <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Unit</a> (ROPs)</li> <li><a href="/wiki/AMD_Accelerated_Processing_Unit#HSA" class="mw-redirect" title="AMD Accelerated Processing Unit">AMD Heterogeneous System Architecture</a> (HSA) 2.0</li> <li><a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">SIP blocks</a>: <a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder</a>, <a href="/wiki/Video_Coding_Engine" title="Video Coding Engine">Video Coding Engine</a>, <a href="/wiki/AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a><a href="#cite_note-SemiAccurate-67">[44]</a></li> <li>Dual-channel (2x64-bit) <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> memory controller</li> <li>Integrated custom <a href="/wiki/ARM_Cortex-A5" title="ARM Cortex-A5">ARM Cortex-A5</a> co-processor<a href="#cite_note-arstechnica.com-68">[45]</a> with <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> Security Extensions<a href="#cite_note-technewspedia.com-69">[46]</a></li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th colspan="5">CPU </th> <th colspan="5">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-194">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-195">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095919/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=124">A6-7000</a> </th> <td rowspan="12">June 2014 </td> <td rowspan="12">28 nm </td> <td rowspan="2">[1]2 </td> <td rowspan="2">2.2 </td> <td rowspan="2">3.0 </td> <td rowspan="12">96 KB inst. per module 16 KB data per core </td> <td rowspan="2">1 </td> <td rowspan="2">R4 </td> <td rowspan="2">192:12:3 3 CU </td> <td>494 </td> <td>533 </td> <td>189.6 </td> <td>1333 </td> <td rowspan="2">17 </td> <td>AM7000ECH23JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140725140917/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=128">A6 PRO - 7050B</a> </th> <td>533 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>204.6 </td> <td>1600 </td> <td>AM705BECH23JA </td></tr> <tr> <th></th> <th colspan="3"></th> <th></th> <th colspan="8"> </th></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100118/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=123">A8-7100</a> </th> <td rowspan="9">[2]4 </td> <td>1.8 </td> <td>3.0 </td> <td rowspan="9">2× 2 MB </td> <td rowspan="2">R5 </td> <td rowspan="2">256:16:4 4 CU </td> <td>450 </td> <td>514 </td> <td>230.4 </td> <td rowspan="5">1600 </td> <td rowspan="5">20 </td> <td>AM7100ECH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140725140613/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=127">A8 PRO - 7150B</a> </th> <td rowspan="2">1.9 </td> <td rowspan="2">3.2 </td> <td>553 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>283.1 </td> <td>AM715BECH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121959/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=122">A10-7300</a> </th> <td rowspan="2">R6 </td> <td rowspan="3">384:24:8 6 CU </td> <td>464 </td> <td>533 </td> <td>356.3 </td> <td>AM7300ECH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/A10-PRO-7350B-with-Radeon%E2%84%A2-R6-Graphics/113">A10 PRO - 7350B</a> </th> <td rowspan="2">2.1 </td> <td rowspan="2">3.3 </td> <td>533 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>424.7 </td> <td>AM735BECH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095913/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=121">FX-7500</a> </th> <td>R7 </td> <td>498 </td> <td>553 </td> <td>382.4 </td> <td>FM7500ECH44JA </td></tr> <tr> <th></th> <th colspan="2"></th> <th colspan="7"></th> <th> </th></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122045/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=120">A8-7200P</a> </th> <td>2.4 </td> <td>3.3 </td> <td>R5 </td> <td>256:16:4 4 CU </td> <td>553 </td> <td>626 </td> <td>283.1 </td> <td rowspan="2">1866 </td> <td rowspan="3">35 </td> <td>AM740PDGH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121954/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=119">A10-7400P</a> </th> <td>2.5 </td> <td>3.4 </td> <td>R6 </td> <td>384:24:8 6 CU </td> <td>576 </td> <td>654 </td> <td>442.3 </td> <td>AM740PDGH44JA </td></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100113/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=118">FX-7600P</a> </th> <td>2.7 </td> <td>3.6 </td> <td>R7 </td> <td>512:32:8 8 CU </td> <td>600 </td> <td>686 </td> <td>614.4 </td> <td>2133 </td> <td>FM760PDGH44JA </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-194"><a href="#cite_ref-kib_194-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-195"><a href="#cite_ref-SFLOPS_195-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Carrizo"_(2015)">"Carrizo" (2015)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=28" title="Edit section: "Carrizo" (2015)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket FP4</li> <li>Up to 4 <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> x86 CPU cores</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> 1.2</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="text-align:left" rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-196">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-197">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="text-align:right; font-size:85%;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-8500P-with-Radeon%E2%84%A2-R5-Graphics/126">A6-8500P</a> </th> <td rowspan="2">June 2015 </td> <td rowspan="13">28 nm </td> <td rowspan="3">[1]2 </td> <td rowspan="2">1.6 </td> <td rowspan="2">3.0 </td> <td rowspan="13">96 KB inst. per module 32 KB data per core </td> <td rowspan="3">1 </td> <td rowspan="3">R5 </td> <td rowspan="3">256:16:4 4 CU </td> <td rowspan="3">800 </td> <td rowspan="3">409.6 </td> <td rowspan="2">3)1600 </td> <td rowspan="13">12- 35 </td> <td>AM850PAAY23KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/AMD-PRO-A6-8500B-with-Radeon%E2%84%A2-R5-Graphics/161">PRO A6-8500B</a> </th> <td>AM850BAAY23KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/6th-Gen-AMD-PRO-A6-8530B-APU/238">PRO A6-8530B</a> </th> <td>Q3 2016 </td> <td>2.3 </td> <td>3.2 </td> <td>4)1866 </td> <td>AM853BADY23AB </td></tr> <tr> <th colspan="2"> </th> <th colspan="3"></th> <th></th> <th colspan="3"></th> <th colspan="2"> </th> <th> </th></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Laptops/A8-8600P-with-Radeon%E2%84%A2-R6-Graphics/125">A8-8600P</a> </th> <td rowspan="4">June 2015 </td> <td rowspan="9">[2]4 </td> <td rowspan="2">1.6 </td> <td rowspan="2">3.0 </td> <td rowspan="9">2× 1MB </td> <td rowspan="4">R6 </td> <td rowspan="5">384:24:8 6 CU </td> <td rowspan="2">720 </td> <td rowspan="2">552.9 </td> <td rowspan="4">3)2133 </td> <td>AM860PAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/AMD-PRO-A8-8600B-with-Radeon%E2%84%A2-R6-Graphics/162">PRO A8-8600B</a> </th> <td>AM860BAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/A10-8700P-with-Radeon%E2%84%A2-R6-Graphics/124">A10-8700P</a> </th> <td rowspan="2">1.8 </td> <td rowspan="2">3.2 </td> <td rowspan="2">800 </td> <td rowspan="2">614.4 </td> <td>AM870PAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/AMD-PRO-A10-8700B-with-Radeon%E2%84%A2-R6-Graphics/163">PRO A10-8700B</a> </th> <td>AM870BAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/6th-Gen-AMD-PRO-A10-8730B-APU/237">PRO A10-8730B</a> </th> <td>Q3 2016 </td> <td>2.4 </td> <td>3.3 </td> <td>R5 </td> <td>720 </td> <td>552.9 </td> <td>4)1866 </td> <td>AM873BADY44AB </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/CPUs/Bulldozer/AMD-A10-Series%20A10-8780P%20Extreme.html">A10-8780P</a> </th> <td>December 2015 </td> <td>2.0 </td> <td>3.3 </td> <td>R8 </td> <td rowspan="3">512:32:8 8 CU </td> <td> </td> <td> </td> <td>3)? </td> <td>AM878PAIY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/FX-8800P-with-Radeon%E2%84%A2-R7-Graphics/123">FX-8800P</a> </th> <td rowspan="2">June 2015 </td> <td rowspan="2">2.1 </td> <td rowspan="2">3.4 </td> <td rowspan="3">R7 </td> <td rowspan="2">800 </td> <td rowspan="2">819.2 </td> <td rowspan="2">4)2133 </td> <td>FM880PAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/AMD-PRO-A12-8800B-with-Radeon%E2%84%A2-R7-Graphics/164">PRO A12-8800B</a> </th> <td>FM880BAAY43KA </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/6th-Gen-AMD-PRO-A12-8830B-APU/236">PRO A12-8830B</a> </th> <td>Q3 2016 </td> <td>2.5 </td> <td>3.4 </td> <td>384:24:8 6 CU </td> <td>758 </td> <td>582.1 </td> <td>4)1866 </td> <td>AM883BADY44AB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-196"><a href="#cite_ref-kib_196-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-197"><a href="#cite_ref-SFLOPS_197-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Bristol_Ridge"_(2016)_2">"Bristol Ridge" (2016)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=29" title="Edit section: "Bristol Ridge" (2016)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket FP4<a href="#cite_note-AMDGen7-198">[126]</a></li> <li>Two or four "<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>" x86 CPU cores</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> 1.2 with <a href="/wiki/VP9" title="VP9">VP9</a> decoding</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="text-align:left" rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR4 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-199">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-200">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/7th-Gen-AMD-PRO-A6-9500B-APU/227">Pro A6-9500B</a> </th> <td>October 24, 2016 </td> <td rowspan="16">28nm </td> <td>[1]2 </td> <td>2.3 </td> <td>3.2 </td> <td rowspan="16">96 KB inst. per module 32 KB data per core </td> <td>1 </td> <td>R5 </td> <td>256:16:4 4 CU </td> <td>800 </td> <td>409.6 </td> <td>1866 </td> <td>12- 15 </td> <td> </td></tr> <tr> <th colspan="2"> </th> <th colspan="3"></th> <th></th> <th colspan="3"></th> <th colspan="4"> </th></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/7th-Gen-AMD-PRO-A8-9600B-APU/226">Pro A8-9600B</a> </th> <td>October 24, 2016 </td> <td rowspan="14">[2]4 </td> <td rowspan="2">2.4 </td> <td rowspan="2">3.3 </td> <td rowspan="14">2× 1 MB </td> <td rowspan="3">R5 </td> <td rowspan="9">384:24:6 6 CU </td> <td rowspan="2">720 </td> <td rowspan="2">552.9 </td> <td rowspan="5">1866 </td> <td rowspan="5">12– 15 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/7th-Gen-A10-9600P-APU/197">A10-9600P</a> </th> <td>June 2016 </td> <td>AM960PADY44AB </td></tr> <tr> <th style="text-align:right; font-size:85%">A10-9620P<a href="#cite_note-201">[127]</a> </th> <td>2017 (OEM) </td> <td rowspan="3">2.5 </td> <td rowspan="3">3.4 </td> <td rowspan="3">758 </td> <td rowspan="3">582.1 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/7th-Gen-AMD-PRO-A10-9700B-APU/224">Pro A10-9700B</a> </th> <td>October 24, 2016 </td> <td rowspan="2">R7 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A12-Series-APU-for-Laptops/7th-Gen-A12-9700P-APU/195">A12-9700P</a> </th> <td>June 2016 </td> <td>AM970PADY44AB </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A8-APU-for-Laptops/7th-Gen-AMD-PRO-A8-9630B/225">Pro A8-9630B</a> </th> <td>October 24, 2016 </td> <td rowspan="2">2.6 </td> <td rowspan="2">3.3 </td> <td rowspan="2">R5 </td> <td rowspan="2">800 </td> <td rowspan="2">614.4 </td> <td rowspan="4">2400 </td> <td rowspan="4">25– 45 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A10-Series-APU-for-Laptops/7th-Gen-A10-9630P-APU/196">A10-9630P</a> </th> <td>June 2016 </td> <td>AM963PAEY44AB </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A10-APU-for-Laptops/7th-Gen-AMD-PRO-A10-9730B-APU/223">Pro A10-9730B</a> </th> <td>October 24, 2016 </td> <td rowspan="2">2.8 </td> <td rowspan="2">3.5 </td> <td rowspan="2">R7 </td> <td rowspan="2">900 </td> <td rowspan="2">691.2 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A12-Series-APU-for-Laptops/7th-Gen-A12-9730P-APU/194">A12-9730P</a> </th> <td>June 2016 </td> <td>AM973PAEY44AB </td></tr> <tr> <th colspan="2"></th> <th colspan="2"></th> <th colspan="3"></th> <th colspan="4"> </th></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/7th-Gen-AMD-PRO-A12-9800B-APU/222">Pro A12-9800B</a> </th> <td>October 24, 2016 </td> <td rowspan="2">2.7 </td> <td rowspan="2">3.6 </td> <td rowspan="4">R7 </td> <td rowspan="4">512:32:8 8 CU </td> <td rowspan="2">758 </td> <td rowspan="2">776.1 </td> <td rowspan="2">1866 </td> <td rowspan="2">12– 15 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external autonumber" href="http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/7th-Gen-FX%E2%84%A2-9800P-APU/193">[1]</a> FX-9800P A12-9720P<a href="#cite_note-202">[128]</a><a href="#cite_note-203">[129]</a> </th> <td>June 2016 2017 (OEM)</td> <td>FM980PADY44AB ? </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A12-APU-for-Laptops/7th-Gen-AMD-PRO-A12-9830B-APU/221">Pro A12-9830B</a> </th> <td>October 24, 2016 </td> <td rowspan="2">3.0 </td> <td rowspan="2">3.7 </td> <td rowspan="2">900 </td> <td rowspan="2">921.6 </td> <td rowspan="2">2400 </td> <td rowspan="2">25– 45 </td> <td> </td></tr> <tr> <th style="text-align:right; font-size:85%"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-FX-Series-Processors/AMD-FX-Series-Processors-for-Laptops/7th-Gen-FX%E2%84%A2-9830P-APU/191">FX-9830P</a> </th> <td>June 2016 </td> <td>FM983PAEY44AB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-199"><a href="#cite_ref-kib_199-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-200"><a href="#cite_ref-SFLOPS_200-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Raven_Ridge"_(2017)">"Raven Ridge" (2017)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=30" title="Edit section: "Raven Ridge" (2017)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li><a href="/wiki/Transistor" title="Transistor">Transistors</a>: 4.94 billion</li> <li>Socket FP5</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 210 mm²</li> <li><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> CPU cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU</li></ul> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1232966811"> <table class="wikitable hover-highlight" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th rowspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> lanes </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-204">[i]</a> </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">MHz</a>) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-205">[ii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8201">Athlon Pro 200U</a> </th> <td>2019 </td> <td rowspan="12"><a href="/wiki/GlobalFoundries" title="GlobalFoundries">GloFo</a> <a href="/wiki/14_nm_process" title="14 nm process">14LP</a> </td> <td rowspan="4">2 (4) </td> <td>2.3 </td> <td>3.2 </td> <td rowspan="12">64 KB inst. 32 KB data per core </td> <td rowspan="12">512 KB per core </td> <td rowspan="12">4 MB </td> <td rowspan="4">Radeon Vega 3 </td> <td rowspan="4">192:12:4 3 CU </td> <td rowspan="2">1000 </td> <td rowspan="2">384 </td> <td rowspan="12">FP5 </td> <td rowspan="12">12 (8+4) </td> <td rowspan="8">DDR4-2400 <a href="/wiki/Dual-channel_architecture" class="mw-redirect" title="Dual-channel architecture">dual-channel</a> </td> <td rowspan="8">12–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8356">Athlon 300U</a> </th> <td>Jan 6, 2019 </td> <td>2.4 </td> <td>3.3 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7231">Ryzen 3 2200U</a> </th> <td>Jan 8, 2018 </td> <td>2.5 </td> <td>3.4 </td> <td>1100 </td> <td>422.4 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8351">Ryzen 3 3200U</a> </th> <td>Jan 6, 2019 </td> <td>2.6 </td> <td>3.5 </td> <td>1200 </td> <td>460.8 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7236">Ryzen 3 2300U</a> </th> <td>Jan 8, 2018 </td> <td rowspan="2">4 (4) </td> <td rowspan="4">2.0 </td> <td rowspan="2">3.4 </td> <td rowspan="2">Radeon Vega 6 </td> <td rowspan="2">384:24:8 6 CU </td> <td rowspan="5">1100 </td> <td rowspan="2">844.8 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7216">Ryzen 3 Pro 2300U</a> </th> <td>May 15, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/5311">Ryzen 5 2500U</a> </th> <td>Oct 26, 2017 </td> <td rowspan="6">4 (8) </td> <td rowspan="3">3.6 </td> <td rowspan="3">Radeon Vega 8 </td> <td rowspan="3">512:32:16 8 CU </td> <td rowspan="3">1126.4 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7211">Ryzen 5 Pro 2500U</a> </th> <td>May 15, 2018 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8256">Ryzen 5 2600H</a> </th> <td>Sep 10, 2018 </td> <td>3.2 </td> <td>DDR4-3200 dual-channel </td> <td>35–54 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/5306">Ryzen 7 2700U</a> </th> <td>Oct 26, 2017 </td> <td rowspan="2">2.2 </td> <td rowspan="3">3.8 </td> <td>Radeon RX Vega 10 </td> <td rowspan="2">640:40:16 10 CU </td> <td rowspan="3">1300 </td> <td rowspan="2">1664 </td> <td rowspan="2">DDR4-2400 dual-channel </td> <td rowspan="2">12–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7206">Ryzen 7 Pro 2700U</a> </th> <td>May 15, 2018 </td> <td>Radeon Vega 10 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8251">Ryzen 7 2800H</a> </th> <td>Sep 10, 2018 </td> <td>3.3 </td> <td>Radeon RX Vega 11 </td> <td>704:44:16 11 CU </td> <td>1830.4 </td> <td>DDR4-3200 dual-channel </td> <td>35–54 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left; position: relative; top: -15px; right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Zen_based_mobile_APUs" title="Template:AMD Zen based mobile APUs"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Zen_based_mobile_APUs" title="Template talk:AMD Zen based mobile APUs"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Zen_based_mobile_APUs" title="Special:EditPage/Template:AMD Zen based mobile APUs"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-204"><a href="#cite_ref-cconfig_204-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units</a> (CU) </li> <li id="cite_note-SFLOPS-205"><a href="#cite_ref-SFLOPS_205-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Picasso"_(2019)_2">"Picasso" (2019)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=31" title="Edit section: "Picasso" (2019)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 12 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket FP5</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 210 mm²</li> <li>Up to four <a href="/wiki/Zen%2B" title="Zen+">Zen+</a> CPU cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual-channel <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> memory controller</li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU</li></ul> Common features of Ryzen 3000 notebook APUs: <ul><li>Socket: FP5.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-2400 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 96 KB (32 KB data + 64 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a> <a href="/wiki/14_nm_process" title="14 nm process">12LP (14LP+)</a>.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and Model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-206">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-207">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-208">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="4">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku11">3780U<a href="#cite_note-209">[130]</a> </th> <td rowspan="9">4 (8) </td> <td rowspan="4">2.3 </td> <td rowspan="4">4.0 </td> <td rowspan="11">4 MB </td> <td rowspan="11">1 × 4 </td> <td>RX Vega 11 </td> <td rowspan="4">1.4 </td> <td>704:44:16 11 CU </td> <td>1971.2 </td> <td>15 W </td> <td>Oct 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku10">3750H<a href="#cite_note-amd-r3750h-210">[131]</a> </th> <td rowspan="3">RX Vega 10 </td> <td rowspan="3">640:40:16 10 CU<a href="#cite_note-211">[132]</a> </td> <td rowspan="3">1792.0 </td> <td>35 W </td> <td>Jan 6, 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9">3700C<a href="#cite_note-212">[133]</a> </th> <td rowspan="3">15 W </td> <td>Sep 22, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8">3700U<a href="#cite_note-PRO-213">[a]</a><a href="#cite_note-amd-r3700u-214">[134]</a> </th> <td>Jan 6, 2019 </td></tr> <tr> <th rowspan="5">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku7">3580U<a href="#cite_note-215">[135]</a> </th> <td rowspan="7">2.1 </td> <td rowspan="4">3.7 </td> <td>Vega 9 </td> <td>1.3 </td> <td>576:36:16 9 CU </td> <td>1497.6 </td> <td>Oct 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6">3550H<a href="#cite_note-amd-r3550h-216">[136]</a> </th> <td rowspan="4">Vega 8 </td> <td rowspan="6">1.2 </td> <td rowspan="4">512:32:16 8 CU<a href="#cite_note-217">[137]</a> </td> <td rowspan="4">1228.8 </td> <td>35 W </td> <td>Jan 6, 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5">3500C<a href="#cite_note-218">[138]</a> </th> <td rowspan="5">15 W </td> <td>Sep 22, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4">3500U<a href="#cite_note-PRO-213">[a]</a><a href="#cite_note-amd-r3500u-219">[139]</a> </th> <td>Jan 6, 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3">3450U<a href="#cite_note-220">[140]</a> </th> <td rowspan="3">3.5 </td> <td>Jun 2020 </td></tr> <tr> <th rowspan="2">Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku2">3350U<a href="#cite_note-221">[141]</a> </th> <td rowspan="2">4 (4) </td> <td rowspan="2">Vega 6 </td> <td rowspan="2">384:24:8 6 CU<a href="#cite_note-222">[142]</a> </td> <td rowspan="2">921.6 </td> <td rowspan="2">Jan 6, 2019 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1">3300U<a href="#cite_note-PRO-213">[a]</a><a href="#cite_note-amd-r3300u-223">[143]</a> </th></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Mobile_3000_Zen%2B_based_series" title="Template:AMD Ryzen Mobile 3000 Zen+ based series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Mobile_3000_Zen%2B_based_series" title="Template talk:AMD Ryzen Mobile 3000 Zen+ based series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Mobile_3000_Zen%2B_based_series" title="Special:EditPage/Template:AMD Ryzen Mobile 3000 Zen+ based series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-206"><a href="#cite_ref-coreconfig_206-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-207"><a href="#cite_ref-gpuconfig_207-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute Units (CU)</a> </li> <li id="cite_note-SFLOPS-208"><a href="#cite_ref-SFLOPS_208-0">^</a> <a href="/wiki/Single_precision_floating-point_format" class="mw-redirect" title="Single precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-PRO-213">^ <a href="#cite_ref-PRO_213-0">a</a> <a href="#cite_ref-PRO_213-1">b</a> <a href="#cite_ref-PRO_213-2">c</a> Model also available as PRO version<a href="#cite_note-224">[144]</a><a href="#cite_note-225">[145]</a><a href="#cite_note-226">[146]</a>, released April 8, 2019. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Renoir"_(2020)_2">"Renoir" (2020)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=32" title="Edit section: "Renoir" (2020)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by TSMC<a href="#cite_note-227">[147]</a><a href="#cite_note-228">[148]</a><a href="#cite_note-229">[149]</a></li> <li>Socket FP6</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 156 mm²</li> <li>9.8 billion transistors on one single 7 nm monolithic die<a href="#cite_note-Renoir-230">[150]</a></li> <li>Up to eight <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> CPU cores</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU</li> <li>Memory support: <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-4266 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li></ul> <div class="mw-heading mw-heading5"><h5 id="U">U</h5>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=33" title="Edit section: U">edit</a>]</div> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3" class="unsortable"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-231">[i]</a> </th> <th rowspan="2" class="unsortable">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">MHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-232">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-233">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="4">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11286">4980U</a> </th> <td rowspan="3">8 (16) </td> <td>2.0 </td> <td>4.4 </td> <td rowspan="8">8 MB </td> <td rowspan="4">2 × 4 </td> <td rowspan="10">Radeon Graphics<a href="#cite_note-gpumodel-234">[a]</a> </td> <td>1950 </td> <td rowspan="2">512:32:8 8 CU </td> <td>1996.8 </td> <td rowspan="10">15 W </td> <td>Apr 13, 2021 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9091">4800U</a> </th> <td>1.8 </td> <td>4.2 </td> <td>1750 </td> <td>1792 </td> <td>Mar 16, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9686">Pro 4750U</a> </th> <td>1.7 </td> <td rowspan="2">4.1 </td> <td rowspan="2">1600 </td> <td rowspan="3">448:28:8 7 CU </td> <td rowspan="2">1433.6 </td> <td>May 7, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9096">4700U</a> </th> <td>8 (8) </td> <td>2.0 </td> <td>Mar 16, 2020 </td></tr> <tr> <th rowspan="4">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11291">4680U</a> </th> <td rowspan="3">6 (12) </td> <td rowspan="3">2.1 </td> <td rowspan="4">4.0 </td> <td rowspan="4">2 × 3 </td> <td rowspan="4">1500 </td> <td>1344 </td> <td>Apr 13, 2021 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9691">Pro 4650U</a> </th> <td rowspan="3">384:24:8 6 CU </td> <td rowspan="3">1152 </td> <td>May 7, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9116">4600U</a> </th> <td rowspan="2">Mar 16, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9101">4500U</a> </th> <td>6 (6) </td> <td>2.3 </td></tr> <tr> <th rowspan="2">Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9696">Pro 4450U</a> </th> <td>4 (8) </td> <td>2.5 </td> <td rowspan="2">3.7 </td> <td rowspan="2">4 MB </td> <td rowspan="2">1 × 4 </td> <td rowspan="2">1400 </td> <td rowspan="2">320:20:8 5 CU </td> <td rowspan="2">896 </td> <td>May 7, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9106">4300U</a> </th> <td>4 (4) </td> <td>2.7 </td> <td>Mar 16, 2020 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Mobile_4000U_series" title="Template:AMD Ryzen Mobile 4000U series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Mobile_4000U_series" title="Template talk:AMD Ryzen Mobile 4000U series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Mobile_4000U_series" title="Special:EditPage/Template:AMD Ryzen Mobile 4000U series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-234"><a href="#cite_ref-gpumodel_234-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-231"><a href="#cite_ref-coreconfig_231-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-232"><a href="#cite_ref-gpuconfig_232-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-233"><a href="#cite_ref-SFLOPS_233-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading5"><h5 id="H">H</h5>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=34" title="Edit section: H">edit</a>]</div> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3" class="unsortable">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2" class="unsortable"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-235">[i]</a> </th> <th rowspan="2" class="unsortable">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">MHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-236">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-237">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="2">Ryzen 9 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9651">4900H</a> </th> <td rowspan="4">8 (16) </td> <td>3.3 </td> <td>4.4 </td> <td rowspan="6">8 MB </td> <td rowspan="4">2 × 4 </td> <td rowspan="6">Radeon Graphics<a href="#cite_note-gpumodel-238">[a]</a> </td> <td rowspan="2">1750 </td> <td rowspan="2">512:32:8 8 CU </td> <td rowspan="2">1792 </td> <td>45 W </td> <td rowspan="6">Mar 16, 2020 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9206">4900HS</a> </th> <td>3.0 </td> <td>4.3 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9081">4800H</a> </th> <td rowspan="2">2.9 </td> <td rowspan="2">4.2 </td> <td rowspan="2">1600 </td> <td rowspan="2">448:28:8 7 CU </td> <td rowspan="2">1433.6 </td> <td rowspan="3">45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10511">4800HS</a> </th></tr> <tr> <th rowspan="2">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9086">4600H</a> </th> <td rowspan="2">6 (12) </td> <td rowspan="2">3.0 </td> <td rowspan="2">4.0 </td> <td rowspan="2">2 × 3 </td> <td rowspan="2">1500 </td> <td rowspan="2">384:24:8 6 CU </td> <td rowspan="2">1152 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1">4600HS<a href="#cite_note-239">[151]</a><a href="#cite_note-240">[152]</a><a href="#cite_note-241">[153]</a> </th> <td>35 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Mobile_4000H_series" title="Template:AMD Ryzen Mobile 4000H series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Mobile_4000H_series" title="Template talk:AMD Ryzen Mobile 4000H series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Mobile_4000H_series" title="Special:EditPage/Template:AMD Ryzen Mobile 4000H series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-238"><a href="#cite_ref-gpumodel_238-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-235"><a href="#cite_ref-coreconfig_235-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-236"><a href="#cite_ref-gpuconfig_236-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-237"><a href="#cite_ref-SFLOPS_237-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Lucienne"_(2021)">"Lucienne" (2021)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=35" title="Edit section: "Lucienne" (2021)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by TSMC</li> <li>Socket FP6</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 156 mm²</li> <li>9.8 billion transistors on one single 7 nm monolithic die[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>]</li> <li>Up to eight <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> CPU cores</li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU (7 nm Vega)</li></ul> Common features of Ryzen 5000 notebook APUs: <ul><li>Socket: FP6.</li> <li>All the CPUs support <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-4266 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li> <li>Includes integrated <a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5th generation</a> GPU.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">7FF</a>.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and Model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_Cache" class="mw-redirect" title="CPU Cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-242">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-243">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-244">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th>Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10846">5700U</a> </th> <td>8 (16) </td> <td>1.8 </td> <td>4.3 </td> <td rowspan="2">8 MB </td> <td>2 × 4 </td> <td rowspan="3">Radeon Graphics <a href="#cite_note-gpumodel-245">[a]</a> </td> <td>1.9 </td> <td>512:32:8 8 CU </td> <td>1945.6 </td> <td rowspan="3">10–25 W </td> <td rowspan="3">Jan 12, 2021 </td></tr> <tr> <th>Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10856">5500U</a><a href="#cite_note-246">[154]</a> </th> <td>6 (12) </td> <td>2.1 </td> <td>4.0 </td> <td>2 × 3 </td> <td>1.8 </td> <td>448:28:8 7 CU </td> <td>1612.8 </td></tr> <tr> <th>Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10861">5300U</a> </th> <td>4 (8) </td> <td>2.6 </td> <td>3.8 </td> <td>4 MB </td> <td>1 × 4 </td> <td>1.5 </td> <td>384:24:8 6 CU </td> <td>1152 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Mobile_5000_Zen_2_based_series" title="Template:AMD Ryzen Mobile 5000 Zen 2 based series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Mobile_5000_Zen_2_based_series" title="Template talk:AMD Ryzen Mobile 5000 Zen 2 based series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Mobile_5000_Zen_2_based_series" title="Special:EditPage/Template:AMD Ryzen Mobile 5000 Zen 2 based series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-242"><a href="#cite_ref-coreconfig_242-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-243"><a href="#cite_ref-gpuconfig_243-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-244"><a href="#cite_ref-SFLOPS_244-0">^</a> <a href="/wiki/Single_precision_floating-point_format" class="mw-redirect" title="Single precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-245"><a href="#cite_ref-gpumodel_245-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Cezanne"_(2021)_2">"Cezanne" (2021)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=36" title="Edit section: "Cezanne" (2021)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by TSMC</li> <li>Socket FP6</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 180 mm²</li> <li>Up to eight <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> CPU cores</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU</li> <li>Memory support: <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-4266 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li></ul> <div class="mw-heading mw-heading5"><h5 id="U_2">U</h5>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=37" title="Edit section: U">edit</a>]</div> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-247">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-248">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-249">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th>Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku4">5800U<a href="#cite_note-PRO-250">[note 1]</a><a href="#cite_note-251">[155]</a> </th> <td>8 (16) </td> <td>1.9 </td> <td>4.4 </td> <td rowspan="2">16 MB </td> <td>1 × 8 </td> <td rowspan="4">Radeon Graphics<a href="#cite_note-gpumodel-252">[a]</a> </td> <td>2.0 </td> <td>512:32:8 8 <abbr title="Compute Unit">CU</abbr>s </td> <td>2048 </td> <td rowspan="4">10–25 W </td> <td rowspan="4">Jan 12, 2021 </td></tr> <tr> <th rowspan="2">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku3">5600U<a href="#cite_note-PRO-250">[note 1]</a><a href="#cite_note-253">[156]</a> </th> <td rowspan="2">6 (12) </td> <td rowspan="2">2.3 </td> <td>4.2 </td> <td rowspan="2">1 × 6 </td> <td>1.8 </td> <td>448:28:8 7 <abbr title="Compute Unit">CU</abbr>s </td> <td>1612.8 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2">5560U<a href="#cite_note-254">[157]</a> </th> <td>4.0 </td> <td rowspan="2">8 MB </td> <td rowspan="2">1.6 </td> <td rowspan="2">384:24:8 6 <abbr title="Compute Unit">CU</abbr>s </td> <td rowspan="2">1228.8 </td></tr> <tr> <th>Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku1">5400U<a href="#cite_note-PRO-250">[note 1]</a><a href="#cite_note-255">[158]</a><a href="#cite_note-256">[159]</a> </th> <td>4 (8) </td> <td>2.7 </td> <td>4.1 </td> <td>1 × 4 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Cezanne_U" title="Template:AMD Cezanne U"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Cezanne_U" title="Template talk:AMD Cezanne U"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Cezanne_U" title="Special:EditPage/Template:AMD Cezanne U"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-252"><a href="#cite_ref-gpumodel_252-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-247"><a href="#cite_ref-coreconfig_247-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-248"><a href="#cite_ref-gpuconfig_248-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-249"><a href="#cite_ref-SFLOPS_249-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="cite-bracket" style="column-width: <ol class="references"> <li id="cite_note-PRO-250">^ <a href="#cite_ref-PRO_250-0">a</a> <a href="#cite_ref-PRO_250-1">b</a> <a href="#cite_ref-PRO_250-2">c</a> <a href="#cite_ref-PRO_250-3">d</a> Model also available as Pro version as 5450U,<a href="#cite_note-257">[160]</a> 5650U,<a href="#cite_note-258">[161]</a> 5850U,<a href="#cite_note-259">[162]</a> released on March 16, 2021. </li> </ol></div> <div class="mw-heading mw-heading5"><h5 id="H_2">H</h5>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=38" title="Edit section: H">edit</a>]</div> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-260">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-261">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-262">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="4">Ryzen 9 </th> <th style="text-align:left;" data-sort-value="sku8">5980HX<a href="#cite_note-263">[163]</a> </th> <td rowspan="6">8 (16) </td> <td>3.3 </td> <td rowspan="2">4.8 </td> <td rowspan="8">16 MB </td> <td rowspan="6">1 × 8 </td> <td rowspan="8">Radeon Graphics<a href="#cite_note-gpumodel-264">[a]</a> </td> <td rowspan="4">2.1 </td> <td rowspan="6">512:32:8 8 <abbr title="Compute Unit">CU</abbr>s </td> <td rowspan="4">2150.4 </td> <td>35–54 W </td> <td rowspan="8">Jan 12, 2021 </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7">5980HS<a href="#cite_note-265">[164]</a> </th> <td>3.0 </td> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku6">5900HX<a href="#cite_note-266">[165]</a> </th> <td>3.3 </td> <td rowspan="2">4.6 </td> <td>35–54 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5">5900HS<a href="#cite_note-267">[166]</a> </th> <td>3.0 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku4">5800H<a href="#cite_note-268">[167]</a><a href="#cite_note-269">[168]</a> </th> <td>3.2 </td> <td rowspan="2">4.4 </td> <td rowspan="2">2.0 </td> <td rowspan="2">2048 </td> <td>35–54 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku3">5800HS<a href="#cite_note-270">[169]</a> </th> <td>2.8 </td> <td>35 W </td></tr> <tr> <th rowspan="2">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku2">5600H<a href="#cite_note-271">[170]</a><a href="#cite_note-272">[171]</a> </th> <td rowspan="2">6 (12) </td> <td>3.3 </td> <td rowspan="2">4.2 </td> <td rowspan="2">1 × 6 </td> <td rowspan="2">1.8 </td> <td rowspan="2">448:28:8 7 <abbr title="Compute Unit">CU</abbr>s </td> <td rowspan="2">1612.8 </td> <td>35–54 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1">5600HS<a href="#cite_note-273">[172]</a> </th> <td>3.0 </td> <td>35 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Cezanne_H" title="Template:AMD Cezanne H"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Cezanne_H" title="Template talk:AMD Cezanne H"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Cezanne_H" title="Special:EditPage/Template:AMD Cezanne H"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-264"><a href="#cite_ref-gpumodel_264-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-260"><a href="#cite_ref-coreconfig_260-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-261"><a href="#cite_ref-gpuconfig_261-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-262"><a href="#cite_ref-SFLOPS_262-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Barceló"_(2022)">"Barceló" (2022)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=39" title="Edit section: "Barceló" (2022)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by TSMC</li> <li>Socket FP6</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 180 mm²</li> <li>Up to eight <a href="/wiki/Zen_3" title="Zen 3">Zen 3</a> CPU cores</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>Fifth generation <a href="/wiki/GCN_5" class="mw-redirect" title="GCN 5">GCN</a>-based GPU</li> <li>Memory support: <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a>-3200 or <a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a>-4266 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">Threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-274">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-275">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-276">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th>Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku3">5825U<a href="#cite_note-PRO-277">[note 1]</a><a href="#cite_note-Chrome-278">[note 2]</a><a href="#cite_note-279">[173]</a> </th> <td>8 (16) </td> <td>2.0 </td> <td>4.5 </td> <td rowspan="2">16 MB </td> <td>1 × 8 </td> <td rowspan="3">Radeon Graphics<a href="#cite_note-gpumodel-280">[a]</a> </td> <td>2.0 </td> <td>512:32:8 8 <abbr title="Compute Unit">CU</abbr>s </td> <td>2048 </td> <td rowspan="3">15 W </td> <td rowspan="2">Jan 4, 2022 </td></tr> <tr> <th>Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku2">5625U<a href="#cite_note-PRO-277">[note 1]</a><a href="#cite_note-Chrome-278">[note 2]</a><a href="#cite_note-281">[174]</a> </th> <td>6 (12) </td> <td>2.3 </td> <td>4.3 </td> <td>1 × 6 </td> <td>1.8 </td> <td>448:28:8 7 <abbr title="Compute Unit">CU</abbr>s </td> <td>1612.8 </td></tr> <tr> <th>Ryzen 3 </th> <th style="text-align:left;" data-sort-value="sku1">5125C<a href="#cite_note-282">[175]</a> </th> <td>2 (4) </td> <td>3.0 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>8 MB </td> <td>1 × 2 </td> <td>? </td> <td>192:12:8 3 CU </td> <td>? </td> <td>May 5, 2022 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Barcel%C3%B3" title="Template:AMD Barceló"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Barcel%C3%B3" title="Template talk:AMD Barceló"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Barcel%C3%B3" title="Special:EditPage/Template:AMD Barceló"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-gpumodel-280"><a href="#cite_ref-gpumodel_280-0">^</a> All of the iGPUs are branded as AMD Radeon Graphics. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-274"><a href="#cite_ref-coreconfig_274-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-275"><a href="#cite_ref-gpuconfig_275-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-276"><a href="#cite_ref-SFLOPS_276-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="cite-bracket" style="column-width: <ol class="references"> <li id="cite_note-PRO-277">^ <a href="#cite_ref-PRO_277-0">a</a> <a href="#cite_ref-PRO_277-1">b</a> <a href="#cite_ref-PRO_277-2">c</a> Model also available as Pro version as 5475U,<a href="#cite_note-283">[176]</a> 5675U,<a href="#cite_note-284">[177]</a> 5875U,<a href="#cite_note-285">[178]</a> released on April 19, 2022. </li> <li id="cite_note-Chrome-278">^ <a href="#cite_ref-Chrome_278-0">a</a> <a href="#cite_ref-Chrome_278-1">b</a> <a href="#cite_ref-Chrome_278-2">c</a> Model also available as Chromebook optimized version as 5425C,<a href="#cite_note-286">[179]</a> 5625C,<a href="#cite_note-287">[180]</a> 5825C,<a href="#cite_note-288">[181]</a> released on May 5, 2022. </li> </ol></div> <div class="mw-heading mw-heading4"><h4 id=""Rembrandt"_(2022)">"Rembrandt" (2022)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=40" title="Edit section: "Rembrandt" (2022)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 6 nm by TSMC</li> <li>Socket FP7</li> <li><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> size: 210 mm²</li> <li>Up to eight <a href="/wiki/Zen_3" title="Zen 3">Zen 3+</a> CPU cores</li> <li>Second generation <a href="/wiki/RDNA_2" title="RDNA 2">RDNA</a>-based GPU</li></ul> Common features of Ryzen 6000 notebook APUs: <ul><li>Socket: FP7, FP7r2.</li> <li>All the CPUs support <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a>-4800 or <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-6400 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 16 <a href="/wiki/PCI_Express#PCI_Express_4.0" title="PCI Express">PCIe 4.0</a> lanes.</li> <li>Native USB 4 (40Gbps) Ports: 2</li> <li>Native USB 3.2 Gen 2 (10Gbps) Ports: 2</li> <li>Includes integrated <a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> GPU.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm_process" title="7 nm process">N6</a> FinFET.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_cache" title="CPU cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-coreconfig-289">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th rowspan="2">Config<a href="#cite_note-gpuconfig-290">[ii]</a> </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-291">[iii]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th rowspan="4">Ryzen 9 </th> <th style="text-align:left;" data-sort-value="sku10"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11531">6980HX</a> </th> <td rowspan="7">8 (16) </td> <td rowspan="4">3.3 </td> <td rowspan="2">5.0 </td> <td rowspan="10">16 MB </td> <td rowspan="7">1 × 8 </td> <td rowspan="7">680M </td> <td rowspan="4">2.4 </td> <td rowspan="7">768:48:8 12 CUs </td> <td rowspan="4">3686.4 </td> <td>45 W </td> <td rowspan="10">Jan 4, 2022 <a href="#cite_note-292">[182]</a> </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku9"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11536">6980HS</a> </th> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku8"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11541">6900HX</a><a href="#cite_note-PRO-293">[a]</a> </th> <td rowspan="2">4.9 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku7"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11561">6900HS</a><a href="#cite_note-PRO-293">[a]</a> </th> <td>35 W </td></tr> <tr> <th rowspan="3">Ryzen 7 </th> <th style="text-align:left;" data-sort-value="sku6"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11546">6800H</a><a href="#cite_note-PRO-293">[a]</a> </th> <td rowspan="2">3.2 </td> <td rowspan="3">4.7 </td> <td rowspan="3">2.2 </td> <td rowspan="3">3379.2 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku5"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11581">6800HS</a><a href="#cite_note-PRO-293">[a]</a> </th> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku4"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11591">6800U</a><a href="#cite_note-PRO-293">[a]</a> </th> <td>2.7 </td> <td>15–28 W </td></tr> <tr> <th rowspan="3">Ryzen 5 </th> <th style="text-align:left;" data-sort-value="sku3"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11551">6600H</a><a href="#cite_note-PRO-293">[a]</a> </th> <td rowspan="3">6 (12) </td> <td rowspan="2">3.3 </td> <td rowspan="3">4.5 </td> <td rowspan="3">1 × 6 </td> <td rowspan="3">660M </td> <td rowspan="3">1.9 </td> <td rowspan="3">384:24:8 6 CUs </td> <td rowspan="3">1459.2 </td> <td>45 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku2"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11586">6600HS</a><a href="#cite_note-PRO-293">[a]</a> </th> <td>35 W </td></tr> <tr> <th style="text-align:left;" data-sort-value="sku1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11596">6600U</a><a href="#cite_note-PRO-293">[a]</a> </th> <td>2.9 </td> <td>15–28 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Mobile_6000_series" title="Template:AMD Ryzen Mobile 6000 series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Mobile_6000_series" title="Template talk:AMD Ryzen Mobile 6000 series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Mobile_6000_series" title="Special:EditPage/Template:AMD Ryzen Mobile 6000 series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-coreconfig-289"><a href="#cite_ref-coreconfig_289-0">^</a> Core Complexes (CCX) × cores per CCX </li> <li id="cite_note-gpuconfig-290"><a href="#cite_ref-gpuconfig_290-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">compute units</a> (CU) </li> <li id="cite_note-SFLOPS-291"><a href="#cite_ref-SFLOPS_291-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-PRO-293">^ <a href="#cite_ref-PRO_293-0">a</a> <a href="#cite_ref-PRO_293-1">b</a> <a href="#cite_ref-PRO_293-2">c</a> <a href="#cite_ref-PRO_293-3">d</a> <a href="#cite_ref-PRO_293-4">e</a> <a href="#cite_ref-PRO_293-5">f</a> <a href="#cite_ref-PRO_293-6">g</a> <a href="#cite_ref-PRO_293-7">h</a> Model also available as PRO version (6650U<a href="#cite_note-294">[183]</a>, 6650H<a href="#cite_note-295">[184]</a>, 6650HS<a href="#cite_note-296">[185]</a>, 6850U<a href="#cite_note-297">[186]</a>, 6850H<a href="#cite_note-298">[187]</a>, 6850HS<a href="#cite_note-299">[188]</a>, 6950H<a href="#cite_note-300">[189]</a>, 6950HS<a href="#cite_note-301">[190]</a>), released on April 19, 2022. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Phoenix"_(2023)">"Phoenix" (2023)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=41" title="Edit section: "Phoenix" (2023)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 4 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Up to eight <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> CPU cores</li> <li>Dual-channel <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> or <a href="/w/index.php?title=LPDDR5x&action=edit&redlink=1" class="new" title="LPDDR5x (page does not exist)">LPDDR5x</a> memory controller</li> <li><a href="/wiki/RDNA3" class="mw-redirect" title="RDNA3">RDNA3</a> iGPU</li> <li><a href="/w/index.php?title=Xilinx_XDNA&action=edit&redlink=1" class="new" title="Xilinx XDNA (page does not exist)">XDNA</a> accelerator</li></ul> <div class="mw-heading mw-heading4"><h4 id=""Dragon_Range"_(2023)">"Dragon Range" (2023)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=42" title="Edit section: "Dragon Range" (2023)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 5 nm (CCD) and 6 nm (cIOD) by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Up to sixteen <a href="/wiki/Zen_4" title="Zen 4">Zen 4</a> CPU cores</li> <li>Dual-channel <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a> memory controller</li> <li>Basic <a href="/wiki/RDNA2" class="mw-redirect" title="RDNA2">RDNA2</a> iGPU</li></ul> <div class="mw-heading mw-heading2"><h2 id="Ultra-mobile_APUs">Ultra-mobile APUs</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=43" title="Edit section: Ultra-mobile APUs">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="Brazos:_"Desna",_"Ontario",_"Zacate"_(2011)">Brazos: "Desna", "Ontario", "Zacate" (2011)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=44" title="Edit section: Brazos: "Desna", "Ontario", "Zacate" (2011)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 40 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Socket FT1 (BGA-413)</li> <li>Based on the <a href="/wiki/Bobcat_(processor)" class="mw-redirect" title="Bobcat (processor)">Bobcat microarchitecture</a><a href="#cite_note-AMD_Brazos_Platform_Preview-302">[191]</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li> <li><a href="/wiki/PowerNow!" title="PowerNow!">PowerNow!</a></li> <li><a href="/wiki/DirectX_11" class="mw-redirect" title="DirectX 11">DirectX 11</a> integrated graphics with <a href="/wiki/Unified_Video_Decoder#UVD_3" title="Unified Video Decoder">UVD 3.0</a></li> <li>Z-series denote Desna; C-series denote Ontario; and the E-series denotes Zacate</li> <li>2.50 GT/s UMI (PCIe 1.0 ×4)</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="5">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-303">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-304">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122326/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=55">Z-01</a> </th> <td>June 1, 2011 </td> <td rowspan="10">40 nm </td> <td rowspan="4">B0 </td> <td>2 (2) </td> <td>1.0 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="10">32KB inst. 32KB data per core </td> <td>2× 512KB </td> <td rowspan="4"><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> </td> <td rowspan="10">80:8:4 </td> <td rowspan="5">276 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="5">44.1 </td> <td rowspan="5">1066 </td> <td>5.9 </td> <td>XMZ01AFVB22GV </td></tr> <tr> <th colspan="2"></th> <th colspan="2"></th> <th></th> <th colspan="2"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095918/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=3">C-30</a> </th> <td rowspan="2">January 4, 2011 </td> <td>1 (1) </td> <td>1.2 </td> <td>512KB </td> <td rowspan="3">9 </td> <td>CMC30AFPB12GT </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110906045550/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=4">C-50</a> </th> <td rowspan="2">2 (2) </td> <td rowspan="2">1.0 </td> <td rowspan="2">2× 512KB </td> <td>CMC50AFPB22GT </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">C-60 </th> <td>August 22, 2011 </td> <td>C0 </td> <td>1.33 </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6290</a> </td> <td>400 </td> <td>CMC60AFPB22GV </td></tr> <tr> <th colspan="2"> </th> <th colspan="4"></th> <th></th> <th></th> <th colspan="6"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122038/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=2">E-240</a> </th> <td>January 4, 2011 </td> <td rowspan="3">B0 </td> <td>1 (1) </td> <td>1.5 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>512KB </td> <td rowspan="3"><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6310</a> </td> <td>500 </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>80 </td> <td rowspan="3">1066 </td> <td rowspan="4">18 </td> <td>EME240GBB12GT </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122001/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=22">E-300</a> </th> <td>August 22, 2011 </td> <td rowspan="3">2 (2) </td> <td>1.3 </td> <td rowspan="3">2× 512KB </td> <td>488 </td> <td>78 </td> <td>EME300GBB22GV </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110424032501/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=1">E-350</a> </th> <td>January 4, 2011 </td> <td>1.6 </td> <td>492 </td> <td>78.7 </td> <td>EME350GBB22GT </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20120207142240/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=21">E-450</a> </th> <td>August 22, 2011 </td> <td>B0 C0 </td> <td>1.65 </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6320</a> </td> <td>508 </td> <td>600 </td> <td>81.2 </td> <td>1333 </td> <td>EME450GBB22GV </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-303"><a href="#cite_ref-kib_303-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-304"><a href="#cite_ref-SFLOPS_304-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Brazos_2.0:_"Ontario",_"Zacate"_(2012)">Brazos 2.0: "Ontario", "Zacate" (2012)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=45" title="Edit section: Brazos 2.0: "Ontario", "Zacate" (2012)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 40 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Socket FT1 (BGA-413)</li> <li>Based on the <a href="/wiki/Bobcat_(processor)" class="mw-redirect" title="Bobcat (processor)">Bobcat microarchitecture</a><a href="#cite_note-AMD_Brazos_Platform_Preview-302">[191]</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li> <li>PowerNow!</li> <li>DirectX 11 integrated graphics</li> <li>C-series denote Ontario; and the E-series denotes Zacate</li> <li>2.50 GT/s UMI (PCIe 1.0 ×4)</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="6">CPU </th> <th colspan="5">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-305">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-306">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122248/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=61">C-70</a> </th> <td>September 15, 2012 </td> <td rowspan="6">40 nm </td> <td>C0 </td> <td rowspan="6">2 (2) </td> <td>1.0 </td> <td>1.33 </td> <td rowspan="6">32 KB inst. 32 KB data per core </td> <td rowspan="6">2× 512KB </td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>HD 7290 </td> <td rowspan="6">80:8:4 </td> <td>276 </td> <td>400 </td> <td>44.1 </td> <td>1066 </td> <td>9 </td> <td>CMC70AFPB22GV </td></tr> <tr> <th colspan="2"> </th> <th></th> <th colspan="2"></th> <th></th> <th></th> <th colspan="6"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907121909/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=40">E1-1200</a> </th> <td>June 6, 2012 </td> <td rowspan="4">C0 </td> <td>1.4 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">HD 7310 </td> <td>500 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>80 </td> <td rowspan="2">1066 </td> <td rowspan="4">18 </td> <td>EM1200GBB22GV </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">E1-1500 </th> <td>January 7, 2013 </td> <td>1.48 </td> <td>529 </td> <td>84.6 </td> <td> </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131029023350/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=39">E2-1800</a> </th> <td>June 6, 2012 </td> <td>1.7 </td> <td rowspan="2">HD 7340 </td> <td>523 </td> <td>680 </td> <td>83.6 </td> <td rowspan="2">1333 </td> <td>EM1800GBB22GV </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">E2-2000 </th> <td>January 7, 2013 </td> <td>1.75 </td> <td>538 </td> <td>700 </td> <td>86 </td> <td> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-305"><a href="#cite_ref-kib_305-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-306"><a href="#cite_ref-SFLOPS_306-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="Brazos-T:_"Hondo"_(2012)">Brazos-T: "Hondo" (2012)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=46" title="Edit section: Brazos-T: "Hondo" (2012)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 40 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Socket FT1 (BGA-413)</li> <li>Based on the <a href="/wiki/Bobcat_(processor)" class="mw-redirect" title="Bobcat (processor)">Bobcat microarchitecture</a><a href="#cite_note-AMD_Brazos_Platform_Preview-302">[191]</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li>Found in tablet computers</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li> <li>PowerNow!</li> <li>DirectX 11 integrated graphics</li> <li>2.50 GT/s UMI (PCIe 1.0 ×4)</li></ul> <table class="wikitable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-307">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-308">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100151/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=56">Z-60</a> </th> <td>October 9, 2012 </td> <td>40 nm </td> <td>C0 </td> <td>2 (2) </td> <td>1.0 </td> <td>32KB inst. 32KB data per core </td> <td>2× 512 KB </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> </td> <td>80:8:4 </td> <td>276 </td> <td>44.1 </td> <td>1066 </td> <td>4.5 </td> <td>XMZ60AFVB22GV </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-307"><a href="#cite_ref-kib_307-0">^</a> AMD in its technical documentation uses KB, which it defines as "kilobyte" and as equal to 1024 B (i.e., 1 <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KiB</a>), and MB, which it defines as "megabyte" and as equal to 1024 KB (1 MiB).<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-308"><a href="#cite_ref-SFLOPS_308-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Kabini",_"Temash"_(2013)">"Kabini", "Temash" (2013)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=47" title="Edit section: "Kabini", "Temash" (2013)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Socket FT3 (BGA)</li> <li>2 to 4 CPU Cores (<a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar (microarchitecture)</a>)</li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>Turbo Dock Technology, C6 and CC6 low power states</li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN)</li> <li><a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">AMD Eyefinity</a> multi-monitor for up to two displays</li></ul> <div class="mw-heading mw-heading4"><h4 id="Temash,_Elite_Mobility_APU">Temash, Elite Mobility APU</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=48" title="Edit section: Temash, Elite Mobility APU">edit</a>]</div> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3L Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-309">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907095801/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=87">A4-1200</a> </th> <td rowspan="4">May 23, 2013 </td> <td rowspan="4">28 nm </td> <td rowspan="4">KB-A1 </td> <td rowspan="2">2 (2) </td> <td rowspan="4">1.0 </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="4">32 KB inst. 32 KB data per core </td> <td rowspan="2">1 </td> <td>HD 8180 </td> <td rowspan="4">128:8:4 2 CU </td> <td>225 </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1066 </td> <td>4 </td> <td>AT1200IFJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907122328/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=86">A4-1250</a> </th> <td rowspan="2">HD 8210 </td> <td rowspan="3">300 </td> <td>1333 </td> <td rowspan="3">8 </td> <td>AT1250IDJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150620124214/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=96">A4-1350</a> </th> <td rowspan="2">4 (4) </td> <td rowspan="2">2 </td> <td rowspan="2">1066 </td> <td>AT1350IDJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20140907100154/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=85">A6-1450</a> </th> <td>1.4 </td> <td>HD 8250 </td> <td>400 </td> <td>AT1450IDJ44HM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-309"><a href="#cite_ref-kib_309-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Kabini,_Mainstream_APU">Kabini, Mainstream APU</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=49" title="Edit section: Kabini, Mainstream APU">edit</a>]</div> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="3">GPU </th> <th rowspan="3">DDR3L Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-310">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2100-with-Radeon%E2%84%A2-HD-8210/91">E1-2100</a> </th> <td>May 2013 </td> <td rowspan="9">28 nm </td> <td rowspan="9">KB-A1 </td> <td rowspan="4">2 (2) </td> <td>1.0 </td> <td rowspan="9">32KB inst. 32KB data per core </td> <td rowspan="4">1 </td> <td rowspan="9" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="2">HD 8210 </td> <td rowspan="9">128:8:4 2 CU </td> <td rowspan="2">300 </td> <td rowspan="3">1333 </td> <td rowspan="2">9 </td> <td>EM2100ICJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2200-with-Radeon%E2%84%A2-HD-8210/92">E1-2200</a> </th> <td>Feb 2014 </td> <td>1.05 </td> <td>EM2200ICJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-2500-with-Radeon%E2%84%A2-HD-8240/93">E1-2500</a> </th> <td rowspan="2">May 2013 </td> <td>1.4 </td> <td>HD 8240 </td> <td>400 </td> <td rowspan="5">15 </td> <td>EM2500IBJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-3000-with-Radeon%E2%84%A2-HD-8280/100">E2-3000</a> </th> <td>1.65 </td> <td rowspan="2">HD 8280 </td> <td rowspan="2">450 </td> <td rowspan="6">1600 </td> <td>EM3000IBJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-3800-with-Radeon%E2%84%A2-HD-8280/96">E2-3800</a> </th> <td>Feb 2014 </td> <td rowspan="5">4 </td> <td>1.3 </td> <td rowspan="5">2 </td> <td>EM3800IBJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-5000-with-Radeon%E2%84%A2-HD-8330/40">A4-5000</a> </th> <td>May 2013 </td> <td>1.5 </td> <td rowspan="2">HD 8330 </td> <td rowspan="2">497 </td> <td>AM5000IBJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-5100-with-Radeon%E2%84%A2-HD-8330/33">A4-5100</a> </th> <td>Feb 2014 </td> <td>1.55 </td> <td>AM5100IBJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Desktops/A6-5200-with-Radeon%E2%84%A2-HD-8400/41">A6-5200</a> </th> <td>May 2013 </td> <td>2.0 </td> <td>HD 8400 </td> <td>600 </td> <td rowspan="2">25 </td> <td>AM5200IAJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Laptops/A4-PRO-3340B-with-Radeon%E2%84%A2-HD-8240-Graphics/154">A4 Pro-3340B</a> </th> <td>Nov 2014 </td> <td>2.2 </td> <td>HD 8240 </td> <td>400 </td> <td>AM334BIAJ44HM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-310"><a href="#cite_ref-kib_310-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Beema",_"Mullins"_(2014)">"Beema", "Mullins" (2014)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=50" title="Edit section: "Beema", "Mullins" (2014)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket <a href="/wiki/Socket_FT3" title="Socket FT3">FT3b</a> (BGA)</li> <li>CPU: 2 to 4 (<a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma cores</a>) <ul><li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li></ul></li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN)</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>Intelligent Turbo Boost</li> <li>Platform Security Processor, with an integrated <a href="/wiki/ARM_Cortex-A5" title="ARM Cortex-A5">ARM Cortex-A5</a> for <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> execution</li></ul> <div class="mw-heading mw-heading4"><h4 id="Mullins,_Tablet/2-in-1_APU">Mullins, Tablet/2-in-1 APU</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=51" title="Edit section: Mullins, Tablet/2-in-1 APU">edit</a>]</div> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3L Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-311">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150623145036/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=111">E1 Micro-6200T</a> </th> <td rowspan="3">Q2 2014 </td> <td rowspan="3">28 nm </td> <td rowspan="3">ML-A1 </td> <td>2 (2) </td> <td rowspan="2">1.0 </td> <td>1.4 </td> <td rowspan="3">32 KB inst. 32 KB data per core </td> <td>1 </td> <td rowspan="3" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>R2 </td> <td rowspan="3">128:8:4 2 CU </td> <td>300 </td> <td>600 </td> <td>1066 </td> <td>3.95 </td> <td>EM620TIWJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150623142121/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=110">A4 Micro-6400T</a> </th> <td rowspan="2">4 (4) </td> <td>1.6 </td> <td rowspan="2">2 </td> <td>R3 </td> <td>350 </td> <td>686 </td> <td rowspan="2">1333 </td> <td rowspan="2">4.5 </td> <td>AM640TIVJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150623162603/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=109">A10 Micro-6700T</a> </th> <td>1.2 </td> <td>2.2 </td> <td>R6 </td> <td>500 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>AM670TIVJ44JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-311"><a href="#cite_ref-kib_311-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="Beema,_Notebook_APU">Beema, Notebook APU</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=52" title="Edit section: Beema, Notebook APU">edit</a>]</div> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">[FPUs]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-312">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-6010-with-Radeon%E2%84%A2-R2-Graphics/94">E1-6010</a> </th> <td>Q2 2014 </td> <td rowspan="7">28 nm </td> <td rowspan="7">ML-A1 </td> <td rowspan="2">2 (2) </td> <td>1.35 </td> <td rowspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="7">32 KB inst. 32 KB data per core </td> <td rowspan="2">1 </td> <td rowspan="7" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">R2 </td> <td rowspan="7">128:8:4 2 CU </td> <td rowspan="3">300 </td> <td rowspan="3">600 </td> <td rowspan="2">(L)1333 </td> <td rowspan="2">10 </td> <td>EM6010IUJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">E1-6015<a href="#cite_note-313">[192]</a> </th> <td>Q2 2015 </td> <td>1.4 </td> <td> </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20150623144907/http://products.amd.com/en-us/NotebookAPUDetail.aspx?id=114">E2-6110</a> </th> <td rowspan="5">Q2 2014 </td> <td rowspan="5">4 (4) </td> <td>1.5 </td> <td rowspan="5">2 </td> <td rowspan="3">(L)1600 </td> <td rowspan="2">15 </td> <td>EM6110ITJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-6210-with-Radeon%E2%84%A2-R3-Graphics/36">A4-6210</a> </th> <td>1.8 </td> <td rowspan="2">R3 </td> <td rowspan="2">350 </td> <td rowspan="2">686 </td> <td>AM6210ITJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">A4-6250J<a href="#cite_note-314">[193]</a> </th> <td>2.0 </td> <td>25 </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-6310-with-Radeon%E2%84%A2-R4-Graphics/53">A6-6310</a> </th> <td>1.8 </td> <td rowspan="2">2.4 </td> <td>R4 </td> <td rowspan="2">300 </td> <td rowspan="2">800 </td> <td rowspan="2">(L)1866 </td> <td rowspan="2">15 </td> <td>AM6310ITJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A8-Series-APU-for-Laptops/A8-6410-with-Radeon%E2%84%A2-R5-Graphics/131">A8-6410</a> </th> <td>2.0 </td> <td>R5 </td> <td>AM6410ITJ44JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-312"><a href="#cite_ref-kib_312-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Carrizo-L"_(2015)">"Carrizo-L" (2015)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=53" title="Edit section: "Carrizo-L" (2015)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket <a href="/wiki/Socket_FT3b" class="mw-redirect" title="Socket FT3b">FT3b</a> (BGA), FP4 (μBGA)<a href="#cite_note-315">[194]</a></li> <li>CPU: 2 to 4 (<a href="/wiki/Puma_(microarchitecture)#Puma+" title="Puma (microarchitecture)">Puma+ cores</a>) <ul><li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li></ul></li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN)</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>Intelligent Turbo Boost</li> <li>Platform Security Processor, with an integrated <a href="/wiki/ARM_Cortex-A5" title="ARM Cortex-A5">ARM Cortex-A5</a> for <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> execution</li> <li>All models except A8-7410 available in both laptop and all-in-one desktop versions</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">[FPUs]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-316">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock </th> <th rowspan="2">Turbo (MHz) </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E1-Series-APU-for-Laptops/E1-7010-with-Radeon%E2%84%A2-R2-Graphics/140">E1-7010</a> </th> <td rowspan="5">May 2015 </td> <td rowspan="6">28 nm </td> <td rowspan="6">ML-A1 </td> <td>2 </td> <td>1.5 </td> <td rowspan="2" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="6">32 KB inst. 32 KB data per core </td> <td>1 </td> <td>R2 </td> <td rowspan="6">128:8:4 2 CU </td> <td> </td> <td>400 </td> <td>(L)1333 </td> <td>10 </td> <td>EM7010IUJ23JB EM7010JCY23JB EM7010JCY23JBD </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/E2-7110-with-Radeon%E2%84%A2-R2-Graphics/139">E2-7110</a> </th> <td rowspan="5">4 </td> <td rowspan="2">1.8 </td> <td rowspan="5">2 </td> <td>R2 </td> <td> </td> <td>600 </td> <td rowspan="2">(L)1600 </td> <td rowspan="3">12–25 </td> <td>EM7110ITJ44JB EM7110JBY44JB EM7110JBY44JBD </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/A4-7210-with-Radeon%E2%84%A2-R3-Graphics/133">A4-7210</a> </th> <td>2.2 </td> <td>R3 </td> <td> </td> <td>686 </td> <td>AM7210ITJ44JB AM7210JBY44JBD </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/A6-7310-with-Radeon%E2%84%A2-R4-Graphics/137">A6-7310</a> </th> <td>2.0 </td> <td>2.4 </td> <td>R4 </td> <td> </td> <td>800 </td> <td rowspan="2">(L)1866 </td> <td>AM7310ITJ44JB AM7310JBY44JB AM7310JBY44JBD </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/5956">A8-7410</a> </th> <td>2.2 </td> <td>2.5 </td> <td>R5 </td> <td> </td> <td>847 </td> <td rowspan="2">15 </td> <td>AM7410JBY44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238216509"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6111">A4 PRO-3350B</a> </th> <td>May 2016 </td> <td>2.0 </td> <td>2.4 </td> <td>R4 </td> <td> </td> <td>800 </td> <td>1600 </td> <td>AM335BITJ44JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-316"><a href="#cite_ref-kib_316-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Stoney_Ridge"_(2016)">"Stoney Ridge" (2016)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=54" title="Edit section: "Stoney Ridge" (2016)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket FP4<a href="#cite_note-AMDGen7-198">[126]</a> / FT4</li> <li>2 "<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>" x86 CPU cores</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>Single-channel DDR4 memory controller</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>GPU based on <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> 3rd Generation with <a href="/wiki/VP9" title="VP9">VP9</a> decoding</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th style="text-align:left;" rowspan="3">Model number </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th colspan="5">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR4 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-317">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2"><a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a><a href="#cite_note-SFLOPS-318">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="text-align:left;">E2-9000e </th> <td>November 2016 </td> <td rowspan="22">28 nm </td> <td rowspan="22">[1]2 </td> <td>1.5 </td> <td>2.0 </td> <td rowspan="22">96 KB inst. per module 32 KB data per core </td> <td rowspan="22">1 </td> <td rowspan="3">R2 </td> <td rowspan="5">128:8:4 2 CU </td> <td rowspan="3">600 </td> <td rowspan="3">153.6 </td> <td rowspan="3">1866 </td> <td>6 </td> <td>EM900EANN23AC </td></tr> <tr> <th style="text-align:left;">E2-9000 </th> <td rowspan="2">June 2016 </td> <td>1.8 </td> <td>2.2 </td> <td>10 </td> <td>EM9000AKN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-E-Series-Processors/AMD-E2-Series-APU-for-Laptops/7th-Gen-E2-9010-APU/200">E2-9010</a> </th> <td>2.0 </td> <td>2.2 </td> <td>10–15 </td> <td>EM9010AVY23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/7th-Gen-A4-9120-APU/235">A4-9120</a> </th> <td>Q2 2017 </td> <td>2.2 </td> <td>2.5 </td> <td rowspan="2">R3 </td> <td>655 </td> <td>167.6 </td> <td rowspan="2">2133 </td> <td rowspan="2">10–15 </td> <td>AM9120AYN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A4-Series-APU-for-Laptops/7th-Gen-A4-9125-APU/268">A4-9125</a> </th> <td>Q2 2018 </td> <td>2.3 </td> <td>2.6 </td> <td>686 </td> <td>175.6 </td> <td>AM9125AYN23AC </td></tr> <tr> <th style="text-align:left"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/7th-gen-a4-9120c-apu">A4-9120C</a> </th> <td>January 6, 2019 </td> <td>1.6 </td> <td>2.4 </td> <td rowspan="6">R4 </td> <td rowspan="17">192:12:8 3 CU </td> <td rowspan="4">600 </td> <td rowspan="4">230.4 </td> <td>1866 </td> <td rowspan="2">6 </td> <td>AM912CANN23AC </td></tr> <tr> <th style="text-align:left;">A6-9200e </th> <td rowspan="2">November 2016 </td> <td>1.8 </td> <td>2.7 </td> <td rowspan="5">2133 </td> <td>AM920EANN23AC </td></tr> <tr> <th style="text-align:left;">A6-9200 </th> <td>2.0 </td> <td>2.8 </td> <td>10 </td> <td>AM9200AKN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9210-APU/199">A6-9210</a> </th> <td>June 2016 </td> <td>2.4 </td> <td>2.8 </td> <td>10–15 </td> <td>AM9210AVY23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9220-APU/234">A6-9220</a> </th> <td>Q2 2017 </td> <td>2.5 </td> <td>2.9 </td> <td>655 </td> <td>251.5 </td> <td rowspan="2">10–15 </td> <td>AM9220AYN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A6-Series-APU-for-Laptops/7th-Gen-A6-9225-APU/267">A6-9225</a> </th> <td>Q2 2018 </td> <td>2.6 </td> <td>3.0 </td> <td>686 </td> <td>263.4 </td> <td>AM9225AYN23AC </td></tr> <tr> <th style="text-align:left"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/7th-gen-a6-9220c-apu">A6-9220C</a> </th> <td>January 6, 2019 </td> <td>1.8 </td> <td>2.7 </td> <td rowspan="11">R5 </td> <td>720 </td> <td>276.4 </td> <td>1866 </td> <td>6 </td> <td>AM922CANN23AC </td></tr> <tr> <th style="text-align:left;">A9-9400 </th> <td>November 2016 </td> <td>2.4 </td> <td>3.2 </td> <td rowspan="2">800 </td> <td rowspan="2">307.2 </td> <td rowspan="4">2133 </td> <td>10 </td> <td>AM9400AKN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9410-APU/198">A9-9410</a> </th> <td>June 2016 </td> <td>2.9 </td> <td>3.5 </td> <td rowspan="3">10–25 </td> <td>AM9410AFY23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9420-APU/233">A9-9420</a> </th> <td>Q2 2017 </td> <td>3.0 </td> <td>3.6 </td> <td>847 </td> <td>325.2 </td> <td>AM9420AYN23AC </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://products.amd.com/en-us/search/APU/AMD-A-Series-Processors/AMD-A9-Series-APU-for-Laptops/7th-Gen-A9-9425-APU/266">A9-9425</a> </th> <td>Q2 2018 </td> <td>3.1 </td> <td>3.7 </td> <td>900 </td> <td>345.6 </td> <td>AM9425AYN23AC </td></tr> <tr> <th style="text-align:left;">A9-9430<a href="#cite_note-319">[195]</a> </th> <td>Q2 2017 </td> <td>3.2 </td> <td>3.5 </td> <td>847 </td> <td>325.2 </td> <td>2400 </td> <td>25 </td> <td>AD9430AJN23AC </td></tr> <tr> <th colspan="2"></th> <th colspan="2"></th> <th></th> <th colspan="4"> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A4-APU-for-Laptops/7th-Gen-AMD-PRO-A4-4350B-APU/248">Pro A4-4350B</a> </th> <td>Q1 2018 </td> <td>2.5 </td> <td>2.9 </td> <td>655 </td> <td>251.5 </td> <td rowspan="4">2133 </td> <td rowspan="4">15 </td> <td> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/7th-gen-amd-pro-a4-5350b-apu">Pro A4-5350B</a> </th> <td>Q1 2020 </td> <td rowspan="2">3.0 </td> <td rowspan="2">3.6 </td> <td rowspan="2">847 </td> <td rowspan="2">325.2 </td> <td> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://products.amd.com/en-us/search/APU/AMD-PRO-A-Series-Processors/AMD-PRO-A-Series-A6-APU-for-Laptops/7th-Gen-AMD-PRO-A6-7350B-APU/249">Pro A6-7350B</a> </th> <td>Q1 2018 </td> <td> </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/7th-gen-amd-pro-a6-8350b-apu">Pro A6-8350B</a> </th> <td>Q1 2020 </td> <td>3.1 </td> <td>3.7 </td> <td>900 </td> <td>345.6 </td> <td> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-317"><a href="#cite_ref-kib_317-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-318"><a href="#cite_ref-SFLOPS_318-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Dalí"_(2020)">"Dalí" (2020)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=55" title="Edit section: "Dalí" (2020)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket FP5</li> <li>Two <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> CPU cores</li> <li>Over 30% die size reduction over predecessor (Raven Ridge)</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual-channel RAM</li></ul> <table class="wikitable" style="font-size: 100%; text-align: center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th rowspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> lanes </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-320">[a]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-321">[b]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9901">AMD 3020e</a> </th> <td>Jan 6, 2020 </td> <td rowspan="10">14 nm </td> <td rowspan="4">2 (2) </td> <td>1.2 </td> <td>2.6 </td> <td rowspan="10">64 KB inst. 32 KB data per core </td> <td rowspan="10">512 KB per core </td> <td rowspan="10">4 MB </td> <td rowspan="10">Radeon Graphics (Vega) </td> <td>192:12:4 3 CU </td> <td>1.0 </td> <td>384 </td> <td rowspan="10">FP5 </td> <td rowspan="10">12 (8+4) </td> <td rowspan="10">DDR4-2400 <a href="/wiki/Dual-channel_architecture" class="mw-redirect" title="Dual-channel architecture">dual-channel</a> </td> <td>6 W </td> <td>YM3020C7T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10901">Athlon PRO 3045B</a> </th> <td>Q1 2021 </td> <td rowspan="3">2.3 </td> <td rowspan="3">3.2 </td> <td rowspan="3">128:8:4 2 CU </td> <td rowspan="3">1.1 </td> <td rowspan="3">281.6 </td> <td rowspan="3">15 W </td> <td>YM3045C4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9056">Athlon Silver 3050U</a> </th> <td>Jan 6, 2020 </td> <td>YM3050C4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9071">Athlon Silver 3050C</a> </th> <td>Sep 22, 2020 </td> <td>YM305CC4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9896">Athlon Silver 3050e</a> </th> <td>Jan 6, 2020 </td> <td rowspan="6">2 (4) </td> <td>1.4 </td> <td>2.8 </td> <td rowspan="6">192:12:4 3 CU<a href="#cite_note-322">[196]</a> </td> <td rowspan="4">1.0 </td> <td rowspan="4">384 </td> <td>6 W </td> <td>YM3050C7T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10896">Athlon PRO 3145B</a> </th> <td>Q1 2021 </td> <td rowspan="3">2.4 </td> <td rowspan="3">3.3 </td> <td rowspan="5">15 W </td> <td>YM3145C4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9061">Athlon Gold 3150U</a> </th> <td>Jan 6, 2020 </td> <td>YM3150C4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9076">Athlon Gold 3150C</a> </th> <td>Sep 22, 2020 </td> <td>YM315CC4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9051">Ryzen 3 3250U</a> </th> <td>Jan 6, 2020 </td> <td rowspan="2">2.6 </td> <td rowspan="2">3.5 </td> <td rowspan="2">1.2 </td> <td rowspan="2">460.8 </td> <td>YM3250C4T2OFG </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9066">Ryzen 3 3250C</a> </th> <td>Sep 22, 2020 </td> <td>YM325CC4T2OFG </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Dal%C3%AD_Mobile" title="Template:AMD Dalí Mobile"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Dal%C3%AD_Mobile" title="Template talk:AMD Dalí Mobile"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Dal%C3%AD_Mobile" title="Special:EditPage/Template:AMD Dalí Mobile"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-320"><a href="#cite_ref-cconfig_320-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units</a> (CU) </li> <li id="cite_note-SFLOPS-321"><a href="#cite_ref-SFLOPS_321-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Pollock"_(2020)">"Pollock" (2020)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=56" title="Edit section: "Pollock" (2020)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Socket FT5</li> <li>Two <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> CPU cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Single-channel RAM</li></ul> <table class="wikitable" style="font-size: 100%; text-align: center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th rowspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> lanes </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-323">[a]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-324">[b]</a> </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10166">AMD 3015e</a> </th> <td>Jul 6, 2020 </td> <td rowspan="2">14 nm </td> <td rowspan="2">2 (4) </td> <td rowspan="2">1.2 </td> <td rowspan="2">2.3 </td> <td rowspan="2">64 KB inst. 32 KB data per core </td> <td rowspan="2">512 KB per core </td> <td rowspan="2">4 MB </td> <td rowspan="2">Radeon Graphics (Vega) </td> <td rowspan="2">192:12:4 3 CU </td> <td rowspan="2">0.6 </td> <td rowspan="2">230.4 </td> <td rowspan="2">FT5 </td> <td rowspan="2">12 (8+4) </td> <td rowspan="2">DDR4-1600 single-channel </td> <td rowspan="2">6 W </td> <td>AM3015BRP2OFJ </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/11201">AMD 3015Ce</a> </th> <td>Apr 29, 2021 </td> <td>AM301CBRP2OFJ </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Pollock_Mobile" title="Template:AMD Pollock Mobile"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Pollock_Mobile" title="Template talk:AMD Pollock Mobile"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Pollock_Mobile" title="Special:EditPage/Template:AMD Pollock Mobile"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-323"><a href="#cite_ref-cconfig_323-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute units</a> (CU) </li> <li id="cite_note-SFLOPS-324"><a href="#cite_ref-SFLOPS_324-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id=""Mendocino"_(2022)">"Mendocino" (2022)</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=57" title="Edit section: "Mendocino" (2022)">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></div> Common features: <ul><li>Socket: FT6</li> <li>All the CPUs support <a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a>-5500 in <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> mode.</li> <li>L1 <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a>: 64 KB (32 KB data + 32 KB instruction) per core.</li> <li>L2 cache: 512 KB per core.</li> <li>All the CPUs support 4 <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> lanes.</li> <li>Includes integrated <a href="/wiki/RDNA_(microarchitecture)#RDNA_2" title="RDNA (microarchitecture)">RDNA2</a> GPU.</li> <li>Fabrication process: <a href="/wiki/TSMC" title="TSMC">TSMC</a> <a href="/wiki/7_nm" class="mw-redirect" title="7 nm">6 nm</a> FinFET.</li></ul> <table class="wikitable sortable" style="text-align:center;"> <tbody><tr> <th colspan="2" rowspan="3">Branding and Model </th> <th colspan="5"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="2"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3">Release date </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>) </th> <th rowspan="2"><a href="/wiki/CPU_Cache" class="mw-redirect" title="CPU Cache">L3 cache</a> (total) </th> <th rowspan="2">Core config<a href="#cite_note-325">[i]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Clock </th></tr> <tr> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Base </th> <th><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1038841319">Boost </th></tr> <tr> <th>Athlon Gold </th> <th>7220U<a href="#cite_note-Chrome-326">[a]</a><a href="#cite_note-327">[197]</a> </th> <td>2 (4) </td> <td rowspan="2">2.4 </td> <td>3.7 </td> <td>4 MB </td> <td rowspan="2">1 x 2 </td> <td rowspan="2">610M 2 CU </td> <td rowspan="2">1900 MHz </td> <td rowspan="2">8–15 W </td> <td rowspan="2">Sep 20, 2022<a href="#cite_note-328">[198]</a> </td></tr> <tr> <th>Athlon Silver </th> <th>7120U<a href="#cite_note-Chrome-326">[a]</a><a href="#cite_note-329">[199]</a> </th> <td>2 (2) </td> <td>3.5 </td> <td>2 MB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Athlon_Mobile_7020_series" title="Template:AMD Athlon Mobile 7020 series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Athlon_Mobile_7020_series" title="Template talk:AMD Athlon Mobile 7020 series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Athlon_Mobile_7020_series" title="Special:EditPage/Template:AMD Athlon Mobile 7020 series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-325"><a href="#cite_ref-325">^</a> Core Complexes (CCX) × cores per CCX </li> </ol></div></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-Chrome-326">^ <a href="#cite_ref-Chrome_326-0">a</a> <a href="#cite_ref-Chrome_326-1">b</a> Model also available as Chromebook optimized version as 7220C<a href="#cite_note-330">[200]</a> and 7120C<a href="#cite_note-331">[201]</a> released on May 23, 2023 </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Embedded_APUs">Embedded APUs</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=58" title="Edit section: Embedded APUs">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></div> <div class="mw-heading mw-heading3"><h3 id="G-Series">G-Series</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=59" title="Edit section: G-Series">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Brazos:_"Ontario"_and_"Zacate"_(2011)">Brazos: "Ontario" and "Zacate" (2011)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=60" title="Edit section: Brazos: "Ontario" and "Zacate" (2011)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 40 nm</li> <li><a href="/wiki/Socket_FT1" title="Socket FT1">Socket FT1</a> (BGA-413)</li> <li>CPU microarchitecture: <a href="/wiki/Bobcat_(processor)" class="mw-redirect" title="Bobcat (processor)">Bobcat</a><a href="#cite_note-332">[202]</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/NX_bit" title="NX bit">NX bit</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a></li> <li>GPU microarchitecture: <a href="/wiki/TeraScale_2" class="mw-redirect" title="TeraScale 2">TeraScale 2 (VLIW5) "Evergreen"</a></li> <li>Memory support: single-channel, support up to two DIMMs of DDR3-1333 or DDR3L-1066</li> <li>5 GT/s UMI</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-333">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-334">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T24L </th> <td>March 1, 2011 May 23, 2011 </td> <td rowspan="15">40 nm </td> <td rowspan="3">B0 </td> <td rowspan="2">1 (1) </td> <td>0.8 1.0 </td> <td rowspan="15">32 KB inst. 32 KB data per core </td> <td rowspan="2">512 KB </td> <td rowspan="3" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="3">1066 </td> <td>5 </td> <td>GET24LFPB12GTE GET24LFQB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T30L </th> <td>March 1, 2011 May 23, 2011 </td> <td rowspan="2">1.4 </td> <td rowspan="2">18 </td> <td>GET30LGBB12GTE GET30LGBB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T48L </th> <td>March 1, 2011 May 23, 2011 </td> <td>2 (2) </td> <td>2 × 512 KB </td> <td>GET48LGBB22GTE GET48LGBB22GVE </td></tr> <tr> <th colspan="2"> </th> <th colspan="3"></th> <th></th> <th colspan="7"> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T16R </th> <td>June 25, 2012 </td> <td rowspan="11">B0 </td> <td rowspan="2">1 (1) </td> <td>0.615 </td> <td rowspan="2">512 KB </td> <td rowspan="3"><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> </td> <td rowspan="11">80:8:4 </td> <td>276 </td> <td>44.1 </td> <td>(L)1066 </td> <td>4.5 </td> <td>GET16RFWB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T40R </th> <td rowspan="2">May 23, 2011 </td> <td rowspan="4">1.0 </td> <td rowspan="6">280 </td> <td rowspan="6">44.8 </td> <td rowspan="7">1066 </td> <td>5.5 </td> <td>GET40RFQB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T40E </th> <td rowspan="2">2 (2) </td> <td rowspan="2">2 × 512 KB </td> <td>6.4 </td> <td>GET40EFQB22GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T40N </th> <td>January 19, 2011 May 23, 2011 </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> <a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6290</a> </td> <td>9 </td> <td>GET40NFPB22GTE GET40NFPB22GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T40R </th> <td>May 23, 2011 </td> <td rowspan="2">1 (1) </td> <td rowspan="2">512 KB </td> <td rowspan="3"><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> </td> <td>5.5 </td> <td>GET40RFSB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T44R </th> <td>January 19, 2011 May 23, 2011 </td> <td>1.2 </td> <td>9 </td> <td>GET44RFPB12GTE GET44RFPB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T48E </th> <td>June 25, 2012 </td> <td rowspan="2">2 (2) </td> <td rowspan="2">1.4 </td> <td rowspan="2">2 × 512 KB </td> <td rowspan="5">18 </td> <td>GET48EGBB22GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T48N </th> <td>January 19, 2011 May 23, 2011 </td> <td rowspan="2"><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6310</a> </td> <td>500 520 </td> <td>80 83.2 </td> <td>GET48NGBB22GTE GET48NGBB22GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T52R </th> <td>January 19, 2011 May 23, 2011 </td> <td>1 (1) </td> <td>1.5 </td> <td>512 KB </td> <td>500 </td> <td>80 </td> <td>1066 1333 </td> <td>GET52RGBB12GTE GET52RGBB12GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T56E </th> <td>June 25, 2012 </td> <td rowspan="2">2 (2) </td> <td>1.65 </td> <td rowspan="2">2 × 512 KB </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6250</a> </td> <td>275 </td> <td>44 </td> <td>1333 </td> <td>GET56EGBB22GVE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">G-Series T56N </th> <td>January 19, 2011 May 23, 2011 </td> <td>1.6 1.65 </td> <td><a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6310</a> <a href="/wiki/Comparison_of_AMD_graphics_processing_units#IGP_(HD_6xxx)" class="mw-redirect" title="Comparison of AMD graphics processing units">HD 6320</a> </td> <td>500 </td> <td>80 </td> <td>1066 1333 </td> <td>GET56NGBB22GTE GET56NGBB22GVE </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-333"><a href="#cite_ref-kib_333-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-334"><a href="#cite_ref-SFLOPS_334-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Kabini"_(2013,_SoC)_2">"Kabini" (2013, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=61" title="Edit section: "Kabini" (2013, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li><a href="/wiki/Socket_FT3" title="Socket FT3">Socket FT3</a> (769-BGA)<a href="#cite_note-335">[203]</a></li> <li>CPU microarchitecture: <a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support. No support for <a href="/wiki/FMA_instruction_set" title="FMA instruction set">FMA (Fused Multiply-Accumulate)</a>. <a href="/wiki/Trusted_Platform_Module" title="Trusted Platform Module">Trusted Platform Module</a> (TPM) 1.2 support</li> <li>GPU microarchitecture: <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) with <a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder</a> 3 (H.264, VC-1, MPEG2, etc.)</li> <li>Single channel DDR3-1600, 1.25 and 1.35 V voltage level support, support for <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a></li> <li>Integrates <a href="/wiki/A85X" class="mw-redirect" title="A85X">Controller Hub</a> functional block, HD audio, 2 SATA channels, USB 2.0 and USB 3.0 (except GX-210JA)</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temperature</a> (°C) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-336">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-337">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210UA </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td rowspan="9">28 nm </td> <td rowspan="9">B0 </td> <td rowspan="5">2 (2) </td> <td rowspan="4">1.0 </td> <td rowspan="9">32 KB inst. 32 KB data per core </td> <td rowspan="5">1 </td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1333 </td> <td>8.5 </td> <td rowspan="2">0-90 </td> <td>GE210UIGJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210JA </th> <td>July 30, 2013 </td> <td>HD 8180E </td> <td rowspan="6">128:8:4 2 CU </td> <td>225 </td> <td>57.6 </td> <td rowspan="2">1066 </td> <td>6 </td> <td>GE210JIHJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-209HA </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td>HD 8400E </td> <td>600 </td> <td>153.6 </td> <td rowspan="2">9 </td> <td>-40-105 </td> <td>GE209HISJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210HA </th> <td rowspan="2">June 1, 2013 </td> <td>HD 8210E </td> <td>300 </td> <td>76.8 </td> <td>1333 </td> <td rowspan="2">0-90 </td> <td>GE210HICJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-217GA </th> <td>1.65 </td> <td>HD 8280E </td> <td>450 </td> <td>115.2 </td> <td>1600 </td> <td rowspan="4">15 </td> <td>GE217GIBJ23HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-411GA </th> <td style="background: var(--background-color-interactive, #EEE); color: var(--color-base, black); vertical-align: middle; white-space: nowrap; text-align: center;" class="table-Unknown">Unknown </td> <td rowspan="4">4 (4) </td> <td>1.1 </td> <td rowspan="4">2 </td> <td>HD 8210E </td> <td>300 </td> <td>76.8 </td> <td>1066 </td> <td>-40-105 </td> <td>GE411GIRJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-415GA </th> <td rowspan="3">June 1, 2013 </td> <td>1.5 </td> <td>HD 8330E </td> <td>500 </td> <td>128 </td> <td rowspan="3">1600 </td> <td rowspan="3">0-90 </td> <td>GE415GIBJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-416RA </th> <td>1.6 </td> <td colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>GE416RIBJ44HM </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-420CA </th> <td>2.0 </td> <td>HD 8400E </td> <td>128:8:4 2 CU </td> <td>600 </td> <td>153.6 </td> <td>25 </td> <td>GE420CIAJ44HM </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-336"><a href="#cite_ref-kib_336-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-337"><a href="#cite_ref-SFLOPS_337-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Steppe_Eagle"_(2014,_SoC)">"Steppe Eagle" (2014, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=62" title="Edit section: "Steppe Eagle" (2014, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li><a href="/wiki/Socket_FT3" title="Socket FT3">Socket FT3b</a> (769-BGA)</li> <li>CPU microarchitecture: <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temperature</a> (°C) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">[FPUs]</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-338">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-339">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210JC </th> <td rowspan="6">June 4, 2014 </td> <td rowspan="6">28 nm </td> <td rowspan="6">ML-A1 </td> <td rowspan="4">2 (2) [1] </td> <td>1.0 </td> <td rowspan="6">32 KB inst. 32 KB data per core </td> <td rowspan="4">1 </td> <td>R1E </td> <td rowspan="6">128:8:4 2 CU </td> <td>267 </td> <td>68.3 </td> <td>1600 </td> <td rowspan="2">6 </td> <td>-40-105 </td> <td>GE210JIZJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-212JC </th> <td>1.2 </td> <td>R2E </td> <td rowspan="2">300 </td> <td rowspan="2">76.8 </td> <td>1333 </td> <td>0-90 </td> <td>GE212JIYJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-216HC </th> <td>1.6 </td> <td>R4E </td> <td>1066 </td> <td>10 </td> <td>-40-105 </td> <td>GE216HHBJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-222GC </th> <td>2.2 </td> <td>R5E </td> <td>655 </td> <td>167.6 </td> <td>1600 </td> <td>15 </td> <td rowspan="3">0-90 </td> <td>GE222GITJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-412HC </th> <td rowspan="2">4 (4) [2] </td> <td>1.2 </td> <td rowspan="2">2 </td> <td>R3E </td> <td>300 </td> <td>76.8 </td> <td>1333 </td> <td>7 </td> <td>GE412HIYJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-424CC </th> <td>2.4 </td> <td>R5E </td> <td>497 </td> <td>127.2 </td> <td>1866 </td> <td>25 </td> <td>GE424CIXJ44JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-338"><a href="#cite_ref-kib_338-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-339"><a href="#cite_ref-SFLOPS_339-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Crowned_Eagle"_(2014,_SoC)">"Crowned Eagle" (2014, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=63" title="Edit section: "Crowned Eagle" (2014, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/wiki/Socket_FT3" title="Socket FT3">FT3b</a> (769-BGA)</li> <li>CPU microarchitecture: <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a></li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>no GPU</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th colspan="4">CPU </th> <th rowspan="3">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction</a> <a href="/wiki/Junction_temperature" title="Junction temperature">temperature</a> (°C) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">[FPUs]</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-340">[a]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-224PC </th> <td rowspan="4">June 4, 2014 </td> <td rowspan="4">28 nm </td> <td>2 (2) [1] </td> <td>2.4 </td> <td rowspan="4">32 KB inst. 32 KB data per core </td> <td>1 </td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>1866 </td> <td>25 </td> <td>0-90 </td> <td>GE224PIXJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-410VC </th> <td rowspan="3">4 (4) [2] </td> <td>1.0 </td> <td rowspan="3">2 </td> <td>1066 </td> <td>7 </td> <td>-40-105 </td> <td>GE410VIZJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-412TC </th> <td>1.2 </td> <td rowspan="2">1600 </td> <td>6 </td> <td rowspan="2">0-90 </td> <td>GE412TIYJ44JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-420MC </th> <td>2.0 </td> <td>17.5 </td> <td>GE420MIXJ44JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-340"><a href="#cite_ref-kib_340-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="LX-Family_(2016,_SoC)">LX-Family (2016, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=64" title="Edit section: LX-Family (2016, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/wiki/Socket_FT3" title="Socket FT3">FT3b</a> (769-BGA)</li> <li>2 <a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a> x86 cores with 1MB shared L2 cache</li> <li>L1 Cache: 32 KB Data per core and 32 KB Instructions per core</li> <li><a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a>, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, CLMUL, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a> support</li> <li>GPU microarchitecture: <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) (1CU) with support for DirectX 11.2</li> <li>Single channel 64-bit DDR3 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>Integrated Controller Hub supports: PCIe® 2.0 4×1, 2 USB3 + 4 USB2 ports, 2 SATA 2.0/3.0 ports</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab </th> <th rowspan="3">Step. </th> <th colspan="4">CPU </th> <th colspan="4">GPU </th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> <a href="/wiki/Thread_(computing)" title="Thread (computing)">(threads)</a> <a href="/wiki/Floating-point_unit" title="Floating-point unit">[FPUs]</a> </th> <th rowspan="2">Clock (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-341">[a]</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config </th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-342">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-208JL </th> <td>February 23, 2016 </td> <td rowspan="6">28 nm </td> <td rowspan="6">ML-A1 </td> <td rowspan="6">2 </td> <td>0.8 </td> <td rowspan="6">32 KB inst. 32 KB data per core </td> <td rowspan="6">1 </td> <td rowspan="6">R1E </td> <td rowspan="6">64:4:1 1 CU </td> <td rowspan="4">267 </td> <td rowspan="4">34.1 </td> <td>1333 </td> <td>6 </td> <td>GE208JIVJ23JB </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210HL </td> <td>2017 </td> <td rowspan="3">1.0 </td> <td>1066 </td> <td>7 </td> <td>GE208HIZJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210JL </th> <td>February 23, 2016 </td> <td rowspan="2">1333 </td> <td>6 </td> <td>GE210JIVJ23JB </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-210KL </td> <td>2017 </td> <td>4.5 </td> <td>GE210KIVJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-215GL </th> <td rowspan="2">February 23, 2016 </td> <td>1.5 </td> <td rowspan="2">497 </td> <td rowspan="2">63.6 </td> <td rowspan="2">1600 </td> <td rowspan="2">15 </td> <td>GE215GITJ23JB </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-218GL </th> <td>1.8 </td> <td>GE218GITJ23JB </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-341"><a href="#cite_ref-kib_341-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-342"><a href="#cite_ref-SFLOPS_342-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="I-Family:_"Brown_Falcon"_(2016,_SoC)">I-Family: "Brown Falcon" (2016, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=65" title="Edit section: I-Family: "Brown Falcon" (2016, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket FP4<a href="#cite_note-343">[204]</a></li> <li>2 or 4 <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> x86 cores with 1MB shared L2 cache</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></li> <li>GPU microarchitecture: <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) (up to 4 CUs) with support for DirectX 12</li> <li>Dual channel 64-bit DDR4 or DDR3 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>4K × 2K H.265 decode capability and multi format encode and decode</li> <li>Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model</th> <th rowspan="3">Released </th> <th rowspan="3">Fab</th> <th colspan="5">CPU</th> <th colspan="4">GPU</th> <th rowspan="3">Memory support</th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-344">[a]</a> </th> <th rowspan="2">Model</th> <th rowspan="2">Config<a href="#cite_note-fn_2-345">[note 1]</a></th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-346">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-217GI </th> <td>February 23, 2016 </td> <td rowspan="2">28 nm</td> <td>[1] 2</td> <td>1.7</td> <td>2.0</td> <td rowspan="2">96 KB inst. per module 32 KB data per core</td> <td>1</td> <td>R6E</td> <td>256:16:4 4 CU</td> <td>758</td> <td>388</td> <td>DDR3/DDR4-1600</td> <td>15</td> <td>GE217GAAY23KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-420GI<a href="#cite_note-347">[205]</a> </th> <td>2016</td> <td>[2] 4</td> <td>2.0</td> <td>2.2</td> <td>2</td> <td>R6E R7E</td> <td>256:16:4 4 CU 384:24:4 6 CU</td> <td>758 626</td> <td>388 480.7</td> <td>DDR4-1866</td> <td>16.1</td> <td>GE420GAAY43KA </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-344"><a href="#cite_ref-kib_344-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-346"><a href="#cite_ref-SFLOPS_346-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="J-Family:_"Prairie_Falcon"_(2016,_SoC)">J-Family: "Prairie Falcon" (2016, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=66" title="Edit section: J-Family: "Prairie Falcon" (2016, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket FP4<a href="#cite_note-348">[206]</a></li> <li>2 "<a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator+</a>" x86 cores with 1MB shared L2 cache</li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></li> <li>GPU microarchitecture: Radeon R5E <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) (up to 3 CUs) with support for DirectX 12</li> <li>Single channel 64-bit DDR4 or DDR3 memory</li> <li>4K × 2K H.265 decode capability with 10-bit compatibility and multi format encode and decode</li> <li>Integrated Controller Hub supports: PCIe 3.0 1×4, PCIe 2/3 4×1, 2 USB3 + 2 USB2 ports, 2 SATA 2.0/3.0 ports</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model</th> <th rowspan="3">Released </th> <th rowspan="3">Fab</th> <th colspan="5">CPU</th> <th colspan="5">GPU</th> <th rowspan="3">Memory support</th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temperature</a> (°C)</th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-349">[a]</a> </th> <th rowspan="2">Model</th> <th rowspan="2">Config<a href="#cite_note-fn_2-345">[note 1]</a></th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo</th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-350">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-212JJ </th> <td>2018 </td> <td rowspan="4">28 nm</td> <td rowspan="4">[1] 2</td> <td>1.2</td> <td>1.6</td> <td rowspan="4">96 KB inst. per module 32 KB data per core</td> <td rowspan="4">1</td> <td>R1E</td> <td>64:4:1 1 CU</td> <td rowspan="4">600</td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>76.8</td> <td>DDR3-1333 DDR4-1600</td> <td rowspan="2">6– 10 </td> <td rowspan="4">0-90</td> <td>GE212JAWY23AC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-215JJ </th> <td>2017</td> <td>1.5</td> <td>2.0</td> <td rowspan="2">R2E</td> <td rowspan="2">128:8:2 2 CU</td> <td rowspan="2">153.6</td> <td rowspan="2">DDR3-1600 DDR4-1866</td> <td>GE215JAWY23AC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-220IJ </th> <td>2018</td> <td>2.0</td> <td>2.2</td> <td rowspan="2">10– 15 </td> <td>GE220IAVY23AC </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">GX-224IJ </th> <td>2017</td> <td>2.4</td> <td>2.8</td> <td>R4E</td> <td>192:12:3 3 CU</td> <td>230.4</td> <td>DDR3-1866 DDR4-2133</td> <td>GE224IAVY23AC </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-349"><a href="#cite_ref-kib_349-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-350"><a href="#cite_ref-SFLOPS_350-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="R-Series">R-Series</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=67" title="Edit section: R-Series">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="Comal:_"Trinity"_(2012)_2">Comal: "Trinity" (2012)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=68" title="Edit section: Comal: "Trinity" (2012)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 32 nm</li> <li>Socket <a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a> (BGA-827), <a href="/wiki/Socket_FS1" title="Socket FS1">FS1r2</a></li> <li>CPU microarchitecture: <a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a></li> <li>L1 Cache: 16 KB Data per core and 64 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> 1.1, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>,<a href="#cite_note-auto-46">[29]</a> <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a></li> <li>GPU microarchitecture: <a href="/wiki/TeraScale_3" class="mw-redirect" title="TeraScale 3">TeraScale 3 (VLIW4) "Northern Islands"</a></li> <li>Memory support: dual-channel 1.35 V <a href="/wiki/DDR3L" class="mw-redirect" title="DDR3L">DDR3L</a>-1600 memory, in addition to regular 1.5 V DDR3</li> <li>2.5 GT/s UMI</li> <li>Die size: 246 mm²; Transistors: 1.303 billion</li> <li>OpenCL 1.1 and OpenGL 4.2 support</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab</th> <th rowspan="3">Step.</th> <th colspan="5">CPU</th> <th colspan="5">GPU</th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-351">[a]</a> </th> <th rowspan="2">Model</th> <th rowspan="2">Config<a href="#cite_note-fn_2-345">[note 1]</a></th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-352">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-252F </th> <td rowspan="8">May 21, 2012 </td> <td rowspan="8">32 nm </td> <td rowspan="8">B0</td> <td rowspan="4">[1] 2</td> <td>1.9</td> <td>2.4</td> <td rowspan="8">64 KB inst. per module 16 KB data per core</td> <td>1</td> <td>HD 7400G</td> <td>192:12:4 3 CU</td> <td>333</td> <td>417</td> <td>127.8</td> <td rowspan="2">1333</td> <td rowspan="2">17</td> <td>RE252FSHE23HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-260H </th> <td>2.1</td> <td>2.6</td> <td>2?</td> <td>HD 7500G</td> <td>256:16:8 4 CU</td> <td>327</td> <td>424</td> <td>167.4</td> <td>RE260HSHE24HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-268D </th> <td>2.5</td> <td>3.0</td> <td rowspan="2">1</td> <td>HD 7420G</td> <td rowspan="2">192:12:4 3 CU</td> <td>470</td> <td>640</td> <td>180.4</td> <td rowspan="4">1600</td> <td rowspan="2">35</td> <td>RE268DDEC23HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-272F </th> <td>2.7</td> <td>3.2</td> <td>HD 7520G</td> <td>497</td> <td>686</td> <td>190.8</td> <td>RE272FDEC23HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-452L </th> <td rowspan="4">[2] 4</td> <td>1.6</td> <td>2.4</td> <td rowspan="4">2 × 2 MB</td> <td>HD 7600G</td> <td rowspan="2">256:16:8 4 CU</td> <td>327</td> <td>424</td> <td>167.4</td> <td>19</td> <td>RE452LSHE44HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-460H </th> <td>1.9</td> <td rowspan="2">2.8</td> <td>HD 7640G</td> <td>497</td> <td>655</td> <td>254.4</td> <td>35</td> <td>RE460HDEC44HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-460L </th> <td>2.0</td> <td>HD 7620G</td> <td rowspan="2">384:24:8 6 CU</td> <td>360</td> <td>497</td> <td>276.4</td> <td>1333</td> <td>25</td> <td>RE460LSIE44HJE </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">R-464L </th> <td>2.3</td> <td>3.2</td> <td>HD 7660G</td> <td>497</td> <td>686</td> <td>381.6</td> <td>1600</td> <td>35</td> <td>RE464LDEC44HJE </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-351"><a href="#cite_ref-kib_351-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-352"><a href="#cite_ref-SFLOPS_352-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Bald_Eagle"_(2014)">"Bald Eagle" (2014)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=69" title="Edit section: "Bald Eagle" (2014)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a></li> <li>Up to 4 <a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a> x86 cores<a href="#cite_note-353">[207]</a></li> <li>L1 Cache: 16 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a> 1.1, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>,<a href="#cite_note-auto-46">[29]</a> <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a></li> <li>GPU microarchitecture: <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) (up to 8 CUs) with support for DirectX 11.1 and OpenGL 4.2</li> <li>Dual channel DDR3 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>Unified Video Decode (UVD) 4.2 and Video Coding Engine (VCE) 2.0</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model </th> <th rowspan="3">Released </th> <th rowspan="3">Fab</th> <th colspan="5">CPU</th> <th colspan="5">GPU</th> <th rowspan="3">DDR3 Memory support </th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temperature</a> (°C)</th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="2"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-354">[a]</a> </th> <th rowspan="2">Model</th> <th rowspan="2">Config<a href="#cite_note-fn_2-345">[note 1]</a></th> <th rowspan="2">Clock (MHz) </th> <th rowspan="2">Turbo (MHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-355">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-219NB </th> <td rowspan="5">May 20, 2014 </td> <td rowspan="5">28 nm</td> <td rowspan="2">[1] 2</td> <td rowspan="2">2.2</td> <td rowspan="2">3.0</td> <td rowspan="5">96 KB inst. per module 16 KB data per core</td> <td rowspan="2">1</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="2">1600</td> <td rowspan="2">15- 17 </td> <td rowspan="5">0-100</td> <td>RE219NECH23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-225FB </th> <td>R4</td> <td>192:12:4 3 CU</td> <td>464</td> <td>533</td> <td>178.1</td> <td>RE225FECH23JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-425BB </th> <td rowspan="3">[2] 4</td> <td>2.5</td> <td>3.4</td> <td rowspan="3">4</td> <td>R6</td> <td>384:24:8 6 CU</td> <td>576</td> <td>654</td> <td>442.3</td> <td>1866</td> <td>30- 35 </td> <td>RE425BDGH44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-427BB </th> <td rowspan="2">2.7</td> <td rowspan="2">3.6</td> <td>R7</td> <td>512:32:8 8 CU</td> <td>600</td> <td>686</td> <td>614.4</td> <td rowspan="2">2133</td> <td rowspan="2">30- 35 </td> <td>RE427BDGH44JA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-427NB </th> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td>RE427NDGH44JA </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-354"><a href="#cite_ref-kib_354-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-355"><a href="#cite_ref-SFLOPS_355-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id=""Merlin_Falcon"_(2015,_SoC)">"Merlin Falcon" (2015, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=70" title="Edit section: "Merlin Falcon" (2015, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 28 nm</li> <li>Socket <a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a></li> <li>Up to 4 <a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a> x86 cores<a href="#cite_note-356">[208]</a></li> <li>L1 Cache: 32 KB Data per core and 96 KB Instructions per module</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/XOP_instruction_set" title="XOP instruction set">XOP</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/FMA4_instruction_set#FMA4_instruction_set" class="mw-redirect" title="FMA4 instruction set">FMA4</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#TBM_(Trailing_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">TBM</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a></li> <li>GPU microarchitecture: <a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">Graphics Core Next</a> (GCN) (up to 8 CUs) with support for DirectX 12</li> <li>Dual channel 64-bit DDR4 or DDR3 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>Unified Video Decode (UVD) 6 (4K H.265 and H.264 decode) and Video Coding Engine (VCE) 3.1 (4K H.264 encode)</li> <li>Dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB)</li> <li>Integrated FCH featuring PCIe 3.0 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, UART</li></ul> <table class="wikitable sortable" style="text-align: center"> <tbody><tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh" rowspan="3">Model</th> <th rowspan="3">Released </th> <th rowspan="3">Fab</th> <th rowspan="3">Stepping</th> <th colspan="6">CPU</th> <th colspan="5">GPU</th> <th rowspan="3">Memory support</th> <th rowspan="3">TDP (W) </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temperature</a> (°C)</th> <th rowspan="3">Part number </th></tr> <tr> <th rowspan="2">[Modules/<a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>] <a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Cores</a>/<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo (GHz) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a><a href="#cite_note-kib-357">[a]</a> </th> <th rowspan="2">Model</th> <th rowspan="2">Config<a href="#cite_note-fn_2-345">[note 1]</a></th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Turbo</th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-358">[b]</a> </th></tr> <tr> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> (MB) </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-216TD </th> <td rowspan="2">October 21, 2015 </td> <td rowspan="6">28 nm</td> <td></td> <td rowspan="2">[1] 2</td> <td rowspan="3">1.6</td> <td rowspan="2">3.0</td> <td rowspan="6">96 KB inst. per module 32 KB data per core</td> <td rowspan="2">1</td> <td rowspan="6" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td rowspan="3">DDR3/DDR4-1600</td> <td rowspan="2">12- 15 </td> <td rowspan="2">0-90</td> <td>RE216TAAY23KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-216GD </th> <td></td> <td>R5</td> <td>256:?:? 4 CU</td> <td>0.8</td> <td rowspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>409.6</td> <td>RE216GAAY23KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-416GD </th> <td></td> <td></td> <td rowspan="4">[2] 4</td> <td>2.4</td> <td rowspan="4">2</td> <td rowspan="2">R6</td> <td>384:?:? 6 CU</td> <td>0.72</td> <td>552.9</td> <td>15</td> <td>-40-105</td> <td>RE416GATY43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-418GD </th> <td rowspan="3">October 21, 2015</td> <td></td> <td>1.8</td> <td>3.2</td> <td>384:?:? 6 CU</td> <td rowspan="2">0.8</td> <td>614.4</td> <td rowspan="3">DDR3-2133 DDR4-2400</td> <td rowspan="3">12- 35 </td> <td rowspan="3">0-90</td> <td>RE418GAAY43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-421BD </th> <td></td> <td rowspan="2">2.1</td> <td rowspan="2">3.4</td> <td>R7</td> <td>512:?:? 8 CU</td> <td>819.2</td> <td>RE421BAAY43KA </td></tr> <tr> <th style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">RX-421ND </th> <td></td> <td colspan="5" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td>RE421NAAY43KA </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-kib-357"><a href="#cite_ref-kib_357-0">^</a> AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<a href="#cite_note-AMD_54945-42">[27]</a> </li> <li id="cite_note-SFLOPS-358"><a href="#cite_ref-SFLOPS_358-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Fused_multiply%E2%80%93add" class="mw-redirect" title="Fused multiply–add">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="1000-Series">1000-Series</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=71" title="Edit section: 1000-Series">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)">V1000-Family: "Great Horned Owl" (2018, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=72" title="Edit section: V1000-Family: "Great Horned Owl" (2018, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Up to 4 <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> cores</li> <li>Socket FP5</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual channel DDR4 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>Fifth generation <a href="/wiki/Graphics_Core_Next#GCN_5th_Generation_(Vega)" title="Graphics Core Next">GCN</a> based GPU</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th> <th rowspan="3"><a href="/wiki/Junction_temperature" title="Junction temperature">Junction temp. range</a> (°C) </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-359">[i]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-360">[ii]</a> </th></tr> <tr> <th><abbr title="3+ active cores">Base</abbr> </th> <th><abbr title="1–2 active cores">Boost</abbr> </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7291">V1202B</a> </th> <td>February 2018 </td> <td rowspan="7"><a href="/wiki/Global_Foundries" class="mw-redirect" title="Global Foundries">GloFo</a> <a href="/wiki/14_nm_process" title="14 nm process">14LP</a> </td> <td>2 (4) </td> <td>2.3 </td> <td>3.2 </td> <td rowspan="7">64 KB <abbr title="instruction">inst.</abbr> 32 KB data per core </td> <td rowspan="7">512 KB per core </td> <td rowspan="7">4 MB </td> <td>Vega 3 </td> <td>192:12:16 3 CU </td> <td>1.0 </td> <td>384 </td> <td rowspan="4">DDR4-2400 <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> </td> <td rowspan="4">12–25 W </td> <td>0–105 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9126">V1404I</a> </th> <td rowspan="2">December 2018 </td> <td rowspan="6">4 (8) </td> <td>2.0 </td> <td>3.6 </td> <td>Vega 8 </td> <td rowspan="1">512:32:16 8 CU </td> <td rowspan="1">1.1 </td> <td rowspan="1">1126.4 </td> <td>-40–105 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8496">V1500B</a> </th> <td>2.2 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="1" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td rowspan="5">0–105 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7281">V1605B</a> </th> <td rowspan="2">February 2018 </td> <td>2.0 </td> <td rowspan="3">3.6 </td> <td rowspan="2">Vega 8 </td> <td rowspan="2">512:32:16 8 CU </td> <td rowspan="2">1.1 </td> <td rowspan="2">1126.4 </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7276">V1756B</a> </th> <td>3.25 </td> <td rowspan="3">DDR4-3200 dual-channel </td> <td rowspan="3">35–54 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8491">V1780B</a> </th> <td>December 2018 </td> <td rowspan="2">3.35 </td> <td rowspan="1" colspan="4" data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/7271">V1807B</a> </th> <td>February 2018 </td> <td>3.8 </td> <td>Vega 11 </td> <td>704:44:16 11 CU </td> <td>1.3 </td> <td>1830.4 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: -5px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_V1000_series" title="Template:AMD V1000 series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_V1000_series" title="Template talk:AMD V1000 series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_V1000_series" title="Special:EditPage/Template:AMD V1000 series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-359"><a href="#cite_ref-cconfig_359-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute Units (CU)</a> </li> <li id="cite_note-SFLOPS-360"><a href="#cite_ref-SFLOPS_360-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="R1000-Family:_"Banded_Kestrel"_(2019,_SoC)">R1000-Family: "Banded Kestrel" (2019, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=73" title="Edit section: R1000-Family: "Banded Kestrel" (2019, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 14 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Up to 2 <a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">Zen</a> cores</li> <li>Socket FP5</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li> <li>Dual channel DDR4 memory with <a href="/wiki/ECC_memory" title="ECC memory">ECC</a></li> <li>Fifth generation <a href="/wiki/Graphics_Core_Next#GCN_5th_Generation_(Vega)" title="Graphics Core Next">GCN</a> based GPU</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6">CPU </th> <th colspan="4">GPU </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Gigahertz" class="mw-redirect" title="Gigahertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/Cache_memory" class="mw-redirect" title="Cache memory">Cache</a> </th> <th rowspan="2">Model </th> <th rowspan="2">Config<a href="#cite_note-cconfig-361">[i]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power (<a href="/wiki/GFLOPS" class="mw-redirect" title="GFLOPS">GFLOPS</a>)<a href="#cite_note-SFLOPS-362">[ii]</a> </th></tr> <tr> <th><abbr title="3+ active cores">Base</abbr> </th> <th><abbr title="1–2 active cores">Boost</abbr> </th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1</a> </th> <th><a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2</a> </th> <th><a href="/wiki/L3_cache" class="mw-redirect" title="L3 cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9226">R1102G</a> </th> <td rowspan="2">February 25, 2020 </td> <td rowspan="4"><a href="/wiki/Global_Foundries" class="mw-redirect" title="Global Foundries">GloFo</a> 14LP </td> <td>2 (2) </td> <td>1.2 </td> <td>2.6 </td> <td rowspan="4">64 KB inst. 32 KB data per core </td> <td rowspan="4">512 KB per core </td> <td rowspan="4">4 MB </td> <td rowspan="4">Vega 3 </td> <td rowspan="4">192:12:4 3 CU </td> <td rowspan="3">1.0 </td> <td rowspan="3">384 </td> <td>DDR4-2400 single-channel </td> <td>6 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/9221">R1305G</a> </th> <td rowspan="3">2 (4) </td> <td>1.5 </td> <td>2.8 </td> <td rowspan="3">DDR4-2400 <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> </td> <td>8-10 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8431">R1505G</a> </th> <td rowspan="2">April 16, 2019 </td> <td>2.4 </td> <td>3.3 </td> <td rowspan="2">12–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/8426">R1606G</a> </th> <td>2.6 </td> <td>3.5 </td> <td>1.2 </td> <td>460.8 </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: -5px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_R1000_series" title="Template:AMD R1000 series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_R1000_series" title="Template talk:AMD R1000 series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_R1000_series" title="Special:EditPage/Template:AMD R1000 series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-361"><a href="#cite_ref-cconfig_361-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute Units (CU)</a> </li> <li id="cite_note-SFLOPS-362"><a href="#cite_ref-SFLOPS_362-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading3"><h3 id="2000-Series">2000-Series</h3>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=74" title="Edit section: 2000-Series">edit</a>]</div> <div class="mw-heading mw-heading4"><h4 id="V2000-Family:_"Grey_Hawk"_(2020,_SoC)">V2000-Family: "Grey Hawk" (2020, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=75" title="Edit section: V2000-Family: "Grey Hawk" (2020, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 7 nm by <a href="/wiki/TSMC" title="TSMC">TSMC</a></li> <li>Up to 8 <a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> cores</li> <li>Fifth generation <a href="/wiki/Graphics_Core_Next#GCN_5th_Generation_(Vega)" title="Graphics Core Next">GCN</a> based GPU</li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th rowspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/CPU_cache" title="CPU cache">Cache</a> </th> <th rowspan="2"><a href="/wiki/Microarchitecture" title="Microarchitecture">Archi- tecture</a> </th> <th rowspan="2">Config<a href="#cite_note-cconfig-363">[i]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power<a href="#cite_note-SFLOPS-364">[ii]</a> (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>) </th></tr> <tr> <th><abbr title="3+ active cores">Base</abbr> </th> <th><abbr title="1–2 active cores">Boost</abbr> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L1</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10551">V2516</a><a href="#cite_note-ref2-365">[209]</a> </th> <td rowspan="4">November 10, 2020<a href="#cite_note-Unveil-366">[210]</a> </td> <td rowspan="4"><a href="/wiki/TSMC" title="TSMC">TSMC</a> 7FF </td> <td rowspan="2">6 (12) </td> <td>2.1 </td> <td>3.95 </td> <td rowspan="4">32 KB <abbr title="instruction">inst.</abbr> 32 KB data per core </td> <td rowspan="4">512 KB per core </td> <td rowspan="4">8 MB </td> <td rowspan="4"><a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5</a> </td> <td rowspan="2">384:24:8 6 CU </td> <td rowspan="2">1.5 </td> <td rowspan="2">1152 </td> <td rowspan="4">FP6 </td> <td rowspan="4">20 (8+4+4+4) <a href="/wiki/PCI_Express#PCI_Express_3.0" title="PCI Express">PCIe 3.0</a> </td> <td rowspan="4">DDR4-3200 <a href="/wiki/Multi-channel_memory_architecture#Dual-channel_architecture" title="Multi-channel memory architecture">dual-channel</a> LPDDR4X-4266 <a href="/wiki/Multi-channel_memory_architecture#Quad-channel_architecture" title="Multi-channel memory architecture">quad-channel</a> </td> <td>10–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10541">V2546</a><a href="#cite_note-ref2-365">[209]</a> </th> <td>3.0 </td> <td>3.95 </td> <td>35–54 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10546">V2718</a><a href="#cite_note-ref2-365">[209]</a> </th> <td rowspan="2">8 (16) </td> <td>1.7 </td> <td>4.15 </td> <td rowspan="2">448:28:8 7 CU </td> <td rowspan="2">1.6 </td> <td rowspan="2">1433.6 </td> <td>10–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/10536">V2748</a><a href="#cite_note-ref2-365">[209]</a> </th> <td>2.9 </td> <td>4.25 </td> <td>35–54 W </td></tr> </tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: -5px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Embedded_V2000_Series" title="Template:AMD Ryzen Embedded V2000 Series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_Ryzen_Embedded_V2000_Series" title="Template talk:AMD Ryzen Embedded V2000 Series"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Embedded_V2000_Series" title="Special:EditPage/Template:AMD Ryzen Embedded V2000 Series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-363"><a href="#cite_ref-cconfig_363-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute Units (CU)</a> </li> <li id="cite_note-SFLOPS-364"><a href="#cite_ref-SFLOPS_364-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading4"><h4 id="R2000-Family:_"River_Hawk"_(2022,_SoC)">R2000-Family: "River Hawk" (2022, <a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a>)</h4>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=76" title="Edit section: R2000-Family: "River Hawk" (2022, SoC)">edit</a>]</div> <ul><li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fabrication</a> 12 nm by <a href="/wiki/GlobalFoundries" title="GlobalFoundries">GlobalFoundries</a></li> <li>Up to 4 <a href="/wiki/Zen%2B" title="Zen+">Zen+</a> cores</li> <li>MMX, <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">SSE</a>, <a href="/wiki/SSE2" title="SSE2">SSE2</a>, <a href="/wiki/SSE3" title="SSE3">SSE3</a>, <a href="/wiki/SSSE3" title="SSSE3">SSSE3</a>, <a href="/wiki/SSE4.1" class="mw-redirect" title="SSE4.1">SSE4.1</a>, <a href="/wiki/SSE4.2" class="mw-redirect" title="SSE4.2">SSE4.2</a>, <a href="/wiki/SSE4a" class="mw-redirect" title="SSE4a">SSE4a</a>, <a href="/wiki/AMD64" class="mw-redirect" title="AMD64">AMD64</a>, <a href="/wiki/AMD-V" class="mw-redirect" title="AMD-V">AMD-V</a>, <a href="/wiki/AES_instruction_set" title="AES instruction set">AES</a>, <a href="/wiki/CLMUL_instruction_set" title="CLMUL instruction set">CLMUL</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX</a>, <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">AVX 1.1</a>, <a href="/wiki/Advanced_Vector_Extensions_2" class="mw-redirect" title="Advanced Vector Extensions 2">AVX2</a>, <a href="/wiki/FMA_instruction_set#FMA3_instruction_set" title="FMA instruction set">FMA3</a>, <a href="/wiki/F16C" title="F16C">F16C</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)" class="mw-redirect" title="Bit Manipulation Instruction Sets">ABM</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI1</a>, <a href="/wiki/Bit_Manipulation_Instruction_Sets#BMI2" class="mw-redirect" title="Bit Manipulation Instruction Sets">BMI2</a>, <a href="/wiki/RDRAND" title="RDRAND">RDRAND</a>, <a href="/wiki/Turbo_Core" class="mw-redirect" title="Turbo Core">Turbo Core</a></li></ul> <table class="wikitable" style="text-align:center;"> <tbody><tr> <th rowspan="3">Model </th> <th rowspan="3">Release date </th> <th rowspan="3"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th colspan="6"><a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> </th> <th colspan="4"><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> </th> <th rowspan="3"><a href="/wiki/CPU_socket" title="CPU socket">Socket</a> </th> <th rowspan="3"><a href="/wiki/PCI_Express" title="PCI Express">PCIe</a> support </th> <th rowspan="3"><a href="/wiki/Memory_controller" title="Memory controller">Memory support</a> </th> <th rowspan="3"><a href="/wiki/Thermal_design_power" title="Thermal design power">TDP</a> </th></tr> <tr> <th rowspan="2"><a href="/wiki/Multi-core_processor" title="Multi-core processor">Cores</a> (<a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>) </th> <th colspan="2"><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a> (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th colspan="3"><a href="/wiki/CPU_cache" title="CPU cache">Cache</a> </th> <th rowspan="2"><a href="/wiki/Microarchitecture" title="Microarchitecture">Archi- tecture</a> </th> <th rowspan="2">Config<a href="#cite_note-cconfig-367">[i]</a> </th> <th rowspan="2">Clock (GHz) </th> <th rowspan="2">Processing power<a href="#cite_note-SFLOPS-368">[ii]</a> (<a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a>) </th></tr> <tr> <th><abbr title="3+ active cores">Base</abbr> </th> <th><abbr title="1–2 active cores">Boost</abbr> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L1</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L2</a> </th> <th><a href="/wiki/CPU_cache#Multi-level_caches" title="CPU cache">L3</a> </th></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/embedded/ryzen/ryzen-r2000-series.html#specifications">R2312</a><a href="#cite_note-ref3-369">[211]</a> </th> <td rowspan="2">June 7, 2022<a href="#cite_note-Unveil-R2000-370">[212]</a> </td> <td rowspan="2"><a href="/wiki/GlobalFoundries" title="GlobalFoundries">GloFo</a> <a href="/wiki/14_nm_process" title="14 nm process">12LP</a> </td> <td>2 (4) </td> <td>2.7 </td> <td rowspan="2">3.5 </td> <td rowspan="2">64 KB <abbr title="instruction">inst.</abbr> 32 KB data per core </td> <td rowspan="2">512 KB per core </td> <td rowspan="2">4 MB </td> <td rowspan="2"><a href="/wiki/Graphics_Core_Next#fifth" title="Graphics Core Next">GCN 5</a> </td> <td>192:12:4 3 CU </td> <td rowspan="2">1.2 </td> <td>460.8 </td> <td rowspan="2">FP5 </td> <td>8 lanes <a href="/wiki/PCIe_3.0" class="mw-redirect" title="PCIe 3.0">Gen 3</a> </td> <td>DDR4-2400 <a href="/wiki/Dual-channel" class="mw-redirect" title="Dual-channel">dual-channel</a> <a href="/wiki/ECC_memory" title="ECC memory">ECC</a> </td> <td>10–25 W </td></tr> <tr> <th style="text-align:left;"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/embedded/ryzen/ryzen-r2000-series.html#specifications">R2314</a><a href="#cite_note-ref3-369">[211]</a> </th> <td>4 (4) </td> <td>2.1 </td> <td>384:24:8 6 CU </td> <td>921.6 </td> <td>16 lanes Gen 3 </td> <td>DDR4-2666 dual-channel ECC </td> <td>10–35 W </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left;position: relative;top: -15px;right: -5px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_Ryzen_Embedded_R2000_Series" title="Template:AMD Ryzen Embedded R2000 Series"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/w/index.php?title=Template_talk:AMD_Ryzen_Embedded_R2000_Series&action=edit&redlink=1" class="new" title="Template talk:AMD Ryzen Embedded R2000 Series (page does not exist)"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_Ryzen_Embedded_R2000_Series" title="Special:EditPage/Template:AMD Ryzen Embedded R2000 Series"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-roman"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-367"><a href="#cite_ref-cconfig_367-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified Shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture Mapping Units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render Output Units</a> and <a href="/wiki/Graphics_Core_Next#Compute_units" title="Graphics Core Next">Compute Units (CU)</a> </li> <li id="cite_note-SFLOPS-368"><a href="#cite_ref-SFLOPS_368-0">^</a> <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-precision</a> performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Custom_APUs">Custom APUs</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=77" title="Edit section: Custom APUs">edit</a>]</div> As of May 1, 2013, AMD opened the doors of their "semi-custom" business unit.<a href="#cite_note-371">[213]</a> Since these chips are custom-made for specific customer needs, they vary widely from both consumer-grade APUs and even the other custom-built ones. Some notable examples of semi-custom chips that have come from this sector include the chips from the <a href="/wiki/PlayStation_4" title="PlayStation 4">PlayStation 4</a> and <a href="/wiki/Xbox_One" title="Xbox One">Xbox One</a>.<a href="#cite_note-372">[214]</a> So far the size of the integrated GPU in these semi-custom APUs exceed by far the GPU size in the consumer-grade APUs. <table class="wikitable" style="font-size:85%; text-align:center;"> <tbody><tr> <th rowspan="2">Chip (device) </th> <th rowspan="2">Release date </th> <th rowspan="2"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Fab</a> </th> <th rowspan="2">Die area (mm2) </th> <th colspan="4">CPU </th> <th colspan="7">GPU </th> <th colspan="3">Memory </th> <th rowspan="2">Storage </th> <th rowspan="2">API support </th> <th colspan="2">Special features </th></tr> <tr> <th>Archi- tecture </th> <th>Cores </th> <th>Clock (<a href="/wiki/Hertz" title="Hertz">GHz</a>) </th> <th>L2 cache </th> <th>Archi- tecture </th> <th>Core config<a href="#cite_note-cconfig-373">[a]</a> </th> <th>Clock (<a href="/wiki/Hertz" title="Hertz">MHz</a>) </th> <th><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">GFLOPS</a><a href="#cite_note-FLOPS-374">[b]</a> </th> <th>Pixel fillrate (<a href="/wiki/Pixel" title="Pixel">GP</a>/s)<a href="#cite_note-pixel_fillrate-375">[c]</a> </th> <th>Texture fillrate (<a href="/wiki/Texel_(graphics)" title="Texel (graphics)">GT</a>/s)<a href="#cite_note-texture_fill-376">[d]</a> </th> <th>Other </th> <th>Size </th> <th>Bus type & width </th> <th>Band- width (<a href="/wiki/Gigabyte" title="Gigabyte">GB</a>/s) </th> <th>Audio </th> <th>Other </th></tr> <tr> <th>Liverpool (<a href="/wiki/PlayStation_4" title="PlayStation 4">PS4</a>) </th> <td>Nov 2013 </td> <td rowspan="3">28 nm </td> <td>348 </td> <td rowspan="8"><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a> </td> <td rowspan="9">8 cores </td> <td>1.6 </td> <td rowspan="9">2× 2 MB </td> <td rowspan="6"><a href="/wiki/Graphics_Core_Next#GCN2" title="Graphics Core Next">GCN 2</a> </td> <td>1152:72:32 18 CU </td> <td>800 </td> <td>1843 </td> <td>25.6 </td> <td>57.6 </td> <td>8 <a href="/wiki/Graphics_Core_Next#Asynchronous_Compute_Engine" title="Graphics Core Next">ACEs</a> </td> <td>8 GB </td> <td>GDDR5 256-bit </td> <td>176 </td> <td><a href="/wiki/Blu-ray" title="Blu-ray">3DBD</a>/<a href="/wiki/DVD" title="DVD">DVD</a> 1× 2.5" <a href="/wiki/SATA" title="SATA">SATA</a> hard drive Easily replaceable hard drive USB 3.0 </td> <td>OpenGL 4.2, <a href="/wiki/PlayStation_4_system_software#Technology" title="PlayStation 4 system software">GNM, GNMX and PSSL</a> </td> <td><a href="/wiki/Dolby_Atmos" title="Dolby Atmos">Dolby Atmos</a> (BD) <a href="/wiki/S/PDIF" title="S/PDIF">S/PDIF</a> </td> <td><a href="/wiki/PlayStation_VR" title="PlayStation VR">PS VR</a> <a href="/wiki/PlayStation_4_technical_specifications#Hardware_modules" title="PlayStation 4 technical specifications">PS4 additional modules</a> <a href="/wiki/HDR10" title="HDR10">HDR10</a> (except discs)<a href="#cite_note-bdhdr-377">[e]</a> <a href="/wiki/Consumer_Electronics_Control" title="Consumer Electronics Control">CEC</a> Optional <a href="/wiki/Remote_control" title="Remote control">IR</a> sensor </td></tr> <tr> <th rowspan="2">Durango (<a href="/wiki/Xbox_One" title="Xbox One">Xbox One</a>) </th> <td rowspan="2">Nov 2013 </td> <td rowspan="2">363 </td> <td rowspan="4">1.75 </td> <td rowspan="4">768:48:16 12 CU </td> <td rowspan="2">853 </td> <td rowspan="2">1310 </td> <td rowspan="2">13.6 </td> <td rowspan="2">40.9 </td> <td rowspan="2">2 ACEs </td> <td style="border-bottom: none">32 MB </td> <td style="border-bottom: none">ESRAM<a href="#cite_note-ramcache-378">[f]</a> </td> <td style="border-bottom: none">204 </td> <td rowspan="2">3DBD/DVD/<a href="/wiki/Compact_Disc_Digital_Audio" title="Compact Disc Digital Audio">CD</a> 1× 2.5" SATA hard drive USB 3.0 </td> <td rowspan="4">Direct3D 11.2 and 12 </td> <td rowspan="2">Fully Dolby Atmos, <a href="/wiki/DTS:X" class="mw-redirect" title="DTS:X">DTS:X</a>, and Windows Sonic S/PDIF </td> <td rowspan="2">Xbox One additional modules <a href="/wiki/FreeSync" title="FreeSync">FreeSync</a> (1) <a href="/wiki/HDMI" title="HDMI">HDMI</a> 1.4 through IR sensor and IR out port <a href="/wiki/Kensington_lock" class="mw-redirect" title="Kensington lock">Kensington lock</a> </td></tr> <tr> <td style="border-top: none">8 GB </td> <td style="border-top: none">DDR3 256-bit </td> <td style="border-top: none">68 </td></tr> <tr> <th rowspan="2">Edmonton (<a href="/wiki/Xbox_One#Xbox_One_S" title="Xbox One">Xbox One S</a>) <a href="#cite_note-379">[215]</a> </th> <td rowspan="2">Jun 2016 </td> <td rowspan="6">16 nm </td> <td rowspan="2">240 </td> <td rowspan="2">914 </td> <td rowspan="2">1404 </td> <td rowspan="2">14.6 </td> <td rowspan="2">43.9 </td> <td rowspan="2">2 ACEs </td> <td style="border-bottom: none">32 MB </td> <td style="border-bottom: none">ESRAM </td> <td style="border-bottom: none">219 </td> <td rowspan="2"><a href="/wiki/Ultra_HD_Blu-ray" title="Ultra HD Blu-ray">4KBD</a>/3DBD/DVD/CD<a href="#cite_note-xboxdigital-380">[g]</a> 1× 2.5" SATA hard drive USB 3.0 </td> <td rowspan="2">Fully Dolby Atmos, DTS:X, and Windows Sonic S/PDIF </td> <td rowspan="2">Xbox One S additional modules Fully HDR10 <a href="/wiki/High-dynamic-range_video#Dolby_Vision" class="mw-redirect" title="High-dynamic-range video">Dolby Vision</a> (streaming) FreeSync (1&2) HDMI 1.4 through IR sensor and IR out port Kensington lock </td></tr> <tr> <td style="border-top: none">8 GB </td> <td style="border-top: none">DDR3 256-bit </td> <td style="border-top: none">68 </td></tr> <tr> <th>(<a href="/wiki/PlayStation_4" title="PlayStation 4">PS4 Slim</a>) </th> <td rowspan="1">Sep 2016 </td> <td>208 </td> <td>1.6 </td> <td>1152:72:32 18 CU </td> <td>800 </td> <td>1843 </td> <td>25.6 </td> <td>57.6 </td> <td>8 ACEs </td> <td>8 GB </td> <td>GDDR5 256-bit </td> <td>176 </td> <td>3DBD/DVD 1× 2.5" SATA hard drive Easily replaceable hard drive USB 3.0 </td> <td>OpenGL 4.2, <a href="/wiki/PlayStation_4_system_software#Technology" title="PlayStation 4 system software">GNM, GNMX and PSSL</a> </td> <td>Dolby Atmos (BD) </td> <td>PS VR PS4 Slim additional modules HDR10 (except discs) CEC Optional <a href="/wiki/Remote_control" title="Remote control">IR</a> sensor </td></tr> <tr> <th rowspan="2">Neo (<a href="/wiki/PlayStation_4#PlayStation_4_Pro" title="PlayStation 4">PS4 Pro</a>) <a href="#cite_note-381">[216]</a><a href="#cite_note-382">[217]</a><a href="#cite_note-383">[218]</a> </th> <td rowspan="2">Nov 2016 </td> <td rowspan="2">325 </td> <td rowspan="2">2.13 </td> <td rowspan="3"><a href="/wiki/Graphics_Core_Next#GCN4" title="Graphics Core Next">GCN 4</a> (Polaris) <a href="#cite_note-384">[219]</a> </td> <td rowspan="2">2304:144:32 36 CU </td> <td rowspan="2">911 </td> <td rowspan="2">4198 </td> <td rowspan="2">58.3 </td> <td rowspan="2">131.2 </td> <td rowspan="2">4 ACEs and 2 <a href="/wiki/Graphics_Core_Next#Hardware_schedulers" title="Graphics Core Next">HWS</a> Double-rate <a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">FP16</a><a href="#cite_note-Rapid_Packed_Math-385">[h]</a> <a href="/wiki/Checkerboard_rendering" title="Checkerboard rendering">checkerboard rendering</a> </td> <td style="border-bottom: none">8 GB<a href="#cite_note-386">[220]</a> </td> <td style="border-bottom: none">GDDR5 256-bit </td> <td style="border-bottom: none">218 </td> <td rowspan="2">3DBD/DVD 1× 2.5" SATA hard drive Easily replaceable hard drive USB 3.0 </td> <td rowspan="2">OpenGL 4.2 (4.5), <a href="/wiki/PlayStation_4_system_software#Technology" title="PlayStation 4 system software">GNM, GNMX and PSSL</a> </td> <td rowspan="2">Dolby Atmos (BD) S/PDIF </td> <td rowspan="2">PS VR PS4 Pro additional modules HDR10 (except discs) Up to <a href="/wiki/4K_resolution#3840_×_2160" title="4K resolution">4K</a>@60 Hz CEC Optional <a href="/wiki/Remote_control" title="Remote control">IR</a> sensor </td></tr> <tr> <td style="border-top: none">1 GB </td> <td style="border-top: none">DDR3<a href="#cite_note-ramswap-387">[i]</a> </td> <td style="border-top: none">? </td></tr> <tr> <th>Scorpio (<a href="/wiki/Xbox_One_X" class="mw-redirect" title="Xbox One X">Xbox One X</a>) <a href="#cite_note-388">[221]</a><a href="#cite_note-389">[222]</a><a href="#cite_note-390">[223]</a> </th> <td>Nov 2017 </td> <td>359 </td> <td><a href="/wiki/Jaguar_(microarchitecture)#Jaguar_derivative_and_successor" title="Jaguar (microarchitecture)">Customized Jaguar</a> </td> <td>2.3 </td> <td>2560:160:32 40 CU </td> <td>1172 </td> <td>6001 </td> <td>37.5 </td> <td>187.5 </td> <td>4 ACEs and 2 HWS </td> <td>12 GB </td> <td>GDDR5 384-bit </td> <td>326 </td> <td>4KBD/3DBD/DVD/CD 1× 2.5" SATA hard drive USB 3.0 </td> <td>Direct3D 11.2 and 12 </td> <td>Fully Dolby Atmos, DTS:X, and Windows Sonic S/PDIF </td> <td>Xbox One X additional modules Fully HDR10 <a href="/wiki/Dolby_Vision" title="Dolby Vision">Dolby Vision</a> (streaming) FreeSync (1&2) Up to 4K@60 Hz HDMI 1.4b through IR sensor and IR out port </td></tr> <tr> <th>Fenghuang (<a href="/w/index.php?title=Subor_Z_Plus&action=edit&redlink=1" class="new" title="Subor Z Plus (page does not exist)">Subor Z+</a>) <a href="#cite_note-391">[224]</a><a href="#cite_note-392">[225]</a><a href="#cite_note-eurogamer-subor-393">[226]</a> </th> <td>cancelled <a href="#cite_note-394">[227]</a> </td> <td>14 nm <a href="#cite_note-df-subor-unboxing-395">[228]</a> </td> <td>397 </td> <td><a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a> </td> <td>4 cores 8 threads </td> <td>3.0 </td> <td> </td> <td><a href="/wiki/Graphics_Core_Next#GCN5" title="Graphics Core Next">GCN 5</a> </td> <td>1536:96:32 24 CU </td> <td>1300 </td> <td>3994 </td> <td>41.6 </td> <td>124.8 </td> <td>Double-rate FP16 </td> <td>8 GB </td> <td>GDDR5 256-bit </td> <td>154 </td> <td>1× 2.5" SATA <a href="/wiki/SSD" class="mw-redirect" title="SSD">SSD</a> 1× 2.5" SATA hard drive Easily replaceable drives USB 3.0 </td> <td>Vulkan 1.1, Direct3D 12.1 </td> <td>S/PDIF </td> <td>Subor Z Plus additional modules Windows 10 Enterprise LTSC </td></tr> <tr> <th>Oberon (<a href="/wiki/PlayStation_5" title="PlayStation 5">PS5</a>)<a href="#cite_note-396">[229]</a> </th> <td>Nov 2020 </td> <td rowspan="6">7 nm </td> <td>308 </td> <td rowspan="9"><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a> </td> <td rowspan="5">8 cores 16 threads </td> <td>3.5 (variable) </td> <td rowspan="5">4 MB </td> <td rowspan="7"><a href="/wiki/RDNA_2" title="RDNA 2">RDNA 2</a> </td> <td>2304:144:64 36 CU </td> <td>2233 (variable) </td> <td>10290 (variable) </td> <td>142.9 </td> <td>321.6 </td> <td>Double-rate FP16 <a href="/wiki/Real-time_computing" title="Real-time computing">Real-time</a> <a href="/wiki/Ray_tracing_(graphics)" title="Ray tracing (graphics)">ray tracing</a> <a href="/wiki/Shader#Primitive_shaders" title="Shader">Primitive shaders</a> Custom <a href="/wiki/3D_audio_effect" title="3D audio effect">3D audio</a> blocks </td> <td>16 GB </td> <td>GDDR6 256-bit </td> <td>448 </td> <td>4KBD Custom 5.5 GB/s <a href="/wiki/PCIe" class="mw-redirect" title="PCIe">PCIe</a> 4.0 x4 <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a> SSD PCIe 4.0 <a href="/wiki/M.2" title="M.2">M.2</a> slot Easily replaceable M.2 SSD USB (except PS5 games) </td> <td>Vulkan 1.2 </td> <td>PS5 TEMPEST 3D AudioTech </td> <td>PS VR Dedicated <a href="/wiki/Direct_memory_access" title="Direct memory access">DMA</a> <a href="/wiki/Memory_controller" title="Memory controller">controller</a> and <a href="/wiki/Input/output" title="Input/output">I/O</a> <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a> Custom <a href="/wiki/Cache_coherence" title="Cache coherence">coherency</a> engines and <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a> scrubbers Custom <a href="/wiki/Data_compression" title="Data compression">decompression</a> block <a href="/wiki/High-dynamic-range_video" class="mw-redirect" title="High-dynamic-range video">HDR</a> Up to 4K@120 Hz Up to <a href="/wiki/8K_resolution#7680_×_4320" title="8K resolution">8K</a>@30 Hz </td></tr> <tr> <th rowspan="2">Anaconda (<a href="/wiki/Xbox_Series_X" class="mw-redirect" title="Xbox Series X">Xbox Series X</a>) </th> <td rowspan="4">Nov 2020 </td> <td rowspan="2">360 </td> <td rowspan="2">3.6 (3.8 w/o SMT) </td> <td rowspan="2">3328:208:64 52 CU </td> <td rowspan="2">1825 </td> <td rowspan="2">12147 </td> <td rowspan="2">116.8 </td> <td rowspan="2">379.6 </td> <td rowspan="4">Double-rate FP16 Real-time ray tracing Mesh shaders Variable rate shading <a href="/wiki/Artificial_neural_network" class="mw-redirect" title="Artificial neural network">ANN</a> acceleration </td> <td style="border-bottom: none">10 GB </td> <td style="border-bottom: none">GDDR6 320-bit </td> <td style="border-bottom: none">560 </td> <td rowspan="4">4KBD Custom 2.4 GB/s NVMe SSD Custom expansion card USB 3.1 (except XSX games) </td> <td rowspan="4">DirectX 12 Ultimate </td> <td rowspan="4">Custom spatial audio block MS Project Acoustics Fully Dolby Atmos, DTS:X, and Windows Sonic </td> <td rowspan="4">Custom decompression block HDR <a href="/wiki/Variable_refresh_rate" title="Variable refresh rate">VRR</a> Up to 4K@120 Hz Up to 8K@30 Hz CEC </td></tr> <tr> <td style="border-top: none">6 GB </td> <td style="border-top: none">GDDR6 192-bit<a href="#cite_note-xsxram-397">[j]</a> </td> <td style="border-top: none">336 </td></tr> <tr> <th rowspan="2">Lockhart (<a href="/wiki/Xbox_Series_S" class="mw-redirect" title="Xbox Series S">Xbox Series S</a>) </th> <td rowspan="2">197 </td> <td rowspan="2">3.4 (3.6 w/o SMT) </td> <td rowspan="2">1280:80:32 20 CU </td> <td rowspan="2">1565 </td> <td rowspan="2">4006 </td> <td rowspan="2">50.1 </td> <td rowspan="2">125.2 </td> <td style="border-bottom: none">8 GB </td> <td style="border-bottom: none">GDDR6 128-bit </td> <td style="border-bottom: none">224 </td></tr> <tr> <td style="border-top: none">2 GB </td> <td style="border-top: none">GDDR6 32-bit </td> <td style="border-top: none">56 </td></tr> <tr> <th>Van Gogh "Aerith" (<a href="/wiki/Steam_Deck" title="Steam Deck">Steam Deck</a>)<a href="#cite_note-398">[230]</a> </th> <td>Dec 2021 </td> <td>163 </td> <td rowspan="2">4 cores 8 threads </td> <td rowspan="2">2.4-3.5 </td> <td rowspan="2">2 MB </td> <td rowspan="2">512:32:16 8 CU </td> <td rowspan="2">1000-1600 </td> <td rowspan="2">1000-1600 </td> <td rowspan="2">16-25.6 </td> <td rowspan="2">32-51.2 </td> <td rowspan="2">Double-rate FP16 Real-time ray tracing Variable rate shading </td> <td rowspan="2">16 GB </td> <td rowspan="2"><a href="/wiki/LPDDR5" class="mw-redirect" title="LPDDR5">LPDDR5</a> 128-bit </td> <td>88 </td> <td>64 GB <a href="/wiki/EMMC" class="mw-redirect" title="EMMC">eMMC</a> (PCIe Gen 2 × 1) 256 GB NVMe SSD (PCIe Gen 3 × 4) 512 GB NVMe SSD (PCIe Gen 3 × 4) <a href="/wiki/MicroSD_card" class="mw-redirect" title="MicroSD card">microSD card</a> slot </td> <td rowspan="2">DirectX 9-12 Ultimate, OpenGL 4.6, Vulkan 1.2 </td> <td> </td> <td> </td></tr> <tr> <th>Van Gogh "Sephiroth" (Steam Deck OLED) </th> <td>Nov 2023 </td> <td>6 nm </td> <td>131 </td> <td>102 </td> <td>256 GB NVMe SSD (PCIe Gen 3 × 4) 512 GB NVMe SSD (PCIe Gen 3 × 4) 1 TB NVMe SSD (PCIe Gen 3 × 4) microSD card slot </td> <td> </td> <td> </td></tr> <tr> <th rowspan="2">Viola (PS5 Pro) </th> <td rowspan="2">Nov 2024 </td> <td rowspan="2">4 nm </td> <td rowspan="2">260 </td> <td rowspan="2">8 cores 16 threads </td> <td rowspan="2">3.85 (variable) </td> <td rowspan="2">4 MB </td> <td rowspan="2"><a href="/wiki/RDNA_3" title="RDNA 3">RDNA 3</a> </td> <td rowspan="2">3840:240:120 60 CU </td> <td rowspan="2">2180 (variable) </td> <td rowspan="2">16742 (variable) </td> <td rowspan="2">261.6 </td> <td rowspan="2">523.2 </td> <td rowspan="2">Double-rate FP16 Real-time ray tracing Primitive shaders Custom 3D audio blocks Hardware-accelerated upscaling </td> <td style="border-bottom: none">16 GB </td> <td style="border-bottom: none">GDDR6 256-bit </td> <td style="border-bottom: none">576 </td> <td rowspan="2">4KBD 2 TB NVMe SSD (PCIe Gen 4 × 4) PCIe 4.0 M.2 slot USB </td> <td rowspan="2">Vulkan 1.2 </td> <td rowspan="2">PS5 TEMPEST 3D AudioTech </td> <td rowspan="2">PS VR Dedicated DMA controller and I/O coprocessors Custom coherency engines and cache scrubbers Custom decompression block HDR Up to 4K@120 Hz Up to 8K@60 Hz </td></tr> <tr> <td style="border-top: none">2 GB </td> <td style="border-top: none"><a href="/wiki/DDR5" class="mw-redirect" title="DDR5">DDR5</a> </td> <td style="border-top: none">? </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini" style="float: left; position: relative; top: -15px; right: 0px;"><ul><li class="nv-view"><a href="/wiki/Template:AMD_custom_APU" title="Template:AMD custom APU"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_custom_APU" title="Template talk:AMD custom APU"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_custom_APU" title="Special:EditPage/Template:AMD custom APU"><abbr title="Edit this template">e</abbr></a></li></ul></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-cconfig-373"><a href="#cite_ref-cconfig_373-0">^</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a> : <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> : <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> </li> <li id="cite_note-FLOPS-374"><a href="#cite_ref-FLOPS_374-0">^</a> Precision performance is calculated from the base (or boost) core clock speed based on a <a href="/wiki/Multiply%E2%80%93accumulate_operation#Fused_multiply–add" title="Multiply–accumulate operation">FMA</a> operation. </li> <li id="cite_note-pixel_fillrate-375"><a href="#cite_ref-pixel_fillrate_375-0">^</a> Pixel fillrate is calculated as the number of ROPs multiplied by the base (or boost) core clock speed. </li> <li id="cite_note-texture_fill-376"><a href="#cite_ref-texture_fill_376-0">^</a> Texture fillrate is calculated as the number of TMUs multiplied by the base (or boost) core clock speed. </li> <li id="cite_note-bdhdr-377"><a href="#cite_ref-bdhdr_377-0">^</a> UHD BD is the only video disc format supporting HDR. </li> <li id="cite_note-ramcache-378"><a href="#cite_ref-ramcache_378-0">^</a> Cache </li> <li id="cite_note-xboxdigital-380"><a href="#cite_ref-xboxdigital_380-0">^</a> "Digital" version does not have an optical drive. </li> <li id="cite_note-Rapid_Packed_Math-385"><a href="#cite_ref-Rapid_Packed_Math_385-0">^</a> Feature preview of Rapid Packed Math, introduced in <a href="/wiki/Graphics_Core_Next#GCN5" title="Graphics Core Next">GCN 5</a>. </li> <li id="cite_note-ramswap-387"><a href="#cite_ref-ramswap_387-0">^</a> Swap </li> <li id="cite_note-xsxram-397"><a href="#cite_ref-xsxram_397-0">^</a> A plain 320-bit 20 GB version could be made by just replacing four 1 GB GDDR6 chips by 2 GB ones. </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=78" title="Edit section: See also">edit</a>]</div> <ul><li><a href="/wiki/List_of_AMD_chipsets" title="List of AMD chipsets">List of AMD chipsets</a></li> <li><a href="/wiki/List_of_AMD_FX_microprocessors" class="mw-redirect" title="List of AMD FX microprocessors">List of AMD FX microprocessors</a></li> <li><a href="/wiki/List_of_AMD_graphics_processing_units" title="List of AMD graphics processing units">List of AMD graphics processing units</a></li> <li><a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=79" title="Edit section: Notes">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-fn_2-345">^ <a href="#cite_ref-fn_2_345-0">a</a> <a href="#cite_ref-fn_2_345-1">b</a> <a href="#cite_ref-fn_2_345-2">c</a> <a href="#cite_ref-fn_2_345-3">d</a> <a href="#cite_ref-fn_2_345-4">e</a> <a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shader processors</a> (USPs): <a href="/wiki/Texture_mapping_unit" title="Texture mapping unit">Texture mapping units</a> (TMUs): <a href="/wiki/Render_output_unit" title="Render output unit">Render output units</a> (ROPs). 1 CU (Compute Unit) = 64 USPs: 4 TMUs : 1 ROPs </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=80" title="Edit section: References">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output 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October 4, 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131110170126/http://hexus.net/tech/reviews/cpu/46157-amd-a10-5800k-dual-graphics-evaluation/">Archived</a> from the original on November 10, 2013. Retrieved November 10, 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Review%3A+AMD+A10-5800K+Dual+Graphics+evaluation%E2%80%94CPU&rft.date=2012-10-04&rft_id=http%3A%2F%2Fhexus.net%2Ftech%2Freviews%2Fcpu%2F46157-amd-a10-5800k-dual-graphics-evaluation%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-50"><a href="#cite_ref-50">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.anandtech.com/show/4476/amd-a83850-review/6">"The AMD A8-3850 Review: Llano on the Desktop"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131110172051/http://www.anandtech.com/show/4476/amd-a83850-review/6">Archived</a> from the original on November 10, 2013. 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Retrieved March 23, 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=AMD+FX-670K+CPU+Shows+Up+in+the+Wild&rft.date=2014-03-23&rft.au=btarunr&rft_id=http%3A%2F%2Fwww.techpowerup.com%2F199179%2Famd-fx-670k-cpu-shows-up-in-the-wild.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-63"><a href="#cite_ref-63">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAnton_Shilov2013" class="citation web cs1">Anton Shilov (May 30, 2013). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130607163138/http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html">"AMD's Next-Gen "Kaveri" APUs Will Require New Mainboards"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html">the original</a> on June 7, 2013. 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June 14, 2012. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130903040946/http://arstechnica.com/information-technology/2012/06/amd-to-add-arm-processors-to-boost-chip-security/">Archived</a> from the original on September 3, 2013. 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Wccftech. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200320221314/https://wccftech.com/amd-carrizo-apu-architecture-hot-chips/">Archived</a> from the original on March 20, 2020. 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October 26, 2018. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20230507000803/https://www.reddit.com/r/hardware/comments/9rmj8t/amd_quietly_launches_new_carrizo_apu_a87680/">Archived</a> from the original on May 7, 2023. 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Retrieved June 29, 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Day+of+the+Dead%3A+AMD+Releases+new+Carrizo+FM2%2B+APU%2C+the+A8-7680&rft.date=2018-10-28&rft.au=Cutress%2C+Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F13524%2Famd-new-carrizo-fm2-apu-a8-7680&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-84"><a href="#cite_ref-84">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2016" class="citation news cs1">Cutress, Ian (September 23, 2016). <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/10705/amd-7th-gen-bristol-ridge-and-am4-analysis-a12-9800-b350-a320-chipset">"AMD 7th Gen Bristol Ridge and AM4 Analysis"</a>. Anandtech.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20161120031954/http://www.anandtech.com/show/10705/amd-7th-gen-bristol-ridge-and-am4-analysis-a12-9800-b350-a320-chipset">Archived</a> from the original on November 20, 2016. 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AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+Athlon%E2%84%A2+X4+940&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2071&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-91"><a href="#cite_ref-91">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Bulldozer/AMD-A6-Series%20A6-9400.html">"AMD A6-Series A6-9400 - AD9400AGM23AB / AD9400AGABBOX"</a>. CPU-World. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220609033029/https://www.cpu-world.com/CPUs/Bulldozer/AMD-A6-Series%20A6-9400.html">Archived</a> from the original on June 9, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=AMD+A6-Series+A6-9400+-+AD9400AGM23AB+%2F+AD9400AGABBOX&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FBulldozer%2FAMD-A6-Series%2520A6-9400.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-92"><a href="#cite_ref-92">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2091">"7th Gen A6-9500E APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505233346/https://www.amd.com/en/product/2091">Archived</a> from the original on May 5, 2022. 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Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+PRO+A6-9500+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F6181&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-96"><a href="#cite_ref-96">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2086">"7th Gen A6-9550 APU"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+A6-9550+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2086&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-97"><a href="#cite_ref-97">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2101">"7th Gen A8-9600 APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505233351/https://www.amd.com/en/product/2101">Archived</a> from the original on May 5, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+A8-9600+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2101&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-98"><a href="#cite_ref-98">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6191">"7th Gen AMD PRO A8-9600 APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505234739/https://www.amd.com/en/product/6191">Archived</a> from the original on May 5, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+PRO+A8-9600+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F6191&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-99"><a href="#cite_ref-99">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2106">"7th Gen A10-9700E APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505233322/https://www.amd.com/en/product/2106">Archived</a> from the original on May 5, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+A10-9700E+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2106&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-100"><a href="#cite_ref-100">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6166">"7th Gen AMD PRO A10-9700E APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240822063425/https://www.amd.com/en/product/6166">Archived</a> from the original on August 22, 2024. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+PRO+A10-9700E+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F6166&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-101"><a href="#cite_ref-101">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2111">"7th Gen A10-9700 APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505233322/https://www.amd.com/en/product/2111">Archived</a> from the original on May 5, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+A10-9700+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2111&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-102"><a href="#cite_ref-102">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6161">"7th Gen AMD PRO A10-9700 APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505234526/https://www.amd.com/en/product/6161">Archived</a> from the original on May 5, 2022. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+PRO+A10-9700+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F6161&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-103"><a href="#cite_ref-103">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2116">"7th Gen A12-9800E APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20220505233322/https://www.amd.com/en/product/2116">Archived</a> from the original on May 5, 2022. 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BodNara Korea. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170517063225/https://translate.google.com/translate?sl=auto&tl=en&js=y&prev=_t&hl=en&ie=UTF-8&u=http%3A%2F%2Fwww.bodnara.co.kr%2Fbbs%2Farticle.html%3Fnum%3D134612%26mn%3D4&edit-text=">Archived</a> from the original on May 17, 2017. Retrieved November 12, 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=AMD+Final+Heavy+Equipment+X+Carrier+ZEN+Bristol+Ridge+A12-9800+platform+change&rft.date=2016-09-19&rft.aulast=Sang-ho&rft.aufirst=Lee&rft_id=https%3A%2F%2Ftranslate.google.com%2Ftranslate%3Fsl%3Dauto%26tl%3Den%26js%3Dy%26prev%3D_t%26hl%3Den%26ie%3DUTF-8%26u%3Dhttp%253A%252F%252Fwww.bodnara.co.kr%252Fbbs%252Farticle.html%253Fnum%253D134612%2526mn%253D4%26edit-text%3D&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-105"><a href="#cite_ref-105">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6176">"7th Gen AMD PRO A12-9800E APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240822063426/https://www.amd.com/en/product/6176">Archived</a> from the original on August 22, 2024. Retrieved June 14, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+AMD+PRO+A12-9800E+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F6176&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-106"><a href="#cite_ref-106">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/2121">"7th Gen A12-9800 APU"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=7th+Gen+A12-9800+APU&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F2121&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-107"><a href="#cite_ref-107">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/6171">"7th Gen AMD PRO A12-9800 APU"</a>. AMD. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240822063458/https://www.amd.com/en/product/6171">Archived</a> from the original on August 22, 2024. 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Retrieved September 6, 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Tom%27s+Hardware&rft.atitle=AMD%27s+Ryzen+5+7600X3D+is+no+longer+exclusive+to+the+U.S.+%E2%80%94+the+latest+3D+V-Cache+chip+is+now+available+in+Germany+for+%E2%82%AC329&rft.date=2024-09-05&rft.aulast=Shilov&rft.aufirst=Anton&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fpc-components%2Fcpus%2Famds-ryzen-5-7600x3d-is-no-longer-exclusive-to-the-us-the-latest-3d-v-cache-chip-is-now-available-in-germany-for-euro329&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-157"><a href="#cite_ref-157">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWhyCry2023" class="citation web cs1">WhyCry (July 23, 2023). <a rel="nofollow" class="external text" href="https://videocardz.com/newz/amd-ryzen-5-7500f-reviews-are-out-cpu-to-launch-globally-at-179">"AMD Ryzen 5 7500F reviews are out, CPU to launch globally at $179"</a>. VideoCardz.com. Retrieved July 23, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=VideoCardz.com&rft.atitle=AMD+Ryzen+5+7500F+reviews+are+out%2C+CPU+to+launch+globally+at+%24179&rft.date=2023-07-23&rft.au=WhyCry&rft_id=https%3A%2F%2Fvideocardz.com%2Fnewz%2Famd-ryzen-5-7500f-reviews-are-out-cpu-to-launch-globally-at-179&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-Anandtech-8000G-162">^ <a href="#cite_ref-Anandtech-8000G_162-0">a</a> <a href="#cite_ref-Anandtech-8000G_162-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBonshor2024" class="citation web cs1">Bonshor, Gavin (January 8, 2024). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/21208/amd-unveils-ryzen-8000g-series-processors-zen-4-apus-for-desktop-with-ryzen-ai">"AMD Unveils Ryzen 8000G Series Processors: Zen 4 APUs For Desktop with Ryzen AI"</a>. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. Retrieved January 9, 2024.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AnandTech&rft.atitle=AMD+Unveils+Ryzen+8000G+Series+Processors%3A+Zen+4+APUs+For+Desktop+with+Ryzen+AI&rft.date=2024-01-08&rft.aulast=Bonshor&rft.aufirst=Gavin&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F21208%2Famd-unveils-ryzen-8000g-series-processors-zen-4-apus-for-desktop-with-ryzen-ai&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-165"><a href="#cite_ref-165">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-3-pro-8300g.html">"AMD Ryzen 5 PRO 8300G"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+8300G&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-3-pro-8300g.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-166"><a href="#cite_ref-166">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-3-pro-8300ge.html">"AMD Ryzen 5 PRO 8300GE"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+8300GE&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-3-pro-8300ge.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-167"><a href="#cite_ref-167">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-5-pro-8500g.html">"AMD Ryzen 5 PRO 8500G"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+8500G&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-5-pro-8500g.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-168"><a href="#cite_ref-168">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-5-pro-8500ge.html">"AMD Ryzen 5 PRO 8500GE"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+8500GE&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-5-pro-8500ge.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-169"><a href="#cite_ref-169">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-5-pro-8600g.html">"AMD Ryzen 5 PRO 8600G"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+8600G&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-5-pro-8600g.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-170"><a href="#cite_ref-170">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/processors/desktops/ryzen-pro/8000-series/amd-ryzen-7-pro-8700g.html">"AMD Ryzen 7 PRO 8700G"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+8700G&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fprocessors%2Fdesktops%2Fryzen-pro%2F8000-series%2Famd-ryzen-7-pro-8700g.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-173"><a href="#cite_ref-173">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Jaguar/AMD-Opteron%20X%20series%20X1150.html">"AMD Opteron X1150 - OX1150IPJ44HM"</a>. CPUWorld. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231113185358/https://www.cpu-world.com/CPUs/Jaguar/AMD-Opteron%20X%20series%20X1150.html">Archived</a> from the original on November 13, 2023. Retrieved November 13, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPUWorld&rft.atitle=AMD+Opteron+X1150+-+OX1150IPJ44HM&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FJaguar%2FAMD-Opteron%2520X%2520series%2520X1150.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-174"><a href="#cite_ref-174">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/press-releases/amd-launches-the-2013may29">"AMD Launches the AMD Opteron X-Series Family: the Industry's Highest Performance Small Core x86 Server Processors"</a>. AMD (Press release). May 29, 2013. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20240822063428/https://www.amd.com/en/newsroom/press-release-search.html#sortCriteria=%40amd_release_date%20descending">Archived</a> from the original on August 22, 2024. Retrieved November 13, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Launches+the+AMD+Opteron+X-Series+Family%3A+the+Industry%E2%80%99s+Highest+Performance+Small+Core+x86+Server+Processors&rft.date=2013-05-29&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fpress-releases%2Famd-launches-the-2013may29&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-175"><a href="#cite_ref-175">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKennedy2017" class="citation news cs1">Kennedy, Patrick (June 5, 2017). <a rel="nofollow" class="external text" href="https://www.servethehome.com/new-hpe-proliant-microserver-gen10-powered-amd-opteron-x3000-apus/">"New HPE ProLiant MicroServer Gen10 Powered by AMD Opteron X3000 APUs"</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170709131741/https://www.servethehome.com/new-hpe-proliant-microserver-gen10-powered-amd-opteron-x3000-apus/">Archived</a> from the original on July 9, 2017. Retrieved June 5, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=New+HPE+ProLiant+MicroServer+Gen10+Powered+by+AMD+Opteron+X3000+APUs&rft.date=2017-06-05&rft.aulast=Kennedy&rft.aufirst=Patrick&rft_id=https%3A%2F%2Fwww.servethehome.com%2Fnew-hpe-proliant-microserver-gen10-powered-amd-opteron-x3000-apus%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-OpteronX3000-176">^ <a href="#cite_ref-OpteronX3000_176-0">a</a> <a href="#cite_ref-OpteronX3000_176-1">b</a> <a href="#cite_ref-OpteronX3000_176-2">c</a> <a href="#cite_ref-OpteronX3000_176-3">d</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20170520180537/https://www.amd.com/en/opteron">"Opteron Family"</a>. AMD. Archived from <a rel="nofollow" class="external text" href="https://www.amd.com/en/opteron">the original</a> on May 20, 2017. Retrieved June 5, 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=Opteron+Family&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fopteron&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-179"><a href="#cite_ref-179">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3216.html">"AMD Opteron X3216 - OX3216AAY23KA"</a>. CPUWorld. Retrieved November 13, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPUWorld&rft.atitle=AMD+Opteron+X3216+-+OX3216AAY23KA&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FBulldozer%2FAMD-Opteron%2520X3000%2520series%2520X3216.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-180"><a href="#cite_ref-180">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3418.html">"AMD Opteron X3418 - OX3418AAY43KA"</a>. CPUWorld. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231113185355/https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3418.html">Archived</a> from the original on November 13, 2023. Retrieved November 13, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPUWorld&rft.atitle=AMD+Opteron+X3418+-+OX3418AAY43KA&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FBulldozer%2FAMD-Opteron%2520X3000%2520series%2520X3418.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-181"><a href="#cite_ref-181">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3421.html">"AMD Opteron X3421 - OX3421AAY43KA"</a>. CPUWorld. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20231113185358/https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20X3000%20series%20X3421.html">Archived</a> from the original on November 13, 2023. Retrieved November 13, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPUWorld&rft.atitle=AMD+Opteron+X3421+-+OX3421AAY43KA&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FBulldozer%2FAMD-Opteron%2520X3000%2520series%2520X3421.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-CPUWorldA8-187">^ <a href="#cite_ref-CPUWorldA8_187-0">a</a> <a href="#cite_ref-CPUWorldA8_187-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.cpu-world.com/news_2013/2013031901_AMD_lists_A8-4557M_and_A10-4657M_mobile_APUs.html">"AMD lists A8-4557M and A10-4657M mobile APUs"</a>. www.cpu-world.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180917105410/http://www.cpu-world.com/news_2013/2013031901_AMD_lists_A8-4557M_and_A10-4657M_mobile_APUs.html">Archived</a> from the original on September 17, 2018. Retrieved September 17, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.cpu-world.com&rft.atitle=AMD+lists+A8-4557M+and+A10-4657M+mobile+APUs&rft_id=http%3A%2F%2Fwww.cpu-world.com%2Fnews_2013%2F2013031901_AMD_lists_A8-4557M_and_A10-4657M_mobile_APUs.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-188"><a href="#cite_ref-188">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://techreport.com/news/24482/amd-intros-35w-richland-mobile-apus">"AMD intros 35W Richland mobile APUs"</a>. March 12, 2013. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130314203047/http://techreport.com/news/24482/amd-intros-35w-richland-mobile-apus">Archived</a> from the original on March 14, 2013. Retrieved November 10, 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+intros+35W+Richland+mobile+APUs&rft.date=2013-03-12&rft_id=http%3A%2F%2Ftechreport.com%2Fnews%2F24482%2Famd-intros-35w-richland-mobile-apus&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-189"><a href="#cite_ref-189">^</a> Poeter, Damon. (March 12, 2013) <a rel="nofollow" class="external text" href="https://www.pcmag.com/article2/0,2817,2416506,00.asp">AMD Bakes New Interface Capabilities Into Richland APUs | News & Opinion</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170712141651/https://www.pcmag.com/article2/0,2817,2416506,00.asp">Archived</a> July 12, 2017, at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a> </li> <li id="cite_note-193"><a href="#cite_ref-193">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20131203121409/http://www.technationnews.com/2013/11/24/amd-kaveri-apu-with-steamrollerb-core-features-20-cpu-and-30-gpu-performance-uplift-over-richland-platform-details-unveiled/">"AMD Kaveri APU with SteamrollerB Core Features 20% CPU and 30% GPU Performance Uplift over Richland – Platform Details Unveiled | TechNationNews.com"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.technationnews.com/2013/11/24/amd-kaveri-apu-with-steamrollerb-core-features-20-cpu-and-30-gpu-performance-uplift-over-richland-platform-details-unveiled/">the original</a> on December 3, 2013. Retrieved November 26, 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Kaveri+APU+with+SteamrollerB+Core+Features+20%25+CPU+and+30%25+GPU+Performance+Uplift+over+Richland+%E2%80%93+Platform+Details+Unveiled+%26%23124%3B+TechNationNews.com&rft_id=http%3A%2F%2Fwww.technationnews.com%2F2013%2F11%2F24%2Famd-kaveri-apu-with-steamrollerb-core-features-20-cpu-and-30-gpu-performance-uplift-over-richland-platform-details-unveiled%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-AMDGen7-198">^ <a href="#cite_ref-AMDGen7_198-0">a</a> <a href="#cite_ref-AMDGen7_198-1">b</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2016" class="citation news cs1">Cutress, Ian (June 1, 2016). <a rel="nofollow" class="external text" href="http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks">"AMD Announces 7th Generation APU"</a>. Anandtech.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20160602125009/http://www.anandtech.com/show/10362/amd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks">Archived</a> from the original on June 2, 2016. Retrieved June 1, 2016.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Anandtech.com&rft.atitle=AMD+Announces+7th+Generation+APU&rft.date=2016-06-01&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=http%3A%2F%2Fwww.anandtech.com%2Fshow%2F10362%2Famd-7th-generation-apu-bristol-ridge-stoney-ridge-for-notebooks&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-201"><a href="#cite_ref-201">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.notebookcheck.net/AMD-A10-9620P-SoC-Benchmarks-and-Specs.234384.0.html">"AMD A10-9620P SoC - Benchmarks and Specs"</a>. Notebookcheck.net. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170825023107/https://www.notebookcheck.net/AMD-A10-9620P-SoC-Benchmarks-and-Specs.234384.0.html">Archived</a> from the original on August 25, 2017. Retrieved July 20, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Notebookcheck.net&rft.atitle=AMD+A10-9620P+SoC+-+Benchmarks+and+Specs&rft_id=https%3A%2F%2Fwww.notebookcheck.net%2FAMD-A10-9620P-SoC-Benchmarks-and-Specs.234384.0.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-202"><a href="#cite_ref-202">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.notebookcheck.net/AMD-A12-9720P-SoC-Benchmarks-and-Specs.234448.0.html">"AMD A12-9720P SoC - Benchmarks and Specs"</a>. Notebookcheck.net. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170825023021/https://www.notebookcheck.net/AMD-A12-9720P-SoC-Benchmarks-and-Specs.234448.0.html">Archived</a> from the original on August 25, 2017. Retrieved July 20, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Notebookcheck.net&rft.atitle=AMD+A12-9720P+SoC+-+Benchmarks+and+Specs&rft_id=https%3A%2F%2Fwww.notebookcheck.net%2FAMD-A12-9720P-SoC-Benchmarks-and-Specs.234448.0.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-203"><a href="#cite_ref-203">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://store.hp.com/us/en/pdp/hp-pavilion-laptop---17z-touch-optional-1gz59av-1">"HP Pavilion 17 - HP® Official Store"</a>. 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Retrieved July 20, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Store.hp.com&rft.atitle=HP+Pavilion+17+-+HP%C2%AE+Official+Store&rft_id=http%3A%2F%2Fstore.hp.com%2Fus%2Fen%2Fpdp%2Fhp-pavilion-laptop---17z-touch-optional-1gz59av-1&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-209"><a href="#cite_ref-209">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-3780u-microsoft-surface-edition">"AMD Ryzen 7 3780U Microsoft Surface® Edition"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+7+3780U+Microsoft+Surface%C2%AE+Edition&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-3780u-microsoft-surface-edition&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-amd-r3750h-210"><a href="#cite_ref-amd-r3750h_210-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-3750h">"AMD Ryzen 7 3750H Mobile Processor with Radeon RX Vega 10 Graphics"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+7+3750H+Mobile+Processor+with+Radeon+RX+Vega+10+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-3750h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-211"><a href="#cite_ref-211">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/gpudb/3053/radeon-rx-vega-10-mobile">"AMD Radeon RX Vega 10 Mobile Specs | TechPowerUp GPU Database"</a>. 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Retrieved January 8, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+5+3550H+Mobile+Processor+with+Radeon+Vega+8+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-3550h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-217"><a href="#cite_ref-217">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/gpudb/3042/radeon-rx-vega-8-mobile">"AMD Radeon Vega 8 Specs | TechPowerUp GPU Database"</a>. Techpowerup.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Radeon+Vega+8+Specs+%26%23124%3B+TechPowerUp+GPU+Database&rft.pub=Techpowerup.com&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Fgpudb%2F3042%2Fradeon-rx-vega-8-mobile&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-218"><a href="#cite_ref-218">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-3500c">"AMD Ryzen 5 3500C"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+5+3500C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-3500c&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-amd-r3500u-219"><a href="#cite_ref-amd-r3500u_219-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-3500u">"AMD Ryzen 5 3500U Mobile Processor with Radeon Vega 8 Graphics"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+5+3500U+Mobile+Processor+with+Radeon+Vega+8+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-3500u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-220"><a href="#cite_ref-220">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-3450u">"AMD Ryzen 5 3450U Processor"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+5+3450U+Processor&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-3450u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-221"><a href="#cite_ref-221">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-3350uhttps://www.amd.com/en/products/apu/amd-ryzen-3-3350u">"AMD Ryzen 3 3350U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+3350U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-3350uhttps%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-3350u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-222"><a href="#cite_ref-222">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/gpudb/3079/radeon-vega-6">"AMD Radeon Vega 6 Mobile Specs | TechPowerUp GPU Database"</a>. Techpowerup.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Radeon+Vega+6+Mobile+Specs+%26%23124%3B+TechPowerUp+GPU+Database&rft.pub=Techpowerup.com&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Fgpudb%2F3079%2Fradeon-vega-6&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-amd-r3300u-223"><a href="#cite_ref-amd-r3300u_223-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-3300u">"AMD Ryzen 3 3300U Mobile Processor with Radeon Vega 6 Graphics"</a>. Retrieved January 6, 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+3+3300U+Mobile+Processor+with+Radeon+Vega+6+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-3300u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-224"><a href="#cite_ref-224">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-pro-3300u">"AMD Ryzen 3 PRO 3300U Mobile Processor with Radeon Vega 6 Graphics"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+3+PRO+3300U+Mobile+Processor+with+Radeon+Vega+6+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-pro-3300u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-225"><a href="#cite_ref-225">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-3500u">"AMD Ryzen 5 PRO 3500U Mobile Processor with Radeon Vega 8 Graphics"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+5+PRO+3500U+Mobile+Processor+with+Radeon+Vega+8+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-3500u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-226"><a href="#cite_ref-226">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-3700u">"AMD Ryzen 7 PRO 3700U Mobile Processor with Radeon Vega 10 Graphics"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+Ryzen+7+PRO+3700U+Mobile+Processor+with+Radeon+Vega+10+Graphics&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-3700u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-227"><a href="#cite_ref-227">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFCutress2020" class="citation web cs1">Cutress, Ian (January 6, 2020). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/15324/amd-ryzen-4000-mobile-apus-7nm-8core-on-both-15w-and-45w-coming-q1">"AMD Ryzen 4000 Mobile APUs: 7nm, 8-core on both 15W and 45W, Coming Q1"</a>. anandtech.com. <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200107000008/https://www.anandtech.com/show/15324/amd-ryzen-4000-mobile-apus-7nm-8core-on-both-15w-and-45w-coming-q1">Archived</a> from the original on January 7, 2020. Retrieved January 7, 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=anandtech.com&rft.atitle=AMD+Ryzen+4000+Mobile+APUs%3A+7nm%2C+8-core+on+both+15W+and+45W%2C+Coming+Q1&rft.date=2020-01-06&rft.aulast=Cutress&rft.aufirst=Ian&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F15324%2Famd-ryzen-4000-mobile-apus-7nm-8core-on-both-15w-and-45w-coming-q1&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-228"><a href="#cite_ref-228">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAlcorn2020" class="citation web cs1">Alcorn, Paul (January 7, 2020). <a rel="nofollow" class="external text" href="https://www.tomshardware.com/news/amd-launches-threadripper-3990x-and-ryzen-4000-renoir-apus">"AMD Launches Threadripper 3990X and Ryzen 4000 'Renoir' APUs"</a>. tomshardware.com. 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Retrieved January 7, 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=tomshardware.com&rft.atitle=AMD+Launches+Threadripper+3990X+and+Ryzen+4000+%27Renoir%27+APUs&rft.date=2020-01-07&rft.aulast=Alcorn&rft.aufirst=Paul&rft_id=https%3A%2F%2Fwww.tomshardware.com%2Fnews%2Famd-launches-threadripper-3990x-and-ryzen-4000-renoir-apus&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-229"><a href="#cite_ref-229">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFGartenberg2020" class="citation web cs1">Gartenberg, Chaim (January 6, 2020). <a rel="nofollow" class="external text" href="https://www.theverge.com/2020/1/6/21054007/amd-7nm-ryzen-4000-cpu-ces-2020-intel-competition-laptop-processors-zen-2">"AMD's 7nm Ryzen 4000 CPUs are here to take on Intel's 10nm Ice Lake laptop chips"</a>. theverge.com. <a href="/wiki/The_Verge" title="The Verge">The Verge</a>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20200106234532/https://www.theverge.com/2020/1/6/21054007/amd-7nm-ryzen-4000-cpu-ces-2020-intel-competition-laptop-processors-zen-2">Archived</a> from the original on January 6, 2020. Retrieved January 7, 2020.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=theverge.com&rft.atitle=AMD%27s+7nm+Ryzen+4000+CPUs+are+here+to+take+on+Intel%27s+10nm+Ice+Lake+laptop+chips&rft.date=2020-01-06&rft.aulast=Gartenberg&rft.aufirst=Chaim&rft_id=https%3A%2F%2Fwww.theverge.com%2F2020%2F1%2F6%2F21054007%2Famd-7nm-ryzen-4000-cpu-ces-2020-intel-competition-laptop-processors-zen-2&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-Renoir-230"><a href="#cite_ref-Renoir_230-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/264801/amd-renoir-die-shot-pictured">"AMD "Renoir" die Shot Pictured"</a>. March 16, 2020. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20201209212449/https://www.techpowerup.com/264801/amd-renoir-die-shot-pictured">Archived</a> from the original on December 9, 2020. Retrieved June 25, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=AMD+%22Renoir%22+die+Shot+Pictured&rft.date=2020-03-16&rft_id=https%3A%2F%2Fwww.techpowerup.com%2F264801%2Famd-renoir-die-shot-pictured&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-239"><a href="#cite_ref-239">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-4600HS">"AMD Ryzen 5 4600HS"</a>. AMD. Retrieved November 10, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+4600HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-4600HS&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988">[<a href="/wiki/Wikipedia:Link_rot" title="Wikipedia:Link rot">permanent dead link</a>‍] </li> <li id="cite_note-240"><a href="#cite_ref-240">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Zen/AMD-Ryzen%205%20Mobile%204600HS.html">"AMD Ryzen 5 4600HS Mobile processor"</a>. CPUWorld. Retrieved November 10, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPUWorld&rft.atitle=AMD+Ryzen+5+4600HS+Mobile+processor&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FZen%2FAMD-Ryzen%25205%2520Mobile%25204600HS.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-241"><a href="#cite_ref-241">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.notebookcheck.com/AMD-Ryzen-7-4600HS-Laptop-Prozessor-Benchmarks-und-Specs.449836.0.html">"AMD Ryzen 7 4600HS Laptop Processor"</a>. Notebookcheck. Retrieved November 10, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Notebookcheck&rft.atitle=AMD+Ryzen+7+4600HS+Laptop+Processor&rft_id=https%3A%2F%2Fwww.notebookcheck.com%2FAMD-Ryzen-7-4600HS-Laptop-Prozessor-Benchmarks-und-Specs.449836.0.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-246"><a href="#cite_ref-246">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/cpu-specs/ryzen-5-5500u.c2372">"AMD Ryzen 5 5500U Specs"</a>. TechPowerUp. Retrieved September 17, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=AMD+Ryzen+5+5500U+Specs&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Fcpu-specs%2Fryzen-5-5500u.c2372&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-251"><a href="#cite_ref-251">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-5800u">"AMD Ryzen 7 5800U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+5800U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-5800u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-253"><a href="#cite_ref-253">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5600u">"AMD Ryzen 5 5600U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5600U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5600u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-254"><a href="#cite_ref-254">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5560u">"AMD Ryzen 5 5560U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5560U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5560u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-255"><a href="#cite_ref-255">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-5400u">"AMD Ryzen 3 5400U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+5400U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-5400u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-256"><a href="#cite_ref-256">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Zen/AMD-Ryzen%203%20Mobile%205400U.html">"AMD Ryzen 3 5400U Mobile processor - 100-000000288"</a>. CPU-World. Retrieved September 17, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=AMD+Ryzen+3+5400U+Mobile+processor+-+100-000000288&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FZen%2FAMD-Ryzen%25203%2520Mobile%25205400U.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-257"><a href="#cite_ref-257">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-pro-5450u">"AMD Ryzen 3 PRO 5450U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+PRO+5450U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-pro-5450u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-258"><a href="#cite_ref-258">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-5650u">"AMD Ryzen 5 PRO 5650U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+5650U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-5650u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-259"><a href="#cite_ref-259">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-5850u">"AMD Ryzen 7 PRO 5850U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+5850U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-5850u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-263"><a href="#cite_ref-263">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-5980hx">"AMD Ryzen 9 5980HX"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+9+5980HX&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-9-5980hx&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-265"><a href="#cite_ref-265">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-5980hs">"AMD Ryzen 9 5980HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+9+5980HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-9-5980hs&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-266"><a href="#cite_ref-266">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-5900hx">"AMD Ryzen 9 5900HX"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+9+5900HX&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-9-5900hx&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-267"><a href="#cite_ref-267">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-5900hs">"AMD Ryzen 9 5900HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+9+5900HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-9-5900hs&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-268"><a href="#cite_ref-268">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-5800h">"AMD Ryzen 7 5800H"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+5800H&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-5800h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-269"><a href="#cite_ref-269">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techpowerup.com/cpu-specs/ryzen-7-5800h.c2368">"AMD Ryzen 7 5800H Specs"</a>. TechPowerUp. Retrieved September 17, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=AMD+Ryzen+7+5800H+Specs&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Fcpu-specs%2Fryzen-7-5800h.c2368&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-270"><a href="#cite_ref-270">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-5800hs">"AMD Ryzen 7 5800HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+5800HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-5800hs&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-271"><a href="#cite_ref-271">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5600h">"AMD Ryzen 5 5600H"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5600H&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5600h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-272"><a href="#cite_ref-272">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/Zen/AMD-Ryzen%205%20Mobile%205600H.html">"AMD Ryzen 5 5600H Mobile processor - 100-000000296"</a>. CPU-World. Retrieved September 17, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=CPU-World&rft.atitle=AMD+Ryzen+5+5600H+Mobile+processor+-+100-000000296&rft_id=https%3A%2F%2Fwww.cpu-world.com%2FCPUs%2FZen%2FAMD-Ryzen%25205%2520Mobile%25205600H.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-273"><a href="#cite_ref-273">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5600hs">"AMD Ryzen 5 5600HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5600HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5600hs&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-279"><a href="#cite_ref-279">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-5825u">"AMD Ryzen 7 5825U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+5825U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-5825u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-281"><a href="#cite_ref-281">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5625u">"AMD Ryzen 5 5625U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5625U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5625u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-282"><a href="#cite_ref-282">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-5125c">"AMD Ryzen 3 5125C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+5125C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-5125c&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-283"><a href="#cite_ref-283">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-pro-5475u">"AMD Ryzen 3 PRO 5475U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+PRO+5475U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-pro-5475u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-284"><a href="#cite_ref-284">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-5675u">"AMD Ryzen 5 PRO 5675U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+5675U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-5675u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-285"><a href="#cite_ref-285">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-5875u">"AMD Ryzen 7 PRO 5875U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+5875U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-5875u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-286"><a href="#cite_ref-286">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-3-5425C">"AMD Ryzen 3 5425C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+3+5425C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-3-5425C&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-287"><a href="#cite_ref-287">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-5625C">"AMD Ryzen 5 5625C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+5625C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-5625C&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-288"><a href="#cite_ref-288">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-5825C">"AMD Ryzen 7 5825C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+5825C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-5825C&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-292"><a href="#cite_ref-292">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/press-releases/2022-01-04-amd-unveils-new-ryzen-mobile-processors-uniting-zen-3-core-amd-rdna-2">"AMD Unveils New Ryzen Mobile Processors Uniting "Zen 3+" core with AMD RDNA 2 Graphics in Powerhouse Design"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Unveils+New+Ryzen+Mobile+Processors+Uniting+%E2%80%9CZen+3%2B%E2%80%9D+core+with+AMD+RDNA+2+Graphics+in+Powerhouse+Design&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fpress-releases%2F2022-01-04-amd-unveils-new-ryzen-mobile-processors-uniting-zen-3-core-amd-rdna-2&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-294"><a href="#cite_ref-294">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-6650u">"AMD Ryzen 5 PRO 6650U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+6650U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-6650u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-295"><a href="#cite_ref-295">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-6650h">"AMD Ryzen 5 PRO 6650H"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+6650H&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-6650h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-296"><a href="#cite_ref-296">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-5-pro-6650HS">"AMD Ryzen 5 PRO 6650HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+5+PRO+6650HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-5-pro-6650HS&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-297"><a href="#cite_ref-297">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-6850u">"AMD Ryzen 7 PRO 6850U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+6850U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-6850u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-298"><a href="#cite_ref-298">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-6850h">"AMD Ryzen 7 PRO 6850H"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+6850H&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-6850h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-299"><a href="#cite_ref-299">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-7-pro-6850HS">"AMD Ryzen 7 PRO 6850HS"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+7+PRO+6850HS&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-7-pro-6850HS&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-300"><a href="#cite_ref-300">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-pro-6950h">"AMD Ryzen 9 PRO 6950H"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Ryzen+9+PRO+6950H&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-ryzen-9-pro-6950h&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-301"><a href="#cite_ref-301">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-ryzen-9-pro-6950HS">"AMD Ryzen 9 PRO 6950HS"</a>. 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Anandtech.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150623162711/http://www.anandtech.com/show/4003/previewing-amds-brazos-part-1-more-details-on-zacateontario-and-fusion/2">Archived</a> from the original on June 23, 2015. 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Retrieved April 25, 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=TechPowerUp&rft.atitle=AMD+Radeon+Vega+3+Mobile+Specs&rft_id=https%3A%2F%2Fwww.techpowerup.com%2Fgpu-specs%2Fradeon-vega-3-mobile.c3592&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-327"><a href="#cite_ref-327">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-athlon-gold-7220u">"AMD Athlon™ Gold 7220U"</a>. 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Retrieved September 21, 2022.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=AMD+Ryzen+7020+Series+Processors+for+Mobile+Bring+High-End+Performance+and+Long+Battery+Life+to+Everyday+Users&rft.date=2022-09-20&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fpress-releases%2F2022-09-20-amd-ryzen-7020-series-processors-for-mobile-bring-high-end-performance&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-329"><a href="#cite_ref-329">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/products/apu/amd-athlon-silver-7120u">"AMD Athlon™ Silver 7120U"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Athlon%E2%84%A2+Silver+7120U&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproducts%2Fapu%2Famd-athlon-silver-7120u&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-330"><a href="#cite_ref-330">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/13326">"AMD Athlon Gold 7220C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Athlon+Gold+7220C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F13326&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-331"><a href="#cite_ref-331">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en/product/13331">"AMD Athlon Silver 7120C"</a>. AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=AMD+Athlon+Silver+7120C&rft_id=https%3A%2F%2Fwww.amd.com%2Fen%2Fproduct%2F13331&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-332"><a href="#cite_ref-332">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/us/press-releases/Pages/apu-embedded-systems-2011jan19.aspx">"Welcome to AMD - Processors - Graphics and Technology - AMD"</a>. Amd.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20131202233529/http://www.amd.com/us/press-releases/Pages/apu-embedded-systems-2011jan19.aspx">Archived</a> from the original on December 2, 2013. Retrieved July 20, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Amd.com&rft.atitle=Welcome+to+AMD+-+Processors+-+Graphics+and+Technology+-+AMD&rft_id=https%3A%2F%2Fwww.amd.com%2Fus%2Fpress-releases%2FPages%2Fapu-embedded-systems-2011jan19.aspx&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-335"><a href="#cite_ref-335">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.amd.com/en-us/products/embedded/processors/g-series">"Embedded Products - High Performance GPU - AMD"</a>. Amd.com. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180102145417/http://www.amd.com/en-us/products/embedded/processors/g-series">Archived</a> from the original on January 2, 2018. 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Cpu-world.com. July 6, 2022. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20180907221419/http://www.cpu-world.com/CPUs/Bulldozer/AMD-G-Series%20GX-420GI.html">Archived</a> from the original on September 7, 2018. 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AMD.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=AMD&rft.atitle=Product+Brief%3A+AMD+Ryzen+Embedded+V2000+Processor+Family&rft_id=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2Fdocuments%2Fv2000-product-brief.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-Unveil-366"><a href="#cite_ref-Unveil_366-0">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://ir.amd.com/news-events/press-releases/detail/979/amd-unveils-amd-ryzen-embedded-v2000-processors-with">"AMD Unveils AMD Ryzen Embedded V2000 Processors with Enhanced Performance and Power Efficiency"</a>. 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Retrieved October 28, 2018.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Hands-On%3A+Subor+Z+Plus+Chinese+PC%2FConsole+Hybrid+-+Ryzen%2BVega+AMD+Analysis%21&rft.pub=Eurogamer&rft.date=2018-09-15&rft.aulast=Leadbetter&rft.aufirst=Leadbetter&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3Dx0KSJg2sqJM&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> <li id="cite_note-396"><a href="#cite_ref-396">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith2019" class="citation news cs1">Smith, Ryan (April 16, 2019). <a rel="nofollow" class="external text" href="https://www.anandtech.com/show/14224/sony-teases-nextgen-playstation-custom-amd-chip-with-zen-2-cpu-navi-gpu-ssd-too">"Sony Teases Next-Gen PlayStation: Custom AMD Chip with Zen 2 CPU & Navi GPU, SSD Too"</a>. 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Retrieved July 18, 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=steamdeck.com&rft.atitle=Tech+Specs&rft_id=https%3A%2F%2Fwww.steamdeck.com%2Fen%2Ftech&rfr_id=info%3Asid%2Fen.wikipedia.org%3AList+of+AMD+processors+with+3D+graphics" class="Z3988"> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=List_of_AMD_processors_with_3D_graphics&action=edit&section=81" title="Edit section: External links">edit</a>]</div> <ul><li><a rel="nofollow" class="external text" href="https://www.amd.com/us/products/technologies/apu/Pages/apu.aspx">AMD Accelerated Processing Units official website</a></li> <li><a rel="nofollow" class="external text" href="http://products.amd.com/en-us/">Technical specification AMD products</a></li> <li><a rel="nofollow" class="external text" href="https://www.amd.com/us/products/Pages/products.aspx">AMD products and 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.navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="AMD_processors178" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:AMD_processors" title="Template:AMD processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_processors" title="Template talk:AMD processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_processors" title="Special:EditPage/Template:AMD processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_processors178" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_AMD_processors" title="List of AMD processors">AMD processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_AMD_processors" title="List of AMD processors">Processors</a> <ul><li><a href="/wiki/List_of_AMD_K5_processors" title="List of AMD K5 processors">K5</a></li> <li><a href="/wiki/List_of_AMD_K6_processors" title="List of AMD K6 processors">K6</a></li> <li><a href="/wiki/List_of_AMD_Athlon_processors" title="List of AMD Athlon processors">Athlon</a> <ul><li><a href="/wiki/List_of_AMD_Athlon_XP_processors" title="List of AMD Athlon XP processors">XP</a></li> <li><a href="/wiki/List_of_AMD_Athlon_64_processors" title="List of AMD Athlon 64 processors">64</a></li> <li><a href="/wiki/List_of_AMD_Athlon_X2_processors" title="List of AMD Athlon X2 processors">X2</a></li> <li><a href="/wiki/List_of_AMD_Athlon_II_processors" title="List of AMD Athlon II processors">II</a></li></ul></li> <li><a href="/wiki/List_of_AMD_Phenom_processors" title="List of AMD Phenom processors">Phenom</a></li> <li><a href="/wiki/List_of_AMD_FX_processors" title="List of AMD FX processors">FX</a></li> <li><a href="/wiki/List_of_AMD_Ryzen_processors" title="List of AMD Ryzen processors">Ryzen</a></li> <li><a href="/wiki/List_of_AMD_Duron_processors" title="List of AMD Duron processors">Duron</a></li> <li><a href="/wiki/List_of_AMD_Sempron_processors" title="List of AMD Sempron processors">Sempron</a></li> <li><a href="/wiki/List_of_AMD_Turion_processors" title="List of AMD Turion processors">Turion</a></li> <li><a href="/wiki/List_of_AMD_Opteron_processors" title="List of AMD Opteron processors">Opteron</a></li> <li><a href="/wiki/List_of_AMD_Epyc_processors" class="mw-redirect" title="List of AMD Epyc processors">Epyc</a></li></ul></li> <li><a class="mw-selflink selflink">APUs</a></li> <li><a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_AMD_chipsets" title="List of AMD chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_AMD_CPU_microarchitectures" title="List of AMD CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K5" title="AMD K5">K5</a></li> <li><a href="/wiki/AMD_K6" title="AMD K6">K6</a></li> <li><a href="/wiki/Athlon" title="Athlon">Athlon/K7</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">x86-64 desktop</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K8" title="AMD K8">K8</a></li> <li><a href="/wiki/AMD_K9" title="AMD K9">K9</a></li> <li><a href="/wiki/AMD_10h" title="AMD 10h">K10 (aka 10h)</a></li> <li>15h <ul><li><a href="/wiki/Bulldozer_(microarchitecture)" title="Bulldozer (microarchitecture)">Bulldozer</a></li> <li><a href="/wiki/Piledriver_(microarchitecture)" title="Piledriver (microarchitecture)">Piledriver</a></li> <li><a href="/wiki/Steamroller_(microarchitecture)" title="Steamroller (microarchitecture)">Steamroller</a></li> <li><a href="/wiki/Excavator_(microarchitecture)" title="Excavator (microarchitecture)">Excavator</a></li></ul></li> <li><a href="/wiki/Zen_(microarchitecture)" title="Zen (microarchitecture)">Zen</a> <ul><li><a href="/wiki/Zen_(first_generation)" title="Zen (first generation)">1st gen</a></li> <li><a href="/wiki/Zen%2B" title="Zen+">Zen+</a></li> <li><a href="/wiki/Zen_2" title="Zen 2">Zen 2</a></li> <li><a href="/wiki/Zen_3" title="Zen 3">Zen 3</a></li> <li><a href="/wiki/Zen_3%2B" class="mw-redirect" title="Zen 3+">Zen 3+</a></li> <li><a href="/wiki/Zen_4" title="Zen 4">Zen 4</a></li> <li><a href="/wiki/Zen_5" title="Zen 5">Zen 5</a></li> <li><a href="/wiki/Zen_6" title="Zen 6">Zen 6</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">x86-64 low-power</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bobcat_(microarchitecture)" title="Bobcat (microarchitecture)">Bobcat (aka 14h)</a></li> <li>16h <ul><li><a href="/wiki/Jaguar_(microarchitecture)" title="Jaguar (microarchitecture)">Jaguar</a></li> <li><a href="/wiki/Puma_(microarchitecture)" title="Puma (microarchitecture)">Puma</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_architecture_family#ARMv8-A" title="ARM architecture family">ARM64</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_K12" title="AMD K12">K12 (aka 12h)</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Athlon" title="Athlon">Athlon</a></li> <li><a href="/wiki/Ryzen" title="Ryzen">Ryzen</a></li> <li><a href="/wiki/Threadripper" title="Threadripper">Threadripper</a></li> <li><a href="/wiki/Epyc" title="Epyc">Epyc</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;background-color: #DDDDDD">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6">Early x86 (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Am286" class="mw-redirect" title="Am286">Am286</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Am386" title="Am386">Am386</a></li> <li><a href="/wiki/Am486" title="Am486">Am486</a></li> <li><a href="/wiki/Am5x86" title="Am5x86">Am5x86</a></li> <li><a href="/wiki/AMD_K5" title="AMD K5">K5</a></li> <li><a href="/wiki/AMD_K6" title="AMD K6">K6</a></li> <li><a href="/wiki/AMD_K6-2" title="AMD K6-2">K6-2</a></li> <li><a href="/wiki/AMD_K6-III" title="AMD K6-III">K6-III</a></li> <li><a href="/wiki/Athlon" title="Athlon">Athlon</a> <ul><li><a href="/wiki/Athlon_XP" class="mw-redirect" title="Athlon XP">XP</a></li> <li><a href="/wiki/Athlon_MP" class="mw-redirect" title="Athlon MP">MP</a></li></ul></li> <li><a href="/wiki/Duron" title="Duron">Duron</a></li> <li><a href="/wiki/Geode_(processor)" title="Geode (processor)">Geode</a></li> <li><a href="/wiki/AMD_%C3%89lan" title="AMD Élan">AMD Élan</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Athlon_64" title="Athlon 64">Athlon 64</a> <ul><li><a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">X2</a></li> <li><a href="/wiki/Athlon_II" title="Athlon II">II</a></li></ul></li> <li><a href="/wiki/Sempron" title="Sempron">Sempron</a></li> <li><a href="/wiki/AMD_Turion" title="AMD Turion">Turion</a></li> <li><a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a> <ul><li><a href="/wiki/Phenom_II" title="Phenom II">II</a></li></ul></li> <li><a href="/wiki/AMD_FX" title="AMD FX">FX</a></li> <li><a href="/wiki/Opteron" title="Opteron">Opteron</a></li> <li><a href="/wiki/AMD_APU" title="AMD APU">A-series APUs</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:8.5em;background-color: #E6E6E6">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am9080" title="AMD Am9080">Am9080</a></li> <li><a href="/wiki/AMD_Am2900" title="AMD Am2900">Am2900</a> <ul><li><a href="/wiki/List_of_AMD_Am2900_and_Am29000_families" title="List of AMD Am2900 and Am29000 families">list</a></li></ul></li> <li><a href="/wiki/AMD_Am29000" title="AMD Am29000">Am29000</a></li> <li><a href="/wiki/Alchemy_(microarchitecture)" class="mw-redirect" title="Alchemy (microarchitecture)">Alchemy</a> <ul><li><a href="/wiki/MIPS_architecture#MIPS32" title="MIPS architecture">MIPS32</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Italics indicates an upcoming architecture.</div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="AMD_sockets_and_chipsets157" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:AMD_CPU_sockets" title="Template:AMD CPU sockets"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_CPU_sockets" title="Template talk:AMD CPU sockets"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_CPU_sockets" title="Special:EditPage/Template:AMD CPU sockets"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_sockets_and_chipsets157" style="font-size:114%;margin:0 4em"><a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> sockets and chipsets</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="AMD_sockets157" style="font-size:114%;margin:0 4em"><a href="/wiki/Category:AMD_sockets" title="Category:AMD sockets">AMD sockets</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Desktop sockets</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Super_Socket_7" title="Super Socket 7">Super Socket 7</a> (1998)</li> <li><a href="/wiki/Slot_A" title="Slot A">Slot A</a> (1999)</li> <li><a href="/wiki/Socket_939" title="Socket 939">939</a> (2004)</li> <li><a href="/wiki/Socket_940" title="Socket 940">940</a> (2003)</li> <li><a href="/wiki/Socket_AM2" title="Socket AM2">AM2</a> (2006)</li> <li><a href="/wiki/Socket_AM2%2B" title="Socket AM2+">AM2+</a> (2007)</li> <li><a href="/wiki/Socket_AM3" title="Socket AM3">AM3</a> (2009)</li> <li><a href="/wiki/Socket_AM3%2B" title="Socket AM3+">AM3+</a> (2011)</li> <li><a href="/wiki/Socket_FM1" title="Socket FM1">FM1</a> (2011)</li> <li><a href="/wiki/Socket_FM2" title="Socket FM2">FM2</a> (2012)</li> <li><a href="/wiki/Socket_FM2%2B" title="Socket FM2+">FM2+</a> (2014)</li> <li><a href="/wiki/Socket_AM1" title="Socket AM1">AM1</a> (2014)</li> <li><a href="/wiki/Socket_AM4" title="Socket AM4">AM4</a> (2016)</li> <li><a href="/wiki/Socket_TR4" title="Socket TR4">TR4</a> (2017)</li> <li><a href="/wiki/Socket_sTRX4" title="Socket sTRX4">sTRX4</a> (2019)</li> <li><a href="/wiki/Socket_sWRX8" title="Socket sWRX8">sWRX8</a> (2020)</li> <li><a href="/wiki/Socket_AM5" title="Socket AM5">AM5</a> (2022)</li> <li><a href="/wiki/Socket_sTR5" title="Socket sTR5">sTR5</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Mobile sockets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_563" title="Socket 563">563</a></li> <li><a href="/wiki/Socket_S1" title="Socket S1">S1</a> (2006)</li> <li><a href="/wiki/Socket_FT1" title="Socket FT1">FT1</a> (2011)</li> <li><a href="/wiki/Socket_FP2" title="Socket FP2">FP2</a> (2012)</li> <li><a href="/wiki/Socket_FS1" title="Socket FS1">FS1</a></li> <li><a href="/wiki/Socket_FT3" title="Socket FT3">FT3</a></li> <li><a href="/wiki/Socket_FP3" title="Socket FP3">FP3</a> (2014)</li> <li><a href="/w/index.php?title=Socket_FP4&action=edit&redlink=1" class="new" title="Socket FP4 (page does not exist)">FP4</a> (2015)</li> <li><a href="/w/index.php?title=Socket_FT4&action=edit&redlink=1" class="new" title="Socket FT4 (page does not exist)">FT4</a> (2016)</li> <li><a href="/w/index.php?title=Socket_FP5&action=edit&redlink=1" class="new" title="Socket FP5 (page does not exist)">FP5</a> (2019)</li> <li><a href="/w/index.php?title=Socket_FT5&action=edit&redlink=1" class="new" title="Socket FT5 (page does not exist)">FT5</a></li> <li><a href="/w/index.php?title=Socket_FP6&action=edit&redlink=1" class="new" title="Socket FP6 (page does not exist)">FP6</a> (2020)</li> <li><a href="/w/index.php?title=Socket_FP7&action=edit&redlink=1" class="new" title="Socket FP7 (page does not exist)">FP7</a> (2022)</li> <li><a href="/w/index.php?title=Socket_FP8&action=edit&redlink=1" class="new" title="Socket FP8 (page does not exist)">FP8</a></li> <li><a href="/w/index.php?title=Socket_FL1&action=edit&redlink=1" class="new" title="Socket FL1 (page does not exist)">FL1</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Server sockets</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_940" title="Socket 940">940</a></li> <li><a href="/wiki/Socket_F" title="Socket F">F</a> (2006)</li> <li><a href="/wiki/Socket_F%2B" title="Socket F+">F+</a></li> <li><a href="/wiki/AMD_Socket_G3" title="AMD Socket G3">G3</a> (not released)</li> <li><a href="/wiki/Socket_G34" title="Socket G34">G34</a></li> <li><a href="/wiki/Socket_C32" title="Socket C32">C32</a> (2010)</li> <li><a href="/wiki/Socket_SP3" title="Socket SP3">SP3</a> (2017)</li> <li><a href="/w/index.php?title=Socket_SP4&action=edit&redlink=1" class="new" title="Socket SP4 (page does not exist)">SP4</a> (2018)</li> <li><a href="/wiki/Socket_SP5" title="Socket SP5">SP5</a> (2022)</li> <li><a href="/wiki/Socket_SP6" title="Socket SP6">SP6</a> (2023)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Combined sockets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Socket_A" title="Socket A">Socket A</a> (2000)</li> <li><a href="/wiki/Socket_754" title="Socket 754">754</a> (2003)</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="ATI_/_AMD_chipsets157" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_AMD_chipsets" title="List of AMD chipsets">ATI / AMD chipsets</a></div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_ATI_chipsets" title="List of ATI chipsets">ATI chipsets</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>IGP 300 series/RX380</li> <li><a href="/wiki/Xpress_200" title="Xpress 200">Radeon Xpress 200</a></li> <li><a href="/wiki/Xpress_3200" title="Xpress 3200">CrossFire Xpress 3200</a></li> <li><a href="/wiki/AMD_690_chipset_series#Radeon_Xpress_1250" title="AMD 690 chipset series">Radeon Xpress 1250</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_AMD_chipsets" title="List of AMD chipsets">AMD chipsets</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_580_chipset_series" title="AMD 580 chipset series">480X/570X/580X</a></li> <li><a href="/wiki/AMD_690_chipset_series" title="AMD 690 chipset series">690 Series</a></li> <li><a href="/wiki/AMD_700_chipset_series" title="AMD 700 chipset series">7-Series</a></li> <li><a href="/wiki/AMD_800_chipset_series" title="AMD 800 chipset series">8-Series</a></li> <li><a href="/wiki/AMD_900_chipset_series" title="AMD 900 chipset series">9-Series</a></li> <li><a href="/wiki/List_of_AMD_chipsets#Fusion_controller_hubs_(FCH)" title="List of AMD chipsets">Fusion Controller Hubs</a></li> <li><a href="/wiki/List_of_AMD_chipsets#AM4_chipsets" title="List of AMD chipsets">AM4 chipsets</a></li> <li><a href="/wiki/List_of_AMD_chipsets#TR4_chipsets" title="List of AMD chipsets">TR4 chipsets</a></li> <li><a href="/wiki/List_of_AMD_chipsets#sTRX4_chipsets" title="List of AMD chipsets">sTRX4 chipsets</a></li> <li><a href="/wiki/List_of_AMD_chipsets#sWRX8_chipsets" title="List of AMD chipsets">sWRX8 chipsets</a></li> <li><a href="/wiki/List_of_AMD_chipsets#AM5_chipsets" title="List of AMD chipsets">AM5 chipsets</a></li> <li><a href="/wiki/List_of_AMD_chipsets#sTR5_chipsets" title="List of AMD chipsets">sTR5 chipsets</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>Combined means that the given socket is supported by all platforms, including desktop, mobile, and server.</div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="AMD_graphics16" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:AMD_graphics" title="Template:AMD graphics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:AMD_graphics" title="Template talk:AMD graphics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:AMD_graphics" title="Special:EditPage/Template:AMD graphics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="AMD_graphics16" style="font-size:114%;margin:0 4em"><a href="/wiki/AMD" title="AMD">AMD</a> graphics</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Radeon-brandList_of_GPUs_(GPU_features_template)_and_List_of_APUs_(APU_features_template)16" style="font-size:114%;margin:0 4em"><a href="/wiki/Radeon" title="Radeon">Radeon</a>-brand <a href="/wiki/List_of_AMD_graphics_processing_units" title="List of AMD graphics processing units">List of GPUs</a> (<a href="/wiki/Template:AMD_GPU_features" title="Template:AMD GPU features">GPU features template</a>) and <a class="mw-selflink selflink">List of APUs</a> (<a href="/wiki/Template:AMD_APU_features" class="mw-redirect" title="Template:AMD APU features">APU features template</a>)</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Fixed pipeline</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ATI_Wonder" title="ATI Wonder">Wonder</a></li> <li><a href="/wiki/ATI_Mach" title="ATI Mach">Mach</a></li> <li><a href="/wiki/ATI_Rage" title="ATI Rage">Rage</a></li> <li><a href="/wiki/All-in-Wonder" title="All-in-Wonder">All-in-Wonder</a> (before 2000)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Vertex and fragment shaders</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_R100_series" title="Radeon R100 series">R100</a></li> <li><a href="/wiki/Radeon_R200_series" title="Radeon R200 series">R200</a></li> <li><a href="/wiki/Radeon_R300_series" title="Radeon R300 series">R300</a></li> <li><a href="/wiki/Radeon_R400_series" title="Radeon R400 series">R400</a></li> <li><a href="/wiki/Radeon_X1000_series" title="Radeon X1000 series">R500</a></li> <li><a href="/wiki/All-in-Wonder" title="All-in-Wonder">All-in-Wonder</a> (after 1999)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Unified_shader_model" title="Unified shader model">Unified shaders</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="TeraScale43" scope="row" class="navbox-group" style="width:1%"><a href="/wiki/TeraScale_(microarchitecture)" title="TeraScale (microarchitecture)">TeraScale</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_HD_2000_series" title="Radeon HD 2000 series">HD 2000</a></li> <li><a href="/wiki/Radeon_HD_3000_series" title="Radeon HD 3000 series">HD 3000</a></li> <li><a href="/wiki/Radeon_HD_4000_series" title="Radeon HD 4000 series">HD 4000</a></li> <li><a href="/wiki/Radeon_HD_5000_series" title="Radeon HD 5000 series">HD 5000</a></li> <li><a href="/wiki/Radeon_HD_6000_series" title="Radeon HD 6000 series">HD 6000</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Unified shaders & <a href="/wiki/Unified_Memory_Architecture" class="mw-redirect" title="Unified Memory Architecture">memory</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Graphics_Core_Next" title="Graphics Core Next">GCN</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_HD_7000_series" title="Radeon HD 7000 series">HD 7000</a></li> <li><a href="/wiki/Radeon_HD_8000_series" title="Radeon HD 8000 series">HD 8000</a></li> <li><a href="/wiki/Radeon_200_series" title="Radeon 200 series">200</a></li> <li><a href="/wiki/Radeon_300_series" title="Radeon 300 series">300</a></li> <li><a href="/wiki/Radeon_400_series" title="Radeon 400 series">400</a></li> <li><a href="/wiki/Radeon_500_series" title="Radeon 500 series">500</a></li> <li><a href="/wiki/Radeon_RX_Vega_series" title="Radeon RX Vega series">RX Vega</a></li> <li><a href="/wiki/Radeon_600_series" title="Radeon 600 series">600</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_RX_5000_series" title="Radeon RX 5000 series">RX 5000</a></li> <li><a href="/wiki/Radeon_RX_6000_series" title="Radeon RX 6000 series">RX 6000</a></li> <li><a href="/wiki/Radeon_RX_7000_series" title="Radeon RX 7000 series">RX 7000</a></li> <li><a href="/wiki/Radeon_RX_9000_Series" class="mw-redirect" title="Radeon RX 9000 Series">RX 9000</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Current_technologies_and_software16" style="font-size:114%;margin:0 4em">Current technologies and software</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Audio/Video acceleration</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Unified_Video_Decoder" title="Unified Video Decoder">Unified Video Decoder (UVD)</a></li> <li><a href="/wiki/Video_Coding_Engine" title="Video Coding Engine">Video Coding Engine (VCE)</a></li> <li><a href="/wiki/Video_Core_Next" title="Video Core Next">Video Core Next (VCN)</a></li> <li><a href="/wiki/AMD_TrueAudio" title="AMD TrueAudio">TrueAudio</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">GPU technologies</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Eyefinity" title="AMD Eyefinity">Eyefinity</a></li> <li><a href="/wiki/FreeSync" title="FreeSync">FreeSync</a></li> <li><a href="/wiki/AMD_PowerTune" title="AMD PowerTune">PowerTune</a></li> <li><a href="/wiki/AMD_CrossFire" title="AMD CrossFire">CrossFire</a></li> <li><a href="/wiki/AMD_Hybrid_Graphics" title="AMD Hybrid Graphics">Hybrid Graphics</a></li> <li><a href="/wiki/HyperMemory" title="HyperMemory">HyperMemory</a></li> <li><a href="/wiki/HyperZ" title="HyperZ">HyperZ</a></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">HSA</a></li> <li><a href="/wiki/RDNA_(microarchitecture)" title="RDNA (microarchitecture)">RDNA</a> <ul><li><a href="/wiki/RDNA_2" title="RDNA 2">2</a></li> <li><a href="/wiki/RDNA_3" title="RDNA 3">3</a></li> <li><a href="/w/index.php?title=RDNA_4&action=edit&redlink=1" class="new" title="RDNA 4 (page does not exist)">4</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Radeon_Software" class="mw-redirect" title="AMD Radeon Software">AMD Radeon Software</a> <ul><li><a href="/wiki/AMD_HD3D" title="AMD HD3D">HD3D</a></li></ul></li> <li><a href="/wiki/ROCm" title="ROCm">ROCm</a></li> <li><a href="/wiki/AMDGPU" class="mw-redirect" title="AMDGPU">AMDGPU</a></li> <li><a href="/wiki/AMD_GPU_PerfStudio" class="mw-redirect" title="AMD GPU PerfStudio">GPU PerfStudio</a></li> <li><a href="/wiki/GPUOpen" title="GPUOpen">GPUOpen</a> <ul><li><a href="/wiki/TressFX" title="TressFX">TressFX</a></li></ul></li> <li><a href="/wiki/HLSL2GLSL" title="HLSL2GLSL">HLSL2GLSL</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_APP_SDK" title="AMD APP SDK">AMD APP SDK</a></li> <li><a href="/wiki/AMD_Catalyst" class="mw-redirect" title="AMD Catalyst">Catalyst</a></li> <li><a href="/wiki/Close_to_Metal" title="Close to Metal">Close to Metal</a></li> <li><a href="/wiki/AMD_CodeAnalyst" title="AMD CodeAnalyst">CodeAnalyst</a></li> <li><a href="/wiki/Mantle_(API)" title="Mantle (API)">Mantle</a></li> <li><a href="/wiki/CodeXL" title="CodeXL">CodeXL</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="col" class="navbox-title" colspan="2" style="text-align:center;"><div id="Other_brands_and_products16" style="font-size:114%;margin:0 4em">Other brands and products</div></th></tr><tr><td colspan="2" class="navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Workstation" title="Workstation">Workstations</a> & <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Radeon_Pro" title="Radeon Pro">Radeon Pro</a></li> <li><a href="/wiki/Radeon_Instinct" class="mw-redirect" title="Radeon Instinct">Radeon Instinct</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_FirePro" title="AMD FirePro">FireGL/FirePro</a></li> <li><a href="/wiki/AMD_FireMV" title="AMD FireMV">FireMV</a></li> <li><a href="/wiki/AMD_FireStream" title="AMD FireStream">FireStream</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Video_game_console" title="Video game console">Consoles</a> & <a href="/wiki/Handheld_PC" title="Handheld PC">handheld PCs</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Flipper_(graphics_chip)" class="mw-redirect" title="Flipper (graphics chip)">Flipper</a> (<a href="/wiki/GameCube" title="GameCube">GameCube</a>)</li> <li><a href="/wiki/Xenos_(graphics_chip)" title="Xenos (graphics chip)">Xenos</a> (<a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a>)</li> <li><a href="/wiki/Hollywood_(graphics_chip)" title="Hollywood (graphics chip)">Hollywood</a> (<a href="/wiki/Wii" title="Wii">Wii</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_2" title="Graphics Core Next">Liverpool</a> (<a href="/wiki/PlayStation_4" title="PlayStation 4">PlayStation 4</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_2" title="Graphics Core Next">Durango</a> (<a href="/wiki/Xbox_One" title="Xbox One">Xbox One</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_4" title="Graphics Core Next">Neo</a> (<a href="/wiki/PlayStation_4_Pro" class="mw-redirect" title="PlayStation 4 Pro">PlayStation 4 Pro</a>)</li> <li><a href="/wiki/Graphics_Core_Next#Graphics_Core_Next_4" title="Graphics Core Next">Scorpio</a> (<a href="/wiki/Xbox_One_X" class="mw-redirect" title="Xbox One X">Xbox One X</a>)</li> <li><a href="/wiki/Atari_VCS_(2021_console)" title="Atari VCS (2021 console)">Atari VCS (2021)</a></li> <li><a href="/wiki/PlayStation_5" title="PlayStation 5">PlayStation 5</a></li> <li><a href="/wiki/Xbox_Series_X_and_Series_S" title="Xbox Series X and Series S">Xbox Series X/S</a></li> <li><a href="/wiki/Steam_Deck" title="Steam Deck">Steam Deck</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=0" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" 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