Search results for: Juyoung Kim

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class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="Juyoung Kim"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 1</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: Juyoung Kim</h1> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1</span> High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Juyoung%20Kim">Juyoung Kim</a>, <a href="https://publications.waset.org/search?q=Taegeun%20Park"> Taegeun Park</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=discrete%20wavelet%20transform" title="discrete wavelet transform">discrete wavelet transform</a>, <a href="https://publications.waset.org/search?q=VLSI%20architecture" title=" VLSI architecture"> VLSI architecture</a>, <a href="https://publications.waset.org/search?q=QMF%20lattice%20filter" title=" QMF lattice filter"> QMF lattice filter</a>, <a href="https://publications.waset.org/search?q=pipelining." title=" pipelining."> pipelining.</a> </p> <a href="https://publications.waset.org/7661/high-performance-vlsi-architecture-of-2d-discrete-wavelet-transform-with-scalable-lattice-structure" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7661/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7661/bibtex" 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Search results for: Juyoung Kim