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class="vector-toc-list"> </ul> </li> <li id="toc-Control_signals" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Control_signals"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Control signals</span> </div> </a> <button aria-controls="toc-Control_signals-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Control signals subsection</span> </button> <ul id="toc-Control_signals-sublist" class="vector-toc-list"> <li id="toc-Command_signals" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Command_signals"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Command signals</span> </div> </a> <ul id="toc-Command_signals-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bank_selection_(BAn)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bank_selection_(BAn)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Bank selection (BAn)</span> </div> </a> <ul id="toc-Bank_selection_(BAn)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Addressing_(A10/An)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Addressing_(A10/An)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Addressing (A10/An)</span> </div> </a> <ul id="toc-Addressing_(A10/An)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Commands" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Commands"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Commands</span> </div> </a> <ul id="toc-Commands-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Construction_and_operation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Construction_and_operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Construction and operation</span> </div> </a> <ul id="toc-Construction_and_operation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Command_interactions" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Command_interactions"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Command interactions</span> </div> </a> <button aria-controls="toc-Command_interactions-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Command interactions subsection</span> </button> <ul id="toc-Command_interactions-sublist" class="vector-toc-list"> <li id="toc-Interrupting_a_read_burst" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Interrupting_a_read_burst"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>Interrupting a read burst</span> </div> </a> <ul id="toc-Interrupting_a_read_burst-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Burst_ordering" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Burst_ordering"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Burst ordering</span> </div> </a> <ul id="toc-Burst_ordering-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Mode_register" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Mode_register"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Mode register</span> </div> </a> <ul id="toc-Mode_register-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Auto_refresh" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Auto_refresh"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Auto refresh</span> </div> </a> <ul id="toc-Auto_refresh-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Low_power_modes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Low_power_modes"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Low power modes</span> </div> </a> <ul id="toc-Low_power_modes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR_SDRAM_prefetch_architecture" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#DDR_SDRAM_prefetch_architecture"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>DDR SDRAM prefetch architecture</span> </div> </a> <ul id="toc-DDR_SDRAM_prefetch_architecture-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Generations" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Generations"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Generations</span> </div> </a> <button aria-controls="toc-Generations-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Generations subsection</span> </button> <ul id="toc-Generations-sublist" class="vector-toc-list"> <li id="toc-SDR" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SDR"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1</span> <span>SDR</span> </div> </a> <ul id="toc-SDR-sublist" class="vector-toc-list"> <li id="toc-PC66" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PC66"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1.1</span> <span>PC66</span> </div> </a> <ul id="toc-PC66-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PC100" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PC100"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1.2</span> <span>PC100</span> </div> </a> <ul id="toc-PC100-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-PC133" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#PC133"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1.3</span> <span>PC133</span> </div> </a> <ul id="toc-PC133-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-DDR" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.2</span> <span>DDR</span> </div> </a> <ul id="toc-DDR-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR2"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.3</span> <span>DDR2</span> </div> </a> <ul id="toc-DDR2-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR3"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.4</span> <span>DDR3</span> </div> </a> <ul id="toc-DDR3-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR4" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR4"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.5</span> <span>DDR4</span> </div> </a> <ul id="toc-DDR4-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-DDR5" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#DDR5"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.6</span> <span>DDR5</span> </div> </a> <ul id="toc-DDR5-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Failed_successors" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Failed_successors"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Failed successors</span> </div> </a> <button aria-controls="toc-Failed_successors-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Failed successors subsection</span> </button> <ul id="toc-Failed_successors-sublist" class="vector-toc-list"> <li id="toc-Rambus_DRAM_(RDRAM)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Rambus_DRAM_(RDRAM)"> <div class="vector-toc-text"> <span class="vector-toc-numb">12.1</span> <span>Rambus DRAM (RDRAM)</span> </div> </a> <ul id="toc-Rambus_DRAM_(RDRAM)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Synchronous-link_DRAM_(SLDRAM)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Synchronous-link_DRAM_(SLDRAM)"> <div class="vector-toc-text"> <span class="vector-toc-numb">12.2</span> <span>Synchronous-link DRAM (SLDRAM)</span> </div> </a> <ul id="toc-Synchronous-link_DRAM_(SLDRAM)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Virtual_channel_memory_(VCM)_SDRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Virtual_channel_memory_(VCM)_SDRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">12.3</span> <span>Virtual channel memory (VCM) SDRAM</span> </div> </a> <ul id="toc-Virtual_channel_memory_(VCM)_SDRAM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Synchronous_Graphics_RAM_(SGRAM)" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Synchronous_Graphics_RAM_(SGRAM)"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>Synchronous Graphics RAM (SGRAM)</span> </div> </a> <button aria-controls="toc-Synchronous_Graphics_RAM_(SGRAM)-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Synchronous Graphics RAM (SGRAM) subsection</span> </button> <ul id="toc-Synchronous_Graphics_RAM_(SGRAM)-sublist" class="vector-toc-list"> <li id="toc-Graphics_double_data_rate_SDRAM_(GDDR_SDRAM)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Graphics_double_data_rate_SDRAM_(GDDR_SDRAM)"> <div class="vector-toc-text"> <span class="vector-toc-numb">13.1</span> <span>Graphics double data rate SDRAM (GDDR SDRAM)</span> </div> </a> <ul id="toc-Graphics_double_data_rate_SDRAM_(GDDR_SDRAM)-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-High_Bandwidth_Memory_(HBM)" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#High_Bandwidth_Memory_(HBM)"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>High Bandwidth Memory (HBM)</span> </div> </a> <ul id="toc-High_Bandwidth_Memory_(HBM)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Timeline" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Timeline"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>Timeline</span> </div> </a> <button aria-controls="toc-Timeline-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Timeline subsection</span> </button> <ul id="toc-Timeline-sublist" class="vector-toc-list"> <li id="toc-SDRAM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SDRAM"> <div class="vector-toc-text"> <span class="vector-toc-numb">15.1</span> <span>SDRAM</span> </div> </a> <ul id="toc-SDRAM-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-SGRAM_and_HBM" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#SGRAM_and_HBM"> <div class="vector-toc-text"> <span class="vector-toc-numb">15.2</span> <span>SGRAM and HBM</span> </div> </a> <ul id="toc-SGRAM_and_HBM-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">16</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">17</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">18</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Synchronous dynamic random-access memory</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 27 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-27" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">27 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B0%D8%A7%D9%83%D8%B1%D8%A9_%D9%88%D8%B5%D9%88%D9%84_%D8%B9%D8%B4%D9%88%D8%A7%D8%A6%D9%8A%D8%A9_%D8%AD%D8%B1%D9%83%D9%8A%D8%A9_%D9%85%D8%AA%D8%B2%D8%A7%D9%85%D9%86%D8%A9" title="ذاكرة وصول عشوائية حركية متزامنة – Arabic" lang="ar" hreflang="ar" data-title="ذاكرة وصول عشوائية حركية متزامنة" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/SDRAM" title="SDRAM – Azerbaijani" lang="az" hreflang="az" data-title="SDRAM" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target"><span>Azərbaycanca</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/SDRAM" title="SDRAM – Catalan" lang="ca" hreflang="ca" data-title="SDRAM" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Synchronous_Dynamic_Random_Access_Memory" title="Synchronous Dynamic Random Access Memory – German" lang="de" hreflang="de" data-title="Synchronous Dynamic Random Access Memory" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/SDRAM" title="SDRAM – Estonian" lang="et" hreflang="et" data-title="SDRAM" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/SDRAM" title="SDRAM – Spanish" lang="es" hreflang="es" data-title="SDRAM" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/SDRAM" title="SDRAM – Basque" lang="eu" hreflang="eu" data-title="SDRAM" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/SDRAM" title="SDRAM – French" lang="fr" hreflang="fr" data-title="SDRAM" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/SDRAM" title="SDRAM – Korean" lang="ko" hreflang="ko" data-title="SDRAM" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/SDRAM" title="SDRAM – Indonesian" lang="id" hreflang="id" data-title="SDRAM" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/SDRAM" title="SDRAM – Italian" lang="it" hreflang="it" data-title="SDRAM" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/SDRAM" title="SDRAM – Hebrew" lang="he" hreflang="he" data-title="SDRAM" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/SDRAM" title="SDRAM – Lithuanian" lang="lt" hreflang="lt" data-title="SDRAM" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/SDRAM" title="SDRAM – Hungarian" lang="hu" hreflang="hu" data-title="SDRAM" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%B8%E0%B4%BF%E0%B5%BB%E0%B4%95%E0%B5%8D%E0%B4%B0%E0%B4%A3%E0%B4%B8%E0%B5%8D_%E0%B4%A1%E0%B5%88%E0%B4%A8%E0%B4%BE%E0%B4%AE%E0%B4%BF%E0%B4%95%E0%B5%8D_%E0%B4%B1%E0%B4%BE%E0%B5%BB%E0%B4%A1%E0%B4%82-%E0%B4%86%E0%B4%95%E0%B5%8D%E0%B4%B8%E0%B4%B8%E0%B5%8D_%E0%B4%AE%E0%B5%86%E0%B4%AE%E0%B5%8D%E0%B4%AE%E0%B4%B1%E0%B4%BF" title="സിൻക്രണസ് ഡൈനാമിക് റാൻഡം-ആക്സസ് മെമ്മറി – Malayalam" lang="ml" hreflang="ml" data-title="സിൻക്രണസ് ഡൈനാമിക് റാൻഡം-ആക്സസ് മെമ്മറി" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/SDRAM" title="SDRAM – Dutch" lang="nl" hreflang="nl" data-title="SDRAM" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/SDRAM" title="SDRAM – Japanese" lang="ja" hreflang="ja" data-title="SDRAM" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/SDRAM" title="SDRAM – Polish" lang="pl" hreflang="pl" data-title="SDRAM" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/SDRAM" title="SDRAM – Portuguese" lang="pt" hreflang="pt" data-title="SDRAM" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/SDRAM" title="SDRAM – Russian" lang="ru" hreflang="ru" data-title="SDRAM" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/SDRAM" title="SDRAM – Slovak" lang="sk" hreflang="sk" data-title="SDRAM" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%A1%D0%B8%D0%BD%D1%85%D1%80%D0%BE%D0%BD%D0%B0_%D0%B4%D0%B8%D0%BD%D0%B0%D0%BC%D0%B8%D1%87%D0%BA%D0%B0_%D0%BC%D0%B5%D0%BC%D0%BE%D1%80%D0%B8%D1%98%D0%B0_%D1%81%D0%B0_%D1%81%D0%BB%D1%83%D1%87%D0%B0%D1%98%D0%BD%D0%B8%D0%BC_%D0%BF%D1%80%D0%B8%D1%81%D1%82%D1%83%D0%BF%D0%BE%D0%BC" title="Синхрона динамичка меморија са случајним приступом – Serbian" lang="sr" hreflang="sr" data-title="Синхрона динамичка меморија са случајним приступом" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/SDRAM" title="SDRAM – Finnish" lang="fi" hreflang="fi" data-title="SDRAM" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/SDRAM" title="SDRAM – Swedish" lang="sv" hreflang="sv" data-title="SDRAM" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/SDRAM" title="SDRAM – Turkish" lang="tr" hreflang="tr" data-title="SDRAM" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/SDRAM" title="SDRAM – Ukrainian" lang="uk" hreflang="uk" data-title="SDRAM" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/SDRAM" title="SDRAM – Chinese" lang="zh" hreflang="zh" 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</div> </div> </div> </nav> </div> </div> </div> <div class="vector-column-end"> <div class="vector-sticky-pinned-container"> <nav class="vector-page-tools-landmark" aria-label="Page tools"> <div id="vector-page-tools-pinned-container" class="vector-pinned-container"> </div> </nav> <nav class="vector-appearance-landmark" aria-label="Appearance"> <div id="vector-appearance-pinned-container" class="vector-pinned-container"> <div id="vector-appearance" class="vector-appearance vector-pinnable-element"> <div class="vector-pinnable-header vector-appearance-pinnable-header vector-pinnable-header-pinned" data-feature-name="appearance-pinned" data-pinnable-element-id="vector-appearance" data-pinned-container-id="vector-appearance-pinned-container" data-unpinned-container-id="vector-appearance-unpinned-container" > <div class="vector-pinnable-header-label">Appearance</div> <button class="vector-pinnable-header-toggle-button vector-pinnable-header-pin-button" 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data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"PC100" redirects here. For the Japanese home computer, see <a href="/wiki/NEC_PC-100" title="NEC PC-100">NEC PC-100</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol ul,.mw-parser-output .hlist ul dl,.mw-parser-output .hlist ul ol,.mw-parser-output .hlist ul ul{display:inline}.mw-parser-output .hlist .mw-empty-li{display:none}.mw-parser-output .hlist dt::after{content:": "}.mw-parser-output .hlist dd::after,.mw-parser-output .hlist li::after{content:" · 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.sidebar-content{padding:0 0.5em 0.4em}.mw-parser-output .sidebar-content-with-subgroup{padding:0.1em 0.4em 0.2em}.mw-parser-output .sidebar-above,.mw-parser-output .sidebar-below{padding:0.3em 0.8em;font-weight:bold}.mw-parser-output .sidebar-collapse .sidebar-above,.mw-parser-output .sidebar-collapse .sidebar-below{border-top:1px solid #aaa;border-bottom:1px solid #aaa}.mw-parser-output .sidebar-navbar{text-align:right;font-size:115%;padding:0 0.4em 0.4em}.mw-parser-output .sidebar-list-title{padding:0 0.4em;text-align:left;font-weight:bold;line-height:1.6em;font-size:105%}.mw-parser-output .sidebar-list-title-c{padding:0 0.4em;text-align:center;margin:0 3.3em}@media(max-width:640px){body.mediawiki .mw-parser-output .sidebar{width:100%!important;clear:both;float:none!important;margin-left:0!important;margin-right:0!important}}body.skin--responsive .mw-parser-output .sidebar a>img{max-width:none!important}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-night .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-list-title,html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle{background:transparent!important}html.skin-theme-clientpref-os .mw-parser-output .sidebar:not(.notheme) .sidebar-title-with-pretitle a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar sidebar-collapse nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="/wiki/Computer_memory" title="Computer memory">Computer memory</a> and <a href="/wiki/Computer_data_storage" title="Computer data storage">data storage</a> types</th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">General</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Memory_coherence" title="Memory coherence">Memory coherence</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a></li> <li><a href="/wiki/Memory_access_pattern" title="Memory access pattern">Memory access pattern</a></li> <li><a href="/wiki/Memory_map" title="Memory map">Memory map</a></li> <li><a href="/wiki/Computer_data_storage#Secondary_storage" title="Computer data storage">Secondary storage</a></li> <li><a href="/wiki/Semiconductor_memory" title="Semiconductor memory">MOS memory</a> <ul><li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">floating-gate</a></li></ul></li> <li><a href="/wiki/Continuous_availability" title="Continuous availability">Continuous availability</a></li> <li><a href="/wiki/Areal_density_(computer_storage)" class="mw-redirect" title="Areal density (computer storage)">Areal density (computer storage)</a></li> <li><a href="/wiki/Block_(data_storage)" title="Block (data storage)">Block (data storage)</a></li> <li><a href="/wiki/Object_storage" title="Object storage">Object storage</a></li> <li><a href="/wiki/Direct-attached_storage" title="Direct-attached storage">Direct-attached storage</a></li> <li><a href="/wiki/Network-attached_storage" title="Network-attached storage">Network-attached storage</a> <ul><li><a href="/wiki/Storage_area_network" title="Storage area network">Storage area network</a></li> <li><a href="/wiki/Block-level_storage" title="Block-level storage">Block-level storage</a></li></ul></li> <li><a href="/wiki/Single-instance_storage" title="Single-instance storage">Single-instance storage</a></li> <li><a href="/wiki/Data" title="Data">Data</a></li> <li><a href="/wiki/Data_model" title="Data model">Structured data</a></li> <li><a href="/wiki/Unstructured_data" title="Unstructured data">Unstructured data</a></li> <li><a href="/wiki/Big_data" title="Big data">Big data</a></li> <li><a href="/wiki/Metadata" title="Metadata">Metadata</a></li> <li><a href="/wiki/Data_compression" title="Data compression">Data compression</a></li> <li><a href="/wiki/Data_corruption" title="Data corruption">Data corruption</a></li> <li><a href="/wiki/Data_cleansing" title="Data cleansing">Data cleansing</a></li> <li><a href="/wiki/Data_degradation" title="Data degradation">Data degradation</a></li> <li><a href="/wiki/Data_integrity" title="Data integrity">Data integrity</a></li> <li><a href="/wiki/Data_security" title="Data security">Data security</a></li> <li><a href="/wiki/Data_validation" title="Data validation">Data validation</a></li> <li><a href="/wiki/Data_validation_and_reconciliation" title="Data validation and reconciliation">Data validation and reconciliation</a></li> <li><a href="/wiki/Data_recovery" title="Data recovery">Data recovery</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Storage</a></li> <li><a href="/wiki/Data_cluster" class="mw-redirect" title="Data cluster">Data cluster</a></li> <li><a href="/wiki/Directory_(computing)" title="Directory (computing)">Directory</a></li> <li><a href="/wiki/Shared_resource" title="Shared resource">Shared resource</a></li> <li><a href="/wiki/File_sharing" title="File sharing">File sharing</a></li> <li><a href="/wiki/File_system" title="File system">File system</a></li> <li><a href="/wiki/Clustered_file_system" title="Clustered file system">Clustered file system</a></li> <li><a href="/wiki/Clustered_file_system#Distributed_file_systems" title="Clustered file system">Distributed file system</a></li> <li><a href="/wiki/Distributed_file_system_for_cloud" title="Distributed file system for cloud">Distributed file system for cloud</a></li> <li><a href="/wiki/Distributed_data_store" title="Distributed data store">Distributed data store</a></li> <li><a href="/wiki/Distributed_database" title="Distributed database">Distributed database</a></li> <li><a href="/wiki/Database" title="Database">Database</a></li> <li><a href="/wiki/Data_bank" title="Data bank">Data bank</a></li> <li><a href="/wiki/Data_storage" title="Data storage">Data storage</a></li> <li><a href="/wiki/Data_store" title="Data store">Data store</a></li> <li><a href="/wiki/Data_deduplication" title="Data deduplication">Data deduplication</a></li> <li><a href="/wiki/Data_structure" title="Data structure">Data structure</a></li> <li><a href="/wiki/Data_redundancy" title="Data redundancy">Data redundancy</a></li> <li><a href="/wiki/Replication_(computing)" title="Replication (computing)">Replication (computing)</a></li> <li><a href="/wiki/Memory_refresh" title="Memory refresh">Memory refresh</a></li> <li><a href="/wiki/Storage_record" title="Storage record">Storage record</a></li> <li><a href="/wiki/Information_repository" title="Information repository">Information repository</a></li> <li><a href="/wiki/Knowledge_base" title="Knowledge base">Knowledge base</a></li> <li><a href="/wiki/Computer_file" title="Computer file">Computer file</a></li> <li><a href="/wiki/Object_file" title="Object file">Object file</a></li> <li><a href="/wiki/File_deletion" title="File deletion">File deletion</a></li> <li><a href="/wiki/File_copying" title="File copying">File copying</a></li> <li><a href="/wiki/Backup" title="Backup">Backup</a></li> <li><a href="/wiki/Core_dump" title="Core dump">Core dump</a></li> <li><a href="/wiki/Hex_dump" title="Hex dump">Hex dump</a></li> <li><a href="/wiki/Data_communication" title="Data communication">Data communication</a></li> <li><a href="/wiki/Information_transfer" title="Information transfer">Information transfer</a></li> <li><a href="/wiki/Temporary_file" title="Temporary file">Temporary file</a></li> <li><a href="/wiki/Copy_protection" title="Copy protection">Copy protection</a></li> <li><a href="/wiki/Digital_rights_management" title="Digital rights management">Digital rights management</a></li> <li><a href="/wiki/Volume_(computing)" title="Volume (computing)">Volume (computing)</a></li> <li><a href="/wiki/Boot_sector" title="Boot sector">Boot sector</a></li> <li><a href="/wiki/Master_boot_record" title="Master boot record">Master boot record</a></li> <li><a href="/wiki/Volume_boot_record" title="Volume boot record">Volume boot record</a></li> <li><a href="/wiki/Disk_array" title="Disk array">Disk array</a></li> <li><a href="/wiki/Disk_image" title="Disk image">Disk image</a></li> <li><a href="/wiki/Disk_mirroring" title="Disk mirroring">Disk mirroring</a></li> <li><a href="/wiki/Disk_aggregation" title="Disk aggregation">Disk aggregation</a></li> <li><a href="/wiki/Disk_partitioning" title="Disk partitioning">Disk partitioning</a></li> <li><a href="/wiki/Memory_segmentation" title="Memory segmentation">Memory segmentation</a></li> <li><a href="/wiki/Locality_of_reference" title="Locality of reference">Locality of reference</a></li> <li><a href="/wiki/Logical_disk" title="Logical disk">Logical disk</a></li> <li><a href="/wiki/Storage_virtualization" title="Storage virtualization">Storage virtualization</a></li> <li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Memory-mapped_file" title="Memory-mapped file">Memory-mapped file</a></li> <li><a href="/wiki/Software_entropy" class="mw-redirect" title="Software entropy">Software entropy</a></li> <li><a href="/wiki/Software_rot" title="Software rot">Software rot</a></li> <li><a href="/wiki/In-memory_database" title="In-memory database">In-memory database</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory processing</a></li> <li><a href="/wiki/Persistence_(computer_science)" title="Persistence (computer science)">Persistence (computer science)</a></li> <li><a href="/wiki/Persistent_data_structure" title="Persistent data structure">Persistent data structure</a></li> <li><a href="/wiki/RAID" title="RAID">RAID</a></li> <li><a href="/wiki/Non-RAID_drive_architectures" title="Non-RAID drive architectures">Non-RAID drive architectures</a></li> <li><a href="/wiki/Memory_paging" title="Memory paging">Memory paging</a></li> <li><a href="/wiki/Bank_switching" title="Bank switching">Bank switching</a></li> <li><a href="/wiki/Grid_computing" title="Grid computing">Grid computing</a></li> <li><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a></li> <li><a href="/wiki/Cloud_storage" title="Cloud storage">Cloud storage</a></li> <li><a href="/wiki/Fog_computing" title="Fog computing">Fog computing</a></li> <li><a href="/wiki/Edge_computing" title="Edge computing">Edge computing</a></li> <li><a href="/wiki/Dew_computing" title="Dew computing">Dew computing</a></li> <li><a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a></li> <li><a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a></li> <li><a href="/wiki/Mark_Kryder#Kryder's_law_projection" title="Mark Kryder">Kryder's law</a></li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Volatile_memory" title="Volatile memory">Volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Cache_(computing)#HARDWARE" title="Cache (computing)">Hardware cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li></ul></li> <li><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a> <ul><li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a class="mw-selflink selflink">SDRAM</a></li> <li><a class="mw-selflink-fragment" href="#Synchronous_Graphics_RAM_(SGRAM)">SGRAM</a></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a></li> <li><a href="/wiki/Quad_Data_Rate_SRAM" title="Quad Data Rate SRAM">QDRSRAM</a></li> <li><a href="/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM" title="Dynamic random-access memory">EDO DRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a></li> <li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a></li></ul></li> <li><a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> <ul><li><a href="/wiki/1T-SRAM" title="1T-SRAM">1T-SRAM</a></li></ul></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">QRAM</a></li> <li><a href="/wiki/Content-addressable_memory" title="Content-addressable memory">Content-addressable memory</a> (CAM)</li> <li><a href="/wiki/Computational_RAM" title="Computational RAM">Computational RAM</a></li> <li><a href="/wiki/Video_random_access_memory" class="mw-redirect" title="Video random access memory">VRAM</a></li> <li><a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">Dual-ported RAM</a> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">Video RAM (dual-ported DRAM)</a></li></ul></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Williams_tube" title="Williams tube">Williams–Kilburn tube</a> (1946–1947)</li> <li><a href="/wiki/Delay-line_memory" title="Delay-line memory">Delay-line memory</a> (1947)</li> <li><a href="/wiki/Mellon_optical_memory" title="Mellon optical memory">Mellon optical memory</a> (1951)</li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a> (1952)</li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/T-RAM" title="T-RAM">T-RAM</a> (2009)</li> <li><a href="/wiki/Z-RAM" title="Z-RAM">Z-RAM</a> (2002–2010)</li></ul></div></div></td> </tr><tr><th class="sidebar-heading"> <a href="/wiki/Non-volatile_memory" title="Non-volatile memory">Non-volatile</a></th></tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Diode_matrix" title="Diode matrix">Diode matrix</a></li> <li><a href="/wiki/Read-only_memory#Factory-programmed" title="Read-only memory">MROM</a></li> <li><a href="/wiki/Programmable_ROM" title="Programmable ROM">PROM</a> <ul><li><a href="/wiki/EPROM" title="EPROM">EPROM</a></li> <li><a href="/wiki/EEPROM" title="EEPROM">EEPROM</a></li></ul></li> <li><a href="/wiki/ROM_cartridge" title="ROM cartridge">ROM cartridge</a></li> <li><a href="/wiki/Solid-state_storage" title="Solid-state storage">Solid-state storage</a> (SSS) <ul><li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> is used in:</li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">Solid-state drive</a> (SSD)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">Solid-state hybrid drive</a> (SSHD)</li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li> <li><a href="/wiki/IBM_FlashSystem" title="IBM FlashSystem">IBM FlashSystem</a></li> <li><a href="/wiki/Flash_Core_Module" title="Flash Core Module">Flash Core Module</a></li></ul></li> <li><a href="/wiki/Memory_card" title="Memory card">Memory card</a> <ul><li><a href="/wiki/Memory_Stick" title="Memory Stick">Memory Stick</a></li> <li><a href="/wiki/CompactFlash" title="CompactFlash">CompactFlash</a></li> <li><a href="/wiki/PC_Card" title="PC Card">PC Card</a></li> <li><a href="/wiki/MultiMediaCard" title="MultiMediaCard">MultiMediaCard</a></li> <li><a href="/wiki/SD_card" title="SD card">SD card</a></li> <li><a href="/wiki/SIM_card" title="SIM card">SIM card</a></li> <li><a href="/wiki/SmartMedia" title="SmartMedia">SmartMedia</a></li> <li><a href="/wiki/Universal_Flash_Storage" title="Universal Flash Storage">Universal Flash Storage</a></li> <li><a href="/wiki/SxS" title="SxS">SxS</a></li> <li><a href="/wiki/MicroP2" title="MicroP2">MicroP2</a></li> <li><a href="/wiki/XQD_card" title="XQD card">XQD card</a></li></ul></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">Programmable metallization cell</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Phase-change_memory" title="Phase-change memory">PCM</a> (<a href="/wiki/3D_XPoint" title="3D XPoint">3D XPoint</a>)</li> <li><a href="/wiki/Magnetoresistive_RAM" title="Magnetoresistive RAM">MRAM</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">Electrochemical RAM</a> (ECRAM)</li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">Nano-RAM</a></li> <li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Early-stage <a href="/wiki/Non-volatile_random-access_memory" title="Non-volatile random-access memory">NVRAM</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Ferroelectric_RAM" title="Ferroelectric RAM">FeRAM</a></li> <li><a href="/wiki/Resistive_random-access_memory" title="Resistive random-access memory">ReRAM</a></li> <li><a href="/wiki/Fe_FET" title="Fe FET">FeFET memory</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Analog_recording" title="Analog recording">Analog recording</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Phonograph_cylinder" title="Phonograph cylinder">Phonograph cylinder</a></li> <li><a href="/wiki/Phonograph_record" title="Phonograph record">Phonograph record</a></li> <li><a href="/wiki/Quadruplex_videotape" title="Quadruplex videotape">Quadruplex videotape</a></li> <li><a href="/wiki/Vision_Electronic_Recording_Apparatus" title="Vision Electronic Recording Apparatus">Vision Electronic Recording Apparatus</a></li> <li><a href="/wiki/Magnetic_recording" class="mw-redirect" title="Magnetic recording">Magnetic recording</a> <ul><li><a href="/wiki/Magnetic_storage" title="Magnetic storage">Magnetic storage</a></li> <li><a href="/wiki/Magnetic_tape" title="Magnetic tape">Magnetic tape</a></li> <li><a href="/wiki/Magnetic-tape_data_storage" title="Magnetic-tape data storage">Magnetic-tape data storage</a></li> <li><a href="/wiki/Tape_drive" title="Tape drive">Tape drive</a></li> <li><a href="/wiki/Tape_library" title="Tape library">Tape library</a></li> <li><a href="/wiki/Digital_Data_Storage" title="Digital Data Storage">Digital Data Storage</a> (DDS)</li> <li><a href="/wiki/Videotape" title="Videotape">Videotape</a></li> <li><a href="/wiki/Videocassette" class="mw-redirect" title="Videocassette">Videocassette</a></li> <li><a href="/wiki/Cassette_tape" title="Cassette tape">Cassette tape</a></li> <li><a href="/wiki/Linear_Tape-Open" title="Linear Tape-Open">Linear Tape-Open</a></li> <li><a href="/wiki/Betamax" title="Betamax">Betamax</a></li> <li><a href="/wiki/8_mm_video_format" title="8 mm video format">8 mm video format</a></li> <li><a href="/wiki/DV_(video_format)" title="DV (video format)">DV</a></li> <li><a href="/wiki/MiniDV" class="mw-redirect" title="MiniDV">MiniDV</a></li> <li><a href="/wiki/MicroMV" title="MicroMV">MicroMV</a></li> <li><a href="/wiki/U-matic" title="U-matic">U-matic</a></li> <li><a href="/wiki/VHS" title="VHS">VHS</a></li> <li><a href="/wiki/S-VHS" title="S-VHS">S-VHS</a></li> <li><a href="/wiki/VHS-C" title="VHS-C">VHS-C</a></li> <li><a href="/wiki/D-VHS" title="D-VHS">D-VHS</a></li></ul></li> <li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">Hard disk drive</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)"><a href="/wiki/Optical_storage" title="Optical storage">Optical</a></div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/3D_optical_data_storage" title="3D optical data storage">3D optical data storage</a> <ul><li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a></li> <li><a href="/wiki/LaserDisc" title="LaserDisc">LaserDisc</a></li> <li><a href="/wiki/Compact_Disc_Digital_Audio" title="Compact Disc Digital Audio">Compact Disc Digital Audio</a> (CDDA)</li> <li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/CD_Video" title="CD Video">CD Video</a></li> <li><a href="/wiki/CD-R" title="CD-R">CD-R</a></li> <li><a href="/wiki/CD-RW" title="CD-RW">CD-RW</a></li> <li><a href="/wiki/Video_CD" title="Video CD">Video CD</a></li> <li><a href="/wiki/Super_Video_CD" title="Super Video CD">Super Video CD</a></li> <li><a href="/wiki/Mini_CD" title="Mini CD">Mini CD</a></li> <li><a href="/wiki/Nintendo_optical_discs" title="Nintendo optical discs">Nintendo optical discs</a></li> <li><a href="/wiki/CD-ROM" title="CD-ROM">CD-ROM</a></li> <li><a href="/wiki/Hyper_CD-ROM" title="Hyper CD-ROM">Hyper CD-ROM</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/DVD_recordable#DVD+R_and_DVD+RW_(DVD_"plus")" title="DVD recordable">DVD+R</a></li> <li><a href="/wiki/DVD-Video" title="DVD-Video">DVD-Video</a></li> <li><a href="/wiki/DVD_card" title="DVD card">DVD card</a></li> <li><a href="/wiki/DVD-RAM" title="DVD-RAM">DVD-RAM</a></li> <li><a href="/wiki/MiniDVD" title="MiniDVD">MiniDVD</a></li> <li><a href="/wiki/HD_DVD" title="HD DVD">HD DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li> <li><a href="/wiki/Ultra_HD_Blu-ray" title="Ultra HD Blu-ray">Ultra HD Blu-ray</a></li> <li><a href="/wiki/Holographic_Versatile_Disc" title="Holographic Versatile Disc">Holographic Versatile Disc</a></li></ul></li> <li><a href="/wiki/Write_once_read_many" title="Write once read many">WORM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">In development</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Programmable_metallization_cell" title="Programmable metallization cell">CBRAM</a></li> <li><a href="/wiki/Racetrack_memory" title="Racetrack memory">Racetrack memory</a></li> <li><a href="/wiki/Nano-RAM" title="Nano-RAM">NRAM</a></li> <li><a href="/wiki/Millipede_memory" title="Millipede memory">Millipede memory</a></li> <li><a href="/wiki/Electrochemical_RAM" title="Electrochemical RAM">ECRAM</a></li> <li><a href="/wiki/Patterned_media" title="Patterned media">Patterned media</a></li> <li><a href="/wiki/Holographic_data_storage" title="Holographic data storage">Holographic data storage</a> <ul><li><a href="/wiki/Electronic_quantum_holography" title="Electronic quantum holography">Electronic quantum holography</a></li></ul></li> <li><a href="/wiki/5D_optical_data_storage" title="5D optical data storage">5D optical data storage</a></li> <li><a href="/wiki/DNA_digital_data_storage" title="DNA digital data storage">DNA digital data storage</a></li> <li><a href="/wiki/Universal_memory" title="Universal memory">Universal memory</a></li> <li><a href="/wiki/Time_crystal" title="Time crystal">Time crystal</a></li> <li><a href="/wiki/Quantum_memory" title="Quantum memory">Quantum memory</a></li> <li><a href="/wiki/UltraRAM" title="UltraRAM">UltraRAM</a></li></ul></div></div></td> </tr><tr><td class="sidebar-content"> <div class="sidebar-list mw-collapsible mw-collapsed"><div class="sidebar-list-title" style="color: var(--color-base)">Historical</div><div class="sidebar-list-content mw-collapsible-content"> <ul><li><a href="/wiki/Paper_data_storage" title="Paper data storage">Paper data storage</a> (1725)</li> <li><a href="/wiki/Punched_card" title="Punched card">Punched card</a> (1725)</li> <li><a href="/wiki/Punched_tape" title="Punched tape">Punched tape</a> (1725)</li> <li><a href="/wiki/Plugboard" title="Plugboard">Plugboard</a></li> <li><a href="/wiki/Drum_memory" title="Drum memory">Drum memory</a> (1932)</li> <li><a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">Magnetic-core memory</a> (1949)</li> <li><a href="/wiki/Plated-wire_memory" title="Plated-wire memory">Plated-wire memory</a> (1957)</li> <li><a href="/wiki/Core_rope_memory" title="Core rope memory">Core rope memory</a> (1960s)</li> <li><a href="/wiki/Thin-film_memory" title="Thin-film memory">Thin-film memory</a> (1962)</li> <li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a> (1962)</li> <li><a href="/wiki/Twistor_memory" title="Twistor memory">Twistor memory</a> (~1968)</li> <li><a href="/wiki/Bubble_memory" title="Bubble memory">Bubble memory</a> (~1970)</li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a> (1971)</li></ul></div></div></td> </tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Memory_types" title="Template:Memory types"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Memory_types" title="Template talk:Memory types"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Memory_types" title="Special:EditPage/Template:Memory types"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SDRAM_memory_module.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/75/SDRAM_memory_module.jpg/220px-SDRAM_memory_module.jpg" decoding="async" width="220" height="221" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/75/SDRAM_memory_module.jpg/330px-SDRAM_memory_module.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/75/SDRAM_memory_module.jpg/440px-SDRAM_memory_module.jpg 2x" data-file-width="2398" data-file-height="2409" /></a><figcaption>SDRAM memory module</figcaption></figure> <p><b>Synchronous dynamic random-access memory</b> (<b>synchronous dynamic RAM</b> or <b>SDRAM</b>) is any <a href="/wiki/Dynamic_RAM" class="mw-redirect" title="Dynamic RAM">DRAM</a> where the operation of its external pin interface is coordinated by an externally supplied <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a>. </p><p>DRAM <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs) produced from the early 1970s to the early 1990s used an <i>asynchronous</i> interface, in which input control signals have a direct effect on internal functions delayed only by the trip across its semiconductor pathways. SDRAM has a <i>synchronous</i> interface, whereby changes on control inputs are recognised after a rising edge of its clock input. In SDRAM families standardized by <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a>, the clock signal controls the stepping of an internal <a href="/wiki/Finite-state_machine" title="Finite-state machine">finite-state machine</a> that responds to incoming commands. These commands can be pipelined to improve performance, with previously started operations completing while new commands are received. The memory is divided into several equally sized but independent sections called <i><a href="/wiki/Memory_bank" title="Memory bank">banks</a></i>, allowing the device to operate on a memory access command in each bank simultaneously and speed up access in an <a href="/wiki/Interleaved_memory" title="Interleaved memory">interleaved</a> fashion. This allows SDRAMs to achieve greater concurrency and higher data transfer rates than asynchronous DRAMs could. </p><p><a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">Pipelining</a> means that the chip can accept a new command before it has finished processing the previous one. For a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written into the memory array. For a pipelined read, the requested data appears a fixed number of clock cycles (latency) after the read command, during which additional commands can be sent. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SDR_SDRAM-1.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/8b/SDR_SDRAM-1.jpg/220px-SDR_SDRAM-1.jpg" decoding="async" width="220" height="58" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/8b/SDR_SDRAM-1.jpg/330px-SDR_SDRAM-1.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/8b/SDR_SDRAM-1.jpg/440px-SDR_SDRAM-1.jpg 2x" data-file-width="1697" data-file-height="450" /></a><figcaption>Eight <a href="/wiki/Hyundai_Electronics" class="mw-redirect" title="Hyundai Electronics">Hyundai</a> SDRAM ICs on a PC100 <a href="/wiki/DIMM" title="DIMM">DIMM</a> package</figcaption></figure> <p>The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>In the late 1980s <a href="/wiki/IBM" title="IBM">IBM</a> invented DDR SDRAM, they built a <a href="/wiki/Double_data_rate" title="Double data rate">dual-edge clocking</a> RAM and presented their results at the International Solid-State Circuits Convention in 1990.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> In 1998, <a href="/wiki/Samsung" title="Samsung">Samsung</a> released a <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> SDRAM, known as <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, chip (64<span class="nowrap"> </span><a href="/wiki/Megabit" class="mw-redirect" title="Megabit">Mbit</a>) followed soon after by <a href="/wiki/Hyundai_Electronics" class="mw-redirect" title="Hyundai Electronics">Hyundai Electronics</a> (now <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a>) the same year and mass-produced in 1993.<sup id="cite_ref-electronic-design_5-0" class="reference"><a href="#cite_note-electronic-design-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> By 2000, SDRAM had replaced virtually all other types of <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a> in modern computers, because of its greater performance. </p><p>SDRAM latency is not inherently lower (faster access times) than asynchronous DRAM. Indeed, early SDRAM was somewhat slower than contemporaneous <a href="/wiki/Burst_EDO_DRAM" class="mw-redirect" title="Burst EDO DRAM">burst EDO DRAM</a> due to the additional logic. The benefits of SDRAM's internal buffering come from its ability to interleave operations to multiple banks of memory, thereby increasing effective <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a>. </p><p>Today, virtually all SDRAM is manufactured in compliance with standards established by <a href="/wiki/JEDEC" title="JEDEC">JEDEC</a>, an electronics industry association that adopts <a href="/wiki/Open_standards" class="mw-redirect" title="Open standards">open standards</a> to facilitate interoperability of electronic components. JEDEC formally adopted its first SDRAM standard in 1993 and subsequently adopted other SDRAM standards, including those for <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a>, <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> and <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a>. </p><p>SDRAM is also available in <a href="/wiki/Registered_memory" title="Registered memory">registered</a> varieties, for systems that require greater scalability such as <a href="/wiki/Server_(computing)" title="Server (computing)">servers</a> and <a href="/wiki/Workstations" class="mw-redirect" title="Workstations">workstations</a>. </p><p>Today, the world's largest manufacturers of SDRAM include <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a>, <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a>, <a href="/wiki/Micron_Technology" title="Micron Technology">Micron Technology</a>, and <a href="/wiki/Nanya_Technology" class="mw-redirect" title="Nanya Technology">Nanya Technology</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Timing">Timing</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=2" title="Edit section: Timing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>There are several limits on DRAM performance. Most noted is the read cycle time, the time between successive read operations to an open row. This time decreased from 10 ns for 100 MHz SDRAM (1 MHz = <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle 10^{6}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msup> <mn>10</mn> <mrow class="MJX-TeXAtom-ORD"> <mn>6</mn> </mrow> </msup> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle 10^{6}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/3ffb66117ef0a7ccf37efe85652c7b3e829f32fb" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.338ex; width:3.379ex; height:2.676ex;" alt="{\displaystyle 10^{6}}"></span> Hz) to 5 ns for DDR-400, but remained relatively unchanged through DDR2-800 and DDR3-1600 generations. However, by operating the interface circuitry at increasingly higher multiples of the fundamental read rate, the achievable bandwidth has increased rapidly. </p><p>Another limit is the <a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a>, the time between supplying a column address and receiving the corresponding data. Again, this has remained relatively constant at 10–15 ns through the last few generations of DDR SDRAM. </p><p>In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low. At higher clock rates, the useful CAS latency in clock cycles naturally increases. 10–15 ns is 2–3 cycles (CL2–3) of the 200 MHz clock of DDR-400 SDRAM, CL4-6 for DDR2-800, and CL8-12 for DDR3-1600. Slower clock cycles will naturally allow lower numbers of CAS latency cycles. </p><p>SDRAM modules have their own timing specifications, which may be slower than those of the chips on the module. When 100 MHz SDRAM chips first appeared, some manufacturers sold "100 MHz" modules that could not reliably operate at that clock rate. In response, Intel published the PC100 standard, which outlines requirements and guidelines for producing a memory module that can operate reliably at 100 MHz. This standard was widely influential, and the term "PC100" quickly became a common identifier for 100 MHz SDRAM modules, and modules are now commonly designated with "PC"-prefixed numbers (PC66, PC100 or PC133 - although the actual meaning of the numbers has changed). </p> <div class="mw-heading mw-heading2"><h2 id="Control_signals">Control signals</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=3" title="Edit section: Control signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>All commands are timed relative to the rising edge of a clock signal. In addition to the clock, there are six control signals, mostly <a href="/wiki/Logic_level" title="Logic level">active low</a>, which are sampled on the rising edge of the clock: </p> <ul><li><b>CKE</b> clock enable. When this signal is low, the chip behaves as if the clock has stopped. No commands are interpreted and command latency times do not elapse. The state of other control lines is not relevant. The effect of this signal is actually delayed by one clock cycle. That is, the current clock cycle proceeds as usual, but the following clock cycle is ignored, except for testing the CKE input again. Normal operations resume on the rising edge of the clock after the one where CKE is sampled high. Put another way, all other chip operations are timed relative to the rising edge of a masked clock. The masked clock is the logical AND of the input clock and the state of the CKE signal during the previous rising edge of the input clock.</li> <li><b><span style="text-decoration:overline;">CS</span></b> chip select. When this signal is high, the chip ignores all other inputs (except for CKE), and acts as if a NOP command is received.</li> <li><b>DQM</b> data mask. (The letter <i>Q</i> appears because, following digital logic conventions, the data lines are known as "DQ" lines.) When high, these signals suppress data I/O. When accompanying write data, the data is not actually written to the DRAM. When asserted high two cycles before a read cycle, the read data is not output from the chip. There is one DQM line per 8 bits on a x16 memory chip or DIMM.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Command_signals">Command signals</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=4" title="Edit section: Command signals"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b><span style="text-decoration:overline;">RAS</span></b>, row address strobe. Despite the name, this is <i>not</i> a strobe, but rather simply a command bit. Along with <span style="text-decoration:overline;">CAS</span> and <span style="text-decoration:overline;">WE</span>, this selects one of eight commands.</li> <li><b><span style="text-decoration:overline;">CAS</span></b>, column address strobe. This is also not a strobe, rather a command bit. Along with <span style="text-decoration:overline;">RAS</span> and <span style="text-decoration:overline;">WE</span>, this selects one of eight commands.</li> <li><b><span style="text-decoration:overline;">WE</span></b>, write enable. Along with <span style="text-decoration:overline;">RAS</span> and <span style="text-decoration:overline;">CAS</span>, this selects one of eight commands. It generally distinguishes read-like commands from write-like commands.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Bank_selection_(BAn)"><span id="Bank_selection_.28BAn.29"></span>Bank selection (BAn)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=5" title="Edit section: Bank selection (BAn)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SDRAM devices are internally divided into either two, four or eight independent internal data banks. One to three bank address inputs (BA0, BA1 and BA2) are used to select which bank a command is directed toward. </p> <div class="mw-heading mw-heading3"><h3 id="Addressing_(A10/An)"><span id="Addressing_.28A10.2FAn.29"></span>Addressing (A10/An)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=6" title="Edit section: Addressing (A10/An)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Many commands also use an address presented on the address input pins. Some commands, which either do not use an address, or present a column address, also use A10 to select variants. </p> <div class="mw-heading mw-heading3"><h3 id="Commands">Commands</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=7" title="Edit section: Commands"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The SDR SDRAM commands are defined as follows: </p> <table class="wikitable" style="text-align:center"> <tbody><tr> <th><span style="text-decoration:overline;">CS</span></th> <th><span style="text-decoration:overline;">RAS</span></th> <th><span style="text-decoration:overline;">CAS</span></th> <th><span style="text-decoration:overline;">WE</span></th> <th>BA<i>n</i></th> <th>A10</th> <th>A<i>n</i></th> <th>Command </th></tr> <tr> <td bgcolor="#ffcccc">H</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td align="left">Command inhibit (no operation) </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td align="left">No operation </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td align="left">Burst terminate: stop a burst read or burst write in progress </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td>bank</td> <td bgcolor="#ccffcc">L</td> <td>column</td> <td align="left">Read: read a burst of data from the currently active row </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td>bank</td> <td bgcolor="#ffcccc">H</td> <td>column</td> <td align="left">Read with auto precharge: as above, and precharge (close row) when done </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td>bank</td> <td bgcolor="#ccffcc">L</td> <td>column</td> <td align="left">Write: write a burst of data to the currently active row </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td>bank</td> <td bgcolor="#ffcccc">H</td> <td>column</td> <td align="left">Write with auto precharge: as above, and precharge (close row) when done </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ffcccc">H</td> <td>bank</td> <td colspan="2">row</td> <td align="left">Active (activate): open a row for read and write commands </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td>bank</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="lightgrey">x</td> <td align="left">Precharge: deactivate (close) the current row of selected bank </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="lightgrey">x</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="lightgrey">x</td> <td align="left">Precharge all: deactivate (close) the current row of all banks </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ffcccc">H</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td bgcolor="lightgrey">x</td> <td align="left">Auto refresh: refresh one row of each bank, using an internal counter. All banks must be precharged. </td></tr> <tr> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td bgcolor="#ccffcc">L</td> <td>0 0</td> <td colspan="2">mode</td> <td align="left">Load mode register: A0 through A9 are loaded to configure the DRAM chip.<br />The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles) </td></tr></tbody></table> <p>All SDRAM generations (SDR and DDRx) use essentially the same commands, with the changes being: </p> <ul><li>Additional address bits to support larger devices</li> <li>Additional bank select bits</li> <li>Wider mode registers (DDR2 and up use 13 bits, A0–A12)</li> <li>Additional extended mode registers (selected by the bank address bits)</li> <li>DDR2 deletes the burst terminate command; DDR3 reassigns it as "ZQ calibration"</li> <li>DDR3 and DDR4 use A12 during read and write command to indicate "burst chop", half-length data transfer</li> <li><a href="/wiki/DDR4#Command_encoding" class="mw-redirect" title="DDR4">DDR4 changes the encoding</a> of the activate command. A new signal <span style="text-decoration:overline;">ACT</span> controls it, during which the other control lines are used as row address bits 16, 15 and 14. When <span style="text-decoration:overline;">ACT</span> is high, other commands are the same as above.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Construction_and_operation">Construction and operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=8" title="Edit section: Construction and operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SDRAM_memory_module,_zoomed.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e3/SDRAM_memory_module%2C_zoomed.jpg/220px-SDRAM_memory_module%2C_zoomed.jpg" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e3/SDRAM_memory_module%2C_zoomed.jpg/330px-SDRAM_memory_module%2C_zoomed.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e3/SDRAM_memory_module%2C_zoomed.jpg/440px-SDRAM_memory_module%2C_zoomed.jpg 2x" data-file-width="2448" data-file-height="3264" /></a><figcaption>SDRAM memory module, zoomed</figcaption></figure> <p>As an example, a 512 MB SDRAM DIMM (which contains 512 MB), might be made of eight or nine SDRAM chips, each containing 512 Mbit of storage, and each one contributing 8 bits to the DIMM's 64- or 72-bit width. A typical 512 Mbit SDRAM <i>chip</i> internally contains four independent 16 MB memory banks. Each bank is an array of 8,192 rows of 16,384 bits each. (2048 8-bit columns). A bank is either idle, active, or changing from one to the other.<sup id="cite_ref-binpre_6-0" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>The <i>active</i> command activates an idle bank. It presents a two-bit bank address (BA0–BA1) and a 13-bit row address (A0–A12), and causes a read of that row into the bank's array of all 16,384 column sense amplifiers. This is also known as "opening" the row. This operation has the side effect of <a href="/wiki/Memory_refresh" title="Memory refresh">refreshing</a> the dynamic (capacitive) memory storage cells of that row. </p><p>Once the row has been activated or "opened", <i>read</i> and <i>write</i> commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay, or t<sub>RCD</sub> before reads or writes to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an <i>active</i> command, and a <i>read</i> or <i>write</i> command. During these wait cycles, additional commands may be sent to other banks; because each bank operates completely independently. </p><p>Both <i>read</i> and <i>write</i> commands require a column address. Because each chip accesses eight bits of data at a time, there are 2,048 possible column addresses thus requiring only 11 address lines (A0–A9, A11). </p><p>When a <i>read</i> command is issued, the SDRAM will produce the corresponding output data on the DQ lines in time for the rising edge of the clock a few clock cycles later, depending on the configured CAS latency. Subsequent words of the burst will be produced in time for subsequent rising clock edges. </p><p>A <i>write</i> command is accompanied by the data to be written driven on to the DQ lines during the same rising clock edge. It is the duty of the memory controller to ensure that the SDRAM is not driving read data on to the DQ lines at the same time that it needs to drive write data on to those lines. This can be done by waiting until a read burst has finished, by terminating a read burst, or by using the DQM control line. </p><p>When the memory controller needs to access a different row, it must first return that bank's sense amplifiers to an idle state, ready to sense the next row. This is known as a "precharge" operation, or "closing" the row. A precharge may be commanded explicitly, or it may be performed automatically at the conclusion of a read or write operation. Again, there is a minimum time, the row precharge delay, t<sub>RP</sub>, which must elapse before that row is fully "closed" and so the bank is idle in order to receive another activate command on that bank. </p><p>Although refreshing a row is an automatic side effect of activating it, there is a minimum time for this to happen, which requires a minimum row access time t<sub>RAS</sub> delay between an <i>active</i> command opening a row, and the corresponding precharge command closing it. This limit is usually dwarfed by desired read and write commands to the row, so its value has little effect on typical performance. </p> <div class="mw-heading mw-heading2"><h2 id="Command_interactions">Command interactions</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=9" title="Edit section: Command interactions"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The no operation command is always permitted, while the load mode register command requires that all banks be idle, and a delay afterward for the changes to take effect. The auto refresh command also requires that all banks be idle, and takes a refresh cycle time t<sub>RFC</sub> to return the chip to the idle state. (This time is usually equal to t<sub>RCD</sub>+t<sub>RP</sub>.) The only other command that is permitted on an idle bank is the active command. This takes, as mentioned above, t<sub>RCD</sub> before the row is fully open and can accept read and write commands. </p><p>When a bank is open, there are four commands permitted: read, write, burst terminate, and precharge. Read and write commands begin bursts, which can be interrupted by following commands. </p> <div class="mw-heading mw-heading3"><h3 id="Interrupting_a_read_burst">Interrupting a read burst</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=10" title="Edit section: Interrupting a read burst"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A read, burst terminate, or precharge command may be issued at any time after a read command, and will interrupt the read burst after the configured CAS latency. So if a read command is issued on cycle 0, another read command is issued on cycle 2, and the CAS latency is 3, then the first read command will begin bursting data out during cycles 3 and 4, then the results from the second read command will appear beginning with cycle 5. </p><p>If the command issued on cycle 2 were burst terminate, or a precharge of the active bank, then no output would be generated during cycle 5. </p><p>Although the interrupting read may be to any active bank, a precharge command will only interrupt the read burst if it is to the same bank or all banks; a precharge command to a different bank will not interrupt a read burst. </p><p>Interrupting a read burst by a write command is possible, but more difficult. It can be done if the DQM signal is used to suppress output from the SDRAM so that the memory controller may drive data over the DQ lines to the SDRAM in time for the write operation. Because the effects of DQM on read data are delayed by two cycles, but the effects of DQM on write data are immediate, DQM must be raised (to mask the read data) beginning at least two cycles before write command but must be lowered for the cycle of the write command (assuming the write command is intended to have an effect). </p><p>Doing this in only two clock cycles requires careful coordination between the time the SDRAM takes to turn off its output on a clock edge and the time the data must be supplied as input to the SDRAM for the write on the following clock edge. If the clock frequency is too high to allow sufficient time, three cycles may be required. </p><p>If the read command includes auto-precharge, the precharge begins the same cycle as the interrupting command. </p> <div class="mw-heading mw-heading2"><h2 id="Burst_ordering"><span class="anchor" id="BURST"></span> Burst ordering</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=11" title="Edit section: Burst ordering"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A modern microprocessor with a <a href="/wiki/CPU_cache" title="CPU cache">cache</a> will generally access memory in units of <a href="/wiki/Cache_line" class="mw-redirect" title="Cache line">cache lines</a>. To transfer a 64-byte cache line requires eight consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by configuring the SDRAM chips, using the mode register, to perform eight-word <a href="/wiki/Burst_mode_(computing)" title="Burst mode (computing)">bursts</a>. A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first. ("Word" here refers to the width of the SDRAM chip or DIMM, which is 64 bits for a typical DIMM.) SDRAM chips support two possible conventions for the ordering of the remaining words in the cache line. </p><p>Bursts always access an aligned block of BL consecutive words beginning on a multiple of BL. So, for example, a four-word burst access to any column address from four to seven will return words four to seven. The ordering, however, depends on the requested address, and the configured burst type option: sequential or interleaved. Typically, a memory controller will require one or the other. When the burst length is one or two, the burst type does not matter. For a burst length of one, the requested word is the only word accessed. For a burst length of two, the requested word is accessed first, and the other word in the aligned block is accessed second. This is the following word if an even address was specified, and the previous word if an odd address was specified. </p><p>For the sequential <a href="/wiki/Burst_mode_(computing)" title="Burst mode (computing)">burst mode</a>, later words are accessed in increasing address order, wrapping back to the start of the block when the end is reached. So, for example, for a burst length of four, and a requested column address of five, the words would be accessed in the order 5-6-7-4. If the burst length were eight, the access order would be 5-6-7-0-1-2-3-4. This is done by adding a counter to the column address, and ignoring carries past the burst length. The interleaved burst mode computes the address using an <a href="/wiki/Exclusive_or" title="Exclusive or">exclusive or</a> operation between the counter and the address. Using the same starting address of five, a four-word burst would return words in the order 5-4-7-6. An eight-word burst would be 5-4-7-6-1-0-3-2.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Although more confusing to humans, this can be easier to implement in hardware, and is preferred by <a href="/wiki/Intel" title="Intel">Intel</a> for its microprocessors.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (August 2015)">citation needed</span></a></i>]</sup> </p><p>If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7. The difference only matters if fetching a cache line from memory in critical-word-first order. </p> <div class="mw-heading mw-heading2"><h2 id="Mode_register">Mode register</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=12" title="Edit section: Mode register"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Single data rate SDRAM has a single 10-bit programmable mode register. Later double-data-rate SDRAM standards add additional mode registers, addressed using the bank address pins. For SDR SDRAM, the bank address pins and address lines A10 and above are ignored, but should be zero during a mode register write. </p><p>The bits are M9 through M0, presented on address lines A9 through A0 during a load mode register cycle. </p> <ul><li>M9: Write burst mode. If 0, writes use the read burst length and mode. If 1, all writes are non-burst (single location).</li> <li>M8, M7: Operating mode. Reserved, and must be 00.</li> <li>M6, M5, M4: CAS latency. Generally only 010 (CL2) and 011 (CL3) are legal. Specifies the number of cycles between a read command and data output from the chip. The chip has a fundamental limit on this value in nanoseconds; during initialization, the memory controller must use its knowledge of the clock frequency to translate that limit into cycles.</li> <li>M3: Burst type. 0 - requests sequential burst ordering, while 1 requests interleaved burst ordering.</li> <li>M2, M1, M0: Burst length. Values of 000, 001, 010 and 011 specify a burst size of 1, 2, 4 or 8 words, respectively. Each read (and write, if M9 is 0) will perform that many accesses, unless interrupted by a burst stop or other command. A value of 111 specifies a full-row burst. The burst will continue until interrupted. Full-row bursts are only permitted with the sequential burst type.</li></ul> <p>Later (double data rate) SDRAM standards use more mode register bits, and provide additional mode registers called "extended mode registers". The register number is encoded on the bank address pins during the load mode register command. For example, DDR2 SDRAM has a 13-bit mode register, a 13-bit extended mode register No. 1 (EMR1), and a 5-bit extended mode register No. 2 (EMR2). </p> <div class="mw-heading mw-heading2"><h2 id="Auto_refresh">Auto refresh</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=13" title="Edit section: Auto refresh"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>It is possible to refresh a RAM chip by opening and closing (activating and precharging) each row in each bank. However, to simplify the memory controller, SDRAM chips support an "auto refresh" command, which performs these operations to one row in each bank simultaneously. The SDRAM also maintains an internal counter, which iterates over all possible rows. The memory controller must simply issue a sufficient number of auto refresh commands (one per row, 8192 in the example we have been using) every refresh interval (t<sub>REF</sub> = 64 ms is a common value). All banks must be idle (closed, precharged) when this command is issued. </p> <div class="mw-heading mw-heading2"><h2 id="Low_power_modes">Low power modes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=14" title="Edit section: Low power modes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As mentioned, the clock enable (CKE) input can be used to effectively stop the clock to an SDRAM. The CKE input is sampled each rising edge of the clock, and if it is low, the following rising edge of the clock is ignored for all purposes other than checking CKE. As long as CKE is low, it is permissible to change the clock rate, or even stop the clock entirely. </p><p>If CKE is lowered while the SDRAM is performing operations, it simply "freezes" in place until CKE is raised again. </p><p>If the SDRAM is idle (all banks precharged, no commands in progress) when CKE is lowered, the SDRAM automatically enters power-down mode, consuming minimal power until CKE is raised again. This must not last longer than the maximum refresh interval t<sub>REF</sub>, or memory contents may be lost. It is legal to stop the clock entirely during this time for additional power savings. </p><p>Finally, if CKE is lowered at the same time as an auto-refresh command is sent to the SDRAM, the SDRAM enters self-refresh mode. This is like power down, but the SDRAM uses an on-chip timer to generate internal refresh cycles as necessary. The clock may be stopped during this time. While self-refresh mode consumes slightly more power than power-down mode, it allows the memory controller to be disabled entirely, which commonly more than makes up the difference. </p><p>SDRAM designed for battery-powered devices offers some additional power-saving options. One is temperature-dependent refresh; an on-chip temperature sensor reduces the refresh rate at lower temperatures, rather than always running it at the worst-case rate. Another is selective refresh, which limits self-refresh to a portion of the DRAM array. The fraction which is refreshed is configured using an extended mode register. The third, implemented in <a href="/wiki/Mobile_DDR" class="mw-redirect" title="Mobile DDR">Mobile DDR</a> (LPDDR) and LPDDR2 is "deep power down" mode, which invalidates the memory and requires a full reinitialization to exit from. This is activated by sending a "burst terminate" command while lowering CKE. </p> <div class="mw-heading mw-heading2"><h2 id="DDR_SDRAM_prefetch_architecture"><span class="anchor" id="PREFETCH"></span> DDR SDRAM prefetch architecture</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=15" title="Edit section: DDR SDRAM prefetch architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>DDR SDRAM employs prefetch architecture to allow quick and easy access to multiple <a href="/wiki/Data_word" class="mw-redirect" title="Data word">data words</a> located on a common physical row in the memory. </p><p>The prefetch architecture takes advantage of the specific characteristics of memory accesses to DRAM. Typical DRAM memory operations involve three phases: <a href="/w/index.php?title=Bitline&action=edit&redlink=1" class="new" title="Bitline (page does not exist)">bitline</a> precharge, row access, column access. Row access is the heart of a read operation, as it involves the careful sensing of the tiny signals in DRAM memory cells; it is the slowest phase of memory operation. However, once a row is read, subsequent column accesses to that same row can be very quick, as the sense amplifiers also act as latches. For reference, a row of a 1 <a href="/wiki/Gigabit" class="mw-redirect" title="Gigabit">Gbit</a><sup id="cite_ref-binpre_6-1" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> device is 2,048 <a href="/wiki/Bit" title="Bit">bits</a> wide, so internally 2,048 bits are read into 2,048 separate sense amplifiers during the row access phase. Row accesses might take 50 <a href="/wiki/Nanosecond" title="Nanosecond">ns</a>, depending on the speed of the DRAM, whereas column accesses off an open row are less than 10 ns. </p><p>Traditional DRAM architectures have long supported fast column access to bits on an open row. For an 8-bit-wide memory chip with a 2,048 bit wide row, accesses to any of the 256 datawords (2048/8) on the row can be very quick, provided no intervening accesses to other rows occur. </p><p>The drawback of the older fast column access method was that a new column address had to be sent for each additional dataword on the row. The address bus had to operate at the same frequency as the data bus. Prefetch architecture simplifies this process by allowing a single address request to result in multiple data words. </p><p>In a prefetch buffer architecture, when a memory access occurs to a row the buffer grabs a set of adjacent data words on the row and reads them out ("bursts" them) in rapid-fire sequence on the IO pins, without the need for individual column address requests. This assumes the CPU wants adjacent datawords in memory, which in practice is very often the case. For instance, in DDR1, two adjacent data words will be read from each chip in the same clock cycle and placed in the pre-fetch buffer. Each word will then be transmitted on consecutive rising and falling edges of the clock cycle. Similarly, in DDR2 with a 4n pre-fetch buffer, four consecutive data words are read and placed in buffer while a clock, which is twice faster than the internal clock of DDR, transmits each of the word in consecutive rising and falling edge of the faster external clock <sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>The prefetch buffer depth can also be thought of as the ratio between the core memory frequency and the IO frequency. In an 8n prefetch architecture (such as <a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a>), the IOs will operate 8 times faster than the memory core (each memory access results in a burst of 8 datawords on the IOs). Thus, a 200 MHz memory core is combined with IOs that each operate eight times faster (1600 megabits per second). If the memory has 16 IOs, the total read bandwidth would be 200 MHz x 8 datawords/access x 16 IOs = 25.6 gigabits per second (Gbit/s) or 3.2 gigabytes per second (GB/s). Modules with multiple DRAM chips can provide correspondingly higher bandwidth. </p><p>Each generation of SDRAM has a different prefetch buffer size: </p> <ul><li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>'s prefetch buffer size is 2n (two datawords per memory access)</li> <li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a>'s prefetch buffer size is 4n (four datawords per memory access)</li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a>'s prefetch buffer size is 8n (eight datawords per memory access)</li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a>'s prefetch buffer size is 8n (eight datawords per memory access)</li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a>'s prefetch buffer size is 8n; there is an additional mode of 16n</li></ul> <div class="mw-heading mw-heading2"><h2 id="Generations">Generations</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=16" title="Edit section: Generations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable floatright"> <caption>SDRAM feature map </caption> <tbody><tr> <th scope="col">Type </th> <th scope="col">Feature changes </th></tr> <tr> <th scope="row">SDRAM </th> <td><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li><span class="nowrap">V<sub>cc</sub> = 3.3 V</span></li><li>Signal: <a href="/wiki/Transistor%E2%80%93transistor_logic#Sub-types" title="Transistor–transistor logic">LVTTL</a></li></ul></div> </td></tr> <tr> <th scope="row"><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR1</a> </th> <td><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>Access is ≥2 words</li><li><a href="/wiki/Double_data_rate" title="Double data rate">Double clocked</a></li><li><span class="nowrap">V<sub>cc</sub> = 2.5 V</span></li><li><span class="nowrap">2.5 - 7.5 ns</span> per cycle</li><li>Signal: <a href="/wiki/Stub_Series_Terminated_Logic" title="Stub Series Terminated Logic">SSTL_2</a> (2.5V)<sup id="cite_ref-edn-dramconsumer_9-0" class="reference"><a href="#cite_note-edn-dramconsumer-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup></li></ul></div> </td></tr> <tr> <th scope="row"><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> </th> <td>Access is ≥4 words<br /> "Burst terminate" removed<br /> 4 units used in parallel<br /> <span class="nowrap">1.25 - 5 ns</span> per cycle<br /> Internal operations are at 1/2 the clock rate.<br /> Signal: <a href="/wiki/Stub_Series_Terminated_Logic" title="Stub Series Terminated Logic">SSTL_18</a> (1.8V)<sup id="cite_ref-edn-dramconsumer_9-1" class="reference"><a href="#cite_note-edn-dramconsumer-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <th scope="row"><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a> </th> <td>Access is ≥8 words<br /> Signal: <a href="/wiki/Stub_Series_Terminated_Logic" title="Stub Series Terminated Logic">SSTL_15</a> (1.5V)<sup id="cite_ref-edn-dramconsumer_9-2" class="reference"><a href="#cite_note-edn-dramconsumer-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup><br /> Much longer CAS latencies </td></tr> <tr> <th scope="row"><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a> </th> <td><span class="nowrap">V<sub>cc</sub> ≤ 1.2 V</span> point-to-point (single module per channel) </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="SDR">SDR</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=17" title="Edit section: SDR"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Micron_48LC32M8A2-AB.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/8/89/Micron_48LC32M8A2-AB.jpg/220px-Micron_48LC32M8A2-AB.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/8/89/Micron_48LC32M8A2-AB.jpg/330px-Micron_48LC32M8A2-AB.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/8/89/Micron_48LC32M8A2-AB.jpg/440px-Micron_48LC32M8A2-AB.jpg 2x" data-file-width="1202" data-file-height="901" /></a><figcaption>The 64 MB<sup id="cite_ref-binpre_6-2" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> of sound memory on the <a href="/wiki/Sound_Blaster_X-Fi" title="Sound Blaster X-Fi">Sound Blaster X-Fi Fatality Pro</a> <a href="/wiki/Sound_card" title="Sound card">sound card</a> is built from two <a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a> 48LC32M8A2 SDRAM chips. They run at 133 MHz (7.5 ns clock period) and have 8-bit wide data buses.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></figcaption></figure> <p>Originally simply known as <i>SDRAM</i>, single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin <a href="/wiki/DIMM" title="DIMM">DIMMs</a> that read or write 64 (non-ECC) or 72 (<a href="/wiki/ECC_memory" title="ECC memory">ECC</a>) bits at a time. </p><p>Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time. </p><p>Typical SDR SDRAM clock rates are 66, 100, and 133 MHz (periods of 15, 10, and 7.5 ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200 MHz were available. It operates at a voltage of 3.3 V. </p><p>This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors <a href="/wiki/Extended_data_out_DRAM" class="mw-redirect" title="Extended data out DRAM">extended data out DRAM</a> (EDO-RAM) and <a href="/wiki/Fast_page_mode_DRAM" class="mw-redirect" title="Fast page mode DRAM">fast page mode DRAM</a> (FPM-RAM) which took typically two or three clocks to transfer one word of data. </p> <div class="mw-heading mw-heading4"><h4 id="PC66">PC66</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=18" title="Edit section: PC66"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>PC66</b> refers to internal removable computer <a href="/wiki/Random-access_memory" title="Random-access memory">memory</a> standard defined by the <a href="/wiki/Joint_Electron_Device_Engineering_Council" class="mw-redirect" title="Joint Electron Device Engineering Council">JEDEC</a>. PC66 is Synchronous DRAM operating at a clock frequency of 66.66 MHz, on a 64-bit bus, at a voltage of 3.3 V. PC66 is available in 168-pin <a href="/wiki/DIMM" title="DIMM">DIMM</a> and 144-pin <a href="/wiki/SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a> form factors. The theoretical bandwidth is 533 MB/s. (1 MB/s = one million bytes per second) </p><p>This standard was used by <a href="/wiki/Original_Intel_Pentium_(P5_microarchitecture)" class="mw-redirect" title="Original Intel Pentium (P5 microarchitecture)">Intel Pentium</a> and <a href="/wiki/AMD_K6" title="AMD K6">AMD K6</a>-based PCs. It also features in the Beige <a href="/wiki/Power_Mac_G3" class="mw-redirect" title="Power Mac G3">Power Mac G3</a>, early <a href="/wiki/IBook" title="IBook">iBooks</a> and <a href="/wiki/PowerBook_G3" title="PowerBook G3">PowerBook G3s</a>. It is also used in many early <a href="/wiki/Intel_Celeron" class="mw-redirect" title="Intel Celeron">Intel Celeron</a> systems with a 66 MHz <a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a>. It was superseded by the PC100 and PC133 standards. </p> <div class="mw-heading mw-heading4"><h4 id="PC100">PC100</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=19" title="Edit section: PC100"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">For the Japanese home computer, see <a href="/wiki/NEC_PC-100" title="NEC PC-100">NEC PC-100</a>.</div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:SDRAM_128MB_133MHz.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/SDRAM_128MB_133MHz.jpg/250px-SDRAM_128MB_133MHz.jpg" decoding="async" width="250" height="66" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/SDRAM_128MB_133MHz.jpg/375px-SDRAM_128MB_133MHz.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9c/SDRAM_128MB_133MHz.jpg/500px-SDRAM_128MB_133MHz.jpg 2x" data-file-width="6600" data-file-height="1750" /></a><figcaption>DIMM: 168 pins and two notches</figcaption></figure> <p><b>PC100</b> is a standard for internal removable computer <a href="/wiki/Random-access_memory" title="Random-access memory">random-access memory</a>, defined by the <a href="/wiki/Joint_Electron_Device_Engineering_Council" class="mw-redirect" title="Joint Electron Device Engineering Council">JEDEC</a>. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin <a href="/wiki/DIMM" title="DIMM">DIMM</a> and 144-pin <a href="/wiki/SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a> <a href="/wiki/Computer_form_factor" class="mw-redirect" title="Computer form factor">form factors</a>. PC100 is <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> with PC66 and was superseded by the PC133 standard. </p><p>A module built out of 100 MHz SDRAM chips is not necessarily capable of operating at 100 MHz. The PC100 standard specifies the capabilities of the memory module as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory. </p> <div class="mw-heading mw-heading4"><h4 id="PC133">PC133</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=20" title="Edit section: PC133"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><b>PC133</b> is a computer memory standard defined by the <a href="/wiki/Joint_Electron_Device_Engineering_Council" class="mw-redirect" title="Joint Electron Device Engineering Council">JEDEC</a>. PC133 refers to <a href="/wiki/SDR_SDRAM" class="mw-redirect" title="SDR SDRAM">SDR SDRAM</a> operating at a clock frequency of 133 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC133 is available in 168-pin <a href="/wiki/DIMM" title="DIMM">DIMM</a> and 144-pin <a href="/wiki/SO-DIMM" class="mw-redirect" title="SO-DIMM">SO-DIMM</a> form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066 GB per second ([133.33 MHz * 64/8]=1.066 GB/s). (1 GB/s = one billion bytes per second) PC133 is <a href="/wiki/Backward_compatible" class="mw-redirect" title="Backward compatible">backward compatible</a> with PC100 and PC66. </p> <div class="mw-heading mw-heading3"><h3 id="DDR"><span class="anchor" id="DDR1"></span> DDR</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=21" title="Edit section: DDR"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a></div> <p>While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5 V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM. </p><p>DDR SDRAM (sometimes called <i>DDR1</i> for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words. </p><p>Typical DDR SDRAM clock rates are 133, 166 and 200 MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5 ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available. </p> <div class="mw-heading mw-heading3"><h3 id="DDR2">DDR2</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=22" title="Edit section: DDR2"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a></div> <p>DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips. </p><p>Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400 MHz (periods of 5, 3.75, 3 and 2.5 ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25 ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533 MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available. </p><p>Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100 MHz) has somewhat higher latency than DDR-400 (internal clock rate 200 MHz). </p> <div class="mw-heading mw-heading3"><h3 id="DDR3">DDR3</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=23" title="Edit section: DDR3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a></div> <p>DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600 M transfers/s (both edges of a 400–800 MHz clock), the internal RAM array has to perform 100–200 M fetches per second. </p><p>Again, with every doubling, the downside is the increased <a href="/wiki/Latency_(engineering)" title="Latency (engineering)">latency</a>. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a <a href="/wiki/CAS_latency" title="CAS latency">CAS latency</a> of 8 with DDR3-800 is 8/(400 MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM). </p><p>DDR3 memory chips are being made commercially,<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> and computer systems using them were available from the second half of 2007,<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> with significant usage from 2008 onwards.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> Initial clock rates were 400 and 533 MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800 MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> Performance up to DDR3-2800 (PC3 22400 modules) are available.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="DDR4">DDR4</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=24" title="Edit section: DDR4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a></div> <p>DDR4 SDRAM is the successor to <a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a>. It was revealed at the <a href="/wiki/Intel_Developer_Forum" title="Intel Developer Forum">Intel Developer Forum</a> in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012,<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> and later (during 2010) expected to be released in 2015,<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2. </p><p>The DDR4 chips run at 1.2 <a href="/wiki/Volt" title="Volt">V</a> or less,<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> compared to the 1.5 V of DDR3 chips, and have in excess of 2 billion <a href="/wiki/Data_transfer" class="mw-redirect" title="Data transfer">data transfers</a> per second. They were expected to be introduced at frequency rates of 2133 MHz, estimated to rise to a potential 4266 MHz<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> and lowered voltage of 1.05 V<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> by 2013. </p><p>DDR4 did <i>not</i> double the internal prefetch width again, but uses the same 8<i>n</i> prefetch as DDR3.<sup id="cite_ref-jedec_ddr3_ddr4_22-0" class="reference"><a href="#cite_note-jedec_ddr3_ddr4-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy. </p><p>In February 2009, <a href="/wiki/Samsung" title="Samsung">Samsung</a> validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> since, as of 2009, current DRAM chips were only beginning to migrate to a 50 nm process.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> In January 2011, <a href="/wiki/Samsung" title="Samsung">Samsung</a> announced the completion and release for testing of a 30 nm 2048 MB<sup id="cite_ref-binpre_6-3" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> DDR4 DRAM module. It has a maximum bandwidth of 2.13 <a href="/wiki/Gbit/s" class="mw-redirect" title="Gbit/s">Gbit/s</a> at 1.2 V, uses <a href="/wiki/Pseudo_open_drain" class="mw-redirect" title="Pseudo open drain">pseudo open drain</a> technology and draws 40% less power than an equivalent DDR3 module.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="DDR5">DDR5</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=25" title="Edit section: DDR5"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a></div> <p>In March 2017, JEDEC announced a DDR5 standard is under development,<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<sup id="cite_ref-anandtech-ddr5_28-0" class="reference"><a href="#cite_note-anandtech-ddr5-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Failed_successors">Failed successors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=26" title="Edit section: Failed successors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In addition to DDR, there were several other proposed memory technologies to succeed SDR SDRAM. </p> <div class="mw-heading mw-heading3"><h3 id="Rambus_DRAM_(RDRAM)"><span id="Rambus_DRAM_.28RDRAM.29"></span>Rambus DRAM (RDRAM)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=27" title="Edit section: Rambus DRAM (RDRAM)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a> was a proprietary technology that competed against DDR. Its relatively high price and disappointing performance (resulting from high latencies and a narrow 16-bit data channel versus DDR's 64 bit channel) caused it to lose the race to succeed SDR SDRAM. </p> <div class="mw-heading mw-heading3"><h3 id="Synchronous-link_DRAM_(SLDRAM)"><span id="Synchronous-link_DRAM_.28SLDRAM.29"></span>Synchronous-link DRAM (SLDRAM)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=28" title="Edit section: Synchronous-link DRAM (SLDRAM)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>SLDRAM boasted higher performance and competed against RDRAM. It was developed during the late 1990s by the SLDRAM Consortium. The SLDRAM Consortium consisted of about 20 major DRAM and computer industry manufacturers. (The SLDRAM Consortium became incorporated as SLDRAM Inc. and then changed its name to Advanced Memory International, Inc.) SLDRAM was an <a href="/wiki/Open_standard" title="Open standard">open standard</a> and did not require licensing fees. The specifications called for a 64-bit bus running at a 200, 300 or 400 MHz clock frequency. This is achieved by all signals being on the same line and thereby avoiding the synchronization time of multiple lines. Like <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a>, SLDRAM uses a double-pumped bus, giving it an effective speed of 400,<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> 600,<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> or 800 <a href="/wiki/MT/s" class="mw-redirect" title="MT/s">MT/s</a>. (1 MT/s = 1000^2 transfers per second) </p><p>SLDRAM used an 11-bit command bus (10 command bits CA9:0 plus one start-of-command FLAG line) to transmit 40-bit command packets on 4 consecutive edges of a differential command clock (CCLK/CCLK#). Unlike SDRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it. Data was transferred in 4- or 8-word bursts across an 18-bit (per chip) data bus, using one of two differential data clocks (DCLK0/DCLK0# and DCLK1/DCLK1#). Unlike standard SDRAM, the clock was generated by the data source (the SLDRAM chip in the case of a read operation) and transmitted in the same direction as the data, greatly reducing data skew. To avoid the need for a pause when the source of the DCLK changes, each command specified which DCLK pair it would use.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p>The basic read/write command consisted of (beginning with CA9 of the first word): </p> <table class="wikitable" style="text-align:center"> <caption>SLDRAM Read, write or row op request packet </caption> <tbody><tr> <th>FLAG</th> <th>CA9</th> <th>CA8</th> <th>CA7</th> <th>CA6</th> <th>CA5</th> <th>CA4</th> <th>CA3</th> <th>CA2</th> <th>CA1</th> <th>CA0 </th></tr> <tr> <th>1 </th> <td bgcolor="#ffcccc">ID8</td> <td colspan="7" bgcolor="#ffcccc">Device ID</td> <td bgcolor="#ffcccc">ID0</td> <td bgcolor="#ccffcc">CMD5 </td></tr> <tr> <th>0 </th> <td colspan="4" bgcolor="#ccffcc">Command code</td> <td bgcolor="#ccffcc">CMD0</td> <td colspan="3" bgcolor="#ff88ff">Bank</td> <td colspan="2" bgcolor="#ffffcc">Row </td></tr> <tr> <th>0 </th> <td colspan="9" bgcolor="#ffffcc">Row (continued)</td> <td bgcolor="lightgrey">0 </td></tr> <tr> <th>0 </th> <td bgcolor="lightgrey">0</td> <td bgcolor="lightgrey">0</td> <td bgcolor="lightgrey">0</td> <td colspan="7" bgcolor="#ccffff">Column </td></tr></tbody></table> <ul><li>9 bits of device ID</li> <li>6 bits of command</li> <li>3 bits of bank address</li> <li>10 or 11 bits of row address</li> <li>5 or 4 bits spare for row or column expansion</li> <li>7 bits of column address</li></ul> <p>Individual devices had 8-bit IDs. The 9th bit of the ID sent in commands was used to address multiple devices. Any aligned power-of-2 sized group could be addressed. If the transmitted msbit was set, all least-significant bits up to and including the least-significant 0 bit of the transmitted address were ignored for "is this addressed to me?" purposes. (If the ID8 bit is actually considered less significant than ID0, the unicast address matching becomes a special case of this pattern.) </p><p>A read/write command had the msbit clear: </p> <ul><li>CMD5=0</li> <li>CMD4=1 to open (activate) the specified row; CMD4=0 to use the currently open row</li> <li>CMD3=1 to transfer an 8-word burst; CMD3=0 for a 4-word burst</li> <li>CMD2=1 for a write, CMD2=0 for a read</li> <li>CMD1=1 to close the row after this access; CMD1=0 to leave it open</li> <li>CMD0 selects the DCLK pair to use (DCLK1 or DCLK0)</li></ul> <p>A notable omission from the specification was per-byte write enables; it was designed for systems with <a href="/wiki/CPU_cache" title="CPU cache">caches</a> and <a href="/wiki/ECC_memory" title="ECC memory">ECC memory</a>, which always write in multiples of a cache line. </p><p>Additional commands (with CMD5 set) opened and closed rows without a data transfer, performed refresh operations, read or wrote configuration registers, and performed other maintenance operations. Most of these commands supported an additional 4-bit sub-ID (sent as 5 bits, using the same multiple-destination encoding as the primary ID) which could be used to distinguish devices that were assigned the same primary ID because they were connected in parallel and always read/written at the same time. </p><p>There were a number of 8-bit control registers and 32-bit status registers to control various device timing parameters. </p> <div class="mw-heading mw-heading3"><h3 id="Virtual_channel_memory_(VCM)_SDRAM"><span id="Virtual_channel_memory_.28VCM.29_SDRAM"></span>Virtual channel memory (VCM) SDRAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=29" title="Edit section: Virtual channel memory (VCM) SDRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>VCM was a proprietary type of SDRAM that was designed by <a href="/wiki/NEC" title="NEC">NEC</a>, but released as an open standard with no licensing fees. It is pin-compatible with standard SDRAM, but the commands are different. The technology was a potential competitor of <a href="/wiki/RDRAM" title="RDRAM">RDRAM</a> because VCM was not nearly as expensive as RDRAM was. A Virtual Channel Memory (VCM) module is mechanically and electrically compatible with standard SDRAM, so support for both depends only on the capabilities of the <a href="/wiki/Memory_controller" title="Memory controller">memory controller</a>. In the late 1990s, a number of PC <a href="/wiki/Northbridge_(computing)" title="Northbridge (computing)">northbridge</a> chipsets (such as the popular <a href="/wiki/List_of_VIA_chipsets#Slot_A_and_Socket_A" title="List of VIA chipsets">VIA KX133 and KT133</a>) included VCSDRAM support. </p><p>VCM inserts an SRAM cache of 16 "channel" buffers, each 1/4 row "segment" in size, between DRAM banks' sense amplifier rows and the data I/O pins. "Prefetch" and "restore" commands, unique to VCSDRAM, copy data between the DRAM's sense amplifier row and the channel buffers, while the equivalent of SDRAM's read and write commands specify a channel number to access. Reads and writes may thus be performed independent of the currently active state of the DRAM array, with the equivalent of four full DRAM rows being "open" for access at a time. This is an improvement over the two open rows possible in a standard two-bank SDRAM. (There is actually a 17th "dummy channel" used for some operations.) </p><p>To read from VCSDRAM, after the active command, a "prefetch" command is required to copy data from the sense amplifier array to the channel SDRAM. This command specifies a bank, two bits of column address (to select the segment of the row), and four bits of channel number. Once this is performed, the DRAM array may be precharged while read commands to the channel buffer continue. To write, first the data is written to a channel buffer (typically previous initialized using a Prefetch command), then a restore command, with the same parameters as the prefetch command, copies a segment of data from the channel to the sense amplifier array. </p><p>Unlike a normal SDRAM write, which must be performed to an active (open) row, the VCSDRAM bank must be precharged (closed) when the restore command is issued. An active command immediately after the restore command specifies the DRAM row completes the write to the DRAM array. There is, in addition, a 17th "dummy channel" which allows writes to the currently open row. It may not be read from, but may be prefetched to, written to, and restored to the sense amplifier array.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> </p><p>Although normally a segment is restored to the same memory address as it was prefetched from, the channel buffers may also be used for very efficient copying or clearing of large, aligned memory blocks. (The use of quarter-row segments is driven by the fact that DRAM cells are narrower than SRAM cells.) The SRAM bits are designed to be four DRAM bits wide, and are conveniently connected to one of the four DRAM bits they straddle.) Additional commands prefetch a pair of segments to a pair of channels, and an optional command combines prefetch, read, and precharge to reduce the overhead of random reads. </p><p>The above are the JEDEC-standardized commands. Earlier chips did not support the dummy channel or pair prefetch, and use a different encoding for precharge. </p><p>A 13-bit address bus, as illustrated here, is suitable for a device up to 128 Mbit<sup id="cite_ref-binpre_6-4" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup>. It has two banks, each containing 8,192 rows and 8,192 columns. Thus, row addresses are 13 bits, segment addresses are two bits, and eight column address bits are required to select one byte from the 2,048 bits (256 bytes) in a segment. </p> <div class="mw-heading mw-heading2"><h2 id="Synchronous_Graphics_RAM_(SGRAM)"><span id="Synchronous_Graphics_RAM_.28SGRAM.29"></span><span class="anchor" id="SGRAM"></span>Synchronous Graphics RAM (SGRAM)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=30" title="Edit section: Synchronous Graphics RAM (SGRAM)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Synchronous graphics RAM (SGRAM) is a specialized form of SDRAM for graphics adaptors. It is designed for graphics-related tasks such as <a href="/wiki/Texture_memory" title="Texture memory">texture memory</a> and <a href="/wiki/Framebuffer" title="Framebuffer">framebuffers</a>, found on <a href="/wiki/Video_card" class="mw-redirect" title="Video card">video cards</a>. It adds functions such as <a href="/wiki/Bit_mask" class="mw-redirect" title="Bit mask">bit masking</a> (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour). Unlike <a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a> and <a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a>, SGRAM is single-ported. However, it can open two memory pages at once, which simulates the <a href="/wiki/Dual-ported_RAM" title="Dual-ported RAM">dual-port</a> nature of other video RAM technologies. </p><p>The earliest known SGRAM memory are 8<span class="nowrap"> </span>Mbit<sup id="cite_ref-binpre_6-5" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> chips dating back to 1994: the <a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> HM5283206, introduced in November 1994,<sup id="cite_ref-HM5283206_34-0" class="reference"><a href="#cite_note-HM5283206-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/NEC" title="NEC">NEC</a> μPD481850, introduced in December 1994.<sup id="cite_ref-D481850_35-0" class="reference"><a href="#cite_note-D481850-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> The earliest known commercial device to use SGRAM is <a href="/wiki/Sony" title="Sony">Sony</a>'s <a href="/wiki/PlayStation_(console)" title="PlayStation (console)">PlayStation</a> (PS) <a href="/wiki/Video_game_console" title="Video game console">video game console</a>, starting with the Japanese <a href="/wiki/PlayStation_models" title="PlayStation models">SCPH-5000</a> model released in December 1995, using the NEC μPD481850 chip.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-nec1995_37-0" class="reference"><a href="#cite_note-nec1995-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Graphics_double_data_rate_SDRAM_(GDDR_SDRAM)"><span id="Graphics_double_data_rate_SDRAM_.28GDDR_SDRAM.29"></span>Graphics double data rate SDRAM (GDDR SDRAM)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=31" title="Edit section: Graphics double data rate SDRAM (GDDR SDRAM)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR SDRAM</a></div> <p>Graphics <a href="/wiki/Double_data_rate" title="Double data rate">double data rate</a> SDRAM (<a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR SDRAM</a>) is a type of specialized <a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> designed to be used as the main memory of <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs). GDDR SDRAM is distinct from commodity types of DDR SDRAM such as DDR3, although they share some core technologies. Their primary characteristics are higher clock frequencies for both the DRAM core and I/O interface, which provides greater memory bandwidth for GPUs. As of 2023, there are eight successive generations of GDDR: <a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a>, <a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>, <a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>, <a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>, <a href="/wiki/GDDR5X" class="mw-redirect" title="GDDR5X">GDDR5X</a>, <a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a>, <a href="/wiki/GDDR6X" class="mw-redirect" title="GDDR6X">GDDR6X</a> and <a href="/wiki/GDDR6W" class="mw-redirect" title="GDDR6W">GDDR6W</a>. </p><p>GDDR was initially known as DDR SGRAM. It was commercially introduced as a 16<span class="nowrap"> </span><a href="/wiki/Megabit" class="mw-redirect" title="Megabit">Mbit</a><sup id="cite_ref-binpre_6-6" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> memory chip by <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung Electronics</a> in 1998.<sup id="cite_ref-samsung98_38-0" class="reference"><a href="#cite_note-samsung98-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="High_Bandwidth_Memory_(HBM)"><span id="High_Bandwidth_Memory_.28HBM.29"></span>High Bandwidth Memory (HBM)</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=32" title="Edit section: High Bandwidth Memory (HBM)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a></div> <p><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM) is a high-performance RAM interface for <a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D-stacked</a> SDRAM from <a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a>, <a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> and <a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a>. It is designed to be used in conjunction with high-performance graphics accelerators and network devices.<sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> The first HBM memory chip was produced by SK Hynix in 2013.<sup id="cite_ref-hynix2010s_40-0" class="reference"><a href="#cite_note-hynix2010s-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Timeline">Timeline</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=33" title="Edit section: Timeline"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Random-access_memory#Timeline" title="Random-access memory">Random-access memory § Timeline</a>, <a href="/wiki/Flash_memory#Timeline" title="Flash memory">Flash memory § Timeline</a>, and <a href="/wiki/Transistor_count#Memory" title="Transistor count">Transistor count § Memory</a></div><style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Update plainlinks metadata ambox ambox-content ambox-Update" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/42px-Ambox_current_red_Americas.svg.png" decoding="async" width="42" height="34" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/63px-Ambox_current_red_Americas.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/53/Ambox_current_red_Americas.svg/84px-Ambox_current_red_Americas.svg.png 2x" data-file-width="360" data-file-height="290" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section needs to be <b>updated</b>. The reason given is: Advances in DDR5 need to be included.<span class="hide-when-compact"> Please help update this article to reflect recent events or newly available information.</span> <span class="date-container"><i>(<span class="date">December 2023</span>)</i></span></div></td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="SDRAM">SDRAM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=34" title="Edit section: SDRAM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align:center"> <caption>Synchronous dynamic random-access memory (SDRAM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>)<sup id="cite_ref-binpre_6-7" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </th> <th>SDRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th data-sort-type="number">Area </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td>1992 </td> <td>KM48SL2000 </td> <td>16 <a href="/wiki/Megabit" class="mw-redirect" title="Megabit">Mbit</a> </td> <td><a href="/wiki/SDR_SDRAM" class="mw-redirect" title="SDR SDRAM">SDR</a> </td> <td><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> </td> <td><i><b>?</b></i> </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-KM48SL2000_41-0" class="reference"><a href="#cite_note-KM48SL2000-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-electronic-design_5-1" class="reference"><a href="#cite_note-electronic-design-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="3">1996 </td> <td>MSM5718C50 </td> <td>18 Mbit </td> <td><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a> </td> <td><a href="/wiki/Oki_Electric_Industry" title="Oki Electric Industry">Oki</a> </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>325 mm<sup>2</sup> </td> <td><sup id="cite_ref-oki-rdram_42-0" class="reference"><a href="#cite_note-oki-rdram-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><a href="/wiki/Nintendo_64_technical_specifications" class="mw-redirect" title="Nintendo 64 technical specifications">N64 RDRAM</a> </td> <td>36 Mbit </td> <td>RDRAM </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><i><b>?</b></i> </td> <td>1024 Mbit </td> <td>SDR </td> <td><a href="/wiki/Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a> </td> <td><a href="/wiki/180_nanometer" class="mw-redirect" title="180 nanometer">150 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-stol_44-0" class="reference"><a href="#cite_note-stol-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1997 </td> <td><i><b>?</b></i> </td> <td>1024 Mbit </td> <td>SDR </td> <td><a href="/wiki/Hyundai_Electronics" class="mw-redirect" title="Hyundai Electronics">Hyundai</a> </td> <td><i><b>?</b></i> </td> <td><a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a> </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix90s_45-0" class="reference"><a href="#cite_note-hynix90s-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1998 </td> <td>MD5764802 </td> <td>64 Mbit </td> <td>RDRAM </td> <td>Oki </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>325 mm<sup>2</sup> </td> <td><sup id="cite_ref-oki-rdram_42-1" class="reference"><a href="#cite_note-oki-rdram-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="1998 !">March 1998</span> </td> <td>Direct RDRAM </td> <td>72 Mbit </td> <td>RDRAM </td> <td><a href="/wiki/Rambus" title="Rambus">Rambus</a> </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="1998 !">June 1998</span> </td> <td><i><b>?</b></i> </td> <td>64 Mbit </td> <td><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR</a> </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung98_38-1" class="reference"><a href="#cite_note-samsung98-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-samsung99_47-0" class="reference"><a href="#cite_note-samsung99-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-phys_48-0" class="reference"><a href="#cite_note-phys-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">1998 </td> <td rowspan="2"><i><b>?</b></i> </td> <td>64 Mbit </td> <td>DDR </td> <td>Hyundai </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix90s_45-1" class="reference"><a href="#cite_note-hynix90s-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>128 Mbit </td> <td>SDR </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung-history_49-0" class="reference"><a href="#cite_note-samsung-history-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-samsung99_47-1" class="reference"><a href="#cite_note-samsung99-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">1999 </td> <td rowspan="2"><i><b>?</b></i> </td> <td>128 Mbit </td> <td>DDR </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung99_47-2" class="reference"><a href="#cite_note-samsung99-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1024 Mbit </td> <td>DDR </td> <td>Samsung </td> <td><a href="/wiki/130_nanometer" class="mw-redirect" title="130 nanometer">140 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-stol_44-1" class="reference"><a href="#cite_note-stol-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2000 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">GS eDRAM</a> </td> <td>32 Mbit </td> <td><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a> </td> <td><a href="/wiki/Sony" title="Sony">Sony</a>, <a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> </td> <td><a href="/wiki/180_nm" class="mw-redirect" title="180 nm">180 nm</a> </td> <td>CMOS </td> <td>279 mm<sup>2</sup> </td> <td><sup id="cite_ref-sony2003_50-0" class="reference"><a href="#cite_note-sony2003-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">2001 </td> <td rowspan="2"><i><b>?</b></i> </td> <td>288 Mbit </td> <td>RDRAM </td> <td>Hynix </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2000s_51-0" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><i><b>?</b></i> </td> <td><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a> </td> <td>Samsung </td> <td><a href="/wiki/100_nm" class="mw-redirect" title="100 nm">100 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-phys_48-1" class="reference"><a href="#cite_note-phys-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-stol_44-2" class="reference"><a href="#cite_note-stol-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2002 </td> <td><i><b>?</b></i> </td> <td>256 Mbit </td> <td>SDR </td> <td>Hynix </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2000s_51-1" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="5">2003 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">EE+GS eDRAM</a> </td> <td>32 Mbit </td> <td>eDRAM </td> <td>Sony, Toshiba </td> <td><a href="/wiki/90_nm" class="mw-redirect" title="90 nm">90 nm</a> </td> <td>CMOS </td> <td>86 mm<sup>2</sup> </td> <td><sup id="cite_ref-sony2003_50-1" class="reference"><a href="#cite_note-sony2003-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="4"><i><b>?</b></i> </td> <td>72 Mbit </td> <td><a href="/wiki/DDR3" class="mw-redirect" title="DDR3">DDR3</a> </td> <td>Samsung </td> <td>90 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">512 Mbit </td> <td rowspan="2">DDR2 </td> <td>Hynix </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2000s_51-2" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><a href="/wiki/Elpida_Memory" class="mw-redirect" title="Elpida Memory">Elpida</a> </td> <td><a href="/wiki/110_nanometer" class="mw-redirect" title="110 nanometer">110 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1024 Mbit </td> <td>DDR2 </td> <td>Hynix </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2000s_51-3" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2004 </td> <td><i><b>?</b></i> </td> <td>2048 Mbit </td> <td>DDR2 </td> <td>Samsung </td> <td>80 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung2004_54-0" class="reference"><a href="#cite_note-samsung2004-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="3">2005 </td> <td><a href="/wiki/PlayStation_2_technical_specifications" title="PlayStation 2 technical specifications">EE+GS eDRAM</a> </td> <td>32 Mbit </td> <td>eDRAM </td> <td>Sony, Toshiba </td> <td><a href="/wiki/65_nm" class="mw-redirect" title="65 nm">65 nm</a> </td> <td>CMOS </td> <td>86 mm<sup>2</sup> </td> <td><sup id="cite_ref-impress_55-0" class="reference"><a href="#cite_note-impress-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><a href="/wiki/Xenos_(graphics_chip)" title="Xenos (graphics chip)">Xenos eDRAM</a> </td> <td>80 Mbit </td> <td>eDRAM </td> <td>NEC </td> <td>90 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><i><b>?</b></i> </td> <td>512 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>80 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-phys_48-2" class="reference"><a href="#cite_note-phys-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-samsung2000s_57-0" class="reference"><a href="#cite_note-samsung2000s-57"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2006 </td> <td><i><b>?</b></i> </td> <td>1024 Mbit </td> <td>DDR2 </td> <td>Hynix </td> <td>60 nm </td> <td rowspan="2">CMOS </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2"><sup id="cite_ref-hynix2000s_51-4" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2008 </td> <td><i><b>?</b></i> </td> <td><i><b>?</b></i> </td> <td><a href="/wiki/LPDDR2" class="mw-redirect" title="LPDDR2">LPDDR2</a> </td> <td>Hynix </td> <td><i><b>?</b></i> </td></tr> <tr> <td><span data-sort-value="2008 !">April 2008</span> </td> <td><i><b>?</b></i> </td> <td>8192 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>50 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td rowspan="2"><sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2008 </td> <td><i><b>?</b></i> </td> <td>16384 Mbit </td> <td>DDR3 </td> <td>Samsung </td> <td>50 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td></tr> <tr> <td rowspan="2">2009 </td> <td rowspan="2"><i><b>?</b></i> </td> <td><i><b>?</b></i> </td> <td>DDR3 </td> <td>Hynix </td> <td><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">44 nm</a> </td> <td rowspan="2">CMOS </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2"><sup id="cite_ref-hynix2000s_51-5" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2048 Mbit </td> <td>DDR3 </td> <td>Hynix </td> <td><a href="/wiki/40_nanometer" class="mw-redirect" title="40 nanometer">40 nm</a> </td></tr> <tr> <td rowspan="2">2011 </td> <td rowspan="2"><i><b>?</b></i> </td> <td>16384 Mbit </td> <td>DDR3 </td> <td>Hynix </td> <td>40 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2010s_40-1" class="reference"><a href="#cite_note-hynix2010s-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2048 Mbit </td> <td><a href="/wiki/DDR4" class="mw-redirect" title="DDR4">DDR4</a> </td> <td>Hynix </td> <td><a href="/wiki/32_nanometer" class="mw-redirect" title="32 nanometer">30 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2010s_40-2" class="reference"><a href="#cite_note-hynix2010s-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2013 </td> <td><i><b>?</b></i> </td> <td><i><b>?</b></i> </td> <td><a href="/wiki/LPDDR4" class="mw-redirect" title="LPDDR4">LPDDR4</a> </td> <td>Samsung </td> <td><a href="/w/index.php?title=20_nm&action=edit&redlink=1" class="new" title="20 nm (page does not exist)">20 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-hynix2010s_40-3" class="reference"><a href="#cite_note-hynix2010s-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2014 </td> <td><i><b>?</b></i> </td> <td>8192 Mbit </td> <td>LPDDR4 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-59" class="reference"><a href="#cite_note-59"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2015 </td> <td><i><b>?</b></i> </td> <td>12 Gbit </td> <td>LPDDR4 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung-history_49-1" class="reference"><a href="#cite_note-samsung-history-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">2018 </td> <td rowspan="2"><i><b>?</b></i> </td> <td>8192 Mbit </td> <td><a href="/wiki/LPDDR#LP-DDR5" title="LPDDR">LPDDR5</a> </td> <td>Samsung </td> <td><a href="/wiki/10_nm_process" title="10 nm process">10 nm</a> </td> <td><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>128 Gbit </td> <td>DDR4 </td> <td>Samsung </td> <td>10 nm </td> <td>FinFET </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="SGRAM_and_HBM">SGRAM and HBM</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=35" title="Edit section: SGRAM and HBM"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable" style="text-align:center"> <caption><a href="/wiki/Synchronous_graphics_random-access_memory" class="mw-redirect" title="Synchronous graphics random-access memory">Synchronous graphics random-access memory</a> (SGRAM) and <a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">High Bandwidth Memory</a> (HBM) </caption> <tbody><tr> <th>Date of introduction </th> <th>Chip name </th> <th>Capacity (<a href="/wiki/Bit" title="Bit">bits</a>)<sup id="cite_ref-binpre_6-8" class="reference"><a href="#cite_note-binpre-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </th> <th>SDRAM type </th> <th>Manufacturer(s) </th> <th data-sort-type="number"><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Process</a> </th> <th><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> </th> <th data-sort-type="number">Area </th> <th><abbr title="Reference(s)">Ref</abbr> </th></tr> <tr> <td><span data-sort-value="1994 !">November 1994</span> </td> <td>HM5283206 </td> <td>8 Mbit </td> <td><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> (<a href="/wiki/SDR_SDRAM" class="mw-redirect" title="SDR SDRAM">SDR</a>) </td> <td><a href="/wiki/Hitachi" title="Hitachi">Hitachi</a> </td> <td><a href="/wiki/350_nm" class="mw-redirect" title="350 nm">350 nm</a> </td> <td><a href="/wiki/CMOS" title="CMOS">CMOS</a> </td> <td>58 mm<sup>2</sup> </td> <td><sup id="cite_ref-HM5283206_34-1" class="reference"><a href="#cite_note-HM5283206-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="1994 !">December 1994</span> </td> <td>μPD481850 </td> <td>8 Mbit </td> <td>SGRAM (SDR) </td> <td><a href="/wiki/NEC" title="NEC">NEC</a> </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>280 mm<sup>2</sup> </td> <td><sup id="cite_ref-D481850_35-1" class="reference"><a href="#cite_note-D481850-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-nec1995_37-1" class="reference"><a href="#cite_note-nec1995-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1997 </td> <td>μPD4811650 </td> <td>16 Mbit </td> <td>SGRAM (SDR) </td> <td>NEC </td> <td>350 nm </td> <td>CMOS </td> <td>280 mm<sup>2</sup> </td> <td><sup id="cite_ref-63" class="reference"><a href="#cite_note-63"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="1998 !">September 1998</span> </td> <td><i><b>?</b></i> </td> <td>16 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a>) </td> <td><a href="/wiki/Samsung_Electronics" title="Samsung Electronics">Samsung</a> </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung98_38-2" class="reference"><a href="#cite_note-samsung98-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>1999 </td> <td>KM4132G112 </td> <td>32 Mbit </td> <td>SGRAM (SDR) </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>280 mm<sup>2</sup> </td> <td><sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2002 </td> <td><i><b>?</b></i> </td> <td>128 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a>) </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-samsung2003_66-0" class="reference"><a href="#cite_note-samsung2003-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td rowspan="2">2003 </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2">256 Mbit </td> <td>SGRAM (GDDR2) </td> <td rowspan="2">Samsung </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2">CMOS </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2"><sup id="cite_ref-samsung2003_66-1" class="reference"><a href="#cite_note-samsung2003-66"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>SGRAM (<a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>) </td></tr> <tr> <td><span data-sort-value="2005 !">March 2005</span> </td> <td>K4D553238F </td> <td>256 Mbit </td> <td>SGRAM (GDDR) </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>77 mm<sup>2</sup> </td> <td><sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="2005 !">October 2005</span> </td> <td><i><b>?</b></i> </td> <td>256 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>) </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2005 </td> <td><i><b>?</b></i> </td> <td>512 Mbit </td> <td>SGRAM (GDDR4) </td> <td><a href="/wiki/Hynix" class="mw-redirect" title="Hynix">Hynix</a> </td> <td><i><b>?</b></i> </td> <td rowspan="3">CMOS </td> <td rowspan="3"><i><b>?</b></i> </td> <td rowspan="3"><sup id="cite_ref-hynix2000s_51-6" class="reference"><a href="#cite_note-hynix2000s-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2007 </td> <td><i><b>?</b></i> </td> <td>1024 Mbit </td> <td>SGRAM (<a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>) </td> <td>Hynix </td> <td><a href="/wiki/65_nanometer" class="mw-redirect" title="65 nanometer">60 nm</a> </td></tr> <tr> <td>2009 </td> <td><i><b>?</b></i> </td> <td>2048 Mbit </td> <td>SGRAM (GDDR5) </td> <td>Hynix </td> <td><a href="/wiki/45_nanometer" class="mw-redirect" title="45 nanometer">40 nm</a> </td></tr> <tr> <td>2010 </td> <td>K4W1G1646G </td> <td>1024 Mbit </td> <td>SGRAM (GDDR3) </td> <td>Samsung </td> <td><i><b>?</b></i> </td> <td>CMOS </td> <td>100 mm<sup>2</sup> </td> <td><sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2012 </td> <td><i><b>?</b></i> </td> <td>4096 Mbit </td> <td>SGRAM (GDDR3) </td> <td rowspan="2"><a href="/wiki/SK_Hynix" title="SK Hynix">SK Hynix</a> </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2">CMOS </td> <td rowspan="2"><i><b>?</b></i> </td> <td rowspan="2"><sup id="cite_ref-hynix2010s_40-4" class="reference"><a href="#cite_note-hynix2010s-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2013 </td> <td><i><b>?</b></i> </td> <td><i><b>?</b></i> </td> <td><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> </td></tr> <tr> <td><span data-sort-value="2016 !">March 2016</span> </td> <td>MT58K256M32JA </td> <td>8 Gbit </td> <td>SGRAM (<a href="/wiki/GDDR5X" class="mw-redirect" title="GDDR5X">GDDR5X</a>) </td> <td><a href="/wiki/Micron_Technology" title="Micron Technology">Micron</a> </td> <td>20 nm </td> <td>CMOS </td> <td>140 mm<sup>2</sup> </td> <td><sup id="cite_ref-70" class="reference"><a href="#cite_note-70"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="2016 !">June 2016</span> </td> <td><i><b>?</b></i> </td> <td>32 Gbit </td> <td><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a> </td> <td>Samsung </td> <td><a href="/w/index.php?title=20_nm&action=edit&redlink=1" class="new" title="20 nm (page does not exist)">20 nm</a> </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-Shilov2017_71-0" class="reference"><a href="#cite_note-Shilov2017-71"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td>2017 </td> <td><i><b>?</b></i> </td> <td>64 Gbit </td> <td>HBM2 </td> <td>Samsung </td> <td>20 nm </td> <td>CMOS </td> <td><i><b>?</b></i> </td> <td><sup id="cite_ref-Shilov2017_71-1" class="reference"><a href="#cite_note-Shilov2017-71"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span data-sort-value="2018 !">January 2018</span> </td> <td>K4ZAF325BM </td> <td>16 Gbit </td> <td>SGRAM (<a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a>) </td> <td>Samsung </td> <td><a href="/wiki/10_nm_process" title="10 nm process">10 nm</a> </td> <td><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> </td> <td>225 mm<sup>2</sup> </td> <td><sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-tr_gddr6_74-0" class="reference"><a href="#cite_note-tr_gddr6-74"><span class="cite-bracket">[</span>74<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-75" class="reference"><a href="#cite_note-75"><span class="cite-bracket">[</span>75<span class="cite-bracket">]</span></a></sup> </td></tr></tbody></table> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=36" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/GDDR" class="mw-redirect" title="GDDR">GDDR</a> (graphics DDR) and its subtypes <a href="/wiki/GDDR2" class="mw-redirect" title="GDDR2">GDDR2</a>, <a href="/wiki/GDDR3" class="mw-redirect" title="GDDR3">GDDR3</a>, <a href="/wiki/GDDR4" class="mw-redirect" title="GDDR4">GDDR4</a>, <a href="/wiki/GDDR5" class="mw-redirect" title="GDDR5">GDDR5</a>, <a href="/wiki/GDDR6" class="mw-redirect" title="GDDR6">GDDR6</a> and <a href="/wiki/GDDR7" class="mw-redirect" title="GDDR7">GDDR7</a></li> <li><a href="/wiki/List_of_device_bandwidths" class="mw-redirect" title="List of device bandwidths">List of device bandwidths</a></li> <li><a href="/wiki/Serial_presence_detect" title="Serial presence detect">Serial presence detect</a> - EEPROM with timing data on SDRAM modules</li> <li><a rel="nofollow" class="external text" href="http://taututorial.yolasite.com/">SDRAM Tutorial</a> - Flash website built by Tel-Aviv University students</li> <li>A concise but thorough review of SDRAM architecture/terminology and command timing dependencies in <a rel="nofollow" class="external text" href="http://drum.lib.umd.edu/bitstream/1903/11269/1/Gross_umd_0117N_11844.pdf">High-Performance DRAM System Design Constraints and Considerations</a>, a master thesis from the University of Maryland.</li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=37" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFP._Darche2020" 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Retrieved <span class="nowrap">16 July</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=Wccftech&rft.atitle=Samsung+Begins+Producing+The+Fastest+GDDR6+Memory+In+The+World&rft.date=2018-01-18&rft_id=https%3A%2F%2Fwccftech.com%2Fsamsung-gddr6-16gb-18gbps-mass-production-official%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ASynchronous+dynamic+random-access+memory" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Synchronous_dynamic_random-access_memory&action=edit&section=38" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.anandtech.com/show/3851/">Everything you always wanted to know about SDRAM (memory), but were afraid to ask</a>, August 2010, <a href="/wiki/AnandTech" title="AnandTech">AnandTech</a></li> <li><a rel="nofollow" class="external text" href="http://www.hardwaresecrets.com/understanding-ram-timings/">Understanding RAM Timings</a>, May 2011, Hardware Secrets</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030803094457/http://developer.intel.com/technology/memory/pc133sdram/spec/sdram133.pdf">PC SDRAM Specification, Rev 1.7</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030429115837/http://developer.intel.com/technology/memory/pc133sdram/spec/PC133sodm1_0c1.pdf">133 MHz PC133 SDRAM SO-DIMM Specification</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20030803113813/http://developer.intel.com/technology/memory/pc133sdram/spec/Spdsd12b.pdf">PC SDRAM Serial Presence Detect (SPD) Specification, Rev 1.2B</a></li></ul> <div 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.navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Dynamic_random-access_memory_(DRAM)" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:DRAM" title="Template:DRAM"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:DRAM" title="Template talk:DRAM"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:DRAM" title="Special:EditPage/Template:DRAM"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Dynamic_random-access_memory_(DRAM)" style="font-size:114%;margin:0 4em"><a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">Dynamic random-access memory</a> (DRAM)</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Asynchronous</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/FPM_DRAM" class="mw-redirect" title="FPM DRAM">FPM DRAM</a></li> <li><a href="/wiki/EDO_DRAM" class="mw-redirect" title="EDO DRAM">EDO DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a class="mw-selflink selflink">Synchronous</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">SDRAM</a></li> <li><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> <ul><li><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2</a></li> <li><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3</a></li> <li><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4</a></li> <li><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5</a></li></ul></li> <li><a href="/wiki/LPDDR" title="LPDDR">LPDDR</a> (Mobile DDR)</li> <li><a href="/wiki/Fast_Cycle_DRAM" title="Fast Cycle DRAM">Fast Cycle DRAM</a> (FCRAM)</li> <li><a href="/wiki/EDRAM" title="EDRAM">eDRAM</a></li> <li><a href="/wiki/RLDRAM" title="RLDRAM">RLDRAM</a></li> <li><a href="/wiki/High_Bandwidth_Memory" title="High Bandwidth Memory">HBM</a> <ul><li><a href="/wiki/HBM2" class="mw-redirect" title="HBM2">HBM2</a></li> <li><a href="/wiki/HBM2E" class="mw-redirect" title="HBM2E">HBM2E</a></li> <li><a href="/wiki/HBM3" class="mw-redirect" title="HBM3">HBM3</a></li> <li><a href="/wiki/HBM-PIM" class="mw-redirect" title="HBM-PIM">HBM-PIM</a></li> <li><a href="/wiki/HBM3E" class="mw-redirect" title="HBM3E">HBM3E</a></li></ul></li> <li><a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Graphics</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Video_RAM_(dual-ported_DRAM)" class="mw-redirect" title="Video RAM (dual-ported DRAM)">VRAM</a></li> <li><a href="/wiki/WRAM_(memory)" class="mw-redirect" title="WRAM (memory)">WRAM</a></li> <li><a href="/wiki/MDRAM" class="mw-redirect" title="MDRAM">MDRAM</a></li> <li><a href="/wiki/SGRAM" class="mw-redirect" title="SGRAM">SGRAM</a> <ul><li><a href="/wiki/GDDR_SDRAM" title="GDDR SDRAM">GDDR</a></li> <li><a href="/wiki/GDDR2_SDRAM" class="mw-redirect" title="GDDR2 SDRAM">GDDR2</a></li> <li><a href="/wiki/GDDR3_SDRAM" title="GDDR3 SDRAM">GDDR3</a></li> <li><a href="/wiki/GDDR4_SDRAM" title="GDDR4 SDRAM">GDDR4</a></li> <li><a href="/wiki/GDDR5_SDRAM" title="GDDR5 SDRAM">GDDR5</a></li> <li><a href="/wiki/GDDR6_SDRAM" title="GDDR6 SDRAM">GDDR6</a></li> <li><a href="/wiki/GDDR7_SDRAM" title="GDDR7 SDRAM">GDDR7</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Rambus" title="Rambus">Rambus</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/RDRAM" title="RDRAM">RDRAM</a></li> <li><a href="/wiki/XDR_DRAM" title="XDR DRAM">XDR DRAM</a></li> <li><a href="/wiki/XDR2_DRAM" title="XDR2 DRAM">XDR2 DRAM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Memory_module" title="Memory module">Memory modules</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/SIMM" title="SIMM">SIMM</a></li> <li><a href="/wiki/DIMM" title="DIMM">DIMM</a></li> <li><a href="/wiki/UniDIMM" title="UniDIMM">UniDIMM</a></li> <li><a href="/wiki/CAMM_(memory_module)" title="CAMM (memory module)">CAMM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Random-access_memory#DRAM" title="Random-access memory">DRAM timeline</a></li> <li><a class="mw-selflink-fragment" href="#Timeline">SDRAM timeline</a></li> <li><a href="/wiki/List_of_interface_bit_rates#Dynamic_random-access_memory" title="List of interface bit rates">Bandwidth</a></li> <li><a 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