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is-link">Go</button> </div> </div> </form> </div> </div> <nav class="pagination is-small is-centered breathe-horizontal" role="navigation" aria-label="pagination"> <a href="" class="pagination-previous is-invisible">Previous </a> <a href="/search/?searchtype=author&query=Ni%2C+K&start=50" class="pagination-next" >Next </a> <ul class="pagination-list"> <li> <a href="/search/?searchtype=author&query=Ni%2C+K&start=0" class="pagination-link is-current" aria-label="Goto page 1">1 </a> </li> <li> <a href="/search/?searchtype=author&query=Ni%2C+K&start=50" class="pagination-link " aria-label="Page 2" aria-current="page">2 </a> </li> </ul> </nav> <ol class="breathe-horizontal" start="1"> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2411.08244">arXiv:2411.08244</a> <span> [<a href="https://arxiv.org/pdf/2411.08244">pdf</a>, <a href="https://arxiv.org/format/2411.08244">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> NVCiM-PT: An NVCiM-assisted Prompt Tuning Framework for Edge LLMs </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Qin%2C+R">Ruiyang Qin</a>, <a href="/search/cs?searchtype=author&query=Ren%2C+P">Pengyu Ren</a>, <a href="/search/cs?searchtype=author&query=Yan%2C+Z">Zheyu Yan</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+L">Liu Liu</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+D">Dancheng Liu</a>, <a href="/search/cs?searchtype=author&query=Nassereldine%2C+A">Amir Nassereldine</a>, <a href="/search/cs?searchtype=author&query=Xiong%2C+J">Jinjun Xiong</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+S">Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Y">Yiyu Shi</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2411.08244v1-abstract-short" style="display: inline;"> Large Language Models (LLMs) deployed on edge devices, known as edge LLMs, need to continuously fine-tune their model parameters from user-generated data under limited resource constraints. However, most existing learning methods are not applicable for edge LLMs because of their reliance on high resources and low learning capacity. Prompt tuning (PT) has recently emerged as an effective fine-tunin… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2411.08244v1-abstract-full').style.display = 'inline'; document.getElementById('2411.08244v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2411.08244v1-abstract-full" style="display: none;"> Large Language Models (LLMs) deployed on edge devices, known as edge LLMs, need to continuously fine-tune their model parameters from user-generated data under limited resource constraints. However, most existing learning methods are not applicable for edge LLMs because of their reliance on high resources and low learning capacity. Prompt tuning (PT) has recently emerged as an effective fine-tuning method for edge LLMs by only modifying a small portion of LLM parameters, but it suffers from user domain shifts, resulting in repetitive training and losing resource efficiency. Conventional techniques to address domain shift issues often involve complex neural networks and sophisticated training, which are incompatible for PT for edge LLMs. Therefore, an open research question is how to address domain shift issues for edge LLMs with limited resources. In this paper, we propose a prompt tuning framework for edge LLMs, exploiting the benefits offered by non-volatile computing-in-memory (NVCiM) architectures. We introduce a novel NVCiM-assisted PT framework, where we narrow down the core operations to matrix-matrix multiplication, which can then be accelerated by performing in-situ computation on NVCiM. To the best of our knowledge, this is the first work employing NVCiM to improve the edge LLM PT performance. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2411.08244v1-abstract-full').style.display = 'none'; document.getElementById('2411.08244v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 12 November, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted by DATE 2025</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2410.19593">arXiv:2410.19593</a> <span> [<a href="https://arxiv.org/pdf/2410.19593">pdf</a>, <a href="https://arxiv.org/format/2410.19593">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Energy Efficient Dual Designs of FeFET-Based Analog In-Memory Computing with Inherent Shift-Add Capability </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yang%2C+Z">Zeyu Yang</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Q">Qingrong Huang</a>, <a href="/search/cs?searchtype=author&query=Qian%2C+Y">Yu Qian</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2410.19593v1-abstract-short" style="display: inline;"> In-memory computing (IMC) architecture emerges as a promising paradigm, improving the energy efficiency of multiply-and-accumulate (MAC) operations within DNNs by integrating the parallel computations within the memory arrays. Various high-precision analog IMC array designs have been developed based on both SRAM and emerging non-volatile memories. These designs perform MAC operations of partial in… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.19593v1-abstract-full').style.display = 'inline'; document.getElementById('2410.19593v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2410.19593v1-abstract-full" style="display: none;"> In-memory computing (IMC) architecture emerges as a promising paradigm, improving the energy efficiency of multiply-and-accumulate (MAC) operations within DNNs by integrating the parallel computations within the memory arrays. Various high-precision analog IMC array designs have been developed based on both SRAM and emerging non-volatile memories. These designs perform MAC operations of partial input and weight, with the corresponding partial products then fed into shift-add circuitry to produce the final MAC results. However, existing works often present intricate shift-add process for weight. The traditional digital shift-add process is limited in throughput due to time-multiplexing of ADCs, and advancing the shift-add process to the analog domain necessitates customized circuit implementations, resulting in compromises in energy and area efficiency. Furthermore, the joint optimization of the partial MAC operations and the weight shift-add process is rarely explored. In this paper, we propose novel, energy efficient dual designs of FeFET based high precision analog IMC featuring inherent shift-add capability. We introduce a FeFET based IMC paradigm that performs partial MAC in each column, and inherently integrates the shift-add process for 4-bit weights by leveraging FeFET's analog storage characteristics. This paradigm supports both 2's complement mode and non-2's complement mode MAC, thereby offering flexible support for 4-/8-bit weight data in 2's complement format. Building upon this paradigm, we propose novel FeFET based dual designs, CurFe for the current mode and ChgFe for the charge mode, to accommodate the high precision analog domain IMC architecture.Evaluation results at circuit and system levels indicate that the circuit/system-level energy efficiency of the proposed FeFET-based analog IMC is 1.56$\times$/1.37$\times$ higher when compared to SOTA analog IMC designs. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.19593v1-abstract-full').style.display = 'none'; document.getElementById('2410.19593v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2410.19356">arXiv:2410.19356</a> <span> [<a href="https://arxiv.org/pdf/2410.19356">pdf</a>, <a href="https://arxiv.org/format/2410.19356">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1145/3649329.3656538">10.1145/3649329.3656538 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> FeBiM: Efficient and Compact Bayesian Inference Engine Empowered with Ferroelectric In-Memory Computing </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Li%2C+C">Chao Li</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+Z">Zhicheng Xu</a>, <a href="/search/cs?searchtype=author&query=Wen%2C+B">Bo Wen</a>, <a href="/search/cs?searchtype=author&query=Mao%2C+R">Ruibin Mao</a>, <a href="/search/cs?searchtype=author&query=Li%2C+C">Can Li</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2410.19356v1-abstract-short" style="display: inline;"> In scenarios with limited training data or where explainability is crucial, conventional neural network-based machine learning models often face challenges. In contrast, Bayesian inference-based algorithms excel in providing interpretable predictions and reliable uncertainty estimation in these scenarios. While many state-of-the-art in-memory computing (IMC) architectures leverage emerging non-vol… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.19356v1-abstract-full').style.display = 'inline'; document.getElementById('2410.19356v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2410.19356v1-abstract-full" style="display: none;"> In scenarios with limited training data or where explainability is crucial, conventional neural network-based machine learning models often face challenges. In contrast, Bayesian inference-based algorithms excel in providing interpretable predictions and reliable uncertainty estimation in these scenarios. While many state-of-the-art in-memory computing (IMC) architectures leverage emerging non-volatile memory (NVM) technologies to offer unparalleled computing capacity and energy efficiency for neural network workloads, their application in Bayesian inference is limited. This is because the core operations in Bayesian inference differ significantly from the multiplication-accumulation (MAC) operations common in neural networks, rendering them generally unsuitable for direct implementation in most existing IMC designs. In this paper, we propose FeBiM, an efficient and compact Bayesian inference engine powered by multi-bit ferroelectric field-effect transistor (FeFET)-based IMC. FeBiM effectively encodes the trained probabilities of a Bayesian inference model within a compact FeFET-based crossbar. It maps quantized logarithmic probabilities to discrete FeFET states. As a result, the accumulated outputs of the crossbar naturally represent the posterior probabilities, i.e., the Bayesian inference model's output given a set of observations. This approach enables efficient in-memory Bayesian inference without the need for additional calculation circuitry. As the first FeFET-based in-memory Bayesian inference engine, FeBiM achieves an impressive storage density of 26.32 Mb/mm$^{2}$ and a computing efficiency of 581.40 TOPS/W in a representative Bayesian classification task. These results demonstrate 10.7$\times$/43.4$\times$ improvement in compactness/efficiency compared to the state-of-the-art hardware implementation of Bayesian inference. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.19356v1-abstract-full').style.display = 'none'; document.getElementById('2410.19356v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">6 pages, 8 figures, to be published in the 61st DAC (Design Automation Conference) proceedings</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2410.15296">arXiv:2410.15296</a> <span> [<a href="https://arxiv.org/pdf/2410.15296">pdf</a>, <a href="https://arxiv.org/format/2410.15296">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Neural and Evolutionary Computing">cs.NE</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Symbolic Computation">cs.SC</span> </div> </div> <p class="title is-5 mathjax"> A Remedy to Compute-in-Memory with Dynamic Random Access Memory: 1FeFET-1C Technology for Neuro-Symbolic AI </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=Barkam%2C+H+E">Hamza Errahmouni Barkam</a>, <a href="/search/cs?searchtype=author&query=M%C3%BCller%2C+F">Franz M眉ller</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Y">Yuxiao Jiang</a>, <a href="/search/cs?searchtype=author&query=Imani%2C+M">Mohsen Imani</a>, <a href="/search/cs?searchtype=author&query=Abdulazhanov%2C+S">Sukhrob Abdulazhanov</a>, <a href="/search/cs?searchtype=author&query=Vardar%2C+A">Alptekin Vardar</a>, <a href="/search/cs?searchtype=author&query=Laleni%2C+N">Nellie Laleni</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Duan%2C+J">Jiahui Duan</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Z">Zhiguo Shi</a>, <a href="/search/cs?searchtype=author&query=Joshi%2C+S">Siddharth Joshi</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">Xiaobo Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2410.15296v1-abstract-short" style="display: inline;"> Neuro-symbolic artificial intelligence (AI) excels at learning from noisy and generalized patterns, conducting logical inferences, and providing interpretable reasoning. Comprising a 'neuro' component for feature extraction and a 'symbolic' component for decision-making, neuro-symbolic AI has yet to fully benefit from efficient hardware accelerators. Additionally, current hardware struggles to acc… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.15296v1-abstract-full').style.display = 'inline'; document.getElementById('2410.15296v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2410.15296v1-abstract-full" style="display: none;"> Neuro-symbolic artificial intelligence (AI) excels at learning from noisy and generalized patterns, conducting logical inferences, and providing interpretable reasoning. Comprising a 'neuro' component for feature extraction and a 'symbolic' component for decision-making, neuro-symbolic AI has yet to fully benefit from efficient hardware accelerators. Additionally, current hardware struggles to accommodate applications requiring dynamic resource allocation between these two components. To address these challenges-and mitigate the typical data-transfer bottleneck of classical Von Neumann architectures-we propose a ferroelectric charge-domain compute-in-memory (CiM) array as the foundational processing element for neuro-symbolic AI. This array seamlessly handles both the critical multiply-accumulate (MAC) operations of the 'neuro' workload and the parallel associative search operations of the 'symbolic' workload. To enable this approach, we introduce an innovative 1FeFET-1C cell, combining a ferroelectric field-effect transistor (FeFET) with a capacitor. This design, overcomes the destructive sensing limitations of DRAM in CiM applications, while capable of capitalizing decades of DRAM expertise with a similar cell structure as DRAM, achieves high immunity against FeFET variation-crucial for neuro-symbolic AI-and demonstrates superior energy efficiency. The functionalities of our design have been successfully validated through SPICE simulations and prototype fabrication and testing. Our hardware platform has been benchmarked in executing typical neuro-symbolic AI reasoning tasks, showing over 2x improvement in latency and 1000x improvement in energy efficiency compared to GPU-based implementations. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.15296v1-abstract-full').style.display = 'none'; document.getElementById('2410.15296v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 20 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2410.14111">arXiv:2410.14111</a> <span> [<a href="https://arxiv.org/pdf/2410.14111">pdf</a>, <a href="https://arxiv.org/format/2410.14111">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> HyCiM: A Hybrid Computing-in-Memory QUBO Solver for General Combinatorial Optimization Problems with Inequality Constraints </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Qian%2C+Y">Yu Qian</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+Z">Zeyu Yang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Vardar%2C+A">Alptekin Vardar</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2410.14111v1-abstract-short" style="display: inline;"> Computationally challenging combinatorial optimization problems (COPs) play a fundamental role in various applications. To tackle COPs, many Ising machines and Quadratic Unconstrained Binary Optimization (QUBO) solvers have been proposed, which typically involve direct transformation of COPs into Ising models or equivalent QUBO forms (D-QUBO). However, when addressing COPs with inequality constrai… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.14111v1-abstract-full').style.display = 'inline'; document.getElementById('2410.14111v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2410.14111v1-abstract-full" style="display: none;"> Computationally challenging combinatorial optimization problems (COPs) play a fundamental role in various applications. To tackle COPs, many Ising machines and Quadratic Unconstrained Binary Optimization (QUBO) solvers have been proposed, which typically involve direct transformation of COPs into Ising models or equivalent QUBO forms (D-QUBO). However, when addressing COPs with inequality constraints, this D-QUBO approach introduces numerous extra auxiliary variables, resulting in a substantially larger search space, increased hardware costs, and reduced solving efficiency. In this work, we propose HyCiM, a novel hybrid computing-in-memory (CiM) based QUBO solver framework, designed to overcome aforementioned challenges. The proposed framework consists of (i) an innovative transformation method (first to our known) that converts COPs with inequality constraints into an inequality-QUBO form, thus eliminating the need of expensive auxiliary variables and associated calculations; (ii) "inequality filter", a ferroelectric FET (FeFET)-based CiM circuit that accelerates the inequality evaluation, and filters out infeasible input configurations; (iii) %When feasible solutions are detected, a FeFET-based CiM annealer that is capable of approaching global solutions of COPs via iterative QUBO computations within a simulated annealing process. The evaluation results show that HyCiM drastically narrows down the search space, eliminating $2^{100} \text{ to } 2^{2536}$ infeasible input configurations compared to the conventional D-QUBO approach. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.14111v1-abstract-full').style.display = 'none'; document.getElementById('2410.14111v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2410.11091">arXiv:2410.11091</a> <span> [<a href="https://arxiv.org/pdf/2410.11091">pdf</a>, <a href="https://arxiv.org/format/2410.11091">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Applied Physics">physics.app-ph</span> </div> </div> <p class="title is-5 mathjax"> Energy-Efficient Cryogenic Ternary Content Addressable Memory using Ferroelectric SQUID </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Alam%2C+S">Shamiul Alam</a>, <a href="/search/cs?searchtype=author&query=Thomann%2C+S">Simon Thomann</a>, <a href="/search/cs?searchtype=author&query=Parihar%2C+S+S">Shivendra Singh Parihar</a>, <a href="/search/cs?searchtype=author&query=Chauhan%2C+Y+S">Yogesh Singh Chauhan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Amrouch%2C+H">Hussam Amrouch</a>, <a href="/search/cs?searchtype=author&query=Aziz%2C+A">Ahmedullah Aziz</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2410.11091v1-abstract-short" style="display: inline;"> Ternary content addressable memories (TCAMs) are useful for certain computing tasks since they allow us to compare a search query with a whole dataset stored in the memory array. They can also unlock unique advantages for cryogenic applications like quantum computing, high-performance computing, and space exploration by improving speed and energy efficiency through parallel searching. This paper e… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.11091v1-abstract-full').style.display = 'inline'; document.getElementById('2410.11091v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2410.11091v1-abstract-full" style="display: none;"> Ternary content addressable memories (TCAMs) are useful for certain computing tasks since they allow us to compare a search query with a whole dataset stored in the memory array. They can also unlock unique advantages for cryogenic applications like quantum computing, high-performance computing, and space exploration by improving speed and energy efficiency through parallel searching. This paper explores the design and implementation of a cryogenic ternary content addressable memory based on ferroelectric superconducting quantum interference devices (FeSQUIDs). The use of FeSQUID for designing the TCAM provides several unique advantages. First, we can get binary decisions (zero or non-zero voltage) for matching and mismatching conditions without using any peripheral circuitry. Moreover, the proposed TCAM needs ultra-low energy (1.36 aJ and 26.5 aJ average energy consumption for 1-bit binary and ternary search, respectively), thanks to the use of energy-efficient SQUIDs. Finally, we show the efficiency of FeSQUID through the brain-inspired application of Hyperdimensional Computing (HDC). Here, the FeSQUID-based TCAM implements the associative memory to support the highly parallel search needed in the inference step. We estimate an energy consumption of 89.4 fJ per vector comparison using a vector size of 10,000 bits. We also compare the FeSQUID-based TCAM array with the 5nm FinFET-based cryogenic SRAM-based TCAM array and observe that the proposed FeSQUID-based TCAM array consumes over one order of magnitude lower energy while performing the same task. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2410.11091v1-abstract-full').style.display = 'none'; document.getElementById('2410.11091v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 14 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">6 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2409.19835">arXiv:2409.19835</a> <span> [<a href="https://arxiv.org/pdf/2409.19835">pdf</a>, <a href="https://arxiv.org/format/2409.19835">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Image and Video Processing">eess.IV</span> </div> </div> <p class="title is-5 mathjax"> GrokLST: Towards High-Resolution Benchmark and Toolkit for Land Surface Temperature Downscaling </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Dai%2C+Q">Qun Dai</a>, <a href="/search/cs?searchtype=author&query=Yuan%2C+C">Chunyang Yuan</a>, <a href="/search/cs?searchtype=author&query=Dai%2C+Y">Yimian Dai</a>, <a href="/search/cs?searchtype=author&query=Li%2C+Y">Yuxuan Li</a>, <a href="/search/cs?searchtype=author&query=Li%2C+X">Xiang Li</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kang Ni</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+J">Jianhui Xu</a>, <a href="/search/cs?searchtype=author&query=Shu%2C+X">Xiangbo Shu</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+J">Jian Yang</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2409.19835v1-abstract-short" style="display: inline;"> Land Surface Temperature (LST) is a critical parameter for environmental studies, but obtaining high-resolution LST data remains challenging due to the spatio-temporal trade-off in satellite remote sensing. Guided LST downscaling has emerged as a solution, but current methods often neglect spatial non-stationarity and lack a open-source ecosystem for deep learning methods. To address these limitat… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.19835v1-abstract-full').style.display = 'inline'; document.getElementById('2409.19835v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2409.19835v1-abstract-full" style="display: none;"> Land Surface Temperature (LST) is a critical parameter for environmental studies, but obtaining high-resolution LST data remains challenging due to the spatio-temporal trade-off in satellite remote sensing. Guided LST downscaling has emerged as a solution, but current methods often neglect spatial non-stationarity and lack a open-source ecosystem for deep learning methods. To address these limitations, we propose the Modality-Conditional Large Selective Kernel (MoCoLSK) Networks, a novel architecture that dynamically fuses multi-modal data through modality-conditioned projections. MoCoLSK re-engineers our previous LSKNet to achieve a confluence of dynamic receptive field adjustment and multi-modal feature integration, leading to enhanced LST prediction accuracy. Furthermore, we establish the GrokLST project, a comprehensive open-source ecosystem featuring the GrokLST dataset, a high-resolution benchmark, and the GrokLST toolkit, an open-source PyTorch-based toolkit encapsulating MoCoLSK alongside 40+ state-of-the-art approaches. Extensive experimental results validate MoCoLSK's effectiveness in capturing complex dependencies and subtle variations within multispectral data, outperforming existing methods in LST downscaling. Our code, dataset, and toolkit are available at https://github.com/GrokCV/GrokLST. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.19835v1-abstract-full').style.display = 'none'; document.getElementById('2409.19835v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 29 September, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2409.03140">arXiv:2409.03140</a> <span> [<a href="https://arxiv.org/pdf/2409.03140">pdf</a>, <a href="https://arxiv.org/format/2409.03140">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Information Retrieval">cs.IR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> </div> </div> <p class="title is-5 mathjax"> GraphEx: A Graph-based Extraction Method for Advertiser Keyphrase Recommendation </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Mishra%2C+A">Ashirbad Mishra</a>, <a href="/search/cs?searchtype=author&query=Dey%2C+S">Soumik Dey</a>, <a href="/search/cs?searchtype=author&query=Wu%2C+M">Marshall Wu</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+J">Jinyu Zhao</a>, <a href="/search/cs?searchtype=author&query=Yu%2C+H">He Yu</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kaichen Ni</a>, <a href="/search/cs?searchtype=author&query=Li%2C+B">Binbin Li</a>, <a href="/search/cs?searchtype=author&query=Madduri%2C+K">Kamesh Madduri</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2409.03140v2-abstract-short" style="display: inline;"> Online sellers and advertisers are recommended keyphrases for their listed products, which they bid on to enhance their sales. One popular paradigm that generates such recommendations is Extreme Multi-Label Classification (XMC), which involves tagging/mapping keyphrases to items. We outline the limitations of using traditional item-query based tagging or mapping techniques for keyphrase recommenda… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.03140v2-abstract-full').style.display = 'inline'; document.getElementById('2409.03140v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2409.03140v2-abstract-full" style="display: none;"> Online sellers and advertisers are recommended keyphrases for their listed products, which they bid on to enhance their sales. One popular paradigm that generates such recommendations is Extreme Multi-Label Classification (XMC), which involves tagging/mapping keyphrases to items. We outline the limitations of using traditional item-query based tagging or mapping techniques for keyphrase recommendations on E-Commerce platforms. We introduce GraphEx, an innovative graph-based approach that recommends keyphrases to sellers using extraction of token permutations from item titles. Additionally, we demonstrate that relying on traditional metrics such as precision/recall can be misleading in practical applications, thereby necessitating a combination of metrics to evaluate performance in real-world scenarios. These metrics are designed to assess the relevance of keyphrases to items and the potential for buyer outreach. GraphEx outperforms production models at eBay, achieving the objectives mentioned above. It supports near real-time inferencing in resource-constrained production environments and scales effectively for billions of items. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2409.03140v2-abstract-full').style.display = 'none'; document.getElementById('2409.03140v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 6 September, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 4 September, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.07611">arXiv:2408.07611</a> <span> [<a href="https://arxiv.org/pdf/2408.07611">pdf</a>, <a href="https://arxiv.org/format/2408.07611">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Information Retrieval">cs.IR</span> </div> </div> <p class="title is-5 mathjax"> WeKnow-RAG: An Adaptive Approach for Retrieval-Augmented Generation Integrating Web Search and Knowledge Graphs </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Xie%2C+W">Weijian Xie</a>, <a href="/search/cs?searchtype=author&query=Liang%2C+X">Xuefeng Liang</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+Y">Yuhui Liu</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kaihua Ni</a>, <a href="/search/cs?searchtype=author&query=Cheng%2C+H">Hong Cheng</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+Z">Zetian Hu</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.07611v2-abstract-short" style="display: inline;"> Large Language Models (LLMs) have greatly contributed to the development of adaptive intelligent agents and are positioned as an important way to achieve Artificial General Intelligence (AGI). However, LLMs are prone to produce factually incorrect information and often produce "phantom" content that undermines their reliability, which poses a serious challenge for their deployment in real-world sc… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.07611v2-abstract-full').style.display = 'inline'; document.getElementById('2408.07611v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.07611v2-abstract-full" style="display: none;"> Large Language Models (LLMs) have greatly contributed to the development of adaptive intelligent agents and are positioned as an important way to achieve Artificial General Intelligence (AGI). However, LLMs are prone to produce factually incorrect information and often produce "phantom" content that undermines their reliability, which poses a serious challenge for their deployment in real-world scenarios. Enhancing LLMs by combining external databases and information retrieval mechanisms is an effective path. To address the above challenges, we propose a new approach called WeKnow-RAG, which integrates Web search and Knowledge Graphs into a "Retrieval-Augmented Generation (RAG)" system. First, the accuracy and reliability of LLM responses are improved by combining the structured representation of Knowledge Graphs with the flexibility of dense vector retrieval. WeKnow-RAG then utilizes domain-specific knowledge graphs to satisfy a variety of queries and domains, thereby improving performance on factual information and complex reasoning tasks by employing multi-stage web page retrieval techniques using both sparse and dense retrieval methods. Our approach effectively balances the efficiency and accuracy of information retrieval, thus improving the overall retrieval process. Finally, we also integrate a self-assessment mechanism for the LLM to evaluate the trustworthiness of the answers it generates. Our approach proves its outstanding effectiveness in a wide range of offline experiments and online submissions. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.07611v2-abstract-full').style.display = 'none'; document.getElementById('2408.07611v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 27 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 14 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">8 pages, 2 figures, technical report for 3rd place in Task 3 of Meta KDD Cup 2024 CRAG Challenge</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.04169">arXiv:2408.04169</a> <span> [<a href="https://arxiv.org/pdf/2408.04169">pdf</a>, <a href="https://arxiv.org/format/2408.04169">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1145/3649329.3655988">10.1145/3649329.3655988 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> C-Nash: A Novel Ferroelectric Computing-in-Memory Architecture for Solving Mixed Strategy Nash Equilibrium </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Qian%2C+Y">Yu Qian</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.04169v1-abstract-short" style="display: inline;"> The concept of Nash equilibrium (NE), pivotal within game theory, has garnered widespread attention across numerous industries. Recent advancements introduced several quantum Nash solvers aimed at identifying pure strategy NE solutions (i.e., binary solutions) by integrating slack terms into the objective function, commonly referred to as slack-quadratic unconstrained binary optimization (S-QUBO).… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.04169v1-abstract-full').style.display = 'inline'; document.getElementById('2408.04169v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.04169v1-abstract-full" style="display: none;"> The concept of Nash equilibrium (NE), pivotal within game theory, has garnered widespread attention across numerous industries. Recent advancements introduced several quantum Nash solvers aimed at identifying pure strategy NE solutions (i.e., binary solutions) by integrating slack terms into the objective function, commonly referred to as slack-quadratic unconstrained binary optimization (S-QUBO). However, incorporation of slack terms into the quadratic optimization results in changes of the objective function, which may cause incorrect solutions. Furthermore, these quantum solvers only identify a limited subset of pure strategy NE solutions, and fail to address mixed strategy NE (i.e., decimal solutions), leaving many solutions undiscovered. In this work, we propose C-Nash, a novel ferroelectric computing-in-memory (CiM) architecture that can efficiently handle both pure and mixed strategy NE solutions. The proposed architecture consists of (i) a transformation method that converts quadratic optimization into a MAX-QUBO form without introducing additional slack variables, thereby avoiding objective function changes; (ii) a ferroelectric FET (FeFET) based bi-crossbar structure for storing payoff matrices and accelerating the core vector-matrix-vector (VMV) multiplications of QUBO form; (iii) A winner-takes-all (WTA) tree implementing the MAX form and a two-phase based simulated annealing (SA) logic for searching NE solutions. Evaluations show that C-Nash has up to 68.6% increase in the success rate for identifying NE solutions, finding all pure and mixed NE solutions rather than only a portion of pure NE solutions, compared to D-Wave based quantum approaches. Moreover, C-Nash boasts a reduction up to 157.9X/79.0X in time-to-solutions compared to D-Wave 2000 Q6 and D-Wave Advantage 4.1, respectively. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.04169v1-abstract-full').style.display = 'none'; document.getElementById('2408.04169v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2407.18637">arXiv:2407.18637</a> <span> [<a href="https://arxiv.org/pdf/2407.18637">pdf</a>, <a href="https://arxiv.org/format/2407.18637">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> DynamicTrack: Advancing Gigapixel Tracking in Crowded Scenes </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Zhao%2C+Y">Yunqi Zhao</a>, <a href="/search/cs?searchtype=author&query=Guo%2C+Y">Yuchen Guo</a>, <a href="/search/cs?searchtype=author&query=Cao%2C+Z">Zheng Cao</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+R">Ruqi Huang</a>, <a href="/search/cs?searchtype=author&query=Fang%2C+L">Lu Fang</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2407.18637v1-abstract-short" style="display: inline;"> Tracking in gigapixel scenarios holds numerous potential applications in video surveillance and pedestrian analysis. Existing algorithms attempt to perform tracking in crowded scenes by utilizing multiple cameras or group relationships. However, their performance significantly degrades when confronted with complex interaction and occlusion inherent in gigapixel images. In this paper, we introduce… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2407.18637v1-abstract-full').style.display = 'inline'; document.getElementById('2407.18637v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2407.18637v1-abstract-full" style="display: none;"> Tracking in gigapixel scenarios holds numerous potential applications in video surveillance and pedestrian analysis. Existing algorithms attempt to perform tracking in crowded scenes by utilizing multiple cameras or group relationships. However, their performance significantly degrades when confronted with complex interaction and occlusion inherent in gigapixel images. In this paper, we introduce DynamicTrack, a dynamic tracking framework designed to address gigapixel tracking challenges in crowded scenes. In particular, we propose a dynamic detector that utilizes contrastive learning to jointly detect the head and body of pedestrians. Building upon this, we design a dynamic association algorithm that effectively utilizes head and body information for matching purposes. Extensive experiments show that our tracker achieves state-of-the-art performance on widely used tracking benchmarks specifically designed for gigapixel crowded scenes. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2407.18637v1-abstract-full').style.display = 'none'; document.getElementById('2407.18637v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 26 July, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> July 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2406.04750">arXiv:2406.04750</a> <span> [<a href="https://arxiv.org/pdf/2406.04750">pdf</a>, <a href="https://arxiv.org/format/2406.04750">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Information Theory">cs.IT</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Signal Processing">eess.SP</span> </div> </div> <p class="title is-5 mathjax"> Throughput and Fairness Trade-off Balancing for UAV-Enabled Wireless Communication Systems </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kejie Ni</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+J">Jingqing Wang</a>, <a href="/search/cs?searchtype=author&query=Cheng%2C+W">Wenchi Cheng</a>, <a href="/search/cs?searchtype=author&query=Zhang%2C+W">Wei Zhang</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2406.04750v1-abstract-short" style="display: inline;"> Given the imperative of 6G networks' ubiquitous connectivity, along with the inherent mobility and cost-effectiveness of unmanned aerial vehicles (UAVs), UAVs play a critical role within 6G wireless networks. Despite advancements in enhancing the UAV-enabled communication systems' throughput in existing studies, there remains a notable gap in addressing issues concerning user fairness and quality-… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2406.04750v1-abstract-full').style.display = 'inline'; document.getElementById('2406.04750v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2406.04750v1-abstract-full" style="display: none;"> Given the imperative of 6G networks' ubiquitous connectivity, along with the inherent mobility and cost-effectiveness of unmanned aerial vehicles (UAVs), UAVs play a critical role within 6G wireless networks. Despite advancements in enhancing the UAV-enabled communication systems' throughput in existing studies, there remains a notable gap in addressing issues concerning user fairness and quality-of-service (QoS) provisioning and lacks an effective scheme to depict the trade-off between system throughput and user fairness. To solve the above challenges, in this paper we introduce a novel fairness control scheme for UAV-enabled wireless communication systems based on a new weighted function. First, we propose a throughput combining model based on a new weighted function with fairness considering. Second, we formulate the optimization problem to maximize the weighted sum of all users' throughput. Third, we decompose the optimization problem and propose an efficient iterative algorithm to solve it. Finally, simulation results are provided to demonstrate the considerable potential of our proposed scheme in fairness and QoS provisioning. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2406.04750v1-abstract-full').style.display = 'none'; document.getElementById('2406.04750v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 June, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">submit to 2024 IEEE GLOBECOM</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2406.02833">arXiv:2406.02833</a> <span> [<a href="https://arxiv.org/pdf/2406.02833">pdf</a>, <a href="https://arxiv.org/format/2406.02833">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> DenoDet: Attention as Deformable Multi-Subspace Feature Denoising for Target Detection in SAR Images </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Dai%2C+Y">Yimian Dai</a>, <a href="/search/cs?searchtype=author&query=Zou%2C+M">Minrui Zou</a>, <a href="/search/cs?searchtype=author&query=Li%2C+Y">Yuxuan Li</a>, <a href="/search/cs?searchtype=author&query=Li%2C+X">Xiang Li</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kang Ni</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+J">Jian Yang</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2406.02833v2-abstract-short" style="display: inline;"> Synthetic Aperture Radar (SAR) target detection has long been impeded by inherent speckle noise and the prevalence of diminutive, ambiguous targets. While deep neural networks have advanced SAR target detection, their intrinsic low-frequency bias and static post-training weights falter with coherent noise and preserving subtle details across heterogeneous terrains. Motivated by traditional SAR ima… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2406.02833v2-abstract-full').style.display = 'inline'; document.getElementById('2406.02833v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2406.02833v2-abstract-full" style="display: none;"> Synthetic Aperture Radar (SAR) target detection has long been impeded by inherent speckle noise and the prevalence of diminutive, ambiguous targets. While deep neural networks have advanced SAR target detection, their intrinsic low-frequency bias and static post-training weights falter with coherent noise and preserving subtle details across heterogeneous terrains. Motivated by traditional SAR image denoising, we propose DenoDet, a network aided by explicit frequency domain transform to calibrate convolutional biases and pay more attention to high-frequencies, forming a natural multi-scale subspace representation to detect targets from the perspective of multi-subspace denoising. We design TransDeno, a dynamic frequency domain attention module that performs as a transform domain soft thresholding operation, dynamically denoising across subspaces by preserving salient target signals and attenuating noise. To adaptively adjust the granularity of subspace processing, we also propose a deformable group fully-connected layer (DeGroFC) that dynamically varies the group conditioned on the input features. Without bells and whistles, our plug-and-play TransDeno sets state-of-the-art scores on multiple SAR target detection datasets. The code is available at https://github.com/GrokCV/GrokSAR. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2406.02833v2-abstract-full').style.display = 'none'; document.getElementById('2406.02833v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 10 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 4 June, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2405.04700">arXiv:2405.04700</a> <span> [<a href="https://arxiv.org/pdf/2405.04700">pdf</a>, <a href="https://arxiv.org/format/2405.04700">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Distributed, Parallel, and Cluster Computing">cs.DC</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Information Retrieval">cs.IR</span> </div> </div> <p class="title is-5 mathjax"> Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Qin%2C+R">Ruiyang Qin</a>, <a href="/search/cs?searchtype=author&query=Yan%2C+Z">Zheyu Yan</a>, <a href="/search/cs?searchtype=author&query=Zeng%2C+D">Dewen Zeng</a>, <a href="/search/cs?searchtype=author&query=Jia%2C+Z">Zhenge Jia</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+D">Dancheng Liu</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+J">Jianbo Liu</a>, <a href="/search/cs?searchtype=author&query=Zheng%2C+Z">Zhi Zheng</a>, <a href="/search/cs?searchtype=author&query=Cao%2C+N">Ningyuan Cao</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Xiong%2C+J">Jinjun Xiong</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Y">Yiyu Shi</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2405.04700v1-abstract-short" style="display: inline;"> Large Language Models (LLMs) deployed on edge devices learn through fine-tuning and updating a certain portion of their parameters. Although such learning methods can be optimized to reduce resource utilization, the overall required resources remain a heavy burden on edge devices. Instead, Retrieval-Augmented Generation (RAG), a resource-efficient LLM learning method, can improve the quality of th… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2405.04700v1-abstract-full').style.display = 'inline'; document.getElementById('2405.04700v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2405.04700v1-abstract-full" style="display: none;"> Large Language Models (LLMs) deployed on edge devices learn through fine-tuning and updating a certain portion of their parameters. Although such learning methods can be optimized to reduce resource utilization, the overall required resources remain a heavy burden on edge devices. Instead, Retrieval-Augmented Generation (RAG), a resource-efficient LLM learning method, can improve the quality of the LLM-generated content without updating model parameters. However, the RAG-based LLM may involve repetitive searches on the profile data in every user-LLM interaction. This search can lead to significant latency along with the accumulation of user data. Conventional efforts to decrease latency result in restricting the size of saved user data, thus reducing the scalability of RAG as user data continuously grows. It remains an open question: how to free RAG from the constraints of latency and scalability on edge devices? In this paper, we propose a novel framework to accelerate RAG via Computing-in-Memory (CiM) architectures. It accelerates matrix multiplications by performing in-situ computation inside the memory while avoiding the expensive data transfer between the computing unit and memory. Our framework, Robust CiM-backed RAG (RoCR), utilizing a novel contrastive learning-based training method and noise-aware training, can enable RAG to efficiently search profile data with CiM. To the best of our knowledge, this is the first work utilizing CiM to accelerate RAG. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2405.04700v1-abstract-full').style.display = 'none'; document.getElementById('2405.04700v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 May, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2404.14316">arXiv:2404.14316</a> <span> [<a href="https://arxiv.org/pdf/2404.14316">pdf</a>, <a href="https://arxiv.org/format/2404.14316">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> </div> </div> <p class="title is-5 mathjax"> Automated Long Answer Grading with RiceChem Dataset </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Sonkar%2C+S">Shashank Sonkar</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kangqi Ni</a>, <a href="/search/cs?searchtype=author&query=Lu%2C+L+T">Lesa Tran Lu</a>, <a href="/search/cs?searchtype=author&query=Kincaid%2C+K">Kristi Kincaid</a>, <a href="/search/cs?searchtype=author&query=Hutchinson%2C+J+S">John S. Hutchinson</a>, <a href="/search/cs?searchtype=author&query=Baraniuk%2C+R+G">Richard G. Baraniuk</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2404.14316v1-abstract-short" style="display: inline;"> We introduce a new area of study in the field of educational Natural Language Processing: Automated Long Answer Grading (ALAG). Distinguishing itself from Automated Short Answer Grading (ASAG) and Automated Essay Grading (AEG), ALAG presents unique challenges due to the complexity and multifaceted nature of fact-based long answers. To study ALAG, we introduce RiceChem, a dataset derived from a col… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2404.14316v1-abstract-full').style.display = 'inline'; document.getElementById('2404.14316v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2404.14316v1-abstract-full" style="display: none;"> We introduce a new area of study in the field of educational Natural Language Processing: Automated Long Answer Grading (ALAG). Distinguishing itself from Automated Short Answer Grading (ASAG) and Automated Essay Grading (AEG), ALAG presents unique challenges due to the complexity and multifaceted nature of fact-based long answers. To study ALAG, we introduce RiceChem, a dataset derived from a college chemistry course, featuring real student responses to long-answer questions with an average word count notably higher than typical ASAG datasets. We propose a novel approach to ALAG by formulating it as a rubric entailment problem, employing natural language inference models to verify whether each criterion, represented by a rubric item, is addressed in the student's response. This formulation enables the effective use of MNLI for transfer learning, significantly improving the performance of models on the RiceChem dataset. We demonstrate the importance of rubric-based formulation in ALAG, showcasing its superiority over traditional score-based approaches in capturing the nuances of student responses. We also investigate the performance of models in cold start scenarios, providing valuable insights into the practical deployment considerations in educational settings. Lastly, we benchmark state-of-the-art open-sourced Large Language Models (LLMs) on RiceChem and compare their results to GPT models, highlighting the increased complexity of ALAG compared to ASAG. Despite leveraging the benefits of a rubric-based approach and transfer learning from MNLI, the lower performance of LLMs on RiceChem underscores the significant difficulty posed by the ALAG task. With this work, we offer a fresh perspective on grading long, fact-based answers and introduce a new dataset to stimulate further research in this important area. Code: \url{https://github.com/luffycodes/Automated-Long-Answer-Grading}. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2404.14316v1-abstract-full').style.display = 'none'; document.getElementById('2404.14316v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 22 April, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2404.00196">arXiv:2404.00196</a> <span> [<a href="https://arxiv.org/pdf/2404.00196">pdf</a>, <a href="https://arxiv.org/format/2404.00196">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Cryptography and Security">cs.CR</span> </div> </div> <p class="title is-5 mathjax"> Combined Static Analysis and Machine Learning Prediction for Application Debloating </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Porter%2C+C">Chris Porter</a>, <a href="/search/cs?searchtype=author&query=Khan%2C+S">Sharjeel Khan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kangqi Ni</a>, <a href="/search/cs?searchtype=author&query=Pande%2C+S">Santosh Pande</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2404.00196v1-abstract-short" style="display: inline;"> Software debloating can effectively thwart certain code reuse attacks by reducing attack surfaces to break gadget chains. Approaches based on static analysis enable a reduced set of functions reachable at a callsite for execution by leveraging static properties of the callgraph. This achieves low runtime overhead, but the function set is conservatively computed, negatively affecting reduction. In… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2404.00196v1-abstract-full').style.display = 'inline'; document.getElementById('2404.00196v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2404.00196v1-abstract-full" style="display: none;"> Software debloating can effectively thwart certain code reuse attacks by reducing attack surfaces to break gadget chains. Approaches based on static analysis enable a reduced set of functions reachable at a callsite for execution by leveraging static properties of the callgraph. This achieves low runtime overhead, but the function set is conservatively computed, negatively affecting reduction. In contrast, approaches based on machine learning (ML) have much better precision and can sharply reduce function sets, leading to significant improvement in attack surface. Nevertheless, mispredictions occur in ML-based approaches. These cause overheads, and worse, there is no clear way to distinguish between mispredictions and actual attacks. In this work, we contend that a software debloating approach that incorporates ML-based predictions at runtime is realistic in a whole application setting, and that it can achieve significant attack surface reductions beyond the state of the art. We develop a framework, Predictive Debloat with Static Guarantees (PDSG). PDSG is fully sound and works on application source code. At runtime it predicts the dynamic callee set emanating from a callsite, and to resolve mispredictions, it employs a lightweight audit based on static invariants of call chains. We deduce the invariants offline and assert that they hold at runtime when there is a misprediction. To the best of our knowledge, it achieves the highest gadget reductions among similar techniques on SPEC CPU 2017, reducing 82.5% of the total gadgets on average. It triggers misprediction checks on only 3.8% of the total predictions invoked at runtime, and it leverages Datalog to verify dynamic call sequences conform to the static call relations. It has an overhead of 8.9%, which makes the scheme attractive for practical deployments. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2404.00196v1-abstract-full').style.display = 'none'; document.getElementById('2404.00196v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 29 March, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2024. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2403.04981">arXiv:2403.04981</a> <span> [<a href="https://arxiv.org/pdf/2403.04981">pdf</a>, <a href="https://arxiv.org/format/2403.04981">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Woo%2C+S">Sola Woo</a>, <a href="/search/cs?searchtype=author&query=Aabrar%2C+K+A">Khandker Akif Aabrar</a>, <a href="/search/cs?searchtype=author&query=Kirtania%2C+S+G">Sharadindu Gopal Kirtania</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Xiao%2C+Y">Yi Xiao</a>, <a href="/search/cs?searchtype=author&query=Mulaosmanovic%2C+H">Halid Mulaosmanovic</a>, <a href="/search/cs?searchtype=author&query=Duenkel%2C+S">Stefan Duenkel</a>, <a href="/search/cs?searchtype=author&query=Kleimaier%2C+D">Dominik Kleimaier</a>, <a href="/search/cs?searchtype=author&query=Soss%2C+S">Steven Soss</a>, <a href="/search/cs?searchtype=author&query=Beyer%2C+S">Sven Beyer</a>, <a href="/search/cs?searchtype=author&query=Joshi%2C+R">Rajiv Joshi</a>, <a href="/search/cs?searchtype=author&query=Meninger%2C+S">Scott Meninger</a>, <a href="/search/cs?searchtype=author&query=Mohamed%2C+M">Mohamed Mohamed</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+K">Kijoon Kim</a>, <a href="/search/cs?searchtype=author&query=Woo%2C+J">Jongho Woo</a>, <a href="/search/cs?searchtype=author&query=Lim%2C+S">Suhwan Lim</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+K">Kwangsoo Kim</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+W">Wanki Kim</a>, <a href="/search/cs?searchtype=author&query=Ha%2C+D">Daewon Ha</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Datta%2C+S">Suman Datta</a>, <a href="/search/cs?searchtype=author&query=Yu%2C+S">Shimeng Yu</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2403.04981v1-abstract-short" style="display: inline;"> In this work, we propose a dual-port cell design to address the pass disturb in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that: i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-${V}_{TH}$ (HVT) state and the screening of the applied field by channel at the low-… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2403.04981v1-abstract-full').style.display = 'inline'; document.getElementById('2403.04981v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2403.04981v1-abstract-full" style="display: none;"> In this work, we propose a dual-port cell design to address the pass disturb in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that: i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-${V}_{TH}$ (HVT) state and the screening of the applied field by channel at the low-${V}_{TH}$ (LVT) state; ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; iii) the proposed design can be incorporated in a highly scaled vertical NAND FeFET string and the pass gate can be incorporated into the existing 3D NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2403.04981v1-abstract-full').style.display = 'none'; document.getElementById('2403.04981v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 March, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> March 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">29 pages, 7 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2402.05000">arXiv:2402.05000</a> <span> [<a href="https://arxiv.org/pdf/2402.05000">pdf</a>, <a href="https://arxiv.org/format/2402.05000">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> </div> </div> <p class="title is-5 mathjax"> Pedagogical Alignment of Large Language Models </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Sonkar%2C+S">Shashank Sonkar</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kangqi Ni</a>, <a href="/search/cs?searchtype=author&query=Chaudhary%2C+S">Sapana Chaudhary</a>, <a href="/search/cs?searchtype=author&query=Baraniuk%2C+R+G">Richard G. Baraniuk</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2402.05000v3-abstract-short" style="display: inline;"> Large Language Models (LLMs), when used in educational settings without pedagogical fine-tuning, often provide immediate answers rather than guiding students through the problem-solving process. This approach falls short of pedagogically best practices and limits their effectiveness as educational tools. We term the objective of training LLMs to emulate effective teaching strategies as `pedagogica… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2402.05000v3-abstract-full').style.display = 'inline'; document.getElementById('2402.05000v3-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2402.05000v3-abstract-full" style="display: none;"> Large Language Models (LLMs), when used in educational settings without pedagogical fine-tuning, often provide immediate answers rather than guiding students through the problem-solving process. This approach falls short of pedagogically best practices and limits their effectiveness as educational tools. We term the objective of training LLMs to emulate effective teaching strategies as `pedagogical alignment.' In this paper, we investigate Learning from Human Preferences (LHP) algorithms to achieve this alignment objective. A key challenge in this process is the scarcity of high-quality preference datasets to guide the alignment. To address this, we propose a novel approach for constructing a large-scale dataset using synthetic data generation techniques, eliminating the need for time-consuming and costly manual annotation. Leveraging this dataset, our experiments with Llama and Mistral models demonstrate that LHP methods outperform standard supervised fine-tuning (SFT), improving pedagogical alignment accuracy by 13.1% and 8.7% respectively. Existing evaluation methods also lack quantitative metrics to adequately measure the pedagogical alignment of LLMs. To address this gap, we propose novel perplexity-based metrics that quantify LLMs' tendency to provide scaffolded guidance versus direct answers, offering a robust measure of pedagogical alignment. Our analysis provides compelling evidence for the superiority of LHP methods over SFT in optimizing LLMs' behavior, underscoring the potential of LHP methods in better aligning LLMs with educational objectives and fostering effective learning experiences. Code and models are available \href{https://github.com/luffycodes/Tutorbot-Spock}{here}. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2402.05000v3-abstract-full').style.display = 'none'; document.getElementById('2402.05000v3-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 5 October, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 7 February, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> February 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted at EMNLP 2024 Findings Track</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2312.17444">arXiv:2312.17444</a> <span> [<a href="https://arxiv.org/pdf/2312.17444">pdf</a>, <a href="https://arxiv.org/format/2312.17444">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Signal Processing">eess.SP</span> </div> </div> <p class="title is-5 mathjax"> Reconfigurable Frequency Multipliers Based on Complementary Ferroelectric Transistors </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Xu%2C+H">Haotian Xu</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+J">Jianyi Yang</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2312.17444v1-abstract-short" style="display: inline;"> Frequency multipliers, a class of essential electronic components, play a pivotal role in contemporary signal processing and communication systems. They serve as crucial building blocks for generating high-frequency signals by multiplying the frequency of an input signal. However, traditional frequency multipliers that rely on nonlinear devices often require energy- and area-consuming filtering an… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.17444v1-abstract-full').style.display = 'inline'; document.getElementById('2312.17444v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2312.17444v1-abstract-full" style="display: none;"> Frequency multipliers, a class of essential electronic components, play a pivotal role in contemporary signal processing and communication systems. They serve as crucial building blocks for generating high-frequency signals by multiplying the frequency of an input signal. However, traditional frequency multipliers that rely on nonlinear devices often require energy- and area-consuming filtering and amplification circuits, and emerging designs based on an ambipolar ferroelectric transistor require costly non-trivial characteristic tuning or complex technology process. In this paper, we show that a pair of standard ferroelectric field effect transistors (FeFETs) can be used to build compact frequency multipliers without aforementioned technology issues. By leveraging the tunable parabolic shape of the 2FeFET structures' transfer characteristics, we propose four reconfigurable frequency multipliers, which can switch between signal transmission and frequency doubling. Furthermore, based on the 2FeFET structures, we propose four frequency multipliers that realize triple, quadruple frequency modes, elucidating a scalable methodology to generate more multiplication harmonics of the input frequency. Performance metrics such as maximum operating frequency, power, etc., are evaluated and compared with existing works. We also implement a practical case of frequency modulation scheme based on the proposed reconfigurable multipliers without additional devices. Our work provides a novel path of scalable and reconfigurable frequency multiplier designs based on devices that have characteristics similar to FeFETs, and show that FeFETs are a promising candidate for signal processing and communication systems in terms of maximum operating frequency and power. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.17444v1-abstract-full').style.display = 'none'; document.getElementById('2312.17444v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 28 December, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">6 pages, 8 figures, 1 table. Accepted by Design Automation and Test in Europe (DATE) 2024</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2312.17442">arXiv:2312.17442</a> <span> [<a href="https://arxiv.org/pdf/2312.17442">pdf</a>, <a href="https://arxiv.org/format/2312.17442">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Zhou%2C+Y">Yifei Zhou</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+X">Xuchu Huang</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+J">Jianyi Yang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Amrouch%2C+H">Hussam Amrouch</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2312.17442v2-abstract-short" style="display: inline;"> Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as 'memory wall' issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.17442v2-abstract-full').style.display = 'inline'; document.getElementById('2312.17442v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2312.17442v2-abstract-full" style="display: none;"> Compute-in-memory (CiM) is a promising solution for addressing the challenges of artificial intelligence (AI) and the Internet of Things (IoT) hardware such as 'memory wall' issue. Specifically, CiM employing nonvolatile memory (NVM) devices in a crossbar structure can efficiently accelerate multiply-accumulation (MAC) computation, a crucial operator in neural networks among various AI models. Low power CiM designs are thus highly desired for further energy efficiency optimization on AI models. Ferroelectric FET (FeFET), an emerging device, is attractive for building ultra-low power CiM array due to CMOS compatibility, high ION/IOFF ratio, etc. Recent studies have explored FeFET based CiM designs that achieve low power consumption. Nevertheless, subthreshold-operated FeFETs, where the operating voltages are scaled down to the subthreshold region to reduce array power consumption, are particularly vulnerable to temperature drift, leading to accuracy degradation. To address this challenge, we propose a temperature-resilient 2T-1FeFET CiM design that performs MAC operations reliably at subthreahold region from 0 to 85 Celsius, while consuming ultra-low power. Benchmarked against the VGG neural network architecture running the CIFAR-10 dataset, the proposed 2T-1FeFET CiM design achieves 89.45% CIFAR-10 test accuracy. Compared to previous FeFET based CiM designs, it exhibits immunity to temperature drift at an 8-bit wordlength scale, and achieves better energy efficiency with 2866 TOPS/W. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.17442v2-abstract-full').style.display = 'none'; document.getElementById('2312.17442v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 10 January, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 28 December, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">6 pages, 9 figures, 2 tables. Accepted by Design Automation and Test in Europe (DATE) 2024</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2312.15444">arXiv:2312.15444</a> <span> [<a href="https://arxiv.org/pdf/2312.15444">pdf</a>, <a href="https://arxiv.org/format/2312.15444">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Manna%2C+B">Bibhas Manna</a>, <a href="/search/cs?searchtype=author&query=Saha%2C+A">Arnob Saha</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Sengupta%2C+A">Abhronil Sengupta</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2312.15444v2-abstract-short" style="display: inline;"> Reliability issues stemming from device level non-idealities of non-volatile emerging technologies like ferroelectric field-effect transistors (FeFET), especially at scaled dimensions, cause substantial degradation in the accuracy of In-Memory crossbar-based AI systems. In this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their imp… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.15444v2-abstract-full').style.display = 'inline'; document.getElementById('2312.15444v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2312.15444v2-abstract-full" style="display: none;"> Reliability issues stemming from device level non-idealities of non-volatile emerging technologies like ferroelectric field-effect transistors (FeFET), especially at scaled dimensions, cause substantial degradation in the accuracy of In-Memory crossbar-based AI systems. In this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian Neural Network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-$k$ metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by $\sim$3.8-16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2312.15444v2-abstract-full').style.display = 'none'; document.getElementById('2312.15444v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 13 March, 2024; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 24 December, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2023. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2310.04940">arXiv:2310.04940</a> <span> [<a href="https://arxiv.org/pdf/2310.04940">pdf</a>, <a href="https://arxiv.org/format/2310.04940">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> SEE-MCAM: Scalable Multi-bit FeFET Content Addressable Memories for Energy Efficient Associative Search </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Shou%2C+S">Shengxi Shou</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+C">Che-Kai Liu</a>, <a href="/search/cs?searchtype=author&query=Yun%2C+S">Sanggeon Yun</a>, <a href="/search/cs?searchtype=author&query=Wan%2C+Z">Zishen Wan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Imani%2C+M">Mohsen Imani</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">X. Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+J">Jianyi Yang</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2310.04940v1-abstract-short" style="display: inline;"> In this work, we propose SEE-MCAM, scalable and compact multi-bit CAM (MCAM) designs that utilize the three-terminal ferroelectric FET (FeFET) as the proxy. By exploiting the multi-level-cell characteristics of FeFETs, our proposed SEE-MCAM designs enable multi-bit associative search functions and achieve better energy efficiency and performance than existing FeFET-based CAM designs. We validated… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2310.04940v1-abstract-full').style.display = 'inline'; document.getElementById('2310.04940v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2310.04940v1-abstract-full" style="display: none;"> In this work, we propose SEE-MCAM, scalable and compact multi-bit CAM (MCAM) designs that utilize the three-terminal ferroelectric FET (FeFET) as the proxy. By exploiting the multi-level-cell characteristics of FeFETs, our proposed SEE-MCAM designs enable multi-bit associative search functions and achieve better energy efficiency and performance than existing FeFET-based CAM designs. We validated the functionality of our proposed designs by achieving 3 bits per cell CAM functionality, resulting in 3x improvement in storage density. The area per bit of the proposed SEE-MCAM cell is 8% of the conventional CMOS CAM. We thoroughly investigated the scalability and robustness of the proposed design. Evaluation results suggest that the proposed 2FeFET-1T SEE-MCAM achieves 9.8x more energy efficiency and 1.6x less search latency compared to the CMOS CAM, respectively. When compared to existing MCAM designs, the proposed SEE-MCAM can achieve 8.7x and 4.9x more energy efficiency than ReRAM-based and FeFET-based MCAMs, respectively. Benchmarking results show that our approach provides up to 3 orders of magnitude improvement in speedup and energy efficiency over a GPU implementation in accelerating a novel quantized hyperdimensional computing (HDC) application. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2310.04940v1-abstract-full').style.display = 'none'; document.getElementById('2310.04940v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 7 October, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted by Internation Conference on Computer-Aided Design (ICCAD), 2023</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2309.13853">arXiv:2309.13853</a> <span> [<a href="https://arxiv.org/pdf/2309.13853">pdf</a>, <a href="https://arxiv.org/format/2309.13853">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1038/s41467-024-46640-x">10.1038/s41467-024-46640-x <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> A Ferroelectric Compute-in-Memory Annealer for Combinatorial Optimization Problems </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=Qian%2C+Y">Yu Qian</a>, <a href="/search/cs?searchtype=author&query=Vardar%2C+A">Alptekin Vardar</a>, <a href="/search/cs?searchtype=author&query=Gunther%2C+M">Marcel Gunther</a>, <a href="/search/cs?searchtype=author&query=Muller%2C+F">Franz Muller</a>, <a href="/search/cs?searchtype=author&query=Laleni%2C+N">Nellie Laleni</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Z">Zhiguo Shi</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Y">Yiyu Shi</a>, <a href="/search/cs?searchtype=author&query=Gong%2C+X">Xiao Gong</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Kampfe%2C+T">Thomas Kampfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2309.13853v1-abstract-short" style="display: inline;"> Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications, including logistical planning, resource allocation, chip design, drug explorations, and more. Due to their critical significance and the inability of conventional hardware in efficiently handling scaled COPs, there is a growing interest in developing computing hardware tailored specifically for COP… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2309.13853v1-abstract-full').style.display = 'inline'; document.getElementById('2309.13853v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2309.13853v1-abstract-full" style="display: none;"> Computationally hard combinatorial optimization problems (COPs) are ubiquitous in many applications, including logistical planning, resource allocation, chip design, drug explorations, and more. Due to their critical significance and the inability of conventional hardware in efficiently handling scaled COPs, there is a growing interest in developing computing hardware tailored specifically for COPs, including digital annealers, dynamical Ising machines, and quantum/photonic systems. However, significant hurdles still remain, such as the memory access issue, the system scalability and restricted applicability to certain types of COPs, and VLSI-incompatibility, respectively. Here, a ferroelectric field effect transistor (FeFET) based compute-in-memory (CiM) annealer is proposed. After converting COPs into quadratic unconstrained binary optimization (QUBO) formulations, a hardware-algorithm co-design is conducted, yielding an energy-efficient, versatile, and scalable hardware for COPs. To accelerate the core vector-matrix-vector (VMV) multiplication of QUBO formulations, a FeFET based CiM array is exploited, which can accelerate the intended operation in-situ due to its unique three-terminal structure. In particular, a lossless compression technique is proposed to prune typically sparse QUBO matrix to reduce hardware cost. Furthermore, a multi-epoch simulated annealing (MESA) algorithm is proposed to replace conventional simulated annealing for its faster convergence and better solution quality. The effectiveness of the proposed techniques is validated through the utilization of developed chip prototypes for successfully solving graph coloring problem, indicating great promise of FeFET CiM annealer in solving general COPs. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2309.13853v1-abstract-full').style.display = 'none'; document.getElementById('2309.13853v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 24 September, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">39 pages, 12 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2306.01863">arXiv:2306.01863</a> <span> [<a href="https://arxiv.org/pdf/2306.01863">pdf</a>, <a href="https://arxiv.org/format/2306.01863">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Embedding Security into Ferroelectric FET Array via In-Situ Memory Operation </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Xu%2C+Y">Yixin Xu</a>, <a href="/search/cs?searchtype=author&query=Xiao%2C+Y">Yi Xiao</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=M%C3%BCller%2C+F">Franz M眉ller</a>, <a href="/search/cs?searchtype=author&query=Vardar%2C+A">Alptekin Vardar</a>, <a href="/search/cs?searchtype=author&query=Gong%2C+X">Xiao Gong</a>, <a href="/search/cs?searchtype=author&query=George%2C+S">Sumitha George</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2306.01863v1-abstract-short" style="display: inline;"> Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2306.01863v1-abstract-full').style.display = 'inline'; document.getElementById('2306.01863v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2306.01863v1-abstract-full" style="display: none;"> Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128x128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows around 22.6x/14.1x increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2306.01863v1-abstract-full').style.display = 'none'; document.getElementById('2306.01863v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 2 June, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2023. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2305.01484">arXiv:2305.01484</a> <span> [<a href="https://arxiv.org/pdf/2305.01484">pdf</a>, <a href="https://arxiv.org/format/2305.01484">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Chatterjee%2C+S">Swetaki Chatterjee</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Islam%2C+M+S">Muhammad Shaffatul Islam</a>, <a href="/search/cs?searchtype=author&query=Xiao%2C+Y">Yi Xiao</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+Y">Yixin Xu</a>, <a href="/search/cs?searchtype=author&query=Meninger%2C+S">Scott Meninger</a>, <a href="/search/cs?searchtype=author&query=Mohamed%2C+M">Mohamed Mohamed</a>, <a href="/search/cs?searchtype=author&query=Joshi%2C+R">Rajiv Joshi</a>, <a href="/search/cs?searchtype=author&query=Chauhan%2C+Y+S">Yogesh Singh Chauhan</a>, <a href="/search/cs?searchtype=author&query=Mulaosmanovic%2C+H">Halid Mulaosmanovic</a>, <a href="/search/cs?searchtype=author&query=Duenkel%2C+S">Stefan Duenkel</a>, <a href="/search/cs?searchtype=author&query=Kleimaier%2C+D">Dominik Kleimaier</a>, <a href="/search/cs?searchtype=author&query=Beyer%2C+S">Sven Beyer</a>, <a href="/search/cs?searchtype=author&query=Amrouch%2C+H">Hussam Amrouch</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2305.01484v1-abstract-short" style="display: inline;"> Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially to the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET w… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.01484v1-abstract-full').style.display = 'inline'; document.getElementById('2305.01484v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2305.01484v1-abstract-full" style="display: none;"> Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially to the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a non-ferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state and thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation have been performed on fully-depleted silicon-on-insulator (FDSOI) FeFETs integrated on 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the non-ferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.01484v1-abstract-full').style.display = 'none'; document.getElementById('2305.01484v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 2 May, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">32 pages</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2305.00149">arXiv:2305.00149</a> <span> [<a href="https://arxiv.org/pdf/2305.00149">pdf</a>, <a href="https://arxiv.org/format/2305.00149">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Image and Video Processing">eess.IV</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> X-ray Recognition: Patient identification from X-rays using a contrastive objective </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Liang%2C+H">Hao Liang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kevin Ni</a>, <a href="/search/cs?searchtype=author&query=Balakrishnan%2C+G">Guha Balakrishnan</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2305.00149v1-abstract-short" style="display: inline;"> Recent research demonstrates that deep learning models are capable of precisely extracting bio-information (e.g. race, gender and age) from patients' Chest X-Rays (CXRs). In this paper, we further show that deep learning models are also surprisingly accurate at recognition, i.e., distinguishing CXRs belonging to the same patient from those belonging to different patients. These findings suggest po… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.00149v1-abstract-full').style.display = 'inline'; document.getElementById('2305.00149v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2305.00149v1-abstract-full" style="display: none;"> Recent research demonstrates that deep learning models are capable of precisely extracting bio-information (e.g. race, gender and age) from patients' Chest X-Rays (CXRs). In this paper, we further show that deep learning models are also surprisingly accurate at recognition, i.e., distinguishing CXRs belonging to the same patient from those belonging to different patients. These findings suggest potential privacy considerations that the medical imaging community should consider with the proliferation of large public CXR databases. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.00149v1-abstract-full').style.display = 'none'; document.getElementById('2305.00149v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 28 April, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2023. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2305.00147">arXiv:2305.00147</a> <span> [<a href="https://arxiv.org/pdf/2305.00147">pdf</a>, <a href="https://arxiv.org/format/2305.00147">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Image and Video Processing">eess.IV</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> Visualizing chest X-ray dataset biases using GANs </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Liang%2C+H">Hao Liang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kevin Ni</a>, <a href="/search/cs?searchtype=author&query=Balakrishnan%2C+G">Guha Balakrishnan</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2305.00147v2-abstract-short" style="display: inline;"> Recent work demonstrates that images from various chest X-ray datasets contain visual features that are strongly correlated with protected demographic attributes like race and gender. This finding raises issues of fairness, since some of these factors may be used by downstream algorithms for clinical predictions. In this work, we propose a framework, using generative adversarial networks (GANs), t… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.00147v2-abstract-full').style.display = 'inline'; document.getElementById('2305.00147v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2305.00147v2-abstract-full" style="display: none;"> Recent work demonstrates that images from various chest X-ray datasets contain visual features that are strongly correlated with protected demographic attributes like race and gender. This finding raises issues of fairness, since some of these factors may be used by downstream algorithms for clinical predictions. In this work, we propose a framework, using generative adversarial networks (GANs), to visualize what features are most different between X-rays belonging to two demographic subgroups. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.00147v2-abstract-full').style.display = 'none'; document.getElementById('2305.00147v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 5 September, 2023; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 28 April, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Medical Imaging with Deep Learning(MIDL) 2023</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2212.08202">arXiv:2212.08202</a> <span> [<a href="https://arxiv.org/pdf/2212.08202">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Applied Physics">physics.app-ph</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Voltage-controlled Cryogenic Boolean Logic Family Based on Ferroelectric SQUID </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Alam%2C+S">Shamiul Alam</a>, <a href="/search/cs?searchtype=author&query=Hossain%2C+M+S">Md Shafayat Hossain</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Aziz%2C+A">Ahmedullah Aziz</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2212.08202v1-abstract-short" style="display: inline;"> The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of th… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.08202v1-abstract-full').style.display = 'inline'; document.getElementById('2212.08202v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2212.08202v1-abstract-full" style="display: none;"> The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a 2-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all-FeSQUID based cryogenic computer, ensure minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.08202v1-abstract-full').style.display = 'none'; document.getElementById('2212.08202v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 15 December, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">11 pages, 4 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2212.04973">arXiv:2212.04973</a> <span> [<a href="https://arxiv.org/pdf/2212.04973">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Eliminating Leakage in Volatile Memory with Anti-Ferroelectric Transistors </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Zhong%2C+H">Hongtao Zhong</a>, <a href="/search/cs?searchtype=author&query=Zheng%2C+Z">Zijie Zheng</a>, <a href="/search/cs?searchtype=author&query=Jiao%2C+L">Leming Jiao</a>, <a href="/search/cs?searchtype=author&query=Zhou%2C+Z">Zuopu Zhou</a>, <a href="/search/cs?searchtype=author&query=Sun%2C+C">Chen Sun</a>, <a href="/search/cs?searchtype=author&query=Ma%2C+X">Xiaoyang Ma</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+H">Huazhong Yang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Gong%2C+X">Xiao Gong</a>, <a href="/search/cs?searchtype=author&query=Li%2C+X">Xueqing Li</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2212.04973v4-abstract-short" style="display: inline;"> Cache serves as a temporary data memory module in many general-purpose processors and domain-specific accelerators. Its density, power, speed, and reliability play a critical role in enhancing the overall system performance and quality of service. Conventional volatile memories, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM) in the complementary meta… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.04973v4-abstract-full').style.display = 'inline'; document.getElementById('2212.04973v4-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2212.04973v4-abstract-full" style="display: none;"> Cache serves as a temporary data memory module in many general-purpose processors and domain-specific accelerators. Its density, power, speed, and reliability play a critical role in enhancing the overall system performance and quality of service. Conventional volatile memories, including static random-access memory (SRAM) and embedded dynamic random-access memory (eDRAM) in the complementary metal-oxide-semiconductor technology, have high performance and good reliability. However, the inherent leakage in both SRAM and eDRAM hinders further improvement towards smaller feature sizes and higher energy efficiency. Although the emerging nonvolatile memories can eliminate the leakage efficiently, the penalties of lower speed and degraded reliability are significant. This article reveals a new opportunity towards leakage-free volatile static memory beyond the known paradigms of existing volatile and nonvolatile memories. By engineering a double-well energy landscape with the assistance of a clamping voltage bias, leakage-free and refresh-free state retention of volatile memory is achieved for the first time. This new memory is highlighted by both the ultra-low leakage of nonvolatile memories and the speed, energy, and reliability advantages of volatile memories. A proof-of-concept memory is demonstrated using in-house anti-ferroelectric field-effect transistors (AFeFETs), delivering an extrapolated endurance of about 1012 cycles, a retention time of over 10 years, and no subthreshold channel leakage current. Such a new concept of AFeFET-based memory enables an improved balance between density, power, and reliability beyond all existing memory solutions. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.04973v4-abstract-full').style.display = 'none'; document.getElementById('2212.04973v4-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 1 February, 2023; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 9 December, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2212.00089">arXiv:2212.00089</a> <span> [<a href="https://arxiv.org/pdf/2212.00089">pdf</a>, <a href="https://arxiv.org/format/2212.00089">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Xu%2C+Y">Yixin Xu</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Xiao%2C+Y">Yi Xiao</a>, <a href="/search/cs?searchtype=author&query=Yu%2C+T">Tongguang Yu</a>, <a href="/search/cs?searchtype=author&query=Mulaosmanovic%2C+H">Halid Mulaosmanovic</a>, <a href="/search/cs?searchtype=author&query=Kleimaier%2C+D">Dominik Kleimaier</a>, <a href="/search/cs?searchtype=author&query=Duenkel%2C+S">Stefan Duenkel</a>, <a href="/search/cs?searchtype=author&query=Beyer%2C+S">Sven Beyer</a>, <a href="/search/cs?searchtype=author&query=Gong%2C+X">Xiao Gong</a>, <a href="/search/cs?searchtype=author&query=Joshi%2C+R">Rajiv Joshi</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">X. Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Wen%2C+S">Shixian Wen</a>, <a href="/search/cs?searchtype=author&query=Rios%2C+A+S">Amanda Sofie Rios</a>, <a href="/search/cs?searchtype=author&query=Lekkala%2C+K">Kiran Lekkala</a>, <a href="/search/cs?searchtype=author&query=Itti%2C+L">Laurent Itti</a>, <a href="/search/cs?searchtype=author&query=Homan%2C+E">Eric Homan</a>, <a href="/search/cs?searchtype=author&query=George%2C+S">Sumitha George</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2212.00089v1-abstract-short" style="display: inline;"> Field Programmable Gate Array (FPGA) is widely used in acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the tradeoff between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. In this paper, we perfor… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.00089v1-abstract-full').style.display = 'inline'; document.getElementById('2212.00089v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2212.00089v1-abstract-full" style="display: none;"> Field Programmable Gate Array (FPGA) is widely used in acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the tradeoff between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. In this paper, we perform technology-circuit-architecture co-design to break this tradeoff with no additional area cost and lower power consumption compared with conventional designs while providing dynamic reconfiguration, which can hide the reconfiguration time behind the execution time. Leveraging the intrinsic transistor structure and non-volatility of ferroelectric FET (FeFET), compact FPGA primitives are proposed and experimentally verified, including 1FeFET look-up table (LUT) cell, 1FeFET routing cell for connection blocks (CBs) and switch boxes (SBs). To support dynamic reconfiguration, two local copies of primitives are placed in parallel, which enables loading of arbitrary configuration without interrupting the active configuration execution. A comprehensive evaluation shows that compared with the SRAM-based FPGA, our dynamic reconfiguration design shows 63.0%/71.1% reduction in LUT/CB area and 82.7%/53.6% reduction in CB/SB power consumption with minimal penalty in the critical path delay (9.6%). We further implement a Super-Sub network model to show the benefit from the context-switching capability of our design. We also evaluate the timing performance of our design over conventional FPGA in various application scenarios. In one scenario that users switch between two preloaded configurations, our design yields significant time saving by 78.7% on average. In the other scenario of implementing multiple configurations with dynamic reconfiguration, our design offers time saving of 20.3% on average. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2212.00089v1-abstract-full').style.display = 'none'; document.getElementById('2212.00089v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 30 November, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> December 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">54 pages, 15 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2211.01556">arXiv:2211.01556</a> <span> [<a href="https://arxiv.org/pdf/2211.01556">pdf</a>, <a href="https://arxiv.org/format/2211.01556">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> Ground Plane Matters: Picking Up Ground Plane Prior in Monocular 3D Object Detection </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yang%2C+F">Fan Yang</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+X">Xinhao Xu</a>, <a href="/search/cs?searchtype=author&query=Chen%2C+H">Hui Chen</a>, <a href="/search/cs?searchtype=author&query=Guo%2C+Y">Yuchen Guo</a>, <a href="/search/cs?searchtype=author&query=Han%2C+J">Jungong Han</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Ding%2C+G">Guiguang Ding</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2211.01556v1-abstract-short" style="display: inline;"> The ground plane prior is a very informative geometry clue in monocular 3D object detection (M3OD). However, it has been neglected by most mainstream methods. In this paper, we identify two key factors that limit the applicability of ground plane prior: the projection point localization issue and the ground plane tilt issue. To pick up the ground plane prior for M3OD, we propose a Ground Plane Enh… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2211.01556v1-abstract-full').style.display = 'inline'; document.getElementById('2211.01556v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2211.01556v1-abstract-full" style="display: none;"> The ground plane prior is a very informative geometry clue in monocular 3D object detection (M3OD). However, it has been neglected by most mainstream methods. In this paper, we identify two key factors that limit the applicability of ground plane prior: the projection point localization issue and the ground plane tilt issue. To pick up the ground plane prior for M3OD, we propose a Ground Plane Enhanced Network (GPENet) which resolves both issues at one go. For the projection point localization issue, instead of using the bottom vertices or bottom center of the 3D bounding box (BBox), we leverage the object's ground contact points, which are explicit pixels in the image and easy for the neural network to detect. For the ground plane tilt problem, our GPENet estimates the horizon line in the image and derives a novel mathematical expression to accurately estimate the ground plane equation. An unsupervised vertical edge mining algorithm is also proposed to address the occlusion of the horizon line. Furthermore, we design a novel 3D bounding box deduction method based on a dynamic back projection algorithm, which could take advantage of the accurate contact points and the ground plane equation. Additionally, using only M3OD labels, contact point and horizon line pseudo labels can be easily generated with NO extra data collection and label annotation cost. Extensive experiments on the popular KITTI benchmark show that our GPENet can outperform other methods and achieve state-of-the-art performance, well demonstrating the effectiveness and the superiority of the proposed approach. Moreover, our GPENet works better than other methods in cross-dataset evaluation on the nuScenes dataset. Our code and models will be published. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2211.01556v1-abstract-full').style.display = 'none'; document.getElementById('2211.01556v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 2 November, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">13 pages, 10 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2209.13685">arXiv:2209.13685</a> <span> [<a href="https://arxiv.org/pdf/2209.13685">pdf</a>, <a href="https://arxiv.org/format/2209.13685">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Hybrid Stochastic Synapses Enabled by Scaled Ferroelectric Field-effect Transistors </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Islam%2C+A+N+M+N">A N M Nafiul Islam</a>, <a href="/search/cs?searchtype=author&query=Saha%2C+A">Arnob Saha</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Sengupta%2C+A">Abhronil Sengupta</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2209.13685v3-abstract-short" style="display: inline;"> Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work we leverage the stochastic switching of a thr… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2209.13685v3-abstract-full').style.display = 'inline'; document.getElementById('2209.13685v3-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2209.13685v3-abstract-full" style="display: none;"> Achieving brain-like density and performance in neuromorphic computers necessitates scaling down the size of nanodevices emulating neuro-synaptic functionalities. However, scaling nanodevices results in reduction of programming resolution and emergence of stochastic non-idealities. While prior work has mainly focused on binary transitions, in this work we leverage the stochastic switching of a three-state ferroelectric field effect transistor (FeFET) to implement a long-term and short-term 2-tier stochastic synaptic memory with a single device. Experimental measurements are performed on a scaled 28nm high-$k$ metal gate technology-based device to develop a probabilistic model of the hybrid stochastic synapse. In addition to the advantage of ultra-low programming energies afforded by scaling, our hardware-algorithm co-design analysis reveals the efficacy of the 2-tier memory in comparison to binary stochastic synapses in on-chip learning tasks -- paving the way for algorithms exploiting multi-state devices with probabilistic transitions beyond deterministic ones. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2209.13685v3-abstract-full').style.display = 'none'; document.getElementById('2209.13685v3-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 10 March, 2023; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 27 September, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2209.11971">arXiv:2209.11971</a> <span> [<a href="https://arxiv.org/pdf/2209.11971">pdf</a>, <a href="https://arxiv.org/format/2209.11971">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Signal Processing">eess.SP</span> </div> </div> <p class="title is-5 mathjax"> A Homogeneous Processing Fabric for Matrix-Vector Multiplication and Associative Search Using Ferroelectric Time-Domain Compute-in-Memory </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Q">Qingrong Huang</a>, <a href="/search/cs?searchtype=author&query=M%C3%BCller%2C+F">Franz M眉ller</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Vardar%2C+A">Alptekin Vardar</a>, <a href="/search/cs?searchtype=author&query=De%2C+S">Sourav De</a>, <a href="/search/cs?searchtype=author&query=Jiang%2C+Z">Zhouhang Jiang</a>, <a href="/search/cs?searchtype=author&query=Imani%2C+M">Mohsen Imani</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2209.11971v1-abstract-short" style="display: inline;"> In this work, we propose a ferroelectric FET(FeFET) time-domain compute-in-memory (TD-CiM) array as a homogeneous processing fabric for binary multiplication-accumulation (MAC) and content addressable memory (CAM). We demonstrate that: i) the XOR(XNOR)/AND logic function can be realized using a single cell composed of 2FeFETs connected in series; ii) a two-phase computation in an inverter chain wi… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2209.11971v1-abstract-full').style.display = 'inline'; document.getElementById('2209.11971v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2209.11971v1-abstract-full" style="display: none;"> In this work, we propose a ferroelectric FET(FeFET) time-domain compute-in-memory (TD-CiM) array as a homogeneous processing fabric for binary multiplication-accumulation (MAC) and content addressable memory (CAM). We demonstrate that: i) the XOR(XNOR)/AND logic function can be realized using a single cell composed of 2FeFETs connected in series; ii) a two-phase computation in an inverter chain with each stage featuring the XOR/AND cell to control the associated capacitor loading and the computation results of binary MAC and CAM are reflected in the chain output signal delay, illustrating full digital compatibility; iii) comprehensive theoretical and experimental validation of the proposed 2FeFET cell and inverter delay chains and their robustness against FeFET variation; iv) the homogeneous processing fabric is applied in hyperdimensional computing to show dynamic and fine-grain resource allocation to accommodate different tasks requiring varying demands over the binary MAC and CAM resources. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2209.11971v1-abstract-full').style.display = 'none'; document.getElementById('2209.11971v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 24 September, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> September 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">8 pages, 8 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2208.14678">arXiv:2208.14678</a> <span> [<a href="https://arxiv.org/pdf/2208.14678">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> Ferroelectric FET-based strong physical unclonable function: a low-power, high-reliable and reconfigurable solution for Internet-of-Things security </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Guo%2C+X">Xinrui Guo</a>, <a href="/search/cs?searchtype=author&query=Ma%2C+X">Xiaoyang Ma</a>, <a href="/search/cs?searchtype=author&query=Muller%2C+F">Franz Muller</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Kampfe%2C+T">Thomas Kampfe</a>, <a href="/search/cs?searchtype=author&query=Liu%2C+Y">Yongpan Liu</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Li%2C+X">Xueqing Li</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2208.14678v1-abstract-short" style="display: inline;"> Hardware security has been a key concern in modern information technologies. Especially, as the number of Internet-of-Things (IoT) devices grows rapidly, to protect the device security with low-cost security primitives becomes essential, among which Physical Unclonable Function (PUF) is a widely-used solution. In this paper, we propose the first FeFET-based strong PUF exploiting the cycle-to-cycle… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2208.14678v1-abstract-full').style.display = 'inline'; document.getElementById('2208.14678v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2208.14678v1-abstract-full" style="display: none;"> Hardware security has been a key concern in modern information technologies. Especially, as the number of Internet-of-Things (IoT) devices grows rapidly, to protect the device security with low-cost security primitives becomes essential, among which Physical Unclonable Function (PUF) is a widely-used solution. In this paper, we propose the first FeFET-based strong PUF exploiting the cycle-to-cycle (C2C) variation of FeFETs as the entropy source. Based on the experimental measurements, the proposed PUF shows satisfying performance including high uniformity, uniqueness, reconfigurability and reliability. To resist machine-learning attack, XOR structure was introduced, and simulations show that our proposed PUF has similar resistance to existing attack models with traditional arbiter PUFs. Furthermore, our design is shown to be power-efficient, and highly robust to write voltage, temperature and device size, which makes it a competitive security solution for Internet-of-Things edge devices. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2208.14678v1-abstract-full').style.display = 'none'; document.getElementById('2208.14678v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 31 August, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2208.08611">arXiv:2208.08611</a> <span> [<a href="https://arxiv.org/pdf/2208.08611">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> </div> </div> <p class="title is-5 mathjax"> Intellectual Property Evaluation Utilizing Machine Learning </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Ding%2C+J">Jinxin Ding</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Y">Yuxin Huang</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Keyang Ni</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+X">Xueyao Wang</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+Y">Yinxiao Wang</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+Y">Yucheng Wang</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2208.08611v1-abstract-short" style="display: inline;"> Intellectual properties is increasingly important in the economic development. To solve the pain points by traditional methods in IP evaluation, we are developing a new technology with machine learning as the core. We have built an online platform and will expand our business in the Greater Bay Area with plans. </span> <span class="abstract-full has-text-grey-dark mathjax" id="2208.08611v1-abstract-full" style="display: none;"> Intellectual properties is increasingly important in the economic development. To solve the pain points by traditional methods in IP evaluation, we are developing a new technology with machine learning as the core. We have built an online platform and will expand our business in the Greater Bay Area with plans. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2208.08611v1-abstract-full').style.display = 'none'; document.getElementById('2208.08611v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 August, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">5 pages, 2 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2208.02613">arXiv:2208.02613</a> <span> [<a href="https://arxiv.org/pdf/2208.02613">pdf</a>, <a href="https://arxiv.org/format/2208.02613">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computer Vision and Pattern Recognition">cs.CV</span> </div> </div> <p class="title is-5 mathjax"> Semantic Interleaving Global Channel Attention for Multilabel Remote Sensing Image Classification </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Liu%2C+Y">Yongkun Liu</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kesong Ni</a>, <a href="/search/cs?searchtype=author&query=Zhang%2C+Y">Yuhan Zhang</a>, <a href="/search/cs?searchtype=author&query=Zhou%2C+L">Lijian Zhou</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+K">Kun Zhao</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2208.02613v2-abstract-short" style="display: inline;"> Multi-Label Remote Sensing Image Classification (MLRSIC) has received increasing research interest. Taking the cooccurrence relationship of multiple labels as additional information helps to improve the performance of this task. Current methods focus on using it to constrain the final feature output of a Convolutional Neural Network (CNN). On the one hand, these methods do not make full use of lab… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2208.02613v2-abstract-full').style.display = 'inline'; document.getElementById('2208.02613v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2208.02613v2-abstract-full" style="display: none;"> Multi-Label Remote Sensing Image Classification (MLRSIC) has received increasing research interest. Taking the cooccurrence relationship of multiple labels as additional information helps to improve the performance of this task. Current methods focus on using it to constrain the final feature output of a Convolutional Neural Network (CNN). On the one hand, these methods do not make full use of label correlation to form feature representation. On the other hand, they increase the label noise sensitivity of the system, resulting in poor robustness. In this paper, a novel method called Semantic Interleaving Global Channel Attention (SIGNA) is proposed for MLRSIC. First, the label co-occurrence graph is obtained according to the statistical information of the data set. The label co-occurrence graph is used as the input of the Graph Neural Network (GNN) to generate optimal feature representations. Then, the semantic features and visual features are interleaved, to guide the feature expression of the image from the original feature space to the semantic feature space with embedded label relations. SIGNA triggers global attention of feature maps channels in a new semantic feature space to extract more important visual features. Multihead SIGNA based feature adaptive weighting networks are proposed to act on any layer of CNN in a plug-and-play manner. For remote sensing images, better classification performance can be achieved by inserting CNN into the shallow layer. We conduct extensive experimental comparisons on three data sets: UCM data set, AID data set, and DFC15 data set. Experimental results demonstrate that the proposed SIGNA achieves superior classification performance compared to state-of-the-art (SOTA) methods. It is worth mentioning that the codes of this paper will be open to the community for reproducibility research. Our codes are available at https://github.com/kyle-one/SIGNA. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2208.02613v2-abstract-full').style.display = 'none'; document.getElementById('2208.02613v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 2 January, 2023; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 4 August, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">14 pages, 13 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2207.12188">arXiv:2207.12188</a> <span> [<a href="https://arxiv.org/pdf/2207.12188">pdf</a>, <a href="https://arxiv.org/format/2207.12188">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> COSIME: FeFET based Associative Memory for In-Memory Cosine Similarity Search </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Liu%2C+C">Che-Kai Liu</a>, <a href="/search/cs?searchtype=author&query=Chen%2C+H">Haobang Chen</a>, <a href="/search/cs?searchtype=author&query=Imani%2C+M">Mohsen Imani</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Kazemi%2C+A">Arman Kazemi</a>, <a href="/search/cs?searchtype=author&query=Laguna%2C+A+F">Ann Franchesca Laguna</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">Xiaobo Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+L">Liang Zhao</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2207.12188v1-abstract-short" style="display: inline;"> In a number of machine learning models, an input query is searched across the trained class vectors to find the closest feature class vector in cosine similarity metric. However, performing the cosine similarities between the vectors in Von-Neumann machines involves a large number of multiplications, Euclidean normalizations and division operations, thus incurring heavy hardware energy and latency… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2207.12188v1-abstract-full').style.display = 'inline'; document.getElementById('2207.12188v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2207.12188v1-abstract-full" style="display: none;"> In a number of machine learning models, an input query is searched across the trained class vectors to find the closest feature class vector in cosine similarity metric. However, performing the cosine similarities between the vectors in Von-Neumann machines involves a large number of multiplications, Euclidean normalizations and division operations, thus incurring heavy hardware energy and latency overheads. Moreover, due to the memory wall problem that presents in the conventional architecture, frequent cosine similarity-based searches (CSSs) over the class vectors requires a lot of data movements, limiting the throughput and efficiency of the system. To overcome the aforementioned challenges, this paper introduces COSIME, an general in-memory associative memory (AM) engine based on the ferroelectric FET (FeFET) device for efficient CSS. By leveraging the one-transistor AND gate function of FeFET devices, current-based translinear analog circuit and winner-take-all (WTA) circuitry, COSIME can realize parallel in-memory CSS across all the entries in a memory block, and output the closest word to the input query in cosine similarity metric. Evaluation results at the array level suggest that the proposed COSIME design achieves 333X and 90.5X latency and energy improvements, respectively, and realizes better classification accuracy when compared with an AM design implementing approximated CSS. The proposed in-memory computing fabric is evaluated for an HDC problem, showcasing that COSIME can achieve on average 47.1X and 98.5X speedup and energy efficiency improvements compared with an GPU implementation. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2207.12188v1-abstract-full').style.display = 'none'; document.getElementById('2207.12188v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 July, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> July 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted by the 41st International Conference on Computer Aided Design (ICCAD), San Diego, USA</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2205.14729">arXiv:2205.14729</a> <span> [<a href="https://arxiv.org/pdf/2205.14729">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Applied Physics">physics.app-ph</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Mallick%2C+A">Antik Mallick</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Bashar%2C+M+K">Mohammad Khairul Bashar</a>, <a href="/search/cs?searchtype=author&query=Alam%2C+S">Shamiul Alam</a>, <a href="/search/cs?searchtype=author&query=Islam%2C+M+M">Md Mazharul Islam</a>, <a href="/search/cs?searchtype=author&query=Xiao%2C+Y">Yi Xiao</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+Y">Yixin Xu</a>, <a href="/search/cs?searchtype=author&query=Aziz%2C+A">Ahmedullah Aziz</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Shukla%2C+N">Nikhil Shukla</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2205.14729v1-abstract-short" style="display: inline;"> Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2205.14729v1-abstract-full').style.display = 'inline'; document.getElementById('2205.14729v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2205.14729v1-abstract-full" style="display: none;"> Realizing compact and scalable Ising machines that are compatible with CMOS-process technology is crucial to the effectiveness and practicality of using such hardware platforms for accelerating computationally intractable problems. Besides the need for realizing compact Ising spins, the implementation of the coupling network, which describes the spin interaction, is also a potential bottleneck in the scalability of such platforms. Therefore, in this work, we propose an Ising machine platform that exploits the novel behavior of compact bi-stable CMOS-latches (cross-coupled inverters) as classical Ising spins interacting through highly scalable and CMOS-process compatible ferroelectric-HfO2-based Ferroelectric FETs (FeFETs) which act as coupling elements. We experimentally demonstrate the prototype building blocks of this system, and evaluate the behavior of the scaled system using simulations. We project that the proposed architecture can compute Ising solutions with an efficiency of ~1.04 x 10^8 solutions/W/second. Our work not only provides a pathway to realizing CMOS-compatible designs but also to overcoming their scaling challenges. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2205.14729v1-abstract-full').style.display = 'none'; document.getElementById('2205.14729v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 29 May, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">29 pages, 10 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2203.07948">arXiv:2203.07948</a> <span> [<a href="https://arxiv.org/pdf/2203.07948">pdf</a>, <a href="https://arxiv.org/format/2203.07948">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Signal Processing">eess.SP</span> </div> </div> <p class="title is-5 mathjax"> An Ultra-Compact Single FeFET Binary and Multi-Bit Associative Search Engine </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=M%C3%BCller%2C+F">Franz M眉ller</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Q">Qingrong Huang</a>, <a href="/search/cs?searchtype=author&query=Li%2C+C">Chao Li</a>, <a href="/search/cs?searchtype=author&query=Imani%2C+M">Mohsen Imani</a>, <a href="/search/cs?searchtype=author&query=Yang%2C+Z">Zeyu Yang</a>, <a href="/search/cs?searchtype=author&query=Cai%2C+J">Jiahao Cai</a>, <a href="/search/cs?searchtype=author&query=Lederer%2C+M">Maximilian Lederer</a>, <a href="/search/cs?searchtype=author&query=Olivo%2C+R">Ricardo Olivo</a>, <a href="/search/cs?searchtype=author&query=Laleni%2C+N">Nellie Laleni</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2203.07948v1-abstract-short" style="display: inline;"> Content addressable memory (CAM) is widely used in associative search tasks for its highly parallel pattern matching capability. To accommodate the increasingly complex and data-intensive pattern matching tasks, it is critical to keep improving the CAM density to enhance the performance and area efficiency. In this work, we demonstrate: i) a novel ultra-compact 1FeFET CAM design that enables paral… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2203.07948v1-abstract-full').style.display = 'inline'; document.getElementById('2203.07948v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2203.07948v1-abstract-full" style="display: none;"> Content addressable memory (CAM) is widely used in associative search tasks for its highly parallel pattern matching capability. To accommodate the increasingly complex and data-intensive pattern matching tasks, it is critical to keep improving the CAM density to enhance the performance and area efficiency. In this work, we demonstrate: i) a novel ultra-compact 1FeFET CAM design that enables parallel associative search and in-memory hamming distance calculation; ii) a multi-bit CAM for exact search using the same CAM cell; iii) compact device designs that integrate the series resistor current limiter into the intrinsic FeFET structure to turn the 1FeFET1R into an effective 1FeFET cell; iv) a successful 2-step search operation and a sufficient sensing margin of the proposed binary and multi-bit 1FeFET1R CAM array with sizes of practical interests in both experiments and simulations, given the existing unoptimized FeFET device variation; v) 89.9x speedup and 66.5x energy efficiency improvement over the state-of-the art alignment tools on GPU in accelerating genome pattern matching applications through the hyperdimensional computing paradigm. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2203.07948v1-abstract-full').style.display = 'none'; document.getElementById('2203.07948v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 15 March, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> March 2022. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">20 pages, 14 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2110.03855">arXiv:2110.03855</a> <span> [<a href="https://arxiv.org/pdf/2110.03855">pdf</a>, <a href="https://arxiv.org/format/2110.03855">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1038/s41467-022-29795-3">10.1038/s41467-022-29795-3 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> Hardware Functional Obfuscation With Ferroelectric Active Interconnects </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yu%2C+T">Tonggunag Yu</a>, <a href="/search/cs?searchtype=author&query=Xu%2C+Y">Yixin Xu</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Jao%2C+N">Nicolas Jao</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+Y+S">You Sung Kim</a>, <a href="/search/cs?searchtype=author&query=Duenkel%2C+S">Stefan Duenkel</a>, <a href="/search/cs?searchtype=author&query=Beyer%2C+S">Sven Beyer</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=George%2C+S">Sumitha George</a>, <a href="/search/cs?searchtype=author&query=Narayanan%2C+V">Vijaykrishnan Narayanan</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2110.03855v2-abstract-short" style="display: inline;"> Camouflaging gate techniques are typically used in hardware security to prevent reverse engineering. Layout level camouflaging by adding dummy contacts ensures some level of protection against extracting the correct netlist. Threshold voltage manipulation for multi-functional logic with identical layouts has also been introduced for functional obfuscation. All these techniques are implemented at t… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.03855v2-abstract-full').style.display = 'inline'; document.getElementById('2110.03855v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2110.03855v2-abstract-full" style="display: none;"> Camouflaging gate techniques are typically used in hardware security to prevent reverse engineering. Layout level camouflaging by adding dummy contacts ensures some level of protection against extracting the correct netlist. Threshold voltage manipulation for multi-functional logic with identical layouts has also been introduced for functional obfuscation. All these techniques are implemented at the expense of circuit-complexity and with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. The active interconnect provides run-time reconfigurable inverter-buffer logic by utilizing the threshold voltage programmability of the FeFETs. Our method utilizes only two FeFETs and an inverter to realize the masking function compared to recent reconfigurable logic gate implementations using several FeFETs and complex differential logic. We fabricate the proposed circuit and demonstrate the functionality. Judicious placement of the proposed logic in the IC makes it acts as a hardware encryption key and enables encoding and decoding of the functional output without affecting the critical path timing delay. Also, we achieve comparable encryption probability with a limited number of encryption units. In addition, we show a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic, hence obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.03855v2-abstract-full').style.display = 'none'; document.getElementById('2110.03855v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 April, 2022; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 7 October, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Journal ref:</span> Nat Commun 13, 2235 (2022) </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2110.02495">arXiv:2110.02495</a> <span> [<a href="https://arxiv.org/pdf/2110.02495">pdf</a>, <a href="https://arxiv.org/format/2110.02495">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Signal Processing">eess.SP</span> </div> </div> <p class="title is-5 mathjax"> Deep Random Forest with Ferroelectric Analog Content Addressable Memory </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=M%C3%BCller%2C+F">Franz M眉ller</a>, <a href="/search/cs?searchtype=author&query=Laguna%2C+A+F">Ann Franchesca Laguna</a>, <a href="/search/cs?searchtype=author&query=Li%2C+C">Chao Li</a>, <a href="/search/cs?searchtype=author&query=Ye%2C+W">Wenwen Ye</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Q">Qingrong Huang</a>, <a href="/search/cs?searchtype=author&query=Zhang%2C+Q">Qinming Zhang</a>, <a href="/search/cs?searchtype=author&query=Shi%2C+Z">Zhiguo Shi</a>, <a href="/search/cs?searchtype=author&query=Lederer%2C+M">Maximilian Lederer</a>, <a href="/search/cs?searchtype=author&query=Laleni%2C+N">Nellie Laleni</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">Xiaobo Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=K%C3%A4mpfe%2C+T">Thomas K盲mpfe</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2110.02495v1-abstract-short" style="display: inline;"> Deep random forest (DRF), which incorporates the core features of deep learning and random forest (RF), exhibits comparable classification accuracy, interpretability, and low memory and computational overhead when compared with deep neural networks (DNNs) in various information processing tasks for edge intelligence. However, the development of efficient hardware to accelerate DRF is lagging behin… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.02495v1-abstract-full').style.display = 'inline'; document.getElementById('2110.02495v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2110.02495v1-abstract-full" style="display: none;"> Deep random forest (DRF), which incorporates the core features of deep learning and random forest (RF), exhibits comparable classification accuracy, interpretability, and low memory and computational overhead when compared with deep neural networks (DNNs) in various information processing tasks for edge intelligence. However, the development of efficient hardware to accelerate DRF is lagging behind its DNN counterparts. The key for hardware acceleration of DRF lies in efficiently realizing the branch-split operation at decision nodes when traversing a decision tree. In this work, we propose to implement DRF through simple associative searches realized with ferroelectric analog content addressable memory (ACAM). Utilizing only two ferroelectric field effect transistors (FeFETs), the ultra-compact ACAM cell can perform a branch-split operation with an energy-efficient associative search by storing the decision boundaries as the analog polarization states in an FeFET. The DRF accelerator architecture and the corresponding mapping of the DRF model to the ACAM arrays are presented. The functionality, characteristics, and scalability of the FeFET ACAM based DRF and its robustness against FeFET device non-idealities are validated both in experiments and simulations. Evaluation results show that the FeFET ACAM DRF accelerator exhibits 10^6x/16x and 10^6x/2.5x improvements in terms of energy and latency when compared with other deep random forest hardware implementations on the state-of-the-art CPU/ReRAM, respectively. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2110.02495v1-abstract-full').style.display = 'none'; document.getElementById('2110.02495v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 6 October, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">44 pages, 16 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2107.13088">arXiv:2107.13088</a> <span> [<a href="https://arxiv.org/pdf/2107.13088">pdf</a>, <a href="https://arxiv.org/format/2107.13088">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1063/5.0064860">10.1063/5.0064860 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> Intrinsic synaptic plasticity of ferroelectric field effect transistors for online learning </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Saha%2C+A">Arnob Saha</a>, <a href="/search/cs?searchtype=author&query=Islam%2C+A+N+M+N">A N M Nafiul Islam</a>, <a href="/search/cs?searchtype=author&query=Zhao%2C+Z">Zijian Zhao</a>, <a href="/search/cs?searchtype=author&query=Deng%2C+S">Shan Deng</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Sengupta%2C+A">Abhronil Sengupta</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2107.13088v2-abstract-short" style="display: inline;"> Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. We provide… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2107.13088v2-abstract-full').style.display = 'inline'; document.getElementById('2107.13088v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2107.13088v2-abstract-full" style="display: none;"> Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. We provide experimental measurements of the synaptic characteristics for a $28nm$ high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performance prediction. Decoupled read-write paths, ultra-low programming energies and the possibility of arranging such devices in a cross-point architecture demonstrate the synaptic efficacy of the device. Our hardware-algorithm co-design analysis reveals that the intrinsic plasticity of the ferroelectric devices has potential to enable unsupervised local learning in edge devices with limited training data. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2107.13088v2-abstract-full').style.display = 'none'; document.getElementById('2107.13088v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 16 September, 2021; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 27 July, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> July 2021. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2106.11757">arXiv:2106.11757</a> <span> [<a href="https://arxiv.org/pdf/2106.11757">pdf</a>, <a href="https://arxiv.org/format/2106.11757">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Distributed, Parallel, and Cluster Computing">cs.DC</span> </div> </div> <p class="title is-5 mathjax"> Application-driven Design Exploration for Dense Ferroelectric Embedded Non-volatile Memories </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Sharifi%2C+M+M">Mohammad Mehdi Sharifi</a>, <a href="/search/cs?searchtype=author&query=Pentecost%2C+L">Lillian Pentecost</a>, <a href="/search/cs?searchtype=author&query=Rajaei%2C+R">Ramin Rajaei</a>, <a href="/search/cs?searchtype=author&query=Kazemi%2C+A">Arman Kazemi</a>, <a href="/search/cs?searchtype=author&query=Lou%2C+Q">Qiuwen Lou</a>, <a href="/search/cs?searchtype=author&query=Wei%2C+G">Gu-Yeon Wei</a>, <a href="/search/cs?searchtype=author&query=Brooks%2C+D">David Brooks</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">X. Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Donato%2C+M">Marco Donato</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2106.11757v1-abstract-short" style="display: inline;"> The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device cha… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2106.11757v1-abstract-full').style.display = 'inline'; document.getElementById('2106.11757v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2106.11757v1-abstract-full" style="display: none;"> The memory wall bottleneck is a key challenge across many data-intensive applications. Multi-level FeFET-based embedded non-volatile memories are a promising solution for denser and more energy-efficient on-chip memory. However, reliable multi-level cell storage requires careful optimizations to minimize the design overhead costs. In this work, we investigate the interplay between FeFET device characteristics, programming schemes, and memory array architecture, and explore different design choices to optimize performance, energy, area, and accuracy metrics for critical data-intensive workloads. From our cross-stack design exploration, we find that we can store DNN weights and social network graphs at a density of over 8MB/mm^2 and sub-2ns read access latency without loss in application accuracy. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2106.11757v1-abstract-full').style.display = 'none'; document.getElementById('2106.11757v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 June, 2021; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2021. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted at ISLPED 2021</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2010.07261">arXiv:2010.07261</a> <span> [<a href="https://arxiv.org/pdf/2010.07261">pdf</a>, <a href="https://arxiv.org/format/2010.07261">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computation and Language">cs.CL</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> </div> </div> <p class="title is-5 mathjax"> Learning Improvised Chatbots from Adversarial Modifications of Natural Language Feedback </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Sreedhar%2C+M+N">Makesh Narsimhan Sreedhar</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kun Ni</a>, <a href="/search/cs?searchtype=author&query=Reddy%2C+S">Siva Reddy</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2010.07261v2-abstract-short" style="display: inline;"> The ubiquitous nature of chatbots and their interaction with users generate an enormous amount of data. Can we improve chatbots using this data? A self-feeding chatbot improves itself by asking natural language feedback when a user is dissatisfied with its response and uses this feedback as an additional training sample. However, user feedback in most cases contains extraneous sequences hindering… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2010.07261v2-abstract-full').style.display = 'inline'; document.getElementById('2010.07261v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2010.07261v2-abstract-full" style="display: none;"> The ubiquitous nature of chatbots and their interaction with users generate an enormous amount of data. Can we improve chatbots using this data? A self-feeding chatbot improves itself by asking natural language feedback when a user is dissatisfied with its response and uses this feedback as an additional training sample. However, user feedback in most cases contains extraneous sequences hindering their usefulness as a training sample. In this work, we propose a generative adversarial model that converts noisy feedback into a plausible natural response in a conversation. The generator's goal is to convert the feedback into a response that answers the user's previous utterance and to fool the discriminator which distinguishes feedback from natural responses. We show that augmenting original training data with these modified feedback responses improves the original chatbot performance from 69.94% to 75.96% in ranking correct responses on the Personachat dataset, a large improvement given that the original model is already trained on 131k samples. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2010.07261v2-abstract-full').style.display = 'none'; document.getElementById('2010.07261v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 14 October, 2020; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 14 October, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2020. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted for publication at Findings of EMNLP 2020</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2004.01866">arXiv:2004.01866</a> <span> [<a href="https://arxiv.org/pdf/2004.01866">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/TED.2020.2994896">10.1109/TED.2020.2994896 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> FeCAM: A Universal Compact Digital and Analog Content Addressable Memory Using Ferroelectric </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Yin%2C+X">Xunzhao Yin</a>, <a href="/search/cs?searchtype=author&query=Li%2C+C">Chao Li</a>, <a href="/search/cs?searchtype=author&query=Huang%2C+Q">Qingrong Huang</a>, <a href="/search/cs?searchtype=author&query=Zhang%2C+L">Li Zhang</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">Xiaobo Sharon Hu</a>, <a href="/search/cs?searchtype=author&query=Zhuo%2C+C">Cheng Zhuo</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2004.01866v2-abstract-short" style="display: inline;"> Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other non-volatile memories (NVMs). Content Addressable Memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matchin… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2004.01866v2-abstract-full').style.display = 'inline'; document.getElementById('2004.01866v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2004.01866v2-abstract-full" style="display: none;"> Ferroelectric field effect transistors (FeFETs) are being actively investigated with the potential for in-memory computing (IMC) over other non-volatile memories (NVMs). Content Addressable Memories (CAMs) are a form of IMC that performs parallel searches for matched entries over a memory array for a given input query. CAMs are widely used for data-centric applications that involve pattern matching and search functionality. To accommodate the ever expanding data, it is attractive to resort to analog CAM for memory density improvement. However, the digital CAM design nowadays based on standard CMOS or emerging nonvolatile memories (e.g., resistive storage devices) is already challenging due to area, power, and cost penalties. Thus, it can be extremely expensive to achieve analog CAM with those technologies due to added cell components. As such, we propose, for the first time, a universal compact FeFET based CAM design, FeCAM, with search and storage functionality enabled in digital and analog domain simultaneously. By exploiting the multi-level-cell (MLC) states of FeFET, FeCAM can store and search inputs in either digital or analog domain. We perform a device-circuit co-design of the proposed FeCAM and validate its functionality and performance using an experimentally calibrated FeFET model. Circuit level simulation results demonstrate that FeCAM can either store continuous matching ranges or encode 3-bit data in a single CAM cell. When compared with the existing digital CMOS based CAM approaches, FeCAM is found to improve both memory density by 22.4X and energy saving by 8.6/3.2X for analog/digital modes, respectively. In the CAM-related application, our evaluations show that FeCAM can achieve 60.5X/23.1X saving in area/search energy compared with conventional CMOS based CAMs. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2004.01866v2-abstract-full').style.display = 'none'; document.getElementById('2004.01866v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 17 July, 2020; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 4 April, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2020. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">8 pages, 8 figures, accepted</span> </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Journal ref:</span> IEEE Transactions on Electron Devices, 2020 </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2004.00703">arXiv:2004.00703</a> <span> [<a href="https://arxiv.org/pdf/2004.00703">pdf</a>, <a href="https://arxiv.org/format/2004.00703">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Emerging Technologies">cs.ET</span> </div> </div> <p class="title is-5 mathjax"> A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Kazemi%2C+A">Arman Kazemi</a>, <a href="/search/cs?searchtype=author&query=Rajaei%2C+R">Ramin Rajaei</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Datta%2C+S">Suman Datta</a>, <a href="/search/cs?searchtype=author&query=Niemier%2C+M">Michael Niemier</a>, <a href="/search/cs?searchtype=author&query=Hu%2C+X+S">X. Sharon Hu</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2004.00703v1-abstract-short" style="display: inline;"> An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and non-volatile most significant bits (MSBs) used for both training and inference. The design works at a 1.8V logic-compatible voltage, provides 10^10 endurance cycles, and r… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2004.00703v1-abstract-full').style.display = 'inline'; document.getElementById('2004.00703v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2004.00703v1-abstract-full" style="display: none;"> An analog synapse circuit based on ferroelectric-metal field-effect transistors is proposed, that offers 6-bit weight precision. The circuit is comprised of volatile least significant bits (LSBs) used solely during training, and non-volatile most significant bits (MSBs) used for both training and inference. The design works at a 1.8V logic-compatible voltage, provides 10^10 endurance cycles, and requires only 250ps update pulses. A variant of LeNet trained with the proposed synapse achieves 98.2% accuracy on MNIST, which is only 0.4% lower than an ideal implementation of the same network with the same bit precision. Furthermore, the proposed synapse offers improvements of up to 26% in area, 44.8% in leakage power, 16.7% in LSB update pulse duration, and two orders of magnitude in endurance cycles, when compared to state-of-the-art hybrid synaptic circuits. Our proposed synapse can be extended to an 8-bit design, enabling a VGG-like network to achieve 88.8% accuracy on CIFAR-10 (only 0.8% lower than an ideal implementation of the same network). <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2004.00703v1-abstract-full').style.display = 'none'; document.getElementById('2004.00703v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 1 April, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2020. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Accepted at ISCAS'20 for oral presentation</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1911.10232">arXiv:1911.10232</a> <span> [<a href="https://arxiv.org/pdf/1911.10232">pdf</a>, <a href="https://arxiv.org/format/1911.10232">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Information Retrieval">cs.IR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">cs.LG</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Computation">stat.CO</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Machine Learning">stat.ML</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/BigData47090.2019.9005633">10.1109/BigData47090.2019.9005633 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> SWAG: Item Recommendations using Convolutions on Weighted Graphs </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Pande%2C+A">Amit Pande</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Kai Ni</a>, <a href="/search/cs?searchtype=author&query=Kini%2C+V">Venkataramani Kini</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1911.10232v1-abstract-short" style="display: inline;"> Recent advancements in deep neural networks for graph-structured data have led to state-of-the-art performance on recommender system benchmarks. In this work, we present a Graph Convolutional Network (GCN) algorithm SWAG (Sample Weight and AGgregate), which combines efficient random walks and graph convolutions on weighted graphs to generate embeddings for nodes (items) that incorporate both graph… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1911.10232v1-abstract-full').style.display = 'inline'; document.getElementById('1911.10232v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1911.10232v1-abstract-full" style="display: none;"> Recent advancements in deep neural networks for graph-structured data have led to state-of-the-art performance on recommender system benchmarks. In this work, we present a Graph Convolutional Network (GCN) algorithm SWAG (Sample Weight and AGgregate), which combines efficient random walks and graph convolutions on weighted graphs to generate embeddings for nodes (items) that incorporate both graph structure as well as node feature information such as item-descriptions and item-images. The three important SWAG operations that enable us to efficiently generate node embeddings based on graph structures are (a) Sampling of graph to homogeneous structure, (b) Weighting the sampling, walks and convolution operations, and (c) using AGgregation functions for generating convolutions. The work is an adaptation of graphSAGE over weighted graphs. We deploy SWAG at Target and train it on a graph of more than 500K products sold online with over 50M edges. Offline and online evaluations reveal the benefit of using a graph-based approach and the benefits of weighing to produce high quality embeddings and product recommendations. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1911.10232v1-abstract-full').style.display = 'none'; document.getElementById('1911.10232v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 22 November, 2019; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2019. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">10 pages, 8 figures, 2019 IEEE BigData special session</span> </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Journal ref:</span> 2019 IEEE International Conference on Big Data </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1806.10227">arXiv:1806.10227</a> <span> [<a href="https://arxiv.org/pdf/1806.10227">pdf</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Computers and Society">cs.CY</span> </div> </div> <p class="title is-5 mathjax"> The Determinants For User Intention To Adopt Web Based Early Childhood Supplementary Educational Platform </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Ni%2C+K+H">Khoo Han Ni</a>, <a href="/search/cs?searchtype=author&query=Baharudin%2C+A+S">Ahmad Suhaimi Baharudin</a>, <a href="/search/cs?searchtype=author&query=Karkonasasi%2C+K">Kamal Karkonasasi</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1806.10227v1-abstract-short" style="display: inline;"> Education is defined as the fundamental key for the success and development for any given society. Hence, the forming of a strong basic educational foundation is crucial to ensure the children to stay competitive and achieve extraordinary in the changing world. I-zLink Sdn. Bhd. is a partnership company that formed by four individuals with the commitment to develop an early childhood learning solu… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1806.10227v1-abstract-full').style.display = 'inline'; document.getElementById('1806.10227v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1806.10227v1-abstract-full" style="display: none;"> Education is defined as the fundamental key for the success and development for any given society. Hence, the forming of a strong basic educational foundation is crucial to ensure the children to stay competitive and achieve extraordinary in the changing world. I-zLink Sdn. Bhd. is a partnership company that formed by four individuals with the commitment to develop an early childhood learning solution named i-Future. The system, i-Future is a Supplementary Educational Platform that designs specially for children that fall between the age categories of two to six years which integrate with the latest technology to increase the engagement and flexibility in learning process as well as the effectiveness of study. In order to ensure that the system has a market value, an empirical study was conducted to determine the acceptance level and also the variables that would affect the user's intention to adopt i-Future. The variables used in the study include Perceived Ease of Use (PEU), Perceived Usefulness (PU), System Quality (SQ) and Social Norm (SN). Through the quantitative study, the relationship between these variables and user's intention to adopt i-Future was determined. Those variables which have significant impact on user's intention to adopt i-Future will be used to design i-Future. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1806.10227v1-abstract-full').style.display = 'none'; document.getElementById('1806.10227v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 26 June, 2018; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> June 2018. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1804.10669">arXiv:1804.10669</a> <span> [<a href="https://arxiv.org/pdf/1804.10669">pdf</a>, <a href="https://arxiv.org/format/1804.10669">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Sound">cs.SD</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Artificial Intelligence">cs.AI</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Audio and Speech Processing">eess.AS</span> </div> </div> <p class="title is-5 mathjax"> Deep Speech Denoising with Vector Space Projections </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Hetherly%2C+J">Jeff Hetherly</a>, <a href="/search/cs?searchtype=author&query=Gamble%2C+P">Paul Gamble</a>, <a href="/search/cs?searchtype=author&query=Barrios%2C+M">Maria Barrios</a>, <a href="/search/cs?searchtype=author&query=Stephenson%2C+C">Cory Stephenson</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Karl Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1804.10669v1-abstract-short" style="display: inline;"> We propose an algorithm to denoise speakers from a single microphone in the presence of non-stationary and dynamic noise. Our approach is inspired by the recent success of neural network models separating speakers from other speakers and singers from instrumental accompaniment. Unlike prior art, we leverage embedding spaces produced with source-contrastive estimation, a technique derived from nega… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1804.10669v1-abstract-full').style.display = 'inline'; document.getElementById('1804.10669v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1804.10669v1-abstract-full" style="display: none;"> We propose an algorithm to denoise speakers from a single microphone in the presence of non-stationary and dynamic noise. Our approach is inspired by the recent success of neural network models separating speakers from other speakers and singers from instrumental accompaniment. Unlike prior art, we leverage embedding spaces produced with source-contrastive estimation, a technique derived from negative sampling techniques in natural language processing, while simultaneously obtaining a continuous inference mask. Our embedding space directly optimizes for the discrimination of speaker and noise by jointly modeling their characteristics. This space is generalizable in that it is not speaker or noise specific and is capable of denoising speech even if the model has not seen the speaker in the training set. Parameters are trained with dual objectives: one that promotes a selective bandpass filter that eliminates noise at time-frequency positions that exceed signal power, and another that proportionally splits time-frequency content between signal and noise. We compare to state of the art algorithms as well as traditional sparse non-negative matrix factorization solutions. The resulting algorithm avoids severe computational burden by providing a more intuitive and easily optimized approach, while achieving competitive accuracy. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1804.10669v1-abstract-full').style.display = 'none'; document.getElementById('1804.10669v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 27 April, 2018; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2018. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">arXiv admin note: text overlap with arXiv:1705.04662</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/1804.05053">arXiv:1804.05053</a> <span> [<a href="https://arxiv.org/pdf/1804.05053">pdf</a>, <a href="https://arxiv.org/format/1804.05053">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Sound">cs.SD</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Audio and Speech Processing">eess.AS</span> </div> </div> <p class="title is-5 mathjax"> Voices Obscured in Complex Environmental Settings (VOICES) corpus </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Richey%2C+C">Colleen Richey</a>, <a href="/search/cs?searchtype=author&query=Barrios%2C+M+A">Maria A. Barrios</a>, <a href="/search/cs?searchtype=author&query=Armstrong%2C+Z">Zeb Armstrong</a>, <a href="/search/cs?searchtype=author&query=Bartels%2C+C">Chris Bartels</a>, <a href="/search/cs?searchtype=author&query=Franco%2C+H">Horacio Franco</a>, <a href="/search/cs?searchtype=author&query=Graciarena%2C+M">Martin Graciarena</a>, <a href="/search/cs?searchtype=author&query=Lawson%2C+A">Aaron Lawson</a>, <a href="/search/cs?searchtype=author&query=Nandwana%2C+M+K">Mahesh Kumar Nandwana</a>, <a href="/search/cs?searchtype=author&query=Stauffer%2C+A">Allen Stauffer</a>, <a href="/search/cs?searchtype=author&query=van+Hout%2C+J">Julien van Hout</a>, <a href="/search/cs?searchtype=author&query=Gamble%2C+P">Paul Gamble</a>, <a href="/search/cs?searchtype=author&query=Hetherly%2C+J">Jeff Hetherly</a>, <a href="/search/cs?searchtype=author&query=Stephenson%2C+C">Cory Stephenson</a>, <a href="/search/cs?searchtype=author&query=Ni%2C+K">Karl Ni</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="1804.05053v2-abstract-short" style="display: inline;"> This paper introduces the Voices Obscured In Complex Environmental Settings (VOICES) corpus, a freely available dataset under Creative Commons BY 4.0. This dataset will promote speech and signal processing research of speech recorded by far-field microphones in noisy room conditions. Publicly available speech corpora are mostly composed of isolated speech at close-range microphony. A typical appro… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1804.05053v2-abstract-full').style.display = 'inline'; document.getElementById('1804.05053v2-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="1804.05053v2-abstract-full" style="display: none;"> This paper introduces the Voices Obscured In Complex Environmental Settings (VOICES) corpus, a freely available dataset under Creative Commons BY 4.0. This dataset will promote speech and signal processing research of speech recorded by far-field microphones in noisy room conditions. Publicly available speech corpora are mostly composed of isolated speech at close-range microphony. A typical approach to better represent realistic scenarios, is to convolve clean speech with noise and simulated room response for model training. Despite these efforts, model performance degrades when tested against uncurated speech in natural conditions. For this corpus, audio was recorded in furnished rooms with background noise played in conjunction with foreground speech selected from the LibriSpeech corpus. Multiple sessions were recorded in each room to accommodate for all foreground speech-background noise combinations. Audio was recorded using twelve microphones placed throughout the room, resulting in 120 hours of audio per microphone. This work is a multi-organizational effort led by SRI International and Lab41 with the intent to push forward state-of-the-art distant microphone approaches in signal processing and speech recognition. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('1804.05053v2-abstract-full').style.display = 'none'; document.getElementById('1804.05053v2-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 15 May, 2018; <span class="has-text-black-bis has-text-weight-semibold">v1</span> submitted 13 April, 2018; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> April 2018. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">Submitted to Interspeech 2018</span> </p> </li> </ol> <nav class="pagination is-small is-centered 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