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class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Time delay between data read command and availability of data in a computer's RAM</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Original_research plainlinks metadata ambox ambox-content ambox-Original_research" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/40px-Ambox_important.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/60px-Ambox_important.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/80px-Ambox_important.svg.png 2x" data-file-width="40" data-file-height="40" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>possibly contains <a href="/wiki/Wikipedia:No_original_research" title="Wikipedia:No original research">original research</a></b>.<span class="hide-when-compact"> Please <a class="external text" href="https://en.wikipedia.org/w/index.php?title=CAS_latency&action=edit">improve it</a> by <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verifying</a> the claims made and adding <a href="/wiki/Wikipedia:Citing_sources#Inline_citations" title="Wikipedia:Citing sources">inline citations</a>. Statements consisting only of original research should be removed.</span> <span class="date-container"><i>(<span class="date">July 2019</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p><b>Column address strobe latency</b>, also called <b>CAS latency</b> or <b>CL</b>, is the delay in clock cycles between the READ command and the moment data is available.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-umd_2-0" class="reference"><a href="#cite_note-umd-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> In asynchronous <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">DRAM</a>, the interval is specified in nanoseconds (absolute time).<sup id="cite_ref-async_3-0" class="reference"><a href="#cite_note-async-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> In <a href="/wiki/Synchronous_dynamic_random-access_memory" title="Synchronous dynamic random-access memory">synchronous DRAM</a>, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of absolute time, the actual time for an <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> module to respond to a CAS event might vary between uses of the same module if the clock rate differs. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="RAM_operation_background">RAM operation background</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=1" title="Edit section: RAM operation background"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/DRAM#Principles_of_operation" class="mw-redirect" title="DRAM">DRAM § Principles of operation</a></div> <p>Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal <i>word line</i>. Sending a logical high signal along a given row enables the <a href="/wiki/MOSFET" title="MOSFET">MOSFETs</a> present in that row, connecting each storage capacitor to its corresponding vertical <i>bit line</i>. Each bit line is connected to a <i>sense amplifier</i> that amplifies the small voltage change produced by the storage capacitor. This amplified signal is then output from the DRAM chip as well as driven back up the bit line to <i>refresh</i> the row. </p><p>When no word line is active, the array is idle and the bit lines are held in a precharged<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> state, with a voltage halfway between high and low. This indeterminate signal is deflected towards high or low by the storage capacitor when a row is made active. </p><p>To access memory, a row must first be selected and loaded into the sense amplifiers. This row is then <i>active,</i> and columns may be accessed for read or write. </p><p>The CAS latency is the delay between the time at which the column address and the <i>column address strobe</i> signal are presented to the memory module and the time at which the corresponding data is made available by the memory module. The desired row must already be active; if it is not, additional time is required. </p><p>As an example, a typical 1 <a href="/wiki/Gibibyte" class="mw-redirect" title="Gibibyte">GiB</a> <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> memory module might contain eight separate one-<a href="/wiki/Gibibit" class="mw-redirect" title="Gibibit">gibibit</a> DRAM chips, each offering 128 <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> of storage space. Each chip is divided internally into eight banks of 2<sup>27</sup>=128 <a href="/wiki/Mebibit" class="mw-redirect" title="Mebibit">Mibits</a>, each of which composes a separate DRAM array. Each bank contains 2<sup>14</sup>=16384 rows of 2<sup>13</sup>=8192 bits each. One byte of memory (from each chip; 64 bits total from the whole DIMM) is accessed by supplying a 3-bit bank number, a 14-bit row address, and a 13-bit column address.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (April 2021)">citation needed</span></a></i>]</sup> </p> <div class="mw-heading mw-heading2"><h2 id="Effect_on_memory_access_speed">Effect on memory access speed</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=2" title="Edit section: Effect on memory access speed"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1251242444" /><table class="box-More_citations_needed_section plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">verification</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/CAS_latency" title="Special:EditPage/CAS latency">improve this article</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a> in this section. Unsourced material may be challenged and removed.</span> <span class="date-container"><i>(<span class="date">September 2020</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>With asynchronous DRAM, memory was accessed by a memory controller on the memory bus based on a set timing rather than a clock, and was separate from the system bus.<sup id="cite_ref-async_3-1" class="reference"><a href="#cite_note-async-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">Synchronous DRAM</a>, however, has a CAS latency that is dependent upon the clock rate. Accordingly, the CAS latency of an <a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> memory module is specified in clock ticks instead of absolute time.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (August 2019)">citation needed</span></a></i>]</sup> </p><p>Because memory modules have multiple internal banks, and data can be output from one during access latency for another, the output pins can be kept 100% busy regardless of the CAS latency through <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipelining</a>; the maximum attainable <a href="/wiki/Bandwidth_(computing)" title="Bandwidth (computing)">bandwidth</a> is determined solely by the clock speed. Unfortunately, this maximum bandwidth can only be attained if the address of the data to be read is known long enough in advance; if the address of the data being accessed is not predictable, <a href="/wiki/Pipeline_stall" title="Pipeline stall">pipeline stalls</a> can occur, resulting in a loss of bandwidth. For a completely unknown memory access (AKA Random access), the relevant latency is the time to close any open row, plus the time to open the desired row, followed by the CAS latency to read data from it. Due to <a href="/wiki/Locality_of_reference" title="Locality of reference">spatial locality</a>, however, it is common to access several words in the same row. In this case, the CAS latency alone determines the elapsed time. </p><p>Because modern <a href="/wiki/DRAM" class="mw-redirect" title="DRAM">DRAM</a> modules' CAS latencies are specified in clock ticks instead of time, when comparing latencies at different clock speeds, latencies must be translated into absolute times to make a fair comparison; a higher numerical CAS latency may still be less time if the clock is faster. Likewise, a memory module which is <a href="/wiki/Underclocked" class="mw-redirect" title="Underclocked">underclocked</a> could have its CAS latency cycle count reduced to preserve the same CAS latency time.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (October 2020)">citation needed</span></a></i>]</sup> </p><p><a href="/wiki/Double_data_rate" title="Double data rate">Double data rate</a> (DDR) <a href="/wiki/RAM" class="mw-redirect" title="RAM">RAM</a> performs two transfers per clock cycle, and it is usually described by this transfer rate. Because the CAS latency is specified in clock cycles, and not transfers (which occur on both the rising and falling edges of the clock), it is important to ensure it is the clock rate (half of the transfer rate) which is being used to compute CAS latency times.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (October 2020)">citation needed</span></a></i>]</sup> </p><p>Another complicating factor is the use of burst transfers. A modern microprocessor might have a <a href="/wiki/Cache_line" class="mw-redirect" title="Cache line">cache line</a> size of 64 bytes, requiring eight transfers from a 64-bit-wide (eight bytes) memory to fill. The CAS latency can only accurately measure the time to transfer the first word of memory; the time to transfer all eight words depends on the data transfer rate as well. Fortunately, the processor typically does not need to wait for all eight words; the burst is usually sent in <i>critical word first</i> order, and the first critical word can be used by the microprocessor immediately. </p><p>In the table below, data rates are given in million transfers—also known as <a href="/wiki/Megatransfer" class="mw-redirect" title="Megatransfer">megatransfers</a>—per second (MT/s), while clock rates are given in MHz, million cycles per second. </p> <div class="mw-heading mw-heading3"><h3 id="Memory_timing_examples">Memory timing examples</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=3" title="Edit section: Memory timing examples"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable sortable"> <caption>Memory timing examples (CAS latency only)<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="I suspect the source of this table is from the Google Sheets Document in the external links below, which is self reported and therefore violates Wikipedia:No original research, and is unverifiable. (July 2019)">citation needed</span></a></i>]</sup><sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:No_original_research" title="Wikipedia:No original research"><span title="The material near this tag possibly contains original research. (December 2019)">original research?</span></a></i>]</sup> </caption> <tbody><tr> <th scope="col">Generation </th> <th scope="col">Type </th> <th scope="col" data-sort-type="number">Data rate </th> <th scope="col" data-sort-type="number">Transfer time<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> </th> <th scope="col" data-sort-type="number">Command rate<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> </th> <th scope="col" data-sort-type="number">Cycle time<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> </th> <th scope="col">CAS latency </th> <th scope="col" data-sort-type="number">First word<sup id="cite_ref-nthword_8-0" class="reference"><a href="#cite_note-nthword-8"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </th> <th scope="col" data-sort-type="number">Fourth word<sup id="cite_ref-nthword_8-1" class="reference"><a href="#cite_note-nthword-8"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </th> <th scope="col" data-sort-type="number">Eighth word<sup id="cite_ref-nthword_8-2" class="reference"><a href="#cite_note-nthword-8"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <th scope="row" rowspan="2"><a href="/wiki/SDRAM" class="mw-redirect" title="SDRAM">SDRAM</a> </th> <td>PC100 </td> <td align="right">100 MT/s </td> <td align="right">10.000 ns </td> <td align="right">100 MHz </td> <td align="right">10.000 ns </td> <td align="center">2 </td> <td align="right">20.00 ns </td> <td align="right">50.00 ns </td> <td align="right">90.00 ns </td></tr> <tr> <td>PC133 </td> <td align="right">133 MT/s </td> <td align="right">7.500 ns </td> <td align="right">133 MHz </td> <td align="right">7.500 ns </td> <td align="center">3 </td> <td align="right">22.50 ns </td> <td align="right">45.00 ns </td> <td align="right">75.00 ns </td></tr> <tr> <th scope="row" rowspan="4"><a href="/wiki/DDR_SDRAM" title="DDR SDRAM">DDR SDRAM</a> </th> <td rowspan="1">DDR-333 </td> <td rowspan="1" align="right">333 MT/s </td> <td rowspan="1" align="right">3.000 ns </td> <td rowspan="1" align="right">166 MHz </td> <td rowspan="1" align="right">6.000 ns </td> <td align="center">2.5 </td> <td align="right">15.00 ns </td> <td align="right">24.00 ns </td> <td align="right">36.00 ns </td></tr> <tr> <td rowspan="3">DDR-400 </td> <td rowspan="3" align="right">400 MT/s </td> <td rowspan="3" align="right">2.500 ns </td> <td rowspan="3" align="right">200 MHz </td> <td rowspan="3" align="right">5.000 ns </td> <td align="center">3 </td> <td align="right">15.00 ns </td> <td align="right">22.50 ns </td> <td align="right">32.50 ns </td></tr> <tr> <td align="center">2.5 </td> <td align="right">12.50 ns </td> <td align="right">20.00 ns </td> <td align="right">30.00 ns </td></tr> <tr> <td align="center">2 </td> <td align="right">10.00 ns </td> <td align="right">17.50 ns </td> <td align="right">27.50 ns </td></tr> <tr> <th scope="row" rowspan="15"><a href="/wiki/DDR2_SDRAM" title="DDR2 SDRAM">DDR2 SDRAM</a> </th> <td rowspan="2">DDR2-400 </td> <td rowspan="2" align="right">400 MT/s </td> <td rowspan="2" align="right">2.500 ns </td> <td rowspan="2" align="right">200 MHz </td> <td rowspan="2" align="right">5.000 ns </td> <td align="center">4 </td> <td align="right">20.00 ns </td> <td align="right">27.50 ns </td> <td align="right">37.50 ns </td></tr> <tr> <td align="center">3 </td> <td align="right">15.00 ns </td> <td align="right">22.50 ns </td> <td align="right">32.50 ns </td></tr> <tr> <td rowspan="2">DDR2-533 </td> <td rowspan="2" align="right">533 MT/s </td> <td rowspan="2" align="right">1.875 ns </td> <td rowspan="2" align="right">266 MHz </td> <td rowspan="2" align="right">3.750 ns </td> <td align="center">4 </td> <td align="right">15.00 ns </td> <td align="right">20.63 ns </td> <td align="right">28.13 ns </td></tr> <tr> <td align="center">3 </td> <td align="right">11.25 ns </td> <td align="right">16.88 ns </td> <td align="right">24.38 ns </td></tr> <tr> <td rowspan="2">DDR2-667 </td> <td rowspan="2" align="right">667 MT/s </td> <td rowspan="2" align="right">1.500 ns </td> <td rowspan="2" align="right">333 MHz </td> <td rowspan="2" align="right">3.000 ns </td> <td align="center">5 </td> <td align="right">15.00 ns </td> <td align="right">19.50 ns </td> <td align="right">25.50 ns </td></tr> <tr> <td align="center">4 </td> <td align="right">12.00 ns </td> <td align="right">16.50 ns </td> <td align="right">22.50 ns </td></tr> <tr> <td rowspan="4">DDR2-800 </td> <td rowspan="4" align="right">800 MT/s </td> <td rowspan="4" align="right">1.250 ns </td> <td rowspan="4" align="right">400 MHz </td> <td rowspan="4" align="right">2.500 ns </td> <td align="center">6 </td> <td align="right">15.00 ns </td> <td align="right">18.75 ns </td> <td align="right">23.75 ns </td></tr> <tr> <td align="center">5 </td> <td align="right">12.50 ns </td> <td align="right">16.25 ns </td> <td align="right">21.25 ns </td></tr> <tr> <td align="center">4.5 </td> <td align="right">11.25 ns </td> <td align="right">15.00 ns </td> <td align="right">20.00 ns </td></tr> <tr> <td align="center">4 </td> <td align="right">10.00 ns </td> <td align="right">13.75 ns </td> <td align="right">18.75 ns </td></tr> <tr> <td rowspan="5">DDR2-1066 </td> <td rowspan="5" align="right">1066 MT/s </td> <td rowspan="5" align="right">0.938 ns </td> <td rowspan="5" align="right">533 MHz </td> <td rowspan="5" align="right">1.875 ns </td> <td align="center">7 </td> <td align="right">13.13 ns </td> <td align="right">15.94 ns </td> <td align="right">19.69 ns </td></tr> <tr> <td align="center">6 </td> <td align="right">11.25 ns </td> <td align="right">14.06 ns </td> <td align="right">17.81 ns </td></tr> <tr> <td align="center">5 </td> <td align="right">9.38 ns </td> <td align="right">12.19 ns </td> <td align="right">15.94 ns </td></tr> <tr> <td align="center">4.5 </td> <td align="right">8.44 ns </td> <td align="right">11.25 ns </td> <td align="right">15.00 ns </td></tr> <tr> <td align="center">4 </td> <td align="right">7.50 ns </td> <td align="right">10.31 ns </td> <td align="right">14.06 ns </td></tr> <tr> <th scope="row" rowspan="41"><a href="/wiki/DDR3_SDRAM" title="DDR3 SDRAM">DDR3 SDRAM</a> </th> <td rowspan="1">DDR3-1066 </td> <td rowspan="1" align="right">1066 MT/s </td> <td rowspan="1" align="right">0.938 ns </td> <td rowspan="1" align="right">533 MHz </td> <td rowspan="1" align="right">1.875 ns </td> <td align="center">7 </td> <td align="right">13.13 ns </td> <td align="right">15.94 ns </td> <td align="right">19.69 ns </td></tr> <tr> <td rowspan="4">DDR3-1333 </td> <td rowspan="4" align="right">1333 MT/s </td> <td rowspan="4" align="right">0.750 ns </td> <td rowspan="4" align="right">666 MHz </td> <td rowspan="4" align="right">1.500 ns </td> <td align="center">9 </td> <td align="right">13.50 ns </td> <td align="right">15.75 ns </td> <td align="right">18.75 ns </td></tr> <tr> <td align="center">8 </td> <td align="right">12.00 ns </td> <td align="right">14.25 ns </td> <td align="right">17.25 ns </td></tr> <tr> <td align="center">7 </td> <td align="right">10.50 ns </td> <td align="right">12.75 ns </td> <td align="right">15.75 ns </td></tr> <tr> <td align="center">6 </td> <td align="right">9.00 ns </td> <td align="right">11.25 ns </td> <td align="right">14.25 ns </td></tr> <tr> <td rowspan="1">DDR3-1375 </td> <td rowspan="1" align="right">1375 MT/s </td> <td rowspan="1" align="right">0.727 ns </td> <td rowspan="1" align="right">687 MHz </td> <td rowspan="1" align="right">1.455 ns </td> <td align="center">5 </td> <td align="right">7.27 ns </td> <td align="right">9.45 ns </td> <td align="right">12.36 ns </td></tr> <tr> <td rowspan="6">DDR3-1600 </td> <td rowspan="6" align="right">1600 MT/s </td> <td rowspan="6" align="right">0.625 ns </td> <td rowspan="6" align="right">800 MHz </td> <td rowspan="6" align="right">1.250 ns </td> <td align="center">11 </td> <td align="right">13.75 ns </td> <td align="right">15.63 ns </td> <td align="right">18.13 ns </td></tr> <tr> <td align="center">10 </td> <td align="right">12.50 ns </td> <td align="right">14.38 ns </td> <td align="right">16.88 ns </td></tr> <tr> <td align="center">9 </td> <td align="right">11.25 ns </td> <td align="right">13.13 ns </td> <td align="right">15.63 ns </td></tr> <tr> <td align="center">8 </td> <td align="right">10.00 ns </td> <td align="right">11.88 ns </td> <td align="right">14.38 ns </td></tr> <tr> <td align="center">7 </td> <td align="right">8.75 ns </td> <td align="right">10.63 ns </td> <td align="right">13.13 ns </td></tr> <tr> <td align="center">6 </td> <td align="right">7.50 ns </td> <td align="right">9.38 ns </td> <td align="right">11.88 ns </td></tr> <tr> <td rowspan="3">DDR3-1866 </td> <td rowspan="3" align="right">1866 MT/s </td> <td rowspan="3" align="right">0.536 ns </td> <td rowspan="3" align="right">933 MHz </td> <td rowspan="3" align="right">1.071 ns </td> <td align="center">10 </td> <td align="right">10.71 ns </td> <td align="right">12.32 ns </td> <td align="right">14.46 ns </td></tr> <tr> <td align="center">9 </td> <td align="right">9.64 ns </td> <td align="right">11.25 ns </td> <td align="right">13.39 ns </td></tr> <tr> <td align="center">8 </td> <td align="right">8.57 ns </td> <td align="right">10.18 ns </td> <td align="right">12.32 ns </td></tr> <tr> <td rowspan="1">DDR3-2000 </td> <td rowspan="1" align="right">2000 MT/s </td> <td rowspan="1" align="right">0.500 ns </td> <td rowspan="1" align="right">1000 MHz </td> <td rowspan="1" align="right">1.000 ns </td> <td align="center">9 </td> <td align="right">9.00 ns </td> <td align="right">10.50 ns </td> <td align="right">12.50 ns </td></tr> <tr> <td rowspan="6">DDR3-2133 </td> <td rowspan="6" align="right">2133 MT/s </td> <td rowspan="6" align="right">0.469 ns </td> <td rowspan="6" align="right">1066 MHz </td> <td rowspan="6" align="right">0.938 ns </td> <td align="center">12 </td> <td align="right">11.25 ns </td> <td align="right">12.66 ns </td> <td align="right">14.53 ns </td></tr> <tr> <td align="center">11 </td> <td align="right">10.31 ns </td> <td align="right">11.72 ns </td> <td align="right">13.59 ns </td></tr> <tr> <td align="center">10 </td> <td align="right">9.38 ns </td> <td align="right">10.78 ns </td> <td align="right">12.66 ns </td></tr> <tr> <td align="center">9 </td> <td align="right">8.44 ns </td> <td align="right">9.84 ns </td> <td align="right">11.72 ns </td></tr> <tr> <td align="center">8 </td> <td align="right">7.50 ns </td> <td align="right">8.91 ns </td> <td align="right">10.78 ns </td></tr> <tr> <td align="center">7 </td> <td align="right">6.56 ns </td> <td align="right">7.97 ns </td> <td align="right">9.84 ns </td></tr> <tr> <td rowspan="1">DDR3-2200 </td> <td rowspan="1" align="right">2200 MT/s </td> <td rowspan="1" align="right">0.455 ns </td> <td rowspan="1" align="right">1100 MHz </td> <td rowspan="1" align="right">0.909 ns </td> <td align="center">7 </td> <td align="right">6.36 ns </td> <td align="right">7.73 ns </td> <td align="right">9.55 ns </td></tr> <tr> <td rowspan="5">DDR3-2400 </td> <td rowspan="5" align="right">2400 MT/s </td> <td rowspan="5" align="right">0.417 ns </td> <td rowspan="5" align="right">1200 MHz </td> <td rowspan="5" align="right">0.833 ns </td> <td align="center">13 </td> <td align="right">10.83 ns </td> <td align="right">12.08 ns </td> <td align="right">13.75 ns </td></tr> <tr> <td align="center">12 </td> <td align="right">10.00 ns </td> <td align="right">11.25 ns </td> <td align="right">12.92 ns </td></tr> <tr> <td align="center">11 </td> <td align="right">9.17 ns </td> <td align="right">10.42 ns </td> <td align="right">12.08 ns </td></tr> <tr> <td align="center">10 </td> <td align="right">8.33 ns </td> <td align="right">9.58 ns </td> <td align="right">11.25 ns </td></tr> <tr> <td align="center">9 </td> <td align="right">7.50 ns </td> <td align="right">8.75 ns </td> <td align="right">10.42 ns </td></tr> <tr> <td rowspan="1">DDR3-2600 </td> <td rowspan="1" align="right">2600 MT/s </td> <td rowspan="1" align="right">0.385 ns </td> <td rowspan="1" align="right">1300 MHz </td> <td rowspan="1" align="right">0.769 ns </td> <td align="center">11 </td> <td align="right">8.46 ns </td> <td align="right">9.62 ns </td> <td align="right">11.15 ns </td></tr> <tr> <td rowspan="4">DDR3-2666 </td> <td rowspan="4" align="right">2666 MT/s </td> <td rowspan="4" align="right">0.375 ns </td> <td rowspan="4" align="right">1333 MHz </td> <td rowspan="4" align="right">0.750 ns </td> <td align="center">15 </td> <td align="right">11.25 ns </td> <td align="right">12.38 ns </td> <td align="right">13.88 ns </td></tr> <tr> <td align="center">13 </td> <td align="right">9.75 ns </td> <td align="right">10.88 ns </td> <td align="right">12.38 ns </td></tr> <tr> <td align="center">12 </td> <td align="right">9.00 ns </td> <td align="right">10.13 ns </td> <td align="right">11.63 ns </td></tr> <tr> <td align="center">11 </td> <td align="right">8.25 ns </td> <td align="right">9.38 ns </td> <td align="right">10.88 ns </td></tr> <tr> <td rowspan="3">DDR3-2800 </td> <td rowspan="3" align="right">2800 MT/s </td> <td rowspan="3" align="right">0.357 ns </td> <td rowspan="3" align="right">1400 MHz </td> <td rowspan="3" align="right">0.714 ns </td> <td align="center">16 </td> <td align="right">11.43 ns </td> <td align="right">12.50 ns </td> <td align="right">13.93 ns </td></tr> <tr> <td align="center">12 </td> <td align="right">8.57 ns </td> <td align="right">9.64 ns </td> <td align="right">11.07 ns </td></tr> <tr> <td align="center">11 </td> <td align="right">7.86 ns </td> <td align="right">8.93 ns </td> <td align="right">10.36 ns </td></tr> <tr> <td rowspan="1">DDR3-2933 </td> <td rowspan="1" align="right">2933 MT/s </td> <td rowspan="1" align="right">0.341 ns </td> <td rowspan="1" align="right">1466 MHz </td> <td rowspan="1" align="right">0.682 ns </td> <td align="center">12 </td> <td align="right">8.18 ns </td> <td align="right">9.20 ns </td> <td align="right">10.57 ns </td></tr> <tr> <td rowspan="1">DDR3-3000 </td> <td rowspan="1" align="right">3000 MT/s </td> <td rowspan="1" align="right">0.333 ns </td> <td rowspan="1" align="right">1500 MHz </td> <td rowspan="1" align="right">0.667 ns </td> <td align="center">12 </td> <td align="right">8.00 ns </td> <td align="right">9.00 ns </td> <td align="right">10.33 ns </td></tr> <tr> <td rowspan="1">DDR3-3100 </td> <td rowspan="1" align="right">3100 MT/s </td> <td rowspan="1" align="right">0.323 ns </td> <td rowspan="1" align="right">1550 MHz </td> <td rowspan="1" align="right">0.645 ns </td> <td align="center">12 </td> <td align="right">7.74 ns </td> <td align="right">8.71 ns </td> <td align="right">10.00 ns </td></tr> <tr> <td rowspan="1">DDR3-3200 </td> <td rowspan="1" align="right">3200 MT/s </td> <td rowspan="1" align="right">0.313 ns </td> <td rowspan="1" align="right">1600 MHz </td> <td rowspan="1" align="right">0.625 ns </td> <td align="center">16 </td> <td align="right">10.00 ns </td> <td align="right">10.94 ns </td> <td align="right">12.19 ns </td></tr> <tr> <td rowspan="1">DDR3-3300 </td> <td rowspan="1" align="right">3300 MT/s </td> <td rowspan="1" align="right">0.303 ns </td> <td rowspan="1" align="right">1650 MHz </td> <td rowspan="1" align="right">0.606 ns </td> <td align="center">16 </td> <td align="right">9.70 ns </td> <td align="right">10.61 ns </td> <td align="right">11.82 ns </td></tr> <tr> <th scope="row" rowspan="63"><a href="/wiki/DDR4_SDRAM" title="DDR4 SDRAM">DDR4 SDRAM</a> </th></tr> <tr> <td rowspan="3">DDR4-1600 </td> <td rowspan="3" align="right">1600 MT/s </td> <td rowspan="3" align="right">0.625 ns </td> <td rowspan="3" align="right">800 MHz </td> <td rowspan="3" align="right">1.250 ns </td> <td align="center">12 </td> <td align="right">15.00 ns </td> <td align="right">16.88 ns </td> <td align="right">19.38 ns </td></tr> <tr> <td align="center">11 </td> <td align="right">13.75 ns </td> <td align="right">15.63 ns </td> <td align="right">18.13 ns </td></tr> <tr> <td align="center">10 </td> <td align="right">12.50 ns </td> <td align="right">14.38 ns </td> <td align="right">16.88 ns </td></tr> <tr> <td rowspan="3">DDR4-1866 </td> <td rowspan="3" align="right">1866 MT/s </td> <td rowspan="3" align="right">0.536 ns </td> <td rowspan="3" align="right">933 MHz </td> <td rowspan="3" align="right">1.071 ns </td> <td align="center">14 </td> <td align="right">15.00 ns </td> <td align="right">16.61 ns </td> <td align="right">18.75 ns </td></tr> <tr> <td align="center">13 </td> <td align="right">13.93 ns </td> <td align="right">15.54 ns </td> <td align="right">17.68 ns </td></tr> <tr> <td align="center">12 </td> <td align="right">12.86 ns </td> <td align="right">14.46 ns </td> <td align="right">16.61 ns </td></tr> <tr> <td rowspan="3">DDR4-2133 </td> <td rowspan="3" align="right">2133 MT/s </td> <td rowspan="3" align="right">0.469 ns </td> <td rowspan="3" align="right">1066 MHz </td> <td rowspan="3" align="right">0.938 ns </td> <td align="center">16 </td> <td align="right">15.00 ns </td> <td align="right">16.41 ns </td> <td align="right">18.28 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">14.06 ns </td> <td align="right">15.47 ns </td> <td align="right">17.34 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">13.13 ns </td> <td align="right">14.53 ns </td> <td align="right">16.41 ns </td></tr> <tr> <td rowspan="3">DDR4-2400 </td> <td rowspan="3" align="right">2400 MT/s </td> <td rowspan="3" align="right">0.417 ns </td> <td rowspan="3" align="right">1200 MHz </td> <td rowspan="3" align="right">0.833 ns </td> <td align="center">17 </td> <td align="right">14.17 ns </td> <td align="right">15.42 ns </td> <td align="right">17.08 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">13.33 ns </td> <td align="right">14.58 ns </td> <td align="right">16.25 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">12.50 ns </td> <td align="right">13.75 ns </td> <td align="right">15.42 ns </td></tr> <tr> <td rowspan="5">DDR4-2666 </td> <td rowspan="5" align="right">2666 MT/s </td> <td rowspan="5" align="right">0.375 ns </td> <td rowspan="5" align="right">1333 MHz </td> <td rowspan="5" align="right">0.750 ns </td> <td align="center">19 </td> <td align="right">14.25 ns </td> <td align="right">15.38 ns </td> <td align="right">16.88 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">12.75 ns </td> <td align="right">13.88 ns </td> <td align="right">15.38 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">12.00 ns </td> <td align="right">13.13 ns </td> <td align="right">14.63 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">11.25 ns </td> <td align="right">12.38 ns </td> <td align="right">13.88 ns </td></tr> <tr> <td align="center">13 </td> <td align="right">9.75 ns </td> <td align="right">10.88 ns </td> <td align="right">12.38 ns </td></tr> <tr> <td rowspan="4">DDR4-2800 </td> <td rowspan="4" align="right">2800 MT/s </td> <td rowspan="4" align="right">0.357 ns </td> <td rowspan="4" align="right">1400 MHz </td> <td rowspan="4" align="right">0.714 ns </td> <td align="center">17 </td> <td align="right">12.14 ns </td> <td align="right">13.21 ns </td> <td align="right">14.64 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">11.43 ns </td> <td align="right">12.50 ns </td> <td align="right">13.93 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">10.71 ns </td> <td align="right">11.79 ns </td> <td align="right">13.21 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">10.00 ns </td> <td align="right">11.07 ns </td> <td align="right">12.50 ns </td></tr> <tr> <td rowspan="4">DDR4-3000 </td> <td rowspan="4" align="right">3000 MT/s </td> <td rowspan="4" align="right">0.333 ns </td> <td rowspan="4" align="right">1500 MHz </td> <td rowspan="4" align="right">0.667 ns </td> <td align="center">17 </td> <td align="right">11.33 ns </td> <td align="right">12.33 ns </td> <td align="right">13.67 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">10.67 ns </td> <td align="right">11.67 ns </td> <td align="right">13.00 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">10.00 ns </td> <td align="right">11.00 ns </td> <td align="right">12.33 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">9.33 ns </td> <td align="right">10.33 ns </td> <td align="right">11.67 ns </td></tr> <tr> <td rowspan="3">DDR4-3200 </td> <td rowspan="3" align="right">3200 MT/s </td> <td rowspan="3" align="right">0.313 ns </td> <td rowspan="3" align="right">1600 MHz </td> <td rowspan="3" align="right">0.625 ns </td> <td align="center">16 </td> <td align="right">10.00 ns </td> <td align="right">10.94 ns </td> <td align="right">12.19 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">9.38 ns </td> <td align="right">10.31 ns </td> <td align="right">11.56 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">8.75 ns </td> <td align="right">9.69 ns </td> <td align="right">10.94 ns </td></tr> <tr> <td rowspan="1">DDR4-3300 </td> <td rowspan="1" align="right">3300 MT/s </td> <td rowspan="1" align="right">0.303 ns </td> <td rowspan="1" align="right">1650 MHz </td> <td rowspan="1" align="right">0.606 ns </td> <td align="center">16 </td> <td align="right">9.70 ns </td> <td align="right">10.61 ns </td> <td align="right">11.82 ns </td></tr> <tr> <td rowspan="1">DDR4-3333 </td> <td rowspan="1" align="right">3333 MT/s </td> <td rowspan="1" align="right">0.300 ns </td> <td rowspan="1" align="right">1666 MHz </td> <td rowspan="1" align="right">0.600 ns </td> <td align="center">16 </td> <td align="right">9.60 ns </td> <td align="right">10.50 ns </td> <td align="right">11.70 ns </td></tr> <tr> <td rowspan="2">DDR4-3400 </td> <td rowspan="2" align="right">3400 MT/s </td> <td rowspan="2" align="right">0.294 ns </td> <td rowspan="2" align="right">1700 MHz </td> <td rowspan="2" align="right">0.588 ns </td> <td align="center">16 </td> <td align="right">9.41 ns </td> <td align="right">10.29 ns </td> <td align="right">11.47 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">8.24 ns </td> <td align="right">9.12 ns </td> <td align="right">10.29 ns </td></tr> <tr> <td rowspan="3">DDR4-3466 </td> <td rowspan="3" align="right">3466 MT/s </td> <td rowspan="3" align="right">0.288 ns </td> <td rowspan="3" align="right">1733 MHz </td> <td rowspan="3" align="right">0.577 ns </td> <td align="center">18 </td> <td align="right">10.38 ns </td> <td align="right">11.25 ns </td> <td align="right">12.40 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">9.81 ns </td> <td align="right">10.67 ns </td> <td align="right">11.83 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">9.23 ns </td> <td align="right">10.10 ns </td> <td align="right">11.25 ns </td></tr> <tr> <td rowspan="2">DDR4-3533 </td> <td rowspan="2" align="right">3533 MT/s </td> <td rowspan="2" align="right">0.283 ns </td> <td rowspan="2" align="right">1766 MHz </td> <td rowspan="2" align="right">0.566 ns </td> <td align="center">16 </td> <td align="right">9.06 ns </td> <td align="right">9.91 ns </td> <td align="right">11.04 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">8.49 ns </td> <td align="right">9.34 ns </td> <td align="right">10.47 ns </td></tr> <tr> <td rowspan="6">DDR4-3600 </td> <td rowspan="6" align="right">3600 MT/s </td> <td rowspan="6" align="right">0.278 ns </td> <td rowspan="6" align="right">1800 MHz </td> <td rowspan="6" align="right">0.556 ns </td> <td align="center">19 </td> <td align="right">10.56 ns </td> <td align="right">11.39 ns </td> <td align="right">12.50 ns </td></tr> <tr> <td align="center">18 </td> <td align="right">10.00 ns </td> <td align="right">10.83 ns </td> <td align="right">11.94 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">9.44 ns </td> <td align="right">10.28 ns </td> <td align="right">11.39 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">8.89 ns </td> <td align="right">9.72 ns </td> <td align="right">10.83 ns </td></tr> <tr> <td align="center">15 </td> <td align="right">8.33 ns </td> <td align="right">9.17 ns </td> <td align="right">10.28 ns </td></tr> <tr> <td align="center">14 </td> <td align="right">7.78 ns </td> <td align="right">8.61 ns </td> <td align="right">9.72 ns </td></tr> <tr> <td rowspan="1">DDR4-3733 </td> <td rowspan="1" align="right">3733 MT/s </td> <td rowspan="1" align="right">0.268 ns </td> <td rowspan="1" align="right">1866 MHz </td> <td rowspan="1" align="right">0.536 ns </td> <td align="center">17 </td> <td align="right">9.11 ns </td> <td align="right">9.91 ns </td> <td align="right">10.98 ns </td></tr> <tr> <td rowspan="1">DDR4-3866 </td> <td rowspan="1" align="right">3866 MT/s </td> <td rowspan="1" align="right">0.259 ns </td> <td rowspan="1" align="right">1933 MHz </td> <td rowspan="1" align="right">0.517 ns </td> <td align="center">18 </td> <td align="right">9.31 ns </td> <td align="right">10.09 ns </td> <td align="right">11.12 ns </td></tr> <tr> <td rowspan="4">DDR4-4000 </td> <td rowspan="4" align="right">4000 MT/s </td> <td rowspan="4" align="right">0.250 ns </td> <td rowspan="4" align="right">2000 MHz </td> <td rowspan="4" align="right">0.500 ns </td> <td align="center">19 </td> <td align="right">9.50 ns </td> <td align="right">10.25 ns </td> <td align="right">11.25 ns </td></tr> <tr> <td align="center">18 </td> <td align="right">9.00 ns </td> <td align="right">9.75 ns </td> <td align="right">10.75 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">8.50 ns </td> <td align="right">9.25 ns </td> <td align="right">10.25 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">8.00 ns </td> <td align="right">8.75 ns </td> <td align="right">9.75 ns </td></tr> <tr> <td rowspan="1">DDR4-4133 </td> <td rowspan="1" align="right">4133 MT/s </td> <td rowspan="1" align="right">0.242 ns </td> <td rowspan="1" align="right">2066 MHz </td> <td rowspan="1" align="right">0.484 ns </td> <td align="center">19 </td> <td align="right">9.19 ns </td> <td align="right">9.92 ns </td> <td align="right">10.89 ns </td></tr> <tr> <td rowspan="1">DDR4-4200 </td> <td rowspan="1" align="right">4200 MT/s </td> <td rowspan="1" align="right">0.238 ns </td> <td rowspan="1" align="right">2100 MHz </td> <td rowspan="1" align="right">0.476 ns </td> <td align="center">19 </td> <td align="right">9.05 ns </td> <td align="right">9.76 ns </td> <td align="right">10.71 ns </td></tr> <tr> <td rowspan="4">DDR4-4266 </td> <td rowspan="4" align="right">4266 MT/s </td> <td rowspan="4" align="right">0.234 ns </td> <td rowspan="4" align="right">2133 MHz </td> <td rowspan="4" align="right">0.469 ns </td> <td align="center">19 </td> <td align="right">8.91 ns </td> <td align="right">9.61 ns </td> <td align="right">10.55 ns </td></tr> <tr> <td align="center">18 </td> <td align="right">8.44 ns </td> <td align="right">9.14 ns </td> <td align="right">10.08 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">7.97 ns </td> <td align="right">8.67 ns </td> <td align="right">9.61 ns </td></tr> <tr> <td align="center">16 </td> <td align="right">7.50 ns </td> <td align="right">8.20 ns </td> <td align="right">9.14 ns </td></tr> <tr> <td rowspan="3">DDR4-4400 </td> <td rowspan="3" align="right">4400 MT/s </td> <td rowspan="3" align="right">0.227 ns </td> <td rowspan="3" align="right">2200 MHz </td> <td rowspan="3" align="right">0.454 ns </td> <td align="center">19 </td> <td align="right">8.64 ns </td> <td align="right">9.32 ns </td> <td align="right">10.23 ns </td></tr> <tr> <td align="center">18 </td> <td align="right">8.18 ns </td> <td align="right">8.86 ns </td> <td align="right">9.77 ns </td></tr> <tr> <td align="center">17 </td> <td align="right">7.73 ns </td> <td align="right">8.41 ns </td> <td align="right">9.32 ns </td></tr> <tr> <td rowspan="2">DDR4-4600 </td> <td rowspan="2" align="right">4600 MT/s </td> <td rowspan="2" align="right">0.217 ns </td> <td rowspan="2" align="right">2300 MHz </td> <td rowspan="2" align="right">0.435 ns </td> <td align="center">19 </td> <td align="right">8.26 ns </td> <td align="right">8.91 ns </td> <td align="right">9.78 ns </td></tr> <tr> <td align="center">18 </td> <td align="right">7.82 ns </td> <td align="right">8.48 ns </td> <td align="right">9.35 ns </td></tr> <tr> <td rowspan="2">DDR4-4800 </td> <td rowspan="2" align="right">4800 MT/s </td> <td rowspan="2" align="right">0.208 ns </td> <td rowspan="2" align="right">2400 MHz </td> <td rowspan="2" align="right">0.417 ns </td> <td align="center">20 </td> <td align="right">8.33 ns </td> <td align="right">8.96 ns </td> <td align="right">9.79 ns </td></tr> <tr> <td align="center">19 </td> <td align="right">7.92 ns </td> <td align="right">8.54 ns </td> <td align="right">9.38 ns </td></tr> <tr> <th scope="row" rowspan="28"><a href="/wiki/DDR5_SDRAM" title="DDR5 SDRAM">DDR5 SDRAM</a> </th></tr> <tr> <td rowspan="4">DDR5-4800 </td> <td rowspan="4" align="right">4800 MT/s </td> <td rowspan="4" align="right">0.208 ns </td> <td rowspan="4" align="right">2400 MHz </td> <td rowspan="4" align="right">0.417 ns </td> <td align="center">40 </td> <td align="right">16.67 ns </td> <td align="right">17.29 ns </td> <td align="right">18.13 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">15.83 ns </td> <td align="right">16.46 ns </td> <td align="right">17.29 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">15.00 ns </td> <td align="right">15.63 ns </td> <td align="right">16.46 ns </td></tr> <tr> <td align="center">34 </td> <td align="right">14.17 ns </td> <td align="right">14.79 ns </td> <td align="right">15.63 ns </td></tr> <tr> <td rowspan="4">DDR5-5200 </td> <td rowspan="4" align="right">5200 MT/s </td> <td rowspan="4" align="right">0.192 ns </td> <td rowspan="4" align="right">2600 MHz </td> <td rowspan="4" align="right">0.385 ns </td> <td align="center">40 </td> <td align="right">15.38 ns </td> <td align="right">15.96 ns </td> <td align="right">16.73 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">14.62 ns </td> <td align="right">15.19 ns </td> <td align="right">15.96 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">13.85 ns </td> <td align="right">14.42 ns </td> <td align="right">15.19 ns </td></tr> <tr> <td align="center">34 </td> <td align="right">13.08 ns </td> <td align="right">13.65 ns </td> <td align="right">14.42 ns </td></tr> <tr> <td rowspan="5">DDR5-5600 </td> <td rowspan="5" align="right">5600 MT/s </td> <td rowspan="5" align="right">0.179 ns </td> <td rowspan="5" align="right">2800 MHz </td> <td rowspan="5" align="right">0.357 ns </td> <td align="center">40 </td> <td align="right">14.29 ns </td> <td align="right">14.82 ns </td> <td align="right">15.54 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">13.57 ns </td> <td align="right">14.11 ns </td> <td align="right">14.82 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">12.86 ns </td> <td align="right">13.39 ns </td> <td align="right">14.11 ns </td></tr> <tr> <td align="center">34 </td> <td align="right">12.14 ns </td> <td align="right">12.68 ns </td> <td align="right">13.39 ns </td></tr> <tr> <td align="center">30 </td> <td align="right">10.71 ns </td> <td align="right">11.25 ns </td> <td align="right">11.96 ns </td></tr> <tr> <td rowspan="5">DDR5-6000 </td> <td rowspan="5" align="right">6000 MT/s </td> <td rowspan="5" align="right">0.167 ns </td> <td rowspan="5" align="right">3000 MHz </td> <td rowspan="5" align="right">0.333 ns </td> <td align="center">40 </td> <td align="right">13.33 ns </td> <td align="right">13.83 ns </td> <td align="right">14.50 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">12.67 ns </td> <td align="right">13.17 ns </td> <td align="right">13.83 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">12.00 ns </td> <td align="right">12.50 ns </td> <td align="right">13.17 ns </td></tr> <tr> <td align="center">32 </td> <td align="right">10.67 ns </td> <td align="right">11.17 ns </td> <td align="right">11.83 ns </td></tr> <tr> <td align="center">30 </td> <td align="right">10.00 ns </td> <td align="right">10.50 ns </td> <td align="right">11.17 ns </td></tr> <tr> <td rowspan="3">DDR5-6200 </td> <td rowspan="3" align="right">6200 MT/s </td> <td rowspan="3" align="right">0.161 ns </td> <td rowspan="3" align="right">3100 MHz </td> <td rowspan="3" align="right">0.323 ns </td> <td align="center">40 </td> <td align="right">12.90 ns </td> <td align="right">13.39 ns </td> <td align="right">14.03 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">12.26 ns </td> <td align="right">12.74 ns </td> <td align="right">13.39 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">11.61 ns </td> <td align="right">12.10 ns </td> <td align="right">12.74 ns </td></tr> <tr> <td rowspan="5">DDR5-6400 </td> <td rowspan="5" align="right">6400 MT/s </td> <td rowspan="5" align="right">0.156 ns </td> <td rowspan="5" align="right">3200 MHz </td> <td rowspan="5" align="right">0.313 ns </td> <td align="center">40 </td> <td align="right">12.50 ns </td> <td align="right">12.97 ns </td> <td align="right">13.59 ns </td></tr> <tr> <td align="center">38 </td> <td align="right">11.88 ns </td> <td align="right">12.34 ns </td> <td align="right">12.97 ns </td></tr> <tr> <td align="center">36 </td> <td align="right">11.25 ns </td> <td align="right">11.72 ns </td> <td align="right">12.34 ns </td></tr> <tr> <td align="center">34 </td> <td align="right">10.63 ns </td> <td align="right">11.09 ns </td> <td align="right">11.72 ns </td></tr> <tr> <td align="center">32 </td> <td align="right">10.00 ns </td> <td align="right">10.47 ns </td> <td align="right">11.09 ns </td></tr> <tr> <td rowspan="1">DDR5-6600 </td> <td rowspan="1" align="right">6600 MT/s </td> <td rowspan="1" align="right">0.152 ns </td> <td rowspan="1" align="right">3300 MHz </td> <td rowspan="1" align="right">0.303 ns </td> <td align="center">34 </td> <td align="right">10.30 ns </td> <td align="right">10.76 ns </td> <td align="right">11.36 ns </td></tr> <tr> <th scope="col">Generation </th> <th scope="col">Type </th> <th scope="col">Data rate </th> <th scope="col">Transfer time </th> <th scope="col">Command rate </th> <th scope="col">Cycle time </th> <th scope="col">CAS latency </th> <th scope="col">First word </th> <th scope="col">Fourth word </th> <th scope="col">Eighth word </th></tr></tbody></table> <div class="mw-heading mw-heading4"><h4 id="Notes">Notes</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=4" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text">Transfer time = 1 / Data rate.</span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text">Command rate = Data rate / 2 for double data rate (DDR), Command rate = Data rate for single data rate (SDR).</span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text">Cycle time = 1 / Command rate = 2 × Transfer time.</span> </li> <li id="cite_note-nthword-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-nthword_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-nthword_8-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-nthword_8-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><i>N</i>th word = [(2 × CAS latency) + (N − 1)] × Transfer time.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=5" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Memory_timings" title="Memory timings">Memory timings</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=6" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626" /><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFStokes1998–2004" class="citation web cs1">Stokes, Jon "Hannibal" (1998–2004). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20121101003215if_/http://archive.arstechnica.com:80/paedia/r/ram_guide/ram_guide.part2-5.html">"Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM"</a>. Ars Technica. Archived from <a rel="nofollow" class="external text" href="http://archive.arstechnica.com/paedia/r/ram_guide/ram_guide.part2-5.html">the original</a> on 2012-11-01.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Ars+Technica+RAM+Guide+Part+II%3A+Asynchronous+and+Synchronous+DRAM&rft.pub=Ars+Technica&rft.date=1998%2F2004&rft.aulast=Stokes&rft.aufirst=Jon+%22Hannibal%22&rft_id=http%3A%2F%2Farchive.arstechnica.com%2Fpaedia%2Fr%2Fram_guide%2Fram_guide.part2-5.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACAS+latency" class="Z3988"></span></span> </li> <li id="cite_note-umd-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-umd_2-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFJacob2002" class="citation cs2">Jacob, Bruce L. (December 10, 2002), <a rel="nofollow" class="external text" href="https://user.eng.umd.edu/~blj/CS-590.26/references/DRAM-Systems.pdf"><i>Synchronous DRAM Architectures, Organizations, and Alternative Technologies</i></a> <span class="cs1-format">(PDF)</span>, University of Maryland</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Synchronous+DRAM+Architectures%2C+Organizations%2C+and+Alternative+Technologies&rft.pub=University+of+Maryland&rft.date=2002-12-10&rft.aulast=Jacob&rft.aufirst=Bruce+L.&rft_id=https%3A%2F%2Fuser.eng.umd.edu%2F~blj%2FCS-590.26%2Freferences%2FDRAM-Systems.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACAS+latency" class="Z3988"></span></span> </li> <li id="cite_note-async-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-async_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-async_3-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://support.hpe.com/hpsc/doc/public/display?docId=emr_na-c01552458"><i>Memory technology evolution: an overview of system memory technologies</i></a>, HP, July 2008</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Memory+technology+evolution%3A+an+overview+of+system+memory+technologies&rft.pub=HP&rft.date=2008-07&rft_id=https%3A%2F%2Fsupport.hpe.com%2Fhpsc%2Fdoc%2Fpublic%2Fdisplay%3FdocId%3Demr_na-c01552458&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACAS+latency" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222" /><cite id="CITEREFKeethBakerJohnsonLin2007" class="citation book cs1">Keeth, Brent; Baker, R. Jacob; Johnson, Brian; Lin, Feng (December 4, 2007). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=TgW3LTubREQC"><i>DRAM Circuit Design: Fundamental and High-Speed Topics</i></a>. John Wiley & Sons. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0470184752" title="Special:BookSources/978-0470184752"><bdi>978-0470184752</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=DRAM+Circuit+Design%3A+Fundamental+and+High-Speed+Topics&rft.pub=John+Wiley+%26+Sons&rft.date=2007-12-04&rft.isbn=978-0470184752&rft.aulast=Keeth&rft.aufirst=Brent&rft.au=Baker%2C+R.+Jacob&rft.au=Johnson%2C+Brian&rft.au=Lin%2C+Feng&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DTgW3LTubREQC&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACAS+latency" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=CAS_latency&action=edit&section=7" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b>Google Sheet:</b> <a rel="nofollow" class="external text" href="https://docs.google.com/spreadsheets/d/1NUcp5ICqiPHfr_uw1zmV_44QazuvsSjjTu-H4KyVfpg/edit?usp=sharing">User-entered Memory Timing Comparisons and Memory timing examples (CAS latency only)</a></li> <li><b>Google Sheet:</b> <a rel="nofollow" class="external text" href="https://docs.google.com/spreadsheets/d/1aNUuLCWCjbbuB255mDsG47RpT2LU9dSgEMW9kQe9gL0/edit?usp=sharing">DDR4 RAM Actual Timings Full Comparison Grid</a></li> <li><a rel="nofollow" class="external text" href="http://www.pcstats.com/articleview.cfm?articleID=873"><i>PCSTATS: Memory Bandwidth vs. Latency Timings</i></a></li> <li><a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/ups-downs,743-3.html"><i>How Memory Access Works</i></a></li> <li><a rel="nofollow" class="external text" href="http://www.tomshardware.com/reviews/tight-timings-high-clock-frequencies,1236.html">Tom's Hardware Guide: <i>Tight Timings vs High Clock Frequencies</i></a></li> <li><a rel="nofollow" class="external text" href="http://www.hardwaresecrets.com/understanding-ram-timings/"><i>Understanding RAM Timings</i></a></li> <li><a rel="nofollow" class="external text" href="http://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask"><i>AnandTech: Everything You Always Wanted To Know About SDRAM Memory But Were Afraid To Ask</i></a></li></ul>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?useformat=desktop&type=1x1&usesul3=0" alt="" width="1" height="1" style="border: none; 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