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id="toc-Technical_factors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Advantages" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Advantages"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Advantages</span> </div> </a> <ul id="toc-Advantages-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Disadvantages" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Disadvantages"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.4</span> <span>Disadvantages</span> </div> </a> <ul id="toc-Disadvantages-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Hardware" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Hardware"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Hardware</span> </div> </a> <button aria-controls="toc-Hardware-sublist" class="cdx-button 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class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Software effects</span> </div> </a> <button aria-controls="toc-Software_effects-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Software effects subsection</span> </button> <ul id="toc-Software_effects-sublist" class="vector-toc-list"> <li id="toc-Licensing" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Licensing"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Licensing</span> </div> </a> <ul id="toc-Licensing-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Embedded_applications" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Embedded_applications"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Embedded applications</span> </div> </a> <ul id="toc-Embedded_applications-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Network_processors" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Network_processors"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Network processors</span> </div> </a> <ul id="toc-Network_processors-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Digital_signal_processing" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Digital_signal_processing"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Digital signal processing</span> </div> </a> <ul id="toc-Digital_signal_processing-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Heterogeneous_systems" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Heterogeneous_systems"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Heterogeneous systems</span> </div> </a> <ul id="toc-Heterogeneous_systems-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Hardware_examples" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Hardware_examples"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Hardware examples</span> </div> </a> <button aria-controls="toc-Hardware_examples-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Hardware examples subsection</span> </button> <ul id="toc-Hardware_examples-sublist" class="vector-toc-list"> <li id="toc-Commercial" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Commercial"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1</span> <span>Commercial</span> </div> </a> <ul id="toc-Commercial-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Free" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Free"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.2</span> <span>Free</span> </div> </a> <ul id="toc-Free-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Academic" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Academic"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.3</span> <span>Academic</span> </div> </a> <ul id="toc-Academic-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Benchmarks" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Benchmarks"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Benchmarks</span> </div> </a> <ul id="toc-Benchmarks-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Multi-core processor</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 30 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-30" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">30 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%85%D8%B9%D8%A7%D9%84%D8%AC_%D9%85%D8%AA%D8%B9%D8%AF%D8%AF_%D8%A7%D9%84%D9%86%D9%88%D9%89" title="معالج متعدد النوى – Arabic" lang="ar" hreflang="ar" data-title="معالج متعدد النوى" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%9C%D0%BD%D0%BE%D0%B3%D0%BE%D1%8F%D0%B4%D1%80%D0%B5%D0%BD_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Многоядрен процесор – Bulgarian" lang="bg" hreflang="bg" data-title="Многоядрен процесор" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Processador_Multinucli" title="Processador Multinucli – Catalan" lang="ca" hreflang="ca" data-title="Processador Multinucli" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/V%C3%ADcej%C3%A1drov%C3%BD_procesor" title="Vícejádrový procesor – Czech" lang="cs" hreflang="cs" data-title="Vícejádrový procesor" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/Flerkernet_processor" title="Flerkernet processor – Danish" lang="da" hreflang="da" data-title="Flerkernet processor" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Mehrkernprozessor" title="Mehrkernprozessor – German" lang="de" hreflang="de" data-title="Mehrkernprozessor" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Mitmetuumaline_protsessor" title="Mitmetuumaline protsessor – Estonian" lang="et" hreflang="et" data-title="Mitmetuumaline protsessor" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Procesador_multin%C3%BAcleo" title="Procesador multinúcleo – Spanish" lang="es" hreflang="es" data-title="Procesador multinúcleo" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%BE%D8%B1%D8%AF%D8%A7%D8%B2%D9%86%D8%AF%D9%87_%DA%86%D9%86%D8%AF%D9%87%D8%B3%D8%AA%D9%87%E2%80%8C%D8%A7%DB%8C" title="پردازنده چندهسته‌ای – Persian" lang="fa" hreflang="fa" data-title="پردازنده چندهسته‌ای" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Microprocesseur_multi-c%C5%93ur" title="Microprocesseur multi-cœur – French" lang="fr" hreflang="fr" data-title="Microprocesseur multi-cœur" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%A9%80%ED%8B%B0_%EC%BD%94%EC%96%B4" title="멀티 코어 – Korean" lang="ko" hreflang="ko" data-title="멀티 코어" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Vi%C5%A1ejezgreni_procesor" title="Višejezgreni procesor – Croatian" lang="hr" hreflang="hr" data-title="Višejezgreni procesor" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Processore_multicore" title="Processore multicore – Italian" lang="it" hreflang="it" data-title="Processore multicore" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-kk mw-list-item"><a href="https://kk.wikipedia.org/wiki/%D0%9A%D3%A9%D0%BF%D1%8F%D0%B4%D1%80%D0%BE%D0%BB%D1%8B%D2%9B_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Көпядролық процессор – Kazakh" lang="kk" hreflang="kk" data-title="Көпядролық процессор" data-language-autonym="Қазақша" data-language-local-name="Kazakh" class="interlanguage-link-target"><span>Қазақша</span></a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/%D0%9F%D0%BE%D0%B2%D0%B5%D1%9C%D0%B5%D1%98%D0%B0%D0%B4%D1%80%D0%B5%D0%BD_%D0%BE%D0%B1%D1%80%D0%B0%D0%B1%D0%BE%D1%82%D1%83%D0%B2%D0%B0%D1%87" title="Повеќејадрен обработувач – Macedonian" lang="mk" hreflang="mk" data-title="Повеќејадрен обработувач" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target"><span>Македонски</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Multikernprocessor" title="Multikernprocessor – Dutch" lang="nl" hreflang="nl" data-title="Multikernprocessor" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%83%9E%E3%83%AB%E3%83%81%E3%82%B3%E3%82%A2" title="マルチコア – Japanese" lang="ja" hreflang="ja" data-title="マルチコア" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Flerkjerners_mikroprosessor" title="Flerkjerners mikroprosessor – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Flerkjerners mikroprosessor" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Procesor_wielordzeniowy" title="Procesor wielordzeniowy – Polish" lang="pl" hreflang="pl" data-title="Procesor wielordzeniowy" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Processador_multin%C3%BAcleo" title="Processador multinúcleo – Portuguese" lang="pt" hreflang="pt" data-title="Processador multinúcleo" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Chip_multiprocessor" title="Chip multiprocessor – Romanian" lang="ro" hreflang="ro" data-title="Chip multiprocessor" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%9C%D0%BD%D0%BE%D0%B3%D0%BE%D1%8F%D0%B4%D0%B5%D1%80%D0%BD%D1%8B%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Многоядерный процессор – Russian" lang="ru" hreflang="ru" data-title="Многоядерный процессор" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Multi-core_processor" title="Multi-core processor – Simple English" lang="en-simple" hreflang="en-simple" data-title="Multi-core processor" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%92%D0%B8%D1%88%D0%B5%D1%98%D0%B5%D0%B7%D0%B3%D0%B0%D1%80%D0%BD%D0%B8_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Вишејезгарни процесор – Serbian" lang="sr" hreflang="sr" data-title="Вишејезгарни процесор" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Moniytimellisyys_(tietotekniikka)" title="Moniytimellisyys (tietotekniikka) – Finnish" lang="fi" hreflang="fi" data-title="Moniytimellisyys (tietotekniikka)" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%A1%E0%B8%B1%E0%B8%A5%E0%B8%95%E0%B8%B4%E0%B8%84%E0%B8%AD%E0%B8%A3%E0%B9%8C" title="มัลติคอร์ – Thai" lang="th" hreflang="th" data-title="มัลติคอร์" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/%C3%87ok_%C3%A7ekirdekli_i%C5%9Flemci" title="Çok çekirdekli işlemci – Turkish" lang="tr" hreflang="tr" data-title="Çok çekirdekli işlemci" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%91%D0%B0%D0%B3%D0%B0%D1%82%D0%BE%D1%8F%D0%B4%D0%B5%D1%80%D0%BD%D0%B8%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Багатоядерний процесор – Ukrainian" lang="uk" hreflang="uk" data-title="Багатоядерний процесор" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/CPU_%C4%91a_nh%C3%A2n" title="CPU đa nhân – Vietnamese" lang="vi" hreflang="vi" data-title="CPU đa nhân" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a 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<div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Microprocessor with more than one processing unit</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"Dual Core" redirects here. Not to be confused with <a href="/wiki/Dual_Core_(hip_hop_duo)" title="Dual Core (hip hop duo)">Dual Core (hip hop duo)</a>.</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Dual_Core_Generic.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Dual_Core_Generic.svg/220px-Dual_Core_Generic.svg.png" decoding="async" width="220" height="255" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Dual_Core_Generic.svg/330px-Dual_Core_Generic.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ec/Dual_Core_Generic.svg/440px-Dual_Core_Generic.svg.png 2x" data-file-width="617" data-file-height="715" /></a><figcaption>Diagram of a generic dual-core processor with CPU-local level-1 caches and a shared, on-die level-2 cache</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:E6750bs8.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/E6750bs8.jpg/220px-E6750bs8.jpg" decoding="async" width="220" height="147" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/af/E6750bs8.jpg/330px-E6750bs8.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/af/E6750bs8.jpg/440px-E6750bs8.jpg 2x" data-file-width="900" data-file-height="600" /></a><figcaption>An Intel <a href="/wiki/Core_2_Duo" class="mw-redirect" title="Core 2 Duo">Core 2 Duo</a> E6750 dual-core processor</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Athlon64x2-6400plus.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fb/Athlon64x2-6400plus.jpg/220px-Athlon64x2-6400plus.jpg" decoding="async" width="220" height="147" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fb/Athlon64x2-6400plus.jpg/330px-Athlon64x2-6400plus.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fb/Athlon64x2-6400plus.jpg/440px-Athlon64x2-6400plus.jpg 2x" data-file-width="774" data-file-height="518" /></a><figcaption>An AMD <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon X2 6400+</a> dual-core processor</figcaption></figure> <p>A <b>multi-core processor</b> (<b>MCP</b>) is a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> on a single <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) with two or more separate <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing units</a> (CPUs), called <i>cores</i> to emphasize their multiplicity (for example, <i>dual-core</i> or <i>quad-core</i>). Each core reads and executes <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">program instructions</a>,<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> specifically ordinary <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">CPU instructions</a> (such as add, move data, and branch). However, the MCP can run instructions on separate cores at the same time, increasing overall speed for programs that support <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multithreading</a> or other <a href="/wiki/Parallel_computing" title="Parallel computing">parallel computing</a> techniques.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Manufacturers typically integrate the cores onto a single IC <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a>, known as a <i>chip multiprocessor</i> (CMP), or onto multiple dies in a single <a href="/wiki/Chip_carrier" title="Chip carrier">chip package</a>. As of 2024, the microprocessors used in almost all new <a href="/wiki/Personal_computer" title="Personal computer">personal computers</a> are multi-core. </p><p>A multi-core processor implements <a href="/wiki/Multiprocessing" title="Multiprocessing">multiprocessing</a> in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For example, cores may or may not share <a href="/wiki/CPU_cache" title="CPU cache">caches</a>, and they may implement <a href="/wiki/Message_passing" title="Message passing">message passing</a> or <a href="/wiki/Shared_memory" title="Shared memory">shared-memory</a> inter-core communication methods. Common <a href="/wiki/Network_topology" title="Network topology">network topologies</a> used to interconnect cores include <a href="/wiki/Bus_network" title="Bus network">bus</a>, <a href="/wiki/Ring_network" title="Ring network">ring</a>, two-dimensional <a href="/wiki/Mesh_networking" title="Mesh networking">mesh</a>, and <a href="/wiki/Crossbar_switch" title="Crossbar switch">crossbar</a>. Homogeneous multi-core systems include only identical cores; <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">heterogeneous</a> multi-core systems have cores that are not identical (e.g. <a href="/wiki/ARM_big.LITTLE" title="ARM big.LITTLE">big.LITTLE</a> have heterogeneous cores that share the same <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set</a>, while <a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">AMD Accelerated Processing Units</a> have cores that do not share the same instruction set). Just as with single-processor systems, cores in multi-core systems may implement architectures such as <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a>, <a href="/wiki/Superscalar_processor" title="Superscalar processor">superscalar</a>, <a href="/wiki/Vector_processor" title="Vector processor">vector</a>, or <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multithreading</a>. </p><p>Multi-core processors are widely used across many application domains, including <a href="/wiki/Computer" title="Computer">general-purpose</a>, <a href="/wiki/Embedded_system" title="Embedded system">embedded</a>, <a href="/wiki/Network_processor" title="Network processor">network</a>, <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> (DSP), and <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics</a> (GPU). Core count goes up to even dozens, and for specialized chips over 10,000,<sup id="cite_ref-10496_CUDA_cores_3-0" class="reference"><a href="#cite_note-10496_CUDA_cores-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> and in <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> (i.e. clusters of chips) the count can go over 10 million (and in <a href="/wiki/Gyoukou" title="Gyoukou">one case</a> up to 20 million processing elements total in addition to host processors).<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>The improvement in performance gained by the use of a multi-core processor depends very much on the <a href="/wiki/Software" title="Software">software</a> algorithms used and their implementation. In particular, possible gains are limited by the fraction of the software that can <a href="/wiki/Parallel_computing" title="Parallel computing">run in parallel</a> simultaneously on multiple cores; this effect is described by <a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a>. In the best case, so-called <a href="/wiki/Embarrassingly_parallel" title="Embarrassingly parallel">embarrassingly parallel</a> problems may realize speedup factors near the number of cores, or even more if the problem is split up enough to fit within each core's cache(s), avoiding use of much slower main-system memory. Most applications, however, are not accelerated as much unless programmers invest effort in <a href="/wiki/Refactoring" class="mw-redirect" title="Refactoring">refactoring</a>.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>The parallelization of software is a significant ongoing topic of research. Cointegration of multiprocessor applications provides flexibility in network architecture design. Adaptability within parallel models is an additional feature of systems utilizing these protocols.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>In the consumer market, dual-core processors (that is, microprocessors with two units) started becoming commonplace on personal computers in the late 2000s.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Quad-core processors were also being adopted in that era for higher-end systems before becoming standard. In the late 2010s, hexa-core (six cores) started entering the mainstream<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> and since the early 2020s has overtaken quad-core in many spaces.<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Terminology">Terminology</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=1" title="Edit section: Terminology"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The terms <i>multi-core</i> and <i>dual-core</i> most commonly refer to some sort of <a href="/wiki/Central_processing_unit" title="Central processing unit">central processing unit</a> (CPU), but are sometimes also applied to <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processors</a> (DSP) and <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a> (SoC). The terms are generally used only to refer to multi-core microprocessors that are manufactured on the <i>same</i> integrated circuit <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a>; separate microprocessor dies in the same package are generally referred to by another name, such as <i><a href="/wiki/Multi-chip_module" title="Multi-chip module">multi-chip module</a></i>. This article uses the terms "multi-core" and "dual-core" for CPUs manufactured on the <i>same</i> integrated circuit, unless otherwise noted. </p><p>In contrast to multi-core systems, the term <i>multi-CPU</i> refers to multiple physically separate processing-units (which often contain special circuitry to facilitate communication between each other). </p><p>The terms <i><a href="/wiki/Manycore_processor" title="Manycore processor">many-core</a></i> and <i>massively multi-core</i> are sometimes used to describe multi-core architectures with an especially high number of cores (tens to thousands<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup>).<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>Some systems use many <a href="/wiki/Soft_microprocessor" title="Soft microprocessor">soft microprocessor</a> cores placed on a single <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a>. Each "core" can be considered a "<a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">semiconductor intellectual property core</a>" as well as a CPU core.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (February 2011)">citation needed</span></a></i>]</sup> </p> <div class="mw-heading mw-heading2"><h2 id="Development">Development</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=2" title="Edit section: Development"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>While manufacturing technology improves, reducing the size of individual gates, physical limits of <a href="/wiki/Semiconductor" title="Semiconductor">semiconductor</a>-based <a href="/wiki/Microelectronics" title="Microelectronics">microelectronics</a> have become a major design concern. These physical limitations can cause significant heat dissipation and data synchronization problems. Various other methods are used to improve CPU performance. Some <i><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a></i> (ILP) methods such as <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">pipelining</a> are suitable for many applications, but are inefficient for others that contain difficult-to-predict code. Many applications are better suited to <i><a href="/wiki/Thread-level_parallelism" class="mw-redirect" title="Thread-level parallelism">thread-level parallelism</a></i> (TLP) methods, and multiple independent CPUs are commonly used to increase a system's overall TLP. A combination of increased available space (due to refined manufacturing processes) and the demand for increased TLP led to the development of multi-core CPUs. </p> <div class="mw-heading mw-heading3"><h3 id="Commercial_incentives">Commercial incentives</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=3" title="Edit section: Commercial incentives"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Several business motives drive the development of multi-core architectures. For decades, it was possible to improve performance of a CPU by shrinking the area of the integrated circuit (IC), which reduced the cost per device on the IC. Alternatively, for the same circuit area, more transistors could be used in the design, which increased functionality, especially for <a href="/wiki/Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">complex instruction set computing</a> (CISC) architectures. <a href="/wiki/Clock_rate" title="Clock rate">Clock rates</a> also increased by orders of magnitude in the decades of the late 20th century, from several megahertz in the 1980s to several gigahertz in the early 2000s. </p><p>As the rate of clock speed improvements slowed, increased use of parallel computing in the form of multi-core processors has been pursued to improve overall processing performance. Multiple cores were used on the same CPU chip, which could then lead to better sales of CPU chips with two or more cores. For example, <a href="/wiki/Intel" title="Intel">Intel</a> has produced a 48-core processor for research in cloud computing; each core has an <a href="/wiki/X86" title="X86">x86</a> architecture.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Technical_factors">Technical factors</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=4" title="Edit section: Technical factors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Since computer manufacturers have long implemented <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP) designs using discrete CPUs, the issues regarding implementing multi-core processor architecture and supporting it with software are well known. </p><p>Additionally: </p> <ul><li>Using a proven processing-core design without architectural changes reduces design risk significantly.</li> <li>For general-purpose processors, much of the motivation for multi-core processors comes from greatly diminished gains in processor performance from increasing the <a href="/wiki/Frequency_scaling" title="Frequency scaling">operating frequency</a>. This is due to three primary factors:<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> <ol><li>The <i>memory wall</i>; the increasing gap between processor and memory speeds. This, in effect, pushes for cache sizes to be larger in order to mask the latency of memory. This helps only to the extent that memory bandwidth is not the bottleneck in performance.</li> <li>The <i>ILP wall</i>; the increasing difficulty of finding enough <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">parallelism in a single instruction stream</a> to keep a high-performance single-core processor busy.</li> <li>The <i>power wall</i>; the trend of consuming exponentially increasing power (and thus also generating exponentially increasing heat) with each factorial increase of operating frequency. This increase can be mitigated by "<a href="/wiki/Die_shrink" title="Die shrink">shrinking</a>" the processor by using smaller traces for the same logic. The <i>power wall</i> poses manufacturing, system design and deployment problems that have not been justified in the face of the diminished gains in performance due to the <i>memory wall</i> and <i>ILP wall</i>.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (October 2019)">citation needed</span></a></i>]</sup></li></ol></li></ul> <p>In order to continue delivering regular performance improvements for general-purpose processors, manufacturers such as <a href="/wiki/Intel" title="Intel">Intel</a> and <a href="/wiki/AMD" title="AMD">AMD</a> have turned to multi-core designs, sacrificing lower manufacturing-costs for higher performance in some applications and systems. Multi-core architectures are being developed, but so are the alternatives. An especially strong contender for established markets is the further integration of peripheral functions into the chip. </p> <div class="mw-heading mw-heading3"><h3 id="Advantages">Advantages</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=5" title="Edit section: Advantages"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The proximity of multiple CPU cores on the same die allows the <a href="/wiki/Cache_coherency" class="mw-redirect" title="Cache coherency">cache coherency</a> circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance of <a href="/wiki/Cache_snooping" class="mw-redirect" title="Cache snooping">cache snoop</a> (alternative: <a href="/wiki/Bus_snooping" title="Bus snooping">Bus snooping</a>) operations. Put simply, this means that <a href="/wiki/Discrete_signal" class="mw-redirect" title="Discrete signal">signals</a> between different CPUs travel shorter distances, and therefore those signals <a href="/wiki/Degradation_(telecommunications)" title="Degradation (telecommunications)">degrade</a> less. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often. </p><p>Assuming that the die can physically fit into the package, multi-core CPU designs require much less <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit board</a> (PCB) space than do multi-chip <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a> designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the <a href="/wiki/Front-side_bus" title="Front-side bus">front-side bus</a> (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns. </p><p>Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Disadvantages">Disadvantages</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=6" title="Edit section: Disadvantages"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Maximizing the usage of the computing resources provided by multi-core processors requires adjustments both to the <a href="/wiki/Operating_system" title="Operating system">operating system</a> (OS) support and to existing application software. Also, the ability of multi-core processors to increase application performance depends on the use of multiple threads within applications. </p><p>Integration of a multi-core chip can lower the chip production yields. They are also more difficult to manage thermally than lower-density single-core designs. Intel has partially countered this first problem by creating its quad-core designs by combining two dual-core ones on a single die with a unified cache, hence any two working dual-core dies can be used, as opposed to producing four cores on a single die and requiring all four to work to produce a quad-core CPU. From an architectural point of view, ultimately, single CPU designs may make better use of the silicon surface area than multiprocessing cores, so a development commitment to this architecture may carry the risk of obsolescence. Finally, raw processing power is not the only constraint on system performance. Two processing cores sharing the same system bus and memory bandwidth limits the real-world performance advantage. </p> <div class="mw-heading mw-heading2"><h2 id="Hardware">Hardware</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=7" title="Edit section: Hardware"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <div class="mw-heading mw-heading3"><h3 id="Trends">Trends</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=8" title="Edit section: Trends"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The trend in processor development has been towards an ever-increasing number of cores, as processors with hundreds or even thousands of cores become theoretically possible.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> In addition, multi-core chips mixed with <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a>, memory-on-chip, and special-purpose <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">"heterogeneous"</a> (or asymmetric) cores promise further performance and efficiency gains, especially in processing multimedia, recognition and networking applications. For example, a <a href="/wiki/ARM_big.LITTLE" title="ARM big.LITTLE">big.LITTLE</a> core includes a high-performance core (called 'big') and a low-power core (called 'LITTLE'). There is also a trend towards improving energy-efficiency by focusing on performance-per-watt with advanced fine-grain or ultra fine-grain <a href="/wiki/Power_management" title="Power management">power management</a> and dynamic <a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">voltage</a> and <a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">frequency scaling</a> (i.e. <a href="/wiki/Laptop" title="Laptop">laptop</a> computers and <a href="/wiki/Portable_media_player" title="Portable media player">portable media players</a>). </p><p>Chips designed from the outset for a large number of cores (rather than having evolved from single core designs) are sometimes referred to as <a href="/wiki/Manycore" class="mw-redirect" title="Manycore">manycore</a> designs, emphasising qualitative differences. </p> <div class="mw-heading mw-heading3"><h3 id="Architecture">Architecture</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=9" title="Edit section: Architecture"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The composition and balance of the cores in multi-core architecture show great variety. Some architectures use one core design repeated consistently ("homogeneous"), while others use a mixture of different cores, each optimized for a different, "<a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">heterogeneous</a>" role. </p><p>How multiple cores are implemented and integrated significantly affects both the developer's programming skills and the consumer's expectations of apps and interactivity versus the device.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> A device advertised as being octa-core will only have independent cores if advertised as <i>True Octa-core</i>, or similar styling, as opposed to being merely two sets of quad-cores each with fixed clock speeds.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>The article "CPU designers debate multi-core future" by Rick Merritt, EE Times 2008,<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> includes these comments: </p> <style data-mw-deduplicate="TemplateStyles:r1244412712">.mw-parser-output .templatequote{overflow:hidden;margin:1em 0;padding:0 32px}.mw-parser-output .templatequotecite{line-height:1.5em;text-align:left;margin-top:0}@media(min-width:500px){.mw-parser-output .templatequotecite{padding-left:1.6em}}</style><blockquote class="templatequote"><p>Chuck Moore [...] suggested computers should be like cellphones, using a variety of specialty cores to run modular software scheduled by a high-level applications programming interface. </p><p>[...] Atsushi Hasegawa, a senior chief engineer at <a href="/wiki/Renesas" class="mw-redirect" title="Renesas">Renesas</a>, generally agreed. He suggested the cellphone's use of many specialty cores working in concert is a good model for future multi-core designs. </p><p> [...] <a href="/wiki/Anant_Agarwal" title="Anant Agarwal">Anant Agarwal</a>, founder and chief executive of startup <a href="/wiki/Tilera" title="Tilera">Tilera</a>, took the opposing view. He said multi-core chips need to be homogeneous collections of general-purpose cores to keep the software model simple.</p></blockquote> <div class="mw-heading mw-heading2"><h2 id="Software_effects">Software effects</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=10" title="Edit section: Software effects"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>An outdated version of an anti-virus application may create a new thread for a scan process, while its <a href="/wiki/Graphical_user_interface" title="Graphical user interface">GUI</a> thread waits for commands from the user (e.g. cancel the scan). In such cases, a multi-core architecture is of little benefit for the application itself due to the single thread doing all the heavy lifting and the inability to balance the work evenly across multiple cores. Programming truly multithreaded code often requires complex co-ordination of threads and can easily introduce subtle and difficult-to-find bugs due to the interweaving of processing on data shared between threads (see <a href="/wiki/Thread-safety" class="mw-redirect" title="Thread-safety">thread-safety</a>). Consequently, such code is much more difficult to debug than single-threaded code when it breaks. There has been a perceived lack of motivation for writing consumer-level threaded applications because of the relative rarity of consumer-level demand for maximum use of computer hardware. Also, serial tasks like decoding the <a href="/wiki/Entropy_encoding" class="mw-redirect" title="Entropy encoding">entropy encoding</a> algorithms used in <a href="/wiki/Video_codec" title="Video codec">video codecs</a> are impossible to parallelize because each result generated is used to help create the next result of the entropy decoding algorithm. </p><p>Given the increasing emphasis on multi-core chip design, stemming from the grave thermal and power consumption problems posed by any further significant increase in processor clock speeds, the extent to which software can be multithreaded to take advantage of these new chips is likely to be the single greatest constraint on computer performance in the future. If developers are unable to design software to fully exploit the resources provided by multiple cores, then they will ultimately reach an insurmountable performance ceiling. </p><p>The telecommunications market had been one of the first that needed a new design of parallel datapath packet processing because there was a very quick adoption of these multiple-core processors for the datapath and the control plane. These MPUs are going to replace<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> the traditional Network Processors that were based on proprietary <a href="/wiki/Microcode" title="Microcode">microcode</a> or <a href="/wiki/Picocode" class="mw-redirect" title="Picocode">picocode</a>. </p><p><a href="/wiki/Parallel_programming" class="mw-redirect" title="Parallel programming">Parallel programming</a> techniques can benefit from multiple cores directly. Some existing <a href="/wiki/Parallel_programming_model" title="Parallel programming model">parallel programming models</a> such as <a href="/wiki/Cilk_Plus" class="mw-redirect" title="Cilk Plus">Cilk Plus</a>, <a href="/wiki/OpenMP" title="OpenMP">OpenMP</a>, <a href="/wiki/OpenHMPP" title="OpenHMPP">OpenHMPP</a>, <a href="/wiki/Algorithmic_skeleton#FastFlow" title="Algorithmic skeleton">FastFlow</a>, Skandium, <a href="/wiki/Message_Passing_Interface" title="Message Passing Interface">MPI</a>, and <a href="/wiki/Erlang_(programming_language)" title="Erlang (programming language)">Erlang</a> can be used on multi-core platforms. Intel introduced a new abstraction for C++ parallelism called <a href="/wiki/Threading_Building_Blocks" title="Threading Building Blocks">TBB</a>. Other research efforts include the <a href="/wiki/Sieve_C%2B%2B_Parallel_Programming_System" title="Sieve C++ Parallel Programming System">Codeplay Sieve System</a>, Cray's <a href="/wiki/Chapel_(programming_language)" title="Chapel (programming language)">Chapel</a>, Sun's <a href="/wiki/Fortress_programming_language" class="mw-redirect" title="Fortress programming language">Fortress</a>, and IBM's <a href="/wiki/X10_(programming_language)" title="X10 (programming language)">X10</a>. </p><p>Multi-core processing has also affected the ability of modern computational software development. Developers programming in newer languages might find that their modern languages do not support multi-core functionality. This then requires the use of <a href="/wiki/List_of_numerical_libraries" title="List of numerical libraries">numerical libraries</a> to access code written in languages like <a href="/wiki/C_(programming_language)" title="C (programming language)">C</a> and <a href="/wiki/Fortran" title="Fortran">Fortran</a>, which perform math computations faster<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (April 2023)">citation needed</span></a></i>]</sup> than newer languages like <a href="/wiki/C_Sharp_(programming_language)" title="C Sharp (programming language)">C#</a>. Intel's MKL and AMD's <a href="/wiki/AMD_Core_Math_Library" title="AMD Core Math Library">ACML</a> are written in these native languages and take advantage of multi-core processing. Balancing the application workload across processors can be problematic, especially if they have different performance characteristics. There are different conceptual models to deal with the problem, for example using a coordination language and program building blocks (programming libraries or higher-order functions). Each block can have a different native implementation for each processor type. Users simply program using these abstractions and an intelligent compiler chooses the best implementation based on the context.<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p><p>Managing <a href="/wiki/Concurrent_computing" title="Concurrent computing">concurrency</a> acquires a central role in developing parallel applications. The basic steps in designing parallel applications are: </p> <dl><dt>Partitioning</dt> <dd>The partitioning stage of a design is intended to expose opportunities for parallel execution. Hence, the focus is on defining a large number of small tasks in order to yield what is termed a fine-grained decomposition of a problem.</dd></dl> <dl><dt>Communication</dt> <dd>The tasks generated by a partition are intended to execute concurrently but cannot, in general, execute independently. The computation to be performed in one task will typically require data associated with another task. Data must then be transferred between tasks so as to allow computation to proceed. This information flow is specified in the communication phase of a design.</dd></dl> <dl><dt>Agglomeration</dt> <dd>In the third stage, development moves from the abstract toward the concrete. Developers revisit decisions made in the partitioning and communication phases with a view to obtaining an algorithm that will execute efficiently on some class of parallel computer. In particular, developers consider whether it is useful to combine, or agglomerate, tasks identified by the partitioning phase, so as to provide a smaller number of tasks, each of greater size. They also determine whether it is worthwhile to replicate data and computation.</dd></dl> <dl><dt>Mapping</dt> <dd>In the fourth and final stage of the design of parallel algorithms, the developers specify where each task is to execute. This mapping problem does not arise on uniprocessors or on shared-memory computers that provide automatic task scheduling.</dd></dl> <p>On the other hand, on the <a href="/wiki/Server-side" class="mw-redirect" title="Server-side">server side</a>, multi-core processors are ideal because they allow many users to connect to a site simultaneously and have independent <a href="/wiki/Thread_(computer_science)" class="mw-redirect" title="Thread (computer science)">threads</a> of execution. This allows for Web servers and application servers that have much better <a href="/wiki/Throughput" class="mw-redirect" title="Throughput">throughput</a>. </p> <div class="mw-heading mw-heading3"><h3 id="Licensing">Licensing</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=11" title="Edit section: Licensing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Vendors may license some software "per processor". This can give rise to ambiguity, because a "processor" may consist either of a single core or of a combination of cores. </p> <ul><li>Initially, for some of its enterprise software, <a href="/wiki/Microsoft" title="Microsoft">Microsoft</a> continued to use a per-<a href="/wiki/CPU_socket" title="CPU socket">socket</a> licensing system. However, for some software such as <a href="/wiki/BizTalk" class="mw-redirect" title="BizTalk">BizTalk Server 2013</a>, <a href="/wiki/Microsoft_SQL_Server" title="Microsoft SQL Server">SQL Server 2014</a>, and <a href="/wiki/Windows_Server_2016" title="Windows Server 2016">Windows Server 2016</a>, Microsoft has shifted to per-core licensing.<sup id="cite_ref-ars-2016license_23-0" class="reference"><a href="#cite_note-ars-2016license-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Oracle_Corporation" title="Oracle Corporation">Oracle Corporation</a> counts an AMD X2 or an Intel dual-core CPU as a single processor<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2015)">citation needed</span></a></i>]</sup> but uses other metrics for other types, especially for processors with more than two cores.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Embedded_applications">Embedded applications</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=12" title="Edit section: Embedded applications"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:DHCOM_Computer_On_Module_-_AM35x.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/6b/DHCOM_Computer_On_Module_-_AM35x.jpg/220px-DHCOM_Computer_On_Module_-_AM35x.jpg" decoding="async" width="220" height="123" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/6b/DHCOM_Computer_On_Module_-_AM35x.jpg/330px-DHCOM_Computer_On_Module_-_AM35x.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/6b/DHCOM_Computer_On_Module_-_AM35x.jpg/440px-DHCOM_Computer_On_Module_-_AM35x.jpg 2x" data-file-width="2126" data-file-height="1185" /></a><figcaption>An <i>embedded system</i> on a plug-in card with processor, memory, power supply, and external interfaces</figcaption></figure> <p><a href="/wiki/Embedded_computing" class="mw-redirect" title="Embedded computing">Embedded computing</a> operates in an area of processor technology distinct from that of "mainstream" PCs. The same technological drives towards multi-core apply here too. Indeed, in many cases the application is a "natural" fit for multi-core technologies, if the task can easily be partitioned between the different processors. </p><p>In addition, embedded software is typically developed for a specific hardware release, making issues of <a href="/wiki/Software_portability" title="Software portability">software portability</a>, legacy code or supporting independent developers less critical than is the case for PC or enterprise computing. As a result, it is easier for developers to adopt new technologies and as a result there is a greater variety of multi-core processing architectures and suppliers. </p> <div class="mw-heading mw-heading2"><h2 id="Network_processors">Network processors</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=13" title="Edit section: Network processors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>As of 2010<sup class="plainlinks noexcerpt noprint asof-tag update" style="display:none;"><a class="external text" href="https://en.wikipedia.org/w/index.php?title=Multi-core_processor&action=edit">[update]</a></sup>, multi-core <a href="/wiki/Network_processors" class="mw-redirect" title="Network processors">network processors</a> have become mainstream, with companies such as <a href="/wiki/Freescale_Semiconductor" title="Freescale Semiconductor">Freescale Semiconductor</a>, <a href="/wiki/Cavium_Networks" class="mw-redirect" title="Cavium Networks">Cavium Networks</a>, <a href="/w/index.php?title=Wintegra&action=edit&redlink=1" class="new" title="Wintegra (page does not exist)">Wintegra</a> and <a href="/wiki/Broadcom" title="Broadcom">Broadcom</a> all manufacturing products with eight processors. For the system developer, a key challenge is how to exploit all the cores in these devices to achieve maximum networking performance at the system level, despite the performance limitations inherent in a <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP) operating system. Companies such as <a href="/wiki/6WIND" title="6WIND">6WIND</a> provide portable packet processing software designed so that the networking data plane runs in a fast path environment outside the operating system of the network device.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Digital_signal_processing">Digital signal processing</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=14" title="Edit section: Digital signal processing"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a> the same trend applies: <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> has the three-core TMS320C6488 and four-core TMS320C5441, <a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a> the four-core MSC8144 and six-core MSC8156 (and both have stated they are working on eight-core successors). Newer entries include the Storm-1 family from <a rel="nofollow" class="external text" href="https://web.archive.org/web/20101210220716/http://www.streamprocessors.com/streamprocessors/Home.html">Stream Processors, Inc</a> with 40 and 80 general purpose ALUs per chip, all programmable in C as a SIMD engine and <a href="/wiki/Picochip" class="mw-redirect" title="Picochip">Picochip</a> with 300 processors on a single die, focused on communication applications. </p> <div class="mw-heading mw-heading2"><h2 id="Heterogeneous_systems">Heterogeneous systems</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=15" title="Edit section: Heterogeneous systems"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In <a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">heterogeneous computing</a>, where a system uses more than one kind of processor or cores, multi-core solutions are becoming more common: <a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> Zynq UltraScale+ MPSoC has a quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5. Software solutions such as OpenAMP are being used to help with inter-processor communication. </p><p>Mobile devices may use the <a href="/wiki/ARM_big.LITTLE" title="ARM big.LITTLE">ARM big.LITTLE</a> architecture. </p> <div class="mw-heading mw-heading2"><h2 id="Hardware_examples">Hardware examples</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=16" title="Edit section: Hardware examples"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Example_farm plainlinks metadata ambox ambox-content" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/40px-Ambox_important.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/60px-Ambox_important.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/b/b4/Ambox_important.svg/80px-Ambox_important.svg.png 2x" data-file-width="40" data-file-height="40" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>may contain <a href="/wiki/Wikipedia:Manual_of_Style/Lists#List_size" title="Wikipedia:Manual of Style/Lists">excessive</a> or <a href="/wiki/Wikipedia:Neutral_point_of_view#Due_and_undue_weight" title="Wikipedia:Neutral point of view">irrelevant</a> examples</b>.<span class="hide-when-compact"> Please help <a class="external text" href="https://en.wikipedia.org/w/index.php?title=Multi-core_processor&action=edit">improve the article</a> by adding descriptive text and removing <a href="/wiki/Wikipedia:Example_cruft" title="Wikipedia:Example cruft">less pertinent examples</a>.</span> <span class="date-container"><i>(<span class="date">July 2016</span>)</i></span></div></td></tr></tbody></table> <div class="mw-heading mw-heading3"><h3 id="Commercial">Commercial</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=17" title="Edit section: Commercial"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Adapteva" class="mw-redirect" title="Adapteva">Adapteva</a> Epiphany, a many-core processor architecture which allows up to 4096 processors on-chip, although only a 16-core version has been commercially produced.</li> <li><a href="/w/index.php?title=Aeroflex_Gaisler&action=edit&redlink=1" class="new" title="Aeroflex Gaisler (page does not exist)">Aeroflex Gaisler</a> <a href="/wiki/LEON#LEON3_processor_core" title="LEON">LEON3</a>, a multi-core <a href="/wiki/SPARC" title="SPARC">SPARC</a> that also exists in a <a href="/wiki/LEON#LEON3FT_processor_core" title="LEON">fault-tolerant version</a>.</li> <li><a href="/wiki/Ageia" title="Ageia">Ageia</a> <a href="/wiki/PhysX" title="PhysX">PhysX</a>, a multi-core <a href="/wiki/Physics_processing_unit" title="Physics processing unit">physics processing unit</a>.</li> <li><a href="/wiki/Ambric" title="Ambric">Ambric</a> Am2045, a 336-core <a href="/wiki/Massively_parallel_processor_array" title="Massively parallel processor array">massively parallel processor array</a> (MPPA)</li> <li><a href="/wiki/Advanced_Micro_Devices" class="mw-redirect" title="Advanced Micro Devices">AMD</a> <ul><li><a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">A-Series</a>, dual-, triple-, and quad-core of Accelerated Processor Units (APU).</li> <li><a href="/wiki/Athlon_64_FX" class="mw-redirect" title="Athlon 64 FX">Athlon 64 FX</a> and <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a> single- and dual-core desktop processors.</li> <li><a href="/wiki/Athlon_II" title="Athlon II">Athlon II</a>, dual-, triple-, and quad-core desktop processors.</li> <li><a href="/wiki/AMD_FX" title="AMD FX">FX-Series</a>, quad-, 6-, and 8-core desktop processors.</li> <li><a href="/wiki/Opteron" title="Opteron">Opteron</a>, single-, dual-, quad-, 6-, 8-, 12-, and 16-core server/workstation processors.</li> <li><a href="/wiki/AMD_Phenom" title="AMD Phenom">Phenom</a>, dual-, triple-, and quad-core processors.</li> <li><a href="/wiki/Phenom_II" title="Phenom II">Phenom II</a>, dual-, triple-, quad-, and 6-core desktop processors.</li> <li><a href="/wiki/Sempron" title="Sempron">Sempron</a>, single-, dual-, and quad-core entry level processors.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/AMD_Turion" title="AMD Turion">Turion</a>, single- and dual-core laptop processors.</li> <li><a href="/wiki/Ryzen" title="Ryzen">Ryzen</a>, dual-, quad-, 6-, 8-, 12-, 16-, 24-, 32-, and 64-core desktop, mobile, and embedded platform processors.</li> <li><a href="/wiki/Epyc" title="Epyc">Epyc</a>, quad-, 8-, 12-, 16-, 24-, 32-, and 64-core server and embedded processors.</li> <li><a href="/wiki/Radeon" title="Radeon">Radeon</a> and <a href="/wiki/AMD_FireStream" title="AMD FireStream">FireStream</a> GPU/<a href="/wiki/GPGPU" class="mw-redirect" title="GPGPU">GPGPU</a>.</li></ul></li> <li>Analog Devices <a href="/wiki/Blackfin" title="Blackfin">Blackfin</a> BF561, a symmetrical dual-core processor</li> <li><a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> <a href="/w/index.php?title=MPCore&action=edit&redlink=1" class="new" title="MPCore (page does not exist)">MPCore</a> is a fully synthesizable multi-core container for <a href="/wiki/ARM11_MPCore" class="mw-redirect" title="ARM11 MPCore">ARM11 MPCore</a> and <a href="/wiki/ARM_Cortex-A9_MPCore" class="mw-redirect" title="ARM Cortex-A9 MPCore">ARM Cortex-A9 MPCore</a> processor cores, intended for high-performance embedded and entertainment applications.</li> <li><a href="/wiki/ASOCS" title="ASOCS">ASOCS</a> ModemX, up to 128 cores, wireless applications.</li> <li><a href="/wiki/Azul_Systems" title="Azul Systems">Azul Systems</a> <ul><li>Vega 1, a 24-core processor, released in 2005.</li> <li>Vega 2, a 48-core processor, released in 2006.</li> <li>Vega 3, a 54-core processor, released in 2008.</li></ul></li> <li>Broadcom <ul><li>SiByte SB1250, SB1255, SB1455</li> <li>BCM2836, BCM2837, BCM2710 and BCM2711 quad-core ARM SoC (designed for different <a href="/wiki/Raspberry_Pi" title="Raspberry Pi">Raspberry Pi</a> models)</li></ul></li> <li>Cadence Design Systems <a href="/wiki/Tensilica" title="Tensilica">Tensilica</a> Xtensa LX6, available in a dual-core configuration in <a href="/wiki/Espressif_Systems" class="mw-redirect" title="Espressif Systems">Espressif Systems</a>'s <a href="/wiki/ESP32" title="ESP32">ESP32</a></li> <li><a href="/wiki/ClearSpeed" title="ClearSpeed">ClearSpeed</a> <ul><li>CSX700, 192-core processor, released in 2008 (32/64-bit floating point; Integer ALU).</li></ul></li> <li>Cradle Technologies CT3400 and CT3600, both multi-core DSPs.</li> <li><a href="/wiki/Cavium_Networks" class="mw-redirect" title="Cavium Networks">Cavium Networks</a> Octeon, a 32-core <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> <a href="/wiki/Manycore_processing_unit" class="mw-redirect" title="Manycore processing unit">MPU</a>.</li> <li><a rel="nofollow" class="external text" href="http://www.coherentlogix.com/">Coherent Logix</a> <a rel="nofollow" class="external text" href="http://www.coherentlogix.com/products/hyperx-processors/">hx3100 Processor</a>, a 100-core DSP/GPP processor.</li> <li><a href="/wiki/Freescale_Semiconductor" title="Freescale Semiconductor">Freescale Semiconductor</a> QorIQ series processors, up to 8 cores, <a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <a href="/wiki/Manycore_processing_unit" class="mw-redirect" title="Manycore processing unit">MPU</a>.</li> <li>Hewlett-Packard <a href="/wiki/PA-8800" class="mw-redirect" title="PA-8800">PA-8800</a> and <a href="/wiki/PA-8900" class="mw-redirect" title="PA-8900">PA-8900</a>, dual core <a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a> processors.</li> <li><a href="/wiki/IBM" title="IBM">IBM</a> <ul><li><a href="/wiki/POWER4" title="POWER4">POWER4</a>, a dual-core <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> processor, released in 2001.</li> <li><a href="/wiki/POWER5" title="POWER5">POWER5</a>, a dual-core PowerPC processor, released in 2004.</li> <li><a href="/wiki/POWER6" title="POWER6">POWER6</a>, a dual-core PowerPC processor, released in 2007.</li> <li><a href="/wiki/POWER7" title="POWER7">POWER7</a>, a 4, 6 and 8-core PowerPC processor, released in 2010.</li> <li><a href="/wiki/POWER8" title="POWER8">POWER8</a>, a 12-core PowerPC processor, released in 2013.</li> <li><a href="/wiki/POWER9" title="POWER9">POWER9</a>, a 12 or 24-core PowerPC processor, released in 2017.</li> <li><a href="/wiki/Power10" title="Power10">Power10</a>, a 15 or 30-core PowerPC processor, released in 2021.</li> <li><a href="/wiki/PowerPC_970" title="PowerPC 970">PowerPC 970</a>MP, a dual-core PowerPC processor, used in the Apple <a href="/wiki/Power_Mac_G5" title="Power Mac G5">Power Mac G5</a>.</li> <li><a href="/wiki/Xenon_(processor)" title="Xenon (processor)">Xenon</a>, a triple-core, <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">SMT</a>-capable, PowerPC microprocessor used in the Microsoft <a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a> game console.</li> <li><a href="/wiki/IBM_z10" title="IBM z10">z10</a>, a quad-core <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a> processor, released in 2008.</li> <li><a href="/wiki/IBM_z196" title="IBM z196">z196</a>, a quad-core z/Architecture processor, released in 2010.</li> <li><a href="/wiki/IBM_zEC12_(microprocessor)" class="mw-redirect" title="IBM zEC12 (microprocessor)">zEC12</a>, a six-core z/Architecture processor, released in 2012.</li> <li><a href="/wiki/IBM_z13_(microprocessor)" class="mw-redirect" title="IBM z13 (microprocessor)">z13</a>, an eight-core z/Architecture processor, released in 2015.</li> <li><a href="/wiki/IBM_z14_(microprocessor)" class="mw-redirect" title="IBM z14 (microprocessor)">z14</a>, a ten-core z/Architecture processor, released in 2017.</li> <li><a href="/wiki/IBM_z15_(microprocessor)" class="mw-redirect" title="IBM z15 (microprocessor)">z15</a>, a twelve-core z/Architecture processor, released in 2019.</li> <li><a href="/wiki/IBM_Telum_(microprocessor)" class="mw-redirect" title="IBM Telum (microprocessor)">Telum</a>, an eight-core z/Architecture processor, released in 2021.</li></ul></li> <li><a href="/wiki/Infineon" class="mw-redirect" title="Infineon">Infineon</a> <ul><li><a href="/wiki/Infineon_AURIX" title="Infineon AURIX">AURIX</a></li> <li>Danube, a dual-core, MIPS-based, <a href="/wiki/Home_gateway" class="mw-redirect" title="Home gateway">home gateway</a> processor.</li></ul></li> <li><a href="/wiki/Intel" title="Intel">Intel</a> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a>, single, dual-core, quad-core, 8-, 12-, and 16-core processors for <a href="/wiki/Netbook" title="Netbook">netbooks</a>, <a href="/wiki/Nettop" class="mw-redirect" title="Nettop">nettops</a>, embedded applications, and <a href="/wiki/Mobile_Internet_device" title="Mobile Internet device">mobile internet devices</a> (MIDs).<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">Atom SoC (system on a chip)</a>, single-core, dual-core, and quad-core processors for smartphones and tablets.<sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a>, the first dual-core (and, later, quad-core) processor for the budget/entry-level market.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Core_Duo" class="mw-redirect" title="Core Duo">Core Duo</a>, a dual-core processor.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Core_2_Duo" class="mw-redirect" title="Core 2 Duo">Core 2 Duo</a>, a dual-core processor.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Core_2_Quad" class="mw-redirect" title="Core 2 Quad">Core 2 Quad</a>, 2 dual-core dies packaged in a multi-chip module.<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Core_i3" class="mw-redirect" title="Core i3">Core i3</a>, <a href="/wiki/Core_i5" class="mw-redirect" title="Core i5">Core i5</a>, <a href="/wiki/Core_i7" class="mw-redirect" title="Core i7">Core i7</a> and <a href="/wiki/List_of_Intel_Core_i9_microprocessors" class="mw-redirect" title="List of Intel Core i9 microprocessors">Core i9</a>, a family of dual-, quad-, 6-, 8-, 10-, 12-, 14-, 16-, and 18-core processors, and the successor of the <a href="/wiki/Core_2_Duo" class="mw-redirect" title="Core 2 Duo">Core 2 Duo</a> and the <a href="/wiki/Core_2_Quad" class="mw-redirect" title="Core 2 Quad">Core 2 Quad</a>.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Itanium" title="Itanium">Itanium</a>, single, dual-core, quad-core, and 8-core processors.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a>, single, dual-core, and quad-core processors for the entry-level market.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Teraflops_Research_Chip" title="Teraflops Research Chip">Teraflops Research Chip</a> (Polaris), a 3.16 GHz, 80-core processor prototype, which the company originally stated would be released by 2011.<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> dual-, quad-, 6-, 8-, 10-, 12-, 14-, 15-, 16-, 18-, 20-, 22-, 24-, 26-, 28-, 32-, 48-, and 56-core processors.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-43" class="reference"><a href="#cite_note-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Intel_MIC#Xeon_Phi" class="mw-redirect" title="Intel MIC">Xeon Phi</a> 57-, 60-, 61-, 64-, 68-, and 72-core processors.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup></li></ul></li> <li>IntellaSys <ul><li>SEAforth 40C18, a 40-core processor.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup></li> <li>SEAforth24, a 24-core processor designed by <a href="/wiki/Charles_H._Moore" title="Charles H. Moore">Charles H. Moore</a>.</li></ul></li> <li><a href="/wiki/Kalray" title="Kalray">Kalray</a> <ul><li><a href="/w/index.php?title=MPPA-256&action=edit&redlink=1" class="new" title="MPPA-256 (page does not exist)">MPPA-256</a>, 256-core processor, released 2012 (256 usable VLIW cores, Network-on-Chip (NoC), 32/64-bit IEEE 754 compliant FPU)</li></ul></li> <li>NetLogic Microsystems <ul><li>XLP, a 32-core, quad-threaded <a href="/wiki/MIPS64" class="mw-redirect" title="MIPS64">MIPS64</a> processor.</li> <li>XLR, an eight-core, quad-threaded MIPS64 processor.</li> <li>XLS, an eight-core, quad-threaded MIPS64 processor.</li></ul></li> <li><a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> <ul><li><a href="/wiki/GeForce_30_series" title="GeForce 30 series">RTX 3090</a> (10496 CUDA cores, <a href="/wiki/GPGPU" class="mw-redirect" title="GPGPU">GPGPU</a> cores;<sup id="cite_ref-10496_CUDA_cores_3-1" class="reference"><a href="#cite_note-10496_CUDA_cores-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> plus other more specialized cores).</li></ul></li> <li><a href="/wiki/Parallax_Propeller" title="Parallax Propeller">Parallax Propeller P8X32</a>, an eight-core <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a>.</li> <li><a href="/wiki/PicoChip" title="PicoChip">picoChip</a> PC200 series 200–300 cores per device for DSP & wireless.</li> <li><a href="/wiki/Plurality_(company)" title="Plurality (company)">Plurality</a> HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.</li> <li>Rapport <a href="/wiki/Kilocore" title="Kilocore">Kilocore</a> KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements".</li> <li>Raspberry Pi Ltd. <a href="/wiki/RP2040" title="RP2040">RP2040</a>, a dual <a href="/wiki/ARM_Cortex-M0%2B" class="mw-redirect" title="ARM Cortex-M0+">ARM Cortex-M0+</a> microcontroller</li> <li><a href="/wiki/SiCortex" title="SiCortex">SiCortex</a> "SiCortex node" has six MIPS64 cores on a single chip.</li> <li><a href="/wiki/SiFive" title="SiFive">SiFive</a> <ul><li>U74 includes 4 cores</li></ul></li> <li><a href="/wiki/Sony" title="Sony">Sony</a>/<a href="/wiki/IBM" title="IBM">IBM</a>/<a href="/wiki/Toshiba" title="Toshiba">Toshiba</a>'s <a href="/wiki/Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">Cell</a> processor, a nine-core processor with one general purpose <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> core and eight specialized SPUs (Synergistic Processing Unit) optimized for vector operations used in the Sony <a href="/wiki/PlayStation_3" title="PlayStation 3">PlayStation 3</a>.</li> <li><a href="/wiki/Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a> <ul><li><a href="/wiki/MAJC" title="MAJC">MAJC</a> 5200, two-core VLIW processor.</li> <li><a href="/wiki/UltraSPARC_IV" title="UltraSPARC IV">UltraSPARC IV</a> and UltraSPARC IV+, dual-core processors.</li> <li><a href="/wiki/UltraSPARC_T1" title="UltraSPARC T1">UltraSPARC T1</a>, an eight-core, 32-thread processor.</li> <li><a href="/wiki/UltraSPARC_T2" title="UltraSPARC T2">UltraSPARC T2</a>, an eight-core, 64-concurrent-thread processor.</li> <li><a href="/wiki/UltraSPARC_T3" class="mw-redirect" title="UltraSPARC T3">UltraSPARC T3</a>, a sixteen-core, 128-concurrent-thread processor.</li> <li><a href="/wiki/SPARC_T4" title="SPARC T4">SPARC T4</a>, an eight-core, 64-concurrent-thread processor.</li> <li><a href="/wiki/SPARC_T5" title="SPARC T5">SPARC T5</a>, a sixteen-core, 128-concurrent-thread processor.</li></ul></li> <li>Sunway <ul><li><a href="/wiki/Sunway_SW26010" title="Sunway SW26010">Sunway SW26010</a>, a 260-core processor used in the <a href="/wiki/Sunway_TaihuLight" title="Sunway TaihuLight">Sunway TaihuLight</a>.</li></ul></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> <ul><li><a href="/wiki/Texas_Instruments_TMS320" class="mw-redirect" title="Texas Instruments TMS320">TMS320C80 MVP</a>, a five-core multimedia video processor.</li> <li>TMS320TMS320C66, 2-, 4-, 8-core DSP.</li></ul></li> <li><a href="/wiki/Tilera" title="Tilera">Tilera</a> <ul><li><a href="/wiki/TILE64" title="TILE64">TILE64</a>, a 64-core 32-bit processor.</li> <li><a href="/wiki/TILE-Gx" title="TILE-Gx">TILE-Gx</a>, a 72-core 64-bit processor.</li></ul></li> <li>XMOS <a href="/wiki/Software_Defined_Silicon" class="mw-redirect" title="Software Defined Silicon">Software Defined Silicon</a> quad-core XS1-G4.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Free">Free</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=18" title="Edit section: Free"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/OpenSPARC" title="OpenSPARC">OpenSPARC</a></li></ul> <div class="mw-heading mw-heading3"><h3 id="Academic">Academic</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=19" title="Edit section: Academic"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Stanford" class="mw-redirect" title="Stanford">Stanford</a>, 4-core Hydra processor<sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/MIT" class="mw-redirect" title="MIT">MIT</a>, 16-core <a rel="nofollow" class="external text" href="http://groups.csail.mit.edu/cag/raw/">RAW</a> processor</li> <li><a href="/wiki/University_of_California,_Davis" title="University of California, Davis">University of California, Davis</a>, <a href="/wiki/Asynchronous_array_of_simple_processors" title="Asynchronous array of simple processors">Asynchronous array of simple processors</a> (AsAP) <ul><li>36-core 610 MHz <a href="/wiki/Asynchronous_array_of_simple_processors#AsAP_1_chip:_36_processors" title="Asynchronous array of simple processors">AsAP</a></li> <li>167-core 1.2 GHz <a href="/wiki/Asynchronous_array_of_simple_processors#AsAP_2_chip:_167_processors" title="Asynchronous array of simple processors">AsAP2</a></li></ul></li> <li><a href="/wiki/University_of_Washington" title="University of Washington">University of Washington</a>, <a rel="nofollow" class="external text" href="http://wavescalar.cs.washington.edu/">Wavescalar</a> processor</li> <li><a href="/wiki/University_of_Texas,_Austin" class="mw-redirect" title="University of Texas, Austin">University of Texas, Austin</a>, <a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a> processor</li> <li><a href="/wiki/Link%C3%B6ping_University" title="Linköping University">Linköping University</a>, Sweden, ePUMA processor</li> <li><a href="/wiki/UC_Davis" class="mw-redirect" title="UC Davis">UC Davis</a>, Kilocore, a 1000 core 1.78 GHz processor on a 32 nm IBM process<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Benchmarks">Benchmarks</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=20" title="Edit section: Benchmarks"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The research and development of multicore processors often compares many options, and benchmarks are developed to help such evaluations. Existing benchmarks include SPLASH-2, PARSEC, and COSMIC for heterogeneous systems.<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=21" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 25em;"> <ul><li><a href="/wiki/CPU_shielding" title="CPU shielding">CPU shielding</a></li> <li><a href="/wiki/CUDA" title="CUDA">CUDA</a></li> <li><a href="/wiki/GPGPU" class="mw-redirect" title="GPGPU">GPGPU</a></li> <li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyper-threading</a></li> <li><a href="/wiki/Manycore" class="mw-redirect" title="Manycore">Manycore</a></li> <li><a href="/wiki/Multicore_Association" title="Multicore Association">Multicore Association</a></li> <li><a href="/wiki/Computer_multitasking" title="Computer multitasking">Multitasking</a></li> <li><a href="/wiki/OpenCL" title="OpenCL">OpenCL</a> (Open Computing Language) – a framework for heterogeneous execution</li> <li><a href="/wiki/Parallel_random_access_machine" class="mw-redirect" title="Parallel random access machine">Parallel random access machine</a></li> <li><a href="/wiki/Partitioned_global_address_space" title="Partitioned global address space">Partitioned global address space</a> (PGAS)</li> <li><a href="/wiki/Race_condition" title="Race condition">Race condition</a></li> <li><a href="/wiki/Thread_(computer_science)" class="mw-redirect" title="Thread (computer science)">Thread</a></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=22" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ol><li><style data-mw-deduplicate="TemplateStyles:r1041539562">.mw-parser-output .citation{word-wrap:break-word}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}</style><span class="citation wikicite" id="endnote_DSP"><b><a href="#ref_DSP">^</a></b></span> <a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processors</a> (DSPs) have used multi-core architectures for much longer than high-end general-purpose processors. A typical example of a DSP-specific implementation would be a combination of a <a href="/wiki/Reduced_instruction_set_computing" class="mw-redirect" title="Reduced instruction set computing">RISC</a> CPU and a DSP <a href="/wiki/Microprocessor" title="Microprocessor">MPU</a>. This allows for the design of products that require a general-purpose processor for user interfaces and a DSP for real-time data processing; this type of design is common in <a href="/wiki/Mobile_phone" title="Mobile phone">mobile phones</a>. In other applications, a growing number of companies have developed multi-core DSPs with very large numbers of processors.</li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1041539562"><span class="citation wikicite" id="endnote_PMTandSMP"><b><a href="#ref_PMTandSMP">^</a></b></span> Two types of <a href="/wiki/Operating_system" title="Operating system">operating systems</a> are able to use a dual-CPU multiprocessor: partitioned multiprocessing and <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP). In a partitioned architecture, each CPU boots into separate segments of physical memory and operate independently; in an SMP OS, processors work in a shared space, executing threads within the OS independently.</li></ol> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=23" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFRouse2007" class="citation web cs1">Rouse, Margaret (March 27, 2007). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html">"Definition: multi-core processor"</a>. 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Intel. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150707120021/http://ark.intel.com/products/family/78584/Intel-Xeon-Processor-E7-v2-Family">Archived</a> from the original on 2015-07-07.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Xeon+Processor+E7+v2+Family&rft.pub=Intel&rft_id=http%3A%2F%2Fark.intel.com%2Fproducts%2Ffamily%2F78584%2FIntel-Xeon-Processor-E7-v2-Family&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMulti-core+processor" class="Z3988"></span></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family">"Intel Xeon Processor E3 v2 Family"</a>. Intel. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20150707120142/http://ark.intel.com/products/family/78580/Intel-Xeon-Processor-E3-v2-Family">Archived</a> from the original on 2015-07-07.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+Xeon+Processor+E3+v2+Family&rft.pub=Intel&rft_id=http%3A%2F%2Fark.intel.com%2Fproducts%2Ffamily%2F78580%2FIntel-Xeon-Processor-E3-v2-Family&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMulti-core+processor" class="Z3988"></span></span> </li> <li id="cite_note-42"><span class="mw-cite-backlink"><b><a href="#cite_ref-42">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techspot.com/news/79481-intel-announces-xeon-platinum-9200-series-cpus-up.html">"Intel shows off Xeon Platinum CPU with up to 56 cores and 112 threads"</a>. <i>TechSpot</i>. 2 April 2019<span class="reference-accessdate">. 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Hasan; Nicolas G. Grounds; John K. Antonio (July 2011). <i>Predicting CPU Availability of a Multi-core Processor Executing Concurrent Java Threads</i>. 17th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA-11). Las Vegas, Nevada, USA. pp. 551–557. <a href="/wiki/Hdl_(identifier)" class="mw-redirect" title="Hdl (identifier)">hdl</a>:<a rel="nofollow" class="external text" href="https://hdl.handle.net/10657.1%2F2440">10657.1/2440</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=Predicting+CPU+Availability+of+a+Multi-core+Processor+Executing+Concurrent+Java+Threads&rft.place=Las+Vegas%2C+Nevada%2C+USA&rft.pages=551-557&rft.date=2011-07&rft_id=info%3Ahdl%2F10657.1%2F2440&rft.au=Khondker+S.+Hasan&rft.au=Nicolas+G.+Grounds&rft.au=John+K.+Antonio&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMulti-core+processor" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKhondker_S._HasanJohn_AntonioSridhar_Radhakrishnan2014" class="citation conference cs1">Khondker S. Hasan; John Antonio; Sridhar Radhakrishnan (February 2014). <i>A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing</i>. The 20th IEEE International Conference on High Performance Computer Architecture (HPCA-14) workshop. Orlando, FL, USA. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.13140%2FRG.2.1.3051.9207">10.13140/RG.2.1.3051.9207</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=A+New+Composite+CPU%2FMemory+Model+for+Predicting+Efficiency+of+Multi-core+Processing&rft.place=Orlando%2C+FL%2C+USA&rft.date=2014-02&rft_id=info%3Adoi%2F10.13140%2FRG.2.1.3051.9207&rft.au=Khondker+S.+Hasan&rft.au=John+Antonio&rft.au=Sridhar+Radhakrishnan&rfr_id=info%3Asid%2Fen.wikipedia.org%3AMulti-core+processor" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Multi-core_processor&action=edit&section=25" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.makeuseof.com/tag/processor-core-makeuseof-explains-2/">"What Is a Processor Core?"</a>—MakeUseOf</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20110424130713/http://embedded-computing.com/embedded-moves-multicore">"Embedded moves to multicore"</a>—<i>Embedded Computing Design</i></li> <li><a rel="nofollow" class="external text" href="https://spectrum.ieee.org/multicore-is-bad-news-for-supercomputers">"Multicore Is Bad News for Supercomputers"</a>—<i><a href="/wiki/IEEE_Spectrum" title="IEEE Spectrum">IEEE Spectrum</a></i></li> <li><a rel="nofollow" class="external text" href="https://www.slideshare.net/Talbott/architecting-solutions-for-the-manycore-future">Architecting solutions for the Manycore future</a>, published on Feb 19, 2010 (more than one dead link in the slide)</li></ul> <div class="navbox-styles"><style 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.navbox-odd{background-color:transparent}.mw-parser-output .navbox .hlist td dl,.mw-parser-output .navbox .hlist td ol,.mw-parser-output .navbox .hlist td ul,.mw-parser-output .navbox td.hlist dl,.mw-parser-output .navbox td.hlist ol,.mw-parser-output .navbox td.hlist ul{padding:0.125em 0}.mw-parser-output .navbox .navbar{display:block;font-size:100%}.mw-parser-output .navbox-title .navbar{float:left;text-align:left;margin-right:0.5em}body.skin--responsive .mw-parser-output .navbox-image img{max-width:none!important}@media print{body.ns-0 .mw-parser-output .navbox{display:none!important}}</style></div><div role="navigation" class="navbox" aria-labelledby="Processor_technologies" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style 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abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a class="mw-selflink selflink">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Parallel_computing" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Parallel_computing" title="Template:Parallel computing"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Parallel_computing" title="Template talk:Parallel computing"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Parallel_computing" title="Special:EditPage/Template:Parallel computing"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Parallel_computing" style="font-size:114%;margin:0 4em"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">General</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Distributed_computing" title="Distributed computing">Distributed computing</a></li> <li><a href="/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></li> <li><a href="/wiki/Massively_parallel" title="Massively parallel">Massively parallel</a></li> <li><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a></li> <li><a href="/wiki/High-performance_computing" title="High-performance computing">High-performance computing</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore processor</a></li> <li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li> <li><a href="/wiki/Computer_network" title="Computer network">Computer network</a></li> <li><a href="/wiki/Systolic_array" title="Systolic array">Systolic array</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Levels</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Thread</a></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Loop-level_parallelism" title="Loop-level parallelism">Loop</a></li> <li><a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">Pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> (SMT)</li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a> (SpMT)</li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Computer_multitasking#Cooperative_multitasking" title="Computer multitasking">Cooperative</a></li> <li><a href="/wiki/Bulldozer_(microarchitecture)#Bulldozer_core" title="Bulldozer (microarchitecture)">Clustered multi-thread</a> (CMT)</li> <li><a href="/wiki/Hardware_scout" title="Hardware scout">Hardware scout</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Theory</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Parallel_RAM" title="Parallel RAM">PRAM model</a></li> <li><a href="/wiki/Parallel_external_memory" title="Parallel external memory">PEM model</a></li> <li><a href="/wiki/Analysis_of_parallel_algorithms" title="Analysis of parallel algorithms">Analysis of parallel algorithms</a></li> <li><a href="/wiki/Amdahl%27s_law" title="Amdahl's law">Amdahl's law</a></li> <li><a href="/wiki/Gustafson%27s_law" title="Gustafson's law">Gustafson's law</a></li> <li><a href="/wiki/Cost_efficiency" title="Cost efficiency">Cost efficiency</a></li> <li><a href="/wiki/Karp%E2%80%93Flatt_metric" title="Karp–Flatt metric">Karp–Flatt metric</a></li> <li><a href="/wiki/Parallel_slowdown" title="Parallel slowdown">Slowdown</a></li> <li><a href="/wiki/Speedup" title="Speedup">Speedup</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Elements</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li> <li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Fiber_(computer_science)" title="Fiber (computer science)">Fiber</a></li> <li><a href="/wiki/Instruction_window" title="Instruction window">Instruction window</a></li> <li><a href="/wiki/Array_(data_structure)" title="Array (data structure)">Array</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Coordination</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Memory_coherence" title="Memory coherence">Memory coherence</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">Cache coherence</a></li> <li><a href="/wiki/Cache_invalidation" title="Cache invalidation">Cache invalidation</a></li> <li><a href="/wiki/Barrier_(computer_science)" title="Barrier (computer science)">Barrier</a></li> <li><a href="/wiki/Synchronization_(computer_science)" title="Synchronization (computer science)">Synchronization</a></li> <li><a href="/wiki/Application_checkpointing" title="Application checkpointing">Application checkpointing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_programming" title="Computer programming">Programming</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Stream_processing" title="Stream processing">Stream processing</a></li> <li><a href="/wiki/Dataflow_programming" title="Dataflow programming">Dataflow programming</a></li> <li><a href="/wiki/Parallel_programming_model" title="Parallel programming model">Models</a> <ul><li><a href="/wiki/Implicit_parallelism" title="Implicit parallelism">Implicit parallelism</a></li> <li><a href="/wiki/Explicit_parallelism" title="Explicit parallelism">Explicit parallelism</a></li> <li><a href="/wiki/Concurrency_(computer_science)" title="Concurrency (computer science)">Concurrency</a></li></ul></li> <li><a href="/wiki/Non-blocking_algorithm" title="Non-blocking algorithm">Non-blocking algorithm</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_hardware" title="Computer hardware">Hardware</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing</a> (SIMT)</li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow architecture</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelined processor</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar processor</a></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector processor</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessor</a> <ul><li><a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric</a></li> <li><a href="/wiki/Asymmetric_multiprocessing" title="Asymmetric multiprocessing">asymmetric</a></li></ul></li> <li><a href="/wiki/Semiconductor_memory" title="Semiconductor memory">Memory</a> <ul><li><a href="/wiki/Shared_memory" title="Shared memory">shared</a></li> <li><a href="/wiki/Distributed_memory" title="Distributed memory">distributed</a></li> <li><a href="/wiki/Distributed_shared_memory" title="Distributed shared memory">distributed shared</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">UMA</a></li> <li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Cache-only_memory_architecture" title="Cache-only memory architecture">COMA</a></li></ul></li> <li><a href="/wiki/Massively_parallel" title="Massively parallel">Massively parallel</a> computer</li> <li><a href="/wiki/Computer_cluster" title="Computer cluster">Computer cluster</a> <ul><li><a href="/wiki/Beowulf_cluster" title="Beowulf cluster">Beowulf cluster</a></li></ul></li> <li><a href="/wiki/Grid_computing" title="Grid computing">Grid computer</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/API" title="API">APIs</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ateji_PX" title="Ateji PX">Ateji PX</a></li> <li><a href="/wiki/Boost_(C%2B%2B_libraries)" title="Boost (C++ libraries)">Boost</a></li> <li><a href="/wiki/Chapel_(programming_language)" title="Chapel (programming language)">Chapel</a></li> <li><a href="/wiki/HPX" title="HPX">HPX</a></li> <li><a href="/wiki/Charm%2B%2B" title="Charm++">Charm++</a></li> <li><a href="/wiki/Cilk" title="Cilk">Cilk</a></li> <li><a href="/wiki/Coarray_Fortran" title="Coarray Fortran">Coarray Fortran</a></li> <li><a href="/wiki/CUDA" title="CUDA">CUDA</a></li> <li><a href="/wiki/Dryad_(programming)" title="Dryad (programming)">Dryad</a></li> <li><a href="/wiki/C%2B%2B_AMP" title="C++ AMP">C++ AMP</a></li> <li><a href="/wiki/Global_Arrays" title="Global Arrays">Global Arrays</a></li> <li><a href="/wiki/GPUOpen" title="GPUOpen">GPUOpen</a></li> <li><a href="/wiki/Message_Passing_Interface" title="Message Passing Interface">MPI</a></li> <li><a href="/wiki/OpenMP" title="OpenMP">OpenMP</a></li> <li><a href="/wiki/OpenCL" title="OpenCL">OpenCL</a></li> <li><a href="/wiki/OpenHMPP" title="OpenHMPP">OpenHMPP</a></li> <li><a href="/wiki/OpenACC" title="OpenACC">OpenACC</a></li> <li><a href="/wiki/Parallel_Extensions" title="Parallel Extensions">Parallel Extensions</a></li> <li><a href="/wiki/Parallel_Virtual_Machine" title="Parallel Virtual Machine">PVM</a></li> <li><a href="/wiki/Pthreads" title="Pthreads">pthreads</a></li> <li><a href="/wiki/RaftLib" title="RaftLib">RaftLib</a></li> <li><a href="/wiki/ROCm" title="ROCm">ROCm</a></li> <li><a href="/wiki/Unified_Parallel_C" title="Unified Parallel C">UPC</a></li> <li><a href="/wiki/Threading_Building_Blocks" title="Threading Building Blocks">TBB</a></li> <li><a href="/wiki/ZPL_(programming_language)" class="mw-redirect" title="ZPL (programming language)">ZPL</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Problems</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a 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