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double-purpose logic gates</title> <meta name="description" content="Search results for: double-purpose logic gates"> <meta name="keywords" content="double-purpose logic gates"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> 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action="https://publications.waset.org/abstracts/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="double-purpose logic gates"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 706</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: double-purpose logic gates</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">706</span> Design and Implementation of Testable Reversible Sequential Circuits Optimized Power</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=B.%20Manikandan">B. Manikandan</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Vijayaprabhu"> A. Vijayaprabhu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The conservative reversible gates are used to designed reversible sequential circuits. The sequential circuits are flip-flops and latches. The conservative logic gates are Feynman, Toffoli, and Fredkin. The design of two vectors testable sequential circuits based on conservative logic gates. All sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, master-slave flip-flops and double edge triggered (DET) flip-flops are presented. We also showed the application of the proposed approach toward 100% fault coverage for single missing/additional cell defect in the quantum- dot cellular automata (QCA) layout of the Fredkin gate. The conservative logic gates are in terms of complexity, speed, and area. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=DET" title="DET">DET</a>, <a href="https://publications.waset.org/abstracts/search?q=QCA" title=" QCA"> QCA</a>, <a href="https://publications.waset.org/abstracts/search?q=reversible%20logic%20gates" title=" reversible logic gates"> reversible logic gates</a>, <a href="https://publications.waset.org/abstracts/search?q=POS" title=" POS"> POS</a>, <a href="https://publications.waset.org/abstracts/search?q=SOP" title=" SOP"> SOP</a>, <a href="https://publications.waset.org/abstracts/search?q=latches" title=" latches"> latches</a>, <a href="https://publications.waset.org/abstracts/search?q=flip%20flops" title=" flip flops"> flip flops</a> </p> <a href="https://publications.waset.org/abstracts/42418/design-and-implementation-of-testable-reversible-sequential-circuits-optimized-power" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/42418.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">304</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">705</span> Low-Cost Reversible Logic Serial Multipliers with Error Detection Capability</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mojtaba%20Valinataj">Mojtaba Valinataj</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays reversible logic has received many attentions as one of the new fields for reducing the power consumption. On the other hand, the processing systems have weaknesses against different external effects. In this paper, some error detecting reversible logic serial multipliers are proposed by incorporating the parity-preserving gates. This way, the new designs are presented for signed parity-preserving serial multipliers based on the Booth's algorithm by exploiting the new arrangements of existing gates. The experimental results show that the proposed 4×4 multipliers in this paper reach up to 20%, 35%, and 41% enhancements in the number of constant inputs, quantum cost, and gate count, respectively, as the reversible logic criteria, compared to previous designs. Furthermore, all the proposed designs have been generalized for n×n multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Booth%E2%80%99s%20algorithm" title="Booth’s algorithm">Booth’s algorithm</a>, <a href="https://publications.waset.org/abstracts/search?q=error%20detection" title=" error detection"> error detection</a>, <a href="https://publications.waset.org/abstracts/search?q=multiplication" title=" multiplication"> multiplication</a>, <a href="https://publications.waset.org/abstracts/search?q=parity-preserving%20gates" title=" parity-preserving gates"> parity-preserving gates</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20computers" title=" quantum computers"> quantum computers</a>, <a href="https://publications.waset.org/abstracts/search?q=reversible%20logic" title=" reversible logic"> reversible logic</a> </p> <a href="https://publications.waset.org/abstracts/68832/low-cost-reversible-logic-serial-multipliers-with-error-detection-capability" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68832.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">228</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">704</span> Design of Parity-Preserving Reversible Logic Signed Array Multipliers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mojtaba%20Valinataj">Mojtaba Valinataj</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Reversible logic as a new favorable design domain can be used for various fields especially creating quantum computers because of its speed and intangible power consumption. However, its susceptibility to a variety of environmental effects may lead to yield the incorrect results. In this paper, because of the importance of multiplication operation in various computing systems, some novel reversible logic array multipliers are proposed with error detection capability by incorporating the parity-preserving gates. The new designs are presented for two main parts of array multipliers, partial product generation and multi-operand addition, by exploiting the new arrangements of existing gates, which results in two signed parity-preserving array multipliers. The experimental results reveal that the best proposed 4×4 multiplier in this paper reaches 12%, 24%, and 26% enhancements in the number of constant inputs, number of required gates, and quantum cost, respectively, compared to previous design. Moreover, the best proposed design is generalized for <em>n</em>×<em>n</em> multipliers with general formulations to estimate the main reversible logic criteria as the functions of the multiplier size. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=array%20multipliers" title="array multipliers">array multipliers</a>, <a href="https://publications.waset.org/abstracts/search?q=Baugh-Wooley%20method" title=" Baugh-Wooley method"> Baugh-Wooley method</a>, <a href="https://publications.waset.org/abstracts/search?q=error%20detection" title=" error detection"> error detection</a>, <a href="https://publications.waset.org/abstracts/search?q=parity-preserving%20gates" title=" parity-preserving gates"> parity-preserving gates</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20computers" title=" quantum computers"> quantum computers</a>, <a href="https://publications.waset.org/abstracts/search?q=reversible%20logic" title=" reversible logic"> reversible logic</a> </p> <a href="https://publications.waset.org/abstracts/68835/design-of-parity-preserving-reversible-logic-signed-array-multipliers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/68835.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">259</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">703</span> A Low-Voltage Synchronous Command for JFET Rectifiers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=P.%20Monginaud">P. Monginaud</a>, <a href="https://publications.waset.org/abstracts/search?q=J.%20C.%20Baudey"> J. C. Baudey </a> </p> <p class="card-text"><strong>Abstract:</strong></p> The synchronous, low-voltage command for JFET Rectifiers has many applications: indeed, replacing the traditional diodes by these components allows enhanced performances in gain, linearity and phase shift. We introduce here a new bridge, including JFET associated with pull-down, bipolar command systems, and double-purpose logic gates. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=synchronous" title="synchronous">synchronous</a>, <a href="https://publications.waset.org/abstracts/search?q=rectifier" title=" rectifier"> rectifier</a>, <a href="https://publications.waset.org/abstracts/search?q=MOSFET" title=" MOSFET"> MOSFET</a>, <a href="https://publications.waset.org/abstracts/search?q=JFET" title=" JFET"> JFET</a>, <a href="https://publications.waset.org/abstracts/search?q=bipolar%20command%20system" title=" bipolar command system"> bipolar command system</a>, <a href="https://publications.waset.org/abstracts/search?q=push-pull%20circuits" title=" push-pull circuits"> push-pull circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=double-purpose%20logic%20gates" title=" double-purpose logic gates"> double-purpose logic gates</a> </p> <a href="https://publications.waset.org/abstracts/4289/a-low-voltage-synchronous-command-for-jfet-rectifiers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/4289.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">365</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">702</span> A Soft Error Rates (SER) Evaluation Method of Combinational Logic Circuit Based on Linear Energy Transfers</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Man%20Li">Man Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Wanting%20Zhou"> Wanting Zhou</a>, <a href="https://publications.waset.org/abstracts/search?q=Lei%20Li"> Lei Li</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Communication stability is the primary concern of communication satellites. Communication satellites are easily affected by particle radiation to generate single event effects (SEE), which leads to soft errors (SE) of the combinational logic circuit. The existing research on soft error rates (SER) of the combined logic circuit is mostly based on the assumption that the logic gates being bombarded have the same pulse width. However, in the actual radiation environment, the pulse widths of the logic gates being bombarded are different due to different linear energy transfers (LET). In order to improve the accuracy of SER evaluation model, this paper proposes a soft error rate evaluation method based on LET. In this paper, the authors analyze the influence of LET on the pulse width of combinational logic and establish the pulse width model based on the LET. Based on this model, the error rate of test circuit ISCAS'85 is calculated. The effectiveness of the model is proved by comparing it with previous experiments. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=communication%20satellite" title="communication satellite">communication satellite</a>, <a href="https://publications.waset.org/abstracts/search?q=pulse%20width" title=" pulse width"> pulse width</a>, <a href="https://publications.waset.org/abstracts/search?q=soft%20error%20rates" title=" soft error rates"> soft error rates</a>, <a href="https://publications.waset.org/abstracts/search?q=LET" title=" LET"> LET</a> </p> <a href="https://publications.waset.org/abstracts/148147/a-soft-error-rates-ser-evaluation-method-of-combinational-logic-circuit-based-on-linear-energy-transfers" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/148147.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">172</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">701</span> A Connected Structure of All-Optical Logic Gate “NOT-AND”</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Roumaissa%20Derdour">Roumaissa Derdour</a>, <a href="https://publications.waset.org/abstracts/search?q=Lebbal%20Mohamed%20Redha"> Lebbal Mohamed Redha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> We present a study of the transmission of the all-optical logic gate using a structure connected with a triangular photonic crystal lattice that is improved. The proposed logic gate consists of a photonic crystal nano-resonator formed by changing the size of the air holes. In addition to the simplicity, the response time is very short, and the designed nano-resonator increases the bit rate of the logic gate. The two-dimensional finite difference time domain (2DFDTD) method is used to simulate the structure; the transmission obtained is about 98% with very negligible losses. The proposed photonic crystal AND logic gate is widely used in future integrated optical microelectronics. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=logic%20gates" title="logic gates">logic gates</a>, <a href="https://publications.waset.org/abstracts/search?q=photonic%20crystals" title=" photonic crystals"> photonic crystals</a>, <a href="https://publications.waset.org/abstracts/search?q=optical%20integrated%20circuits" title=" optical integrated circuits"> optical integrated circuits</a>, <a href="https://publications.waset.org/abstracts/search?q=resonant%20cavities" title=" resonant cavities"> resonant cavities</a> </p> <a href="https://publications.waset.org/abstracts/161597/a-connected-structure-of-all-optical-logic-gate-not-and" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/161597.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">98</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">700</span> Mathematical and Fuzzy Logic in the Interpretation of the Quran</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Morteza%20Khorrami">Morteza Khorrami</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The logic as an intellectual infrastructure plays an essential role in the Islamic sciences. Hence, there are a few of the verses of the Holy Quran that their interpretation is not possible due to lack of proper logic. In many verses in the Quran, argument and the respondent has requested from the audience that shows the logic rule is in the Quran. The paper which use a descriptive and analytic method, tries to show the role of logic in understanding of the Quran reasoning methods and display some of Quranic statements with mathematical symbols and point that we can help these symbols for interesting and interpretation and answering to some questions and doubts. In this paper, this problem has been mentioned that the Quran did not use two-valued logic (Aristotelian) in all cases, but the fuzzy logic can also be searched in the Quran. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=aristotelian%20logic" title="aristotelian logic">aristotelian logic</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title=" fuzzy logic"> fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=interpretation" title=" interpretation"> interpretation</a>, <a href="https://publications.waset.org/abstracts/search?q=Holy%20Quran" title=" Holy Quran"> Holy Quran</a> </p> <a href="https://publications.waset.org/abstracts/37444/mathematical-and-fuzzy-logic-in-the-interpretation-of-the-quran" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/37444.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">676</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">699</span> Dual-Rail Logic Unit in Double Pass Transistor Logic</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hamdi%20Belgacem">Hamdi Belgacem</a>, <a href="https://publications.waset.org/abstracts/search?q=Fradi%20Aymen"> Fradi Aymen</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper we present a low power, low cost differential logic unit (LU). The proposed LU receives dual-rail inputs and generates dual-rail outputs. The proposed circuit can be used in Arithmetic and Logic Units (ALU) of processor. It can be also dedicated for self-checking applications based on dual duplication code. Four logic functions as well as their inverses are implemented within a single Logic Unit. The hardware overhead for the implementation of the proposed LU is lower than the hardware overhead required for standard LU implemented with standard CMOS logic style. This new implementation is attractive as fewer transistors are required to implement important logic functions. The proposed differential logic unit can perform 8 Boolean logical operations by using only 16 transistors. Spice simulations using a 32 nm technology was utilized to evaluate the performance of the proposed circuit and to prove its acceptable electrical behaviour. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=differential%20logic%20unit" title="differential logic unit">differential logic unit</a>, <a href="https://publications.waset.org/abstracts/search?q=double%20pass%20transistor%20logic" title=" double pass transistor logic"> double pass transistor logic</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power%20CMOS%20design" title=" low power CMOS design"> low power CMOS design</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20cost%20CMOS%20design" title=" low cost CMOS design"> low cost CMOS design</a> </p> <a href="https://publications.waset.org/abstracts/35814/dual-rail-logic-unit-in-double-pass-transistor-logic" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/35814.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">452</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">698</span> Autonomous Quantum Competitive Learning</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohammed%20A.%20Zidan">Mohammed A. Zidan</a>, <a href="https://publications.waset.org/abstracts/search?q=Alaa%20Sagheer"> Alaa Sagheer</a>, <a href="https://publications.waset.org/abstracts/search?q=Nasser%20Metwally"> Nasser Metwally</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Real-time learning is an important goal that most of artificial intelligence researches try to achieve it. There are a lot of problems and applications which require low cost learning such as learn a robot to be able to classify and recognize patterns in real time and real-time recall. In this contribution, we suggest a model of quantum competitive learning based on a series of quantum gates and additional operator. The proposed model enables to recognize any incomplete patterns, where we can increase the probability of recognizing the pattern at the expense of the undesired ones. Moreover, these undesired ones could be utilized as new patterns for the system. The proposed model is much better compared with classical approaches and more powerful than the current quantum competitive learning approaches. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=competitive%20learning" title="competitive learning">competitive learning</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20gates" title=" quantum gates"> quantum gates</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20gates" title=" quantum gates"> quantum gates</a>, <a href="https://publications.waset.org/abstracts/search?q=winner-take-all" title=" winner-take-all"> winner-take-all</a> </p> <a href="https://publications.waset.org/abstracts/25398/autonomous-quantum-competitive-learning" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/25398.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">472</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">697</span> Theoretical Study of the Photophysical Properties and Potential Use of Pseudo-Hemi-Indigo Derivatives as Molecular Logic Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Christina%20Eleftheria%20Tzeliou">Christina Eleftheria Tzeliou</a>, <a href="https://publications.waset.org/abstracts/search?q=Demeter%20Tzeli"> Demeter Tzeli</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Introduction: Molecular Logic Gates (MLGs) are molecular machines that can perform complex work, such as solving logic operations. Molecular switches, which are molecules that can experience chemical changes are examples of successful types of MLGs. Recently, Quintana-Romero and Ariza-Castolo studied experimentally six stable pseudo-hemi-indigo-derived MLGs capable of solving complex logic operations. The MLG design relies on a molecular switch that experiences Z and E isomerism, thus the molecular switch's axis has to be a double bond. The hemi-indigo structure was preferred for the assembly of molecular switches due to its interaction with visible light. Z and E pseudo-hemi-indigo isomers can also be utilized for selective isomerization as they have distinct absorption spectra. Methodology: Here, the photophysical properties of pseudo-hemi-indigo derivatives are examined, i.e., derivatives of molecule 1 with anthracene, naphthalene, phenanthrene, pyrene, and pyrrole. In conjunction with some trials that were conducted, the level of theory mentioned subsequently was determined. The structures under study were optimized in both cis and trans conformations at the PBE0/6-31G(d,p) level of theory. The absorption spectra of the structures were calculated at PBE0/DEF2TZVP. In all cases, the absorption spectra of the studied systems were calculated including up to 50 singlet- and triplet-spin excited electronic states. Transition states (cis → cis, cis → trans, and trans → trans) were obtained in cases where it was possible, with PBE0/6-31G(d,p) for the optimization of the transition states and PBE0/DEF2TZVP for the respective absorption spectra. Emission spectra were obtained for the first singlet state of each molecule in cis both and trans conformations in PBE0/DEF2TZVP as well. All studies were performed in chloroform solvent that was added as a dielectric constant and the polarizable continuum model was also employed. Findings: Shifts of up to 25 nm are observed in the absorption spectra due to cis-trans isomerization, while the transition state is shifted up to about 150 nm. The electron density distribution is also examined, where charge transfer and electron transfer phenomena are observed regarding the three excitations of interest, i.e., H-1 → L, H → L and H → L+1. Emission spectra calculations were also carried out at PBE0/DEF2TZVP for the complete investigation of these molecules. Using protonation as input, selected molecules act as MLGs. Conclusion: Theoretical data so far indicate that both cis-trans isomerization, and cis-cis and trans-trans conformer isomerization affect the UV-visible absorption and emission spectra. Specifically, shifts of up to 30 nm are observed, while the transition state is shifted up to about 150 nm in cis-cis isomerization. The computational data obtained are in agreement with available experimental data, which have predicted that the pyrrole derivative is a MLG at 445 nm and 400 nm using protonation as input, while the anthracene derivative is a MLG that operates at 445 nm using protonation as input. Finally, it was found that selected molecules are candidates as MLG using protonation and light as inputs. These MLGs could be used as chemical sensors or as particular intracellular indicators, among several other applications. Acknowledgements: The author acknowledges the Hellenic Foundation for Research and Innovation for the financial support of this project (Fellowship Number: 21006). <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=absorption%20spectra" title="absorption spectra">absorption spectra</a>, <a href="https://publications.waset.org/abstracts/search?q=DFT%20calculations" title=" DFT calculations"> DFT calculations</a>, <a href="https://publications.waset.org/abstracts/search?q=isomerization" title=" isomerization"> isomerization</a>, <a href="https://publications.waset.org/abstracts/search?q=molecular%20logic%20gates" title=" molecular logic gates"> molecular logic gates</a> </p> <a href="https://publications.waset.org/abstracts/192447/theoretical-study-of-the-photophysical-properties-and-potential-use-of-pseudo-hemi-indigo-derivatives-as-molecular-logic-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/192447.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">21</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">696</span> Dynamic Fault Tree Analysis of Dynamic Positioning System through Monte Carlo Approach</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=A.%20S.%20Cheliyan">A. S. Cheliyan</a>, <a href="https://publications.waset.org/abstracts/search?q=S.%20K.%20Bhattacharyya"> S. K. Bhattacharyya </a> </p> <p class="card-text"><strong>Abstract:</strong></p> Dynamic Positioning System (DPS) is employed in marine vessels of the offshore oil and gas industry. It is a computer controlled system to automatically maintain a ship’s position and heading by using its own thrusters. Reliability assessment of the same can be analyzed through conventional fault tree. However, the complex behaviour like sequence failure, redundancy management and priority of failing of events cannot be analyzed by the conventional fault trees. The Dynamic Fault Tree (DFT) addresses these shortcomings of conventional Fault Tree by defining additional gates called dynamic gates. Monte Carlo based simulation approach has been adopted for the dynamic gates. This method of realistic modeling of DPS gives meaningful insight into the system reliability and the ability to improve the same. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=dynamic%20positioning%20system" title="dynamic positioning system">dynamic positioning system</a>, <a href="https://publications.waset.org/abstracts/search?q=dynamic%20fault%20tree" title=" dynamic fault tree"> dynamic fault tree</a>, <a href="https://publications.waset.org/abstracts/search?q=Monte%20Carlo%20simulation" title=" Monte Carlo simulation"> Monte Carlo simulation</a>, <a href="https://publications.waset.org/abstracts/search?q=reliability%20assessment" title=" reliability assessment "> reliability assessment </a> </p> <a href="https://publications.waset.org/abstracts/58683/dynamic-fault-tree-analysis-of-dynamic-positioning-system-through-monte-carlo-approach" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/58683.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">774</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">695</span> Key Performance Indicators and the Model for Achieving Digital Inclusion for Smart Cities</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Khalid%20Obaed%20Mahmod">Khalid Obaed Mahmod</a>, <a href="https://publications.waset.org/abstracts/search?q=Mesut%20Cevik"> Mesut Cevik</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The term smart city has appeared recently and was accompanied by many definitions and concepts, but as a simplified and clear definition, it can be said that the smart city is a geographical location that has gained efficiency and flexibility in providing public services to citizens through its use of technological and communication technologies, and this is what distinguishes it from other cities. Smart cities connect the various components of the city through the main and sub-networks in addition to a set of applications and thus be able to collect data that is the basis for providing technological solutions to manage resources and provide services. The basis of the work of the smart city is the use of artificial intelligence and the technology of the Internet of Things. The work presents the concept of smart cities, the pillars, standards, and evaluation indicators on which smart cities depend, and the reasons that prompted the world to move towards its establishment. It also provides a simplified hypothetical way to measure the ideal smart city model by defining some indicators and key pillars, simulating them with logic circuits, and testing them to determine if the city can be considered an ideal smart city or not. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=factors" title="factors">factors</a>, <a href="https://publications.waset.org/abstracts/search?q=indicators" title=" indicators"> indicators</a>, <a href="https://publications.waset.org/abstracts/search?q=logic%20gates" title=" logic gates"> logic gates</a>, <a href="https://publications.waset.org/abstracts/search?q=pillars" title=" pillars"> pillars</a>, <a href="https://publications.waset.org/abstracts/search?q=smart%20city" title=" smart city"> smart city</a> </p> <a href="https://publications.waset.org/abstracts/150374/key-performance-indicators-and-the-model-for-achieving-digital-inclusion-for-smart-cities" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/150374.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">150</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">694</span> Transformative Concept of Logic to Islamic Science: Reflections on Al-Ghazālī's Influence</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Umar%20Sheikh%20Tahir">Umar Sheikh Tahir</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Before al-Ghazālī, Islamic scholars perceived logic as an intrusive knowledge. The knowledge therefore, did not receive ample attention among scholars on how it should be adapted into Islamic sciences. General scholarship in that period rejects logic as an instrumental knowledge. This attitude became unquestionable to the scholars from different perspectives with diversification of suggestions in the pre-al-Ghazālī’s period. However, al-Ghazālī proclaimed with new perspective that transform Logic from ‘intrusive knowledge’ to a useful tool for Islamic sciences. This study explores the contributions of al-Ghazālī to epistemology regarding the use and the relevance of Logic. The study applies qualitative research methodology dealing strictly with secondary data from medieval age and contemporary sources. The study concludes that al-Ghazālī’s contributions which supported the transformation of Logic to useful tool in the Muslim world were drawn from his experience within Islamic tradition. He succeeded in reconciling Islamic tradition with the wisdom of Greek sciences. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Al-Ghaz%C4%81l%C4%AB" title="Al-Ghazālī">Al-Ghazālī</a>, <a href="https://publications.waset.org/abstracts/search?q=classical%20logic" title=" classical logic"> classical logic</a>, <a href="https://publications.waset.org/abstracts/search?q=epistemology" title=" epistemology"> epistemology</a>, <a href="https://publications.waset.org/abstracts/search?q=Islamdom%20and%20Islamic%20sciences" title=" Islamdom and Islamic sciences"> Islamdom and Islamic sciences</a> </p> <a href="https://publications.waset.org/abstracts/56474/transformative-concept-of-logic-to-islamic-science-reflections-on-al-ghazalis-influence" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/56474.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">250</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">693</span> Area Efficient Carry Select Adder Using XOR Gate Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mahendrapal%20Singh%20Pachlaniya">Mahendrapal Singh Pachlaniya</a>, <a href="https://publications.waset.org/abstracts/search?q=Laxmi%20Kumre"> Laxmi Kumre</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The AOI (AND – OR- INVERTER) based design of XOR gate is proposed in this paper with less number of gates. This new XOR gate required four basic gates and basic gate include only AND, OR, Inverter (AOI). Conventional XOR gate required five basic gates. Ripple Carry Adder (RCA) used in parallel addition but propagation delay time is large. RCA replaced with Carry Select Adder (CSLA) to reduce propagation delay time. CSLA design with dual RCA considering carry = ‘0’ and carry = ‘1’, so it is not an area efficient adder. To make area efficient, modified CSLA is designed with single RCA considering carry = ‘0’ and another RCA considering carry = ‘1’ replaced with Binary to Excess 1 Converter (BEC). Now replacement of conventional XOR gate by new design of XOR gate in modified CSLA reduces much area compared to regular CSLA and modified CSLA. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CSLA" title="CSLA">CSLA</a>, <a href="https://publications.waset.org/abstracts/search?q=BEC" title=" BEC"> BEC</a>, <a href="https://publications.waset.org/abstracts/search?q=XOR%20gate" title=" XOR gate"> XOR gate</a>, <a href="https://publications.waset.org/abstracts/search?q=area%20efficient" title=" area efficient"> area efficient</a> </p> <a href="https://publications.waset.org/abstracts/41782/area-efficient-carry-select-adder-using-xor-gate-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/41782.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">361</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">692</span> Analysis on Yogyakarta Istimewa Citygates on Urban Area Arterial Roads</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Nizar%20Caraka%20Trihanasia">Nizar Caraka Trihanasia</a>, <a href="https://publications.waset.org/abstracts/search?q=Suparwoko"> Suparwoko</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The purpose of this paper is to analyze the design model of city gates on arterial roads as Yogyakarta’s “Istimewa” (special) identity. City marketing has become a trend among cities in the past few years. It began to compete with each other in promoting their identity to the world. One of the easiest ways to recognize the identity is by knowing the image of the city which can be seen through architectural buildings or urban elements. The idea is to recognize how the image of the city can represent Yogyakarta’s identity, which is limited to the contribution of the city gates distinctiveness on Yogyakarta urban area. This study has concentrated on the aspect of city gates as built environment that provides a diversity, configuration and scale of development that promotes a sense of place and community. The visual analysis will be conducted to interpreted the existing Yogyakarta city gates (as built environment) focussing on some variables of 1) character and pattern, 2) circulation system establishment, and 3) open space utilisation. Literature review and site survey are also conducted to understand the relationship between the built environment and the sense of place in the community. This study suggests that visually the Yogyakarta city gate model has strong visual characters and pattern by using the concept of a sense of place of Yogyakarta community value. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=visual%20analysis" title="visual analysis">visual analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=model" title=" model"> model</a>, <a href="https://publications.waset.org/abstracts/search?q=Yogyakarta%20%E2%80%9CIstimewa%E2%80%9D" title=" Yogyakarta “Istimewa”"> Yogyakarta “Istimewa”</a>, <a href="https://publications.waset.org/abstracts/search?q=citygates" title=" citygates"> citygates</a> </p> <a href="https://publications.waset.org/abstracts/53761/analysis-on-yogyakarta-istimewa-citygates-on-urban-area-arterial-roads" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/53761.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">258</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">691</span> Maximum Power Point Tracking Using FLC Tuned with GA</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mohamed%20Amine%20Haraoubia">Mohamed Amine Haraoubia</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdelaziz%20Hamzaoui"> Abdelaziz Hamzaoui</a>, <a href="https://publications.waset.org/abstracts/search?q=Najib%20Essounbouli"> Najib Essounbouli</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The pursuit of the MPPT has led to the development of many kinds of controllers, one of which is the Fuzzy Logic Controller, which has proven its worth. To further tune this controller this paper will discuss and analyze the use of Genetic Algorithms to tune the Fuzzy Logic Controller. It will provide an introduction to both systems, and test their compatibility and performance. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic%20controller" title="fuzzy logic controller">fuzzy logic controller</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title=" fuzzy logic"> fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=genetic%20algorithm" title=" genetic algorithm"> genetic algorithm</a>, <a href="https://publications.waset.org/abstracts/search?q=maximum%20power%20point" title=" maximum power point"> maximum power point</a>, <a href="https://publications.waset.org/abstracts/search?q=maximum%20power%20point%20tracking" title=" maximum power point tracking"> maximum power point tracking</a> </p> <a href="https://publications.waset.org/abstracts/7055/maximum-power-point-tracking-using-flc-tuned-with-ga" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/7055.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">373</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">690</span> Improving Ride Comfort of a Bus Using Fuzzy Logic Controlled Suspension</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mujde%20Turkkan">Mujde Turkkan</a>, <a href="https://publications.waset.org/abstracts/search?q=Nurkan%20Yagiz"> Nurkan Yagiz</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this study an active controller is presented for vibration suppression of a full-bus model. The bus is modelled having seven degrees of freedom. Using the achieved model via Lagrange Equations the system equations of motion are derived. The suspensions of the bus model include air springs with two auxiliary chambers are used. Fuzzy logic controller is used to improve the ride comfort. The numerical results, verifies that the presented fuzzy logic controller improves the ride comfort. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=ride%20comfort" title="ride comfort">ride comfort</a>, <a href="https://publications.waset.org/abstracts/search?q=air%20spring" title=" air spring"> air spring</a>, <a href="https://publications.waset.org/abstracts/search?q=bus" title=" bus"> bus</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic%20controller" title=" fuzzy logic controller"> fuzzy logic controller</a> </p> <a href="https://publications.waset.org/abstracts/3740/improving-ride-comfort-of-a-bus-using-fuzzy-logic-controlled-suspension" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/3740.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">430</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">689</span> A Novel Approach to Asynchronous State Machine Modeling on Multisim for Avoiding Function Hazards</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Parisi%20L.">Parisi L.</a>, <a href="https://publications.waset.org/abstracts/search?q=Hamili%20D."> Hamili D.</a>, <a href="https://publications.waset.org/abstracts/search?q=Azlan%20N."> Azlan N.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The aim of this study was to design and simulate a particular type of Asynchronous State Machine (ASM), namely a ‘traffic light controller’ (TLC), operated at a frequency of 0.5 Hz. The design task involved two main stages: firstly, designing a 4-bit binary counter using J-K flip flops as the timing signal and subsequently, attaining the digital logic by deploying ASM design process. The TLC was designed such that it showed a sequence of three different colours, i.e. red, yellow and green, corresponding to set thresholds by deploying the least number of AND, OR and NOT gates possible. The software Multisim was deployed to design such circuit and simulate it for circuit troubleshooting in order for it to display the output sequence of the three different colours on the traffic light in the correct order. A clock signal, an asynchronous 4-bit binary counter that was designed through the use of J-K flip flops along with an ASM were used to complete this sequence, which was programmed to be repeated indefinitely. Eventually, the circuit was debugged and optimized, thus displaying the correct waveforms of the three outputs through the logic analyzer. However, hazards occurred when the frequency was increased to 10 MHz. This was attributed to delays in the feedback being too high. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=asynchronous%20state%20machine" title="asynchronous state machine">asynchronous state machine</a>, <a href="https://publications.waset.org/abstracts/search?q=traffic%20light%20controller" title=" traffic light controller"> traffic light controller</a>, <a href="https://publications.waset.org/abstracts/search?q=circuit%20design" title=" circuit design"> circuit design</a>, <a href="https://publications.waset.org/abstracts/search?q=digital%20electronics" title=" digital electronics"> digital electronics</a> </p> <a href="https://publications.waset.org/abstracts/22349/a-novel-approach-to-asynchronous-state-machine-modeling-on-multisim-for-avoiding-function-hazards" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/22349.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">429</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">688</span> Fault Tolerant and Testable Designs of Reversible Sequential Building Blocks</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Vishal%20Pareek">Vishal Pareek</a>, <a href="https://publications.waset.org/abstracts/search?q=Shubham%20Gupta"> Shubham Gupta</a>, <a href="https://publications.waset.org/abstracts/search?q=Sushil%20Chandra%20Jain"> Sushil Chandra Jain</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With increasing high-speed computation demand the power consumption, heat dissipation and chip size issues are posing challenges for logic design with conventional technologies. Recovery of bit loss and bit errors is other issues that require reversibility and fault tolerance in the computation. The reversible computing is emerging as an alternative to conventional technologies to overcome the above problems and helpful in a diverse area such as low-power design, nanotechnology, quantum computing. Bit loss issue can be solved through unique input-output mapping which require reversibility and bit error issue require the capability of fault tolerance in design. In order to incorporate reversibility a number of combinational reversible logic based circuits have been developed. However, very few sequential reversible circuits have been reported in the literature. To make the circuit fault tolerant, a number of fault model and test approaches have been proposed for reversible logic. In this paper, we have attempted to incorporate fault tolerance in sequential reversible building blocks such as D flip-flop, T flip-flop, JK flip-flop, R-S flip-flop, Master-Slave D flip-flop, and double edge triggered D flip-flop by making them parity preserving. The importance of this proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault and single bit fault. In our opinion our design of reversible building blocks is superior to existing designs in term of quantum cost, hardware complexity, constant input, garbage output, number of gates and design of online testable D flip-flop have been proposed for the first time. We hope our work can be extended for building complex reversible sequential circuits. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=parity%20preserving%20gate" title="parity preserving gate">parity preserving gate</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20computing" title=" quantum computing"> quantum computing</a>, <a href="https://publications.waset.org/abstracts/search?q=fault%20tolerance" title=" fault tolerance"> fault tolerance</a>, <a href="https://publications.waset.org/abstracts/search?q=flip-flop" title=" flip-flop"> flip-flop</a>, <a href="https://publications.waset.org/abstracts/search?q=sequential%20reversible%20logic" title=" sequential reversible logic"> sequential reversible logic</a> </p> <a href="https://publications.waset.org/abstracts/12069/fault-tolerant-and-testable-designs-of-reversible-sequential-building-blocks" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/12069.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">545</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">687</span> Future of Nanotechnology in Digital MacDraw</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Pejman%20Hosseinioun">Pejman Hosseinioun</a>, <a href="https://publications.waset.org/abstracts/search?q=Abolghasem%20Ghasempour"> Abolghasem Ghasempour</a>, <a href="https://publications.waset.org/abstracts/search?q=Elham%20Gholami"> Elham Gholami</a>, <a href="https://publications.waset.org/abstracts/search?q=Hamed%20Sarbazi"> Hamed Sarbazi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Considering the development in global semiconductor technology, it is anticipated that gadgets such as diodes and resonant transistor tunnels (RTD/RTT), Single electron transistors (SET) and quantum cellular automata (QCA) will substitute CMOS (Complementary Metallic Oxide Semiconductor) gadgets in many applications. Unfortunately, these new technologies cannot disembark the common Boolean logic efficiently and are only appropriate for liminal logic. Therefor there is no doubt that with the development of these new gadgets it is necessary to find new MacDraw technologies which are compatible with them. Resonant transistor tunnels (RTD/RTT) and circuit MacDraw with enhanced computing abilities are candida for accumulating Nano criterion in the future. Quantum cellular automata (QCA) are also advent Nano technological gadgets for electrical circuits. Advantages of these gadgets such as higher speed, smaller dimensions, and lower consumption loss are of great consideration. QCA are basic gadgets in manufacturing gates, fuses and memories. Regarding the complex Nano criterion physical entity, circuit designers can focus on logical and constructional design to decrease complication in MacDraw. Moreover Single electron technology (SET) is another noteworthy gadget considered in Nano technology. This article is a survey in future of Nano technology in digital MacDraw. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=nano%20technology" title="nano technology">nano technology</a>, <a href="https://publications.waset.org/abstracts/search?q=resonant%20transistor%20tunnels" title=" resonant transistor tunnels"> resonant transistor tunnels</a>, <a href="https://publications.waset.org/abstracts/search?q=quantum%20cellular%20automata" title=" quantum cellular automata"> quantum cellular automata</a>, <a href="https://publications.waset.org/abstracts/search?q=semiconductor" title=" semiconductor"> semiconductor</a> </p> <a href="https://publications.waset.org/abstracts/37247/future-of-nanotechnology-in-digital-macdraw" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/37247.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">265</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">686</span> Modelling and Control of Electrohydraulic System Using Fuzzy Logic Algorithm</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hajara%20Abdulkarim%20Aliyu">Hajara Abdulkarim Aliyu</a>, <a href="https://publications.waset.org/abstracts/search?q=Abdulbasid%20Ismail%20Isa"> Abdulbasid Ismail Isa</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This research paper studies electrohydraulic system for its role in position and motion control system and develops as mathematical model describing the behaviour of the system. The research further proposes Fuzzy logic and conventional PID controllers in order to achieve both accurate positioning of the payload and overall improvement of the system performance. The simulation result shows Fuzzy logic controller has a superior tracking performance and high disturbance rejection efficiency for its shorter settling time, less overshoot, smaller values of integral of absolute and deviation errors over the conventional PID controller at all the testing conditions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=electrohydraulic" title="electrohydraulic">electrohydraulic</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title=" fuzzy logic"> fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=modelling" title=" modelling"> modelling</a>, <a href="https://publications.waset.org/abstracts/search?q=NZ-PID" title=" NZ-PID"> NZ-PID</a> </p> <a href="https://publications.waset.org/abstracts/46295/modelling-and-control-of-electrohydraulic-system-using-fuzzy-logic-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/46295.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">470</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">685</span> Application of Fuzzy Logic in Voltage Regulation of Radial Feeder with Distributed Generators</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Anubhav%20Shrivastava">Anubhav Shrivastava</a>, <a href="https://publications.waset.org/abstracts/search?q=Lakshya%20Bhat"> Lakshya Bhat</a>, <a href="https://publications.waset.org/abstracts/search?q=Shivarudraswamy"> Shivarudraswamy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Distributed Generation is the need of the hour. With current advancements in the DG technology, there are some major issues that need to be tackled in order to make this method of generation of energy more efficient and feasible. Among other problems, the control in voltage is the major issue that needs to be addressed. This paper focuses on control of voltage using reactive power control of DGs with the help of fuzzy logic. The membership functions have been defined accordingly and the control of the system is achieved. Finally, with the help of simulation results in Matlab, the control of voltage within the tolerance limit set (+/- 5%) is achieved. The voltage waveform graphs for the IEEE 14 bus system are obtained by using simple algorithm with MATLAB and then with fuzzy logic for 14 bus system. The goal of this project was to control the voltage within limits by controlling the reactive power of the DG using fuzzy logic. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=distributed%20generation" title="distributed generation">distributed generation</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title=" fuzzy logic"> fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=matlab" title=" matlab"> matlab</a>, <a href="https://publications.waset.org/abstracts/search?q=newton%20raphson" title=" newton raphson"> newton raphson</a>, <a href="https://publications.waset.org/abstracts/search?q=IEEE%2014%20bus" title=" IEEE 14 bus"> IEEE 14 bus</a>, <a href="https://publications.waset.org/abstracts/search?q=voltage%20regulation" title=" voltage regulation"> voltage regulation</a>, <a href="https://publications.waset.org/abstracts/search?q=radial%20network" title=" radial network"> radial network</a> </p> <a href="https://publications.waset.org/abstracts/31759/application-of-fuzzy-logic-in-voltage-regulation-of-radial-feeder-with-distributed-generators" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/31759.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">637</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">684</span> Mediatization of Politics and Democracy in Pakistan: An Interpretative Phenomenological Analysis</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Shahid%20Imran">Shahid Imran</a> </p> <p class="card-text"><strong>Abstract:</strong></p> 'Mediatization' has influenced the politics by shaping and transforming the attitudes and practices of political actors. It is a serious challenge to democracy in today’s era. This study aims to analyze the dynamics of media politics interplay in Pakistan and the contextual factors which govern this interplay. It will also address the perceived influence of media on the practices of politicians from the perspectives of the actors. The objectives have been achieved qualitatively through Interpretive Phenomenological Analysis (IPA). The phenomenological data have been collected using semi-structured interviews of journalists and politicians of Pakistan. The findings depict that politics in Pakistan is more driven by media logic than political or democratic logic. Media and politics have a ‘Tom and Jerry’ relationship. Political ecology is highly media-induced: politicians strategically adopt and adapt the media logic to be in the ‘media spotlight’; journalists, on the other hands, do not practice ‘fair journalism rather a more politically parallelized. The mediatized political communication behaviours of the actors are the undermining the public service logic and affecting the spirit of democracy in Pakistan. The study offers some valued implications for media, politicians and policy makers. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=medialization" title="medialization">medialization</a>, <a href="https://publications.waset.org/abstracts/search?q=media%20logic" title=" media logic"> media logic</a>, <a href="https://publications.waset.org/abstracts/search?q=politics" title=" politics"> politics</a>, <a href="https://publications.waset.org/abstracts/search?q=political%20logic" title=" political logic"> political logic</a> </p> <a href="https://publications.waset.org/abstracts/95473/mediatization-of-politics-and-democracy-in-pakistan-an-interpretative-phenomenological-analysis" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/95473.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">224</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">683</span> Intelligent and Optimized Placement for CPLD Devices</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelkader%20Hadjoudja">Abdelkader Hadjoudja</a>, <a href="https://publications.waset.org/abstracts/search?q=Hajar%20Bouazza"> Hajar Bouazza</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The PLD/CPLD devices are widely used for logic synthesis since several decades. Based on sum of product terms (PTs) architecture, the PLD/CPLD offer a high degree of flexibility to support various application requirements. They are suitable for large combinational logic, finite state machines as well as intensive I/O designs. CPLDs offer very predictable timing characteristics and are therefore ideal for critical control applications. This paper describes how the logic synthesis techniques, such as 1) XOR detection, 2) logic doubling, 3) complement of a Boolean function are combined, applied and used to optimize the CPLDs devices architecture that is based on PAL-like macrocells. Our goal is to use these techniques for minimizing the number of macrocells required to implement a circuit and minimize the delay of mapped circuit. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=CPLD" title="CPLD">CPLD</a>, <a href="https://publications.waset.org/abstracts/search?q=doubling" title=" doubling"> doubling</a>, <a href="https://publications.waset.org/abstracts/search?q=optimization" title=" optimization"> optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=XOR" title=" XOR"> XOR</a> </p> <a href="https://publications.waset.org/abstracts/8359/intelligent-and-optimized-placement-for-cpld-devices" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/8359.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">282</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">682</span> Soliton Interaction in Multi-Core Optical Fiber: Application to WDM System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=S.%20Arun%20Prakash">S. Arun Prakash</a>, <a href="https://publications.waset.org/abstracts/search?q=V.%20Malathi"> V. Malathi</a>, <a href="https://publications.waset.org/abstracts/search?q=M.%20S.%20Mani%20Rajan"> M. S. Mani Rajan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The analytical bright two soliton solution of the 3-coupled nonlinear Schrödinger equations with variable coefficients in birefringent optical fiber is obtained by Darboux transformation method. To the design of ultra-speed optical devices, Soliton interaction and control in birefringence fiber is investigated. Lax pair is constructed for N coupled NLS system through AKNS method. Using two soliton solution, we demonstrate different interaction behaviors of solitons in birefringent fiber depending on the choice of control parameters. Our results shows that interactions of optical solitons have some specific applications such as construction of logic gates, optical computing, soliton switching, and soliton amplification in wavelength division multiplexing (WDM) system. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=optical%20soliton" title="optical soliton">optical soliton</a>, <a href="https://publications.waset.org/abstracts/search?q=soliton%20interaction" title=" soliton interaction"> soliton interaction</a>, <a href="https://publications.waset.org/abstracts/search?q=soliton%20switching" title=" soliton switching"> soliton switching</a>, <a href="https://publications.waset.org/abstracts/search?q=WDM" title=" WDM"> WDM</a> </p> <a href="https://publications.waset.org/abstracts/37276/soliton-interaction-in-multi-core-optical-fiber-application-to-wdm-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/37276.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">505</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">681</span> Prediction of Coronary Heart Disease Using Fuzzy Logic</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Elda%20Maraj">Elda Maraj</a>, <a href="https://publications.waset.org/abstracts/search?q=Shkelqim%20Kuka"> Shkelqim Kuka</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Coronary heart disease causes many deaths in the world. Unfortunately, this problem will continue to increase in the future. In this paper, a fuzzy logic model to predict coronary heart disease is presented. This model has been developed with seven input variables and one output variable that was implemented for 30 patients in Albania. Here fuzzy logic toolbox of MATLAB is used. Fuzzy model inputs are considered as cholesterol, blood pressure, physical activity, age, BMI, smoking, and diabetes, whereas the output is the disease classification. The fuzzy sets and membership functions are chosen in an appropriate manner. Centroid method is used for defuzzification. The database is taken from University Hospital Center "Mother Teresa" in Tirana, Albania. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=coronary%20heart%20disease" title="coronary heart disease">coronary heart disease</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic%20toolbox" title=" fuzzy logic toolbox"> fuzzy logic toolbox</a>, <a href="https://publications.waset.org/abstracts/search?q=membership%20function" title=" membership function"> membership function</a>, <a href="https://publications.waset.org/abstracts/search?q=prediction%20model" title=" prediction model"> prediction model</a> </p> <a href="https://publications.waset.org/abstracts/148911/prediction-of-coronary-heart-disease-using-fuzzy-logic" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/148911.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">161</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">680</span> Failure Localization of Bipolar Integrated Circuits by Implementing Active Voltage Contrast</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Yiqiang%20Ni">Yiqiang Ni</a>, <a href="https://publications.waset.org/abstracts/search?q=Xuanlong%20Chen"> Xuanlong Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Enliang%20Li"> Enliang Li</a>, <a href="https://publications.waset.org/abstracts/search?q=Linting%20Zheng"> Linting Zheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Shizheng%20Yang"> Shizheng Yang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Bipolar ICs are playing an important role in military applications, mainly used in logic gates, such as inverter and NAND gate. The defect of metal break located on the step is one of the main failure mechanisms of bipolar ICs, resulting in open-circuit or functional failure. In this situation, general failure localization methods like optical beam-induced resistance change (OBIRCH) and photon emission microscopy (PEM) might not be fully effective. However, active voltage contrast (AVC) can be used as a voltage probe, which may pinpoint the incorrect potential and thus locate the failure position. Two case studies will be present in this paper on how to implement AVC for failure localization, and the detailed failure mechanism will be discussed. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=bipolar%20IC" title="bipolar IC">bipolar IC</a>, <a href="https://publications.waset.org/abstracts/search?q=failure%20localization" title=" failure localization"> failure localization</a>, <a href="https://publications.waset.org/abstracts/search?q=metal%20break" title=" metal break"> metal break</a>, <a href="https://publications.waset.org/abstracts/search?q=open%20failure" title=" open failure"> open failure</a>, <a href="https://publications.waset.org/abstracts/search?q=voltage%20contrast" title=" voltage contrast"> voltage contrast</a> </p> <a href="https://publications.waset.org/abstracts/132527/failure-localization-of-bipolar-integrated-circuits-by-implementing-active-voltage-contrast" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/132527.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">291</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">679</span> Fuzzy Logic Driven PID Controller for PWM Based Buck Converter</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Bandreddy%20Anand%20Babu">Bandreddy Anand Babu</a>, <a href="https://publications.waset.org/abstracts/search?q=Mandadi%20Srinivasa%20Rao"> Mandadi Srinivasa Rao</a>, <a href="https://publications.waset.org/abstracts/search?q=Chintala%20Pradeep%20Reddy"> Chintala Pradeep Reddy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The main theme of this paper is to design fuzzy logic Proportional Integral Derivative controller for controlling of Pulse Width Modulator (PWM) based DCDC buck converter in continuous conduction mode of operation and comparing the results of FPID and ANFIS. Simulation is done to fuzzy the given input variables and membership functions of input values, creating the interference rules linking the input and output variables and after then defuzzfies the output variables. Fuzzy logic is simple for nonlinear models like buck converter. Fuzzy logic based PID controller technique is to control, nonlinear plants like buck converters in switching variables of power electronics. The characteristics of FPID are in terms of rise time, settling time, rise time, steady state errors for different inputs and load disturbances. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title="fuzzy logic">fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=PID%20controller" title=" PID controller"> PID controller</a>, <a href="https://publications.waset.org/abstracts/search?q=DC-DC%20buck%20converter" title=" DC-DC buck converter"> DC-DC buck converter</a>, <a href="https://publications.waset.org/abstracts/search?q=pulse%20width%20modulation" title=" pulse width modulation"> pulse width modulation</a> </p> <a href="https://publications.waset.org/abstracts/13742/fuzzy-logic-driven-pid-controller-for-pwm-based-buck-converter" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/13742.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1013</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">678</span> Design and Study of a Low Power High Speed 8 Transistor Based Full Adder Using Multiplexer and XOR Gates</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Biswarup%20Mukherjee">Biswarup Mukherjee</a>, <a href="https://publications.waset.org/abstracts/search?q=Aniruddha%20Ghoshal"> Aniruddha Ghoshal</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, we propose a new technique for implementing a low power high speed full adder using 8 transistors. Full adder circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the full adder. Simulated results indicate the superior performance of the proposed technique over conventional 28 transistor CMOS full adder. Detailed comparison of simulated results for the conventional and present method of implementation is presented. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=high%20speed%20low%20power%20full%20adder" title="high speed low power full adder">high speed low power full adder</a>, <a href="https://publications.waset.org/abstracts/search?q=2-T%20MUX" title=" 2-T MUX"> 2-T MUX</a>, <a href="https://publications.waset.org/abstracts/search?q=3-T%20XOR" title=" 3-T XOR"> 3-T XOR</a>, <a href="https://publications.waset.org/abstracts/search?q=8-T%20FA" title=" 8-T FA"> 8-T FA</a>, <a href="https://publications.waset.org/abstracts/search?q=pass%20transistor%20logic" title=" pass transistor logic"> pass transistor logic</a>, <a href="https://publications.waset.org/abstracts/search?q=CMOS%20%28complementary%20metal%20oxide%20semiconductor%29" title=" CMOS (complementary metal oxide semiconductor)"> CMOS (complementary metal oxide semiconductor)</a> </p> <a href="https://publications.waset.org/abstracts/21932/design-and-study-of-a-low-power-high-speed-8-transistor-based-full-adder-using-multiplexer-and-xor-gates" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/21932.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">348</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">677</span> Intelligent Control Design of Car Following Behavior Using Fuzzy Logic</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Abdelkader%20Merah">Abdelkader Merah</a>, <a href="https://publications.waset.org/abstracts/search?q=Kada%20Hartani"> Kada Hartani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> A reference model based control approach for improving behavior following car is proposed in this paper. The reference model is nonlinear and provides dynamic solutions consistent with safety constraints and comfort specifications. a robust fuzzy logic based control strategy is further proposed in this paper. A set of simulation results showing the suitability of the proposed technique for various demanding cenarios is also included in this paper. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=reference%20model" title="reference model">reference model</a>, <a href="https://publications.waset.org/abstracts/search?q=longitudinal%20control" title=" longitudinal control"> longitudinal control</a>, <a href="https://publications.waset.org/abstracts/search?q=fuzzy%20logic" title=" fuzzy logic"> fuzzy logic</a>, <a href="https://publications.waset.org/abstracts/search?q=design%20of%20car" title=" design of car"> design of car</a> </p> <a href="https://publications.waset.org/abstracts/14210/intelligent-control-design-of-car-following-behavior-using-fuzzy-logic" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/14210.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info 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