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a{color:var(--color-progressive)!important}}@media print{body.ns-0 .mw-parser-output .sidebar{display:none!important}}</style><table class="sidebar nomobile nowraplinks hlist"><tbody><tr><th class="sidebar-title"><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a>, and <a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> architectures</th></tr><tr><th class="sidebar-heading" style="background:#DEDEDE"> NXP (formerly Freescale and Motorola)</th></tr><tr><td class="sidebar-content"> <ul><li>PowerPC e series (2006) <ul><li><a href="/wiki/PowerPC_e200" title="PowerPC e200">e200</a></li> <li><a href="/wiki/PowerPC_e300" title="PowerPC e300">e300</a></li> <li><a href="/wiki/PowerPC_e500" title="PowerPC e500">e500</a></li> <li><a href="/wiki/PowerPC_e600" title="PowerPC e600">e600</a></li> <li><a href="/wiki/PowerPC_e5500" title="PowerPC e5500">e5500</a></li> <li><a href="/wiki/PowerPC_e6500" title="PowerPC e6500">e6500</a></li></ul></li></ul> <ul><li>Qor series (2008) <ul><li><a href="/wiki/QorIQ" title="QorIQ">QorIQ</a></li> <li><a href="/wiki/Qorivva" title="Qorivva">Qorivva</a></li></ul></li></ul></td> </tr><tr><th class="sidebar-heading" style="background:#DEDEDE"> IBM</th></tr><tr><td class="sidebar-content"> <ul><li><a href="/wiki/IBM_Power_microprocessors" title="IBM Power microprocessors">Power</a> series (1990) <ul><li><i><a href="/wiki/POWER1" title="POWER1">POWER1</a></i></li> <li><i><a href="/wiki/POWER2" title="POWER2">POWER2</a></i></li> <li><i><a href="/wiki/POWER3" title="POWER3">POWER3</a></i></li> <li><i><a href="/wiki/POWER4" title="POWER4">POWER4</a></i></li> <li><i><a href="/wiki/POWER5" title="POWER5">POWER5</a></i></li> <li><a href="/wiki/POWER6" title="POWER6">POWER6</a></li> <li><a href="/wiki/POWER7" title="POWER7">POWER7</a></li> <li><a href="/wiki/POWER8" title="POWER8">POWER8</a></li> <li><a href="/wiki/POWER9" title="POWER9">POWER9</a></li> <li><a href="/wiki/Power10" title="Power10">Power10</a></li></ul></li></ul> <ul><li>PowerPC series (1992) <ul><li><i><a href="/wiki/PowerPC_600" title="PowerPC 600">6xx</a></i></li> <li><a href="/wiki/PowerPC_400" title="PowerPC 400">4xx</a></li> <li><a href="/wiki/PowerPC_7xx" title="PowerPC 7xx">7xx</a></li> <li><i><a href="/wiki/PowerPC_G4" title="PowerPC G4">74xx</a></i></li> <li><i><a href="/wiki/PowerPC_970" title="PowerPC 970">970</a></i></li> <li><a href="/wiki/IBM_A2" title="IBM A2">A2</a> (2010) <ul><li>A2I</li> <li>A2O</li></ul></li> <li>RAD series (1997) <ul><li><i><a href="/wiki/IBM_RAD6000" title="IBM RAD6000">RAD6000</a></i></li> <li><a href="/wiki/RAD750" title="RAD750">RAD750</a></li> <li><a href="/wiki/RAD5500" title="RAD5500">RAD5500</a></li></ul></li></ul></li></ul> <ul><li><i><a class="mw-selflink selflink">RS64</a> series</i> (1996)</li></ul></td> </tr><tr><th class="sidebar-heading" style="background:#DEDEDE"> IBM/Nintendo</th></tr><tr><td class="sidebar-content"> <ul><li><i><a href="/wiki/Gekko_(processor)" title="Gekko (processor)">Gekko</a></i></li> <li><i><a href="/wiki/Broadway_(processor)" title="Broadway (processor)">Broadway</a></i></li> <li><i><a href="/wiki/Espresso_(processor)" title="Espresso (processor)">Espresso</a></i></li></ul></td> </tr><tr><th class="sidebar-heading" style="background:#DEDEDE"> Other</th></tr><tr><td class="sidebar-content"> <ul><li><a href="/wiki/Titan_(processor)" title="Titan (processor)"><span style="color:#808080">Titan</span></a></li> <li><a href="/wiki/PWRficient" title="PWRficient">PWRficient</a></li> <li><a href="/wiki/Cell_(processor)" title="Cell (processor)">Cell</a></li> <li><a href="/wiki/Xenon_(processor)" title="Xenon (processor)">Xenon</a></li> <li><i><a href="/wiki/X704" title="X704">X704</a></i></li></ul></td> </tr><tr><th class="sidebar-heading" style="background:#DEDEDE"> Related links</th></tr><tr><td class="sidebar-content"> <ul><li><a href="/wiki/OpenPOWER_Foundation" title="OpenPOWER Foundation">OpenPOWER Foundation</a></li> <li><a href="/wiki/AIM_alliance" title="AIM alliance">AIM alliance</a></li> <li><a href="/wiki/Reduced_instruction_set_computing" class="mw-redirect" title="Reduced instruction set computing">RISC</a></li> <li><a href="/wiki/IBM_Blue_Gene" title="IBM Blue Gene">Blue Gene</a></li> <li><a href="/wiki/Power.org" title="Power.org">Power.org</a></li> <li><a href="/wiki/Power_Architecture_Platform_Reference" title="Power Architecture Platform Reference">PAPR</a></li> <li><a href="/wiki/PowerPC_Reference_Platform" title="PowerPC Reference Platform">PReP</a></li> <li><a href="/wiki/Common_Hardware_Reference_Platform" title="Common Hardware Reference Platform">CHRP</a></li> <li><a href="/wiki/AltiVec" title="AltiVec">AltiVec</a></li></ul></td> </tr><tr><td class="sidebar-below" style="border-top:#aaa 1px solid; font-weight:normal;"> <span style="color:#808080">Cancelled in gray</span>, <i>historic in italic</i></td></tr><tr><td class="sidebar-navbar"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style data-mw-deduplicate="TemplateStyles:r1239400231">.mw-parser-output .navbar{display:inline;font-size:88%;font-weight:normal}.mw-parser-output .navbar-collapse{float:left;text-align:left}.mw-parser-output .navbar-boxtext{word-spacing:0}.mw-parser-output .navbar ul{display:inline-block;white-space:nowrap;line-height:inherit}.mw-parser-output .navbar-brackets::before{margin-right:-0.125em;content:"[ "}.mw-parser-output .navbar-brackets::after{margin-left:-0.125em;content:" ]"}.mw-parser-output .navbar li{word-spacing:-0.125em}.mw-parser-output .navbar a>span,.mw-parser-output .navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:POWER,_PowerPC,_and_Power_ISA" title="Template:POWER, PowerPC, and Power ISA"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:POWER,_PowerPC,_and_Power_ISA" title="Template talk:POWER, PowerPC, and Power ISA"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:POWER,_PowerPC,_and_Power_ISA" title="Special:EditPage/Template:POWER, PowerPC, and Power ISA"><abbr title="Edit this template">e</abbr></a></li></ul></div></td></tr></tbody></table> <p>The <b>IBM RS64</b> is a family of <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a> introduced in the mid 1990s, and used in IBM's <a href="/wiki/RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> and <a href="/wiki/AS/400" class="mw-redirect" title="AS/400">AS/400</a> <a href="/wiki/Server_(computing)" title="Server (computing)">servers</a>. </p><p>These microprocessors implement the "Amazon", or "PowerPC-AS", <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA). Amazon is a superset of the <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a>, with the addition of special features not in the PowerPC specification, mainly derived from <a href="/wiki/POWER2" title="POWER2">POWER2</a><sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (March 2018)">citation needed</span></a></i>]</sup> and the original AS/400 processor, and has been <a href="/wiki/64-bit" class="mw-redirect" title="64-bit">64-bit</a> from the start. The processors in this family are optimized for commercial workloads (<a href="/wiki/Integer" title="Integer">integer</a> performance, large <a href="/wiki/Cache_(computing)" title="Cache (computing)">caches</a>, frequent <a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">branches</a>) and do not feature the strong <a href="/wiki/Floating_point" class="mw-redirect" title="Floating point">floating point</a> performance of the processors in the <a href="/wiki/IBM_Power_microprocessors" title="IBM Power microprocessors">POWER</a> family, its sibling. </p><p>The RS64 family was phased out soon after the introduction of the <a href="/wiki/POWER4" title="POWER4">POWER4</a>, which was developed to unite the RS64 and POWER families. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1990, the <a href="/wiki/AS/400" class="mw-redirect" title="AS/400">AS/400</a> engineering team at <a href="/wiki/IBM_Rochester" title="IBM Rochester">IBM Rochester</a> began work on a new architecture known as <i>C-RISC</i> (Commercial <a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a>) to replace the IMPI architecture of the AS/400.<sup id="cite_ref-inside-as400_1-0" class="reference"><a href="#cite_note-inside-as400-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> C-RISC was an evolution of the IMPI instruction set, extending the <a href="/wiki/Address_space" title="Address space">address space</a> to 96 bits and adding some RISC instructions to speed up the more computationally intensive commercial applications that were being created for AS/400s. IBM president <a href="/wiki/Jack_Kuehler" title="Jack Kuehler">Jack Kuehler</a> wanted them to use PowerPC, but they resisted, arguing that the existing 32/64-bit PowerPC instruction set would not enable a viable transition for OS/400 software and that the existing instruction set required extensions for the commercial applications on the AS/400. At Kuehler's insistence, a team at Rochester led by <a href="/wiki/Frank_Soltis" title="Frank Soltis">Frank Soltis</a> investigated the feasibility of extending the PowerPC instruction set to support the needs of the AS/400 platform. These extensions became known as <b>Amazon</b> and were selected by IBM <a href="/wiki/Executive_management" class="mw-redirect" title="Executive management">executive management</a> for further development over continued development of C-RISC.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>At the same time, the <a href="/wiki/RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> developers were broadly expanding their product line to include systems which spanned from low-end <a href="/wiki/Workstations" class="mw-redirect" title="Workstations">workstations</a>, to <a href="/wiki/Mainframe" class="mw-redirect" title="Mainframe">mainframe</a>-competitor large enterprise SMP systems, to clustered <a href="/wiki/IBM_Scalable_POWERparallel" title="IBM Scalable POWERparallel">RS/6000-SP2</a> supercomputing systems. PowerPC processors developed in the <a href="/wiki/AIM_alliance" title="AIM alliance">AIM alliance</a> suited the low-end RISC workstation and small server space well. But mainframe and large clustered supercomputing systems required more performance and <a href="/wiki/Reliability,_availability_and_serviceability" title="Reliability, availability and serviceability">reliability, availability and serviceability</a> features than processors designed for <a href="/wiki/Apple_Power_Mac" class="mw-redirect" title="Apple Power Mac">Apple Power Macs</a>. Multiple processor designs were required to simultaneously meet the requirements of the cost-focused Apple Power Mac, high-performance and RAS RS/6000 systems, and the AS/400 transition to PowerPC. </p><p>Amazon was extended to support those features as well, so that processors could be designed for use in both high-end RS/6000 and AS/400 machines. </p><p>The project to develop the first such processor was "Bellatrix" (the name of <a href="/wiki/Bellatrix" title="Bellatrix">a star in the Orion constellation</a>, also called the "Amazon Star"). The Bellatrix project was extremely ambitious in its pervasive use of self-timed & pulse-based circuits and the EDA tools required to support this design strategy, and was eventually terminated. To address technical workstation, <a href="/wiki/Supercomputer" title="Supercomputer">supercomputer</a>, and engineering/scientific markets, IBM Austin (the home of the RS/6000s) then started developing a time-to-market single-chip version of the Power2 (P2SC) in parallel with the development of a sophisticated 64-bit PowerPC processor with the POWER2 extensions and twin sophisticated MAF <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point units</a> (the POWER3/630). To address RS/6000 commercial applications and AS/400 systems, IBM Rochester (the home of the AS/400s) started developing the first of the high-end 64-bit PowerPC processors with AS/400 extensions, and IBM Endicott started developing a low-end single-chip PowerPC processor with AS/400 extensions. </p> <div class="mw-heading mw-heading2"><h2 id="Cobra_and_Muskie">Cobra and Muskie</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=2" title="Edit section: Cobra and Muskie"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>In 1995, IBM released the <b>Cobra</b>, or <b>A10</b> processor, the first full implementation of PowerPC AS, for the IBM <a href="/wiki/AS/400" class="mw-redirect" title="AS/400">AS/400</a> systems. It was a single-chip processor running at 50-77 MHz. It was designed with a semi-custom methodology, as a consequence of time-to-market constraints. The die contains 4.7 million <a href="/wiki/Transistor" title="Transistor">transistors</a> and measures 14.6 mm by 14.6 mm (213 mm<sup>2</sup>). It was fabricated by IBM in their CMOS 5L process, a 0.5 <a href="/wiki/%CE%9Cm" class="mw-redirect" title="Μm">μm</a>, four-layer-metal CMOS process. It used a 3.0 V power supply and dissipated 17.7 W maximum, 13.4 W minimum at 77 MHz. It was packaged in a 625-contact <a href="/wiki/Ceramic_ball_grid_array" class="mw-redirect" title="Ceramic ball grid array">ceramic ball grid array</a> (CBGA) that measured 32 mm by 32 mm. </p><p>Cobra was preceded by a simplified implementation known as <b>Cobra-Lite</b> in 1994, which was used in the first <a href="/wiki/IBM_Advanced/36" title="IBM Advanced/36">IBM Advanced/36</a> systems.<sup id="cite_ref-inside-as400_1-1" class="reference"><a href="#cite_note-inside-as400-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> It lacked 17 instructions from the full PowerPC AS ISA which were not needed for the Advanced/36. </p><p>In 1996, IBM released the high-end, 4-way <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">SMP</a>, multi-chip version called <b>Muskie</b>, <b>A25</b> or <b>A30</b> in AS/400 systems. It ran at 125-154 MHz. It was manufactured on a <a href="/wiki/BiCMOS" title="BiCMOS">BiCMOS</a> fabrication process. </p><p>These processors were only used in AS/400 and Advanced/36 machines. </p> <div class="mw-heading mw-heading2"><h2 id="RS64">RS64</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=3" title="Edit section: RS64"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_RS64_Apache.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9e/IBM_RS64_Apache.png/220px-IBM_RS64_Apache.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9e/IBM_RS64_Apache.png/330px-IBM_RS64_Apache.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9e/IBM_RS64_Apache.png/440px-IBM_RS64_Apache.png 2x" data-file-width="1562" data-file-height="1565" /></a><figcaption>IBM RS64 Apache</figcaption></figure> <p>The <b>RS64</b> or <b>Apache</b> was introduced in 1997. It was developed from "Cobra" and "Muskie" but included a more complete PowerPC ISA and was therefore set to be used in <a href="/wiki/RS/6000" class="mw-redirect" title="RS/6000">RS/6000</a> machines as well as in AS/400 systems. It featured 128 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> total on-die <a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1 cache</a>, 4 <a href="/wiki/Megabyte" title="Megabyte">MB</a> full speed off-chip L2 on a 128-bit bus, and a clock of 125 MHz. It scaled to a 12-processor SMP configuration in IBM's machines. </p><p>RS64 was called <b>A35</b> in AS/400 and was one time referred to as the <b>PowerPC 625</b>, between the defunct <a href="/wiki/PowerPC_600#PowerPC_620" title="PowerPC 600">PowerPC 620</a> and the PowerPC 630 (later renamed <a href="/wiki/POWER3" title="POWER3">POWER3</a>). </p><p>It was manufactured with a BiCMOS fabrication process. </p> <div class="mw-heading mw-heading2"><h2 id="RS64-II">RS64-II</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=4" title="Edit section: RS64-II"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_RS64-II.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/IBM_RS64-II.png/220px-IBM_RS64-II.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e6/IBM_RS64-II.png/330px-IBM_RS64-II.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e6/IBM_RS64-II.png/440px-IBM_RS64-II.png 2x" data-file-width="1562" data-file-height="1565" /></a><figcaption>IBM RS64-II</figcaption></figure> <p>The <b>RS64-II</b> or <b>Northstar</b> was introduced at 262 MHz in 1998 with 8 MB of full speed L2 on a 256 bit 6XX bus (also used in <a href="/wiki/PowerPC_600#PowerPC_620" title="PowerPC 600">PowerPC 620</a> and <a href="/wiki/POWER3" title="POWER3">POWER3</a>). Processor boards containing 4 RS64-II's could be swapped into machines designed for similar 4-way RS64 boards, avoiding a "fork lift upgrade". The RS64-II contained 12.5 million transistors, was 162 mm² large and drew 27 watts maximum power. Manufacturing changed to a 0.35 μm <a href="/wiki/CMOS" title="CMOS">CMOS</a> fabrication. </p><p><b>RS64-II</b> was the first mass-market processor to implement <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multithreading</a>. Essentially, each chip stores state information for 2 threads at any given time and appears to be two processors to the OS. One logical processor runs what is called the foreground thread. When this thread encounters a high-latency event (<a href="/wiki/L2_cache" class="mw-redirect" title="L2 cache">L2 cache</a> miss, etc.) the background thread is switched to, on the second logical processor from the OS's point of view. In the event of a "less long" latency event (L1 miss, etc.), <a href="/wiki/Thread_switching" class="mw-redirect" title="Thread switching">thread switching</a> will only occur if the background thread is ready to execute. If the background thread is also waiting for a miss, thread switching will not occur. IBM calls this scheme "coarse grained multithreading". It is not exactly the same thing as <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> as found on later <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a> processors. An IBM paper notes that the coarse grained scheme is a better fit for an in-order <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a> like RS64. </p><p>RS64-II was called <b>A50</b> in AS/400 systems. </p> <div class="mw-heading mw-heading2"><h2 id="RS64-III">RS64-III</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=5" title="Edit section: RS64-III"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_RS64-III_DCM.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/IBM_RS64-III_DCM.png/220px-IBM_RS64-III_DCM.png" decoding="async" width="220" height="171" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/IBM_RS64-III_DCM.png/330px-IBM_RS64-III_DCM.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1f/IBM_RS64-III_DCM.png/440px-IBM_RS64-III_DCM.png 2x" data-file-width="1562" data-file-height="1217" /></a><figcaption>IBM RS64-III DCM</figcaption></figure> <p>The <b>RS64-III</b> or <b>Pulsar</b> was introduced in 1999 at 450 MHz. Key changes included larger 128 KiB L1 instruction and data caches, improved <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction</a> accuracy and reduced branch misprediction penalties of zero or one cycle. The RS64-III has a five-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> and a 256-bit wide L2 cache bus, which provided the processor with 14.4 GB/s of bandwidth from the 8 MiB L2 cache, implemented with 225 MHz DDR SRAMs. </p><p>The RS64-III has 34 million transistors, a die size of 140 mm², and is manufactured on the 0.22 μm CMOS 7S process with six levels of <a href="/wiki/Copper_interconnects" title="Copper interconnects">copper interconnect</a>. </p><p>In 2000, IBM launched a refined version called <b>IStar</b> manufactured with a <a href="/wiki/Silicon_on_insulator" title="Silicon on insulator">SOI</a> <a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">fabrication process</a> with copper interconnects, which increased the processor's clock frequency to 600 MHz. This was the first processor implemented in this process. Architecturally however, the IStar was identical to Pulsar. </p> <div class="mw-heading mw-heading2"><h2 id="RS64-IV">RS64-IV</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=6" title="Edit section: RS64-IV"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_RS64-IV_SCM.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/ee/IBM_RS64-IV_SCM.png/220px-IBM_RS64-IV_SCM.png" decoding="async" width="220" height="171" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/ee/IBM_RS64-IV_SCM.png/330px-IBM_RS64-IV_SCM.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/ee/IBM_RS64-IV_SCM.png/440px-IBM_RS64-IV_SCM.png 2x" data-file-width="1562" data-file-height="1217" /></a><figcaption>IBM RS64-IV SCM</figcaption></figure> <p>The <b>RS64-IV</b> or <b>Sstar</b> was introduced in 2000 at 600 MHz, later increased to 750 MHz. Up to 16 MB DDR L2 cache was supported in the same manner as the RS64-III (19.2 GB/s bandwidth). The RS64-IV had 44 million transistors and was 128 mm² large manufactured on a 0.18 μm process. Unlike POWER, energy consumption remained low, at under 15 watts per core. </p><p>For a time, while the POWER line stagnated at half the clock speed of its competitors, the RS64 family was at the top of the IBM large SMP <a href="/wiki/UNIX" class="mw-redirect" title="UNIX">UNIX</a> server line. The integer / commercial workload performance of the RS-64 IV was similar to the <a href="/wiki/Sun_Microsystems" title="Sun Microsystems">Sun Microsystems</a> processors with which it competed, though its floating point power was not comparable to the contemporary <a href="/wiki/POWER3" title="POWER3">POWER3-II</a>, which remained reasonably competitive throughout its lifecycle. </p> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=7" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-inside-as400-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-inside-as400_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-inside-as400_1-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFFrank_G._Soltis1997" class="citation book cs1">Frank G. Soltis (1997). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=5DoPAAAACAAJ"><i>Inside the AS/400, Second Edition</i></a>. Duke Press. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1882419661" title="Special:BookSources/978-1882419661"><bdi>978-1882419661</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Inside+the+AS%2F400%2C+Second+Edition&rft.pub=Duke+Press&rft.date=1997&rft.isbn=978-1882419661&rft.au=Frank+G.+Soltis&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D5DoPAAAACAAJ&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+RS64" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLeif_Svalgaard2003" class="citation mailinglist cs1">Leif Svalgaard (2003-10-08). <a rel="nofollow" class="external text" href="https://archive.midrange.com/mi400/200310/msg00008.html">"Re: Re: MI emulator"</a>. <i>MI400</i> (Mailing list)<span class="reference-accessdate">. Retrieved <span class="nowrap">2021-02-26</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Re%3A+Re%3A+MI+emulator&rft.date=2003-10-08&rft.au=Leif+Svalgaard&rft_id=https%3A%2F%2Farchive.midrange.com%2Fmi400%2F200310%2Fmsg00008.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+RS64" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAdam_T._StallmanFrank_G._Soltis1995" class="citation magazine cs1">Adam T. Stallman; Frank G. Soltis (July 1, 1995). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130831203807/http://iprodeveloper.com/systems-management/inside-powerpc">"Inside the PowerPC AS"</a>. <i>System iNEWS Magazine</i>. Archived from <a rel="nofollow" class="external text" href="http://iprodeveloper.com/systems-management/inside-powerpc">the original</a> on August 31, 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=System+iNEWS+Magazine&rft.atitle=Inside+the+PowerPC+AS&rft.date=1995-07-01&rft.au=Adam+T.+Stallman&rft.au=Frank+G.+Soltis&rft_id=http%3A%2F%2Fiprodeveloper.com%2Fsystems-management%2Finside-powerpc&rfr_id=info%3Asid%2Fen.wikipedia.org%3AIBM+RS64" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=8" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Gwennap, Linley (31 July 1995). "IBM Creates PowerPC Processors for AS/400". <i><a href="/wiki/Microprocessor_Report" title="Microprocessor Report">Microprocessor Report</a></i>.</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=IBM_RS64&action=edit&section=9" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://www.research.ibm.com/journal/rd/446/borkenhagen.html">IBM paper on RS64-IV</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20060806141741/http://www.rootvg.net/column_risc.htm">27 years of IBM RISC</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20111003182753/http://systeminetwork.com/article/when-powerpc-not-powerpc">When Is PowerPC Not PowerPC?</a> - History of the POWER Architecture by <a href="/wiki/Frank_Soltis" title="Frank Soltis">Frank Soltis</a></li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20080529/http://www.ibm.com/developerworks/power/library/pa-powerppl/"><i>POWER to the people</i></a></li> <li><a rel="nofollow" class="external text" href="http://www.csee.umbc.edu/help/architecture/ppcnstar.pdf">4th Generation 64-bit PowerPC-Compatible Commercial Processor Design</a></li> <li><a rel="nofollow" class="external text" href="http://iprodeveloper.com/systems-management/inside-powerpc">Inside the PowerPC AS</a> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20130831203807/http://iprodeveloper.com/systems-management/inside-powerpc">Archived</a> 2013-08-31 at the <a href="/wiki/Wayback_Machine" title="Wayback Machine">Wayback Machine</a></li></ul> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><style 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System/7">System/7</a></li> <li><a href="/wiki/IBM_System_9000" title="IBM System 9000">System 9000</a></li> <li><a href="/wiki/IBM_System_p" title="IBM System p">System p</a></li> <li><a href="/wiki/Lenovo_System_x" title="Lenovo System x">System x</a> <ul><li><a href="/wiki/Lenovo_System_x#IBM_iDataPlex" title="Lenovo System x">iDataPlex</a></li> <li>Predecessors: <a href="/wiki/Lenovo_System_x#IBM_PS/2_Server" title="Lenovo System x">PS/2 Server</a></li> <li><a href="/wiki/Lenovo_System_x#IBM_PC_Server" title="Lenovo System x">PC Server</a></li> <li><a href="/wiki/Lenovo_System_x#IBM_Netfinity" title="Lenovo System x">Netfinity</a></li> <li><a href="/wiki/IBM_eServer" title="IBM eServer">eServer</a></li></ul></li> <li><a href="/wiki/IBM_Power_Systems" title="IBM Power Systems">Power Systems</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IBM_AS/400" title="IBM AS/400">AS/400</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_Advanced/36" title="IBM Advanced/36">Advanced/36</a>*</li> <li><a class="mw-selflink selflink">RS64 microprocessor</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="Applications,_software,_and_concepts" scope="row" class="navbox-group" style="width:1%">Applications, software, and concepts</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Control_Language" title="Control Language">Control Language</a></li> <li><a href="/wiki/Dealer_Business_System" title="Dealer Business System">Dealer Business System</a></li> <li><a href="/wiki/Dynamic_Logical_Partitioning" title="Dynamic Logical Partitioning">Dynamic Logical Partitioning</a></li> <li><a href="/wiki/IBM_i" title="IBM i">OS/400</a> <ul><li><a href="/wiki/Object_(IBM_i)" title="Object (IBM i)">object</a></li></ul></li> <li><a href="/wiki/Programming_Development_Manager" title="Programming Development Manager">Programming Development Manager</a></li> <li><a href="/wiki/Quick_Response_Engine" title="Quick Response Engine">Quick Response Engine</a></li> <li><a href="/wiki/Single-level_store" title="Single-level store">Single-level store</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IBM_RS/6000" title="IBM RS/6000">RS/6000</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_ThinkPad_Power_Series" title="IBM ThinkPad Power Series">ThinkPad Power Series</a></li> <li>Predecessors: <a href="/wiki/IBM_RT_PC" title="IBM RT PC">RT PC</a></li> <li><a href="/wiki/IBM_Academic_System" class="mw-redirect" title="IBM Academic System">Academic System</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_801" title="IBM 801">IBM 801</a></li> <li><a href="/wiki/IBM_3790" title="IBM 3790">3790 Communications System</a></li> <li><a href="/wiki/IBM_8100" title="IBM 8100">8100 Information System</a></li> <li><a href="/wiki/IBM_BladeCenter" title="IBM BladeCenter">BladeCenter</a></li> <li><a href="/wiki/IBM_IntelliStation" title="IBM IntelliStation">IntelliStation</a></li> <li><a href="/wiki/IBM_Series/1" title="IBM Series/1">Series/1</a></li></ul> </div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>* Also based on the System/36 <ul><li><span class="noviewer" typeof="mw:File"><span title="Category"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/96/Symbol_category_class.svg/16px-Symbol_category_class.svg.png" decoding="async" width="16" height="16" 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