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class="vector-toc-numb">2</span> <span>Standard-cell designs</span> </div> </a> <ul id="toc-Standard-cell_designs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gate-array_and_semi-custom_design" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Gate-array_and_semi-custom_design"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Gate-array and semi-custom design</span> </div> </a> <ul id="toc-Gate-array_and_semi-custom_design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Full-custom_design" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Full-custom_design"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Full-custom design</span> </div> </a> <ul id="toc-Full-custom_design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Structured_design" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Structured_design"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Structured design</span> </div> </a> <ul id="toc-Structured_design-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cell_libraries,_IP-based_design,_hard_and_soft_macros" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Cell_libraries,_IP-based_design,_hard_and_soft_macros"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Cell libraries, IP-based design, hard and soft macros</span> </div> </a> <ul id="toc-Cell_libraries,_IP-based_design,_hard_and_soft_macros-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Multi-project_wafers" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Multi-project_wafers"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Multi-project wafers</span> </div> </a> <ul id="toc-Multi-project_wafers-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Application-specific_standard_product" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Application-specific_standard_product"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Application-specific standard product</span> </div> </a> <ul id="toc-Application-specific_standard_product-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Sources" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Sources"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Sources</span> </div> </a> <ul id="toc-Sources-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main 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class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Circuit_integrat_d%27aplicaci%C3%B3_espec%C3%ADfica" title="Circuit integrat d'aplicació específica – Catalan" lang="ca" hreflang="ca" data-title="Circuit integrat d'aplicació específica" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Z%C3%A1kaznick%C3%BD_integrovan%C3%BD_obvod" title="Zákaznický integrovaný obvod – Czech" lang="cs" hreflang="cs" data-title="Zákaznický integrovaný obvod" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/ASIC" title="ASIC – Danish" lang="da" hreflang="da" data-title="ASIC" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Anwendungsspezifische_integrierte_Schaltung" title="Anwendungsspezifische integrierte Schaltung – German" lang="de" hreflang="de" data-title="Anwendungsspezifische integrierte Schaltung" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Rakendus-spetsiifiline_integraall%C3%BClitus" title="Rakendus-spetsiifiline integraallülitus – Estonian" lang="et" hreflang="et" data-title="Rakendus-spetsiifiline integraallülitus" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Circuito_integrado_de_aplicaci%C3%B3n_espec%C3%ADfica" title="Circuito integrado de aplicación específica – Spanish" lang="es" hreflang="es" data-title="Circuito integrado de aplicación específica" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%85%D8%AF%D8%A7%D8%B1%D9%87%D8%A7%DB%8C_%D9%85%D8%AC%D8%AA%D9%85%D8%B9_%D8%A8%D8%A7_%DA%A9%D8%A7%D8%B1%D8%A8%D8%B1%D8%AF_%D8%AE%D8%A7%D8%B5" title="مدارهای مجتمع با کاربرد خاص – Persian" lang="fa" hreflang="fa" data-title="مدارهای مجتمع با کاربرد خاص" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit – French" lang="fr" hreflang="fr" data-title="Application-specific integrated circuit" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/ASIC" title="ASIC – Korean" lang="ko" hreflang="ko" data-title="ASIC" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hi mw-list-item"><a href="https://hi.wikipedia.org/wiki/%E0%A4%8F%E0%A4%B8%E0%A4%BF%E0%A4%95" title="एसिक – Hindi" lang="hi" hreflang="hi" data-title="एसिक" data-language-autonym="हिन्दी" data-language-local-name="Hindi" class="interlanguage-link-target"><span>हिन्दी</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Aplikasi_spesifik_sirkuit_terpadu" title="Aplikasi spesifik sirkuit terpadu – Indonesian" lang="id" hreflang="id" data-title="Aplikasi spesifik sirkuit terpadu" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Application_specific_integrated_circuit" title="Application specific integrated circuit – Italian" lang="it" hreflang="it" data-title="Application specific integrated circuit" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/ASIC" title="ASIC – Hebrew" lang="he" hreflang="he" data-title="ASIC" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/Specialios_paskirties_integrinis_grandynas" title="Specialios paskirties integrinis grandynas – Lithuanian" lang="lt" hreflang="lt" data-title="Specialios paskirties integrinis grandynas" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Alkalmaz%C3%A1sspecifikus_integr%C3%A1lt_%C3%A1ramk%C3%B6r" title="Alkalmazásspecifikus integrált áramkör – Hungarian" lang="hu" hreflang="hu" data-title="Alkalmazásspecifikus integrált áramkör" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/ASIC" title="ASIC – Dutch" lang="nl" hreflang="nl" data-title="ASIC" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/ASIC" title="ASIC – Japanese" lang="ja" hreflang="ja" data-title="ASIC" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/ASIC" title="ASIC – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="ASIC" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Specjalizowany_uk%C5%82ad_scalony" title="Specjalizowany układ scalony – Polish" lang="pl" hreflang="pl" data-title="Specjalizowany układ scalony" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Circuito_integrado_de_aplica%C3%A7%C3%A3o_especifica" title="Circuito integrado de aplicação especifica – Portuguese" lang="pt" hreflang="pt" data-title="Circuito integrado de aplicação especifica" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/ASIC" title="ASIC – Romanian" lang="ro" hreflang="ro" data-title="ASIC" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%98%D0%BD%D1%82%D0%B5%D0%B3%D1%80%D0%B0%D0%BB%D1%8C%D0%BD%D0%B0%D1%8F_%D1%81%D1%85%D0%B5%D0%BC%D0%B0_%D1%81%D0%BF%D0%B5%D1%86%D0%B8%D0%B0%D0%BB%D1%8C%D0%BD%D0%BE%D0%B3%D0%BE_%D0%BD%D0%B0%D0%B7%D0%BD%D0%B0%D1%87%D0%B5%D0%BD%D0%B8%D1%8F" title="Интегральная схема специального назначения – Russian" lang="ru" hreflang="ru" data-title="Интегральная схема специального назначения" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit – Simple English" lang="en-simple" hreflang="en-simple" data-title="Application-specific integrated circuit" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/ASIC" title="ASIC – Slovak" lang="sk" hreflang="sk" data-title="ASIC" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/Integrisano_kolo_specifi%C4%8Dne_namene" title="Integrisano kolo specifične namene – Serbian" lang="sr" hreflang="sr" data-title="Integrisano kolo specifične namene" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/ASIC" title="ASIC – Finnish" lang="fi" hreflang="fi" data-title="ASIC" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/ASIC" title="ASIC – Swedish" lang="sv" hreflang="sv" data-title="ASIC" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/ASIC" title="ASIC – Turkish" lang="tr" hreflang="tr" data-title="ASIC" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/ASIC" title="ASIC – Ukrainian" lang="uk" hreflang="uk" data-title="ASIC" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li 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<div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Integrated circuit customized for a specific task</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"ASIC" redirects here. For other uses, see <a href="/wiki/ASIC_(disambiguation)" class="mw-disambig" title="ASIC (disambiguation)">ASIC (disambiguation)</a>.</div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-More_footnotes_needed plainlinks metadata ambox ambox-style ambox-More_footnotes_needed" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a4/Text_document_with_red_question_mark.svg/40px-Text_document_with_red_question_mark.svg.png" decoding="async" width="40" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a4/Text_document_with_red_question_mark.svg/60px-Text_document_with_red_question_mark.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a4/Text_document_with_red_question_mark.svg/80px-Text_document_with_red_question_mark.svg.png 2x" data-file-width="48" data-file-height="48" /></span></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article includes a list of <a href="/wiki/Wikipedia:Citing_sources#General_references" title="Wikipedia:Citing sources">general references</a>, but <b>it lacks sufficient corresponding <a href="/wiki/Wikipedia:Citing_sources#Inline_citations" title="Wikipedia:Citing sources">inline citations</a></b>.<span class="hide-when-compact"> Please help to <a href="/wiki/Wikipedia:WikiProject_Reliability" title="Wikipedia:WikiProject Reliability">improve</a> this article by <a href="/wiki/Wikipedia:When_to_cite" title="Wikipedia:When to cite">introducing</a> more precise citations.</span> <span class="date-container"><i>(<span class="date">October 2015</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p class="mw-empty-elt"> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:SSDTR-ASIC_technology.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/SSDTR-ASIC_technology.jpg/220px-SSDTR-ASIC_technology.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/79/SSDTR-ASIC_technology.jpg/330px-SSDTR-ASIC_technology.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/79/SSDTR-ASIC_technology.jpg/440px-SSDTR-ASIC_technology.jpg 2x" data-file-width="500" data-file-height="500" /></a><figcaption>A tray of application-specific integrated circuit (ASIC) chips</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg/220px-Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg" decoding="async" width="220" height="169" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg/330px-Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg/440px-Network_traffic_processing_ASIC_inside_an_Ethernet_switch.jpg 2x" data-file-width="2220" data-file-height="1707" /></a><figcaption>A packet processing ASIC inside an Ethernet switch</figcaption></figure> <p>An <b>application-specific integrated circuit</b> (<b>ASIC</b> <span class="rt-commentedText nowrap"><span class="IPA nopopups noexcerpt" lang="en-fonipa"><a href="/wiki/Help:IPA/English" title="Help:IPA/English">/<span style="border-bottom:1px dotted"><span title="/ˈ/: primary stress follows">ˈ</span><span title="/eɪ/: 'a' in 'face'">eɪ</span><span title="'s' in 'sigh'">s</span><span title="/ɪ/: 'i' in 'kit'">ɪ</span><span title="'k' in 'kind'">k</span></span>/</a></span></span>) is an <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) chip customized for a particular use, rather than intended for general-purpose use, such as a chip designed to run in a <a href="/wiki/Digital_voice_recorder" class="mw-redirect" title="Digital voice recorder">digital voice recorder</a> or a high-efficiency <a href="/wiki/Video_codec" title="Video codec">video codec</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> <a href="#Application-specific_standard_product">Application-specific standard product</a> chips are intermediate between ASICs and industry standard integrated circuits like the <a href="/wiki/7400_series" class="mw-redirect" title="7400 series">7400 series</a> or the <a href="/wiki/4000_series" class="mw-redirect" title="4000 series">4000 series</a>.<sup id="cite_ref-:0_2-0" class="reference"><a href="#cite_note-:0-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> ASIC chips are typically <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> using <a href="/wiki/Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">metal–oxide–semiconductor</a> (MOS) technology, as <a href="/wiki/MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> chips.<sup id="cite_ref-computerhistory1967_3-0" class="reference"><a href="#cite_note-computerhistory1967-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>As feature sizes have shrunk and <a href="/wiki/Electronic_design_automation" title="Electronic design automation">chip design tools</a> improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 <a href="/wiki/Logic_gate" title="Logic gate">logic gates</a> to over 100 million. Modern ASICs often include entire <a href="/wiki/Central_processing_unit" title="Central processing unit">microprocessors</a>, <a href="/wiki/Memory" title="Memory">memory</a> blocks including <a href="/wiki/Read-only_memory" title="Read-only memory">ROM</a>, <a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a>, <a href="/wiki/EEPROM" title="EEPROM">EEPROM</a>, <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a> and other large building blocks. Such an ASIC is often termed a SoC (<a href="/wiki/System-on-chip" class="mw-redirect" title="System-on-chip">system-on-chip</a>). Designers of digital ASICs often use a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL), such as <a href="/wiki/Verilog" title="Verilog">Verilog</a> or <a href="/wiki/VHDL" title="VHDL">VHDL</a>, to describe the functionality of ASICs.<sup id="cite_ref-:0_2-1" class="reference"><a href="#cite_note-:0-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate arrays</a> (FPGA) are the modern-day technology improvement on <a href="/wiki/Breadboard" title="Breadboard">breadboards</a>, meaning that they are not made to be application-specific as opposed to ASICs. Programmable logic blocks and programmable interconnects allow the same FPGA to be used in many different applications. For smaller designs or lower production volumes, FPGAs may be more cost-effective than an ASIC design, even in production. The <a href="/wiki/Non-recurring_engineering" title="Non-recurring engineering">non-recurring engineering</a> (NRE) cost of an ASIC can run into the millions of dollars. Therefore, device manufacturers typically prefer FPGAs <a href="/wiki/FPGA_prototyping" title="FPGA prototyping">for prototyping</a> and devices with low production volume and ASICs for <a href="/wiki/Mass_production" title="Mass production">very large production volumes</a> where NRE costs can be <a href="/wiki/Amortized_cost" class="mw-redirect" title="Amortized cost">amortized</a> across many devices.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Early ASICs used <a href="/wiki/Gate_array" title="Gate array">gate array</a> technology. By 1967, <a href="/wiki/Ferranti" title="Ferranti">Ferranti</a> and Interdesign were manufacturing early <a href="/wiki/Bipolar_transistor" class="mw-redirect" title="Bipolar transistor">bipolar</a> gate arrays. In 1967, <a href="/wiki/Fairchild_Semiconductor" title="Fairchild Semiconductor">Fairchild Semiconductor</a> introduced the Micromatrix family of bipolar <a href="/wiki/Diode%E2%80%93transistor_logic" title="Diode–transistor logic">diode–transistor logic</a> (DTL) and <a href="/wiki/Transistor%E2%80%93transistor_logic" title="Transistor–transistor logic">transistor–transistor logic</a> (TTL) arrays.<sup id="cite_ref-computerhistory1967_3-1" class="reference"><a href="#cite_note-computerhistory1967-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Complementary_metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Complementary metal–oxide–semiconductor">Complementary metal–oxide–semiconductor</a> (CMOS) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp,<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> in 1974 for International Microcircuits, Inc. (IMI).<sup id="cite_ref-computerhistory1967_3-2" class="reference"><a href="#cite_note-computerhistory1967-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Metal%E2%80%93oxide%E2%80%93semiconductor" class="mw-redirect" title="Metal–oxide–semiconductor">Metal–oxide–semiconductor</a> (MOS) <a href="/wiki/Standard-cell" class="mw-redirect" title="Standard-cell">standard-cell</a> technology was introduced by Fairchild and <a href="/wiki/Motorola" title="Motorola">Motorola</a>, under the trade names Micromosaic and Polycell, in the 1970s. This technology was later successfully commercialized by <a href="/wiki/VLSI_Technology" title="VLSI Technology">VLSI Technology</a> (founded 1979) and <a href="/wiki/LSI_Logic" class="mw-redirect" title="LSI Logic">LSI Logic</a> (1981).<sup id="cite_ref-computerhistory1967_3-3" class="reference"><a href="#cite_note-computerhistory1967-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> </p><p>A successful commercial application of gate array circuitry was found in the low-end 8-bit <a href="/wiki/ZX81" title="ZX81">ZX81</a> and <a href="/wiki/ZX_Spectrum" title="ZX Spectrum">ZX Spectrum</a> <a href="/wiki/Personal_computer" title="Personal computer">personal computers</a>, introduced in 1981 and 1982. These were used by <a href="/wiki/Sinclair_Research" title="Sinclair Research">Sinclair Research</a> (UK) essentially as a low-cost <a href="/wiki/Input/output" title="Input/output">I/O</a> solution aimed at handling the <a href="/wiki/Computer_graphics" title="Computer graphics">computer's graphics</a>. </p><p>Customization occurred by varying a metal interconnect mask. Gate arrays had complexities of up to a few thousand gates; this is now called <a href="/wiki/Mid-scale_integration" class="mw-redirect" title="Mid-scale integration">mid-scale integration</a>. Later versions became more generalized, with different <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">base dies</a> customized by both metal and <a href="/wiki/Polycrystalline_silicon" title="Polycrystalline silicon">polysilicon</a> layers. Some base dies also include <a href="/wiki/Random-access_memory" title="Random-access memory">random-access memory</a> (RAM) elements. </p> <div class="mw-heading mw-heading2"><h2 id="Standard-cell_designs">Standard-cell designs</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=2" title="Edit section: Standard-cell designs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Standard_cell" title="Standard cell">Standard cell</a></div> <p>In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the <a href="/wiki/Integrated_circuit_layout" title="Integrated circuit layout">layout</a> and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers used factory-specific tools to complete the implementation of their designs. A solution to this problem, which also yielded a much higher density device, was the implementation of <a href="/wiki/Standard_cell" title="Standard cell">standard cells</a>.<sup id="cite_ref-MichaelJohnSebastianSmith_7-0" class="reference"><a href="#cite_note-MichaelJohnSebastianSmith-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as <a href="/wiki/Propagation_delay" title="Propagation delay">propagation delay</a>, capacitance and inductance, that could also be represented in third-party tools. Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard-cell design is intermediate between <a href="#Gate-array_and_semi-custom_design">§ Gate-array and semi-custom design</a> and <a href="#Full-custom_design">§ Full-custom design</a> in terms of its non-recurring engineering and recurring component costs as well as performance and speed of development (including <a href="/wiki/Time_to_market" title="Time to market">time to market</a>). </p><p>By the late 1990s, <a href="/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a> tools became available. Such tools could compile <a href="/wiki/Hardware_description_language" title="Hardware description language">HDL</a> descriptions into a gate-level <a href="/wiki/Netlist" title="Netlist">netlist</a>. Standard-cell <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs) are designed in the following conceptual stages referred to as <a href="/wiki/Design_flow_(EDA)" title="Design flow (EDA)">electronics design flow</a>, although these stages overlap significantly in practice: </p> <ol><li><b><a href="/wiki/Requirements_engineering" title="Requirements engineering">Requirements engineering</a></b>: A team of design engineers starts with a non-formal understanding of the <a href="/wiki/Requirement" title="Requirement">required functions</a> for a new ASIC, usually derived from <a href="/wiki/Requirements_analysis" title="Requirements analysis">requirements analysis</a>.</li> <li><b><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> (RTL) design</b>: The design team constructs a description of an ASIC to achieve these goals using a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a>. This process is similar to writing a computer program in a <a href="/wiki/High-level_programming_language" title="High-level programming language">high-level language</a>.</li> <li><b><a href="/wiki/Functional_verification" title="Functional verification">Functional verification</a></b>: Suitability for purpose is verified by functional verification. This may include such techniques as <a href="/wiki/Logic_simulation" title="Logic simulation">logic simulation</a> through <a href="/wiki/Test_bench" title="Test bench">test benches</a>, <a href="/wiki/Formal_verification" title="Formal verification">formal verification</a>, <a href="/wiki/Hardware_emulation" title="Hardware emulation">emulation</a>, or creating and evaluating an equivalent pure <a href="/wiki/Software" title="Software">software</a> model, as in <a href="/wiki/Simics" title="Simics">Simics</a>. Each verification technique has advantages and disadvantages, and most often several methods are used together for ASIC verification. Unlike most <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGAs</a>, ASICs cannot be <a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">reprogrammed</a> once <a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">fabricated</a> and therefore ASIC designs that are not completely correct are much more costly, increasing the need for full <a href="/wiki/Test_coverage" class="mw-redirect" title="Test coverage">test coverage</a>.</li> <li><b>Logic synthesis</b>: <a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a> transforms the RTL design into a large collection called of lower-level constructs called standard cells. These constructs are taken from a <a href="/wiki/Library_(electronics)" class="mw-redirect" title="Library (electronics)">standard-cell library</a> consisting of pre-characterized collections of <a href="/wiki/Logic_gate" title="Logic gate">logic gates</a> performing specific functions. The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells and the needed electrical connections between them is called a gate-level <a href="/wiki/Netlist" title="Netlist">netlist</a>.</li> <li><b>Placement</b>: The gate-level netlist is next processed by a <a href="/wiki/Placement_(EDA)" class="mw-redirect" title="Placement (EDA)">placement</a> tool which places the standard cells onto a region of an <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">integrated circuit die</a> representing the final ASIC. The placement tool attempts to find an <a href="/wiki/Mathematical_optimization" title="Mathematical optimization">optimized</a> placement of the standard cells, subject to a variety of specified constraints.</li> <li><b>Routing</b>: An electronics <a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">routing</a> tool takes the physical placement of the standard cells and uses the netlist to create the <a href="/wiki/Electrical_connection" class="mw-redirect" title="Electrical connection">electrical connections</a> between them. Since the <a href="/wiki/Optimization_problem#Search_space" title="Optimization problem">search space</a> is large, this process will produce a "sufficient" rather than "<a href="/wiki/Global_optimum" class="mw-redirect" title="Global optimum">globally optimal</a>" solution. The output is a file which can be used to create a set of <a href="/wiki/Photomask" title="Photomask">photomasks</a> enabling a <a href="/wiki/Semiconductor_fabrication_plant" title="Semiconductor fabrication plant">semiconductor fabrication facility</a>, commonly called a 'fab' or 'foundry' to <a href="/wiki/Manufacturing" title="Manufacturing">manufacture</a> physical <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a>. Placement and routing are closely interrelated and are collectively called <a href="/wiki/Place_and_route" title="Place and route">place and route</a> in electronics design.</li> <li><b>Sign-off</b>: Given the final layout, <a href="/wiki/Circuit_extraction" title="Circuit extraction">circuit extraction</a> computes the <a href="/wiki/Parasitic_element_(electrical_networks)" class="mw-redirect" title="Parasitic element (electrical networks)">parasitic resistances and capacitances</a>. In the case of a <a href="/wiki/Digital_circuit" class="mw-redirect" title="Digital circuit">digital circuit</a>, this will then be further mapped into <a href="/wiki/Propagation_delay" title="Propagation delay">delay information</a> from which the circuit performance can be estimated, usually by <a href="/wiki/Static_timing_analysis" title="Static timing analysis">static timing analysis</a>. This, and other final tests such as <a href="/wiki/Design_rule_checking" title="Design rule checking">design rule checking</a> and <a href="/wiki/Power_analysis" title="Power analysis">power analysis</a> collectively called <a href="/wiki/Signoff_(electronic_design_automation)" title="Signoff (electronic design automation)">signoff</a> are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the <a href="/wiki/Photomask" title="Photomask">photomask</a> information is released for <a href="/wiki/Chip_fabrication" class="mw-redirect" title="Chip fabrication">chip fabrication</a>.</li></ol> <p>These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>The design steps also called <a href="/wiki/Design_flow_(EDA)" title="Design flow (EDA)">design flow</a>, are also common to standard product design. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than a full custom design. Standard cells produce a <a href="/wiki/Transistor_density" class="mw-redirect" title="Transistor density">design density</a> that is cost-effective, and they can also integrate <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP cores</a> and <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM) effectively, unlike gate arrays. </p> <div class="mw-heading mw-heading2"><h2 id="Gate-array_and_semi-custom_design">Gate-array and semi-custom design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=3" title="Edit section: Gate-array and semi-custom design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:S-MOS_Systems_ASIC_SLA6140.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/S-MOS_Systems_ASIC_SLA6140.jpg/220px-S-MOS_Systems_ASIC_SLA6140.jpg" decoding="async" width="220" height="223" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/S-MOS_Systems_ASIC_SLA6140.jpg/330px-S-MOS_Systems_ASIC_SLA6140.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9c/S-MOS_Systems_ASIC_SLA6140.jpg/440px-S-MOS_Systems_ASIC_SLA6140.jpg 2x" data-file-width="2409" data-file-height="2445" /></a><figcaption>Microscope photograph of a gate-array ASIC showing the predefined logic cells and custom interconnections. This particular design uses less than 20% of available logic gates.</figcaption></figure> <p><a href="/wiki/Gate_array" title="Gate array">Gate array</a> design is a manufacturing method in which diffused layers, each consisting of <a href="/wiki/Transistor" title="Transistor">transistors</a> and other <a href="/wiki/Active_element" class="mw-redirect" title="Active element">active devices</a>, are predefined and <a href="/wiki/Wafer_(electronics)" title="Wafer (electronics)">electronics wafers</a> containing such devices are "held in stock" or unconnected prior to the <a href="/wiki/Metallizing" title="Metallizing">metallization</a> stage of the <a href="/wiki/Fabrication_process" class="mw-redirect" title="Fabrication process">fabrication process</a>. The <a href="/wiki/Physical_design_(electronics)" title="Physical design (electronics)">physical design</a> process defines the interconnections of these layers for the final device. For most ASIC manufacturers, this consists of between two and nine metal layers with each layer running perpendicular to the one below it. Non-recurring engineering costs are much lower than full custom designs, as <a href="/wiki/Photolithography" title="Photolithography">photolithographic</a> masks are required only for the metal layers. Production cycles are much shorter, as metallization is a comparatively quick process; thereby accelerating <a href="/wiki/Time_to_market" title="Time to market">time to market</a>. </p><p>Gate-array ASICs are always a compromise between rapid design and <a href="/wiki/Computer_performance" title="Computer performance">performance</a> as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% <a href="/wiki/Circuit_utilization" class="mw-redirect" title="Circuit utilization">circuit utilization</a>. Often difficulties in <a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">routing</a> the interconnect require migration onto a larger array device with a consequent increase in the piece part price. These difficulties are often a result of the layout <a href="/wiki/Electronic_design_automation" title="Electronic design automation">EDA</a> software used to develop the interconnect. </p><p>Pure, logic-only gate-array design is rarely implemented by circuit designers today, having been almost entirely replaced by <a href="/wiki/Field-programmability" title="Field-programmability">field-programmable</a> devices. The most prominent of such devices are <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGAs) which can be programmed by the user and thus offer minimal tooling charges, non-recurring engineering, only marginally increased piece part cost, and comparable performance. </p><p>Today, gate arrays are evolving into <a href="/wiki/Structured_ASIC_platform" title="Structured ASIC platform">structured ASICs</a> that consist of a large <a href="/wiki/IP_core" class="mw-redirect" title="IP core">IP core</a> like a <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a>, <a href="/wiki/Digital_signal_processor" title="Digital signal processor">digital signal processor</a> units, <a href="/wiki/Peripheral" title="Peripheral">peripherals</a>, standard <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">interfaces</a>, integrated <a href="/wiki/Computer_memory" title="Computer memory">memories</a>, <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a>, and a block of <a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">reconfigurable</a>, uncommitted logic. This shift is largely because ASIC devices are capable of integrating large blocks of <a href="/wiki/Systems_engineering" title="Systems engineering">system</a> functionality, and <a href="/wiki/System_on_a_chip" title="System on a chip">systems on a chip</a> (SoCs) require <a href="/wiki/Glue_logic" title="Glue logic">glue logic</a>, <a href="/wiki/Communications_system" title="Communications system">communications subsystems</a> (such as <a href="/wiki/Network_on_a_chip" title="Network on a chip">networks on chip</a>), <a href="/wiki/Peripheral" title="Peripheral">peripherals</a>, and other components rather than only <a href="/wiki/Functional_unit" class="mw-redirect" title="Functional unit">functional units</a> and basic interconnection. </p><p>In their frequent usages in the field, the terms "gate array" and "semi-custom" are synonymous when referring to ASICs. <a href="/wiki/Process_engineering" title="Process engineering">Process engineers</a> more commonly use the term "semi-custom", while "gate-array" is more commonly used by logic (or gate-level) designers. </p> <div class="mw-heading mw-heading2"><h2 id="Full-custom_design">Full-custom design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=4" title="Edit section: Full-custom design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Full_custom" title="Full custom">Full custom</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/7b/VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg/220px-VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg" decoding="async" width="220" height="215" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/7b/VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg/330px-VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/7b/VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg/440px-VLSI_VL82C486_Single_Chip_486_System_Controller_HV.jpg 2x" data-file-width="2509" data-file-height="2454" /></a><figcaption>Microscope photograph of custom ASIC (486 chipset) showing gate-based design on top and custom circuitry on bottom</figcaption></figure> <p>By contrast, full-custom ASIC design defines all the photolithographic layers of the device.<sup id="cite_ref-MichaelJohnSebastianSmith_7-1" class="reference"><a href="#cite_note-MichaelJohnSebastianSmith-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Full-custom design is used for both ASIC design and for standard product design. </p><p>The benefits of full-custom design include reduced area (and therefore recurring component cost), <a href="/wiki/Computer_performance" title="Computer performance">performance</a> improvements, and also the ability to integrate <a href="/wiki/Analog_signal" title="Analog signal">analog</a> components and other <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">pre-designed</a>—and thus fully verified—components, such as <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> cores, that form a <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a>. </p><p>The disadvantages of full-custom design can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the <a href="/wiki/Computer-aided_design" title="Computer-aided design">computer-aided design</a> (CAD) and <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic design automation</a> systems, and a much higher skill requirement on the part of the design team. </p><p>For digital-only designs, however, "standard-cell" cell libraries, together with modern CAD systems, can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimize any performance-limiting aspect of the design. </p><p>This is designed by using basic logic gates, circuits or layout specially for a design. </p> <div class="mw-heading mw-heading2"><h2 id="Structured_design">Structured design</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=5" title="Edit section: Structured design"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Structured_ASIC_platform" title="Structured ASIC platform">Structured ASIC platform</a> and <a href="/wiki/Platform-based_design" title="Platform-based design">Platform-based design</a></div> <p><i>Structured ASIC design</i> (also referred to as "<i>platform ASIC design</i>") is a relatively new trend in the semiconductor industry, resulting in some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). </p><p> Definition from Foundations of Embedded Systems states that:<sup id="cite_ref-9" class="reference"><a href="#cite_note-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> <style data-mw-deduplicate="TemplateStyles:r1244412712">.mw-parser-output .templatequote{overflow:hidden;margin:1em 0;padding:0 32px}.mw-parser-output .templatequotecite{line-height:1.5em;text-align:left;margin-top:0}@media(min-width:500px){.mw-parser-output .templatequotecite{padding-left:1.6em}}</style></p><blockquote class="templatequote"><p>In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design.</p><div class="templatequotecite">— <cite>Foundations of Embedded Systems</cite></div></blockquote> <p>This is effectively the same definition as a gate array. What distinguishes a structured ASIC from a gate array is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC, the use of predefined metallization is primarily to reduce cost of the mask sets as well as making the design cycle time significantly shorter. </p><p>For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves. By contrast, these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array based designs. Likewise, the design tools used for structured ASIC can be substantially lower cost and easier (faster) to use than cell-based tools, because they do not have to perform all the functions that cell-based tools do. In some cases, the structured ASIC vendor requires customized tools for their device (e.g., custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly. </p> <div class="mw-heading mw-heading2"><h2 id="Cell_libraries,_IP-based_design,_hard_and_soft_macros"><span id="Cell_libraries.2C_IP-based_design.2C_hard_and_soft_macros"></span>Cell libraries, IP-based design, hard and soft macros</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=6" title="Edit section: Cell libraries, IP-based design, hard and soft macros"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Library_(electronics)" class="mw-redirect" title="Library (electronics)">Cell libraries</a> of logical primitives are usually provided by the device manufacturer as part of the service. Although they will incur no additional cost, their release will be covered by the terms of a <a href="/wiki/Non-disclosure_agreement" title="Non-disclosure agreement">non-disclosure agreement</a> (NDA) and they will be regarded as intellectual property by the manufacturer. Usually, their physical design will be pre-defined so they could be termed "hard macros". </p><p>What most engineers understand as "<a href="/wiki/Intellectual_property" title="Intellectual property">intellectual property</a>" are <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">IP cores</a>, designs purchased from a third-party as sub-components of a larger ASIC. They may be provided in the form of a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> (often termed a "soft macro"), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a "hard macro"). Many organizations now sell such pre-designed cores – CPUs, Ethernet, USB or telephone interfaces – and larger organizations may have an entire department or division to produce cores for the rest of the organization. The company <a href="/wiki/ARM_(company)" class="mw-redirect" title="ARM (company)">ARM</a> <i>only</i> sells IP cores, making it a <a href="/wiki/Fabless_manufacturing" title="Fabless manufacturing">fabless manufacturer</a>. </p><p>Indeed, the wide range of functions now available in structured ASIC design is a result of the phenomenal improvement in electronics in the late 1990s and early 2000s; as a core takes a lot of time and investment to create, its <a href="/wiki/Code_reuse" title="Code reuse">re-use</a> and further development cuts product cycle times dramatically and creates better products. Additionally, <a href="/wiki/Open-source_hardware" title="Open-source hardware">open-source hardware</a> organizations such as <a href="/wiki/OpenCores" title="OpenCores">OpenCores</a> are collecting free IP cores, paralleling the <a href="/wiki/Open-source_software" title="Open-source software">open-source software</a> movement in hardware design. </p><p>Soft macros are often process-independent (i.e. they can be fabricated on a wide range of manufacturing processes and different manufacturers). Hard macros are process-limited and usually further design effort must be invested to migrate (port) to a different process or manufacturer. </p> <div class="mw-heading mw-heading2"><h2 id="Multi-project_wafers">Multi-project wafers</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=7" title="Edit section: Multi-project wafers"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Some manufacturers and IC design houses offer <a href="/wiki/Multi-project_wafer_service" title="Multi-project wafer service">multi-project wafer service</a> (MPW) as a method of obtaining low cost prototypes. Often called shuttles, these MPWs, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, usually with limited liability on the part of the manufacturer. The contract involves delivery of bare dies or the assembly and packaging of a handful of devices. The service usually involves the supply of a physical design database (i.e. masking information or pattern generation (PG) tape). The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the process. </p> <div class="mw-heading mw-heading2"><h2 id="Application-specific_standard_product">Application-specific standard product</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=8" title="Edit section: Application-specific standard product"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/74/Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg/220px-Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/74/Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg/330px-Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/74/Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg/440px-Kyocera_FS-C5200DN_-_interface_board_-_Renesas_M66591GP-4189.jpg 2x" data-file-width="3790" data-file-height="3790" /></a><figcaption><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> M66591GP: USB2.0 Peripheral Controller</figcaption></figure> <p>An <b>application-specific standard product</b> or <b>ASSP</b> is an <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> that implements a specific <a href="/wiki/Function_(engineering)" title="Function (engineering)">function</a> that appeals to a wide market. As opposed to ASICs that combine a collection of functions and are designed by or for one <a href="/wiki/Customer" title="Customer">customer</a>, ASSPs are available as off-the-shelf components. ASSPs are used in all industries, from automotive to communications.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (August 2017)">citation needed</span></a></i>]</sup> As a general rule, if you can find a <a href="/wiki/Design" title="Design">design</a> in a data <a href="/wiki/Book" title="Book">book</a>, then it is probably not an ASIC, but there are some exceptions.<sup class="noprint Inline-Template" style="margin-left:0.1em; white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Please_clarify" title="Wikipedia:Please clarify"><span title="The text near this tag may need clarification or removal of jargon. (January 2020)">clarification needed</span></a></i>]</sup> </p><p>For example, two ICs that might or might not be considered ASICs are a controller chip for a PC and a chip for a <a href="/wiki/Modem" title="Modem">modem</a>. Both of these examples are specific to an application (which is typical of an ASIC) but are sold to many different system vendors (which is typical of standard parts). ASICs such as these are sometimes called application-specific standard products (ASSPs). </p><p>Examples of ASSPs are encoding/decoding chip, Ethernet network interface controller chip, etc. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=9" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col"> <ul><li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific instruction set processor</a> (ASIP)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a> (EDA or ECAD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Multi-project_chip" class="mw-redirect" title="Multi-project chip">Multi-project chip</a> (MPC)</li> <li><a href="/wiki/Very_Large_Scale_Integration" class="mw-redirect" title="Very Large Scale Integration">Very Large Scale Integration</a> (VLSI)</li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a> for an overview of computing based primarily in hardware</li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=10" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFGolshan2007" class="citation book cs1">Golshan, Khosrow (2007). <i>Physical Design Essentials: An ASIC Design Implementation Perspective</i>. Boston, MA: Springer. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-387-36642-5" title="Special:BookSources/978-0-387-36642-5"><bdi>978-0-387-36642-5</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Physical+Design+Essentials%3A+An+ASIC+Design+Implementation+Perspective&rft.place=Boston%2C+MA&rft.pub=Springer&rft.date=2007&rft.isbn=978-0-387-36642-5&rft.aulast=Golshan&rft.aufirst=Khosrow&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-:0-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-:0_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-:0_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBarr2007" class="citation book cs1">Barr, Keith (2007). <span class="id-lock-registration" title="Free registration required"><a rel="nofollow" class="external text" href="https://archive.org/details/asicdesigninsili0000barr"><i>ASIC Design in the Silicon Sandbox: A Complete Guide to Building Mixed-signal Integrated Circuits</i></a></span>. New York: McGraw-Hill. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-07-148161-8" title="Special:BookSources/978-0-07-148161-8"><bdi>978-0-07-148161-8</bdi></a>. <a href="/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/76935560">76935560</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=ASIC+Design+in+the+Silicon+Sandbox%3A+A+Complete+Guide+to+Building+Mixed-signal+Integrated+Circuits&rft.place=New+York&rft.pub=McGraw-Hill&rft.date=2007&rft_id=info%3Aoclcnum%2F76935560&rft.isbn=978-0-07-148161-8&rft.aulast=Barr&rft.aufirst=Keith&rft_id=https%3A%2F%2Farchive.org%2Fdetails%2Fasicdesigninsili0000barr&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-computerhistory1967-3"><span class="mw-cite-backlink">^ <a href="#cite_ref-computerhistory1967_3-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-computerhistory1967_3-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-computerhistory1967_3-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-computerhistory1967_3-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.computerhistory.org/siliconengine/application-specific-integrated-circuits-employ-computer-aided-design/">"1967: Application Specific Integrated Circuits employ Computer-Aided Design"</a>. <i>The Silicon Engine</i>. <a href="/wiki/Computer_History_Museum" title="Computer History Museum">Computer History Museum</a><span class="reference-accessdate">. Retrieved <span class="nowrap">9 November</span> 2019</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Silicon+Engine&rft.atitle=1967%3A+Application+Specific+Integrated+Circuits+employ+Computer-Aided+Design&rft_id=https%3A%2F%2Fwww.computerhistory.org%2Fsiliconengine%2Fapplication-specific-integrated-circuits-employ-computer-aided-design%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKriegbaum2004" class="citation web cs1">Kriegbaum, Jeff (13 September 2004). <a rel="nofollow" class="external text" href="https://www.eetimes.com/fpgas-vs-asics/">"FPGA's vs. ASIC's"</a>. <i><a href="/wiki/EE_Times" title="EE Times">EE Times</a></i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=FPGA%27s+vs.+ASIC%27s&rft.date=2004-09-13&rft.aulast=Kriegbaum&rft.aufirst=Jeff&rft_id=https%3A%2F%2Fwww.eetimes.com%2Ffpgas-vs-asics%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://www.computerhistory.org/collections/catalog/102706880"><i>Lipp, Bob oral history</i></a>. Computer History Museum. 14 February 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">28 January</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Lipp%2C+Bob+oral+history&rft.pub=Computer+History+Museum&rft.date=2017-02-14&rft_id=http%3A%2F%2Fwww.computerhistory.org%2Fcollections%2Fcatalog%2F102706880&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span> <span class="cs1-visible-error citation-comment"><code class="cs1-code">{{<a href="/wiki/Template:Cite_book" title="Template:Cite book">cite book</a>}}</code>: </span><span class="cs1-visible-error citation-comment"><code class="cs1-code">|website=</code> ignored (<a href="/wiki/Help:CS1_errors#periodical_ignored" title="Help:CS1 errors">help</a>)</span></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.computerhistory.org/siliconengine/people/">"People"</a>. <i>The Silicon Engine</i>. Computer History Museum<span class="reference-accessdate">. Retrieved <span class="nowrap">28 January</span> 2018</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Silicon+Engine&rft.atitle=People&rft_id=http%3A%2F%2Fwww.computerhistory.org%2Fsiliconengine%2Fpeople%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-MichaelJohnSebastianSmith-7"><span class="mw-cite-backlink">^ <a href="#cite_ref-MichaelJohnSebastianSmith_7-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-MichaelJohnSebastianSmith_7-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFSmith,_Michael_John_Sebastian1997" class="citation book cs1">Smith, Michael John Sebastian (1997). <i>Application-Specific Integrated Circuits</i>. Addison-Wesley Professional. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-201-50022-6" title="Special:BookSources/978-0-201-50022-6"><bdi>978-0-201-50022-6</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Application-Specific+Integrated+Circuits&rft.pub=Addison-Wesley+Professional&rft.date=1997&rft.isbn=978-0-201-50022-6&rft.au=Smith%2C+Michael+John+Sebastian&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHurley,_Jaden_Mclean_&_Carmen.2019" class="citation book cs1">Hurley, Jaden Mclean & Carmen. (2019). <i>Logic Design</i>. EDTECH. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-83947-319-7" title="Special:BookSources/978-1-83947-319-7"><bdi>978-1-83947-319-7</bdi></a>. <a href="/wiki/OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/1132366891">1132366891</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Logic+Design&rft.pub=EDTECH&rft.date=2019&rft_id=info%3Aoclcnum%2F1132366891&rft.isbn=978-1-83947-319-7&rft.au=Hurley%2C+Jaden+Mclean+%26+Carmen.&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> <li id="cite_note-9"><span class="mw-cite-backlink"><b><a href="#cite_ref-9">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFBarkalovTitarenkoMazurkiewicz2019" class="citation book cs1">Barkalov, Alexander; Titarenko, Larysa; Mazurkiewicz, Małgorzata (2019). <i>Foundations of Embedded Systems</i>. Studies in Systems, Decision and Control. Vol. 195. Cham: Springer International Publishing. <a href="/wiki/Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1007%2F978-3-030-11961-4">10.1007/978-3-030-11961-4</a>. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/9783030119607" title="Special:BookSources/9783030119607"><bdi>9783030119607</bdi></a>. <a href="/wiki/S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:86596100">86596100</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Foundations+of+Embedded+Systems&rft.place=Cham&rft.series=Studies+in+Systems%2C+Decision+and+Control&rft.pub=Springer+International+Publishing&rft.date=2019&rft_id=https%3A%2F%2Fapi.semanticscholar.org%2FCorpusID%3A86596100%23id-name%3DS2CID&rft_id=info%3Adoi%2F10.1007%2F978-3-030-11961-4&rft.isbn=9783030119607&rft.aulast=Barkalov&rft.aufirst=Alexander&rft.au=Titarenko%2C+Larysa&rft.au=Mazurkiewicz%2C+Ma%C5%82gorzata&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Sources">Sources</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=11" title="Edit section: Sources"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAnthony_Cataldo2002" class="citation news cs1">Anthony Cataldo (26 March 2002). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20070929100135/http://www.eetimes.com/story/OEG20020325S0060">"Xilinx looks to ease path to custom FPGAs"</a>. <i>EE Times</i>. CMP Media, LLC. Archived from <a rel="nofollow" class="external text" href="http://www.eetimes.com/story/OEG20020325S0060">the original</a> on 29 September 2007<span class="reference-accessdate">. Retrieved <span class="nowrap">14 December</span> 2006</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EE+Times&rft.atitle=Xilinx+looks+to+ease+path+to+custom+FPGAs&rft.date=2002-03-26&rft.au=Anthony+Cataldo&rft_id=http%3A%2F%2Fwww.eetimes.com%2Fstory%2FOEG20020325S0060&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation news cs1"><a rel="nofollow" class="external text" href="http://www.thefreelibrary.com/Xilinx+intros+next-gen+EasyPath+FPGAs+priced+below+structured+ASICs.-a0125948398">"Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs"</a>. <i>EDP Weekly's IT Monitor</i>. Millin Publishing, Inc. 18 October 2004.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.jtitle=EDP+Weekly%27s+IT+Monitor&rft.atitle=Xilinx+intros+next-gen+EasyPath+FPGAs+priced+below+structured+ASICs&rft.date=2004-10-18&rft_id=http%3A%2F%2Fwww.thefreelibrary.com%2FXilinx%2Bintros%2Bnext-gen%2BEasyPath%2BFPGAs%2Bpriced%2Bbelow%2Bstructured%2BASICs.-a0125948398&rfr_id=info%3Asid%2Fen.wikipedia.org%3AApplication-specific+integrated+circuit" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Application-specific_integrated_circuit&action=edit&section=12" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Commons-logo.svg" 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href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a class="mw-selflink selflink">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Central_processing_unit" title="Central processing unit">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Programmable_logic" title="Template:Programmable logic"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Programmable_logic" title="Template talk:Programmable logic"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Programmable_logic" title="Special:EditPage/Template:Programmable logic"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Programmable_logic" style="font-size:114%;margin:0 4em"><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">ASIC</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> <ul><li><a href="/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Digital_electronics" title="Template:Digital electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Digital_electronics" title="Template talk:Digital electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Digital_electronics" title="Special:EditPage/Template:Digital electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Digital_electronics" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a class="mw-selflink selflink">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Hardware_acceleration" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Hardware_acceleration" title="Template:Hardware acceleration"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Hardware_acceleration" title="Template talk:Hardware acceleration"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Hardware_acceleration" title="Special:EditPage/Template:Hardware acceleration"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Hardware_acceleration" style="font-size:114%;margin:0 4em"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Models_of_computation" class="mw-redirect" title="Models of computation">Theory</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal Turing machine</a></li> <li><a href="/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></li> <li><a href="/wiki/Distributed_computing" title="Distributed computing">Distributed computing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a> <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li> <li><a href="/wiki/DirectX_Video_Acceleration" title="DirectX Video Acceleration">DirectX</a></li></ul></li> <li><a href="/wiki/Sound_card" title="Sound card">Audio</a></li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processing</a></li> <li><a href="/wiki/Hardware_random_number_generator" title="Hardware random number generator">Hardware random number generation</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">Artificial intelligence</a></li> <li><a href="/wiki/Cryptographic_accelerator" title="Cryptographic accelerator">Cryptography</a> <ul><li><a href="/wiki/TLS_acceleration" title="TLS acceleration">TLS</a></li></ul></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Machine vision</a></li> <li><a href="/wiki/Custom_hardware_attack" title="Custom hardware attack">Custom hardware attack</a> <ul><li><a href="/wiki/Scrypt" title="Scrypt">scrypt</a></li></ul></li> <li><a href="/wiki/Network_processor" title="Network processor">Networking</a></li> <li><a href="/wiki/Data_processing_unit" title="Data processing unit">Data</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Implementations</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a> <ul><li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li></ul></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a class="mw-selflink selflink">ASIC</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> <ul><li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport triggered</a></li> <li><a href="/wiki/Multicore" class="mw-redirect" title="Multicore">Multicore</a></li> <li><a href="/wiki/Manycore" class="mw-redirect" title="Manycore">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous</a></li> <li><a href="/wiki/In-memory_processing" title="In-memory processing">In-memory computing</a></li> <li><a href="/wiki/Systolic_array" title="Systolic array">Systolic array</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Programmable_logic" class="mw-redirect" title="Programmable logic">Programmable logic</a></li> <li><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor</a> <ul><li><a href="/wiki/Processor_design" title="Processor design">design</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">chronology</a></li></ul></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Virtualization" title="Virtualization">Virtualization</a> <ul><li><a href="/wiki/Hardware_emulation" title="Hardware emulation">Hardware emulation</a></li></ul></li> <li><a href="/wiki/Logic_synthesis" title="Logic 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