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<!DOCTYPE html> <html lang="en"> <head> <meta content="text/html; charset=utf-8" http-equiv="content-type"/> <title>Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs</title>  <meta content="width=device-width, initial-scale=1, shrink-to-fit=no" name="viewport"/> <link href="https://cdn.jsdelivr.net/npm/bootstrap@5.3.0/dist/css/bootstrap.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/ar5iv.0.7.9.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/ar5iv-fonts.0.7.9.min.css" rel="stylesheet" type="text/css"/> <link href="/static/browse/0.3.4/css/latexml_styles.css" rel="stylesheet" type="text/css"/> <script src="https://cdn.jsdelivr.net/npm/bootstrap@5.3.0/dist/js/bootstrap.bundle.min.js"></script> <script src="https://cdnjs.cloudflare.com/ajax/libs/html2canvas/1.3.3/html2canvas.min.js"></script> <script src="/static/browse/0.3.4/js/addons_new.js"></script> <script src="/static/browse/0.3.4/js/feedbackOverlay.js"></script> <meta content="Flash, SSD, Storage, Caching, FDP, Data placement, Small objects" lang="en" name="keywords"/> <base href="/html/2503.11665v1/"/></head> <body> <nav class="ltx_page_navbar"> <nav class="ltx_TOC"> <ol class="ltx_toclist"> <li class="ltx_tocentry ltx_tocentry_section"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S1" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">1 </span>Introduction</span></a></li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">2 </span>Background</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2.SS1" title="In 2. Background ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">2.1 </span>SSDs and Write Amplification</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2.SS2" title="In 2. Background ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">2.2 </span>DLWA and Carbon Emissions</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2.SS3" title="In 2. Background ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">2.3 </span>Flash Caches and CacheLib</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3 </span>NVMe Flexible Data Placement (FDP)</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS1" title="In 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.1 </span>Overview</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS2" title="In 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.2 </span>Physical Isolation in SSDs with FDP</span></a> <ol class="ltx_toclist ltx_toclist_subsection"> <li class="ltx_tocentry ltx_tocentry_subsubsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS2.SSS1" title="In 3.2. Physical Isolation in SSDs with FDP ‣ 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.2.1 </span>FDP Architectural Concepts</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsubsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS2.SSS2" title="In 3.2. Physical Isolation in SSDs with FDP ‣ 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.2.2 </span>Data Placement with RUHs</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS3" title="In 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.3 </span>FDP Events and Statistics</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS4" title="In 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.4 </span>FDP and Other Major Data Placement Proposals</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.SS5" title="In 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">3.5 </span>Limitations</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">4 </span>Why FDP Matters for CacheLib and Hybrid Caches?</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.SS1" title="In 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">4.1 </span>Insights and Observations</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.SS2" title="In 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">4.2 </span>Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions</span></a> <ol class="ltx_toclist ltx_toclist_subsection"> <li class="ltx_tocentry ltx_tocentry_subsubsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.SS2.SSS1" title="In 4.2. Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">4.2.1 </span>Modelling CO2 emissions (CO2e) for FDP-enabled CacheLib</span></a></li> </ol> </li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5 </span>Design and Implementation</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.SS1" title="In 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5.1 </span>Design Principles</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.SS2" title="In 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5.2 </span>Placement Handles</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.SS3" title="In 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5.3 </span>Placement Handle Allocator</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.SS4" title="In 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5.4 </span>FDP Aware I/O Management</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.SS5" title="In 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">5.5 </span>Lessons Learned and Future Directions</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6 </span>Evaluation</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS1" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.1 </span>Experimental Setup</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS2" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.2 </span>FDP-based segregation achieves a DLWA of <math alttext="\sim" class="ltx_Math" display="inline"><semantics><mo>∼</mo><annotation-xml encoding="MathML-Content"><csymbol cd="latexml">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex">\sim</annotation><annotation encoding="application/x-llamapun">∼</annotation></semantics></math>1</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS3" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.3 </span>FDP-based segregation enables better SSD utilization without affecting performance</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS4" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.4 </span>FDP-based segregation lowers DLWA with other write-intensive workloads</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS5" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.5 </span>FDP-based segregation gains diminish with increase in SOC size</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS6" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.6 </span>FDP-based segregation enables cost-effective and carbon-efficient CacheLib deployments</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS7" title="In 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">6.7 </span>FDP-based segregation enables multi-tenant KV Cache deployments</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S7" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">7 </span>Related Work</span></a> <ol class="ltx_toclist ltx_toclist_section"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S7.SS1" title="In 7. Related Work ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">7.1 </span>Data Placement in SSDs</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S7.SS2" title="In 7. Related Work ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">7.2 </span>Key-Value Stores and Hybrid Caching</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_section"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S8" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">8 </span>Conclusion</span></a></li> <li class="ltx_tocentry ltx_tocentry_appendix"> <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">A </span>Theoretical Model of DLWA in FDP-enabled CacheLib</span></a> <ol class="ltx_toclist ltx_toclist_appendix"> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.SS1" title="In Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">A.1 </span>System Model: Assumptions and Observations</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.SS2" title="In Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">A.2 </span>Derivation</span></a></li> <li class="ltx_tocentry ltx_tocentry_subsection"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.SS3" title="In Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">A.3 </span>Validation of the DLWA Model with FDP-enabled CacheLib Empirical Result</span></a></li> </ol> </li> <li class="ltx_tocentry ltx_tocentry_appendix"><a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A2" title="In Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_title"><span class="ltx_tag ltx_tag_ref">B </span>FDP-based Segregation Benefits with WO KV Cache Workload</span></a></li> </ol></nav> </nav> <div class="ltx_page_main"> <div class="ltx_page_content"> <article class="ltx_document ltx_authors_1line ltx_leqno"> <h1 class="ltx_title ltx_title_document">Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs</h1> <div class="ltx_authors"> <span class="ltx_creator ltx_role_author"> <span class="ltx_personname">Michael Allison, Arun George, Javier Gonzalez, Dan Helmick, Vikash Kumar, Roshan R Nair, <br class="ltx_break"/>Vivek Shah </span><span class="ltx_author_notes"> <span class="ltx_contact ltx_role_affiliation"><span class="ltx_text ltx_affiliation_institution" id="id1.1.id1">Samsung Electronics</span><span class="ltx_text ltx_affiliation_city" id="id2.2.id2"></span><span class="ltx_text ltx_affiliation_country" id="id3.3.id3"></span> </span></span></span> </div> <div class="ltx_dates">(2025)</div> <div class="ltx_abstract"> <h6 class="ltx_title ltx_title_abstract">Abstract.</h6> <p class="ltx_p" id="id4.id1">NVMe Flash-based SSDs are widely deployed in data centers to cache working sets of large-scale web services. As data centers face increasing sustainability demands, such as reduced carbon emissions, efficient management of Flash overprovisioning and endurance has become crucial. Our analysis demonstrates that mixing data with different lifetimes on Flash blocks results in high device garbage collection costs, which either reduce device lifetime or necessitate host overprovisioning. Targeted data placement on Flash to minimize data intermixing and thus device write amplification shows promise for addressing this issue.</p> <p class="ltx_p" id="id5.id2">The NVMe Flexible Data Placement (FDP) proposal is a newly ratified technical proposal aimed at addressing data placement needs while reducing the software engineering costs associated with past storage interfaces, such as ZNS and Open-Channel SSDs. In this study, we explore the feasibility, benefits, and limitations of leveraging NVMe FDP primitives for data placement on Flash media in CacheLib, a popular open-source Flash cache widely deployed and used in Meta’s software ecosystem as a caching building block. We demonstrate that targeted data placement in CacheLib using NVMe FDP SSDs helps reduce device write amplification, embodied carbon emissions, and power consumption with almost no overhead to other metrics. Using multiple production traces and their configurations from Meta and Twitter, we show that an ideal device write amplification of ~1 can be achieved with FDP, leading to improved SSD utilization and sustainable Flash cache deployments.</p> </div> <div class="ltx_keywords">Flash, SSD, Storage, Caching, FDP, Data placement, Small objects </div> <span class="ltx_note ltx_note_frontmatter ltx_role_submissionid" id="id1"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">submissionid: </span>¡751¿</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_ccs" id="id2"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">ccs: </span>Information systems Flash memory</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_ccs" id="id3"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">ccs: </span>Hardware External storage</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_ccs" id="id4"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">ccs: </span>Computer systems organization Cloud computing</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_journalyear" id="id5"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">journalyear: </span>2025</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_copyright" id="id6"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">copyright: </span>rightsretained</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_conference" id="id7"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">conference: </span>Twentieth European Conference on Computer Systems; March 30–April 3, 2025; Rotterdam, Netherlands</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_booktitle" id="id8"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">booktitle: </span>Twentieth European Conference on Computer Systems (EuroSys ’25), March 30–April 3, 2025, Rotterdam, Netherlands</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_doi" id="id9"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">doi: </span>10.1145/3689031.3696091</span></span></span><span class="ltx_note ltx_note_frontmatter ltx_role_isbn" id="id10"><sup class="ltx_note_mark">†</sup><span class="ltx_note_outer"><span class="ltx_note_content"><sup class="ltx_note_mark">†</sup><span class="ltx_note_type">isbn: </span>979-8-4007-1196-1/25/03</span></span></span> <section class="ltx_section" id="S1"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">1. </span>Introduction</h2> <div class="ltx_para" id="S1.p1"> <p class="ltx_p" id="S1.p1.1">Caching is an intuitive and pervasive technique employed in modern large-scale web service architectures for high performance and better resource utilization. These web services range across various domains e.g., social networks, microblogging platforms, and emerging IoT applications, to name a few <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; Yang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib60" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Bronson et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib28" title="">2013</a>)</cite>. <span class="ltx_text ltx_font_italic" id="S1.p1.1.1">The challenges in the design of the caching solutions for this domain are (1) the large working set size and (2) the problem of caching objects of different sizes, especially dominated by numerous small-sized objects <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Yang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib60" title="">2020</a>)</cite></span>. The use of Flash-based SSDs has become popular in the design of these caches given their excellent performance cost tradeoff compared to DRAM and HDD <cite class="ltx_cite ltx_citemacro_citep">(Tang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib57" title="">2015</a>; Eisenman et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib33" title="">2019</a>; Wong et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib59" title="">2024</a>; Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite>. However, managing the limited write endurance of Flash in these caches remains a challenge <cite class="ltx_cite ltx_citemacro_citep">(Lee et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib43" title="">2015</a>; He et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib37" title="">2017</a>; Jung and Kandemir, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib40" title="">2013</a>)</cite>. To maximize Flash lifetime in Flash caches, extensive research has gone into admission policies, application write amplification, and caching algorithms. However, the problem of device-level write amplification (DLWA) in Flash caches has not received much attention.</p> </div> <div class="ltx_para" id="S1.p2"> <p class="ltx_p" id="S1.p2.1">The problem of device-level write amplification is important today given the increased focus on data center carbon emissions. As multiple data center operators e.g., Amazon <cite class="ltx_cite ltx_citemacro_citep">(ama, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib3" title="">2024</a>)</cite>, Google <cite class="ltx_cite ltx_citemacro_citep">(goo, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib6" title="">2024</a>)</cite>, Meta <cite class="ltx_cite ltx_citemacro_citep">(met, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib15" title="">2024</a>)</cite>, and Microsoft <cite class="ltx_cite ltx_citemacro_citep">(Nagakawa, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib50" title="">2024</a>)</cite> are aiming to achieve Net Zero greenhouse emissions, they are focusing on cutting down on embodied carbon emissions. Reductions in embodied carbon emission will constitute the bulk of data center emissions post their switch to renewable sources of energy <cite class="ltx_cite ltx_citemacro_citep">(Gupta et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib35" title="">2022a</a>)</cite>. Since Flash is more carbon-efficient than DRAM per bit <cite class="ltx_cite ltx_citemacro_citep">(Gupta et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib35" title="">2022a</a>; Tannu and Nair, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib58" title="">2023</a>)</cite>, it is important to cache more data in Flash than DRAM and increase the lifetime of Flash devices for carbon-efficient deployment of Flash caches at scale.</p> </div> <div class="ltx_para" id="S1.p3"> <p class="ltx_p" id="S1.p3.1">State of the art Flash caches <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite> employ specialized engines for caching small and large objects. A set-associative cache design is used to minimize the tracking overhead of numerous small objects while a log-structured design is used to cache large objects to generate Flash-friendly writes. These two cache designs have distinct write patterns on the SSD. The set-associative cache produces frequent updates in a random fashion while the log-structured cache produces infrequent updates in a sequential fashion on the SSD. To counteract high DLWA, production deployments of these caches underutilize the Flash device leading to a large embodied carbon footprint. Production deployments of CacheLib <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite> which is an open-source Flash cache used as a caching building block to build and deploy 100s of services at Meta only utilizes 50% of the Flash capacity <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite>. <span class="ltx_text ltx_font_italic" id="S1.p3.1.1">Our analysis shows that the cause of high DLWA in these cache designs is the intermixing of data from the two different caching engines. Targeted data placement on Flash to isolate data from the specialized engines holds promise to reduce DLWA and embodied carbon footprint.</span></p> </div> <div class="ltx_para" id="S1.p4"> <p class="ltx_p" id="S1.p4.1">The ratified NVMe Flexible Data Placement technical proposal <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib20" title="">2024b</a>)</cite> is the latest technical proposal on data placement that incorporates lessons learned from previous proposals (e.g., Multi-Stream SSDs <cite class="ltx_cite ltx_citemacro_citep">(Kang, Jeong-Uk and Hyun, Jeeseok and Maeng, Hyunjoo and Cho, Sangyeun, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib41" title="">2014</a>)</cite>, Open-Channel <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib26" title="">2017</a>)</cite>, ZNS <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib25" title="">2021</a>)</cite>) to improve adoption. It provides abstractions for isolating data on NAND media without incurring the software engineering cost of garbage collection or NAND media management. FDP is backward compatible so an application can run unchanged on it. This is particularly important for the adoption of FDP SSDs by production systems that favour stability and are sensitive to maintenance burden of emerging storage interfaces over time.</p> </div> <div class="ltx_para" id="S1.p5"> <p class="ltx_p" id="S1.p5.1">We designed and implemented data isolation modules by harnessing FDP features to reduce data intermixing in Flash media from Flash caches. <span class="ltx_text ltx_font_italic" id="S1.p5.1.1">Our key insight is that the high invalidation rate of set-associative cache design over a small LBA space can be harnessed along with device overprovisioning to ensure the availability of spare blocks for writing new incoming data for it.</span> This is important in maintaining a low predictable DLWA and reduces embodied carbon emissions.</p> </div> <div class="ltx_para" id="S1.p6"> <p class="ltx_p" id="S1.p6.1">Our design utilizing FDP data placement features is non-invasive to the architecture of Flash caches. We observe that the specialized architecture of Flash caches, designed for both small and large objects, can efficiently tag the objects stored within it along the I/O path. This aligns well with the feature set of FDP which allows applications to experiment with data placement only. Our design allows the automatic discovery of FDP features and adaptability to the SSD topology. It also enables the pluggability of various placement decisions to allow extensibility.</p> </div> <div class="ltx_para" id="S1.p7"> <p class="ltx_p" id="S1.p7.1">We designed and implemented our data isolation features for small and large objects in a state-of-the-art open-source caching library CacheLib <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite>. <span class="ltx_text ltx_font_italic" id="S1.p7.1.1">Our changes have been merged in the upstream repository and deployed at scale <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib8" title="">2024a</a>)</cite></span>. To quantify the gains of data isolation in Flash caches, we also devised a theoretical model for DLWA. We present a comprehensive evaluation of our design and implementation using multiple publicly available production workloads from Meta and Twitter, used in past research <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Yang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib60" title="">2020</a>)</cite>, to quantify the benefits and limitations of our approach. Our experiments demonstrate that data separation in flash caches can result in a 2x reduction in SSD device costs and a 4x reduction in embodied carbon footprint. Moreover, our results also highlight opportunities to reduce the DRAM sizes in Flash cache deployments and explore multi-tenant deployments that were not possible earlier due to host overprovisioning. At scale, this translates to massive cost benefits and embodied carbon emission reductions.</p> </div> <div class="ltx_para" id="S1.p8"> <p class="ltx_p" id="S1.p8.1">Concretely, this paper makes the following contributions. We review the concepts of the FDP storage interface, its limitations, and its connection to previous data placement proposals (Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3" title="3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3</span></a>). We analyze the advantages of data segregation by leveraging FDP features in Flash cache architectures equipped with specialized engines for storing objects of varying sizes (Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4" title="4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4</span></a>). Additionally, we present a theoretical model to quantify DLWA. We present the design and implementation details of Flash cache data segregation by incorporating FDP features into CacheLib, a popular state-of-the-art open-source caching library, without altering its architecture or user-facing API (Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5" title="5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">5</span></a>). Our experiments show that separating small, hot data from large, cold data in Flash caches can reach an optimal DLWA of ~1 without requiring any host overprovisioning, even with multiple challenging read- and write-intensive workloads with billions of small object accesses.</p> </div> </section> <section class="ltx_section" id="S2"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">2. </span>Background</h2> <div class="ltx_para" id="S2.p1"> <p class="ltx_p" id="S2.p1.1">In this section, we highlight important concepts to facilitate a better understanding of the rest of the paper. We provide a summary of how SSDs work, the challenges associated with Flash caches, and the architecture of CacheLib <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite>.</p> </div> <section class="ltx_subsection" id="S2.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">2.1. </span>SSDs and Write Amplification</h3> <div class="ltx_para ltx_noindent" id="S2.SS1.p1"> <p class="ltx_p" id="S2.SS1.p1.1"><span class="ltx_text ltx_font_bold" id="S2.SS1.p1.1.1">SSD Basics.</span> A SSD NAND package is organised into dies, planes, blocks, and pages <cite class="ltx_cite ltx_citemacro_citep">(Agrawal et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib22" title="">2008</a>)</cite>. NAND SSDs cannot be directly overwritten due to the erase before write property. The erase operation happens in terms of erase blocks (EBs) (tens to hundreds of MBs) while the writes happen in terms of pages (16KB, 48KB, 64 KB, etc.). The Flash Translation Layer (FTL) in SSDs handles the overwrites by (1) writing (programming) the new data in a free page, (2) invalidating the old data, and (3) updating the metadata to point to the new data. The metadata translates the logical addresses to physical addresses in the NAND media. Writing to logical addresses in an SSD creates invalid pages, that have to be reclaimed by a process called Garbage Collection (GC).</p> </div> <div class="ltx_para ltx_noindent" id="S2.SS1.p2"> <p class="ltx_p" id="S2.SS1.p2.1"><span class="ltx_text ltx_font_bold" id="S2.SS1.p2.1.1">SSD Garbage Collection (GC).</span> The garbage collection process is triggered whenever there is a scarcity of free blocks in the SSD. This process reads the remaining valid pages from an erase block and programs them to a new location. The now fully invalid erase block is available in the free pool. Any erase block in the free pool may be erased and programmed with the next incoming data to be written. Garbage collection is an expensive operation and the energy consumed by the SSD is directly proportional to the number and duration of garbage collection operations.</p> </div> <div class="ltx_para ltx_noindent" id="S2.SS1.p3"> <p class="ltx_p" id="S2.SS1.p3.1"><span class="ltx_text ltx_font_bold" id="S2.SS1.p3.1.1">Device-level Write Amplification (DLWA).</span> DLWA is a metric used to quantify the amount of data that was written internally in the SSD compared to the actual amount of data sent by the host to the SSD. It can be calculated as follows:</p> <table class="ltx_equation ltx_eqn_table" id="S2.E1"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(1)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{DLWA}=\frac{\text{Total NAND Writes}}{\text{Total SSD Writes}}" class="ltx_Math" display="block" id="S2.E1.m1.1"><semantics id="S2.E1.m1.1a"><mrow id="S2.E1.m1.1.1" xref="S2.E1.m1.1.1.cmml"><mtext id="S2.E1.m1.1.1.2" xref="S2.E1.m1.1.1.2a.cmml">DLWA</mtext><mo id="S2.E1.m1.1.1.1" xref="S2.E1.m1.1.1.1.cmml">=</mo><mfrac id="S2.E1.m1.1.1.3" xref="S2.E1.m1.1.1.3.cmml"><mtext id="S2.E1.m1.1.1.3.2" xref="S2.E1.m1.1.1.3.2a.cmml">Total NAND Writes</mtext><mtext id="S2.E1.m1.1.1.3.3" xref="S2.E1.m1.1.1.3.3a.cmml">Total SSD Writes</mtext></mfrac></mrow><annotation-xml encoding="MathML-Content" id="S2.E1.m1.1b"><apply id="S2.E1.m1.1.1.cmml" xref="S2.E1.m1.1.1"><eq id="S2.E1.m1.1.1.1.cmml" xref="S2.E1.m1.1.1.1"></eq><ci id="S2.E1.m1.1.1.2a.cmml" xref="S2.E1.m1.1.1.2"><mtext id="S2.E1.m1.1.1.2.cmml" xref="S2.E1.m1.1.1.2">DLWA</mtext></ci><apply id="S2.E1.m1.1.1.3.cmml" xref="S2.E1.m1.1.1.3"><divide id="S2.E1.m1.1.1.3.1.cmml" xref="S2.E1.m1.1.1.3"></divide><ci id="S2.E1.m1.1.1.3.2a.cmml" xref="S2.E1.m1.1.1.3.2"><mtext id="S2.E1.m1.1.1.3.2.cmml" xref="S2.E1.m1.1.1.3.2">Total NAND Writes</mtext></ci><ci id="S2.E1.m1.1.1.3.3a.cmml" xref="S2.E1.m1.1.1.3.3"><mtext id="S2.E1.m1.1.1.3.3.cmml" xref="S2.E1.m1.1.1.3.3">Total SSD Writes</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S2.E1.m1.1c">\text{DLWA}=\frac{\text{Total NAND Writes}}{\text{Total SSD Writes}}</annotation><annotation encoding="application/x-llamapun" id="S2.E1.m1.1d">DLWA = divide start_ARG Total NAND Writes end_ARG start_ARG Total SSD Writes end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para ltx_noindent" id="S2.SS1.p4"> <p class="ltx_p" id="S2.SS1.p4.1"><span class="ltx_text ltx_font_bold" id="S2.SS1.p4.1.1">Application-level Write Amplification (ALWA).</span> ALWA is a metric used to quantify the amount of data that was sent to the SSD to be written compared to the actual amount of data received to be written by the application. It can be calculated as follows:</p> <table class="ltx_equation ltx_eqn_table" id="S2.E2"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(2)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{ALWA}=\frac{\text{Total SSD Writes}}{\text{Total Application Writes}}" class="ltx_Math" display="block" id="S2.E2.m1.1"><semantics id="S2.E2.m1.1a"><mrow id="S2.E2.m1.1.1" xref="S2.E2.m1.1.1.cmml"><mtext id="S2.E2.m1.1.1.2" xref="S2.E2.m1.1.1.2a.cmml">ALWA</mtext><mo id="S2.E2.m1.1.1.1" xref="S2.E2.m1.1.1.1.cmml">=</mo><mfrac id="S2.E2.m1.1.1.3" xref="S2.E2.m1.1.1.3.cmml"><mtext id="S2.E2.m1.1.1.3.2" xref="S2.E2.m1.1.1.3.2a.cmml">Total SSD Writes</mtext><mtext id="S2.E2.m1.1.1.3.3" xref="S2.E2.m1.1.1.3.3a.cmml">Total Application Writes</mtext></mfrac></mrow><annotation-xml encoding="MathML-Content" id="S2.E2.m1.1b"><apply id="S2.E2.m1.1.1.cmml" xref="S2.E2.m1.1.1"><eq id="S2.E2.m1.1.1.1.cmml" xref="S2.E2.m1.1.1.1"></eq><ci id="S2.E2.m1.1.1.2a.cmml" xref="S2.E2.m1.1.1.2"><mtext id="S2.E2.m1.1.1.2.cmml" xref="S2.E2.m1.1.1.2">ALWA</mtext></ci><apply id="S2.E2.m1.1.1.3.cmml" xref="S2.E2.m1.1.1.3"><divide id="S2.E2.m1.1.1.3.1.cmml" xref="S2.E2.m1.1.1.3"></divide><ci id="S2.E2.m1.1.1.3.2a.cmml" xref="S2.E2.m1.1.1.3.2"><mtext id="S2.E2.m1.1.1.3.2.cmml" xref="S2.E2.m1.1.1.3.2">Total SSD Writes</mtext></ci><ci id="S2.E2.m1.1.1.3.3a.cmml" xref="S2.E2.m1.1.1.3.3"><mtext id="S2.E2.m1.1.1.3.3.cmml" xref="S2.E2.m1.1.1.3.3">Total Application Writes</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S2.E2.m1.1c">\text{ALWA}=\frac{\text{Total SSD Writes}}{\text{Total Application Writes}}</annotation><annotation encoding="application/x-llamapun" id="S2.E2.m1.1d">ALWA = divide start_ARG Total SSD Writes end_ARG start_ARG Total Application Writes end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para ltx_noindent" id="S2.SS1.p5"> <p class="ltx_p" id="S2.SS1.p5.1"><span class="ltx_text ltx_font_bold" id="S2.SS1.p5.1.1">Importance of DLWA.</span> The additional reads and writes from garbage collection interfere with the processing of other commands in the SSD affecting the QoS. Moreover, the additional NAND activity will consume the limited endurance of NAND media. A DLWA of 2 implies that for every 4 KB of data that the user writes, the FTL has written an extra 4 KB due to garbage collection. Since NAND media has a fixed number of Program and Erase cycles (P/E cycles) after which it can either only be read or becomes faulty, a DLWA of 2 causes the device’s lifetime to be halved. Device-level write amplification impacts other SSD performance metrics, such as QoS, bandwidth, lifetime, reliability, and power consumption. It is often used as a simple proxy metric for monitoring SSD performance.</p> </div> </section> <section class="ltx_subsection" id="S2.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">2.2. </span>DLWA and Carbon Emissions</h3> <div class="ltx_para" id="S2.SS2.p1"> <p class="ltx_p" id="S2.SS2.p1.1">The lifetime of an SSD is inversely proportional to the device-level write amplification <cite class="ltx_cite ltx_citemacro_citep">(Li et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib45" title="">2019</a>)</cite>. A DLWA of 2 causes the SSD to fail twice as fast compared to DLWA of 1. A high DLWA results in premature SSD failure and requires frequent replacement of the device. <span class="ltx_text ltx_font_italic" id="S2.SS2.p1.1.1">SSD manufacturing produces millions of metric tonnes of CO2 emissions per year <cite class="ltx_cite ltx_citemacro_citep">(Tannu and Nair, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib58" title="">2023</a>)</cite>. These emissions are broadly categorized as embodied carbon emissions.</span> With systems moving away from HDDs to SSDs, the need to reduce DLWA is crucial because the embodied carbon cost of SSDs is at least an order of magnitude larger than HDDs. Reduction of DLWA amortizes both capital costs and embodied carbon emissions of Flash-based systems at scale.</p> </div> <div class="ltx_para" id="S2.SS2.p2"> <p class="ltx_p" id="S2.SS2.p2.1">High DLWA results from increased garbage collection operations to move valid pages to free up SSD blocks. Consequently, the SSD spends more time in the active state than in the idle state which results in a larger energy consumption <cite class="ltx_cite ltx_citemacro_citep">(Seo et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib54" title="">2008</a>; Cho et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib30" title="">2015</a>; sus, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib19" title="">2024</a>)</cite>. Lower DLWA results in lower consumption of operational energy and translates to higher operational carbon efficiency. Although operational carbon efficiency optimization is important, big carbon efficiency gains are not expected from it. This is because SSDs are designed to be energy efficient and optimized to switch to idle state when not in use.</p> </div> </section> <section class="ltx_subsection" id="S2.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">2.3. </span>Flash Caches and CacheLib</h3> <figure class="ltx_figure" id="S2.F1"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_square" height="673" id="S2.F1.g1" src="x1.png" width="663"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 1. </span>CacheLib Architecture Overview</figcaption> </figure> <div class="ltx_para ltx_noindent" id="S2.SS3.p1"> <p class="ltx_p" id="S2.SS3.p1.1"><span class="ltx_text ltx_font_bold" id="S2.SS3.p1.1.1">Caching in Flash.</span> Caching is widely employed in large-scale web services to provide high performance and reduce operational costs. Flash-based SSDs have become popular for caching large working sets of popular web services <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; Eisenman et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib33" title="">2019</a>; Tang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib57" title="">2015</a>; Wong et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib59" title="">2024</a>)</cite> due to their excellent price performance tradeoff compared to DRAM and HDD. Caching on Flash is write-intensive since evictions upon read from DRAM translate to writes on Flash. Writes to Flash caches increase with the size of the working set, churn in keys, and reduction of DRAM sizes in the deployment. However, the limited write endurance of Flash coupled with unpredictable workloads pose a challenge in the design of these caches.</p> </div> <div class="ltx_para" id="S2.SS3.p2"> <p class="ltx_p" id="S2.SS3.p2.1">Recent research has investigated the design of caching algorithms, admission policies, and application-level write amplification to manage the limited device endurance of Flash while delivering high hit ratios but device-level write amplification (DLWA) has been an understudied problem in this area. <span class="ltx_text ltx_font_italic" id="S2.SS3.p2.1.1">As sustainability challenges mount, Flash-based SSDs will become increasingly attractive compared to DRAM to cache large working set sizes at acceptable performance. However, before claiming Flash-based SSDs to be a panacea for sustainability, DLWA of Flash caches needs to be studied</span>.</p> </div> <div class="ltx_para ltx_noindent" id="S2.SS3.p3"> <p class="ltx_p" id="S2.SS3.p3.1"><span class="ltx_text ltx_font_bold" id="S2.SS3.p3.1.1">CacheLib Architecture.</span> <span class="ltx_text ltx_font_italic" id="S2.SS3.p3.1.2">CacheLib <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite> is an open-source caching library that is widely used and deployed as a fundamental caching building block by 100s of services at Meta</span>. It employs a hybrid cache architecture (see Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2.F1" title="Figure 1 ‣ 2.3. Flash Caches and CacheLib ‣ 2. Background ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">1</span></a>) to leverage both DRAM and Flash-based SSD to cache data hierarchically. DRAM is used to cache the most popular items while the SSD caches data that is less popular and evicted from the DRAM cache. The SSD cache is further decomposed into a small object cache (SOC) and a large object cache (LOC) to store objects of different sizes. The threshold for characterizing objects as small or large is configurable at deployment, along with the sizes of the DRAM and SSD. A single instance of CacheLib can consist of multiple DRAM and SSD cache engines, each with their configured resource budgets.</p> </div> <div class="ltx_para" id="S2.SS3.p4"> <p class="ltx_p" id="S2.SS3.p4.1">The SOC employs a set-associative cache design to perform in-place SSD writes in terms of buckets (typically aligned with 4 KB page size) and utilizes a uniform hashing function to minimize the overhead of tracking numerous small objects. The LOC employs a log-structured design to perform SSD-friendly writes in terms of large regions (16 MB, 256 MB, etc.) that align with erase block sizes. The LOC can be configured to use FIFO or LRU eviction policies. The strengths and weaknesses of the SOC and LOC complement each other. The LOC has SSD-friendly write patterns but has DRAM overheads for tracking objects, while the SOC has SSD-unfriendly write patterns and almost no overhead for tracking objects. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S2.SS3.p5"> <p class="ltx_p" id="S2.SS3.p5.1"><span class="ltx_text ltx_font_bold" id="S2.SS3.p5.1.1">Challenges in Production Flash Caches and CacheLib.</span> The central challenge of Flash caches deployed in the wild is to manage the limited endurance of Flash while ensuring a high hit ratio and low indexing overhead. They have to deal with mixed workloads with objects of varying sizes and access patterns. <span class="ltx_text ltx_font_bold" id="S2.SS3.p5.1.2">Large caching services typically handle billions of frequently accessed small items and millions of infrequently accessed large items <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Yang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib60" title="">2020</a>)</cite></span>. The use of host overprovisioning and threshold admission policy is common for reducing DLWA. <span class="ltx_text ltx_font_bold" id="S2.SS3.p5.1.3">In production CacheLib deployments, 50% of the Flash capacity is overprovisioned to keep DLWA within acceptable levels of ~1.3</span> <cite class="ltx_cite ltx_citemacro_citep">(McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite>. Increasing utilization of Flash with low DLWA is crucial for sustainable deployments of Flash caches at scale in the future.</p> </div> </section> </section> <section class="ltx_section" id="S3"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">3. </span>NVMe Flexible Data Placement (FDP)</h2> <section class="ltx_subsection" id="S3.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">3.1. </span>Overview</h3> <div class="ltx_para" id="S3.SS1.p1"> <p class="ltx_p" id="S3.SS1.p1.1">The ratified NVMe Flexible Data Placement technical proposal <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib20" title="">2024b</a>)</cite> represents an evolution in the space of SSD data placement based on lessons learned in the wild over the past decade. It is a merger of Google’s SmartFTL <cite class="ltx_cite ltx_citemacro_citep">(Sabol and Desai, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib53" title="">[n. d.]</a>)</cite> and Meta’s Direct Placement Mode proposals to enable data placement on Flash media without the high software engineering costs of explicit garbage collection of ZNS <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib25" title="">2021</a>)</cite> and low-level media control of Open-Channel SSD proposals <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib26" title="">2017</a>)</cite>. It borrows elements from the multi-streamed SSD interface <cite class="ltx_cite ltx_citemacro_citep">(Kang, Jeong-Uk and Hyun, Jeeseok and Maeng, Hyunjoo and Cho, Sangyeun, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib41" title="">2014</a>)</cite> that was proposed a decade ago but did not really take off due to a lack of industry and academic interest. It has been designed with backward compatibility in mind so that applications can work unchanged with it. The choice of leveraging data placement and evaluating its costs and benefits has been left to the application. This enables investment of engineering effort in a pay-as-you-go fashion instead of an upfront cost.</p> </div> </section> <section class="ltx_subsection" id="S3.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">3.2. </span>Physical Isolation in SSDs with FDP</h3> <section class="ltx_subsubsection" id="S3.SS2.SSS1"> <h4 class="ltx_title ltx_title_subsubsection"> <span class="ltx_tag ltx_tag_subsubsection">3.2.1. </span>FDP Architectural Concepts</h4> <div class="ltx_para" id="S3.SS2.SSS1.p1"> <p class="ltx_p" id="S3.SS2.SSS1.p1.1">The Flexible Data Placement interface provides abstractions to the host to group data on the device with a similar expected lifetime (e.g., death time). The interface introduces the following concepts to expose the SSD physical architecture (see Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.F2" title="Figure 2 ‣ 3.2.1. FDP Architectural Concepts ‣ 3.2. Physical Isolation in SSDs with FDP ‣ 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">2</span></a>).</p> </div> <figure class="ltx_figure" id="S3.F2"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="607" id="S3.F2.g1" src="x2.png" width="1079"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 2. </span>Conventional SSD vs FDP SSD Architecture.</figcaption> </figure> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS1.p2"> <p class="ltx_p" id="S3.SS2.SSS1.p2.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p2.1.1">Reclaim Unit (RU).</span> The NAND media is organized into a set of reclaim units where a reclaim unit consists of a set of blocks that can be written. A reclaim unit will typically consist of one or more erase blocks but no guarantees are made in the proposal towards this end. The size of an RU is decided by the SSD manufacturer. In this paper, our device has superblock-sized RUs where a superblock is a collection of erase blocks across the planes of dies in the SSD. If an SSD has 8 dies each with 2 planes and 2 erase blocks per plane, the superblock will consist of 32 erase blocks.</p> </div> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS1.p3"> <p class="ltx_p" id="S3.SS2.SSS1.p3.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p3.1.1">Reclaim Group (RG).</span> A reclaim group is a set of reclaim units.</p> </div> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS1.p4"> <p class="ltx_p" id="S3.SS2.SSS1.p4.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p4.1.1">Reclaim Unit Handles (RUH).</span> A reclaim unit handle is an abstraction in the device controller similar to a pointer that allows host software to point to the reclaim units in the device. Since a reclaim unit is not directly addressable by the host, the host software uses the reclaim unit handles to logically isolate data. The device manages the mapping of reclaim unit handles to a reclaim unit and has complete control over this mapping. The number of RUHs in the device determines the number of different logical locations in the NAND where the host software can concurrently place data.</p> </div> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS1.p5"> <p class="ltx_p" id="S3.SS2.SSS1.p5.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p5.1.1">RUH Types.</span> The FDP interface specifies two types of reclaim unit handles, each offering distinct data movement guarantees during garbage collection, along with their respective tradeoffs. During garbage collection, the RUH type is used to determine the source and destination RUs of data to be moved. FDP defines two RUH types namely,</p> <ol class="ltx_enumerate" id="S3.I1"> <li class="ltx_item" id="S3.I1.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(1)</span> <div class="ltx_para" id="S3.I1.i1.p1"> <p class="ltx_p" id="S3.I1.i1.p1.1"><span class="ltx_text ltx_font_bold" id="S3.I1.i1.p1.1.1">Initially Isolated</span> - All the reclaim units within a reclaim group pointed to by the RUHs of this type are candidates for data movement. For multiple RUHs of initially isolated type, data starts off being isolated from data written using another RUH of initially isolated type. However, upon garbage collection valid data written using these two handles can be intermixed. This type is the cheapest to implement on the SSD controller as it does not require explicit tracking of data written using RUHs and imposes the least constraints on data movement during garbage collection.</p> </div> </li> <li class="ltx_item" id="S3.I1.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(2)</span> <div class="ltx_para" id="S3.I1.i2.p1"> <p class="ltx_p" id="S3.I1.i2.p1.1"><span class="ltx_text ltx_font_bold" id="S3.I1.i2.p1.1.1">Persistently Isolated</span> - All the reclaim units within a reclaim group that have been written utilizing the RUH are the only candidates for data movement upon garbage collection. This RUH type provides a stronger guarantee of data isolation but is expensive to implement on the controller as it requires explicit tracking of data written using RUHs and imposes more constraints on data movement during garbage collection.</p> </div> </li> </ol> <p class="ltx_p" id="S3.SS2.SSS1.p5.2"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p5.2.1">Example.</span> Consider a write pattern using two RUHs, RUH0 and RUH1 where RUH0 has written LBAs to RU0 and RU1 while RUH1 has written LBAs to RU2. For simplicity, let us assume that all the RUs belong to the same reclaim group. If RUH0 and RUH1 are of initially isolated type, then upon garbage collection valid data from RU0, RU1 and RU2 are candidates for movement and can be intermixed. If RUH0 and RUH1 are of persistently isolated type, then only data from RU0 and RU1 can be intermixed upon garbage collection while the data in RU2 is isolated from data in RU0 and RU1.</p> </div> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS1.p6"> <p class="ltx_p" id="S3.SS2.SSS1.p6.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS1.p6.1.1">FDP Configurations.</span> An FDP configuration defines the RUHs, RUH type (Initially or Persistently Isolated), their association to RGs, and the RU size. <span class="ltx_text ltx_font_italic" id="S3.SS2.SSS1.p6.1.2">The FDP configurations available on the device are predetermined by the manufacturer</span> and cannot be changed. This paper uses an SSD with a single FDP configuration of 8 Initially Isolated RUHs, 1RG and RU size of 6GB. A device can support multiple configurations that can be chosen by the host.</p> </div> </section> <section class="ltx_subsubsection" id="S3.SS2.SSS2"> <h4 class="ltx_title ltx_title_subsubsection"> <span class="ltx_tag ltx_tag_subsubsection">3.2.2. </span>Data Placement with RUHs</h4> <div class="ltx_para" id="S3.SS2.SSS2.p1"> <p class="ltx_p" id="S3.SS2.SSS2.p1.1">In this section, we highlight important aspects of the FDP interface that influence data placement designs by the host. <br class="ltx_break"/><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS2.p1.1.1">Physically Isolating Logical Blocks with RUHs.</span> The FDP storage interface does not introduce any new command sets to write to the device. Instead, a new data placement directive has been defined that allows each write command to specify a RUH. Thus, the host software can use the RUH to place a logical block in a RU utilizing the RUH. By allowing the host to dynamically associate a logical block with a RU, FDP enables flexible grouping of data based on varying temperature and death time (e.g., hot and cold data separation) or different data streams (e.g., large streams and small journals). This facilitates writing to different RUs in a physically isolated manner. By careful deallocation of all the data in a previously written RU, the host can achieve a DLWA of ~1.</p> </div> <div class="ltx_para" id="S3.SS2.SSS2.p2"> <p class="ltx_p" id="S3.SS2.SSS2.p2.1">During namespace creation, the host software selects a list of RUHs that are accessible by the created namespace. Since FDP is backward compatible, a default RUH is chosen by the device for a namespace if it is not specified. Data is placed in this RUH in the absence of the placement directive from the host. Read operations remain unchanged as before. Writes in FDP can cross RU boundaries. If a write operation overfills an RU because the RU is written to its capacity, the device chooses a new RU and updates the mapping of the RUH to the new RU. Although this process is not visible to the host, the event is logged by the SSD in the device logs that the host can examine.</p> </div> <div class="ltx_para ltx_noindent" id="S3.SS2.SSS2.p3"> <p class="ltx_p" id="S3.SS2.SSS2.p3.1"><span class="ltx_text ltx_font_bold" id="S3.SS2.SSS2.p3.1.1">Managing Invalidations and Tracking RUs.</span> Since FDP does not focus on garbage collection but purely data placement, it does not introduce any new abstractions for erase operations. As in conventional SSDs, LBAs are invalidated or dealloacted in two ways, (1) by overwriting an LBA, (2) by explicitly using a trim operation over one or many LBAs. If all the data in a RU is invalidated, then the RU is erased for future writes and no logical blocks have to copied across RUs upon garbage collection. Since the host software can only access RUHs and not an RU, in order to perform fine-grained and targeted deallocation of RUs, the host software needs to track the LBAs that have been written to an RU together and deallocate those. The FDP specification also allows the host to query the available space in an RU which is currently referenced by the RUH.</p> </div> </section> </section> <section class="ltx_subsection" id="S3.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">3.3. </span>FDP Events and Statistics</h3> <div class="ltx_para" id="S3.SS3.p1"> <p class="ltx_p" id="S3.SS3.p1.1">FDP provides an elaborate set of events and garbage collection statistics for the host to track the FDP related events in the SSD. These help the host to be aware of device-level exceptions and make sure that both host and device are in sync regarding data placement.</p> </div> </section> <section class="ltx_subsection" id="S3.SS4"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">3.4. </span>FDP and Other Major Data Placement Proposals</h3> <div class="ltx_para" id="S3.SS4.p1"> <p class="ltx_p" id="S3.SS4.p1.1">NVMe FDP technical proposal was conceived based on lessons learnt from integrating software stacks with the past data placement proposals. It has been designed to focus on data placement to allow host software stack to perform data segregation while leaving NAND media management and garbage collection to the SSD controller. In Table <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S3.T1" title="Table 1 ‣ 3.4. FDP and Other Major Data Placement Proposals ‣ 3. NVMe Flexible Data Placement (FDP) ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">1</span></a>, we outline some of the key differences between the major data placement proposals of the past years. More details can be found in some of the recent industry presentations on FDP <cite class="ltx_cite ltx_citemacro_citep">(sdc, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib11" title="">2024a</a>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib18" title="">b</a>)</cite>.</p> </div> <figure class="ltx_table" id="S3.T1"> <table class="ltx_tabular ltx_centering ltx_align_middle" id="S3.T1.1"> <tr class="ltx_tr" id="S3.T1.1.1"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.1.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.1.1.1"> <span class="ltx_p" id="S3.T1.1.1.1.1.1" style="width:65.0pt;">Characteristic</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.1.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.1.2.1"> <span class="ltx_p" id="S3.T1.1.1.2.1.1" style="width:78.0pt;"><span class="ltx_text ltx_font_bold" id="S3.T1.1.1.2.1.1.1">Streams <cite class="ltx_cite ltx_citemacro_citep">(Kang, Jeong-Uk and Hyun, Jeeseok and Maeng, Hyunjoo and Cho, Sangyeun, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib41" title="">2014</a>)</cite></span></span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.1.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.1.3.1"> <span class="ltx_p" id="S3.T1.1.1.3.1.1" style="width:78.0pt;"><span class="ltx_text ltx_font_bold" id="S3.T1.1.1.3.1.1.1">Open-Channel <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib26" title="">2017</a>)</cite></span></span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.1.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.1.4.1"> <span class="ltx_p" id="S3.T1.1.1.4.1.1" style="width:65.0pt;"><span class="ltx_text ltx_font_bold" id="S3.T1.1.1.4.1.1.1">ZNS <cite class="ltx_cite ltx_citemacro_citep">(zns, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib2" title="">2024</a>; Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib25" title="">2021</a>)</cite></span></span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.1.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.1.5.1"> <span class="ltx_p" id="S3.T1.1.1.5.1.1" style="width:78.0pt;"><span class="ltx_text ltx_font_bold" id="S3.T1.1.1.5.1.1.1">FDP <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib20" title="">2024b</a>)</cite></span></span> </span> </td> </tr> <tr class="ltx_tr" id="S3.T1.1.2"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.2.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.2.1.1"> <span class="ltx_p" id="S3.T1.1.2.1.1.1" style="width:65.0pt;">Supported write patterns</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.2.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.2.2.1"> <span class="ltx_p" id="S3.T1.1.2.2.1.1" style="width:78.0pt;">Random, Sequential</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.2.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.2.3.1"> <span class="ltx_p" id="S3.T1.1.2.3.1.1" style="width:78.0pt;">Random, Sequential</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.2.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.2.4.1"> <span class="ltx_p" id="S3.T1.1.2.4.1.1" style="width:65.0pt;">Sequential</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.2.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.2.5.1"> <span class="ltx_p" id="S3.T1.1.2.5.1.1" style="width:78.0pt;">Random, Sequential</span> </span> </td> </tr> <tr class="ltx_tr" id="S3.T1.1.3"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.3.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.3.1.1"> <span class="ltx_p" id="S3.T1.1.3.1.1.1" style="width:65.0pt;">Data placement primitive</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.3.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.3.2.1"> <span class="ltx_p" id="S3.T1.1.3.2.1.1" style="width:78.0pt;">Using stream identifiers</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.3.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.3.3.1"> <span class="ltx_p" id="S3.T1.1.3.3.1.1" style="width:78.0pt;">Using logical to physical address mapping by host</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.3.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.3.4.1"> <span class="ltx_p" id="S3.T1.1.3.4.1.1" style="width:65.0pt;">Using zones</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.3.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.3.5.1"> <span class="ltx_p" id="S3.T1.1.3.5.1.1" style="width:78.0pt;">Using reclaim unit handles</span> </span> </td> </tr> <tr class="ltx_tr" id="S3.T1.1.4"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.4.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.4.1.1"> <span class="ltx_p" id="S3.T1.1.4.1.1.1" style="width:65.0pt;">Control of garbage collection</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.4.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.4.2.1"> <span class="ltx_p" id="S3.T1.1.4.2.1.1" style="width:78.0pt;">SSD-based without feedback to host</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.4.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.4.3.1"> <span class="ltx_p" id="S3.T1.1.4.3.1.1" style="width:78.0pt;">Host-based</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.4.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.4.4.1"> <span class="ltx_p" id="S3.T1.1.4.4.1.1" style="width:65.0pt;">Host-based</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.4.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.4.5.1"> <span class="ltx_p" id="S3.T1.1.4.5.1.1" style="width:78.0pt;">SSD-based with feedback through logs</span> </span> </td> </tr> <tr class="ltx_tr" id="S3.T1.1.5"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.5.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.5.1.1"> <span class="ltx_p" id="S3.T1.1.5.1.1.1" style="width:65.0pt;">NAND media management by host</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.5.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.5.2.1"> <span class="ltx_p" id="S3.T1.1.5.2.1.1" style="width:78.0pt;">No</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.5.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.5.3.1"> <span class="ltx_p" id="S3.T1.1.5.3.1.1" style="width:78.0pt;">Yes</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.5.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.5.4.1"> <span class="ltx_p" id="S3.T1.1.5.4.1.1" style="width:65.0pt;">No</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_r ltx_border_t" id="S3.T1.1.5.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.5.5.1"> <span class="ltx_p" id="S3.T1.1.5.5.1.1" style="width:78.0pt;">No</span> </span> </td> </tr> <tr class="ltx_tr" id="S3.T1.1.6"> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_bb ltx_border_l ltx_border_r ltx_border_t" id="S3.T1.1.6.1"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.6.1.1"> <span class="ltx_p" id="S3.T1.1.6.1.1.1" style="width:65.0pt;">Can run applications unchanged</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_bb ltx_border_r ltx_border_t" id="S3.T1.1.6.2"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.6.2.1"> <span class="ltx_p" id="S3.T1.1.6.2.1.1" style="width:78.0pt;">Yes</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_bb ltx_border_r ltx_border_t" id="S3.T1.1.6.3"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.6.3.1"> <span class="ltx_p" id="S3.T1.1.6.3.1.1" style="width:78.0pt;">No</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_bb ltx_border_r ltx_border_t" id="S3.T1.1.6.4"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.6.4.1"> <span class="ltx_p" id="S3.T1.1.6.4.1.1" style="width:65.0pt;">No</span> </span> </td> <td class="ltx_td ltx_align_justify ltx_align_top ltx_border_bb ltx_border_r ltx_border_t" id="S3.T1.1.6.5"> <span class="ltx_inline-block ltx_align_top" id="S3.T1.1.6.5.1"> <span class="ltx_p" id="S3.T1.1.6.5.1.1" style="width:78.0pt;">Yes</span> </span> </td> </tr> </table> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_table">Table 1. </span>High-Level Comparison of Major Data Placement Proposals.</figcaption> </figure> </section> <section class="ltx_subsection" id="S3.SS5"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">3.5. </span>Limitations</h3> <div class="ltx_para" id="S3.SS5.p1"> <ol class="ltx_enumerate" id="S3.I2"> <li class="ltx_item" id="S3.I2.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(1)</span> <div class="ltx_para" id="S3.I2.i1.p1"> <p class="ltx_p" id="S3.I2.i1.p1.1"><span class="ltx_text ltx_font_bold" id="S3.I2.i1.p1.1.1">New and evolving technology.</span> The FDP technical proposal was ratified at the end of 2022, and some devices from Samsung, such as the PM9D3a <cite class="ltx_cite ltx_citemacro_citep">(pm9, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib17" title="">2024</a>)</cite> are emerging on the market with support for it, along with offerings from other vendors. Due to the relatively recent ratification, the proposal may undergo modifications over time to include extensions for desirable features.</p> </div> </li> <li class="ltx_item" id="S3.I2.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(2)</span> <div class="ltx_para" id="S3.I2.i2.p1"> <p class="ltx_p" id="S3.I2.i2.p1.1"><span class="ltx_text ltx_font_bold" id="S3.I2.i2.p1.1.1">Lack of host control over garbage collection.</span> FDP was designed specifically for data placement while allowing hosts to perform random writes to LBAs, enabling the SSD to manage garbage collection. Consequently, the host has no control over the garbage collection process in the SSD, aside from invalidating LBAs by deallocating or overwriting them. Note that this limitation only applies in scenarios where the host can achieve greater performance gains by managing garbage collection more efficiently than the SSD, rather than focusing solely on data placement.</p> </div> </li> <li class="ltx_item" id="S3.I2.i3" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(3)</span> <div class="ltx_para" id="S3.I2.i3.p1"> <p class="ltx_p" id="S3.I2.i3.p1.1"><span class="ltx_text ltx_font_bold" id="S3.I2.i3.p1.1.1">Requires device overprovisioning and mapping table in SSD.</span> As in conventional SSDs today, FDP SSDs will also require a mapping table in DRAM to support transparent mapping of logical to physical addresses. Moreover, NAND overprovisioning in the device is required for acceptable performance in the absence of host-based garbage collection. This is a limitation when the proposal is viewed from the lenses of the cost of fabrication of FDP SSDs.</p> </div> </li> </ol> </div> </section> </section> <section class="ltx_section" id="S4"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">4. </span>Why FDP Matters for CacheLib and Hybrid Caches?</h2> <div class="ltx_para" id="S4.p1"> <p class="ltx_p" id="S4.p1.1">In this section, we discuss the fit of FDP and the opportunities afforded by it for CacheLib and hybrid caches based on the analysis of CacheLib’s Flash Cache architecture, web service caching deployments, and workloads.</p> </div> <section class="ltx_subsection" id="S4.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">4.1. </span>Insights and Observations</h3> <figure class="ltx_figure" id="S4.F3"> <div class="ltx_flex_figure"> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S4.F3.sf1"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="270" id="S4.F3.sf1.g1" src="x3.png" width="747"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">(a) </span>a</figcaption> </figure> </div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_align_center" id="S4.F3.sf2"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="207" id="S4.F3.sf2.g1" src="x4.png" width="747"/> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">(b) </span>b</figcaption> </figure> </div> <div class="ltx_flex_break"></div> </div> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 3. </span>SSD cross-section. <span class="ltx_text" id="S4.F3.6.1" style="font-size:144%;">\small1a⃝</span> shows the intermixing of LOC’s sequential and cold data with SOC’s random and hot data in SSD blocks. <span class="ltx_text" id="S4.F3.7.2" style="font-size:144%;">\small1b⃝</span> shows the inefficient use of device OP by both LOC and SOC data. <span class="ltx_text" id="S4.F3.8.3" style="font-size:144%;">\small2a⃝</span> shows that with SOC data being segregated, invalidation of its data can result in free SSD blocks. <span class="ltx_text" id="S4.F3.9.4" style="font-size:144%;">\small2b⃝</span> shows that with FDP, LOC data which is written sequentially will not cause DLWA. <span class="ltx_text" id="S4.F3.10.5" style="font-size:144%;">\small2c⃝</span> shows the efficient use of device OP exclusively by SOC data to cushion SOC DLWA.</figcaption> </figure> <div class="ltx_para ltx_noindent" id="S4.SS1.p1"> <p class="ltx_p" id="S4.SS1.p1.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p1.1.1">Insight 1: Intermixing of SOC and LOC data leads to high DLWA<span class="ltx_text ltx_font_upright" id="S4.SS1.p1.1.1.1">.</span></span> Large cache items are written into the LOC in a log-structured fashion utilizing a FIFO or LRU eviction policy. This results in a sequential write pattern to the SSD. Small cache items are written into SOC buckets using a uniform hash function. Each item insert causes the entire SOC bucket (size is configurable but default is 4 KB) to be written to the SSD. Contrary to LOC, SOC writes generate a random write pattern to the SSD.</p> </div> <div class="ltx_para" id="S4.SS1.p2"> <p class="ltx_p" id="S4.SS1.p2.1">For workloads with large working set sizes and key churn, the Flash cache layer receives writes due to evictions from the RAM cache <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite>. For workloads dominant in small object accesses, this segregation leads to an infrequent and cold data access pattern in the LOC together with a frequent and hot data access pattern in the SOC. This leads to the intermixing of LOC’s sequential and cold data with SOC’s random and hot data in a single SSD block (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.F3.sf1" title="Figure 3a ‣ Figure 3 ‣ 4.1. Insights and Observations ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3a</span></a> <span class="ltx_text" id="S4.SS1.p2.1.1" style="font-size:144%;">\small1a⃝</span>) causing high DLWA upon garbage collection. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S4.SS1.p3"> <p class="ltx_p" id="S4.SS1.p3.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p3.1.2">Insight 2: The use of host overprovisioning as a control measure for DLWA is inefficient<span class="ltx_text ltx_font_upright" id="S4.SS1.p3.1.2.1">.</span></span> As explained in Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S2.SS3" title="2.3. Flash Caches and CacheLib ‣ 2. Background ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">2.3</span></a>, <span class="ltx_text ltx_font_italic" id="S4.SS1.p3.1.1">CacheLib deployments utilize a host overprovisioning of almost 50% of the SSD to limit DLWA to an acceptable value of <math alttext="\sim" class="ltx_Math" display="inline" id="S4.SS1.p3.1.1.m1.1"><semantics id="S4.SS1.p3.1.1.m1.1a"><mo id="S4.SS1.p3.1.1.m1.1.1" xref="S4.SS1.p3.1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S4.SS1.p3.1.1.m1.1b"><csymbol cd="latexml" id="S4.SS1.p3.1.1.m1.1.1.cmml" xref="S4.SS1.p3.1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S4.SS1.p3.1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S4.SS1.p3.1.1.m1.1d">∼</annotation></semantics></math>1.3</span>. This is inefficient from both cost and carbon efficiency perspectives. The LOC data due to its sequential and cold access pattern does not need any host or device overprovisioning for a DLWA of 1. Without host overprovisioning the only extra space available to help control DLWA is the device overprovisioning space. The random SOC data would benefit the most from the device overprovisioned space because it is small, hot and updated frequently. However, the intermixing of SOC and LOC results in an inefficient use of the device overprovisioning space (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.F3.sf1" title="Figure 3a ‣ Figure 3 ‣ 4.1. Insights and Observations ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3a</span></a> <span class="ltx_text" id="S4.SS1.p3.1.3" style="font-size:144%;">\small1b⃝</span>) as both the SOC and LOC data share it causing unnecessary data movement. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S4.SS1.p4"> <p class="ltx_p" id="S4.SS1.p4.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p4.1.1">Insight 3: High SOC invalidation and its small size can be harnessed to control DLWA<span class="ltx_text ltx_font_upright" id="S4.SS1.p4.1.1.1">.</span></span> A smaller SOC size on devices leads to fewer buckets and a higher rate of key collisions. Since the entire SOC bucket of 4KB is written out, a larger SOC bucket invalidation rate is SSD-friendly because it leads to more SSD page invalidation. If only invalidated SOC data resided in an SSD erase block, this would result in the entire erase block freeing itself up and not needing movement of valid data. For workloads dominant in small object accesses, a high invalidation of SOC happens but the SOC data in erase blocks is intermixed with LOC data. This prevents the SSD from taking advantage of the updates occurring in the SOC buckets over a small LBA space. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S4.SS1.p5"> <p class="ltx_p" id="S4.SS1.p5.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p5.1.1">Insight 4: Data placement using FDP can help CacheLib control DLWA<span class="ltx_text ltx_font_upright" id="S4.SS1.p5.1.1.1">.</span></span> FDP can be utilized by CacheLib to separate the SOC and LOC data in the SSD using different reclaim unit handles. This allows the LOC data and SOC data to reside in mutually exclusive SSD blocks (reclaim units). Such a design will have the following benefits,</p> <ol class="ltx_enumerate" id="S4.I1"> <li class="ltx_item" id="S4.I1.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(1)</span> <div class="ltx_para" id="S4.I1.i1.p1"> <p class="ltx_p" id="S4.I1.i1.p1.1">The SSD blocks containing LOC data get overwritten sequentially resulting in minimal data movement and DLWA (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.F3.sf2" title="Figure 3b ‣ Figure 3 ‣ 4.1. Insights and Observations ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3b</span></a> <span class="ltx_text" id="S4.I1.i1.p1.1.1" style="font-size:144%;">\small2b⃝</span>). If LOC data resides in separate reclaim units than SOC data, the device overprovisioning space can be used exclusively by SOC data.</p> </div> </li> <li class="ltx_item" id="S4.I1.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(2)</span> <div class="ltx_para" id="S4.I1.i2.p1"> <p class="ltx_p" id="S4.I1.i2.p1.1">The ideal behaviour of SOC data invalidating only itself (Insight 3) can be realized by segregating it into separate reclaim units (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.F3.sf2" title="Figure 3b ‣ Figure 3 ‣ 4.1. Insights and Observations ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3b</span></a> <span class="ltx_text" id="S4.I1.i2.p1.1.1" style="font-size:144%;">\small2a⃝</span>). A smaller SOC size leads to a greater invalidation rate causing most of the SOC data in the SSD erase block being invalid. This leads to minimal live data movement and DLWA. As the SOC size increases we expect an increase in DLWA even with LOC and SOC segregation across reclaim units.</p> </div> </li> <li class="ltx_item" id="S4.I1.i3" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(3)</span> <div class="ltx_para" id="S4.I1.i3.p1"> <p class="ltx_p" id="S4.I1.i3.p1.1">The ideal utilization of device overprovisioning space (Insight 2) is possible with FDP (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.F3.sf2" title="Figure 3b ‣ Figure 3 ‣ 4.1. Insights and Observations ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">3b</span></a> <span class="ltx_text" id="S4.I1.i3.p1.1.1" style="font-size:144%;">\small2c⃝</span>). SOC data can use the overprovisioned space to cushion DLWA. When the SOC size is smaller than the device overprovisioning space we expect a DLWA of <math alttext="\sim" class="ltx_Math" display="inline" id="S4.I1.i3.p1.1.m1.1"><semantics id="S4.I1.i3.p1.1.m1.1a"><mo id="S4.I1.i3.p1.1.m1.1.1" xref="S4.I1.i3.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S4.I1.i3.p1.1.m1.1b"><csymbol cd="latexml" id="S4.I1.i3.p1.1.m1.1.1.cmml" xref="S4.I1.i3.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S4.I1.i3.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S4.I1.i3.p1.1.m1.1d">∼</annotation></semantics></math>1 since there is at least one spare block available for each block of SOC data.</p> </div> </li> <li class="ltx_item" id="S4.I1.i4" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(4)</span> <div class="ltx_para" id="S4.I1.i4.p1"> <p class="ltx_p" id="S4.I1.i4.p1.1">The separation of LOC and SOC data in the SSD does not necessitate a change in the CacheLib architecture and API. Therefore, we expect no change in the application-level write amplification (ALWA).</p> </div> </li> </ol> </div> <div class="ltx_para ltx_noindent" id="S4.SS1.p6"> <p class="ltx_p" id="S4.SS1.p6.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p6.1.1">Insight 5: Initially Isolated FDP devices will suffice in controlling the DLWA in CacheLib<span class="ltx_text ltx_font_upright" id="S4.SS1.p6.1.1.1">.</span></span> With the separation of LOC and SOC data within the SSD, the only live data movement will be due to SOC data. Irrespective of whether the SSD is initially isolated or persistently isolated only SOC data would reside in reclaim units used for garbage collection. Therefore, the isolation of LOC and SOC data would be preserved regardless. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S4.SS1.p7"> <p class="ltx_p" id="S4.SS1.p7.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S4.SS1.p7.1.1">Insight 6: Data placement using FDP can help reduce carbon emissions in CacheLib<span class="ltx_text ltx_font_upright" id="S4.SS1.p7.1.1.1">.</span></span> Embodied carbon emissions account for the major chunk of carbon emissions compared to operational carbon emissions. The DLWA gains from using FDP-enabled CacheLib leads to an improved device lifetime. This results in fewer device replacements during the system lifecycle leading to reduction in embodied carbon emissions.</p> </div> <div class="ltx_para" id="S4.SS1.p8"> <p class="ltx_p" id="S4.SS1.p8.1">Fewer garbage collection operations are the reason for the DLWA gains with FDP-enabled CacheLib. For a fixed number of host operations, fewer data migrations result in fewer total device operations. The reduction in total operations requires the device to spend fewer cycles in the active state leading to a lower SSD energy consumption and reduced operational carbon footprint <cite class="ltx_cite ltx_citemacro_citep">(Cho et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib30" title="">2015</a>; Seo et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib54" title="">2008</a>)</cite>.</p> </div> </section> <section class="ltx_subsection" id="S4.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">4.2. </span>Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions</h3> <div class="ltx_para" id="S4.SS2.p1"> <p class="ltx_p" id="S4.SS2.p1.1">We formulate a theoretical model of DLWA and carbon emissions for SOC and LOC data segregation in CacheLib using the insights of the previous section. We assume the DLWA of LOC data is <math alttext="\sim" class="ltx_Math" display="inline" id="S4.SS2.p1.1.m1.1"><semantics id="S4.SS2.p1.1.m1.1a"><mo id="S4.SS2.p1.1.m1.1.1" xref="S4.SS2.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S4.SS2.p1.1.m1.1b"><csymbol cd="latexml" id="S4.SS2.p1.1.m1.1.1.cmml" xref="S4.SS2.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S4.SS2.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S4.SS2.p1.1.m1.1d">∼</annotation></semantics></math>1. Additionally, we use the fact that only SOC data will use the device overprovisioning space and item insertions to the SOC buckets follow a uniform hash function. To simplify our analysis, we assume that the uniform hash function used in CacheLib is fairly well-behaved. Modelling DLWA by estimating live data movement for a uniform random workload has been used proposed before <cite class="ltx_cite ltx_citemacro_citep">(Dayan et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib31" title="">2015</a>)</cite>. We extend that methodology to model the SOC DLWA that translates to the DLWA for FDP-enabled CacheLib as the LOC does not contribute to DLWA. The derivation of the theorems in this section is available in Appendix <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.SS1" title="A.1. System Model: Assumptions and Observations ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">A.1</span></a>.</p> </div> <div class="ltx_theorem ltx_theorem_theorem" id="S4.Thmtheorem1"> <h6 class="ltx_title ltx_runin ltx_font_smallcaps ltx_title_theorem">Theorem 1.</h6> <div class="ltx_para" id="S4.Thmtheorem1.p1"> <p class="ltx_p" id="S4.Thmtheorem1.p1.1"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p1.1.1">The DLWA for FDP-enabled CacheLib using SOC and LOC data segregation is,</span></p> <table class="ltx_equation ltx_eqn_table" id="S4.Ex1"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{DLWA}=\frac{1}{1-\delta}" class="ltx_Math" display="block" id="S4.Ex1.m1.1"><semantics id="S4.Ex1.m1.1a"><mrow id="S4.Ex1.m1.1.1" xref="S4.Ex1.m1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex1.m1.1.1.2" xref="S4.Ex1.m1.1.1.2a.cmml">DLWA</mtext><mo id="S4.Ex1.m1.1.1.1" xref="S4.Ex1.m1.1.1.1.cmml">=</mo><mfrac id="S4.Ex1.m1.1.1.3" xref="S4.Ex1.m1.1.1.3.cmml"><mn id="S4.Ex1.m1.1.1.3.2" xref="S4.Ex1.m1.1.1.3.2.cmml">1</mn><mrow id="S4.Ex1.m1.1.1.3.3" xref="S4.Ex1.m1.1.1.3.3.cmml"><mn id="S4.Ex1.m1.1.1.3.3.2" xref="S4.Ex1.m1.1.1.3.3.2.cmml">1</mn><mo id="S4.Ex1.m1.1.1.3.3.1" xref="S4.Ex1.m1.1.1.3.3.1.cmml">−</mo><mi id="S4.Ex1.m1.1.1.3.3.3" xref="S4.Ex1.m1.1.1.3.3.3.cmml">δ</mi></mrow></mfrac></mrow><annotation-xml encoding="MathML-Content" id="S4.Ex1.m1.1b"><apply id="S4.Ex1.m1.1.1.cmml" xref="S4.Ex1.m1.1.1"><eq id="S4.Ex1.m1.1.1.1.cmml" xref="S4.Ex1.m1.1.1.1"></eq><ci id="S4.Ex1.m1.1.1.2a.cmml" xref="S4.Ex1.m1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex1.m1.1.1.2.cmml" xref="S4.Ex1.m1.1.1.2">DLWA</mtext></ci><apply id="S4.Ex1.m1.1.1.3.cmml" xref="S4.Ex1.m1.1.1.3"><divide id="S4.Ex1.m1.1.1.3.1.cmml" xref="S4.Ex1.m1.1.1.3"></divide><cn id="S4.Ex1.m1.1.1.3.2.cmml" type="integer" xref="S4.Ex1.m1.1.1.3.2">1</cn><apply id="S4.Ex1.m1.1.1.3.3.cmml" xref="S4.Ex1.m1.1.1.3.3"><minus id="S4.Ex1.m1.1.1.3.3.1.cmml" xref="S4.Ex1.m1.1.1.3.3.1"></minus><cn id="S4.Ex1.m1.1.1.3.3.2.cmml" type="integer" xref="S4.Ex1.m1.1.1.3.3.2">1</cn><ci id="S4.Ex1.m1.1.1.3.3.3.cmml" xref="S4.Ex1.m1.1.1.3.3.3">𝛿</ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Ex1.m1.1c">\text{DLWA}=\frac{1}{1-\delta}</annotation><annotation encoding="application/x-llamapun" id="S4.Ex1.m1.1d">DLWA = divide start_ARG 1 end_ARG start_ARG 1 - italic_δ end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para ltx_noindent" id="S4.Thmtheorem1.p2"> <p class="ltx_p" id="S4.Thmtheorem1.p2.1"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.1.1">where </span><math alttext="\delta" class="ltx_Math" display="inline" id="S4.Thmtheorem1.p2.1.m1.1"><semantics id="S4.Thmtheorem1.p2.1.m1.1a"><mi id="S4.Thmtheorem1.p2.1.m1.1.1" xref="S4.Thmtheorem1.p2.1.m1.1.1.cmml">δ</mi><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem1.p2.1.m1.1b"><ci id="S4.Thmtheorem1.p2.1.m1.1.1.cmml" xref="S4.Thmtheorem1.p2.1.m1.1.1">𝛿</ci></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem1.p2.1.m1.1c">\delta</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem1.p2.1.m1.1d">italic_δ</annotation></semantics></math><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.1.2"> denotes the average live SOC bucket migration due to garbage collection and is given by,</span></p> <table class="ltx_equation ltx_eqn_table" id="S4.Ex2"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math 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xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2"></divide><apply id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2"><csymbol cd="ambiguous" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.1.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2">subscript</csymbol><ci id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.2a.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.2.cmml" mathsize="50%" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.2">S</mtext></ci><ci id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.3a.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.3.cmml" mathsize="50%" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.2.3">P-SOC</mtext></ci></apply><apply id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3"><csymbol cd="ambiguous" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.1.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3">subscript</csymbol><ci id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.2a.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.2.cmml" mathsize="50%" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.2">S</mtext></ci><ci id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.3a.cmml" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.3.cmml" mathsize="50%" xref="S4.Ex2.m1.1.1.1.1.1.1.1.2.3.3.2.3.3">SOC</mtext></ci></apply></apply></apply></apply></apply></apply></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Ex2.m1.1c">\delta=-\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{P-SOC}}}\times\mathcal{W}% (-\frac{\text{S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}\times e^{-\frac{\text{% S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}})</annotation><annotation encoding="application/x-llamapun" id="S4.Ex2.m1.1d">italic_δ = - divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG × caligraphic_W ( - divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG × italic_e start_POSTSUPERSCRIPT - divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG end_POSTSUPERSCRIPT )</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> <p class="ltx_p" id="S4.Thmtheorem1.p2.4"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.4.1">where </span><math alttext="\text{S}_{\text{SOC}}" class="ltx_Math" display="inline" id="S4.Thmtheorem1.p2.2.m1.1"><semantics id="S4.Thmtheorem1.p2.2.m1.1a"><msub id="S4.Thmtheorem1.p2.2.m1.1.1" xref="S4.Thmtheorem1.p2.2.m1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.2.m1.1.1.2" xref="S4.Thmtheorem1.p2.2.m1.1.1.2a.cmml">S</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.2.m1.1.1.3" xref="S4.Thmtheorem1.p2.2.m1.1.1.3a.cmml">SOC</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem1.p2.2.m1.1b"><apply id="S4.Thmtheorem1.p2.2.m1.1.1.cmml" xref="S4.Thmtheorem1.p2.2.m1.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem1.p2.2.m1.1.1.1.cmml" xref="S4.Thmtheorem1.p2.2.m1.1.1">subscript</csymbol><ci id="S4.Thmtheorem1.p2.2.m1.1.1.2a.cmml" xref="S4.Thmtheorem1.p2.2.m1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.2.m1.1.1.2.cmml" xref="S4.Thmtheorem1.p2.2.m1.1.1.2">S</mtext></ci><ci id="S4.Thmtheorem1.p2.2.m1.1.1.3a.cmml" xref="S4.Thmtheorem1.p2.2.m1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.2.m1.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem1.p2.2.m1.1.1.3">SOC</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem1.p2.2.m1.1c">\text{S}_{\text{SOC}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem1.p2.2.m1.1d">S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT</annotation></semantics></math><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.4.2"> is the total SOC size in bytes, </span><math alttext="\text{S}_{\text{P-SOC}}" class="ltx_Math" display="inline" id="S4.Thmtheorem1.p2.3.m2.1"><semantics id="S4.Thmtheorem1.p2.3.m2.1a"><msub id="S4.Thmtheorem1.p2.3.m2.1.1" xref="S4.Thmtheorem1.p2.3.m2.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.3.m2.1.1.2" xref="S4.Thmtheorem1.p2.3.m2.1.1.2a.cmml">S</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.3.m2.1.1.3" xref="S4.Thmtheorem1.p2.3.m2.1.1.3a.cmml">P-SOC</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem1.p2.3.m2.1b"><apply id="S4.Thmtheorem1.p2.3.m2.1.1.cmml" xref="S4.Thmtheorem1.p2.3.m2.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem1.p2.3.m2.1.1.1.cmml" xref="S4.Thmtheorem1.p2.3.m2.1.1">subscript</csymbol><ci id="S4.Thmtheorem1.p2.3.m2.1.1.2a.cmml" xref="S4.Thmtheorem1.p2.3.m2.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.3.m2.1.1.2.cmml" xref="S4.Thmtheorem1.p2.3.m2.1.1.2">S</mtext></ci><ci id="S4.Thmtheorem1.p2.3.m2.1.1.3a.cmml" xref="S4.Thmtheorem1.p2.3.m2.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem1.p2.3.m2.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem1.p2.3.m2.1.1.3">P-SOC</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem1.p2.3.m2.1c">\text{S}_{\text{P-SOC}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem1.p2.3.m2.1d">S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT</annotation></semantics></math><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.4.3"> is the total physical space available for SOC data including device overprovisioning in bytes and </span><math alttext="\mathcal{W}" class="ltx_Math" display="inline" id="S4.Thmtheorem1.p2.4.m3.1"><semantics id="S4.Thmtheorem1.p2.4.m3.1a"><mi class="ltx_font_mathcaligraphic" id="S4.Thmtheorem1.p2.4.m3.1.1" xref="S4.Thmtheorem1.p2.4.m3.1.1.cmml">𝒲</mi><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem1.p2.4.m3.1b"><ci id="S4.Thmtheorem1.p2.4.m3.1.1.cmml" xref="S4.Thmtheorem1.p2.4.m3.1.1">𝒲</ci></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem1.p2.4.m3.1c">\mathcal{W}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem1.p2.4.m3.1d">caligraphic_W</annotation></semantics></math><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem1.p2.4.4"> denotes the Lambert W function.</span></p> </div> </div> <section class="ltx_subsubsection" id="S4.SS2.SSS1"> <h4 class="ltx_title ltx_title_subsubsection"> <span class="ltx_tag ltx_tag_subsubsection">4.2.1. </span>Modelling CO2 emissions (CO2e) for FDP-enabled CacheLib</h4> <div class="ltx_para" id="S4.SS2.SSS1.p1"> <p class="ltx_p" id="S4.SS2.SSS1.p1.1">The total carbon footprint is the sum of embodied and operational carbon emissions.</p> <table class="ltx_equation ltx_eqn_table" id="S4.Ex3"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{Total}_{\text{CO2e}}=\text{C}_{\text{embodied}}+\text{C}_{\text{% operational}}" class="ltx_Math" display="block" id="S4.Ex3.m1.1"><semantics id="S4.Ex3.m1.1a"><mrow id="S4.Ex3.m1.1.1" xref="S4.Ex3.m1.1.1.cmml"><msub id="S4.Ex3.m1.1.1.2" xref="S4.Ex3.m1.1.1.2.cmml"><mtext id="S4.Ex3.m1.1.1.2.2" xref="S4.Ex3.m1.1.1.2.2a.cmml">Total</mtext><mtext id="S4.Ex3.m1.1.1.2.3" xref="S4.Ex3.m1.1.1.2.3a.cmml">CO2e</mtext></msub><mo id="S4.Ex3.m1.1.1.1" xref="S4.Ex3.m1.1.1.1.cmml">=</mo><mrow id="S4.Ex3.m1.1.1.3" xref="S4.Ex3.m1.1.1.3.cmml"><msub id="S4.Ex3.m1.1.1.3.2" xref="S4.Ex3.m1.1.1.3.2.cmml"><mtext id="S4.Ex3.m1.1.1.3.2.2" xref="S4.Ex3.m1.1.1.3.2.2a.cmml">C</mtext><mtext id="S4.Ex3.m1.1.1.3.2.3" xref="S4.Ex3.m1.1.1.3.2.3a.cmml">embodied</mtext></msub><mo id="S4.Ex3.m1.1.1.3.1" xref="S4.Ex3.m1.1.1.3.1.cmml">+</mo><msub id="S4.Ex3.m1.1.1.3.3" xref="S4.Ex3.m1.1.1.3.3.cmml"><mtext id="S4.Ex3.m1.1.1.3.3.2" xref="S4.Ex3.m1.1.1.3.3.2a.cmml">C</mtext><mtext id="S4.Ex3.m1.1.1.3.3.3" xref="S4.Ex3.m1.1.1.3.3.3a.cmml">operational</mtext></msub></mrow></mrow><annotation-xml encoding="MathML-Content" id="S4.Ex3.m1.1b"><apply id="S4.Ex3.m1.1.1.cmml" xref="S4.Ex3.m1.1.1"><eq id="S4.Ex3.m1.1.1.1.cmml" xref="S4.Ex3.m1.1.1.1"></eq><apply id="S4.Ex3.m1.1.1.2.cmml" xref="S4.Ex3.m1.1.1.2"><csymbol cd="ambiguous" id="S4.Ex3.m1.1.1.2.1.cmml" xref="S4.Ex3.m1.1.1.2">subscript</csymbol><ci id="S4.Ex3.m1.1.1.2.2a.cmml" xref="S4.Ex3.m1.1.1.2.2"><mtext id="S4.Ex3.m1.1.1.2.2.cmml" xref="S4.Ex3.m1.1.1.2.2">Total</mtext></ci><ci id="S4.Ex3.m1.1.1.2.3a.cmml" xref="S4.Ex3.m1.1.1.2.3"><mtext id="S4.Ex3.m1.1.1.2.3.cmml" mathsize="70%" xref="S4.Ex3.m1.1.1.2.3">CO2e</mtext></ci></apply><apply id="S4.Ex3.m1.1.1.3.cmml" xref="S4.Ex3.m1.1.1.3"><plus id="S4.Ex3.m1.1.1.3.1.cmml" xref="S4.Ex3.m1.1.1.3.1"></plus><apply id="S4.Ex3.m1.1.1.3.2.cmml" xref="S4.Ex3.m1.1.1.3.2"><csymbol cd="ambiguous" id="S4.Ex3.m1.1.1.3.2.1.cmml" xref="S4.Ex3.m1.1.1.3.2">subscript</csymbol><ci id="S4.Ex3.m1.1.1.3.2.2a.cmml" xref="S4.Ex3.m1.1.1.3.2.2"><mtext id="S4.Ex3.m1.1.1.3.2.2.cmml" xref="S4.Ex3.m1.1.1.3.2.2">C</mtext></ci><ci id="S4.Ex3.m1.1.1.3.2.3a.cmml" xref="S4.Ex3.m1.1.1.3.2.3"><mtext id="S4.Ex3.m1.1.1.3.2.3.cmml" mathsize="70%" xref="S4.Ex3.m1.1.1.3.2.3">embodied</mtext></ci></apply><apply id="S4.Ex3.m1.1.1.3.3.cmml" xref="S4.Ex3.m1.1.1.3.3"><csymbol cd="ambiguous" id="S4.Ex3.m1.1.1.3.3.1.cmml" xref="S4.Ex3.m1.1.1.3.3">subscript</csymbol><ci id="S4.Ex3.m1.1.1.3.3.2a.cmml" xref="S4.Ex3.m1.1.1.3.3.2"><mtext id="S4.Ex3.m1.1.1.3.3.2.cmml" xref="S4.Ex3.m1.1.1.3.3.2">C</mtext></ci><ci id="S4.Ex3.m1.1.1.3.3.3a.cmml" xref="S4.Ex3.m1.1.1.3.3.3"><mtext id="S4.Ex3.m1.1.1.3.3.3.cmml" mathsize="70%" xref="S4.Ex3.m1.1.1.3.3.3">operational</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Ex3.m1.1c">\text{Total}_{\text{CO2e}}=\text{C}_{\text{embodied}}+\text{C}_{\text{% operational}}</annotation><annotation encoding="application/x-llamapun" id="S4.Ex3.m1.1d">Total start_POSTSUBSCRIPT CO2e end_POSTSUBSCRIPT = C start_POSTSUBSCRIPT embodied end_POSTSUBSCRIPT + C start_POSTSUBSCRIPT operational end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_theorem ltx_theorem_theorem" id="S4.Thmtheorem2"> <h6 class="ltx_title ltx_runin ltx_font_smallcaps ltx_title_theorem">Theorem 2.</h6> <div class="ltx_para" id="S4.Thmtheorem2.p1"> <p class="ltx_p" id="S4.Thmtheorem2.p1.1"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem2.p1.1.1">The embodied carbon emissions from using CacheLib by accounting for SSD replacement during the system lifecycle of T years and rated SSD warranty of <math alttext="\text{L}_{\text{dev}}" class="ltx_Math" display="inline" id="S4.Thmtheorem2.p1.1.1.m1.1"><semantics id="S4.Thmtheorem2.p1.1.1.m1.1a"><msub id="S4.Thmtheorem2.p1.1.1.m1.1.1" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p1.1.1.m1.1.1.2" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.2a.cmml">L</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p1.1.1.m1.1.1.3" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.3a.cmml">dev</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem2.p1.1.1.m1.1b"><apply id="S4.Thmtheorem2.p1.1.1.m1.1.1.cmml" xref="S4.Thmtheorem2.p1.1.1.m1.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p1.1.1.m1.1.1.1.cmml" xref="S4.Thmtheorem2.p1.1.1.m1.1.1">subscript</csymbol><ci id="S4.Thmtheorem2.p1.1.1.m1.1.1.2a.cmml" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p1.1.1.m1.1.1.2.cmml" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.2">L</mtext></ci><ci id="S4.Thmtheorem2.p1.1.1.m1.1.1.3a.cmml" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p1.1.1.m1.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p1.1.1.m1.1.1.3">dev</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem2.p1.1.1.m1.1c">\text{L}_{\text{dev}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem2.p1.1.1.m1.1d">L start_POSTSUBSCRIPT dev end_POSTSUBSCRIPT</annotation></semantics></math> years is,</span></p> </div> <div class="ltx_para" id="S4.Thmtheorem2.p2"> <table class="ltx_equation ltx_eqn_table" id="S4.Ex4"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{C}_{\text{embodied}}=\text{DLWA}\times\text{Device}_{\text{cap}}\times% \frac{T}{\text{L}_{\text{dev}}}\times\text{C}_{\text{SSD}}" class="ltx_Math" display="block" id="S4.Ex4.m1.1"><semantics id="S4.Ex4.m1.1a"><mrow id="S4.Ex4.m1.1.1" xref="S4.Ex4.m1.1.1.cmml"><msub id="S4.Ex4.m1.1.1.2" xref="S4.Ex4.m1.1.1.2.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.2.2" xref="S4.Ex4.m1.1.1.2.2a.cmml">C</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.2.3" xref="S4.Ex4.m1.1.1.2.3a.cmml">embodied</mtext></msub><mo id="S4.Ex4.m1.1.1.1" xref="S4.Ex4.m1.1.1.1.cmml">=</mo><mrow id="S4.Ex4.m1.1.1.3" xref="S4.Ex4.m1.1.1.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.2" xref="S4.Ex4.m1.1.1.3.2a.cmml">DLWA</mtext><mo id="S4.Ex4.m1.1.1.3.1" lspace="0.222em" rspace="0.222em" xref="S4.Ex4.m1.1.1.3.1.cmml">×</mo><msub id="S4.Ex4.m1.1.1.3.3" xref="S4.Ex4.m1.1.1.3.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.3.2" xref="S4.Ex4.m1.1.1.3.3.2a.cmml">Device</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.3.3" xref="S4.Ex4.m1.1.1.3.3.3a.cmml">cap</mtext></msub><mo id="S4.Ex4.m1.1.1.3.1a" lspace="0.222em" rspace="0.222em" xref="S4.Ex4.m1.1.1.3.1.cmml">×</mo><mfrac id="S4.Ex4.m1.1.1.3.4" xref="S4.Ex4.m1.1.1.3.4.cmml"><mi id="S4.Ex4.m1.1.1.3.4.2" xref="S4.Ex4.m1.1.1.3.4.2.cmml">T</mi><msub id="S4.Ex4.m1.1.1.3.4.3" xref="S4.Ex4.m1.1.1.3.4.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.4.3.2" xref="S4.Ex4.m1.1.1.3.4.3.2a.cmml">L</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.4.3.3" xref="S4.Ex4.m1.1.1.3.4.3.3a.cmml">dev</mtext></msub></mfrac><mo id="S4.Ex4.m1.1.1.3.1b" lspace="0.222em" rspace="0.222em" xref="S4.Ex4.m1.1.1.3.1.cmml">×</mo><msub id="S4.Ex4.m1.1.1.3.5" xref="S4.Ex4.m1.1.1.3.5.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.5.2" xref="S4.Ex4.m1.1.1.3.5.2a.cmml">C</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.5.3" xref="S4.Ex4.m1.1.1.3.5.3a.cmml">SSD</mtext></msub></mrow></mrow><annotation-xml encoding="MathML-Content" id="S4.Ex4.m1.1b"><apply id="S4.Ex4.m1.1.1.cmml" xref="S4.Ex4.m1.1.1"><eq id="S4.Ex4.m1.1.1.1.cmml" xref="S4.Ex4.m1.1.1.1"></eq><apply id="S4.Ex4.m1.1.1.2.cmml" xref="S4.Ex4.m1.1.1.2"><csymbol cd="ambiguous" id="S4.Ex4.m1.1.1.2.1.cmml" xref="S4.Ex4.m1.1.1.2">subscript</csymbol><ci id="S4.Ex4.m1.1.1.2.2a.cmml" xref="S4.Ex4.m1.1.1.2.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.2.2.cmml" xref="S4.Ex4.m1.1.1.2.2">C</mtext></ci><ci id="S4.Ex4.m1.1.1.2.3a.cmml" xref="S4.Ex4.m1.1.1.2.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.2.3.cmml" mathsize="70%" xref="S4.Ex4.m1.1.1.2.3">embodied</mtext></ci></apply><apply id="S4.Ex4.m1.1.1.3.cmml" xref="S4.Ex4.m1.1.1.3"><times id="S4.Ex4.m1.1.1.3.1.cmml" xref="S4.Ex4.m1.1.1.3.1"></times><ci id="S4.Ex4.m1.1.1.3.2a.cmml" xref="S4.Ex4.m1.1.1.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.2.cmml" xref="S4.Ex4.m1.1.1.3.2">DLWA</mtext></ci><apply id="S4.Ex4.m1.1.1.3.3.cmml" xref="S4.Ex4.m1.1.1.3.3"><csymbol cd="ambiguous" id="S4.Ex4.m1.1.1.3.3.1.cmml" xref="S4.Ex4.m1.1.1.3.3">subscript</csymbol><ci id="S4.Ex4.m1.1.1.3.3.2a.cmml" xref="S4.Ex4.m1.1.1.3.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.3.2.cmml" xref="S4.Ex4.m1.1.1.3.3.2">Device</mtext></ci><ci id="S4.Ex4.m1.1.1.3.3.3a.cmml" xref="S4.Ex4.m1.1.1.3.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.3.3.cmml" mathsize="70%" xref="S4.Ex4.m1.1.1.3.3.3">cap</mtext></ci></apply><apply id="S4.Ex4.m1.1.1.3.4.cmml" xref="S4.Ex4.m1.1.1.3.4"><divide id="S4.Ex4.m1.1.1.3.4.1.cmml" xref="S4.Ex4.m1.1.1.3.4"></divide><ci id="S4.Ex4.m1.1.1.3.4.2.cmml" xref="S4.Ex4.m1.1.1.3.4.2">𝑇</ci><apply id="S4.Ex4.m1.1.1.3.4.3.cmml" xref="S4.Ex4.m1.1.1.3.4.3"><csymbol cd="ambiguous" id="S4.Ex4.m1.1.1.3.4.3.1.cmml" xref="S4.Ex4.m1.1.1.3.4.3">subscript</csymbol><ci id="S4.Ex4.m1.1.1.3.4.3.2a.cmml" xref="S4.Ex4.m1.1.1.3.4.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.4.3.2.cmml" xref="S4.Ex4.m1.1.1.3.4.3.2">L</mtext></ci><ci id="S4.Ex4.m1.1.1.3.4.3.3a.cmml" xref="S4.Ex4.m1.1.1.3.4.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.4.3.3.cmml" mathsize="70%" xref="S4.Ex4.m1.1.1.3.4.3.3">dev</mtext></ci></apply></apply><apply id="S4.Ex4.m1.1.1.3.5.cmml" xref="S4.Ex4.m1.1.1.3.5"><csymbol cd="ambiguous" id="S4.Ex4.m1.1.1.3.5.1.cmml" xref="S4.Ex4.m1.1.1.3.5">subscript</csymbol><ci id="S4.Ex4.m1.1.1.3.5.2a.cmml" xref="S4.Ex4.m1.1.1.3.5.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.5.2.cmml" xref="S4.Ex4.m1.1.1.3.5.2">C</mtext></ci><ci id="S4.Ex4.m1.1.1.3.5.3a.cmml" xref="S4.Ex4.m1.1.1.3.5.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex4.m1.1.1.3.5.3.cmml" mathsize="70%" xref="S4.Ex4.m1.1.1.3.5.3">SSD</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Ex4.m1.1c">\text{C}_{\text{embodied}}=\text{DLWA}\times\text{Device}_{\text{cap}}\times% \frac{T}{\text{L}_{\text{dev}}}\times\text{C}_{\text{SSD}}</annotation><annotation encoding="application/x-llamapun" id="S4.Ex4.m1.1d">C start_POSTSUBSCRIPT embodied end_POSTSUBSCRIPT = DLWA × Device start_POSTSUBSCRIPT cap end_POSTSUBSCRIPT × divide start_ARG italic_T end_ARG start_ARG L start_POSTSUBSCRIPT dev end_POSTSUBSCRIPT end_ARG × C start_POSTSUBSCRIPT SSD end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> <p class="ltx_p" id="S4.Thmtheorem2.p2.4"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem2.p2.4.4">where <math alttext="\text{Device}_{\text{cap}}" class="ltx_Math" display="inline" id="S4.Thmtheorem2.p2.1.1.m1.1"><semantics id="S4.Thmtheorem2.p2.1.1.m1.1a"><msub id="S4.Thmtheorem2.p2.1.1.m1.1.1" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.1.1.m1.1.1.2" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.2a.cmml">Device</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.1.1.m1.1.1.3" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.3a.cmml">cap</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem2.p2.1.1.m1.1b"><apply id="S4.Thmtheorem2.p2.1.1.m1.1.1.cmml" xref="S4.Thmtheorem2.p2.1.1.m1.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.1.1.m1.1.1.1.cmml" xref="S4.Thmtheorem2.p2.1.1.m1.1.1">subscript</csymbol><ci id="S4.Thmtheorem2.p2.1.1.m1.1.1.2a.cmml" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.1.1.m1.1.1.2.cmml" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.2">Device</mtext></ci><ci id="S4.Thmtheorem2.p2.1.1.m1.1.1.3a.cmml" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.1.1.m1.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.1.1.m1.1.1.3">cap</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem2.p2.1.1.m1.1c">\text{Device}_{\text{cap}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem2.p2.1.1.m1.1d">Device start_POSTSUBSCRIPT cap end_POSTSUBSCRIPT</annotation></semantics></math> is the physical capacity of the device. <br class="ltx_break"/><math alttext="\text{Host}_{\text{cap}}=\text{Device}_{\text{cap}}\times(1-\text{Total}_{% \text{op}})" class="ltx_Math" display="inline" id="S4.Thmtheorem2.p2.2.2.m2.1"><semantics id="S4.Thmtheorem2.p2.2.2.m2.1a"><mrow id="S4.Thmtheorem2.p2.2.2.m2.1.1" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.cmml"><msub id="S4.Thmtheorem2.p2.2.2.m2.1.1.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2a.cmml">Host</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3a.cmml">cap</mtext></msub><mo id="S4.Thmtheorem2.p2.2.2.m2.1.1.2" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.2.cmml">=</mo><mrow id="S4.Thmtheorem2.p2.2.2.m2.1.1.1" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.cmml"><msub id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.2" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.2a.cmml">Device</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.3a.cmml">cap</mtext></msub><mo id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.2" lspace="0.222em" rspace="0.222em" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.2.cmml">×</mo><mrow id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.cmml"><mo id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.2" stretchy="false" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.cmml">(</mo><mrow id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.cmml"><mn id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.2" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.2.cmml">1</mn><mo id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.1" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.1.cmml">−</mo><msub id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2a.cmml">Total</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3a.cmml">op</mtext></msub></mrow><mo id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.3" stretchy="false" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.cmml">)</mo></mrow></mrow></mrow><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem2.p2.2.2.m2.1b"><apply id="S4.Thmtheorem2.p2.2.2.m2.1.1.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1"><eq id="S4.Thmtheorem2.p2.2.2.m2.1.1.2.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.2"></eq><apply id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.1.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3">subscript</csymbol><ci id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2a.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.2">Host</mtext></ci><ci id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3a.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.3.3">cap</mtext></ci></apply><apply id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1"><times id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.2.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.2"></times><apply id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.3.cmml" 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id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.1.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3">subscript</csymbol><ci id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2a.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.2">Total</mtext></ci><ci id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3a.cmml" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.2.2.m2.1.1.1.1.1.1.3.3">op</mtext></ci></apply></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem2.p2.2.2.m2.1c">\text{Host}_{\text{cap}}=\text{Device}_{\text{cap}}\times(1-\text{Total}_{% \text{op}})</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem2.p2.2.2.m2.1d">Host start_POSTSUBSCRIPT cap end_POSTSUBSCRIPT = Device start_POSTSUBSCRIPT cap end_POSTSUBSCRIPT × ( 1 - Total start_POSTSUBSCRIPT op end_POSTSUBSCRIPT )</annotation></semantics></math> denotes the SSD capacity used by the host system in GB, <math alttext="\text{H}_{\text{op}}\text{ and }\text{D}_{\text{op}}\in[0,1)" class="ltx_Math" display="inline" id="S4.Thmtheorem2.p2.3.3.m3.2"><semantics id="S4.Thmtheorem2.p2.3.3.m3.2a"><mrow id="S4.Thmtheorem2.p2.3.3.m3.2.3" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.cmml"><mrow id="S4.Thmtheorem2.p2.3.3.m3.2.3.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.cmml"><msub id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2a.cmml">H</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3a.cmml">op</mtext></msub><mo id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.1" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.1.cmml">⁢</mo><msub id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.cmml"><mrow id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2c.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2a" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2c.cmml"> and </mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2b" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2c.cmml">D</mtext></mrow><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3a.cmml">op</mtext></msub></mrow><mo id="S4.Thmtheorem2.p2.3.3.m3.2.3.1" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.1.cmml">∈</mo><mrow id="S4.Thmtheorem2.p2.3.3.m3.2.3.3.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.3.1.cmml"><mo id="S4.Thmtheorem2.p2.3.3.m3.2.3.3.2.1" stretchy="false" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.3.1.cmml">[</mo><mn id="S4.Thmtheorem2.p2.3.3.m3.1.1" xref="S4.Thmtheorem2.p2.3.3.m3.1.1.cmml">0</mn><mo id="S4.Thmtheorem2.p2.3.3.m3.2.3.3.2.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.3.1.cmml">,</mo><mn id="S4.Thmtheorem2.p2.3.3.m3.2.2" xref="S4.Thmtheorem2.p2.3.3.m3.2.2.cmml">1</mn><mo id="S4.Thmtheorem2.p2.3.3.m3.2.3.3.2.3" stretchy="false" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.3.1.cmml">)</mo></mrow></mrow><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem2.p2.3.3.m3.2b"><apply id="S4.Thmtheorem2.p2.3.3.m3.2.3.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3"><in id="S4.Thmtheorem2.p2.3.3.m3.2.3.1.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.1"></in><apply id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2"><times id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.1.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.1"></times><apply id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.1.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2">subscript</csymbol><ci id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2a.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.2">H</mtext></ci><ci id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3a.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.2.3">op</mtext></ci></apply><apply id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.1.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3">subscript</csymbol><ci id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2c.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2"><mrow id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2a.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2"> and </mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2b.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.2">D</mtext></mrow></ci><ci id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3a.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.2.3.3">op</mtext></ci></apply></apply><interval closure="closed-open" id="S4.Thmtheorem2.p2.3.3.m3.2.3.3.1.cmml" xref="S4.Thmtheorem2.p2.3.3.m3.2.3.3.2"><cn id="S4.Thmtheorem2.p2.3.3.m3.1.1.cmml" type="integer" xref="S4.Thmtheorem2.p2.3.3.m3.1.1">0</cn><cn id="S4.Thmtheorem2.p2.3.3.m3.2.2.cmml" type="integer" xref="S4.Thmtheorem2.p2.3.3.m3.2.2">1</cn></interval></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem2.p2.3.3.m3.2c">\text{H}_{\text{op}}\text{ and }\text{D}_{\text{op}}\in[0,1)</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem2.p2.3.3.m3.2d">H start_POSTSUBSCRIPT op end_POSTSUBSCRIPT italic_and italic_D start_POSTSUBSCRIPT op end_POSTSUBSCRIPT ∈ [ 0 , 1 )</annotation></semantics></math> is the fraction of host overprovisioning and device overprovisioning and <math alttext="\text{C}_{\text{SSD}}" class="ltx_Math" display="inline" id="S4.Thmtheorem2.p2.4.4.m4.1"><semantics id="S4.Thmtheorem2.p2.4.4.m4.1a"><msub id="S4.Thmtheorem2.p2.4.4.m4.1.1" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.4.4.m4.1.1.2" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.2a.cmml">C</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.4.4.m4.1.1.3" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.3a.cmml">SSD</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem2.p2.4.4.m4.1b"><apply id="S4.Thmtheorem2.p2.4.4.m4.1.1.cmml" xref="S4.Thmtheorem2.p2.4.4.m4.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem2.p2.4.4.m4.1.1.1.cmml" xref="S4.Thmtheorem2.p2.4.4.m4.1.1">subscript</csymbol><ci id="S4.Thmtheorem2.p2.4.4.m4.1.1.2a.cmml" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.4.4.m4.1.1.2.cmml" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.2">C</mtext></ci><ci id="S4.Thmtheorem2.p2.4.4.m4.1.1.3a.cmml" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem2.p2.4.4.m4.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem2.p2.4.4.m4.1.1.3">SSD</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem2.p2.4.4.m4.1c">\text{C}_{\text{SSD}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem2.p2.4.4.m4.1d">C start_POSTSUBSCRIPT SSD end_POSTSUBSCRIPT</annotation></semantics></math> is the amount of CO2e (Kg) per GB of SSD manufactured.</span></p> </div> </div> <div class="ltx_para" id="S4.SS2.SSS1.p2"> <p class="ltx_p" id="S4.SS2.SSS1.p2.1">Operational Energy can be converted to CO2 emission (CO2e) using the greenhouse equivalence calculator <cite class="ltx_cite ltx_citemacro_citep">(gre, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib10" title="">2024</a>)</cite>. The operational energy consumed can be modelled by estimating the time spent in idle and active states <cite class="ltx_cite ltx_citemacro_citep">(Cho et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib30" title="">2015</a>)</cite>. The time spent in active states is proportional to the total number of device operations during the period in question,</p> </div> <div class="ltx_theorem ltx_theorem_theorem" id="S4.Thmtheorem3"> <h6 class="ltx_title ltx_runin ltx_font_smallcaps ltx_title_theorem">Theorem 3.</h6> <div class="ltx_para" id="S4.Thmtheorem3.p1"> <p class="ltx_p" id="S4.Thmtheorem3.p1.2"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem3.p1.2.1">Operational energy is proportional to the total number of garbage collection events.</span></p> <table class="ltx_equation ltx_eqn_table" id="S4.Ex5"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\mathcal{E}_{\text{operational}}\propto\mathcal{E}(\text{Host}_{\text{% operations}})+\mathcal{E}(\text{Device}_{\text{migrations}})" class="ltx_Math" display="block" id="S4.Ex5.m1.2"><semantics id="S4.Ex5.m1.2a"><mrow id="S4.Ex5.m1.2.2" xref="S4.Ex5.m1.2.2.cmml"><msub id="S4.Ex5.m1.2.2.4" xref="S4.Ex5.m1.2.2.4.cmml"><mi class="ltx_font_mathcaligraphic" id="S4.Ex5.m1.2.2.4.2" xref="S4.Ex5.m1.2.2.4.2.cmml">ℰ</mi><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.4.3" xref="S4.Ex5.m1.2.2.4.3a.cmml">operational</mtext></msub><mo id="S4.Ex5.m1.2.2.3" xref="S4.Ex5.m1.2.2.3.cmml">∝</mo><mrow id="S4.Ex5.m1.2.2.2" xref="S4.Ex5.m1.2.2.2.cmml"><mrow id="S4.Ex5.m1.1.1.1.1" xref="S4.Ex5.m1.1.1.1.1.cmml"><mi class="ltx_font_mathcaligraphic" id="S4.Ex5.m1.1.1.1.1.3" xref="S4.Ex5.m1.1.1.1.1.3.cmml">ℰ</mi><mo id="S4.Ex5.m1.1.1.1.1.2" xref="S4.Ex5.m1.1.1.1.1.2.cmml">⁢</mo><mrow id="S4.Ex5.m1.1.1.1.1.1.1" xref="S4.Ex5.m1.1.1.1.1.1.1.1.cmml"><mo id="S4.Ex5.m1.1.1.1.1.1.1.2" stretchy="false" xref="S4.Ex5.m1.1.1.1.1.1.1.1.cmml">(</mo><msub id="S4.Ex5.m1.1.1.1.1.1.1.1" xref="S4.Ex5.m1.1.1.1.1.1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.1.1.1.1.1.1.1.2" xref="S4.Ex5.m1.1.1.1.1.1.1.1.2a.cmml">Host</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.1.1.1.1.1.1.1.3" xref="S4.Ex5.m1.1.1.1.1.1.1.1.3a.cmml">operations</mtext></msub><mo id="S4.Ex5.m1.1.1.1.1.1.1.3" stretchy="false" xref="S4.Ex5.m1.1.1.1.1.1.1.1.cmml">)</mo></mrow></mrow><mo id="S4.Ex5.m1.2.2.2.3" xref="S4.Ex5.m1.2.2.2.3.cmml">+</mo><mrow id="S4.Ex5.m1.2.2.2.2" xref="S4.Ex5.m1.2.2.2.2.cmml"><mi class="ltx_font_mathcaligraphic" id="S4.Ex5.m1.2.2.2.2.3" xref="S4.Ex5.m1.2.2.2.2.3.cmml">ℰ</mi><mo id="S4.Ex5.m1.2.2.2.2.2" xref="S4.Ex5.m1.2.2.2.2.2.cmml">⁢</mo><mrow id="S4.Ex5.m1.2.2.2.2.1.1" xref="S4.Ex5.m1.2.2.2.2.1.1.1.cmml"><mo id="S4.Ex5.m1.2.2.2.2.1.1.2" stretchy="false" xref="S4.Ex5.m1.2.2.2.2.1.1.1.cmml">(</mo><msub id="S4.Ex5.m1.2.2.2.2.1.1.1" xref="S4.Ex5.m1.2.2.2.2.1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.2.2.1.1.1.2" xref="S4.Ex5.m1.2.2.2.2.1.1.1.2a.cmml">Device</mtext><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.2.2.1.1.1.3" xref="S4.Ex5.m1.2.2.2.2.1.1.1.3a.cmml">migrations</mtext></msub><mo id="S4.Ex5.m1.2.2.2.2.1.1.3" stretchy="false" xref="S4.Ex5.m1.2.2.2.2.1.1.1.cmml">)</mo></mrow></mrow></mrow></mrow><annotation-xml encoding="MathML-Content" id="S4.Ex5.m1.2b"><apply id="S4.Ex5.m1.2.2.cmml" xref="S4.Ex5.m1.2.2"><csymbol cd="latexml" id="S4.Ex5.m1.2.2.3.cmml" xref="S4.Ex5.m1.2.2.3">proportional-to</csymbol><apply id="S4.Ex5.m1.2.2.4.cmml" xref="S4.Ex5.m1.2.2.4"><csymbol cd="ambiguous" id="S4.Ex5.m1.2.2.4.1.cmml" xref="S4.Ex5.m1.2.2.4">subscript</csymbol><ci id="S4.Ex5.m1.2.2.4.2.cmml" xref="S4.Ex5.m1.2.2.4.2">ℰ</ci><ci id="S4.Ex5.m1.2.2.4.3a.cmml" xref="S4.Ex5.m1.2.2.4.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.4.3.cmml" mathsize="70%" xref="S4.Ex5.m1.2.2.4.3">operational</mtext></ci></apply><apply id="S4.Ex5.m1.2.2.2.cmml" xref="S4.Ex5.m1.2.2.2"><plus id="S4.Ex5.m1.2.2.2.3.cmml" xref="S4.Ex5.m1.2.2.2.3"></plus><apply id="S4.Ex5.m1.1.1.1.1.cmml" xref="S4.Ex5.m1.1.1.1.1"><times id="S4.Ex5.m1.1.1.1.1.2.cmml" xref="S4.Ex5.m1.1.1.1.1.2"></times><ci id="S4.Ex5.m1.1.1.1.1.3.cmml" xref="S4.Ex5.m1.1.1.1.1.3">ℰ</ci><apply id="S4.Ex5.m1.1.1.1.1.1.1.1.cmml" xref="S4.Ex5.m1.1.1.1.1.1.1"><csymbol cd="ambiguous" id="S4.Ex5.m1.1.1.1.1.1.1.1.1.cmml" xref="S4.Ex5.m1.1.1.1.1.1.1">subscript</csymbol><ci id="S4.Ex5.m1.1.1.1.1.1.1.1.2a.cmml" xref="S4.Ex5.m1.1.1.1.1.1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.1.1.1.1.1.1.1.2.cmml" xref="S4.Ex5.m1.1.1.1.1.1.1.1.2">Host</mtext></ci><ci id="S4.Ex5.m1.1.1.1.1.1.1.1.3a.cmml" xref="S4.Ex5.m1.1.1.1.1.1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.1.1.1.1.1.1.1.3.cmml" mathsize="70%" xref="S4.Ex5.m1.1.1.1.1.1.1.1.3">operations</mtext></ci></apply></apply><apply id="S4.Ex5.m1.2.2.2.2.cmml" xref="S4.Ex5.m1.2.2.2.2"><times id="S4.Ex5.m1.2.2.2.2.2.cmml" xref="S4.Ex5.m1.2.2.2.2.2"></times><ci id="S4.Ex5.m1.2.2.2.2.3.cmml" xref="S4.Ex5.m1.2.2.2.2.3">ℰ</ci><apply id="S4.Ex5.m1.2.2.2.2.1.1.1.cmml" xref="S4.Ex5.m1.2.2.2.2.1.1"><csymbol cd="ambiguous" id="S4.Ex5.m1.2.2.2.2.1.1.1.1.cmml" xref="S4.Ex5.m1.2.2.2.2.1.1">subscript</csymbol><ci id="S4.Ex5.m1.2.2.2.2.1.1.1.2a.cmml" xref="S4.Ex5.m1.2.2.2.2.1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.2.2.1.1.1.2.cmml" xref="S4.Ex5.m1.2.2.2.2.1.1.1.2">Device</mtext></ci><ci id="S4.Ex5.m1.2.2.2.2.1.1.1.3a.cmml" xref="S4.Ex5.m1.2.2.2.2.1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Ex5.m1.2.2.2.2.1.1.1.3.cmml" mathsize="70%" xref="S4.Ex5.m1.2.2.2.2.1.1.1.3">migrations</mtext></ci></apply></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Ex5.m1.2c">\mathcal{E}_{\text{operational}}\propto\mathcal{E}(\text{Host}_{\text{% operations}})+\mathcal{E}(\text{Device}_{\text{migrations}})</annotation><annotation encoding="application/x-llamapun" id="S4.Ex5.m1.2d">caligraphic_E start_POSTSUBSCRIPT operational end_POSTSUBSCRIPT ∝ caligraphic_E ( Host start_POSTSUBSCRIPT operations end_POSTSUBSCRIPT ) + caligraphic_E ( Device start_POSTSUBSCRIPT migrations end_POSTSUBSCRIPT )</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> <p class="ltx_p" id="S4.Thmtheorem3.p1.1"><span class="ltx_text ltx_font_italic" id="S4.Thmtheorem3.p1.1.1">where, <math alttext="\text{Device}_{\text{migrations}}" class="ltx_Math" display="inline" id="S4.Thmtheorem3.p1.1.1.m1.1"><semantics id="S4.Thmtheorem3.p1.1.1.m1.1a"><msub id="S4.Thmtheorem3.p1.1.1.m1.1.1" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.cmml"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem3.p1.1.1.m1.1.1.2" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.2a.cmml">Device</mtext><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem3.p1.1.1.m1.1.1.3" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.3a.cmml">migrations</mtext></msub><annotation-xml encoding="MathML-Content" id="S4.Thmtheorem3.p1.1.1.m1.1b"><apply id="S4.Thmtheorem3.p1.1.1.m1.1.1.cmml" xref="S4.Thmtheorem3.p1.1.1.m1.1.1"><csymbol cd="ambiguous" id="S4.Thmtheorem3.p1.1.1.m1.1.1.1.cmml" xref="S4.Thmtheorem3.p1.1.1.m1.1.1">subscript</csymbol><ci id="S4.Thmtheorem3.p1.1.1.m1.1.1.2a.cmml" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.2"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem3.p1.1.1.m1.1.1.2.cmml" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.2">Device</mtext></ci><ci id="S4.Thmtheorem3.p1.1.1.m1.1.1.3a.cmml" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.3"><mtext class="ltx_mathvariant_italic" id="S4.Thmtheorem3.p1.1.1.m1.1.1.3.cmml" mathsize="70%" xref="S4.Thmtheorem3.p1.1.1.m1.1.1.3">migrations</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="S4.Thmtheorem3.p1.1.1.m1.1c">\text{Device}_{\text{migrations}}</annotation><annotation encoding="application/x-llamapun" id="S4.Thmtheorem3.p1.1.1.m1.1d">Device start_POSTSUBSCRIPT migrations end_POSTSUBSCRIPT</annotation></semantics></math> is the number of garbage collection operations triggered in the SSD.</span></p> </div> </div> </section> </section> </section> <section class="ltx_section" id="S5"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">5. </span>Design and Implementation</h2> <div class="ltx_para" id="S5.p1"> <p class="ltx_p" id="S5.p1.1">In this section we outline the design principles, implementation details, and lessons learned while building FDP-aware SOC and LOC data segregation in CacheLib.</p> </div> <section class="ltx_subsection" id="S5.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">5.1. </span>Design Principles</h3> <div class="ltx_para" id="S5.SS1.p1"> <p class="ltx_p" id="S5.SS1.p1.1">CacheLib is a popular building block for various caching services with diverse use cases. It is important to design a minimally invasive, adaptable, and maintainable solution for SOC and LOC data segregation. We applied the following design principles while building FDP-based data segregation support in CacheLib.</p> </div> <div class="ltx_para ltx_noindent" id="S5.SS1.p2"> <p class="ltx_p" id="S5.SS1.p2.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS1.p2.1.1">1. Keep it simple <cite class="ltx_cite ltx_citemacro_citep">(Lampson, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib42" title="">1983</a>)</cite><span class="ltx_text ltx_font_upright" id="S5.SS1.p2.1.1.1">.</span></span> This guiding principle enabled us to merge our changes upstream given the diverse use cases of CacheLib and the need for stability and maintainability of the codebase.</p> </div> <div class="ltx_para ltx_noindent" id="S5.SS1.p3"> <p class="ltx_p" id="S5.SS1.p3.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS1.p3.1.1">2. FDP is just another storage technology for CacheLib<span class="ltx_text ltx_font_upright" id="S5.SS1.p3.1.1.1">.</span></span> The design should seamlessly support deployments and setups where FDP is not used, requiring minimal configuration changes to remain user-friendly. This ensures that CacheLib maintains backward compatibility for users who do not utilize FDP SSDs.</p> </div> <div class="ltx_para ltx_noindent" id="S5.SS1.p4"> <p class="ltx_p" id="S5.SS1.p4.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS1.p4.1.1">3. Allow software extensibility for various data placement technologies<span class="ltx_text ltx_font_upright" id="S5.SS1.p4.1.1.1">.</span></span> The design should be generic and extensible to allow existing and future modules in CacheLib to segregate data and experiment with various data placement policies and decisions.</p> </div> <div class="ltx_para ltx_noindent" id="S5.SS1.p5"> <p class="ltx_p" id="S5.SS1.p5.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS1.p5.1.1">4. Allow hardware extensibility for evolving data placement technologies<span class="ltx_text ltx_font_upright" id="S5.SS1.p5.1.1.1">.</span></span> Since the FDP specification is new and expected to evolve over time, its use should be localized in the CacheLib architecture to minimize changes to the codebase over time as the hardware technology evolves.</p> </div> </section> <section class="ltx_subsection" id="S5.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">5.2. </span>Placement Handles</h3> <div class="ltx_para" id="S5.SS2.p1"> <p class="ltx_p" id="S5.SS2.p1.1">We introduce the abstract concept of <span class="ltx_text ltx_font_typewriter" id="S5.SS2.p1.1.1">Placement Handle</span> to CacheLib’s SSD I/O path to achieve FDP-based data placement while preserving backward compatibility. <span class="ltx_text ltx_font_typewriter" id="S5.SS2.p1.1.2">Placement handles</span> allow various consuming modules to segregate data. The set of available placement handles are allocated from a data placement aware device layer upon initialization. Such an abstraction hides the semantics of the underlying data placement technology e.g., FDP providing hardware extensibility. If FDP is not enabled on the underlying device, a default placement handle is used to indicate no placement preference.</p> </div> </section> <section class="ltx_subsection" id="S5.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">5.3. </span>Placement Handle Allocator</h3> <figure class="ltx_figure" id="S5.F4"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="519" id="S5.F4.g1" src="x5.png" width="665"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 4. </span>CacheLib I/O Path. <span class="ltx_text" id="S5.F4.2.1" style="font-size:144%;">\small1a⃝</span> denotes the placement handle allocator that is responsible for allocating placement handles that consume FDP.</figcaption> </figure> <div class="ltx_para" id="S5.SS3.p1"> <p class="ltx_p" id="S5.SS3.p1.1">We implement a <span class="ltx_text ltx_font_typewriter" id="S5.SS3.p1.1.1">Placement Handle Allocator</span> (Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S5.F4" title="Figure 4 ‣ 5.3. Placement Handle Allocator ‣ 5. Design and Implementation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4</span></a> <span class="ltx_text" id="S5.SS3.p1.1.2" style="font-size:144%;">\small1a⃝</span>) that is responsible for allocating placement handles to any module that wishes to use data placement. If FDP is enabled in CacheLib and the underlying SSD supports FDP, this module assigns an available ¡RUH, RG¿ pair, referred as a Placement Identifier (PID) in the FDP specification, to the placement handle it allocates. This abstracts out FDP semantics from the consumers of FDP. If the underlying SSD does not support FDP, the default handle will be allocated. This indicates that there is no placement preference. In CacheLib, SOC and LOC in each I/O engine pair get different allocation of placement handles during initialization. Modules that are minor consumers of SSD, e.g., the metadata, do not state their placement preferences, so the default reclaim unit handle is assigned to them. The introduction of the placement handle allocator provides software extensibility and flexibility.</p> </div> </section> <section class="ltx_subsection" id="S5.SS4"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">5.4. </span>FDP Aware I/O Management</h3> <div class="ltx_para" id="S5.SS4.p1"> <p class="ltx_p" id="S5.SS4.p1.1">The SOC and LOC instances tag their I/Os with unique placement handles. The FDP-aware device layer translates these handles to the corresponding FDP Placement Identifier (PID). The PIDs are further translated to the NVMe specification placement directive fields (DSPEC and DTYPE fields <cite class="ltx_cite ltx_citemacro_citep">(NVM, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib13" title="">2024</a>)</cite>), attached to the uring_cmd <cite class="ltx_cite ltx_citemacro_citep">(uri, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib21" title="">2024</a>)</cite> I/Os and then submitted. We use the I/O Passthru <cite class="ltx_cite ltx_citemacro_citep">(io-, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib12" title="">2024</a>; Joshi et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib39" title="">2024</a>)</cite> mechanism to send FDP-enabled I/Os to the Linux kernel. We use an io_uring <cite class="ltx_cite ltx_citemacro_citep">(Axboe, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib23" title="">2019</a>)</cite> queue pair per worker thread so that I/Os can be sent to the kernel without synchronization or concurrency challenges in the submission and completion queues of io_uring. The FDP aware I/O management layer provides hardware extensibility by abstracting the layout of an FDP-enabled SSD.</p> </div> </section> <section class="ltx_subsection" id="S5.SS5"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">5.5. </span>Lessons Learned and Future Directions</h3> <div class="ltx_para" id="S5.SS5.p1"> <p class="ltx_p" id="S5.SS5.p1.1">In this section, we outline a few lessons learnt over time as we integrated FDP features in CacheLib. Some of these lessons can be useful for future directions of work. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S5.SS5.p2"> <p class="ltx_p" id="S5.SS5.p2.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS5.p2.1.1">1. FDP specialized LOC eviction policy in CacheLib did not provide much benefit<span class="ltx_text ltx_font_upright" id="S5.SS5.p2.1.1.1">.</span></span> We explored the notion of a specialized FDP eviction policy for CacheLib by building reclaim unit size awareness in the region-based eviction policy of the LOC. The FDP specification provides the required semantics for the host to track writes to a reclaim unit. Utilizing it, we can track the LOC regions that belong to a reclaim unit and invalidate multiple regions in a reclaim unit together. This can be paired with a <span class="ltx_text ltx_font_typewriter" id="S5.SS5.p2.1.2">TRIM</span> command to free an entire reclaim unit and aid the garbage collection process on the SSD. Early exploration of this policy showed minimal gains and was shelved. We speculate that such a policy could be beneficial in cases where reclaim units are smaller in size. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S5.SS5.p3"> <p class="ltx_p" id="S5.SS5.p3.1"><span class="ltx_text ltx_font_bold ltx_font_italic" id="S5.SS5.p3.1.1">2. Dynamic and adaptive data placement is outperformed by simple static solutions<span class="ltx_text ltx_font_upright" id="S5.SS5.p3.1.1.1">.</span></span> Using FDP event logs, the host can inform itself of garbage collection operations in the SSD. This allows host software to understand the impact of its data placement decisions in real time. A host software stack can utilize the logs to build a feedback loop to understand its placement decisions and adapt accordingly. We explored some dynamic data placement policies using various load balancing and data temperature techniques early in the project. However, we saw minimal gains compared to the engineering complexity for such an effort over a static predefined placement handle for segregating SOC and LOC data for the small object dominant hybrid workloads.</p> </div> </section> </section> <section class="ltx_section" id="S6"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">6. </span>Evaluation</h2> <div class="ltx_para" id="S6.p1"> <p class="ltx_p" id="S6.p1.1">In this section, we explore the benefits and limitations of segregating data in the small object cache and the large object cache of CacheLib on FDP SSDs.</p> </div> <section class="ltx_subsection" id="S6.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.1. </span>Experimental Setup</h3> <div class="ltx_para" id="S6.SS1.p1"> <p class="ltx_p" id="S6.SS1.p1.1">This section describes the setup of the system, the workloads for our experiments, and the metrics used in our evaluation. <br class="ltx_break"/><span class="ltx_text ltx_font_bold" id="S6.SS1.p1.1.1">Hardware and Software Setup.</span> We use two different machines in our experimental setup with similar hardware characteristics. Both machines have two 24-core Intel Xeon Gold 6432 processors with ~528 GB of DRAM. Each machine uses a 1.88 TB Samsung PM9D3 SSD with a firmware version that supports the FDP specification. The FDP configuration on the device supports 2 namespaces, 1 RG and 8 initially isolated RU handles that can be used concurrently. For all experiments, we create a single namespace and map all the RU handles to it. Each RU is ~6 GB in size. One of the machines runs Ubuntu 22.04 with a 6.1.64 Linux kernel, while the other machine runs CentOS 9 with a 6.1.53 Linux kernel. We use <span class="ltx_text ltx_font_typewriter" id="S6.SS1.p1.1.2">nvme-cli</span> <cite class="ltx_cite ltx_citemacro_citep">(nvm, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib14" title="">2024</a>)</cite> version 2.7.1 for configuring FDP features on the SSD. <br class="ltx_break"/><span class="ltx_text ltx_font_bold" id="S6.SS1.p1.1.3">System Comparisons.</span> For our experiments, we use the main branch of the CacheLib repository which contains our upstreamed FDP-based data placement changes to segregate SOC and LOC <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib8" title="">2024a</a>; cac, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib5" title="">2024b</a>)</cite>. We use <span class="ltx_text ltx_font_typewriter" id="S6.SS1.p1.1.4">nvme-cli</span> to enable and disable FDP features on the controller to contrast between a conventional SSD and an FDP SSD. In the rest of the paper, we use the following terms to highlight the system comparisons under test,</p> <ol class="ltx_enumerate" id="S6.I1"> <li class="ltx_item" id="S6.I1.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(1)</span> <div class="ltx_para" id="S6.I1.i1.p1"> <p class="ltx_p" id="S6.I1.i1.p1.1"><span class="ltx_text ltx_font_bold" id="S6.I1.i1.p1.1.1">FDP:</span> FDP-based data segregation enabled in CacheLib and FDP configuration enabled on the SSD.</p> </div> </li> <li class="ltx_item" id="S6.I1.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">(2)</span> <div class="ltx_para" id="S6.I1.i2.p1"> <p class="ltx_p" id="S6.I1.i2.p1.1"><span class="ltx_text ltx_font_bold" id="S6.I1.i2.p1.1.1">Non-FDP:</span> FDP-based data segregation disabled in CacheLib and FDP configuration disabled on the SSD.</p> </div> </li> </ol> <p class="ltx_p" id="S6.SS1.p1.2">We use the CacheBench workload generator and trace replaying tool <cite class="ltx_cite ltx_citemacro_citep">(cac, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib4" title="">2024a</a>)</cite> to run the workloads. CacheBench is an application that invokes the CacheLib cache API in the same process and can be used to run captured traces or generate benchmarks. All the scripts used to run experiments are available publicly <cite class="ltx_cite ltx_citemacro_citep">(cac, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib9" title="">2024d</a>)</cite>. <br class="ltx_break"/><span class="ltx_text ltx_font_bold" id="S6.SS1.p1.2.1">Metrics.</span> We focus on DLWA as the primary metric to evaluate the efficacy of our data segregation changes since it has a direct correlation to endurance and embodied carbon emissions. We measure DLWA by using the <span class="ltx_text ltx_font_typewriter" id="S6.SS1.p1.2.2">nvme-cli</span> tool to query log pages (<span class="ltx_text ltx_font_typewriter" id="S6.SS1.p1.2.3">nvme get-log</span>) from the SSD controller that tracks the host bytes written to it and the device bytes that were written on NAND media over an interval of 10 minutes. We reset the SSD to a clean state before every experiment by issuing a TRIM for the entire device size. We use the CacheBench tool to measure and report throughput, latency, DRAM and NVM cache hit ratios, and ALWA for our experiments. <br class="ltx_break"/><span class="ltx_text ltx_font_bold" id="S6.SS1.p1.2.4">Workloads.</span> Our experiments use sampled 5 day anonymized traces from Meta’s key-value cache (KV Cache) cluster <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; cac, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib7" title="">2024c</a>)</cite> and 7-day anonymized traces from Twitter’s cluster12 <cite class="ltx_cite ltx_citemacro_citep">(Yang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib60" title="">2020</a>)</cite> that are publicly available for research and experimentation. <span class="ltx_text ltx_font_bold" id="S6.SS1.p1.2.5">KV Cache</span> is a read-intensive workload where the GETs outnumber SETs by a 4:1 ratio. For KV Cache, we use ~42 GB of DRAM and ~930 GB of SSD (50% device utilization) for caching as the default setup. Twitter’s cluster12 workload is write-intensive, where the SETs outnumber GETs by a 4:1 ratio. For the <span class="ltx_text ltx_font_bold" id="S6.SS1.p1.2.6">Twitter workload</span>, we use ~16 GB of DRAM and ~930 GB of SSD (50% device utilization) as the default setup. To stress the SSDs more and generate high DLWA scenarios in a shorter duration, we generated an additional write-only KV cache workload by removing the GET operations from the KV cache trace so it almost exclusively consists of SET operations. We refer to it as the <span class="ltx_text ltx_font_bold" id="S6.SS1.p1.2.7">WO KV Cache</span> workload and use the same DRAM and SSD configurations as mentioned for KV Cache.</p> </div> </section> <section class="ltx_subsection" id="S6.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.2. </span>FDP-based segregation achieves a DLWA of <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS2.1.m1.1"><semantics id="S6.SS2.1.m1.1b"><mo id="S6.SS2.1.m1.1.1" xref="S6.SS2.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS2.1.m1.1c"><csymbol cd="latexml" id="S6.SS2.1.m1.1.1.cmml" xref="S6.SS2.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS2.1.m1.1d">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS2.1.m1.1e">∼</annotation></semantics></math>1</h3> <figure class="ltx_figure" id="S6.F5"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="512" id="S6.F5.g1" src="x6.png" width="665"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 5. </span>DLWA over 60 hours with the KV Cache workload using 50% device utilization, 42GB of RAM and 4% SOC size. FDP-based segregation results in a 1.3x reduction in DLWA.</figcaption> </figure> <div class="ltx_para" id="S6.SS2.p1"> <p class="ltx_p" id="S6.SS2.p1.1">We run the KV Cache workload with the default DRAM cache size of ~42 GB and SSD cache size of ~930 GB out of a total size of 1.88 TB SSD for an effective utilization of 50%. The SOC size in the default configuration is set to 4% of the SSD size. Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F5" title="Figure 5 ‣ 6.2. FDP-based segregation achieves a DLWA of ∼1 ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">5</span></a> shows the interval DLWA over a run duration of more than 2 days. We can see that the SOC and LOC data segregation into two different reclaim unit handles helps to lower DLWA from 1.3 observed without data segregation to 1.03. This validates our analysis that segregating the sequential and cold write pattern of LOC from the random and hot write pattern of SOC by utilizing device overprovisioning helps control DLWA. <span class="ltx_text ltx_font_italic" id="S6.SS2.p1.1.1">Thus, we achieve an ideal DLWA of <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS2.p1.1.1.m1.1"><semantics id="S6.SS2.p1.1.1.m1.1a"><mo id="S6.SS2.p1.1.1.m1.1.1" xref="S6.SS2.p1.1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS2.p1.1.1.m1.1b"><csymbol cd="latexml" id="S6.SS2.p1.1.1.m1.1.1.cmml" xref="S6.SS2.p1.1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS2.p1.1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS2.p1.1.1.m1.1d">∼</annotation></semantics></math>1 with the FDP-based segregation in CacheLib.</span></p> </div> </section> <section class="ltx_subsection" id="S6.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.3. </span>FDP-based segregation enables better SSD utilization without affecting performance</h3> <figure class="ltx_figure ltx_minipage ltx_align_middle" id="S6.F6.1" style="width:390.3pt;"> <p class="ltx_p ltx_align_center" id="S6.F6.1.1"><span class="ltx_text" id="S6.F6.1.1.1"><img alt="Refer to caption" class="ltx_graphics ltx_img_square" height="814" id="S6.F6.1.1.1.g1" src="x7.png" width="789"/></span></p> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">Figure 6. </span>Effect of varying SSD utilization for caching with KV Cache Workload on DLWA and other CacheLib performance metrics like throughput, p99 read and write latency, and DRAM and SSD cache hit ratios. FDP-based segregation results in a DLWA of 1 without affecting performance irrespective of device utilization. At higher utilizations, FDP improves p99 read and write latency.</figcaption> </figure> <div class="ltx_para" id="S6.SS3.p1"> <p class="ltx_p" id="S6.SS3.p1.1">Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F6.1" title="Figure 6 ‣ 6.3. FDP-based segregation enables better SSD utilization without affecting performance ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">6</span></a> shows the impact of varying the SSD capacity used for caching upon various important metrics in CacheLib. This experiment quantifies the effect of increasing the host-level utilization of the SSD for caching. We see that the DLWA increases from 1.3 at 50% utilization to 3.5 at 100% utilization when data segregation is not employed, but the DLWA remains unchanged at ~1.03 across utilizations when data segregation is employed. We omit presentation of data points for utilization between 50% and 90% for brevity because they are similar to 50%. This result validates our analysis of device overprovisioning and the SOC invalidation rate being key factors affecting the DLWA. At 4% SOC size, the collision rate of SOC buckets is very high. This results in a high invalidation rate of SOC data in the SSD. As SOC data is segregated from LOC data, this high invalidation rate will result in minimal valid data movement due to garbage collection. Furthermore, the SSD device overprovisioning capacity, which ranges from 7-20% of SSD capacity, can now be used exclusively by SOC data to reduce the impact of garbage collection. Since the random writes of SOC constitute only 4% of the SSD capacity, their impact even at 100% device utilization is absorbed by the extra free blocks reserved by the the SSD. <span class="ltx_text ltx_font_italic" id="S6.SS3.p1.1.1">We can see that the throughput, DRAM and NVM cache hit ratio metrics remain unchanged with FDP-based segregation compared to the baseline. The p99 read and write latency also show improvement with increasing utilization due to lower interference from the garbage collection process.</span> At 100% device utilization, the p99 read and write latency shows an improvement of 1.75X and 10X respectively. <span class="ltx_text ltx_font_bold" id="S6.SS3.p1.1.2">Since we made no changes to how data is stored in SOC and LOC, we did not expect to see any change in the ALWA which we confirmed from the CacheBench logs.</span></p> </div> </section> <section class="ltx_subsection" id="S6.SS4"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.4. </span>FDP-based segregation lowers DLWA with other write-intensive workloads</h3> <figure class="ltx_figure" id="S6.F8"> <div class="ltx_flex_figure"> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_minipage ltx_align_center ltx_align_middle" id="S6.F8.2" style="width:433.6pt;"> <div class="ltx_flex_figure"> <div class="ltx_flex_cell ltx_flex_size_1"><img alt="Refer to caption" class="ltx_graphics ltx_figure_panel ltx_img_landscape" height="294" id="S6.F8.1.g1" src="x8.png" width="382"/></div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"><img alt="Refer to caption" class="ltx_graphics ltx_figure_panel ltx_img_landscape" height="301" id="S6.F8.2.g2" src="x9.png" width="382"/></div> </div> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">Figure 7. </span>DLWA over 60 hours with the Twitter cluster 12 workloads with 16GB RAM, 4% SOC size. a.) 50% device utilization and b.) 100% device utilization. FDP-based segregation achieves a DLWA of 1.</figcaption> </figure> </div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"> <figure class="ltx_figure ltx_figure_panel ltx_minipage ltx_align_center ltx_align_middle" id="S6.F8.4" style="width:433.6pt;"> <div class="ltx_flex_figure"> <div class="ltx_flex_cell ltx_flex_size_1"><img alt="Refer to caption" class="ltx_graphics ltx_figure_panel ltx_img_landscape" height="285" id="S6.F8.3.g1" src="x10.png" width="382"/></div> <div class="ltx_flex_break"></div> <div class="ltx_flex_cell ltx_flex_size_1"><img alt="Refer to caption" class="ltx_graphics ltx_figure_panel ltx_img_landscape" height="294" id="S6.F8.4.g2" src="x11.png" width="382"/></div> </div> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">Figure 8. </span>DLWA over 60 hours with the WO KV Cache workload with 42 GB RAM and 4% SOC size. a.) 50% device utilization and b.) 100% device utilization. FDP-based segregation achieves a DLWA of 1.</figcaption> </figure> </div> </div> </figure> <div class="ltx_para" id="S6.SS4.p1"> <p class="ltx_p" id="S6.SS4.p1.3">In previous sections, we demonstrated the effect of the FDP-based segregation on DLWA with the read-intensive KV Cache workload. We now explore the efficacy of our solution with the write-heavy Twitter cluster12 workload and the write-only KV Cache workload (WO KV Cache). We run experiments with both workloads at 50% and 100% device utilization, 4% of SOC size and use <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS4.p1.1.m1.1"><semantics id="S6.SS4.p1.1.m1.1a"><mo id="S6.SS4.p1.1.m1.1.1" xref="S6.SS4.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS4.p1.1.m1.1b"><csymbol cd="latexml" id="S6.SS4.p1.1.m1.1.1.cmml" xref="S6.SS4.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS4.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS4.p1.1.m1.1d">∼</annotation></semantics></math>16GB and <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS4.p1.2.m2.1"><semantics id="S6.SS4.p1.2.m2.1a"><mo id="S6.SS4.p1.2.m2.1.1" xref="S6.SS4.p1.2.m2.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS4.p1.2.m2.1b"><csymbol cd="latexml" id="S6.SS4.p1.2.m2.1.1.cmml" xref="S6.SS4.p1.2.m2.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS4.p1.2.m2.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS4.p1.2.m2.1d">∼</annotation></semantics></math>42GB of DRAM for the Twitter and WO KV cache workloads respectively as used in past research <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>; McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite>. From Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F8" title="Figure 8 ‣ 6.4. FDP-based segregation lowers DLWA with other write-intensive workloads ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">8</span></a> and <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F8" title="Figure 8 ‣ 6.4. FDP-based segregation lowers DLWA with other write-intensive workloads ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">8</span></a>, we can see that the DLWA trends observed with the KV Cache workload at 50% and 100% device utilizations remain consistent with the Twitter and WO KV Cache workloads as well. <span class="ltx_text ltx_font_italic" id="S6.SS4.p1.3.1">The FDP-based segregation achieves a DLWA of <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS4.p1.3.1.m1.1"><semantics id="S6.SS4.p1.3.1.m1.1a"><mo id="S6.SS4.p1.3.1.m1.1.1" xref="S6.SS4.p1.3.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS4.p1.3.1.m1.1b"><csymbol cd="latexml" id="S6.SS4.p1.3.1.m1.1.1.cmml" xref="S6.SS4.p1.3.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS4.p1.3.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS4.p1.3.1.m1.1d">∼</annotation></semantics></math>1 with both these challenging write-intensive workloads dominant in small object accesses.</span></p> </div> </section> <section class="ltx_subsection" id="S6.SS5"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.5. </span>FDP-based segregation gains diminish with increase in SOC size</h3> <figure class="ltx_figure" id="S6.F9"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_square" height="546" id="S6.F9.g1" src="x12.png" width="664"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 9. </span>Average DLWA with the KV Cache workload using 100% device utilization, 42GB of RAM and varying SOC size from 4% to 96% of the SSD size. FDP’s DLWA gains diminish with an increase in the SOC size beyond the device overprovisioning size.</figcaption> </figure> <div class="ltx_para" id="S6.SS5.p1"> <p class="ltx_p" id="S6.SS5.p1.1">In previous sections, we observed excellent DLWA behaviour for the KV cache workload primarily because our implementation segregates SOC’s random and hot data from LOC’s sequential and cold data. The small SOC size of 4% paired with data segregation enabled a high invalidation of SOC data in the SSD and allowed device overprovisioning to efficiently cushion garbage collection of SOC data. To further validate our analysis, we study the impact of increase of SOC size (random writes) on DLWA beyond the device overprovisioning size, which is typically 7-20% of SSD capacity. We can see from Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F9" title="Figure 9 ‣ 6.5. FDP-based segregation gains diminish with increase in SOC size ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">9</span></a> that when SOC size is increased from the default 4% to 64% the DLWA of our implementation increases from 1.03 to 2.5 while the DLWA without segregation remains above 3 for all SOC sizes.</p> </div> <div class="ltx_para" id="S6.SS5.p2"> <p class="ltx_p" id="S6.SS5.p2.1">As the SOC size crosses the device overprovisioning size, the DLWA with FDP no longer remains 1. The high DLWA at larger SOC sizes occurs because the spare blocks are fewer than the SOC data blocks. Consequently, the spare blocks coming from the device overprovisioning space fail to provide an adequate cushion for the garbage collection of SOC data. Despite the lack of cushioning, we can see that data segregation is helpful in invalidating the SOC data blocks and reduces movement of LOC data upon garbage collection. At very high SOC sizes e.g., 90% and 96% we observe that data segregation does not yield any benefits. At very high SOC sizes, there is a high probability of erase blocks containing both valid and invalid SOC data. In this scenario, data intermixing might be beneficial since sharing of invalid SOC and LOC data in an erase block would minimize data movement. Moreover, garbage collection has a lower threshold when FDP is enabled compared to when it is disabled that may accentuate the DLWA of data segregation. We observe that increasing the SOC size does not benefit the cache behavior of the workload dominant in small objects since the hit ratio almost remains unchanged.</p> </div> </section> <section class="ltx_subsection" id="S6.SS6"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.6. </span>FDP-based segregation enables cost-effective and carbon-efficient CacheLib deployments</h3> <div class="ltx_para" id="S6.SS6.p1"> <p class="ltx_p" id="S6.SS6.p1.1">In previous sections, we showed large gains in DLWA from using FDP-based segregation in CacheLib. These gains translate to a longer SSD lifetime that leads to reductions in embodied carbon emissions. The DLWA gains also aid in improving the operational efficiency of SSDs due to fewer device garbage collection operations. This results in a reduction in operational carbon emissions. In this section, we discuss the promise of FDP as a sustainable solution to combat carbon emissions.</p> </div> <figure class="ltx_figure" id="S6.F10"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="407" id="S6.F10.g1" src="x13.png" width="830"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 10. </span>Analysis of carbon savings on FDP vs Non-FDP with the KV Cache workload. a.) Embodied carbon emissions reduce drastically with FDP and b.) Garbage Collection events are reduced by a factor of <math alttext="\sim" class="ltx_Math" display="inline" id="S6.F10.2.m1.1"><semantics id="S6.F10.2.m1.1b"><mo id="S6.F10.2.m1.1.1" xref="S6.F10.2.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.F10.2.m1.1c"><csymbol cd="latexml" id="S6.F10.2.m1.1.1.cmml" xref="S6.F10.2.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.F10.2.m1.1d">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.F10.2.m1.1e">∼</annotation></semantics></math>3.6 with FDP.</figcaption> </figure> <div class="ltx_para ltx_noindent" id="S6.SS6.p2"> <p class="ltx_p" id="S6.SS6.p2.1"><span class="ltx_text ltx_font_bold" id="S6.SS6.p2.1.1">FDP-based segregation reduces carbon emissions.</span> To calculate the embodied emissions, we use Theorem 2 presented in Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.Ex3" title="4.2.1. Modelling CO2 emissions (CO2e) for FDP-enabled CacheLib ‣ 4.2. Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4.2.1</span></a> which models the embodied carbon emissions as a function of DLWA, system lifecycle period, SSD warranty, and carbon emitted by the SSD manufacturing process. We use a system lifecycle and SSD warranty of 5 years and 0.16 CO2e (Kg) as the carbon emitted per GB of SSD manufactured <cite class="ltx_cite ltx_citemacro_citep">(Tannu and Nair, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib58" title="">2023</a>)</cite>. Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F10" title="Figure 10 ‣ 6.6. FDP-based segregation enables cost-effective and carbon-efficient CacheLib deployments ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">10</span></a>a.) shows the embodied carbon emissions with and without FDP-based segregation in CacheLib. We can see that FDP enables substantial embodied carbon savings as a result of the DLWA gains. These embodied carbon gains are for a single SSD over a 5-year lifecycle. If we factor the deployment of 1000s of CacheLib clusters each consisting of 1000s of nodes, the embodied carbon emission gains from using FDP are massive.</p> </div> <div class="ltx_para" id="S6.SS6.p3"> <p class="ltx_p" id="S6.SS6.p3.1">The operational energy consumption of an SSD is directly proportional to the garbage collection events (see Theorem 3 in Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.Ex3" title="4.2.1. Modelling CO2 emissions (CO2e) for FDP-enabled CacheLib ‣ 4.2. Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4.2.1</span></a>). Utilizing FDP’s <span class="ltx_text ltx_font_typewriter" id="S6.SS6.p3.1.1">Media Relocated</span> Event in the SSD log <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib20" title="">2024b</a>)</cite> we calculate the total number of garbage collection events that occurred when FDP is enabled. For the case of Non-FDP, we run the experiment with FDP enabled but force SOC and LOC to use a single RUH to simulate the Non-FDP scenario. We ensure the garbage collection events occur for the same amount of host writes to the SSD to account for the energy consumption due to internal operations. Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F10" title="Figure 10 ‣ 6.6. FDP-based segregation enables cost-effective and carbon-efficient CacheLib deployments ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">10</span></a>b.) shows that with the KV Cache workload, FDP-based segregation resulted in <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS6.p3.1.m1.1"><semantics id="S6.SS6.p3.1.m1.1a"><mo id="S6.SS6.p3.1.m1.1.1" xref="S6.SS6.p3.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS6.p3.1.m1.1b"><csymbol cd="latexml" id="S6.SS6.p3.1.m1.1.1.cmml" xref="S6.SS6.p3.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS6.p3.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS6.p3.1.m1.1d">∼</annotation></semantics></math>3.6x fewer GC events for the same amount of host writes to the SSD. This shows that FDP-based segregation helps in improving the operational energy consumption of the SSD leading to operational carbon savings. Based on DLWA gains obtained for Twitter and WO KV Cache in Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS4" title="6.4. FDP-based segregation lowers DLWA with other write-intensive workloads ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">6.4</span></a>, large embodied and operational carbon gains can be realized for both those workloads. <br class="ltx_break"/></p> </div> <div class="ltx_para ltx_noindent" id="S6.SS6.p4"> <p class="ltx_p" id="S6.SS6.p4.1"><span class="ltx_text ltx_font_bold" id="S6.SS6.p4.1.1">FDP-based segregation allows for carbon-efficient deployments with lower DRAM requirements.</span></p> </div> <figure class="ltx_table" id="S6.T2"> <table class="ltx_tabular ltx_centering ltx_align_middle" id="S6.T2.1"> <tr class="ltx_tr" id="S6.T2.1.1"> <td class="ltx_td ltx_align_left ltx_border_tt" id="S6.T2.1.1.1"> <span class="ltx_text" id="S6.T2.1.1.1.1"></span> <span class="ltx_text" id="S6.T2.1.1.1.2"> <span class="ltx_tabular ltx_align_middle" id="S6.T2.1.1.1.2.1"> <span class="ltx_tr" id="S6.T2.1.1.1.2.1.1"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.1.2.1.1.1">Configuration</span></span> </span></span><span class="ltx_text" id="S6.T2.1.1.1.3"></span></td> <td class="ltx_td ltx_align_center ltx_border_tt" id="S6.T2.1.1.2"> <span class="ltx_text" id="S6.T2.1.1.2.1"></span> <span class="ltx_text" id="S6.T2.1.1.2.2"> <span class="ltx_tabular ltx_align_middle" id="S6.T2.1.1.2.2.1"> <span class="ltx_tr" id="S6.T2.1.1.2.2.1.1"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.2.2.1.1.1">Hit Ratio</span></span> <span class="ltx_tr" id="S6.T2.1.1.2.2.1.2"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.2.2.1.2.1">(%)</span></span> </span></span><span class="ltx_text" id="S6.T2.1.1.2.3"></span></td> <td class="ltx_td ltx_align_center ltx_border_tt" id="S6.T2.1.1.3"> <span class="ltx_text" id="S6.T2.1.1.3.1"></span> <span class="ltx_text" id="S6.T2.1.1.3.2"> <span class="ltx_tabular ltx_align_middle" id="S6.T2.1.1.3.2.1"> <span class="ltx_tr" id="S6.T2.1.1.3.2.1.1"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.3.2.1.1.1">NVM Hit</span></span> <span class="ltx_tr" id="S6.T2.1.1.3.2.1.2"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.3.2.1.2.1">Ratio (%)</span></span> </span></span><span class="ltx_text" id="S6.T2.1.1.3.3"></span></td> <td class="ltx_td ltx_align_center ltx_border_tt" id="S6.T2.1.1.4">KGET/s</td> <td class="ltx_td ltx_align_center ltx_border_tt" id="S6.T2.1.1.5"> <span class="ltx_text" id="S6.T2.1.1.5.1"></span> <span class="ltx_text" id="S6.T2.1.1.5.2"> <span class="ltx_tabular ltx_align_middle" id="S6.T2.1.1.5.2.1"> <span class="ltx_tr" id="S6.T2.1.1.5.2.1.1"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.5.2.1.1.1">CO2e</span></span> <span class="ltx_tr" id="S6.T2.1.1.5.2.1.2"> <span class="ltx_td ltx_nopad_r ltx_align_center" id="S6.T2.1.1.5.2.1.2.1">(Kg)</span></span> </span></span><span class="ltx_text" id="S6.T2.1.1.5.3"></span></td> </tr> <tr class="ltx_tr" id="S6.T2.1.2"> <td class="ltx_td ltx_align_left ltx_border_t" id="S6.T2.1.2.1">FDP 4GB</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.2.2">86.3</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.2.3">37.74</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.2.4">303.1</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.2.5">347.2</td> </tr> <tr class="ltx_tr" id="S6.T2.1.3"> <td class="ltx_td ltx_align_left" id="S6.T2.1.3.1">Non-FDP 4GB</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.3.2">86.11</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.3.3">37.41</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.3.4">298.8</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.3.5">1081.1</td> </tr> <tr class="ltx_tr" id="S6.T2.1.4"> <td class="ltx_td ltx_align_left ltx_border_t" id="S6.T2.1.4.1">FDP 20GB</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.4.2">91.9</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.4.3">31.37</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.4.4">412.2</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.4.5">372.8</td> </tr> <tr class="ltx_tr" id="S6.T2.1.5"> <td class="ltx_td ltx_align_left" id="S6.T2.1.5.1">Non-FDP 20GB</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.5.2">92.1</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.5.3">33</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.5.4">399.1</td> <td class="ltx_td ltx_align_center" id="S6.T2.1.5.5">1106.8</td> </tr> <tr class="ltx_tr" id="S6.T2.1.6"> <td class="ltx_td ltx_align_left ltx_border_t" id="S6.T2.1.6.1">FDP 42GB</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.6.2">90.32</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.6.3">17.51</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.6.4">445.9</td> <td class="ltx_td ltx_align_center ltx_border_t" id="S6.T2.1.6.5">409.6</td> </tr> <tr class="ltx_tr" id="S6.T2.1.7"> <td class="ltx_td ltx_align_left ltx_border_bb" id="S6.T2.1.7.1">Non-FDP 42GB</td> <td class="ltx_td ltx_align_center ltx_border_bb" id="S6.T2.1.7.2">90.22</td> <td class="ltx_td ltx_align_center ltx_border_bb" id="S6.T2.1.7.3">17.34</td> <td class="ltx_td ltx_align_center ltx_border_bb" id="S6.T2.1.7.4">434.4</td> <td class="ltx_td ltx_align_center ltx_border_bb" id="S6.T2.1.7.5">1143.6</td> </tr> </table> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_table">Table 2. </span>KV Cache workload with 100% device utilization, 4% SOC size and RAM size of 4GB and 42GB. We see that FDP enables carbon-efficient deployments with reduced DRAM for a tradeoff in hit ratio and throughput.</figcaption> </figure> <div class="ltx_para" id="S6.SS6.p5"> <p class="ltx_p" id="S6.SS6.p5.1">In this section, we explore whether increase in SSD utilization in the Flash Cache of CacheLib can help reduce the DRAM Cache size. The main motivation behind this exploration is to reduce the cost and carbon footprint of CacheLib deployments. DRAM’s embodied carbon footprint is at least an order of magnitude higher than an SSD <cite class="ltx_cite ltx_citemacro_citep">(Gupta et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib36" title="">2022b</a>)</cite>. A similar trend also exists for cost. We run the KV Cache workload with 100% device utilization, 4% SOC size and vary the DRAM used in the RAM Cache layer of CacheLib.</p> </div> <div class="ltx_para" id="S6.SS6.p6"> <p class="ltx_p" id="S6.SS6.p6.1">Table <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.T2" title="Table 2 ‣ 6.6. FDP-based segregation enables cost-effective and carbon-efficient CacheLib deployments ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">2</span></a> shows the overall hit ratios, NVM hit ratios, throughput and effective carbon emission with different RAM cache sizes. We see that a lower DRAM leads to a reduction in hit ratio and throughput while being more carbon-efficient. An SSD utilization of 100% enables more items to be cached in the Flash Cache. Consequently, we see that as the RAM cache size reduces, the NVM hit ratios improve massively for both FDP and Non-FDP while the overall hit ratios and throughput drop. <span class="ltx_text ltx_font_italic" id="S6.SS6.p6.1.1">A deployment with lower DRAM and 100% device utilization was not viable without FDP-based segregation due to the high DLWA of <math alttext="\sim" class="ltx_Math" display="inline" id="S6.SS6.p6.1.1.m1.1"><semantics id="S6.SS6.p6.1.1.m1.1a"><mo id="S6.SS6.p6.1.1.m1.1.1" xref="S6.SS6.p6.1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="S6.SS6.p6.1.1.m1.1b"><csymbol cd="latexml" id="S6.SS6.p6.1.1.m1.1.1.cmml" xref="S6.SS6.p6.1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="S6.SS6.p6.1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="S6.SS6.p6.1.1.m1.1d">∼</annotation></semantics></math>3.5</span>. While the 1.5x reduction in throughput might not be acceptable to applications with strict SLAs, applications that can tolerate this decrease for a 4x gain in carbon savings might find this deployment appealing. Since CacheLib is used as a building block for services <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite>, the flexibility in deployment provided by FDP to achieve greater carbon efficiency may be highly desirable.</p> </div> </section> <section class="ltx_subsection" id="S6.SS7"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">6.7. </span>FDP-based segregation enables multi-tenant KV Cache deployments</h3> <figure class="ltx_figure" id="S6.F11"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="471" id="S6.F11.g1" src="x14.png" width="663"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 11. </span>DLWA over 60 hours with the WO KV Cache workload running on two tenants each using 930GB SSD space and 4% SOC size and 42 GB RAM. FDP enables a 3.5x reduction in DLWA in this multi-tenant deployment.</figcaption> </figure> <div class="ltx_para" id="S6.SS7.p1"> <p class="ltx_p" id="S6.SS7.p1.1">Without the use of FDP, 50% of the SSD had to be reserved for host overprovisioning to achieve an acceptable DLWA. With FDP, however, we demonstrated that a DLWA of ~1 can be achieved without any host overprovisioning. This effectively frees up half of the device, allowing it to be utilized for other purposes. One option we explored was to increase the SSD capacity for a single CacheLib instance from 50% to 100%. Another option involves running two CacheLib instances that share the SSD, each using half of the available space for its Flash cache to simulate a multi-tenant setup.</p> </div> <div class="ltx_para" id="S6.SS7.p2"> <p class="ltx_p" id="S6.SS7.p2.1">We evaluate the effectiveness of SOC and LOC data segregation under this multi-tenant configuration, with two KV cache instances running the WO KV cache workload on a shared 1.88 TB SSD without any overprovisioning. We partition the SSD into two equal parts (~930 GB each), with each KV cache instance (tenant) assigned to one partition. Both SOC and LOC sizes are set at 4% and 96% respectively. Our placement policy maps the SOC and LOC of the two tenants to different reclaim unit handles while all other parameters remain unchanged. Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.F11" title="Figure 11 ‣ 6.7. FDP-based segregation enables multi-tenant KV Cache deployments ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">11</span></a> shows that the DLWA remains ~1 because each tenant segregates its SOC and LOC data. In contrast, without FDP the DLWA increases to ~3.5.</p> </div> </section> </section> <section class="ltx_section" id="S7"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">7. </span>Related Work</h2> <section class="ltx_subsection" id="S7.SS1"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">7.1. </span>Data Placement in SSDs</h3> <div class="ltx_para" id="S7.SS1.p1"> <p class="ltx_p" id="S7.SS1.p1.1">Write amplification in Flash-based SSDs <cite class="ltx_cite ltx_citemacro_citep">(Boboila and Desnoyers, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib27" title="">2010</a>; He et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib37" title="">2017</a>; Lee et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib43" title="">2015</a>; Lu et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib47" title="">2013</a>; Jung and Kandemir, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib40" title="">2013</a>)</cite> is a well studied problem that has received attention through various data placement proposals over the past years. To tackle device-level write amplification (DLWA), SSD controllers use various heuristics to segregate data based on its characteristics (e.g., access patterns, temperature, etc.) on Flash media to minimize garbage collection and data movement costs <cite class="ltx_cite ltx_citemacro_citep">(Gal and Toledo, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib34" title="">2005</a>; Chang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib29" title="">2004</a>)</cite>. There have been various proposals in the NVMe data placement space for cooperation between host and FTL to leverage host application domain knowledge. One approach is to pass hints to the FTL as proposed in Multi-Streamed SSDs <cite class="ltx_cite ltx_citemacro_citep">(Kang, Jeong-Uk and Hyun, Jeeseok and Maeng, Hyunjoo and Cho, Sangyeun, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib41" title="">2014</a>)</cite>. Another contrary approach proposed in Open-Channel SSDs <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib26" title="">2017</a>)</cite> and DFS <cite class="ltx_cite ltx_citemacro_citep">(Josephson et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib38" title="">2010</a>)</cite> is to expose the SSD internals completely paving the way for host-based FTLs. There have also been software-defined Flash proposals to expose NAND channels in SDF <cite class="ltx_cite ltx_citemacro_citep">(Ouyang et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib51" title="">2014</a>)</cite> and to explore alternative storage abstractions that can be leveraged by key-value stores <cite class="ltx_cite ltx_citemacro_citep">(Lee et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib44" title="">2016</a>)</cite>.</p> </div> <div class="ltx_para" id="S7.SS1.p2"> <p class="ltx_p" id="S7.SS1.p2.1">Zoned Namespaces (ZNS) <cite class="ltx_cite ltx_citemacro_citep">(Bjørling et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib25" title="">2021</a>)</cite> was a follow-up on Open-Channel SSD 2.0 specification designed to leverage existing support of SMR HDDs. Despite impressive DLWA results, the append-only write model and host-based garbage collection imposes upfront software engineering costs for applications that do not conform to log-structured access patterns. This has posed a challenge for the wide adoption of ZNS. FDP TP <cite class="ltx_cite ltx_citemacro_citep">(fdp, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib20" title="">2024b</a>)</cite> was proposed based on lessons learned from the past. It consolidates Google’s SmartFTL <cite class="ltx_cite ltx_citemacro_citep">(Sabol and Desai, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib53" title="">[n. d.]</a>)</cite> and Meta’s Direct Placement Mode proposals to fill the cost-benefit gap between ZNS and conventional SSDs. The concept of RUHs in FDP borrows heavily from the concept of streams in multi-streamed SSDs. FDP was crafted with backward compatibility in mind, enabling an application storage stack to operate seamlessly without modifications. Additionally, applications have the option to harness FDP features by opting to enable them. FDP also does not introduce any new command sets. In this work, we have leveraged FDP features for data placement using Linux kernel I/O Passthru features <cite class="ltx_cite ltx_citemacro_citep">(io-, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib12" title="">2024</a>; Joshi et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib39" title="">2024</a>)</cite>. The backward compatibility of FDP and its ease of integration into the CacheLib software have been key drivers in the upstreaming process of our work.</p> </div> </section> <section class="ltx_subsection" id="S7.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">7.2. </span>Key-Value Stores and Hybrid Caching</h3> <div class="ltx_para" id="S7.SS2.p1"> <p class="ltx_p" id="S7.SS2.p1.1">A lot of research effort has been dedicated to the design of key-value stores <cite class="ltx_cite ltx_citemacro_citep">(roc, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib16" title="">2024</a>; Lim et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib46" title="">2011</a>; Raju et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib52" title="">2017</a>)</cite> that conform to the performance tradeoffs of Flash-based SSDs <cite class="ltx_cite ltx_citemacro_citep">(He et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib37" title="">2017</a>; Jung and Kandemir, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib40" title="">2013</a>; Agrawal et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib22" title="">2008</a>)</cite>. Their inadequacy for hybrid caching use cases at Meta that are dominated by random writes of small objects causing severe DLWA has been previously highlighted <cite class="ltx_cite ltx_citemacro_citep">(McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>; Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite>. Log-structured caches <cite class="ltx_cite ltx_citemacro_citep">(Shen et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib55" title="">2017</a>; Eisenman et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib33" title="">2019</a>)</cite> designed for Flash to minimize write amplification suffer from DRAM overhead issues (especially for numerous small items) which formed the motivation for the work in Kangaroo <cite class="ltx_cite ltx_citemacro_citep">(McAllister, Sara and Berg, Benjamin and Tutuncu-Macias, Julian and Yang, Juncheng and Gunasekar, Sathya and Lu, Jimmy and Berger, Daniel S and Beckmann, Nathan and Ganger, Gregory R, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib49" title="">2021</a>)</cite>. Our present work is complementary to these efforts because we keep the cache architecture and design of CacheLib <cite class="ltx_cite ltx_citemacro_citep">(Benjamin Berg and Daniel S. Berger and Sara McAllister and Isaac Grosof and Sathya Gunasekar and Jimmy Lu and Michael Uhlar and Jim Carrig and Nathan Beckmann and Mor Harchol-Balter and Gregory R. Ganger, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib24" title="">2020</a>)</cite> unchanged and leverage FDP features for data placement in its I/O write paths to minimize DLWA. FairyWren <cite class="ltx_cite ltx_citemacro_citep">(McAllister et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib48" title="">2024</a>)</cite> extended Kangaroo to integrate ZNS devices for lower DLWA. We observe similar DLWA and carbon emission gains through data placement alone, without modifying the original architecture and design of CacheLib.</p> </div> </section> </section> <section class="ltx_section" id="S8"> <h2 class="ltx_title ltx_title_section"> <span class="ltx_tag ltx_tag_section">8. </span>Conclusion</h2> <div class="ltx_para" id="S8.p1"> <p class="ltx_p" id="S8.p1.1">The problem of device-level write amplification (DLWA) is becoming exceedingly important given the increased deployment of Flash caches and the sustainability challenges faced by modern data centers. Our work of segregating Flash cache data in Flash media using FDP SSDs shows an ideal DLWA of ~1 is possible without any host overprovisioning and overhead to Flash cache metrics. This results in massive cost (2x) and carbon emission (4x) reductions at scale. The reduction in DLWA, along with increased device utilization, opens up new deployment opportunities for hybrid caches that were previously unfeasible. For example, this approach can reduce DRAM consumption while enabling SSD sharing in multi-tenant settings. Our work to isolate data using FDP in a state-of-the-art Flash cache, CacheLib has already been merged in the upstream repository. This highlights its impact and the appeal of reduced engineering cost of FDP SSDs for Flash caches where data placement is key to reduce their DLWA and carbon emissions. </p> </div> <div class="ltx_acknowledgements"> <h6 class="ltx_title ltx_title_acknowledgements">Acknowledgements.</h6> We would like to thank the anonymous reviewers and our shepherd, Jian Huang, for their constructive feedback and insightful comments, which greatly shaped this work. We also extend our gratitude to Samsung Memory Research Center (SMRC) for providing the infrastructure that enabled experimentation for this study, as well as for their support. Additionally, we would like to acknowledge the efforts of Ross Stenfort, Jaesoo Lee, and the entire CacheLib team at Meta for their invaluable feedback and guidance. Lastly, we are grateful to the members of Samsung’s Global Open-ecoSystem Team (GOST) for their feedback, guidance, and support in enabling the FDP ecosystem, without which this work would not have been possible. </div> </section> <section class="ltx_bibliography" id="bib"> <h2 class="ltx_title ltx_title_bibliography">References</h2> <ul class="ltx_biblist"> <li class="ltx_bibitem" id="bib.bib1"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">(1)</span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib2"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">zns (2024)</span> <span class="ltx_bibblock"> 2024. </span> <span class="ltx_bibblock"> Zoned Namespaces (ZNS) SSDs. <a class="ltx_ref ltx_url ltx_font_typewriter" href="https://zonedstorage.io/docs/introduction" title="">https://zonedstorage.io/docs/introduction</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib3"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">ama (2024)</span> <span class="ltx_bibblock"> 2024. </span> <span class="ltx_bibblock">Amazon Sustainability. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://sustainability.aboutamazon.com/climate-solutions" title="">https://sustainability.aboutamazon.com/climate-solutions</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib4"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">cac (2024a)</span> <span class="ltx_bibblock"> 2024a. </span> <span class="ltx_bibblock">CacheBench. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://cachelib.org/docs/Cache_Library_User_Guides/Cachebench_Overview/" title="">https://cachelib.org/docs/Cache_Library_User_Guides/Cachebench_Overview/</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib5"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">cac (2024b)</span> <span class="ltx_bibblock"> 2024b. </span> <span class="ltx_bibblock">CacheLib Github Repository. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://github.com/facebook/CacheLib" title="">https://github.com/facebook/CacheLib</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib6"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">goo (2024)</span> <span class="ltx_bibblock"> 2024. </span> <span class="ltx_bibblock">Climate change is humanity’s next big moonshot. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://blog.google/outreach-initiatives/sustainability/dear-earth/" title="">https://blog.google/outreach-initiatives/sustainability/dear-earth/</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib7"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">cac (2024c)</span> <span class="ltx_bibblock"> 2024c. </span> <span class="ltx_bibblock">Evaluating SSD hardware for Facebook workloads. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://cachelib.org/docs/Cache_Library_User_Guides/Cachebench_FB_HW_eval/##list-of-traces" title="">https://cachelib.org/docs/Cache_Library_User_Guides/Cachebench_FB_HW_eval/##list-of-traces</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib8"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">fdp (2024a)</span> <span class="ltx_bibblock"> 2024a. </span> <span class="ltx_bibblock">FDP PR on CacheLib. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://github.com/facebook/CacheLib/pull/277" title="">https://github.com/facebook/CacheLib/pull/277</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib9"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">cac (2024d)</span> <span class="ltx_bibblock"> 2024d. </span> <span class="ltx_bibblock">Github Repository <span class="ltx_text ltx_font_typewriter" id="bib.bib9.1.1">cachelib-devops</span>. </span> <span class="ltx_bibblock"><a class="ltx_ref ltx_url ltx_font_typewriter" href="https://github.com/SamsungDS/cachelib-devops" title="">https://github.com/SamsungDS/cachelib-devops</a>. </span> <span class="ltx_bibblock"> </span> </li> <li class="ltx_bibitem" id="bib.bib10"> <span class="ltx_tag ltx_role_refnum ltx_tag_bibitem">gre (2024)</span> <span class="ltx_bibblock"> 2024. </span> <span class="ltx_bibblock">Greenhouse Gases Equivalencies Calculator - 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This results in a purely sequential write pattern of LBAs to the SSD.</p> </div> </li> <li class="ltx_item" id="A1.I1.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i2.p1"> <p class="ltx_p" id="A1.I1.i2.p1.1">With FDP, the LOC writes are written into a separate RU and physical block. The purely sequential write pattern of LOC and its segregation into a separate physical block and RU means that LOC data invalidates itself nicely and contributes to negligible (or no) live data movement.</p> </div> </li> <li class="ltx_item" id="A1.I1.i3" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i3.p1"> <p class="ltx_p" id="A1.I1.i3.p1.1">Items are inserted into the SOC buckets using a uniform hash function. Every SOC item insertion results in the entire hashed bucket (a 4KB page) being written. While a modulo is not purely sequential, for this model we assume that the SOC generates a uniform random write pattern.</p> </div> </li> <li class="ltx_item" id="A1.I1.i4" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i4.p1"> <p class="ltx_p" id="A1.I1.i4.p1.1">With FDP, all SOC data is segregated into a separate RU and physical block. The random nature of SOC writes means that its data contributes to live data movement.</p> </div> </li> <li class="ltx_item" id="A1.I1.i5" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i5.p1"> <p class="ltx_p" id="A1.I1.i5.p1.1">As the LOC writes are sequential and will not need any live data movement, it is safe to assume that only SOC writes contribute to device-level write amplification.</p> </div> </li> <li class="ltx_item" id="A1.I1.i6" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i6.p1"> <p class="ltx_p" id="A1.I1.i6.p1.1">The SSD has some amount of overprovisioning space.</p> </div> </li> <li class="ltx_item" id="A1.I1.i7" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I1.i7.p1"> <p class="ltx_p" id="A1.I1.i7.p1.1">In the case of FDP, since the physical blocks and RUs that contain LOC data free themselves up due to the sequential write pattern, we assume that the overprovisioned space can be entirely used by the writes from SOC data.</p> </div> </li> </ul> </div> <figure class="ltx_table" id="A1.T3"> <table class="ltx_tabular ltx_centering ltx_align_middle" id="A1.T3.12"> <tr class="ltx_tr" id="A1.T3.12.13"> <td class="ltx_td ltx_align_left ltx_border_tt" id="A1.T3.12.13.1"><span class="ltx_text ltx_font_bold" id="A1.T3.12.13.1.1">Variable</span></td> <td class="ltx_td ltx_align_left ltx_border_tt" id="A1.T3.12.13.2"><span class="ltx_text ltx_font_bold" id="A1.T3.12.13.2.1">Description</span></td> </tr> <tr class="ltx_tr" id="A1.T3.1.1"> <td class="ltx_td ltx_align_left ltx_border_t" id="A1.T3.1.1.1"><math alttext="\text{N}_{\text{B}}" class="ltx_Math" display="inline" id="A1.T3.1.1.1.m1.1"><semantics id="A1.T3.1.1.1.m1.1a"><msub id="A1.T3.1.1.1.m1.1.1" xref="A1.T3.1.1.1.m1.1.1.cmml"><mtext id="A1.T3.1.1.1.m1.1.1.2" xref="A1.T3.1.1.1.m1.1.1.2a.cmml">N</mtext><mtext id="A1.T3.1.1.1.m1.1.1.3" xref="A1.T3.1.1.1.m1.1.1.3a.cmml">B</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.T3.1.1.1.m1.1b"><apply id="A1.T3.1.1.1.m1.1.1.cmml" xref="A1.T3.1.1.1.m1.1.1"><csymbol cd="ambiguous" id="A1.T3.1.1.1.m1.1.1.1.cmml" xref="A1.T3.1.1.1.m1.1.1">subscript</csymbol><ci id="A1.T3.1.1.1.m1.1.1.2a.cmml" xref="A1.T3.1.1.1.m1.1.1.2"><mtext id="A1.T3.1.1.1.m1.1.1.2.cmml" xref="A1.T3.1.1.1.m1.1.1.2">N</mtext></ci><ci id="A1.T3.1.1.1.m1.1.1.3a.cmml" xref="A1.T3.1.1.1.m1.1.1.3"><mtext id="A1.T3.1.1.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.1.1.1.m1.1.1.3">B</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.1.1.1.m1.1c">\text{N}_{\text{B}}</annotation><annotation encoding="application/x-llamapun" id="A1.T3.1.1.1.m1.1d">N start_POSTSUBSCRIPT B end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left ltx_border_t" id="A1.T3.1.1.2">Number of SOC Buckets</td> </tr> <tr class="ltx_tr" id="A1.T3.2.2"> <td class="ltx_td ltx_align_left" id="A1.T3.2.2.1"><math alttext="\text{N}_{\text{BB}}" class="ltx_Math" display="inline" id="A1.T3.2.2.1.m1.1"><semantics id="A1.T3.2.2.1.m1.1a"><msub id="A1.T3.2.2.1.m1.1.1" xref="A1.T3.2.2.1.m1.1.1.cmml"><mtext id="A1.T3.2.2.1.m1.1.1.2" xref="A1.T3.2.2.1.m1.1.1.2a.cmml">N</mtext><mtext id="A1.T3.2.2.1.m1.1.1.3" xref="A1.T3.2.2.1.m1.1.1.3a.cmml">BB</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.T3.2.2.1.m1.1b"><apply id="A1.T3.2.2.1.m1.1.1.cmml" xref="A1.T3.2.2.1.m1.1.1"><csymbol cd="ambiguous" id="A1.T3.2.2.1.m1.1.1.1.cmml" xref="A1.T3.2.2.1.m1.1.1">subscript</csymbol><ci id="A1.T3.2.2.1.m1.1.1.2a.cmml" xref="A1.T3.2.2.1.m1.1.1.2"><mtext id="A1.T3.2.2.1.m1.1.1.2.cmml" xref="A1.T3.2.2.1.m1.1.1.2">N</mtext></ci><ci id="A1.T3.2.2.1.m1.1.1.3a.cmml" xref="A1.T3.2.2.1.m1.1.1.3"><mtext id="A1.T3.2.2.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.2.2.1.m1.1.1.3">BB</mtext></ci></apply></annotation-xml><annotation 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id="A1.T3.6.6.1.m1.1.1.1.cmml" xref="A1.T3.6.6.1.m1.1.1">subscript</csymbol><ci id="A1.T3.6.6.1.m1.1.1.2a.cmml" xref="A1.T3.6.6.1.m1.1.1.2"><mtext id="A1.T3.6.6.1.m1.1.1.2.cmml" xref="A1.T3.6.6.1.m1.1.1.2">S</mtext></ci><ci id="A1.T3.6.6.1.m1.1.1.3a.cmml" xref="A1.T3.6.6.1.m1.1.1.3"><mtext id="A1.T3.6.6.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.6.6.1.m1.1.1.3">Usable</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.6.6.1.m1.1c">\text{S}_{\text{Usable}}</annotation><annotation encoding="application/x-llamapun" id="A1.T3.6.6.1.m1.1d">S start_POSTSUBSCRIPT Usable end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left" id="A1.T3.6.6.2">Total Usable Physical Space</td> </tr> <tr class="ltx_tr" id="A1.T3.7.7"> <td class="ltx_td ltx_align_left" id="A1.T3.7.7.1"><math alttext="\text{S}_{\text{OP}}" class="ltx_Math" display="inline" id="A1.T3.7.7.1.m1.1"><semantics id="A1.T3.7.7.1.m1.1a"><msub id="A1.T3.7.7.1.m1.1.1" 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class="ltx_td ltx_align_left" id="A1.T3.7.7.2">Total OP Space</td> </tr> <tr class="ltx_tr" id="A1.T3.8.8"> <td class="ltx_td ltx_align_left" id="A1.T3.8.8.1"><math alttext="\text{S}_{\text{LOC}}" class="ltx_Math" display="inline" id="A1.T3.8.8.1.m1.1"><semantics id="A1.T3.8.8.1.m1.1a"><msub id="A1.T3.8.8.1.m1.1.1" xref="A1.T3.8.8.1.m1.1.1.cmml"><mtext id="A1.T3.8.8.1.m1.1.1.2" xref="A1.T3.8.8.1.m1.1.1.2a.cmml">S</mtext><mtext id="A1.T3.8.8.1.m1.1.1.3" xref="A1.T3.8.8.1.m1.1.1.3a.cmml">LOC</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.T3.8.8.1.m1.1b"><apply id="A1.T3.8.8.1.m1.1.1.cmml" xref="A1.T3.8.8.1.m1.1.1"><csymbol cd="ambiguous" id="A1.T3.8.8.1.m1.1.1.1.cmml" xref="A1.T3.8.8.1.m1.1.1">subscript</csymbol><ci id="A1.T3.8.8.1.m1.1.1.2a.cmml" xref="A1.T3.8.8.1.m1.1.1.2"><mtext id="A1.T3.8.8.1.m1.1.1.2.cmml" xref="A1.T3.8.8.1.m1.1.1.2">S</mtext></ci><ci id="A1.T3.8.8.1.m1.1.1.3a.cmml" xref="A1.T3.8.8.1.m1.1.1.3"><mtext id="A1.T3.8.8.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.8.8.1.m1.1.1.3">LOC</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.8.8.1.m1.1c">\text{S}_{\text{LOC}}</annotation><annotation encoding="application/x-llamapun" id="A1.T3.8.8.1.m1.1d">S start_POSTSUBSCRIPT LOC end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left" id="A1.T3.8.8.2">Total LOC logical Space</td> </tr> <tr class="ltx_tr" id="A1.T3.9.9"> <td class="ltx_td ltx_align_left" id="A1.T3.9.9.1"><math alttext="\text{S}_{\text{P-LOC}}" class="ltx_Math" display="inline" id="A1.T3.9.9.1.m1.1"><semantics id="A1.T3.9.9.1.m1.1a"><msub id="A1.T3.9.9.1.m1.1.1" xref="A1.T3.9.9.1.m1.1.1.cmml"><mtext id="A1.T3.9.9.1.m1.1.1.2" xref="A1.T3.9.9.1.m1.1.1.2a.cmml">S</mtext><mtext id="A1.T3.9.9.1.m1.1.1.3" xref="A1.T3.9.9.1.m1.1.1.3a.cmml">P-LOC</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.T3.9.9.1.m1.1b"><apply id="A1.T3.9.9.1.m1.1.1.cmml" xref="A1.T3.9.9.1.m1.1.1"><csymbol cd="ambiguous" id="A1.T3.9.9.1.m1.1.1.1.cmml" xref="A1.T3.9.9.1.m1.1.1">subscript</csymbol><ci id="A1.T3.9.9.1.m1.1.1.2a.cmml" xref="A1.T3.9.9.1.m1.1.1.2"><mtext id="A1.T3.9.9.1.m1.1.1.2.cmml" xref="A1.T3.9.9.1.m1.1.1.2">S</mtext></ci><ci id="A1.T3.9.9.1.m1.1.1.3a.cmml" xref="A1.T3.9.9.1.m1.1.1.3"><mtext id="A1.T3.9.9.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.9.9.1.m1.1.1.3">P-LOC</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.9.9.1.m1.1c">\text{S}_{\text{P-LOC}}</annotation><annotation encoding="application/x-llamapun" id="A1.T3.9.9.1.m1.1d">S start_POSTSUBSCRIPT P-LOC end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left" id="A1.T3.9.9.2">Total Physical Space for LOC</td> </tr> <tr class="ltx_tr" id="A1.T3.10.10"> <td class="ltx_td ltx_align_left" id="A1.T3.10.10.1"><math alttext="\text{S}_{\text{P-SOC}}" class="ltx_Math" display="inline" id="A1.T3.10.10.1.m1.1"><semantics id="A1.T3.10.10.1.m1.1a"><msub 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start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left" id="A1.T3.10.10.2">Total Physical Space for SOC data</td> </tr> <tr class="ltx_tr" id="A1.T3.11.11"> <td class="ltx_td ltx_align_left" id="A1.T3.11.11.1"><math alttext="\text{S}_{\text{NVM}}" class="ltx_Math" display="inline" id="A1.T3.11.11.1.m1.1"><semantics id="A1.T3.11.11.1.m1.1a"><msub id="A1.T3.11.11.1.m1.1.1" xref="A1.T3.11.11.1.m1.1.1.cmml"><mtext id="A1.T3.11.11.1.m1.1.1.2" xref="A1.T3.11.11.1.m1.1.1.2a.cmml">S</mtext><mtext id="A1.T3.11.11.1.m1.1.1.3" xref="A1.T3.11.11.1.m1.1.1.3a.cmml">NVM</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.T3.11.11.1.m1.1b"><apply id="A1.T3.11.11.1.m1.1.1.cmml" xref="A1.T3.11.11.1.m1.1.1"><csymbol cd="ambiguous" id="A1.T3.11.11.1.m1.1.1.1.cmml" xref="A1.T3.11.11.1.m1.1.1">subscript</csymbol><ci id="A1.T3.11.11.1.m1.1.1.2a.cmml" xref="A1.T3.11.11.1.m1.1.1.2"><mtext id="A1.T3.11.11.1.m1.1.1.2.cmml" xref="A1.T3.11.11.1.m1.1.1.2">S</mtext></ci><ci id="A1.T3.11.11.1.m1.1.1.3a.cmml" xref="A1.T3.11.11.1.m1.1.1.3"><mtext id="A1.T3.11.11.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.T3.11.11.1.m1.1.1.3">NVM</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.11.11.1.m1.1c">\text{S}_{\text{NVM}}</annotation><annotation encoding="application/x-llamapun" id="A1.T3.11.11.1.m1.1d">S start_POSTSUBSCRIPT NVM end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_td ltx_align_left" id="A1.T3.11.11.2">Total logical space used for the NVM Cache</td> </tr> <tr class="ltx_tr" id="A1.T3.12.12"> <td class="ltx_td ltx_align_left ltx_border_bb" id="A1.T3.12.12.1"><math alttext="\delta" class="ltx_Math" display="inline" id="A1.T3.12.12.1.m1.1"><semantics id="A1.T3.12.12.1.m1.1a"><mi id="A1.T3.12.12.1.m1.1.1" xref="A1.T3.12.12.1.m1.1.1.cmml">δ</mi><annotation-xml encoding="MathML-Content" id="A1.T3.12.12.1.m1.1b"><ci id="A1.T3.12.12.1.m1.1.1.cmml" xref="A1.T3.12.12.1.m1.1.1">𝛿</ci></annotation-xml><annotation encoding="application/x-tex" id="A1.T3.12.12.1.m1.1c">\delta</annotation><annotation encoding="application/x-llamapun" id="A1.T3.12.12.1.m1.1d">italic_δ</annotation></semantics></math></td> <td class="ltx_td ltx_align_left ltx_border_bb" id="A1.T3.12.12.2">Avg. live SOC bucket migrations due to GC</td> </tr> </table> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_table">Table 3. </span>System Variables</figcaption> </figure> </section> <section class="ltx_subsection" id="A1.SS2"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">A.2. </span>Derivation</h3> <div class="ltx_para" id="A1.SS2.p1"> <p class="ltx_p" id="A1.SS2.p1.1">We follow the same methodology as proposed in <cite class="ltx_cite ltx_citemacro_citep">(Dayan et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib31" title="">2015</a>)</cite> to model the DLWA of SOC writes in the SSD. The SOC DLWA equates to the overall CacheLib DLWA because the write amplification of LOC data after data segregation with FDP is <math alttext="\sim" class="ltx_Math" display="inline" id="A1.SS2.p1.1.m1.1"><semantics id="A1.SS2.p1.1.m1.1a"><mo id="A1.SS2.p1.1.m1.1.1" xref="A1.SS2.p1.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="A1.SS2.p1.1.m1.1b"><csymbol cd="latexml" id="A1.SS2.p1.1.m1.1.1.cmml" xref="A1.SS2.p1.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p1.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p1.1.m1.1d">∼</annotation></semantics></math>1.</p> </div> <div class="ltx_para" id="A1.SS2.p2"> <p class="ltx_p" id="A1.SS2.p2.2">The total number of SOC buckets can be calculated as:</p> <table class="ltx_equation ltx_eqn_table" id="A1.E3"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(3)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{N}_{\text{B}}=\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{Bucket}}}" class="ltx_Math" display="block" id="A1.E3.m1.1"><semantics id="A1.E3.m1.1a"><mrow id="A1.E3.m1.1.1" xref="A1.E3.m1.1.1.cmml"><msub id="A1.E3.m1.1.1.2" xref="A1.E3.m1.1.1.2.cmml"><mtext id="A1.E3.m1.1.1.2.2" xref="A1.E3.m1.1.1.2.2a.cmml">N</mtext><mtext id="A1.E3.m1.1.1.2.3" xref="A1.E3.m1.1.1.2.3a.cmml">B</mtext></msub><mo id="A1.E3.m1.1.1.1" xref="A1.E3.m1.1.1.1.cmml">=</mo><mfrac id="A1.E3.m1.1.1.3" xref="A1.E3.m1.1.1.3.cmml"><msub id="A1.E3.m1.1.1.3.2" xref="A1.E3.m1.1.1.3.2.cmml"><mtext id="A1.E3.m1.1.1.3.2.2" xref="A1.E3.m1.1.1.3.2.2a.cmml">S</mtext><mtext id="A1.E3.m1.1.1.3.2.3" xref="A1.E3.m1.1.1.3.2.3a.cmml">SOC</mtext></msub><msub id="A1.E3.m1.1.1.3.3" xref="A1.E3.m1.1.1.3.3.cmml"><mtext id="A1.E3.m1.1.1.3.3.2" xref="A1.E3.m1.1.1.3.3.2a.cmml">S</mtext><mtext id="A1.E3.m1.1.1.3.3.3" xref="A1.E3.m1.1.1.3.3.3a.cmml">Bucket</mtext></msub></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E3.m1.1b"><apply id="A1.E3.m1.1.1.cmml" xref="A1.E3.m1.1.1"><eq id="A1.E3.m1.1.1.1.cmml" xref="A1.E3.m1.1.1.1"></eq><apply id="A1.E3.m1.1.1.2.cmml" xref="A1.E3.m1.1.1.2"><csymbol cd="ambiguous" id="A1.E3.m1.1.1.2.1.cmml" xref="A1.E3.m1.1.1.2">subscript</csymbol><ci id="A1.E3.m1.1.1.2.2a.cmml" xref="A1.E3.m1.1.1.2.2"><mtext id="A1.E3.m1.1.1.2.2.cmml" xref="A1.E3.m1.1.1.2.2">N</mtext></ci><ci id="A1.E3.m1.1.1.2.3a.cmml" xref="A1.E3.m1.1.1.2.3"><mtext id="A1.E3.m1.1.1.2.3.cmml" mathsize="70%" xref="A1.E3.m1.1.1.2.3">B</mtext></ci></apply><apply id="A1.E3.m1.1.1.3.cmml" xref="A1.E3.m1.1.1.3"><divide id="A1.E3.m1.1.1.3.1.cmml" xref="A1.E3.m1.1.1.3"></divide><apply id="A1.E3.m1.1.1.3.2.cmml" xref="A1.E3.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E3.m1.1.1.3.2.1.cmml" xref="A1.E3.m1.1.1.3.2">subscript</csymbol><ci id="A1.E3.m1.1.1.3.2.2a.cmml" xref="A1.E3.m1.1.1.3.2.2"><mtext id="A1.E3.m1.1.1.3.2.2.cmml" xref="A1.E3.m1.1.1.3.2.2">S</mtext></ci><ci id="A1.E3.m1.1.1.3.2.3a.cmml" xref="A1.E3.m1.1.1.3.2.3"><mtext id="A1.E3.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E3.m1.1.1.3.2.3">SOC</mtext></ci></apply><apply id="A1.E3.m1.1.1.3.3.cmml" xref="A1.E3.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E3.m1.1.1.3.3.1.cmml" xref="A1.E3.m1.1.1.3.3">subscript</csymbol><ci id="A1.E3.m1.1.1.3.3.2a.cmml" xref="A1.E3.m1.1.1.3.3.2"><mtext id="A1.E3.m1.1.1.3.3.2.cmml" xref="A1.E3.m1.1.1.3.3.2">S</mtext></ci><ci id="A1.E3.m1.1.1.3.3.3a.cmml" xref="A1.E3.m1.1.1.3.3.3"><mtext id="A1.E3.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E3.m1.1.1.3.3.3">Bucket</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E3.m1.1c">\text{N}_{\text{B}}=\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{Bucket}}}</annotation><annotation encoding="application/x-llamapun" id="A1.E3.m1.1d">N start_POSTSUBSCRIPT B end_POSTSUBSCRIPT = divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT Bucket end_POSTSUBSCRIPT end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> <p class="ltx_p" id="A1.SS2.p2.1">Items are inserted into buckets using a % <math alttext="\text{N}_{\text{B}}" class="ltx_Math" display="inline" id="A1.SS2.p2.1.m1.1"><semantics id="A1.SS2.p2.1.m1.1a"><msub id="A1.SS2.p2.1.m1.1.1" xref="A1.SS2.p2.1.m1.1.1.cmml"><mtext id="A1.SS2.p2.1.m1.1.1.2" xref="A1.SS2.p2.1.m1.1.1.2a.cmml">N</mtext><mtext id="A1.SS2.p2.1.m1.1.1.3" xref="A1.SS2.p2.1.m1.1.1.3a.cmml">B</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.SS2.p2.1.m1.1b"><apply id="A1.SS2.p2.1.m1.1.1.cmml" xref="A1.SS2.p2.1.m1.1.1"><csymbol cd="ambiguous" id="A1.SS2.p2.1.m1.1.1.1.cmml" xref="A1.SS2.p2.1.m1.1.1">subscript</csymbol><ci id="A1.SS2.p2.1.m1.1.1.2a.cmml" xref="A1.SS2.p2.1.m1.1.1.2"><mtext id="A1.SS2.p2.1.m1.1.1.2.cmml" xref="A1.SS2.p2.1.m1.1.1.2">N</mtext></ci><ci id="A1.SS2.p2.1.m1.1.1.3a.cmml" xref="A1.SS2.p2.1.m1.1.1.3"><mtext id="A1.SS2.p2.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.SS2.p2.1.m1.1.1.3">B</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p2.1.m1.1c">\text{N}_{\text{B}}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p2.1.m1.1d">N start_POSTSUBSCRIPT B end_POSTSUBSCRIPT</annotation></semantics></math>. As the bucket size increases, the total number of SOC buckets reduces. <br class="ltx_break"/></p> </div> <div class="ltx_para" id="A1.SS2.p3"> <p class="ltx_p" id="A1.SS2.p3.1">The total physical space in the SSD can be given by:</p> <table class="ltx_equation ltx_eqn_table" id="A1.E4"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(4)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{S}_{\text{Total}}=\text{S}_{\text{Usable}}+\text{S}_{\text{OP}}" class="ltx_Math" display="block" id="A1.E4.m1.1"><semantics id="A1.E4.m1.1a"><mrow id="A1.E4.m1.1.1" xref="A1.E4.m1.1.1.cmml"><msub id="A1.E4.m1.1.1.2" xref="A1.E4.m1.1.1.2.cmml"><mtext id="A1.E4.m1.1.1.2.2" xref="A1.E4.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.E4.m1.1.1.2.3" xref="A1.E4.m1.1.1.2.3a.cmml">Total</mtext></msub><mo id="A1.E4.m1.1.1.1" xref="A1.E4.m1.1.1.1.cmml">=</mo><mrow id="A1.E4.m1.1.1.3" xref="A1.E4.m1.1.1.3.cmml"><msub id="A1.E4.m1.1.1.3.2" xref="A1.E4.m1.1.1.3.2.cmml"><mtext id="A1.E4.m1.1.1.3.2.2" xref="A1.E4.m1.1.1.3.2.2a.cmml">S</mtext><mtext id="A1.E4.m1.1.1.3.2.3" xref="A1.E4.m1.1.1.3.2.3a.cmml">Usable</mtext></msub><mo id="A1.E4.m1.1.1.3.1" xref="A1.E4.m1.1.1.3.1.cmml">+</mo><msub id="A1.E4.m1.1.1.3.3" xref="A1.E4.m1.1.1.3.3.cmml"><mtext id="A1.E4.m1.1.1.3.3.2" xref="A1.E4.m1.1.1.3.3.2a.cmml">S</mtext><mtext id="A1.E4.m1.1.1.3.3.3" xref="A1.E4.m1.1.1.3.3.3a.cmml">OP</mtext></msub></mrow></mrow><annotation-xml encoding="MathML-Content" id="A1.E4.m1.1b"><apply id="A1.E4.m1.1.1.cmml" xref="A1.E4.m1.1.1"><eq id="A1.E4.m1.1.1.1.cmml" xref="A1.E4.m1.1.1.1"></eq><apply id="A1.E4.m1.1.1.2.cmml" xref="A1.E4.m1.1.1.2"><csymbol cd="ambiguous" id="A1.E4.m1.1.1.2.1.cmml" xref="A1.E4.m1.1.1.2">subscript</csymbol><ci id="A1.E4.m1.1.1.2.2a.cmml" xref="A1.E4.m1.1.1.2.2"><mtext id="A1.E4.m1.1.1.2.2.cmml" xref="A1.E4.m1.1.1.2.2">S</mtext></ci><ci id="A1.E4.m1.1.1.2.3a.cmml" xref="A1.E4.m1.1.1.2.3"><mtext id="A1.E4.m1.1.1.2.3.cmml" mathsize="70%" xref="A1.E4.m1.1.1.2.3">Total</mtext></ci></apply><apply id="A1.E4.m1.1.1.3.cmml" xref="A1.E4.m1.1.1.3"><plus id="A1.E4.m1.1.1.3.1.cmml" xref="A1.E4.m1.1.1.3.1"></plus><apply id="A1.E4.m1.1.1.3.2.cmml" xref="A1.E4.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E4.m1.1.1.3.2.1.cmml" xref="A1.E4.m1.1.1.3.2">subscript</csymbol><ci id="A1.E4.m1.1.1.3.2.2a.cmml" xref="A1.E4.m1.1.1.3.2.2"><mtext id="A1.E4.m1.1.1.3.2.2.cmml" xref="A1.E4.m1.1.1.3.2.2">S</mtext></ci><ci id="A1.E4.m1.1.1.3.2.3a.cmml" xref="A1.E4.m1.1.1.3.2.3"><mtext id="A1.E4.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E4.m1.1.1.3.2.3">Usable</mtext></ci></apply><apply id="A1.E4.m1.1.1.3.3.cmml" xref="A1.E4.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E4.m1.1.1.3.3.1.cmml" xref="A1.E4.m1.1.1.3.3">subscript</csymbol><ci id="A1.E4.m1.1.1.3.3.2a.cmml" xref="A1.E4.m1.1.1.3.3.2"><mtext id="A1.E4.m1.1.1.3.3.2.cmml" xref="A1.E4.m1.1.1.3.3.2">S</mtext></ci><ci id="A1.E4.m1.1.1.3.3.3a.cmml" xref="A1.E4.m1.1.1.3.3.3"><mtext id="A1.E4.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E4.m1.1.1.3.3.3">OP</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E4.m1.1c">\text{S}_{\text{Total}}=\text{S}_{\text{Usable}}+\text{S}_{\text{OP}}</annotation><annotation encoding="application/x-llamapun" id="A1.E4.m1.1d">S start_POSTSUBSCRIPT Total end_POSTSUBSCRIPT = S start_POSTSUBSCRIPT Usable end_POSTSUBSCRIPT + S start_POSTSUBSCRIPT OP end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p4"> <p class="ltx_p" id="A1.SS2.p4.1">We assume that LOC data will use <math alttext="\sim" class="ltx_Math" display="inline" id="A1.SS2.p4.1.m1.1"><semantics id="A1.SS2.p4.1.m1.1a"><mo id="A1.SS2.p4.1.m1.1.1" xref="A1.SS2.p4.1.m1.1.1.cmml">∼</mo><annotation-xml encoding="MathML-Content" id="A1.SS2.p4.1.m1.1b"><csymbol cd="latexml" id="A1.SS2.p4.1.m1.1.1.cmml" xref="A1.SS2.p4.1.m1.1.1">similar-to</csymbol></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p4.1.m1.1c">\sim</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p4.1.m1.1d">∼</annotation></semantics></math>0 OP space, i.e.</p> <table class="ltx_equation ltx_eqn_table" id="A1.E5"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(5)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{S}_{\text{LOC}}=\text{S}_{\text{P-LOC}}" class="ltx_Math" display="block" id="A1.E5.m1.1"><semantics id="A1.E5.m1.1a"><mrow id="A1.E5.m1.1.1" xref="A1.E5.m1.1.1.cmml"><msub id="A1.E5.m1.1.1.2" xref="A1.E5.m1.1.1.2.cmml"><mtext id="A1.E5.m1.1.1.2.2" xref="A1.E5.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.E5.m1.1.1.2.3" xref="A1.E5.m1.1.1.2.3a.cmml">LOC</mtext></msub><mo id="A1.E5.m1.1.1.1" xref="A1.E5.m1.1.1.1.cmml">=</mo><msub id="A1.E5.m1.1.1.3" xref="A1.E5.m1.1.1.3.cmml"><mtext id="A1.E5.m1.1.1.3.2" xref="A1.E5.m1.1.1.3.2a.cmml">S</mtext><mtext id="A1.E5.m1.1.1.3.3" xref="A1.E5.m1.1.1.3.3a.cmml">P-LOC</mtext></msub></mrow><annotation-xml encoding="MathML-Content" id="A1.E5.m1.1b"><apply id="A1.E5.m1.1.1.cmml" xref="A1.E5.m1.1.1"><eq id="A1.E5.m1.1.1.1.cmml" xref="A1.E5.m1.1.1.1"></eq><apply id="A1.E5.m1.1.1.2.cmml" xref="A1.E5.m1.1.1.2"><csymbol cd="ambiguous" id="A1.E5.m1.1.1.2.1.cmml" xref="A1.E5.m1.1.1.2">subscript</csymbol><ci id="A1.E5.m1.1.1.2.2a.cmml" xref="A1.E5.m1.1.1.2.2"><mtext id="A1.E5.m1.1.1.2.2.cmml" xref="A1.E5.m1.1.1.2.2">S</mtext></ci><ci id="A1.E5.m1.1.1.2.3a.cmml" xref="A1.E5.m1.1.1.2.3"><mtext id="A1.E5.m1.1.1.2.3.cmml" mathsize="70%" xref="A1.E5.m1.1.1.2.3">LOC</mtext></ci></apply><apply id="A1.E5.m1.1.1.3.cmml" xref="A1.E5.m1.1.1.3"><csymbol cd="ambiguous" id="A1.E5.m1.1.1.3.1.cmml" xref="A1.E5.m1.1.1.3">subscript</csymbol><ci id="A1.E5.m1.1.1.3.2a.cmml" xref="A1.E5.m1.1.1.3.2"><mtext id="A1.E5.m1.1.1.3.2.cmml" xref="A1.E5.m1.1.1.3.2">S</mtext></ci><ci id="A1.E5.m1.1.1.3.3a.cmml" xref="A1.E5.m1.1.1.3.3"><mtext id="A1.E5.m1.1.1.3.3.cmml" mathsize="70%" xref="A1.E5.m1.1.1.3.3">P-LOC</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E5.m1.1c">\text{S}_{\text{LOC}}=\text{S}_{\text{P-LOC}}</annotation><annotation encoding="application/x-llamapun" id="A1.E5.m1.1d">S start_POSTSUBSCRIPT LOC end_POSTSUBSCRIPT = S start_POSTSUBSCRIPT P-LOC end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p5"> <p class="ltx_p" id="A1.SS2.p5.1">Using Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E4" title="Equation 4 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4</span></a> and Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E5" title="Equation 5 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">5</span></a>, and assuming the entire usable space will make up the NVM Cache capacity (i.e. no host overprovisioning),</p> </div> <div class="ltx_para" id="A1.SS2.p6"> <table class="ltx_equation ltx_eqn_table" id="A1.E6"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(6)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{S}_{\text{P-SOC}}=\text{S}_{\text{SOC}}+\text{S}_{\text{OP}}" class="ltx_Math" display="block" id="A1.E6.m1.1"><semantics id="A1.E6.m1.1a"><mrow id="A1.E6.m1.1.1" xref="A1.E6.m1.1.1.cmml"><msub id="A1.E6.m1.1.1.2" xref="A1.E6.m1.1.1.2.cmml"><mtext id="A1.E6.m1.1.1.2.2" xref="A1.E6.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.E6.m1.1.1.2.3" xref="A1.E6.m1.1.1.2.3a.cmml">P-SOC</mtext></msub><mo id="A1.E6.m1.1.1.1" xref="A1.E6.m1.1.1.1.cmml">=</mo><mrow id="A1.E6.m1.1.1.3" xref="A1.E6.m1.1.1.3.cmml"><msub id="A1.E6.m1.1.1.3.2" xref="A1.E6.m1.1.1.3.2.cmml"><mtext id="A1.E6.m1.1.1.3.2.2" xref="A1.E6.m1.1.1.3.2.2a.cmml">S</mtext><mtext id="A1.E6.m1.1.1.3.2.3" xref="A1.E6.m1.1.1.3.2.3a.cmml">SOC</mtext></msub><mo id="A1.E6.m1.1.1.3.1" xref="A1.E6.m1.1.1.3.1.cmml">+</mo><msub id="A1.E6.m1.1.1.3.3" xref="A1.E6.m1.1.1.3.3.cmml"><mtext id="A1.E6.m1.1.1.3.3.2" xref="A1.E6.m1.1.1.3.3.2a.cmml">S</mtext><mtext id="A1.E6.m1.1.1.3.3.3" xref="A1.E6.m1.1.1.3.3.3a.cmml">OP</mtext></msub></mrow></mrow><annotation-xml encoding="MathML-Content" id="A1.E6.m1.1b"><apply id="A1.E6.m1.1.1.cmml" xref="A1.E6.m1.1.1"><eq id="A1.E6.m1.1.1.1.cmml" xref="A1.E6.m1.1.1.1"></eq><apply id="A1.E6.m1.1.1.2.cmml" xref="A1.E6.m1.1.1.2"><csymbol cd="ambiguous" id="A1.E6.m1.1.1.2.1.cmml" xref="A1.E6.m1.1.1.2">subscript</csymbol><ci id="A1.E6.m1.1.1.2.2a.cmml" xref="A1.E6.m1.1.1.2.2"><mtext id="A1.E6.m1.1.1.2.2.cmml" xref="A1.E6.m1.1.1.2.2">S</mtext></ci><ci id="A1.E6.m1.1.1.2.3a.cmml" xref="A1.E6.m1.1.1.2.3"><mtext id="A1.E6.m1.1.1.2.3.cmml" mathsize="70%" xref="A1.E6.m1.1.1.2.3">P-SOC</mtext></ci></apply><apply id="A1.E6.m1.1.1.3.cmml" xref="A1.E6.m1.1.1.3"><plus id="A1.E6.m1.1.1.3.1.cmml" xref="A1.E6.m1.1.1.3.1"></plus><apply id="A1.E6.m1.1.1.3.2.cmml" xref="A1.E6.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E6.m1.1.1.3.2.1.cmml" xref="A1.E6.m1.1.1.3.2">subscript</csymbol><ci id="A1.E6.m1.1.1.3.2.2a.cmml" xref="A1.E6.m1.1.1.3.2.2"><mtext id="A1.E6.m1.1.1.3.2.2.cmml" xref="A1.E6.m1.1.1.3.2.2">S</mtext></ci><ci id="A1.E6.m1.1.1.3.2.3a.cmml" xref="A1.E6.m1.1.1.3.2.3"><mtext id="A1.E6.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E6.m1.1.1.3.2.3">SOC</mtext></ci></apply><apply id="A1.E6.m1.1.1.3.3.cmml" xref="A1.E6.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E6.m1.1.1.3.3.1.cmml" xref="A1.E6.m1.1.1.3.3">subscript</csymbol><ci id="A1.E6.m1.1.1.3.3.2a.cmml" xref="A1.E6.m1.1.1.3.3.2"><mtext id="A1.E6.m1.1.1.3.3.2.cmml" xref="A1.E6.m1.1.1.3.3.2">S</mtext></ci><ci id="A1.E6.m1.1.1.3.3.3a.cmml" xref="A1.E6.m1.1.1.3.3.3"><mtext id="A1.E6.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E6.m1.1.1.3.3.3">OP</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E6.m1.1c">\text{S}_{\text{P-SOC}}=\text{S}_{\text{SOC}}+\text{S}_{\text{OP}}</annotation><annotation encoding="application/x-llamapun" id="A1.E6.m1.1d">S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT = S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT + S start_POSTSUBSCRIPT OP end_POSTSUBSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p7"> <p class="ltx_p" id="A1.SS2.p7.2">The LBA space of the SOC data i.e. <math alttext="\text{S}_{\text{SOC}}" class="ltx_Math" display="inline" id="A1.SS2.p7.1.m1.1"><semantics id="A1.SS2.p7.1.m1.1a"><msub id="A1.SS2.p7.1.m1.1.1" xref="A1.SS2.p7.1.m1.1.1.cmml"><mtext id="A1.SS2.p7.1.m1.1.1.2" xref="A1.SS2.p7.1.m1.1.1.2a.cmml">S</mtext><mtext id="A1.SS2.p7.1.m1.1.1.3" xref="A1.SS2.p7.1.m1.1.1.3a.cmml">SOC</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.SS2.p7.1.m1.1b"><apply id="A1.SS2.p7.1.m1.1.1.cmml" xref="A1.SS2.p7.1.m1.1.1"><csymbol cd="ambiguous" id="A1.SS2.p7.1.m1.1.1.1.cmml" xref="A1.SS2.p7.1.m1.1.1">subscript</csymbol><ci id="A1.SS2.p7.1.m1.1.1.2a.cmml" xref="A1.SS2.p7.1.m1.1.1.2"><mtext id="A1.SS2.p7.1.m1.1.1.2.cmml" xref="A1.SS2.p7.1.m1.1.1.2">S</mtext></ci><ci id="A1.SS2.p7.1.m1.1.1.3a.cmml" xref="A1.SS2.p7.1.m1.1.1.3"><mtext id="A1.SS2.p7.1.m1.1.1.3.cmml" mathsize="70%" xref="A1.SS2.p7.1.m1.1.1.3">SOC</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p7.1.m1.1c">\text{S}_{\text{SOC}}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p7.1.m1.1d">S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT</annotation></semantics></math> is uniformly distributed. We assume that the number of SOC buckets in an erase block is <math alttext="\text{N}_{\text{BB}}" class="ltx_Math" display="inline" id="A1.SS2.p7.2.m2.1"><semantics id="A1.SS2.p7.2.m2.1a"><msub id="A1.SS2.p7.2.m2.1.1" xref="A1.SS2.p7.2.m2.1.1.cmml"><mtext id="A1.SS2.p7.2.m2.1.1.2" xref="A1.SS2.p7.2.m2.1.1.2a.cmml">N</mtext><mtext id="A1.SS2.p7.2.m2.1.1.3" xref="A1.SS2.p7.2.m2.1.1.3a.cmml">BB</mtext></msub><annotation-xml encoding="MathML-Content" id="A1.SS2.p7.2.m2.1b"><apply id="A1.SS2.p7.2.m2.1.1.cmml" xref="A1.SS2.p7.2.m2.1.1"><csymbol cd="ambiguous" id="A1.SS2.p7.2.m2.1.1.1.cmml" xref="A1.SS2.p7.2.m2.1.1">subscript</csymbol><ci id="A1.SS2.p7.2.m2.1.1.2a.cmml" xref="A1.SS2.p7.2.m2.1.1.2"><mtext id="A1.SS2.p7.2.m2.1.1.2.cmml" xref="A1.SS2.p7.2.m2.1.1.2">N</mtext></ci><ci id="A1.SS2.p7.2.m2.1.1.3a.cmml" xref="A1.SS2.p7.2.m2.1.1.3"><mtext id="A1.SS2.p7.2.m2.1.1.3.cmml" mathsize="70%" xref="A1.SS2.p7.2.m2.1.1.3">BB</mtext></ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p7.2.m2.1c">\text{N}_{\text{BB}}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p7.2.m2.1d">N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT</annotation></semantics></math>. Then, it follows that after X SOC insertions the probability that a particular SOC bucket gets updated in an erase block is:</p> <table class="ltx_equation ltx_eqn_table" id="A1.E7"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(7)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{p(SOC bucket rewrite)}=\frac{\text{N}_{\text{BB}}}{\text{S}_{\text{SOC}}}" class="ltx_Math" display="block" id="A1.E7.m1.1"><semantics id="A1.E7.m1.1a"><mrow id="A1.E7.m1.1.1" xref="A1.E7.m1.1.1.cmml"><mtext id="A1.E7.m1.1.1.2" xref="A1.E7.m1.1.1.2a.cmml">p(SOC bucket rewrite)</mtext><mo id="A1.E7.m1.1.1.1" xref="A1.E7.m1.1.1.1.cmml">=</mo><mfrac id="A1.E7.m1.1.1.3" xref="A1.E7.m1.1.1.3.cmml"><msub id="A1.E7.m1.1.1.3.2" xref="A1.E7.m1.1.1.3.2.cmml"><mtext id="A1.E7.m1.1.1.3.2.2" xref="A1.E7.m1.1.1.3.2.2a.cmml">N</mtext><mtext id="A1.E7.m1.1.1.3.2.3" xref="A1.E7.m1.1.1.3.2.3a.cmml">BB</mtext></msub><msub id="A1.E7.m1.1.1.3.3" xref="A1.E7.m1.1.1.3.3.cmml"><mtext id="A1.E7.m1.1.1.3.3.2" xref="A1.E7.m1.1.1.3.3.2a.cmml">S</mtext><mtext id="A1.E7.m1.1.1.3.3.3" xref="A1.E7.m1.1.1.3.3.3a.cmml">SOC</mtext></msub></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E7.m1.1b"><apply id="A1.E7.m1.1.1.cmml" xref="A1.E7.m1.1.1"><eq id="A1.E7.m1.1.1.1.cmml" xref="A1.E7.m1.1.1.1"></eq><ci id="A1.E7.m1.1.1.2a.cmml" xref="A1.E7.m1.1.1.2"><mtext id="A1.E7.m1.1.1.2.cmml" xref="A1.E7.m1.1.1.2">p(SOC bucket rewrite)</mtext></ci><apply id="A1.E7.m1.1.1.3.cmml" xref="A1.E7.m1.1.1.3"><divide id="A1.E7.m1.1.1.3.1.cmml" xref="A1.E7.m1.1.1.3"></divide><apply id="A1.E7.m1.1.1.3.2.cmml" xref="A1.E7.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E7.m1.1.1.3.2.1.cmml" xref="A1.E7.m1.1.1.3.2">subscript</csymbol><ci id="A1.E7.m1.1.1.3.2.2a.cmml" xref="A1.E7.m1.1.1.3.2.2"><mtext id="A1.E7.m1.1.1.3.2.2.cmml" xref="A1.E7.m1.1.1.3.2.2">N</mtext></ci><ci id="A1.E7.m1.1.1.3.2.3a.cmml" xref="A1.E7.m1.1.1.3.2.3"><mtext id="A1.E7.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E7.m1.1.1.3.2.3">BB</mtext></ci></apply><apply id="A1.E7.m1.1.1.3.3.cmml" xref="A1.E7.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E7.m1.1.1.3.3.1.cmml" xref="A1.E7.m1.1.1.3.3">subscript</csymbol><ci id="A1.E7.m1.1.1.3.3.2a.cmml" xref="A1.E7.m1.1.1.3.3.2"><mtext id="A1.E7.m1.1.1.3.3.2.cmml" xref="A1.E7.m1.1.1.3.3.2">S</mtext></ci><ci id="A1.E7.m1.1.1.3.3.3a.cmml" xref="A1.E7.m1.1.1.3.3.3"><mtext id="A1.E7.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E7.m1.1.1.3.3.3">SOC</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E7.m1.1c">\text{p(SOC bucket rewrite)}=\frac{\text{N}_{\text{BB}}}{\text{S}_{\text{SOC}}}</annotation><annotation encoding="application/x-llamapun" id="A1.E7.m1.1d">p(SOC bucket rewrite) = divide start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p8"> <p class="ltx_p" id="A1.SS2.p8.1">This follows a geometric distribution. This is similar to other DLWA modelling work done before <cite class="ltx_cite ltx_citemacro_citep">(Dayan et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib31" title="">2015</a>)</cite>. In a geometric distribution, after X trials we get a success of a particular bucket getting overwritten or updated. In a geometric distribution, the mean is <math alttext="\frac{1}{p}" class="ltx_Math" display="inline" id="A1.SS2.p8.1.m1.1"><semantics id="A1.SS2.p8.1.m1.1a"><mfrac id="A1.SS2.p8.1.m1.1.1" xref="A1.SS2.p8.1.m1.1.1.cmml"><mn id="A1.SS2.p8.1.m1.1.1.2" xref="A1.SS2.p8.1.m1.1.1.2.cmml">1</mn><mi id="A1.SS2.p8.1.m1.1.1.3" xref="A1.SS2.p8.1.m1.1.1.3.cmml">p</mi></mfrac><annotation-xml encoding="MathML-Content" id="A1.SS2.p8.1.m1.1b"><apply id="A1.SS2.p8.1.m1.1.1.cmml" xref="A1.SS2.p8.1.m1.1.1"><divide id="A1.SS2.p8.1.m1.1.1.1.cmml" xref="A1.SS2.p8.1.m1.1.1"></divide><cn id="A1.SS2.p8.1.m1.1.1.2.cmml" type="integer" xref="A1.SS2.p8.1.m1.1.1.2">1</cn><ci id="A1.SS2.p8.1.m1.1.1.3.cmml" xref="A1.SS2.p8.1.m1.1.1.3">𝑝</ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p8.1.m1.1c">\frac{1}{p}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p8.1.m1.1d">divide start_ARG 1 end_ARG start_ARG italic_p end_ARG</annotation></semantics></math>. So,</p> </div> <div class="ltx_para" id="A1.SS2.p9"> <table class="ltx_equation ltx_eqn_table" id="A1.E8"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(8)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\mu=\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}" class="ltx_Math" display="block" id="A1.E8.m1.1"><semantics id="A1.E8.m1.1a"><mrow id="A1.E8.m1.1.1" xref="A1.E8.m1.1.1.cmml"><mi id="A1.E8.m1.1.1.2" xref="A1.E8.m1.1.1.2.cmml">μ</mi><mo id="A1.E8.m1.1.1.1" xref="A1.E8.m1.1.1.1.cmml">=</mo><mfrac id="A1.E8.m1.1.1.3" xref="A1.E8.m1.1.1.3.cmml"><msub id="A1.E8.m1.1.1.3.2" xref="A1.E8.m1.1.1.3.2.cmml"><mtext id="A1.E8.m1.1.1.3.2.2" xref="A1.E8.m1.1.1.3.2.2a.cmml">S</mtext><mtext id="A1.E8.m1.1.1.3.2.3" xref="A1.E8.m1.1.1.3.2.3a.cmml">SOC</mtext></msub><msub id="A1.E8.m1.1.1.3.3" xref="A1.E8.m1.1.1.3.3.cmml"><mtext id="A1.E8.m1.1.1.3.3.2" xref="A1.E8.m1.1.1.3.3.2a.cmml">N</mtext><mtext id="A1.E8.m1.1.1.3.3.3" xref="A1.E8.m1.1.1.3.3.3a.cmml">BB</mtext></msub></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E8.m1.1b"><apply id="A1.E8.m1.1.1.cmml" xref="A1.E8.m1.1.1"><eq id="A1.E8.m1.1.1.1.cmml" xref="A1.E8.m1.1.1.1"></eq><ci id="A1.E8.m1.1.1.2.cmml" xref="A1.E8.m1.1.1.2">𝜇</ci><apply id="A1.E8.m1.1.1.3.cmml" xref="A1.E8.m1.1.1.3"><divide id="A1.E8.m1.1.1.3.1.cmml" xref="A1.E8.m1.1.1.3"></divide><apply id="A1.E8.m1.1.1.3.2.cmml" xref="A1.E8.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E8.m1.1.1.3.2.1.cmml" xref="A1.E8.m1.1.1.3.2">subscript</csymbol><ci id="A1.E8.m1.1.1.3.2.2a.cmml" xref="A1.E8.m1.1.1.3.2.2"><mtext id="A1.E8.m1.1.1.3.2.2.cmml" xref="A1.E8.m1.1.1.3.2.2">S</mtext></ci><ci id="A1.E8.m1.1.1.3.2.3a.cmml" xref="A1.E8.m1.1.1.3.2.3"><mtext id="A1.E8.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E8.m1.1.1.3.2.3">SOC</mtext></ci></apply><apply id="A1.E8.m1.1.1.3.3.cmml" xref="A1.E8.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E8.m1.1.1.3.3.1.cmml" xref="A1.E8.m1.1.1.3.3">subscript</csymbol><ci id="A1.E8.m1.1.1.3.3.2a.cmml" xref="A1.E8.m1.1.1.3.3.2"><mtext id="A1.E8.m1.1.1.3.3.2.cmml" xref="A1.E8.m1.1.1.3.3.2">N</mtext></ci><ci id="A1.E8.m1.1.1.3.3.3a.cmml" xref="A1.E8.m1.1.1.3.3.3"><mtext id="A1.E8.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E8.m1.1.1.3.3.3">BB</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E8.m1.1c">\mu=\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}</annotation><annotation encoding="application/x-llamapun" id="A1.E8.m1.1d">italic_μ = divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p10"> <p class="ltx_p" id="A1.SS2.p10.2">Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E8" title="Equation 8 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">8</span></a> is analogous to saying that on average after <math alttext="\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}" class="ltx_Math" display="inline" id="A1.SS2.p10.1.m1.1"><semantics id="A1.SS2.p10.1.m1.1a"><mfrac id="A1.SS2.p10.1.m1.1.1" xref="A1.SS2.p10.1.m1.1.1.cmml"><msub id="A1.SS2.p10.1.m1.1.1.2" xref="A1.SS2.p10.1.m1.1.1.2.cmml"><mtext id="A1.SS2.p10.1.m1.1.1.2.2" xref="A1.SS2.p10.1.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.SS2.p10.1.m1.1.1.2.3" xref="A1.SS2.p10.1.m1.1.1.2.3a.cmml">SOC</mtext></msub><msub id="A1.SS2.p10.1.m1.1.1.3" xref="A1.SS2.p10.1.m1.1.1.3.cmml"><mtext id="A1.SS2.p10.1.m1.1.1.3.2" xref="A1.SS2.p10.1.m1.1.1.3.2a.cmml">N</mtext><mtext id="A1.SS2.p10.1.m1.1.1.3.3" xref="A1.SS2.p10.1.m1.1.1.3.3a.cmml">BB</mtext></msub></mfrac><annotation-xml encoding="MathML-Content" id="A1.SS2.p10.1.m1.1b"><apply id="A1.SS2.p10.1.m1.1.1.cmml" xref="A1.SS2.p10.1.m1.1.1"><divide id="A1.SS2.p10.1.m1.1.1.1.cmml" xref="A1.SS2.p10.1.m1.1.1"></divide><apply id="A1.SS2.p10.1.m1.1.1.2.cmml" xref="A1.SS2.p10.1.m1.1.1.2"><csymbol cd="ambiguous" id="A1.SS2.p10.1.m1.1.1.2.1.cmml" xref="A1.SS2.p10.1.m1.1.1.2">subscript</csymbol><ci id="A1.SS2.p10.1.m1.1.1.2.2a.cmml" xref="A1.SS2.p10.1.m1.1.1.2.2"><mtext id="A1.SS2.p10.1.m1.1.1.2.2.cmml" mathsize="70%" xref="A1.SS2.p10.1.m1.1.1.2.2">S</mtext></ci><ci id="A1.SS2.p10.1.m1.1.1.2.3a.cmml" xref="A1.SS2.p10.1.m1.1.1.2.3"><mtext id="A1.SS2.p10.1.m1.1.1.2.3.cmml" mathsize="50%" xref="A1.SS2.p10.1.m1.1.1.2.3">SOC</mtext></ci></apply><apply id="A1.SS2.p10.1.m1.1.1.3.cmml" xref="A1.SS2.p10.1.m1.1.1.3"><csymbol cd="ambiguous" id="A1.SS2.p10.1.m1.1.1.3.1.cmml" xref="A1.SS2.p10.1.m1.1.1.3">subscript</csymbol><ci id="A1.SS2.p10.1.m1.1.1.3.2a.cmml" xref="A1.SS2.p10.1.m1.1.1.3.2"><mtext id="A1.SS2.p10.1.m1.1.1.3.2.cmml" mathsize="70%" xref="A1.SS2.p10.1.m1.1.1.3.2">N</mtext></ci><ci id="A1.SS2.p10.1.m1.1.1.3.3a.cmml" xref="A1.SS2.p10.1.m1.1.1.3.3"><mtext id="A1.SS2.p10.1.m1.1.1.3.3.cmml" mathsize="50%" xref="A1.SS2.p10.1.m1.1.1.3.3">BB</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p10.1.m1.1c">\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p10.1.m1.1d">divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG</annotation></semantics></math> updates/SOC writes, the first SOC bucket gets overwritten in a particular erase block. Similarly, the second SOC bucket gets overwritten after <math alttext="\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}-1}" class="ltx_Math" display="inline" id="A1.SS2.p10.2.m2.1"><semantics id="A1.SS2.p10.2.m2.1a"><mfrac id="A1.SS2.p10.2.m2.1.1" xref="A1.SS2.p10.2.m2.1.1.cmml"><msub id="A1.SS2.p10.2.m2.1.1.2" xref="A1.SS2.p10.2.m2.1.1.2.cmml"><mtext id="A1.SS2.p10.2.m2.1.1.2.2" xref="A1.SS2.p10.2.m2.1.1.2.2a.cmml">S</mtext><mtext id="A1.SS2.p10.2.m2.1.1.2.3" xref="A1.SS2.p10.2.m2.1.1.2.3a.cmml">SOC</mtext></msub><mrow id="A1.SS2.p10.2.m2.1.1.3" xref="A1.SS2.p10.2.m2.1.1.3.cmml"><msub id="A1.SS2.p10.2.m2.1.1.3.2" xref="A1.SS2.p10.2.m2.1.1.3.2.cmml"><mtext id="A1.SS2.p10.2.m2.1.1.3.2.2" xref="A1.SS2.p10.2.m2.1.1.3.2.2a.cmml">N</mtext><mtext id="A1.SS2.p10.2.m2.1.1.3.2.3" xref="A1.SS2.p10.2.m2.1.1.3.2.3a.cmml">BB</mtext></msub><mo id="A1.SS2.p10.2.m2.1.1.3.1" xref="A1.SS2.p10.2.m2.1.1.3.1.cmml">−</mo><mn id="A1.SS2.p10.2.m2.1.1.3.3" xref="A1.SS2.p10.2.m2.1.1.3.3.cmml">1</mn></mrow></mfrac><annotation-xml encoding="MathML-Content" id="A1.SS2.p10.2.m2.1b"><apply id="A1.SS2.p10.2.m2.1.1.cmml" xref="A1.SS2.p10.2.m2.1.1"><divide id="A1.SS2.p10.2.m2.1.1.1.cmml" xref="A1.SS2.p10.2.m2.1.1"></divide><apply id="A1.SS2.p10.2.m2.1.1.2.cmml" xref="A1.SS2.p10.2.m2.1.1.2"><csymbol cd="ambiguous" id="A1.SS2.p10.2.m2.1.1.2.1.cmml" xref="A1.SS2.p10.2.m2.1.1.2">subscript</csymbol><ci id="A1.SS2.p10.2.m2.1.1.2.2a.cmml" xref="A1.SS2.p10.2.m2.1.1.2.2"><mtext id="A1.SS2.p10.2.m2.1.1.2.2.cmml" mathsize="70%" xref="A1.SS2.p10.2.m2.1.1.2.2">S</mtext></ci><ci id="A1.SS2.p10.2.m2.1.1.2.3a.cmml" xref="A1.SS2.p10.2.m2.1.1.2.3"><mtext id="A1.SS2.p10.2.m2.1.1.2.3.cmml" mathsize="50%" xref="A1.SS2.p10.2.m2.1.1.2.3">SOC</mtext></ci></apply><apply id="A1.SS2.p10.2.m2.1.1.3.cmml" xref="A1.SS2.p10.2.m2.1.1.3"><minus id="A1.SS2.p10.2.m2.1.1.3.1.cmml" xref="A1.SS2.p10.2.m2.1.1.3.1"></minus><apply id="A1.SS2.p10.2.m2.1.1.3.2.cmml" xref="A1.SS2.p10.2.m2.1.1.3.2"><csymbol cd="ambiguous" id="A1.SS2.p10.2.m2.1.1.3.2.1.cmml" xref="A1.SS2.p10.2.m2.1.1.3.2">subscript</csymbol><ci id="A1.SS2.p10.2.m2.1.1.3.2.2a.cmml" xref="A1.SS2.p10.2.m2.1.1.3.2.2"><mtext id="A1.SS2.p10.2.m2.1.1.3.2.2.cmml" mathsize="70%" xref="A1.SS2.p10.2.m2.1.1.3.2.2">N</mtext></ci><ci id="A1.SS2.p10.2.m2.1.1.3.2.3a.cmml" xref="A1.SS2.p10.2.m2.1.1.3.2.3"><mtext id="A1.SS2.p10.2.m2.1.1.3.2.3.cmml" mathsize="50%" xref="A1.SS2.p10.2.m2.1.1.3.2.3">BB</mtext></ci></apply><cn id="A1.SS2.p10.2.m2.1.1.3.3.cmml" type="integer" xref="A1.SS2.p10.2.m2.1.1.3.3">1</cn></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p10.2.m2.1c">\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}-1}</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p10.2.m2.1d">divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT - 1 end_ARG</annotation></semantics></math> SOC inserts on average, and so on. <br class="ltx_break"/>It follows that the number of updates after which there are no SOC buckets yet to be overwritten is,</p> </div> <div class="ltx_para" id="A1.SS2.p11"> <table class="ltx_equation ltx_eqn_table" id="A1.E9"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(9)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}+\frac{\text{S}_{\text{SOC}}% }{\text{N}_{\text{BB}}-1}+\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}-2}% +...+\frac{\text{S}_{\text{SOC}}}{1}" class="ltx_Math" display="block" id="A1.E9.m1.1"><semantics id="A1.E9.m1.1a"><mrow id="A1.E9.m1.1.1" xref="A1.E9.m1.1.1.cmml"><mfrac id="A1.E9.m1.1.1.2" xref="A1.E9.m1.1.1.2.cmml"><msub id="A1.E9.m1.1.1.2.2" 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xref="A1.E9.m1.1.1.6.3">1</cn></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E9.m1.1c">\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}}+\frac{\text{S}_{\text{SOC}}% }{\text{N}_{\text{BB}}-1}+\frac{\text{S}_{\text{SOC}}}{\text{N}_{\text{BB}}-2}% +...+\frac{\text{S}_{\text{SOC}}}{1}</annotation><annotation encoding="application/x-llamapun" id="A1.E9.m1.1d">divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG + divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT - 1 end_ARG + divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT - 2 end_ARG + … + divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG 1 end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p12"> <p class="ltx_p" id="A1.SS2.p12.1">This harmonic series can be simplified using Euler’s approximation.</p> <table class="ltx_equation ltx_eqn_table" id="A1.E10"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(10)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{X}=\text{S}_{\text{SOC}}\sum_{i=1}^{\text{N}_{\text{BB}}}\frac{1}{i}" class="ltx_Math" display="block" id="A1.E10.m1.1"><semantics id="A1.E10.m1.1a"><mrow id="A1.E10.m1.1.1" xref="A1.E10.m1.1.1.cmml"><mtext id="A1.E10.m1.1.1.2" xref="A1.E10.m1.1.1.2a.cmml">X</mtext><mo id="A1.E10.m1.1.1.1" xref="A1.E10.m1.1.1.1.cmml">=</mo><mrow id="A1.E10.m1.1.1.3" xref="A1.E10.m1.1.1.3.cmml"><msub id="A1.E10.m1.1.1.3.2" xref="A1.E10.m1.1.1.3.2.cmml"><mtext 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id="A1.E10.m1.1c">\text{X}=\text{S}_{\text{SOC}}\sum_{i=1}^{\text{N}_{\text{BB}}}\frac{1}{i}</annotation><annotation encoding="application/x-llamapun" id="A1.E10.m1.1d">X = S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT ∑ start_POSTSUBSCRIPT italic_i = 1 end_POSTSUBSCRIPT start_POSTSUPERSCRIPT N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_POSTSUPERSCRIPT divide start_ARG 1 end_ARG start_ARG italic_i end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p13"> <p class="ltx_p" id="A1.SS2.p13.1">If <span class="ltx_text ltx_markedasmath" id="A1.SS2.p13.1.1">L</span> SOC buckets are yet to be overwritten on average in an erase block after X SOC insertions. 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xref="A1.E11.m1.1.1.3.3.3.1.3">𝐿</ci></apply><apply id="A1.E11.m1.1.1.3.3.3.2.cmml" xref="A1.E11.m1.1.1.3.3.3.2"><divide id="A1.E11.m1.1.1.3.3.3.2.1.cmml" xref="A1.E11.m1.1.1.3.3.3.2"></divide><cn id="A1.E11.m1.1.1.3.3.3.2.2.cmml" type="integer" xref="A1.E11.m1.1.1.3.3.3.2.2">1</cn><ci id="A1.E11.m1.1.1.3.3.3.2.3.cmml" xref="A1.E11.m1.1.1.3.3.3.2.3">𝑖</ci></apply></apply></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E11.m1.1c">\text{X}=\text{S}_{\text{SOC}}\sum_{i=1}^{\text{N}_{\text{BB}}}\frac{1}{i}-% \text{S}_{\text{SOC}}\sum_{i=1}^{L}\frac{1}{i}</annotation><annotation encoding="application/x-llamapun" id="A1.E11.m1.1d">X = S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT ∑ start_POSTSUBSCRIPT italic_i = 1 end_POSTSUBSCRIPT start_POSTSUPERSCRIPT N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_POSTSUPERSCRIPT divide start_ARG 1 end_ARG start_ARG italic_i end_ARG - S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT ∑ start_POSTSUBSCRIPT italic_i = 1 end_POSTSUBSCRIPT start_POSTSUPERSCRIPT italic_L end_POSTSUPERSCRIPT divide start_ARG 1 end_ARG start_ARG italic_i end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p14"> <p class="ltx_p" id="A1.SS2.p14.1">This can be expressed as:</p> <table class="ltx_equation ltx_eqn_table" id="A1.E12"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(12)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{L}=\text{N}_{\text{BB}}e^{-X/\text{S}_{\text{SOC}}}" class="ltx_Math" display="block" id="A1.E12.m1.1"><semantics id="A1.E12.m1.1a"><mrow id="A1.E12.m1.1.1" xref="A1.E12.m1.1.1.cmml"><mtext id="A1.E12.m1.1.1.2" xref="A1.E12.m1.1.1.2a.cmml">L</mtext><mo id="A1.E12.m1.1.1.1" xref="A1.E12.m1.1.1.1.cmml">=</mo><mrow id="A1.E12.m1.1.1.3" xref="A1.E12.m1.1.1.3.cmml"><msub id="A1.E12.m1.1.1.3.2" xref="A1.E12.m1.1.1.3.2.cmml"><mtext id="A1.E12.m1.1.1.3.2.2" xref="A1.E12.m1.1.1.3.2.2a.cmml">N</mtext><mtext id="A1.E12.m1.1.1.3.2.3" xref="A1.E12.m1.1.1.3.2.3a.cmml">BB</mtext></msub><mo id="A1.E12.m1.1.1.3.1" xref="A1.E12.m1.1.1.3.1.cmml">⁢</mo><msup id="A1.E12.m1.1.1.3.3" xref="A1.E12.m1.1.1.3.3.cmml"><mi id="A1.E12.m1.1.1.3.3.2" xref="A1.E12.m1.1.1.3.3.2.cmml">e</mi><mrow id="A1.E12.m1.1.1.3.3.3" xref="A1.E12.m1.1.1.3.3.3.cmml"><mo id="A1.E12.m1.1.1.3.3.3a" xref="A1.E12.m1.1.1.3.3.3.cmml">−</mo><mrow id="A1.E12.m1.1.1.3.3.3.2" xref="A1.E12.m1.1.1.3.3.3.2.cmml"><mi id="A1.E12.m1.1.1.3.3.3.2.2" xref="A1.E12.m1.1.1.3.3.3.2.2.cmml">X</mi><mo id="A1.E12.m1.1.1.3.3.3.2.1" xref="A1.E12.m1.1.1.3.3.3.2.1.cmml">/</mo><msub id="A1.E12.m1.1.1.3.3.3.2.3" xref="A1.E12.m1.1.1.3.3.3.2.3.cmml"><mtext id="A1.E12.m1.1.1.3.3.3.2.3.2" xref="A1.E12.m1.1.1.3.3.3.2.3.2a.cmml">S</mtext><mtext id="A1.E12.m1.1.1.3.3.3.2.3.3" xref="A1.E12.m1.1.1.3.3.3.2.3.3a.cmml">SOC</mtext></msub></mrow></mrow></msup></mrow></mrow><annotation-xml encoding="MathML-Content" id="A1.E12.m1.1b"><apply id="A1.E12.m1.1.1.cmml" xref="A1.E12.m1.1.1"><eq id="A1.E12.m1.1.1.1.cmml" xref="A1.E12.m1.1.1.1"></eq><ci id="A1.E12.m1.1.1.2a.cmml" xref="A1.E12.m1.1.1.2"><mtext id="A1.E12.m1.1.1.2.cmml" xref="A1.E12.m1.1.1.2">L</mtext></ci><apply id="A1.E12.m1.1.1.3.cmml" xref="A1.E12.m1.1.1.3"><times id="A1.E12.m1.1.1.3.1.cmml" xref="A1.E12.m1.1.1.3.1"></times><apply id="A1.E12.m1.1.1.3.2.cmml" xref="A1.E12.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E12.m1.1.1.3.2.1.cmml" xref="A1.E12.m1.1.1.3.2">subscript</csymbol><ci id="A1.E12.m1.1.1.3.2.2a.cmml" xref="A1.E12.m1.1.1.3.2.2"><mtext id="A1.E12.m1.1.1.3.2.2.cmml" xref="A1.E12.m1.1.1.3.2.2">N</mtext></ci><ci id="A1.E12.m1.1.1.3.2.3a.cmml" xref="A1.E12.m1.1.1.3.2.3"><mtext id="A1.E12.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E12.m1.1.1.3.2.3">BB</mtext></ci></apply><apply id="A1.E12.m1.1.1.3.3.cmml" xref="A1.E12.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E12.m1.1.1.3.3.1.cmml" xref="A1.E12.m1.1.1.3.3">superscript</csymbol><ci id="A1.E12.m1.1.1.3.3.2.cmml" xref="A1.E12.m1.1.1.3.3.2">𝑒</ci><apply id="A1.E12.m1.1.1.3.3.3.cmml" xref="A1.E12.m1.1.1.3.3.3"><minus id="A1.E12.m1.1.1.3.3.3.1.cmml" xref="A1.E12.m1.1.1.3.3.3"></minus><apply id="A1.E12.m1.1.1.3.3.3.2.cmml" xref="A1.E12.m1.1.1.3.3.3.2"><divide id="A1.E12.m1.1.1.3.3.3.2.1.cmml" xref="A1.E12.m1.1.1.3.3.3.2.1"></divide><ci id="A1.E12.m1.1.1.3.3.3.2.2.cmml" xref="A1.E12.m1.1.1.3.3.3.2.2">𝑋</ci><apply id="A1.E12.m1.1.1.3.3.3.2.3.cmml" xref="A1.E12.m1.1.1.3.3.3.2.3"><csymbol cd="ambiguous" id="A1.E12.m1.1.1.3.3.3.2.3.1.cmml" xref="A1.E12.m1.1.1.3.3.3.2.3">subscript</csymbol><ci id="A1.E12.m1.1.1.3.3.3.2.3.2a.cmml" xref="A1.E12.m1.1.1.3.3.3.2.3.2"><mtext id="A1.E12.m1.1.1.3.3.3.2.3.2.cmml" mathsize="70%" xref="A1.E12.m1.1.1.3.3.3.2.3.2">S</mtext></ci><ci id="A1.E12.m1.1.1.3.3.3.2.3.3a.cmml" xref="A1.E12.m1.1.1.3.3.3.2.3.3"><mtext id="A1.E12.m1.1.1.3.3.3.2.3.3.cmml" mathsize="50%" xref="A1.E12.m1.1.1.3.3.3.2.3.3">SOC</mtext></ci></apply></apply></apply></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E12.m1.1c">\text{L}=\text{N}_{\text{BB}}e^{-X/\text{S}_{\text{SOC}}}</annotation><annotation encoding="application/x-llamapun" id="A1.E12.m1.1d">L = N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT italic_e start_POSTSUPERSCRIPT - italic_X / S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_POSTSUPERSCRIPT</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p15"> <p class="ltx_p" id="A1.SS2.p15.1">We now factor in the overprovisioned space available to the SOC data during SSD garbage collection operations to cushion the DLWA. <br class="ltx_break"/></p> </div> <div class="ltx_para" id="A1.SS2.p16"> <p class="ltx_p" id="A1.SS2.p16.4">Say the average SOC buckets that remain valid in an erase block when GC is triggered is <math alttext="\delta" class="ltx_Math" display="inline" id="A1.SS2.p16.1.m1.1"><semantics id="A1.SS2.p16.1.m1.1a"><mi id="A1.SS2.p16.1.m1.1.1" xref="A1.SS2.p16.1.m1.1.1.cmml">δ</mi><annotation-xml encoding="MathML-Content" id="A1.SS2.p16.1.m1.1b"><ci id="A1.SS2.p16.1.m1.1.1.cmml" xref="A1.SS2.p16.1.m1.1.1">𝛿</ci></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p16.1.m1.1c">\delta</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p16.1.m1.1d">italic_δ</annotation></semantics></math>. Then each GC operation on average involves <math alttext="\text{N}_{\text{BB}}\times\delta" class="ltx_Math" display="inline" id="A1.SS2.p16.2.m2.1"><semantics id="A1.SS2.p16.2.m2.1a"><mrow id="A1.SS2.p16.2.m2.1.1" xref="A1.SS2.p16.2.m2.1.1.cmml"><msub id="A1.SS2.p16.2.m2.1.1.2" xref="A1.SS2.p16.2.m2.1.1.2.cmml"><mtext id="A1.SS2.p16.2.m2.1.1.2.2" xref="A1.SS2.p16.2.m2.1.1.2.2a.cmml">N</mtext><mtext id="A1.SS2.p16.2.m2.1.1.2.3" xref="A1.SS2.p16.2.m2.1.1.2.3a.cmml">BB</mtext></msub><mo id="A1.SS2.p16.2.m2.1.1.1" lspace="0.222em" rspace="0.222em" xref="A1.SS2.p16.2.m2.1.1.1.cmml">×</mo><mi id="A1.SS2.p16.2.m2.1.1.3" xref="A1.SS2.p16.2.m2.1.1.3.cmml">δ</mi></mrow><annotation-xml encoding="MathML-Content" id="A1.SS2.p16.2.m2.1b"><apply id="A1.SS2.p16.2.m2.1.1.cmml" xref="A1.SS2.p16.2.m2.1.1"><times id="A1.SS2.p16.2.m2.1.1.1.cmml" xref="A1.SS2.p16.2.m2.1.1.1"></times><apply id="A1.SS2.p16.2.m2.1.1.2.cmml" xref="A1.SS2.p16.2.m2.1.1.2"><csymbol cd="ambiguous" id="A1.SS2.p16.2.m2.1.1.2.1.cmml" xref="A1.SS2.p16.2.m2.1.1.2">subscript</csymbol><ci id="A1.SS2.p16.2.m2.1.1.2.2a.cmml" xref="A1.SS2.p16.2.m2.1.1.2.2"><mtext id="A1.SS2.p16.2.m2.1.1.2.2.cmml" xref="A1.SS2.p16.2.m2.1.1.2.2">N</mtext></ci><ci id="A1.SS2.p16.2.m2.1.1.2.3a.cmml" xref="A1.SS2.p16.2.m2.1.1.2.3"><mtext id="A1.SS2.p16.2.m2.1.1.2.3.cmml" mathsize="70%" xref="A1.SS2.p16.2.m2.1.1.2.3">BB</mtext></ci></apply><ci id="A1.SS2.p16.2.m2.1.1.3.cmml" xref="A1.SS2.p16.2.m2.1.1.3">𝛿</ci></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p16.2.m2.1c">\text{N}_{\text{BB}}\times\delta</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p16.2.m2.1d">N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT × italic_δ</annotation></semantics></math> migrations. It also follows that the number of SOC bucket writes or insertions that can be accommodated due to this migration is <math alttext="\text{N}_{\text{BB}}\times(1-\delta)" class="ltx_Math" display="inline" id="A1.SS2.p16.3.m3.1"><semantics id="A1.SS2.p16.3.m3.1a"><mrow id="A1.SS2.p16.3.m3.1.1" xref="A1.SS2.p16.3.m3.1.1.cmml"><msub id="A1.SS2.p16.3.m3.1.1.3" xref="A1.SS2.p16.3.m3.1.1.3.cmml"><mtext id="A1.SS2.p16.3.m3.1.1.3.2" xref="A1.SS2.p16.3.m3.1.1.3.2a.cmml">N</mtext><mtext id="A1.SS2.p16.3.m3.1.1.3.3" xref="A1.SS2.p16.3.m3.1.1.3.3a.cmml">BB</mtext></msub><mo id="A1.SS2.p16.3.m3.1.1.2" lspace="0.222em" rspace="0.222em" xref="A1.SS2.p16.3.m3.1.1.2.cmml">×</mo><mrow id="A1.SS2.p16.3.m3.1.1.1.1" xref="A1.SS2.p16.3.m3.1.1.1.1.1.cmml"><mo id="A1.SS2.p16.3.m3.1.1.1.1.2" stretchy="false" xref="A1.SS2.p16.3.m3.1.1.1.1.1.cmml">(</mo><mrow id="A1.SS2.p16.3.m3.1.1.1.1.1" xref="A1.SS2.p16.3.m3.1.1.1.1.1.cmml"><mn id="A1.SS2.p16.3.m3.1.1.1.1.1.2" xref="A1.SS2.p16.3.m3.1.1.1.1.1.2.cmml">1</mn><mo id="A1.SS2.p16.3.m3.1.1.1.1.1.1" xref="A1.SS2.p16.3.m3.1.1.1.1.1.1.cmml">−</mo><mi id="A1.SS2.p16.3.m3.1.1.1.1.1.3" xref="A1.SS2.p16.3.m3.1.1.1.1.1.3.cmml">δ</mi></mrow><mo id="A1.SS2.p16.3.m3.1.1.1.1.3" stretchy="false" xref="A1.SS2.p16.3.m3.1.1.1.1.1.cmml">)</mo></mrow></mrow><annotation-xml encoding="MathML-Content" id="A1.SS2.p16.3.m3.1b"><apply id="A1.SS2.p16.3.m3.1.1.cmml" xref="A1.SS2.p16.3.m3.1.1"><times id="A1.SS2.p16.3.m3.1.1.2.cmml" xref="A1.SS2.p16.3.m3.1.1.2"></times><apply id="A1.SS2.p16.3.m3.1.1.3.cmml" xref="A1.SS2.p16.3.m3.1.1.3"><csymbol cd="ambiguous" id="A1.SS2.p16.3.m3.1.1.3.1.cmml" xref="A1.SS2.p16.3.m3.1.1.3">subscript</csymbol><ci id="A1.SS2.p16.3.m3.1.1.3.2a.cmml" xref="A1.SS2.p16.3.m3.1.1.3.2"><mtext id="A1.SS2.p16.3.m3.1.1.3.2.cmml" xref="A1.SS2.p16.3.m3.1.1.3.2">N</mtext></ci><ci id="A1.SS2.p16.3.m3.1.1.3.3a.cmml" xref="A1.SS2.p16.3.m3.1.1.3.3"><mtext id="A1.SS2.p16.3.m3.1.1.3.3.cmml" mathsize="70%" xref="A1.SS2.p16.3.m3.1.1.3.3">BB</mtext></ci></apply><apply id="A1.SS2.p16.3.m3.1.1.1.1.1.cmml" xref="A1.SS2.p16.3.m3.1.1.1.1"><minus id="A1.SS2.p16.3.m3.1.1.1.1.1.1.cmml" xref="A1.SS2.p16.3.m3.1.1.1.1.1.1"></minus><cn id="A1.SS2.p16.3.m3.1.1.1.1.1.2.cmml" type="integer" xref="A1.SS2.p16.3.m3.1.1.1.1.1.2">1</cn><ci id="A1.SS2.p16.3.m3.1.1.1.1.1.3.cmml" xref="A1.SS2.p16.3.m3.1.1.1.1.1.3">𝛿</ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p16.3.m3.1c">\text{N}_{\text{BB}}\times(1-\delta)</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p16.3.m3.1d">N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT × ( 1 - italic_δ )</annotation></semantics></math>. <br class="ltx_break"/>We assume a greedy GC policy (i.e. the erase block with least valid pages will be picked first for GC). Say the expected number of GC operations between two successive victim selections of the same block is <span class="ltx_text ltx_markedasmath" id="A1.SS2.p16.4.1">G</span>. Given the uniform workload pattern we can see that,</p> <table class="ltx_equation ltx_eqn_table" id="A1.E13"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(13)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\text{G}=\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}" class="ltx_Math" display="block" id="A1.E13.m1.1"><semantics id="A1.E13.m1.1a"><mrow id="A1.E13.m1.1.1" xref="A1.E13.m1.1.1.cmml"><mtext id="A1.E13.m1.1.1.2" xref="A1.E13.m1.1.1.2a.cmml">G</mtext><mo id="A1.E13.m1.1.1.1" xref="A1.E13.m1.1.1.1.cmml">=</mo><mfrac id="A1.E13.m1.1.1.3" xref="A1.E13.m1.1.1.3.cmml"><msub id="A1.E13.m1.1.1.3.2" xref="A1.E13.m1.1.1.3.2.cmml"><mtext id="A1.E13.m1.1.1.3.2.2" xref="A1.E13.m1.1.1.3.2.2a.cmml">S</mtext><mtext id="A1.E13.m1.1.1.3.2.3" xref="A1.E13.m1.1.1.3.2.3a.cmml">P-SOC</mtext></msub><msub id="A1.E13.m1.1.1.3.3" xref="A1.E13.m1.1.1.3.3.cmml"><mtext id="A1.E13.m1.1.1.3.3.2" xref="A1.E13.m1.1.1.3.3.2a.cmml">N</mtext><mtext id="A1.E13.m1.1.1.3.3.3" xref="A1.E13.m1.1.1.3.3.3a.cmml">BB</mtext></msub></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E13.m1.1b"><apply id="A1.E13.m1.1.1.cmml" xref="A1.E13.m1.1.1"><eq id="A1.E13.m1.1.1.1.cmml" xref="A1.E13.m1.1.1.1"></eq><ci id="A1.E13.m1.1.1.2a.cmml" xref="A1.E13.m1.1.1.2"><mtext id="A1.E13.m1.1.1.2.cmml" xref="A1.E13.m1.1.1.2">G</mtext></ci><apply id="A1.E13.m1.1.1.3.cmml" xref="A1.E13.m1.1.1.3"><divide id="A1.E13.m1.1.1.3.1.cmml" xref="A1.E13.m1.1.1.3"></divide><apply id="A1.E13.m1.1.1.3.2.cmml" xref="A1.E13.m1.1.1.3.2"><csymbol cd="ambiguous" id="A1.E13.m1.1.1.3.2.1.cmml" xref="A1.E13.m1.1.1.3.2">subscript</csymbol><ci id="A1.E13.m1.1.1.3.2.2a.cmml" xref="A1.E13.m1.1.1.3.2.2"><mtext id="A1.E13.m1.1.1.3.2.2.cmml" xref="A1.E13.m1.1.1.3.2.2">S</mtext></ci><ci id="A1.E13.m1.1.1.3.2.3a.cmml" xref="A1.E13.m1.1.1.3.2.3"><mtext id="A1.E13.m1.1.1.3.2.3.cmml" mathsize="70%" xref="A1.E13.m1.1.1.3.2.3">P-SOC</mtext></ci></apply><apply id="A1.E13.m1.1.1.3.3.cmml" xref="A1.E13.m1.1.1.3.3"><csymbol cd="ambiguous" id="A1.E13.m1.1.1.3.3.1.cmml" xref="A1.E13.m1.1.1.3.3">subscript</csymbol><ci id="A1.E13.m1.1.1.3.3.2a.cmml" xref="A1.E13.m1.1.1.3.3.2"><mtext id="A1.E13.m1.1.1.3.3.2.cmml" xref="A1.E13.m1.1.1.3.3.2">N</mtext></ci><ci id="A1.E13.m1.1.1.3.3.3a.cmml" xref="A1.E13.m1.1.1.3.3.3"><mtext id="A1.E13.m1.1.1.3.3.3.cmml" mathsize="70%" xref="A1.E13.m1.1.1.3.3.3">BB</mtext></ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E13.m1.1c">\text{G}=\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}</annotation><annotation encoding="application/x-llamapun" id="A1.E13.m1.1d">G = divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> <p class="ltx_p" id="A1.SS2.p16.5">This can be interpreted as follows,</p> <ul class="ltx_itemize" id="A1.I2"> <li class="ltx_item" id="A1.I2.i1" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I2.i1.p1"> <p class="ltx_p" id="A1.I2.i1.p1.1">We have <math alttext="\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}" class="ltx_Math" display="inline" id="A1.I2.i1.p1.1.m1.1"><semantics id="A1.I2.i1.p1.1.m1.1a"><mfrac id="A1.I2.i1.p1.1.m1.1.1" xref="A1.I2.i1.p1.1.m1.1.1.cmml"><msub id="A1.I2.i1.p1.1.m1.1.1.2" xref="A1.I2.i1.p1.1.m1.1.1.2.cmml"><mtext id="A1.I2.i1.p1.1.m1.1.1.2.2" xref="A1.I2.i1.p1.1.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.I2.i1.p1.1.m1.1.1.2.3" xref="A1.I2.i1.p1.1.m1.1.1.2.3a.cmml">P-SOC</mtext></msub><msub id="A1.I2.i1.p1.1.m1.1.1.3" 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id="A1.I2.i1.p1.1.m1.1.1.3.cmml" xref="A1.I2.i1.p1.1.m1.1.1.3"><csymbol cd="ambiguous" id="A1.I2.i1.p1.1.m1.1.1.3.1.cmml" xref="A1.I2.i1.p1.1.m1.1.1.3">subscript</csymbol><ci id="A1.I2.i1.p1.1.m1.1.1.3.2a.cmml" xref="A1.I2.i1.p1.1.m1.1.1.3.2"><mtext id="A1.I2.i1.p1.1.m1.1.1.3.2.cmml" mathsize="70%" xref="A1.I2.i1.p1.1.m1.1.1.3.2">N</mtext></ci><ci id="A1.I2.i1.p1.1.m1.1.1.3.3a.cmml" xref="A1.I2.i1.p1.1.m1.1.1.3.3"><mtext id="A1.I2.i1.p1.1.m1.1.1.3.3.cmml" mathsize="50%" xref="A1.I2.i1.p1.1.m1.1.1.3.3">BB</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.I2.i1.p1.1.m1.1c">\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}</annotation><annotation encoding="application/x-llamapun" id="A1.I2.i1.p1.1.m1.1d">divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG</annotation></semantics></math> number of erase blocks holding SOC data in the SSD.</p> </div> </li> <li class="ltx_item" id="A1.I2.i2" style="list-style-type:none;"> <span class="ltx_tag ltx_tag_item">•</span> <div class="ltx_para" id="A1.I2.i2.p1"> <p class="ltx_p" id="A1.I2.i2.p1.1">Once an erase block is picked, on average it is picked after <math alttext="\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}" class="ltx_Math" display="inline" id="A1.I2.i2.p1.1.m1.1"><semantics id="A1.I2.i2.p1.1.m1.1a"><mfrac id="A1.I2.i2.p1.1.m1.1.1" xref="A1.I2.i2.p1.1.m1.1.1.cmml"><msub id="A1.I2.i2.p1.1.m1.1.1.2" xref="A1.I2.i2.p1.1.m1.1.1.2.cmml"><mtext id="A1.I2.i2.p1.1.m1.1.1.2.2" xref="A1.I2.i2.p1.1.m1.1.1.2.2a.cmml">S</mtext><mtext id="A1.I2.i2.p1.1.m1.1.1.2.3" xref="A1.I2.i2.p1.1.m1.1.1.2.3a.cmml">P-SOC</mtext></msub><msub id="A1.I2.i2.p1.1.m1.1.1.3" xref="A1.I2.i2.p1.1.m1.1.1.3.cmml"><mtext id="A1.I2.i2.p1.1.m1.1.1.3.2" xref="A1.I2.i2.p1.1.m1.1.1.3.2a.cmml">N</mtext><mtext id="A1.I2.i2.p1.1.m1.1.1.3.3" xref="A1.I2.i2.p1.1.m1.1.1.3.3a.cmml">BB</mtext></msub></mfrac><annotation-xml encoding="MathML-Content" id="A1.I2.i2.p1.1.m1.1b"><apply id="A1.I2.i2.p1.1.m1.1.1.cmml" xref="A1.I2.i2.p1.1.m1.1.1"><divide id="A1.I2.i2.p1.1.m1.1.1.1.cmml" xref="A1.I2.i2.p1.1.m1.1.1"></divide><apply id="A1.I2.i2.p1.1.m1.1.1.2.cmml" xref="A1.I2.i2.p1.1.m1.1.1.2"><csymbol cd="ambiguous" id="A1.I2.i2.p1.1.m1.1.1.2.1.cmml" xref="A1.I2.i2.p1.1.m1.1.1.2">subscript</csymbol><ci id="A1.I2.i2.p1.1.m1.1.1.2.2a.cmml" xref="A1.I2.i2.p1.1.m1.1.1.2.2"><mtext id="A1.I2.i2.p1.1.m1.1.1.2.2.cmml" mathsize="70%" xref="A1.I2.i2.p1.1.m1.1.1.2.2">S</mtext></ci><ci id="A1.I2.i2.p1.1.m1.1.1.2.3a.cmml" xref="A1.I2.i2.p1.1.m1.1.1.2.3"><mtext id="A1.I2.i2.p1.1.m1.1.1.2.3.cmml" mathsize="50%" xref="A1.I2.i2.p1.1.m1.1.1.2.3">P-SOC</mtext></ci></apply><apply id="A1.I2.i2.p1.1.m1.1.1.3.cmml" xref="A1.I2.i2.p1.1.m1.1.1.3"><csymbol cd="ambiguous" id="A1.I2.i2.p1.1.m1.1.1.3.1.cmml" xref="A1.I2.i2.p1.1.m1.1.1.3">subscript</csymbol><ci id="A1.I2.i2.p1.1.m1.1.1.3.2a.cmml" xref="A1.I2.i2.p1.1.m1.1.1.3.2"><mtext id="A1.I2.i2.p1.1.m1.1.1.3.2.cmml" mathsize="70%" xref="A1.I2.i2.p1.1.m1.1.1.3.2">N</mtext></ci><ci id="A1.I2.i2.p1.1.m1.1.1.3.3a.cmml" xref="A1.I2.i2.p1.1.m1.1.1.3.3"><mtext id="A1.I2.i2.p1.1.m1.1.1.3.3.cmml" mathsize="50%" xref="A1.I2.i2.p1.1.m1.1.1.3.3">BB</mtext></ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.I2.i2.p1.1.m1.1c">\frac{\text{S}_{\text{P-SOC}}}{\text{N}_{\text{BB}}}</annotation><annotation encoding="application/x-llamapun" id="A1.I2.i2.p1.1.m1.1d">divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT end_ARG</annotation></semantics></math> GC operations.</p> </div> </li> </ul> </div> <div class="ltx_para" id="A1.SS2.p17"> <p class="ltx_p" id="A1.SS2.p17.2">As <span class="ltx_text ltx_markedasmath" id="A1.SS2.p17.2.1">G</span> erase blocks are picked for GC before the same block is picked again, <math alttext="\text{G}\times\text{N}_{\text{BB}}\times(1-\delta)" class="ltx_Math" display="inline" id="A1.SS2.p17.2.m2.1"><semantics id="A1.SS2.p17.2.m2.1a"><mrow id="A1.SS2.p17.2.m2.1.1" xref="A1.SS2.p17.2.m2.1.1.cmml"><mtext id="A1.SS2.p17.2.m2.1.1.3" xref="A1.SS2.p17.2.m2.1.1.3a.cmml">G</mtext><mo id="A1.SS2.p17.2.m2.1.1.2" lspace="0.222em" rspace="0.222em" xref="A1.SS2.p17.2.m2.1.1.2.cmml">×</mo><msub id="A1.SS2.p17.2.m2.1.1.4" xref="A1.SS2.p17.2.m2.1.1.4.cmml"><mtext id="A1.SS2.p17.2.m2.1.1.4.2" xref="A1.SS2.p17.2.m2.1.1.4.2a.cmml">N</mtext><mtext id="A1.SS2.p17.2.m2.1.1.4.3" xref="A1.SS2.p17.2.m2.1.1.4.3a.cmml">BB</mtext></msub><mo id="A1.SS2.p17.2.m2.1.1.2a" lspace="0.222em" rspace="0.222em" xref="A1.SS2.p17.2.m2.1.1.2.cmml">×</mo><mrow id="A1.SS2.p17.2.m2.1.1.1.1" xref="A1.SS2.p17.2.m2.1.1.1.1.1.cmml"><mo id="A1.SS2.p17.2.m2.1.1.1.1.2" stretchy="false" xref="A1.SS2.p17.2.m2.1.1.1.1.1.cmml">(</mo><mrow id="A1.SS2.p17.2.m2.1.1.1.1.1" xref="A1.SS2.p17.2.m2.1.1.1.1.1.cmml"><mn id="A1.SS2.p17.2.m2.1.1.1.1.1.2" xref="A1.SS2.p17.2.m2.1.1.1.1.1.2.cmml">1</mn><mo id="A1.SS2.p17.2.m2.1.1.1.1.1.1" xref="A1.SS2.p17.2.m2.1.1.1.1.1.1.cmml">−</mo><mi id="A1.SS2.p17.2.m2.1.1.1.1.1.3" xref="A1.SS2.p17.2.m2.1.1.1.1.1.3.cmml">δ</mi></mrow><mo id="A1.SS2.p17.2.m2.1.1.1.1.3" stretchy="false" xref="A1.SS2.p17.2.m2.1.1.1.1.1.cmml">)</mo></mrow></mrow><annotation-xml encoding="MathML-Content" id="A1.SS2.p17.2.m2.1b"><apply id="A1.SS2.p17.2.m2.1.1.cmml" xref="A1.SS2.p17.2.m2.1.1"><times id="A1.SS2.p17.2.m2.1.1.2.cmml" xref="A1.SS2.p17.2.m2.1.1.2"></times><ci id="A1.SS2.p17.2.m2.1.1.3a.cmml" xref="A1.SS2.p17.2.m2.1.1.3"><mtext id="A1.SS2.p17.2.m2.1.1.3.cmml" xref="A1.SS2.p17.2.m2.1.1.3">G</mtext></ci><apply id="A1.SS2.p17.2.m2.1.1.4.cmml" xref="A1.SS2.p17.2.m2.1.1.4"><csymbol cd="ambiguous" id="A1.SS2.p17.2.m2.1.1.4.1.cmml" xref="A1.SS2.p17.2.m2.1.1.4">subscript</csymbol><ci id="A1.SS2.p17.2.m2.1.1.4.2a.cmml" xref="A1.SS2.p17.2.m2.1.1.4.2"><mtext id="A1.SS2.p17.2.m2.1.1.4.2.cmml" xref="A1.SS2.p17.2.m2.1.1.4.2">N</mtext></ci><ci id="A1.SS2.p17.2.m2.1.1.4.3a.cmml" xref="A1.SS2.p17.2.m2.1.1.4.3"><mtext id="A1.SS2.p17.2.m2.1.1.4.3.cmml" mathsize="70%" xref="A1.SS2.p17.2.m2.1.1.4.3">BB</mtext></ci></apply><apply id="A1.SS2.p17.2.m2.1.1.1.1.1.cmml" xref="A1.SS2.p17.2.m2.1.1.1.1"><minus id="A1.SS2.p17.2.m2.1.1.1.1.1.1.cmml" xref="A1.SS2.p17.2.m2.1.1.1.1.1.1"></minus><cn id="A1.SS2.p17.2.m2.1.1.1.1.1.2.cmml" type="integer" xref="A1.SS2.p17.2.m2.1.1.1.1.1.2">1</cn><ci id="A1.SS2.p17.2.m2.1.1.1.1.1.3.cmml" xref="A1.SS2.p17.2.m2.1.1.1.1.1.3">𝛿</ci></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p17.2.m2.1c">\text{G}\times\text{N}_{\text{BB}}\times(1-\delta)</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p17.2.m2.1d">G × N start_POSTSUBSCRIPT BB end_POSTSUBSCRIPT × ( 1 - italic_δ )</annotation></semantics></math> SOC writes occur on average between two GC operations on the same erase block. <br class="ltx_break"/></p> </div> <div class="ltx_para" id="A1.SS2.p18"> <p class="ltx_p" id="A1.SS2.p18.1">Using this in Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E12" title="Equation 12 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">12</span></a> and Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E13" title="Equation 13 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">13</span></a> we get,</p> </div> <div class="ltx_para" id="A1.SS2.p19"> <table class="ltx_equation ltx_eqn_table" id="A1.E14"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(14)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{P-SOC}}}=\frac{\delta-1}{\text{ln% }(\delta)}" class="ltx_Math" display="block" id="A1.E14.m1.1"><semantics id="A1.E14.m1.1a"><mrow id="A1.E14.m1.1.2" xref="A1.E14.m1.1.2.cmml"><mfrac id="A1.E14.m1.1.2.2" xref="A1.E14.m1.1.2.2.cmml"><msub id="A1.E14.m1.1.2.2.2" xref="A1.E14.m1.1.2.2.2.cmml"><mtext id="A1.E14.m1.1.2.2.2.2" xref="A1.E14.m1.1.2.2.2.2a.cmml">S</mtext><mtext id="A1.E14.m1.1.2.2.2.3" xref="A1.E14.m1.1.2.2.2.3a.cmml">SOC</mtext></msub><msub id="A1.E14.m1.1.2.2.3" xref="A1.E14.m1.1.2.2.3.cmml"><mtext id="A1.E14.m1.1.2.2.3.2" xref="A1.E14.m1.1.2.2.3.2a.cmml">S</mtext><mtext id="A1.E14.m1.1.2.2.3.3" xref="A1.E14.m1.1.2.2.3.3a.cmml">P-SOC</mtext></msub></mfrac><mo id="A1.E14.m1.1.2.1" xref="A1.E14.m1.1.2.1.cmml">=</mo><mfrac id="A1.E14.m1.1.1" xref="A1.E14.m1.1.1.cmml"><mrow id="A1.E14.m1.1.1.3" xref="A1.E14.m1.1.1.3.cmml"><mi id="A1.E14.m1.1.1.3.2" xref="A1.E14.m1.1.1.3.2.cmml">δ</mi><mo id="A1.E14.m1.1.1.3.1" xref="A1.E14.m1.1.1.3.1.cmml">−</mo><mn id="A1.E14.m1.1.1.3.3" xref="A1.E14.m1.1.1.3.3.cmml">1</mn></mrow><mrow id="A1.E14.m1.1.1.1" xref="A1.E14.m1.1.1.1.cmml"><mtext id="A1.E14.m1.1.1.1.3" xref="A1.E14.m1.1.1.1.3a.cmml">ln</mtext><mo id="A1.E14.m1.1.1.1.2" xref="A1.E14.m1.1.1.1.2.cmml">⁢</mo><mrow id="A1.E14.m1.1.1.1.4.2" xref="A1.E14.m1.1.1.1.cmml"><mo id="A1.E14.m1.1.1.1.4.2.1" stretchy="false" xref="A1.E14.m1.1.1.1.cmml">(</mo><mi id="A1.E14.m1.1.1.1.1" xref="A1.E14.m1.1.1.1.1.cmml">δ</mi><mo id="A1.E14.m1.1.1.1.4.2.2" stretchy="false" xref="A1.E14.m1.1.1.1.cmml">)</mo></mrow></mrow></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E14.m1.1b"><apply id="A1.E14.m1.1.2.cmml" xref="A1.E14.m1.1.2"><eq id="A1.E14.m1.1.2.1.cmml" xref="A1.E14.m1.1.2.1"></eq><apply id="A1.E14.m1.1.2.2.cmml" xref="A1.E14.m1.1.2.2"><divide id="A1.E14.m1.1.2.2.1.cmml" xref="A1.E14.m1.1.2.2"></divide><apply id="A1.E14.m1.1.2.2.2.cmml" xref="A1.E14.m1.1.2.2.2"><csymbol cd="ambiguous" id="A1.E14.m1.1.2.2.2.1.cmml" xref="A1.E14.m1.1.2.2.2">subscript</csymbol><ci id="A1.E14.m1.1.2.2.2.2a.cmml" xref="A1.E14.m1.1.2.2.2.2"><mtext id="A1.E14.m1.1.2.2.2.2.cmml" xref="A1.E14.m1.1.2.2.2.2">S</mtext></ci><ci id="A1.E14.m1.1.2.2.2.3a.cmml" xref="A1.E14.m1.1.2.2.2.3"><mtext id="A1.E14.m1.1.2.2.2.3.cmml" mathsize="70%" xref="A1.E14.m1.1.2.2.2.3">SOC</mtext></ci></apply><apply id="A1.E14.m1.1.2.2.3.cmml" xref="A1.E14.m1.1.2.2.3"><csymbol cd="ambiguous" id="A1.E14.m1.1.2.2.3.1.cmml" xref="A1.E14.m1.1.2.2.3">subscript</csymbol><ci id="A1.E14.m1.1.2.2.3.2a.cmml" xref="A1.E14.m1.1.2.2.3.2"><mtext id="A1.E14.m1.1.2.2.3.2.cmml" xref="A1.E14.m1.1.2.2.3.2">S</mtext></ci><ci id="A1.E14.m1.1.2.2.3.3a.cmml" xref="A1.E14.m1.1.2.2.3.3"><mtext id="A1.E14.m1.1.2.2.3.3.cmml" mathsize="70%" xref="A1.E14.m1.1.2.2.3.3">P-SOC</mtext></ci></apply></apply><apply id="A1.E14.m1.1.1.cmml" xref="A1.E14.m1.1.1"><divide id="A1.E14.m1.1.1.2.cmml" xref="A1.E14.m1.1.1"></divide><apply id="A1.E14.m1.1.1.3.cmml" xref="A1.E14.m1.1.1.3"><minus id="A1.E14.m1.1.1.3.1.cmml" xref="A1.E14.m1.1.1.3.1"></minus><ci id="A1.E14.m1.1.1.3.2.cmml" xref="A1.E14.m1.1.1.3.2">𝛿</ci><cn id="A1.E14.m1.1.1.3.3.cmml" type="integer" xref="A1.E14.m1.1.1.3.3">1</cn></apply><apply id="A1.E14.m1.1.1.1.cmml" xref="A1.E14.m1.1.1.1"><times id="A1.E14.m1.1.1.1.2.cmml" xref="A1.E14.m1.1.1.1.2"></times><ci id="A1.E14.m1.1.1.1.3a.cmml" xref="A1.E14.m1.1.1.1.3"><mtext id="A1.E14.m1.1.1.1.3.cmml" xref="A1.E14.m1.1.1.1.3">ln</mtext></ci><ci id="A1.E14.m1.1.1.1.1.cmml" xref="A1.E14.m1.1.1.1.1">𝛿</ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E14.m1.1c">\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{P-SOC}}}=\frac{\delta-1}{\text{ln% }(\delta)}</annotation><annotation encoding="application/x-llamapun" id="A1.E14.m1.1d">divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG = divide start_ARG italic_δ - 1 end_ARG start_ARG ln ( italic_δ ) end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p20"> <p class="ltx_p" id="A1.SS2.p20.1">Equation <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.E14" title="Equation 14 ‣ A.2. Derivation ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">14</span></a> can be simplified using the Lambert W function <cite class="ltx_cite ltx_citemacro_citep">(Dayan et al<span class="ltx_text">.</span>, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib31" title="">2015</a>; Desnoyers, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib32" title="">2012</a>; Stoica and Ailamaki, <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#bib.bib56" title="">2013</a>)</cite> as follows:</p> </div> <div class="ltx_para" id="A1.SS2.p21"> <table class="ltx_equation ltx_eqn_table" id="A1.E15"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(15)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="\delta=-\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{P-SOC}}}\times\mathcal{W}% (-\frac{\text{S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}\times e^{-\frac{\text{% S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}})" class="ltx_Math" display="block" id="A1.E15.m1.1"><semantics id="A1.E15.m1.1a"><mrow id="A1.E15.m1.1.1" xref="A1.E15.m1.1.1.cmml"><mi id="A1.E15.m1.1.1.3" xref="A1.E15.m1.1.1.3.cmml">δ</mi><mo id="A1.E15.m1.1.1.2" xref="A1.E15.m1.1.1.2.cmml">=</mo><mrow id="A1.E15.m1.1.1.1" xref="A1.E15.m1.1.1.1.cmml"><mo id="A1.E15.m1.1.1.1a" xref="A1.E15.m1.1.1.1.cmml">−</mo><mrow id="A1.E15.m1.1.1.1.1" xref="A1.E15.m1.1.1.1.1.cmml"><mrow id="A1.E15.m1.1.1.1.1.3" xref="A1.E15.m1.1.1.1.1.3.cmml"><mfrac id="A1.E15.m1.1.1.1.1.3.2" xref="A1.E15.m1.1.1.1.1.3.2.cmml"><msub id="A1.E15.m1.1.1.1.1.3.2.2" xref="A1.E15.m1.1.1.1.1.3.2.2.cmml"><mtext id="A1.E15.m1.1.1.1.1.3.2.2.2" xref="A1.E15.m1.1.1.1.1.3.2.2.2a.cmml">S</mtext><mtext id="A1.E15.m1.1.1.1.1.3.2.2.3" xref="A1.E15.m1.1.1.1.1.3.2.2.3a.cmml">SOC</mtext></msub><msub id="A1.E15.m1.1.1.1.1.3.2.3" xref="A1.E15.m1.1.1.1.1.3.2.3.cmml"><mtext id="A1.E15.m1.1.1.1.1.3.2.3.2" xref="A1.E15.m1.1.1.1.1.3.2.3.2a.cmml">S</mtext><mtext id="A1.E15.m1.1.1.1.1.3.2.3.3" xref="A1.E15.m1.1.1.1.1.3.2.3.3a.cmml">P-SOC</mtext></msub></mfrac><mo id="A1.E15.m1.1.1.1.1.3.1" lspace="0.222em" rspace="0.222em" xref="A1.E15.m1.1.1.1.1.3.1.cmml">×</mo><mi class="ltx_font_mathcaligraphic" id="A1.E15.m1.1.1.1.1.3.3" xref="A1.E15.m1.1.1.1.1.3.3.cmml">𝒲</mi></mrow><mo id="A1.E15.m1.1.1.1.1.2" xref="A1.E15.m1.1.1.1.1.2.cmml">⁢</mo><mrow id="A1.E15.m1.1.1.1.1.1.1" xref="A1.E15.m1.1.1.1.1.1.1.1.cmml"><mo id="A1.E15.m1.1.1.1.1.1.1.2" stretchy="false" xref="A1.E15.m1.1.1.1.1.1.1.1.cmml">(</mo><mrow id="A1.E15.m1.1.1.1.1.1.1.1" xref="A1.E15.m1.1.1.1.1.1.1.1.cmml"><mo id="A1.E15.m1.1.1.1.1.1.1.1a" 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encoding="application/x-tex" id="A1.E15.m1.1c">\delta=-\frac{\text{S}_{\text{SOC}}}{\text{S}_{\text{P-SOC}}}\times\mathcal{W}% (-\frac{\text{S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}\times e^{-\frac{\text{% S}_{\text{P-SOC}}}{\text{S}_{\text{SOC}}}})</annotation><annotation encoding="application/x-llamapun" id="A1.E15.m1.1d">italic_δ = - divide start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG × caligraphic_W ( - divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG × italic_e start_POSTSUPERSCRIPT - divide start_ARG S start_POSTSUBSCRIPT P-SOC end_POSTSUBSCRIPT end_ARG start_ARG S start_POSTSUBSCRIPT SOC end_POSTSUBSCRIPT end_ARG end_POSTSUPERSCRIPT )</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> <div class="ltx_para" id="A1.SS2.p22"> <p class="ltx_p" id="A1.SS2.p22.1">The SSD DLWA can be calculated using <math alttext="\delta" class="ltx_Math" display="inline" id="A1.SS2.p22.1.m1.1"><semantics id="A1.SS2.p22.1.m1.1a"><mi id="A1.SS2.p22.1.m1.1.1" xref="A1.SS2.p22.1.m1.1.1.cmml">δ</mi><annotation-xml encoding="MathML-Content" id="A1.SS2.p22.1.m1.1b"><ci id="A1.SS2.p22.1.m1.1.1.cmml" xref="A1.SS2.p22.1.m1.1.1">𝛿</ci></annotation-xml><annotation encoding="application/x-tex" id="A1.SS2.p22.1.m1.1c">\delta</annotation><annotation encoding="application/x-llamapun" id="A1.SS2.p22.1.m1.1d">italic_δ</annotation></semantics></math> as,</p> <table class="ltx_equation ltx_eqn_table" id="A1.E16"> <tbody><tr class="ltx_equation ltx_eqn_row ltx_align_baseline"> <td class="ltx_eqn_cell ltx_eqn_eqno ltx_align_middle ltx_align_left" rowspan="1"><span class="ltx_tag ltx_tag_equation ltx_align_left">(16)</span></td> <td class="ltx_eqn_cell ltx_eqn_center_padleft"></td> <td class="ltx_eqn_cell ltx_align_center"><math alttext="DLWA=\frac{1}{1-\delta}" class="ltx_Math" display="block" id="A1.E16.m1.1"><semantics id="A1.E16.m1.1a"><mrow id="A1.E16.m1.1.1" xref="A1.E16.m1.1.1.cmml"><mrow id="A1.E16.m1.1.1.2" xref="A1.E16.m1.1.1.2.cmml"><mi id="A1.E16.m1.1.1.2.2" xref="A1.E16.m1.1.1.2.2.cmml">D</mi><mo id="A1.E16.m1.1.1.2.1" xref="A1.E16.m1.1.1.2.1.cmml">⁢</mo><mi id="A1.E16.m1.1.1.2.3" xref="A1.E16.m1.1.1.2.3.cmml">L</mi><mo id="A1.E16.m1.1.1.2.1a" xref="A1.E16.m1.1.1.2.1.cmml">⁢</mo><mi id="A1.E16.m1.1.1.2.4" xref="A1.E16.m1.1.1.2.4.cmml">W</mi><mo id="A1.E16.m1.1.1.2.1b" xref="A1.E16.m1.1.1.2.1.cmml">⁢</mo><mi id="A1.E16.m1.1.1.2.5" xref="A1.E16.m1.1.1.2.5.cmml">A</mi></mrow><mo id="A1.E16.m1.1.1.1" xref="A1.E16.m1.1.1.1.cmml">=</mo><mfrac id="A1.E16.m1.1.1.3" xref="A1.E16.m1.1.1.3.cmml"><mn id="A1.E16.m1.1.1.3.2" xref="A1.E16.m1.1.1.3.2.cmml">1</mn><mrow id="A1.E16.m1.1.1.3.3" xref="A1.E16.m1.1.1.3.3.cmml"><mn id="A1.E16.m1.1.1.3.3.2" xref="A1.E16.m1.1.1.3.3.2.cmml">1</mn><mo id="A1.E16.m1.1.1.3.3.1" xref="A1.E16.m1.1.1.3.3.1.cmml">−</mo><mi id="A1.E16.m1.1.1.3.3.3" xref="A1.E16.m1.1.1.3.3.3.cmml">δ</mi></mrow></mfrac></mrow><annotation-xml encoding="MathML-Content" id="A1.E16.m1.1b"><apply id="A1.E16.m1.1.1.cmml" xref="A1.E16.m1.1.1"><eq id="A1.E16.m1.1.1.1.cmml" xref="A1.E16.m1.1.1.1"></eq><apply id="A1.E16.m1.1.1.2.cmml" xref="A1.E16.m1.1.1.2"><times id="A1.E16.m1.1.1.2.1.cmml" xref="A1.E16.m1.1.1.2.1"></times><ci id="A1.E16.m1.1.1.2.2.cmml" xref="A1.E16.m1.1.1.2.2">𝐷</ci><ci id="A1.E16.m1.1.1.2.3.cmml" xref="A1.E16.m1.1.1.2.3">𝐿</ci><ci id="A1.E16.m1.1.1.2.4.cmml" xref="A1.E16.m1.1.1.2.4">𝑊</ci><ci id="A1.E16.m1.1.1.2.5.cmml" xref="A1.E16.m1.1.1.2.5">𝐴</ci></apply><apply id="A1.E16.m1.1.1.3.cmml" xref="A1.E16.m1.1.1.3"><divide id="A1.E16.m1.1.1.3.1.cmml" xref="A1.E16.m1.1.1.3"></divide><cn id="A1.E16.m1.1.1.3.2.cmml" type="integer" xref="A1.E16.m1.1.1.3.2">1</cn><apply id="A1.E16.m1.1.1.3.3.cmml" xref="A1.E16.m1.1.1.3.3"><minus id="A1.E16.m1.1.1.3.3.1.cmml" xref="A1.E16.m1.1.1.3.3.1"></minus><cn id="A1.E16.m1.1.1.3.3.2.cmml" type="integer" xref="A1.E16.m1.1.1.3.3.2">1</cn><ci id="A1.E16.m1.1.1.3.3.3.cmml" xref="A1.E16.m1.1.1.3.3.3">𝛿</ci></apply></apply></apply></annotation-xml><annotation encoding="application/x-tex" id="A1.E16.m1.1c">DLWA=\frac{1}{1-\delta}</annotation><annotation encoding="application/x-llamapun" id="A1.E16.m1.1d">italic_D italic_L italic_W italic_A = divide start_ARG 1 end_ARG start_ARG 1 - italic_δ end_ARG</annotation></semantics></math></td> <td class="ltx_eqn_cell ltx_eqn_center_padright"></td> </tr></tbody> </table> </div> </section> <section class="ltx_subsection" id="A1.SS3"> <h3 class="ltx_title ltx_title_subsection"> <span class="ltx_tag ltx_tag_subsection">A.3. </span>Validation of the DLWA Model with FDP-enabled CacheLib Empirical Result</h3> <figure class="ltx_figure" id="A1.F12"><img alt="Refer to caption" class="ltx_graphics ltx_centering ltx_img_landscape" height="463" id="A1.F12.g1" src="x15.png" width="581"/> <figcaption class="ltx_caption ltx_centering"><span class="ltx_tag ltx_tag_figure">Figure 12. </span>DLWA obtained from experiments using the KV Cache workload at 100% device utilization, 42GB RAM and varying SOC size in comparison to the DLWA obtained from the formula. We see minimal error in DLWA estimation using the formula.</figcaption> </figure> <div class="ltx_para" id="A1.SS3.p1"> <p class="ltx_p" id="A1.SS3.p1.1">Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A1.F12" title="Figure 12 ‣ A.3. Validation of the DLWA Model with FDP-enabled CacheLib Empirical Result ‣ Appendix A Theoretical Model of DLWA in FDP-enabled CacheLib ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">12</span></a> shows the minimal error in estimating CacheLib’s DLWA using the DLWA model (Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S4.SS2" title="4.2. Theoretical Analysis of FDP-enabled CacheLib DLWA and Carbon Emissions ‣ 4. Why FDP Matters for CacheLib and Hybrid Caches? ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">4.2</span></a>) in comparison to the observed DLWA obtained from experiments with the KV Cache workload. We see that at high SOC values the model diverges by a maximum of ~16% from the observed DLWA. We observe that at high SOC values, the model diverges from the empirical results because it assumes a uniform distribution of keys to SOC buckets. This is actually not the case due to skew causing the observed DLWA to be lower than the predicted DLWA. Note that we ran this experiment at 100% device utilization. At lower device utilization, the error will be similar to low SOC values due to low DLWA.</p> </div> </section> </section> <section class="ltx_appendix" id="A2"> <h2 class="ltx_title ltx_title_appendix"> <span class="ltx_tag ltx_tag_appendix">Appendix B </span>FDP-based Segregation Benefits with WO KV Cache Workload</h2> <figure class="ltx_figure ltx_minipage ltx_align_middle" id="A2.F13.1" style="width:411.9pt;"> <p class="ltx_p ltx_align_center" id="A2.F13.1.1"><span class="ltx_text" id="A2.F13.1.1.1"><img alt="Refer to caption" class="ltx_graphics ltx_img_landscape" height="546" id="A2.F13.1.1.1.g1" src="x16.png" width="789"/></span></p> <figcaption class="ltx_caption"><span class="ltx_tag ltx_tag_figure">Figure 13. </span>Effect of varying SSD utilization for caching with WO KV Cache Workload on DLWA and p99 read and write latency. FDP-based segregation results in a DLWA of 1 without affecting performance irrespective of device utilization. At higher utilizations, FDP improves p99 read and write latency.</figcaption> </figure> <div class="ltx_para" id="A2.p1"> <p class="ltx_p" id="A2.p1.1">Figure <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#A2.F13.1" title="Figure 13 ‣ Appendix B FDP-based Segregation Benefits with WO KV Cache Workload ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">13</span></a> shows the observed DLWA, p99 read and write latencies with FDP-enabled CacheLib using the WO KV Cache workload across different device utilization. We see similar trends as observed before with other workloads in Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS3" title="6.3. FDP-based segregation enables better SSD utilization without affecting performance ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">6.3</span></a> and Section <a class="ltx_ref" href="https://arxiv.org/html/2503.11665v1#S6.SS4" title="6.4. FDP-based segregation lowers DLWA with other write-intensive workloads ‣ 6. Evaluation ‣ Towards Efficient Flash Caches with Emerging NVMe Flexible Data Placement SSDs"><span class="ltx_text ltx_ref_tag">6.4</span></a> i.e., increasing gains in DLWA and lowering of p99 read and write latency at higher device utilizations. At 100% device utilization, FDP-based data segregation obtains 3.5x gains in DLWA, 2.2x gains in p99 read latency, and 9.5x gains in p99 write latency.</p> </div> <div class="ltx_pagination ltx_role_newpage"></div> </section> </article> </div> <footer class="ltx_page_footer"> <div class="ltx_page_logo">Generated on Fri Feb 21 12:29:22 2025 by <a class="ltx_LaTeXML_logo" href="http://dlmf.nist.gov/LaTeXML/"><span style="letter-spacing:-0.2em; margin-right:0.1em;">L<span class="ltx_font_smallcaps" style="position:relative; bottom:2.2pt;">a</span>T<span class="ltx_font_smallcaps" style="font-size:120%;position:relative; bottom:-0.2ex;">e</span></span><span style="font-size:90%; position:relative; bottom:-0.2ex;">XML</span><img alt="Mascot Sammy" src="data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAAsAAAAOCAYAAAD5YeaVAAAAAXNSR0IArs4c6QAAAAZiS0dEAP8A/wD/oL2nkwAAAAlwSFlzAAALEwAACxMBAJqcGAAAAAd0SU1FB9wKExQZLWTEaOUAAAAddEVYdENvbW1lbnQAQ3JlYXRlZCB3aXRoIFRoZSBHSU1Q72QlbgAAAdpJREFUKM9tkL+L2nAARz9fPZNCKFapUn8kyI0e4iRHSR1Kb8ng0lJw6FYHFwv2LwhOpcWxTjeUunYqOmqd6hEoRDhtDWdA8ApRYsSUCDHNt5ul13vz4w0vWCgUnnEc975arX6ORqN3VqtVZbfbTQC4uEHANM3jSqXymFI6yWazP2KxWAXAL9zCUa1Wy2tXVxheKA9YNoR8Pt+aTqe4FVVVvz05O6MBhqUIBGk8Hn8HAOVy+T+XLJfLS4ZhTiRJgqIoVBRFIoric47jPnmeB1mW/9rr9ZpSSn3Lsmir1fJZlqWlUonKsvwWwD8ymc/nXwVBeLjf7xEKhdBut9Hr9WgmkyGEkJwsy5eHG5vN5g0AKIoCAEgkEkin0wQAfN9/cXPdheu6P33fBwB4ngcAcByHJpPJl+fn54mD3Gg0NrquXxeLRQAAwzAYj8cwTZPwPH9/sVg8PXweDAauqqr2cDjEer1GJBLBZDJBs9mE4zjwfZ85lAGg2+06hmGgXq+j3+/DsixYlgVN03a9Xu8jgCNCyIegIAgx13Vfd7vdu+FweG8YRkjXdWy329+dTgeSJD3ieZ7RNO0VAXAPwDEAO5VKndi2fWrb9jWl9Esul6PZbDY9Go1OZ7PZ9z/lyuD3OozU2wAAAABJRU5ErkJggg=="/></a> </div></footer> </div> </body> </html>