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<button class="button is-small is-link">Go</button> </div> </div> </form> </div> </div> <ol class="breathe-horizontal" start="1"> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.12592">arXiv:2408.12592</a> <span> [<a href="https://arxiv.org/pdf/2408.12592">pdf</a>, <a href="https://arxiv.org/format/2408.12592">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Exposing Shadow Branches </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Pepi%2C+C">Chrysanthos Pepi</a>, <a href="/search/cs?searchtype=author&query=Godala%2C+B+R">Bhargav Reddy Godala</a>, <a href="/search/cs?searchtype=author&query=Tibrewala%2C+K">Krishnam Tibrewala</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=Jim%C3%A9nez%2C+D+A">Daniel A. Jim茅nez</a>, <a href="/search/cs?searchtype=author&query=Pokam%2C+G+A">Gilles A. Pokam</a>, <a href="/search/cs?searchtype=author&query=August%2C+D+I">David I. August</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.12592v1-abstract-short" style="display: inline;"> Modern processors implement a decoupled front-end in the form of Fetch Directed Instruction Prefetching (FDIP) to avoid front-end stalls. FDIP is driven by the Branch Prediction Unit (BPU), relying on the BPU's accuracy and branch target tracking structures to speculatively fetch instructions into the Instruction Cache (L1I). As data center applications become more complex, their code footprints a… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.12592v1-abstract-full').style.display = 'inline'; document.getElementById('2408.12592v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.12592v1-abstract-full" style="display: none;"> Modern processors implement a decoupled front-end in the form of Fetch Directed Instruction Prefetching (FDIP) to avoid front-end stalls. FDIP is driven by the Branch Prediction Unit (BPU), relying on the BPU's accuracy and branch target tracking structures to speculatively fetch instructions into the Instruction Cache (L1I). As data center applications become more complex, their code footprints also grow, resulting in an increase in Branch Target Buffer (BTB) misses. FDIP can alleviate L1I cache misses, but when it encounters a BTB miss, the BPU may not identify the current instruction as a branch to FDIP. This can prevent FDIP from prefetching or cause it to speculate down the wrong path, further polluting the L1I cache. We observe that the vast majority, 75%, of BTB-missing, unidentified branches are actually present in instruction cache lines that FDIP has previously fetched but, these missing branches have not yet been decoded and inserted into the BTB. This is because the instruction line is decoded from an entry point (which is the target of the previous taken branch) till an exit point (the taken branch). Branch instructions present in the ignored portion of the cache line we call them "Shadow Branches". Here we present Skeia, a novel shadow branch decoding technique that identifies and decodes unused bytes in cache lines fetched by FDIP, inserting them into a Shadow Branch Buffer (SBB). The SBB is accessed in parallel with the BTB, allowing FDIP to speculate despite a BTB miss. With a minimal storage state of 12.25KB, Skeia delivers a geomean speedup of ~5.7% over an 8K-entry BTB (78KB) and ~2% versus adding an equal amount of state to the BTB across 16 front-end bound applications. Since many branches stored in the SBB are unique compared to those in a similarly sized BTB, we consistently observe greater performance gains with Skeia across all examined sizes until saturation. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.12592v1-abstract-full').style.display = 'none'; document.getElementById('2408.12592v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 22 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">13 pages, 16 figures, Submitted to ASPLOS 2025</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2408.05912">arXiv:2408.05912</a> <span> [<a href="https://arxiv.org/pdf/2408.05912">pdf</a>, <a href="https://arxiv.org/format/2408.05912">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Correct Wrong Path </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Godala%2C+B+R">Bhargav Reddy Godala</a>, <a href="/search/cs?searchtype=author&query=Ramesh%2C+S+P">Sankara Prasad Ramesh</a>, <a href="/search/cs?searchtype=author&query=Tibrewala%2C+K">Krishnam Tibrewala</a>, <a href="/search/cs?searchtype=author&query=Pepi%2C+C">Chrysanthos Pepi</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Kanev%2C+S">Svilen Kanev</a>, <a href="/search/cs?searchtype=author&query=Pokam%2C+G+A">Gilles A. Pokam</a>, <a href="/search/cs?searchtype=author&query=Jim%C3%A9nez%2C+D+A">Daniel A. Jim茅nez</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=August%2C+D+I">David I. August</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2408.05912v1-abstract-short" style="display: inline;"> Modern OOO CPUs have very deep pipelines with large branch misprediction recovery penalties. Speculatively executed instructions on the wrong path can significantly change cache state, depending on speculation levels. Architects often employ trace-driven simulation models in the design exploration stage, which sacrifice precision for speed. Trace-driven simulators are orders of magnitude faster th… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.05912v1-abstract-full').style.display = 'inline'; document.getElementById('2408.05912v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2408.05912v1-abstract-full" style="display: none;"> Modern OOO CPUs have very deep pipelines with large branch misprediction recovery penalties. Speculatively executed instructions on the wrong path can significantly change cache state, depending on speculation levels. Architects often employ trace-driven simulation models in the design exploration stage, which sacrifice precision for speed. Trace-driven simulators are orders of magnitude faster than execution-driven models, reducing the often hundreds of thousands of simulation hours needed to explore new micro-architectural ideas. Despite this strong benefit of trace-driven simulation, these often fail to adequately model the consequences of wrong path because obtaining them is nontrivial. Prior works consider either a positive or negative impact of wrong path but not both. Here, we examine wrong path execution in simulation results and design a set of infrastructure for enabling wrong-path execution in a trace driven simulator. Our analysis shows the wrong path affects structures on both the instruction and data sides extensively, resulting in performance variations ranging from $-3.05$\% to $20.9$\% when ignoring wrong path. To benefit the research community and enhance the accuracy of simulators, we opened our traces and tracing utility in the hopes that industry can provide wrong-path traces generated by their internal simulators, enabling academic simulation without exposing industry IP. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2408.05912v1-abstract-full').style.display = 'none'; document.getElementById('2408.05912v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 11 August, 2024; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> August 2024. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">5 pages, 7 Figures, Submited to Computer Architecture Letters</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2305.02918">arXiv:2305.02918</a> <span> [<a href="https://arxiv.org/pdf/2305.02918">pdf</a>, <a href="https://arxiv.org/format/2305.02918">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Networking and Internet Architecture">cs.NI</span> </div> </div> <p class="title is-5 mathjax"> Flow Correlator: A Flow Table Cache Management Strategy </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=McHale%2C+L">Luke McHale</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V Gratz</a>, <a href="/search/cs?searchtype=author&query=Sprintson%2C+A">Alex Sprintson</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2305.02918v1-abstract-short" style="display: inline;"> Switching, routing, and security functions are the backbone of packet processing networks. Fast and efficient processing of packets requires maintaining the state of a large number of transient network connections. In particular, modern stateful firewalls, security monitoring devices, and software-defined networking (SDN) programmable dataplanes require maintaining stateful flow tables. These flow… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.02918v1-abstract-full').style.display = 'inline'; document.getElementById('2305.02918v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2305.02918v1-abstract-full" style="display: none;"> Switching, routing, and security functions are the backbone of packet processing networks. Fast and efficient processing of packets requires maintaining the state of a large number of transient network connections. In particular, modern stateful firewalls, security monitoring devices, and software-defined networking (SDN) programmable dataplanes require maintaining stateful flow tables. These flow tables often grow much larger than can be expected to fit within on-chip memory, requiring a managed caching layer to maintain performance. This paper focuses on improving the efficiency of caching, an important architectural component of the packet processing data planes. We present a novel predictive approach to network flow table cache management. Our approach leverages a Hashed Perceptron binary classifier as well as an iterative approach to feature selection and ranking to improve the reliability and performance of the data plane caches. We validate the efficiency of the proposed techniques through extensive experimentation using real-world data sets. Our numerical results demonstrate that our techniques improve the reliability and performance of flow-centric packet processing architectures. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2305.02918v1-abstract-full').style.display = 'none'; document.getElementById('2305.02918v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 4 May, 2023; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> May 2023. </p> <p class="comments is-size-7"> <span class="has-text-black-bis has-text-weight-semibold">Comments:</span> <span class="has-text-grey-dark mathjax">26 pages, 22 figures</span> </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2210.14324">arXiv:2210.14324</a> <span> [<a href="https://arxiv.org/pdf/2210.14324">pdf</a>, <a href="https://arxiv.org/format/2210.14324">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> The Championship Simulator: Architectural Simulation for Education and Competition </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Gober%2C+N">Nathan Gober</a>, <a href="/search/cs?searchtype=author&query=Chacon%2C+G">Gino Chacon</a>, <a href="/search/cs?searchtype=author&query=Wang%2C+L">Lei Wang</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=Jimenez%2C+D+A">Daniel A. Jimenez</a>, <a href="/search/cs?searchtype=author&query=Teran%2C+E">Elvira Teran</a>, <a href="/search/cs?searchtype=author&query=Pugsley%2C+S">Seth Pugsley</a>, <a href="/search/cs?searchtype=author&query=Kim%2C+J">Jinchun Kim</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2210.14324v1-abstract-short" style="display: inline;"> Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their par… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.14324v1-abstract-full').style.display = 'inline'; document.getElementById('2210.14324v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2210.14324v1-abstract-full" style="display: none;"> Recent years have seen a dramatic increase in the microarchitectural complexity of processors. This increase in complexity presents a twofold challenge for the field of computer architecture. First, no individual architect can fully comprehend the complexity of the entire microarchitecture of the core. This leads to increasingly specialized architects, who treat parts of the core outside their particular expertise as black boxes. Second, with increasing complexity, the field becomes decreasingly accessible to new students of the field. When learning core microarchitecture, new students must first learn the big picture of how the system works in order to understand how the pieces all fit together. The tools used to study microarchitecture experience a similar struggle. As with the microarchitectures they simulate, an increase in complexity reduces accessibility to new users. In this work, we present ChampSim. ChampSim uses a modular design and configurable structure to achieve a low barrier to entry into the field of microarchitecural simulation. ChampSim has shown itself to be useful in multiple areas of research, competition, and education. In this way, we seek to promote access and inclusion despite the increasing complexity of the field of computer architecture. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.14324v1-abstract-full').style.display = 'none'; document.getElementById('2210.14324v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 25 October, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2210.00058">arXiv:2210.00058</a> <span> [<a href="https://arxiv.org/pdf/2210.00058">pdf</a>, <a href="https://arxiv.org/format/2210.00058">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Cryptography and Security">cs.CR</span> <span class="tag is-small is-grey tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> </div> <p class="title is-5 mathjax"> Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Chacon%2C+G+A">Gino A. Chacon</a>, <a href="/search/cs?searchtype=author&query=Williams%2C+C">Charles Williams</a>, <a href="/search/cs?searchtype=author&query=Knechtel%2C+J">Johann Knechtel</a>, <a href="/search/cs?searchtype=author&query=Sinanoglu%2C+O">Ozgur Sinanoglu</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2210.00058v1-abstract-short" style="display: inline;"> As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify dat… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.00058v1-abstract-full').style.display = 'inline'; document.getElementById('2210.00058v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2210.00058v1-abstract-full" style="display: none;"> As industry moves toward chiplet-based designs, the insertion of hardware Trojans poses a significant threat to the security of these systems. These systems rely heavily on cache coherence for coherent data communication, making coherence an attractive target. Critically, unlike prior work, which focuses only on malicious packet modifications, a Trojan attack that exploits coherence can modify data in memory that was never touched and is not owned by the chiplet which contains the Trojan. Further, the Trojan need not even be physically between the victim and the memory controller to attack the victim's memory transactions. Here, we explore the fundamental attack vectors possible in chiplet-based systems and provide an example Trojan implementation capable of directly modifying victim data in memory. This work aims to highlight the need for developing mechanisms that can protect and secure the coherence scheme from these forms of attacks. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2210.00058v1-abstract-full').style.display = 'none'; document.getElementById('2210.00058v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 30 September, 2022; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> October 2022. </p> </li> <li class="arxiv-result"> <div class="is-marginless"> <p class="list-title is-inline-block"><a href="https://arxiv.org/abs/2011.04567">arXiv:2011.04567</a> <span> [<a href="https://arxiv.org/pdf/2011.04567">pdf</a>, <a href="https://arxiv.org/format/2011.04567">other</a>] </span> </p> <div class="tags is-inline-block"> <span class="tag is-small is-link tooltip is-tooltip-top" data-tooltip="Hardware Architecture">cs.AR</span> </div> <div class="is-inline-block" style="margin-left: 0.5rem"> <div class="tags has-addons"> <span class="tag is-dark is-size-7">doi</span> <span class="tag is-light is-size-7"><a class="" href="https://doi.org/10.1109/FPL53798.2021.00039">10.1109/FPL53798.2021.00039 <i class="fa fa-external-link" aria-hidden="true"></i></a></span> </div> </div> </div> <p class="title is-5 mathjax"> FPGA-based Hyrbid Memory Emulation System </p> <p class="authors"> <span class="search-hit">Authors:</span> <a href="/search/cs?searchtype=author&query=Wen%2C+F">Fei Wen</a>, <a href="/search/cs?searchtype=author&query=Qin%2C+M">Mian Qin</a>, <a href="/search/cs?searchtype=author&query=Gratz%2C+P+V">Paul V. Gratz</a>, <a href="/search/cs?searchtype=author&query=Reddy%2C+A+L+N">A. L. Narasimha Reddy</a> </p> <p class="abstract mathjax"> <span class="has-text-black-bis has-text-weight-semibold">Abstract</span>: <span class="abstract-short has-text-grey-dark mathjax" id="2011.04567v1-abstract-short" style="display: inline;"> Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of applications. Emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as… <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2011.04567v1-abstract-full').style.display = 'inline'; document.getElementById('2011.04567v1-abstract-short').style.display = 'none';">▽ More</a> </span> <span class="abstract-full has-text-grey-dark mathjax" id="2011.04567v1-abstract-full" style="display: none;"> Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of applications. Emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of two memory classes point towards the design of hybrid memory systems containing multiple classes of main memory. In the iterative and incremental development of new architectures, the timeliness of simulation completion is critical to project progression. Hence, a highly efficient simulation method is needed to evaluate the performance of different hybrid memory system designs. Design exploration for hybrid memory systems is challenging, because it requires emulation of the full system stack, including the OS, memory controller, and interconnect. Moreover, benchmark applications for memory performance test typically have much larger working sets, thus taking even longer simulation warm-up period. In this paper, we propose a FPGA-based hybrid memory system emulation platform. We target at the mobile computing system, which is sensitive to energy consumption and is likely to adopt NVM for its power efficiency. Here, because the focus of our platform is on the design of the hybrid memory system, we leverage the on-board hard IP ARM processors to both improve simulation performance while improving accuracy of the results. Thus, users can implement their data placement/migration policies with the FPGA logic elements and evaluate new designs quickly and effectively. Results show that our emulation platform provides a speedup of 9280x in simulation time compared to the software counterpart Gem5. <a class="is-size-7" style="white-space: nowrap;" onclick="document.getElementById('2011.04567v1-abstract-full').style.display = 'none'; document.getElementById('2011.04567v1-abstract-short').style.display = 'inline';">△ Less</a> </span> </p> <p class="is-size-7"><span class="has-text-black-bis has-text-weight-semibold">Submitted</span> 9 November, 2020; <span class="has-text-black-bis has-text-weight-semibold">originally announced</span> November 2020. </p> </li> </ol> <div class="is-hidden-tablet">  <span class="help" style="display: inline-block;"><a href="https://github.com/arXiv/arxiv-search/releases">Search v0.5.6 released 2020-02-24</a>  </span> </div> </div> </main> <footer> <div class="columns is-desktop" role="navigation" aria-label="Secondary">  <div class="column"> <div class="columns"> <div class="column"> <ul class="nav-spaced"> <li><a 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