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class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Transistor_CPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>Transistor CPUs</span> </div> </a> <ul id="toc-Transistor_CPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Small-scale_integration_CPUs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Small-scale_integration_CPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Small-scale integration CPUs</span> </div> </a> <ul id="toc-Small-scale_integration_CPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Large-scale_integration_CPUs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Large-scale_integration_CPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Large-scale integration CPUs</span> </div> </a> <ul id="toc-Large-scale_integration_CPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Microprocessors" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Microprocessors"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Microprocessors</span> </div> </a> <ul id="toc-Microprocessors-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Operation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Operation"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Operation</span> </div> </a> <button aria-controls="toc-Operation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Operation subsection</span> </button> <ul id="toc-Operation-sublist" class="vector-toc-list"> <li id="toc-Fetch" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Fetch"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Fetch</span> </div> </a> <ul id="toc-Fetch-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Decode" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Decode"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.2</span> <span>Decode</span> </div> </a> <ul id="toc-Decode-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Execute" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Execute"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.3</span> <span>Execute</span> </div> </a> <ul id="toc-Execute-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Structure_and_implementation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Structure_and_implementation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Structure and implementation</span> </div> </a> <button aria-controls="toc-Structure_and_implementation-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Structure and implementation subsection</span> </button> <ul id="toc-Structure_and_implementation-sublist" class="vector-toc-list"> <li id="toc-Control_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Control_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Control unit</span> </div> </a> <ul id="toc-Control_unit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Arithmetic_logic_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Arithmetic_logic_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Arithmetic logic unit</span> </div> </a> <ul id="toc-Arithmetic_logic_unit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Address_generation_unit" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Address_generation_unit"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Address generation unit</span> </div> </a> <ul id="toc-Address_generation_unit-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_management_unit_(MMU)" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Memory_management_unit_(MMU)"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Memory management unit (MMU)</span> </div> </a> <ul id="toc-Memory_management_unit_(MMU)-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Cache" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Cache"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.5</span> <span>Cache</span> </div> </a> <ul id="toc-Cache-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Clock_rate" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Clock_rate"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.6</span> <span>Clock rate</span> </div> </a> <ul id="toc-Clock_rate-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Clockless_CPUs" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Clockless_CPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.7</span> <span>Clockless CPUs</span> </div> </a> <ul id="toc-Clockless_CPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Voltage_regulator_module" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Voltage_regulator_module"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.8</span> <span>Voltage regulator module</span> </div> </a> <ul id="toc-Voltage_regulator_module-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Integer_range" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Integer_range"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.9</span> <span>Integer range</span> </div> </a> <ul id="toc-Integer_range-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Parallelism" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Parallelism"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10</span> <span>Parallelism</span> </div> </a> <ul id="toc-Parallelism-sublist" class="vector-toc-list"> <li id="toc-Instruction-level_parallelism" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Instruction-level_parallelism"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10.1</span> <span>Instruction-level parallelism</span> </div> </a> <ul id="toc-Instruction-level_parallelism-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Task-level_parallelism" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Task-level_parallelism"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10.2</span> <span>Task-level parallelism</span> </div> </a> <ul id="toc-Task-level_parallelism-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Data_parallelism" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Data_parallelism"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.10.3</span> <span>Data parallelism</span> </div> </a> <ul id="toc-Data_parallelism-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Hardware_performance_counter" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Hardware_performance_counter"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.11</span> <span>Hardware performance counter</span> </div> </a> <ul id="toc-Hardware_performance_counter-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Privileged_modes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Privileged_modes"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Privileged modes</span> </div> </a> <ul id="toc-Privileged_modes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Performance" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Performance"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Performance</span> </div> </a> <ul id="toc-Performance-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " aria-label="Toggle the table of contents" > <label id="vector-page-titlebar-toc-label" for="vector-page-titlebar-toc-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--icon-only " aria-hidden="true" ><span class="vector-icon mw-ui-icon-listBullet mw-ui-icon-wikimedia-listBullet"></span> <span class="vector-dropdown-label-text">Toggle the table of contents</span> </label> <div class="vector-dropdown-content"> <div id="vector-page-titlebar-toc-unpinned-container" class="vector-unpinned-container"> </div> </div> </div> </nav> <h1 id="firstHeading" class="firstHeading mw-first-heading"><span class="mw-page-title-main">Central processing unit</span></h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 111 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-111" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">111 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-af mw-list-item"><a href="https://af.wikipedia.org/wiki/Sentrale_verwerkingseenheid" title="Sentrale verwerkingseenheid – Afrikaans" lang="af" hreflang="af" data-title="Sentrale verwerkingseenheid" data-language-autonym="Afrikaans" data-language-local-name="Afrikaans" class="interlanguage-link-target"><span>Afrikaans</span></a></li><li class="interlanguage-link interwiki-als mw-list-item"><a href="https://als.wikipedia.org/wiki/Central_Processing_Unit" title="Central Processing Unit – Alemannic" lang="gsw" hreflang="gsw" data-title="Central Processing Unit" data-language-autonym="Alemannisch" data-language-local-name="Alemannic" class="interlanguage-link-target"><span>Alemannisch</span></a></li><li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D9%88%D8%AD%D8%AF%D8%A9_%D9%85%D8%B9%D8%A7%D9%84%D8%AC%D8%A9_%D9%85%D8%B1%D9%83%D8%B2%D9%8A%D8%A9" title="وحدة معالجة مركزية – Arabic" lang="ar" hreflang="ar" data-title="وحدة معالجة مركزية" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-an mw-list-item"><a href="https://an.wikipedia.org/wiki/Unidat_central_de_procesamiento" title="Unidat central de procesamiento – Aragonese" lang="an" hreflang="an" data-title="Unidat central de procesamiento" data-language-autonym="Aragonés" data-language-local-name="Aragonese" class="interlanguage-link-target"><span>Aragonés</span></a></li><li class="interlanguage-link interwiki-hyw mw-list-item"><a href="https://hyw.wikipedia.org/wiki/%D5%84%D5%B7%D5%A1%D5%AF%D5%AB%D5%B9" title="Մշակիչ – Western Armenian" lang="hyw" hreflang="hyw" data-title="Մշակիչ" data-language-autonym="Արեւմտահայերէն" data-language-local-name="Western Armenian" class="interlanguage-link-target"><span>Արեւմտահայերէն</span></a></li><li class="interlanguage-link interwiki-ast mw-list-item"><a href="https://ast.wikipedia.org/wiki/Unid%C3%A1_central_de_procesamientu" title="Unidá central de procesamientu – Asturian" lang="ast" hreflang="ast" data-title="Unidá central de procesamientu" data-language-autonym="Asturianu" data-language-local-name="Asturian" class="interlanguage-link-target"><span>Asturianu</span></a></li><li class="interlanguage-link interwiki-az mw-list-item"><a href="https://az.wikipedia.org/wiki/M%C9%99rk%C9%99zi_prosessor" title="Mərkəzi prosessor – Azerbaijani" lang="az" hreflang="az" data-title="Mərkəzi prosessor" data-language-autonym="Azərbaycanca" data-language-local-name="Azerbaijani" class="interlanguage-link-target"><span>Azərbaycanca</span></a></li><li class="interlanguage-link interwiki-azb mw-list-item"><a href="https://azb.wikipedia.org/wiki/%D9%85%D8%B1%DA%A9%D8%B2%DB%8C_%D8%A7%DB%8C%D8%B4%D9%84%D9%85%DA%86%DB%8C" title="مرکزی ایشلمچی – South Azerbaijani" lang="azb" hreflang="azb" data-title="مرکزی ایشلمچی" data-language-autonym="تۆرکجه" data-language-local-name="South Azerbaijani" class="interlanguage-link-target"><span>تۆرکجه</span></a></li><li class="interlanguage-link interwiki-bn mw-list-item"><a href="https://bn.wikipedia.org/wiki/%E0%A6%95%E0%A7%87%E0%A6%A8%E0%A7%8D%E0%A6%A6%E0%A7%8D%E0%A6%B0%E0%A7%80%E0%A6%AF%E0%A6%BC_%E0%A6%AA%E0%A7%8D%E0%A6%B0%E0%A6%95%E0%A7%8D%E0%A6%B0%E0%A6%BF%E0%A6%AF%E0%A6%BC%E0%A6%BE%E0%A6%9C%E0%A6%BE%E0%A6%A4%E0%A6%95%E0%A6%B0%E0%A6%A3_%E0%A6%87%E0%A6%89%E0%A6%A8%E0%A6%BF%E0%A6%9F" title="কেন্দ্রীয় প্রক্রিয়াজাতকরণ ইউনিট – Bangla" lang="bn" hreflang="bn" data-title="কেন্দ্রীয় প্রক্রিয়াজাতকরণ ইউনিট" data-language-autonym="বাংলা" data-language-local-name="Bangla" class="interlanguage-link-target"><span>বাংলা</span></a></li><li class="interlanguage-link interwiki-zh-min-nan mw-list-item"><a href="https://zh-min-nan.wikipedia.org/wiki/Tiong-iong_chh%C3%B9-l%C3%AD_tan-go%C3%A2n" title="Tiong-iong chhù-lí tan-goân – Minnan" lang="nan" hreflang="nan" data-title="Tiong-iong chhù-lí tan-goân" data-language-autonym="閩南語 / Bân-lâm-gú" data-language-local-name="Minnan" class="interlanguage-link-target"><span>閩南語 / Bân-lâm-gú</span></a></li><li class="interlanguage-link interwiki-ba mw-list-item"><a href="https://ba.wikipedia.org/wiki/%D2%AE%D2%99%D3%99%D0%BA_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Үҙәк процессор – Bashkir" lang="ba" hreflang="ba" data-title="Үҙәк процессор" data-language-autonym="Башҡортса" data-language-local-name="Bashkir" class="interlanguage-link-target"><span>Башҡортса</span></a></li><li class="interlanguage-link interwiki-be mw-list-item"><a href="https://be.wikipedia.org/wiki/%D0%A6%D1%8D%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D1%8C%D0%BD%D1%8B_%D0%BF%D1%80%D0%B0%D1%86%D1%8D%D1%81%D0%B0%D1%80" title="Цэнтральны працэсар – Belarusian" lang="be" hreflang="be" data-title="Цэнтральны працэсар" data-language-autonym="Беларуская" data-language-local-name="Belarusian" class="interlanguage-link-target"><span>Беларуская</span></a></li><li class="interlanguage-link interwiki-be-x-old mw-list-item"><a href="https://be-tarask.wikipedia.org/wiki/%D0%A6%D1%8D%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D1%8C%D0%BD%D1%8B_%D0%BF%D1%80%D0%B0%D1%86%D1%8D%D1%81%D0%B0%D1%80" title="Цэнтральны працэсар – Belarusian (Taraškievica orthography)" lang="be-tarask" hreflang="be-tarask" data-title="Цэнтральны працэсар" data-language-autonym="Беларуская (тарашкевіца)" data-language-local-name="Belarusian (Taraškievica orthography)" class="interlanguage-link-target"><span>Беларуская (тарашкевіца)</span></a></li><li class="interlanguage-link interwiki-bg mw-list-item"><a href="https://bg.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D0%B5%D0%BD_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Централен процесор – Bulgarian" lang="bg" hreflang="bg" data-title="Централен процесор" data-language-autonym="Български" data-language-local-name="Bulgarian" class="interlanguage-link-target"><span>Български</span></a></li><li class="interlanguage-link interwiki-bo mw-list-item"><a href="https://bo.wikipedia.org/wiki/CPU" title="CPU – Tibetan" lang="bo" hreflang="bo" data-title="CPU" data-language-autonym="བོད་ཡིག" data-language-local-name="Tibetan" class="interlanguage-link-target"><span>བོད་ཡིག</span></a></li><li class="interlanguage-link interwiki-bs mw-list-item"><a href="https://bs.wikipedia.org/wiki/Centralna_procesorska_jedinica" title="Centralna procesorska jedinica – Bosnian" lang="bs" hreflang="bs" data-title="Centralna procesorska jedinica" data-language-autonym="Bosanski" data-language-local-name="Bosnian" class="interlanguage-link-target"><span>Bosanski</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Unitat_central_de_processament" title="Unitat central de processament – Catalan" lang="ca" hreflang="ca" data-title="Unitat central de processament" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Centr%C3%A1ln%C3%AD_procesorov%C3%A1_jednotka" title="Centrální procesorová jednotka – Czech" lang="cs" hreflang="cs" data-title="Centrální procesorová jednotka" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-cy mw-list-item"><a href="https://cy.wikipedia.org/wiki/Uned_brosesu_ganolog" title="Uned brosesu ganolog – Welsh" lang="cy" hreflang="cy" data-title="Uned brosesu ganolog" data-language-autonym="Cymraeg" data-language-local-name="Welsh" class="interlanguage-link-target"><span>Cymraeg</span></a></li><li class="interlanguage-link interwiki-da mw-list-item"><a href="https://da.wikipedia.org/wiki/CPU" title="CPU – Danish" lang="da" hreflang="da" data-title="CPU" data-language-autonym="Dansk" data-language-local-name="Danish" class="interlanguage-link-target"><span>Dansk</span></a></li><li class="interlanguage-link interwiki-de badge-Q70894304 mw-list-item" title=""><a href="https://de.wikipedia.org/wiki/Hauptprozessor" title="Hauptprozessor – German" lang="de" hreflang="de" data-title="Hauptprozessor" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Keskseade" title="Keskseade – Estonian" lang="et" hreflang="et" data-title="Keskseade" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/%CE%9A%CE%B5%CE%BD%CF%84%CF%81%CE%B9%CE%BA%CE%AE_%CE%9C%CE%BF%CE%BD%CE%AC%CE%B4%CE%B1_%CE%95%CF%80%CE%B5%CE%BE%CE%B5%CF%81%CE%B3%CE%B1%CF%83%CE%AF%CE%B1%CF%82" title="Κεντρική Μονάδα Επεξεργασίας – Greek" lang="el" hreflang="el" data-title="Κεντρική Μονάδα Επεξεργασίας" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Unidad_central_de_procesamiento" title="Unidad central de procesamiento – Spanish" lang="es" hreflang="es" data-title="Unidad central de procesamiento" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-eo mw-list-item"><a href="https://eo.wikipedia.org/wiki/%C4%88efprocesoro" title="Ĉefprocesoro – Esperanto" lang="eo" hreflang="eo" data-title="Ĉefprocesoro" data-language-autonym="Esperanto" data-language-local-name="Esperanto" class="interlanguage-link-target"><span>Esperanto</span></a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/Prozesatzeko_unitate_zentral" title="Prozesatzeko unitate zentral – Basque" lang="eu" hreflang="eu" data-title="Prozesatzeko unitate zentral" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target"><span>Euskara</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D9%88%D8%A7%D8%AD%D8%AF_%D9%BE%D8%B1%D8%AF%D8%A7%D8%B2%D8%B4_%D9%85%D8%B1%DA%A9%D8%B2%DB%8C" title="واحد پردازش مرکزی – Persian" lang="fa" hreflang="fa" data-title="واحد پردازش مرکزی" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-hif mw-list-item"><a href="https://hif.wikipedia.org/wiki/Central_processing_unit" title="Central processing unit – Fiji Hindi" lang="hif" hreflang="hif" data-title="Central processing unit" data-language-autonym="Fiji Hindi" data-language-local-name="Fiji Hindi" class="interlanguage-link-target"><span>Fiji Hindi</span></a></li><li class="interlanguage-link interwiki-fr badge-Q70894304 mw-list-item" title=""><a href="https://fr.wikipedia.org/wiki/CPU" title="CPU – French" lang="fr" hreflang="fr" data-title="CPU" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-fur mw-list-item"><a href="https://fur.wikipedia.org/wiki/CPU" title="CPU – Friulian" lang="fur" hreflang="fur" data-title="CPU" data-language-autonym="Furlan" data-language-local-name="Friulian" class="interlanguage-link-target"><span>Furlan</span></a></li><li class="interlanguage-link interwiki-ga mw-list-item"><a href="https://ga.wikipedia.org/wiki/L%C3%A1raonad_pr%C3%B3ise%C3%A1la" title="Láraonad próiseála – Irish" lang="ga" hreflang="ga" data-title="Láraonad próiseála" data-language-autonym="Gaeilge" data-language-local-name="Irish" class="interlanguage-link-target"><span>Gaeilge</span></a></li><li class="interlanguage-link interwiki-gl mw-list-item"><a href="https://gl.wikipedia.org/wiki/Unidade_central_de_procesamento" title="Unidade central de procesamento – Galician" lang="gl" hreflang="gl" data-title="Unidade central de procesamento" data-language-autonym="Galego" data-language-local-name="Galician" class="interlanguage-link-target"><span>Galego</span></a></li><li class="interlanguage-link interwiki-ki mw-list-item"><a href="https://ki.wikipedia.org/wiki/Cipiyu" title="Cipiyu – Kikuyu" lang="ki" hreflang="ki" data-title="Cipiyu" data-language-autonym="Gĩkũyũ" data-language-local-name="Kikuyu" class="interlanguage-link-target"><span>Gĩkũyũ</span></a></li><li class="interlanguage-link interwiki-glk mw-list-item"><a href="https://glk.wikipedia.org/wiki/%D8%B3%DB%8C_%D9%BE%DB%8C_%DB%8C%D9%88" title="سی پی یو – Gilaki" lang="glk" hreflang="glk" data-title="سی پی یو" data-language-autonym="گیلکی" data-language-local-name="Gilaki" class="interlanguage-link-target"><span>گیلکی</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%A4%91%EC%95%99_%EC%B2%98%EB%A6%AC_%EC%9E%A5%EC%B9%98" title="중앙 처리 장치 – Korean" lang="ko" hreflang="ko" data-title="중앙 처리 장치" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hy mw-list-item"><a href="https://hy.wikipedia.org/wiki/%D5%84%D5%B7%D5%A1%D5%AF%D5%AB%D5%B9" title="Մշակիչ – Armenian" lang="hy" hreflang="hy" data-title="Մշակիչ" data-language-autonym="Հայերեն" data-language-local-name="Armenian" class="interlanguage-link-target"><span>Հայերեն</span></a></li><li class="interlanguage-link interwiki-hi mw-list-item"><a href="https://hi.wikipedia.org/wiki/%E0%A4%B8%E0%A5%87%E0%A4%82%E0%A4%9F%E0%A5%8D%E0%A4%B0%E0%A4%B2_%E0%A4%AA%E0%A5%8D%E0%A4%B0%E0%A5%8B%E0%A4%B8%E0%A5%87%E0%A4%B8%E0%A4%BF%E0%A4%82%E0%A4%97_%E0%A4%AF%E0%A5%82%E0%A4%A8%E0%A4%BF%E0%A4%9F" title="सेंट्रल प्रोसेसिंग यूनिट – Hindi" lang="hi" hreflang="hi" data-title="सेंट्रल प्रोसेसिंग यूनिट" data-language-autonym="हिन्दी" data-language-local-name="Hindi" class="interlanguage-link-target"><span>हिन्दी</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Procesor_(ra%C4%8Dunarstvo)" title="Procesor (računarstvo) – Croatian" lang="hr" hreflang="hr" data-title="Procesor (računarstvo)" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Unit_Pemroses_Sentral" title="Unit Pemroses Sentral – Indonesian" lang="id" hreflang="id" data-title="Unit Pemroses Sentral" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-ia mw-list-item"><a href="https://ia.wikipedia.org/wiki/Processor_central" title="Processor central – Interlingua" lang="ia" hreflang="ia" data-title="Processor central" data-language-autonym="Interlingua" data-language-local-name="Interlingua" class="interlanguage-link-target"><span>Interlingua</span></a></li><li class="interlanguage-link interwiki-zu mw-list-item"><a href="https://zu.wikipedia.org/wiki/Isidludlungi_esimqoka" title="Isidludlungi esimqoka – Zulu" lang="zu" hreflang="zu" data-title="Isidludlungi esimqoka" data-language-autonym="IsiZulu" data-language-local-name="Zulu" class="interlanguage-link-target"><span>IsiZulu</span></a></li><li class="interlanguage-link interwiki-is mw-list-item"><a href="https://is.wikipedia.org/wiki/Mi%C3%B0verk" title="Miðverk – Icelandic" lang="is" hreflang="is" data-title="Miðverk" data-language-autonym="Íslenska" data-language-local-name="Icelandic" class="interlanguage-link-target"><span>Íslenska</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/CPU" title="CPU – Italian" lang="it" hreflang="it" data-title="CPU" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/%D7%9E%D7%A2%D7%91%D7%93" title="מעבד – Hebrew" lang="he" hreflang="he" data-title="מעבד" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target"><span>עברית</span></a></li><li class="interlanguage-link interwiki-jv mw-list-item"><a href="https://jv.wikipedia.org/wiki/Piranti_Pamros%C3%A9san_Sentral" title="Piranti Pamrosésan Sentral – Javanese" lang="jv" hreflang="jv" data-title="Piranti Pamrosésan Sentral" data-language-autonym="Jawa" data-language-local-name="Javanese" class="interlanguage-link-target"><span>Jawa</span></a></li><li class="interlanguage-link interwiki-kn mw-list-item"><a href="https://kn.wikipedia.org/wiki/%E0%B2%95%E0%B3%87%E0%B2%82%E0%B2%A6%E0%B3%8D%E0%B2%B0_%E0%B2%B8%E0%B2%82%E0%B2%B8%E0%B3%8D%E0%B2%95%E0%B2%B0%E0%B2%A3_%E0%B2%98%E0%B2%9F%E0%B2%95" title="ಕೇಂದ್ರ ಸಂಸ್ಕರಣ ಘಟಕ – Kannada" lang="kn" hreflang="kn" data-title="ಕೇಂದ್ರ ಸಂಸ್ಕರಣ ಘಟಕ" data-language-autonym="ಕನ್ನಡ" data-language-local-name="Kannada" class="interlanguage-link-target"><span>ಕನ್ನಡ</span></a></li><li class="interlanguage-link interwiki-ka mw-list-item"><a href="https://ka.wikipedia.org/wiki/%E1%83%AA%E1%83%94%E1%83%9C%E1%83%A2%E1%83%A0%E1%83%90%E1%83%9A%E1%83%A3%E1%83%A0%E1%83%98_%E1%83%9E%E1%83%A0%E1%83%9D%E1%83%AA%E1%83%94%E1%83%A1%E1%83%9D%E1%83%A0%E1%83%98" title="ცენტრალური პროცესორი – Georgian" lang="ka" hreflang="ka" data-title="ცენტრალური პროცესორი" data-language-autonym="ქართული" data-language-local-name="Georgian" class="interlanguage-link-target"><span>ქართული</span></a></li><li class="interlanguage-link interwiki-kk mw-list-item"><a href="https://kk.wikipedia.org/wiki/%D0%9E%D1%80%D1%82%D0%B0%D0%BB%D1%8B%D2%9B_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Орталық процессор – Kazakh" lang="kk" hreflang="kk" data-title="Орталық процессор" data-language-autonym="Қазақша" data-language-local-name="Kazakh" class="interlanguage-link-target"><span>Қазақша</span></a></li><li class="interlanguage-link interwiki-sw mw-list-item"><a href="https://sw.wikipedia.org/wiki/Kichakato_kikuu" title="Kichakato kikuu – Swahili" lang="sw" hreflang="sw" data-title="Kichakato kikuu" data-language-autonym="Kiswahili" data-language-local-name="Swahili" class="interlanguage-link-target"><span>Kiswahili</span></a></li><li class="interlanguage-link interwiki-ku mw-list-item"><a href="https://ku.wikipedia.org/wiki/Yekeya_p%C3%AAvajoy%C3%AA_ya_navend%C3%AE" title="Yekeya pêvajoyê ya navendî – Kurdish" lang="ku" hreflang="ku" data-title="Yekeya pêvajoyê ya navendî" data-language-autonym="Kurdî" data-language-local-name="Kurdish" class="interlanguage-link-target"><span>Kurdî</span></a></li><li class="interlanguage-link interwiki-ky mw-list-item"><a href="https://ky.wikipedia.org/wiki/%D0%91%D0%BE%D1%80%D0%B1%D0%BE%D1%80%D0%B4%D1%83%D0%BA_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Борбордук процессор – Kyrgyz" lang="ky" hreflang="ky" data-title="Борбордук процессор" data-language-autonym="Кыргызча" data-language-local-name="Kyrgyz" class="interlanguage-link-target"><span>Кыргызча</span></a></li><li class="interlanguage-link interwiki-lo mw-list-item"><a href="https://lo.wikipedia.org/wiki/%E0%BA%8A%E0%BA%B5%E0%BA%9E%E0%BA%B5%E0%BA%A2%E0%BA%B9" title="ຊີພີຢູ – Lao" lang="lo" hreflang="lo" data-title="ຊີພີຢູ" data-language-autonym="ລາວ" data-language-local-name="Lao" class="interlanguage-link-target"><span>ລາວ</span></a></li><li class="interlanguage-link interwiki-la mw-list-item"><a href="https://la.wikipedia.org/wiki/Procestrum_princeps" title="Procestrum princeps – Latin" lang="la" hreflang="la" data-title="Procestrum princeps" data-language-autonym="Latina" data-language-local-name="Latin" class="interlanguage-link-target"><span>Latina</span></a></li><li class="interlanguage-link interwiki-lv mw-list-item"><a href="https://lv.wikipedia.org/wiki/Centr%C4%81lais_procesors" title="Centrālais procesors – Latvian" lang="lv" hreflang="lv" data-title="Centrālais procesors" data-language-autonym="Latviešu" data-language-local-name="Latvian" class="interlanguage-link-target"><span>Latviešu</span></a></li><li class="interlanguage-link interwiki-lt mw-list-item"><a href="https://lt.wikipedia.org/wiki/Centrinis_procesorius" title="Centrinis procesorius – Lithuanian" lang="lt" hreflang="lt" data-title="Centrinis procesorius" data-language-autonym="Lietuvių" data-language-local-name="Lithuanian" class="interlanguage-link-target"><span>Lietuvių</span></a></li><li class="interlanguage-link interwiki-ln mw-list-item"><a href="https://ln.wikipedia.org/wiki/B%C9%94ng%C9%94%CC%81_(elektron%C3%ADki)" title="Bɔngɔ́ (elektroníki) – Lingala" lang="ln" hreflang="ln" data-title="Bɔngɔ́ (elektroníki)" data-language-autonym="Lingála" data-language-local-name="Lingala" class="interlanguage-link-target"><span>Lingála</span></a></li><li class="interlanguage-link interwiki-lmo mw-list-item"><a href="https://lmo.wikipedia.org/wiki/Central_processing_unit" title="Central processing unit – Lombard" lang="lmo" hreflang="lmo" data-title="Central processing unit" data-language-autonym="Lombard" data-language-local-name="Lombard" class="interlanguage-link-target"><span>Lombard</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Central_processing_unit" title="Central processing unit – Hungarian" lang="hu" hreflang="hu" data-title="Central processing unit" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-mk mw-list-item"><a href="https://mk.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D0%BD%D0%B0_%D0%BE%D0%B1%D1%80%D0%B0%D0%B1%D0%BE%D1%82%D1%83%D0%B2%D0%B0%D1%87%D0%BA%D0%B0_%D0%B5%D0%B4%D0%B8%D0%BD%D0%B8%D1%86%D0%B0" title="Централна обработувачка единица – Macedonian" lang="mk" hreflang="mk" data-title="Централна обработувачка единица" data-language-autonym="Македонски" data-language-local-name="Macedonian" class="interlanguage-link-target"><span>Македонски</span></a></li><li class="interlanguage-link interwiki-ml mw-list-item"><a href="https://ml.wikipedia.org/wiki/%E0%B4%B8%E0%B5%86%E0%B5%BB%E0%B4%9F%E0%B5%8D%E0%B4%B0%E0%B5%BD_%E0%B4%AA%E0%B5%8D%E0%B4%B0%E0%B5%8A%E0%B4%B8%E0%B4%B8%E0%B4%BF%E0%B4%99%E0%B5%8D_%E0%B4%AF%E0%B5%82%E0%B4%A3%E0%B4%BF%E0%B4%B1%E0%B5%8D%E0%B4%B1%E0%B5%8D" title="സെൻട്രൽ പ്രൊസസിങ് യൂണിറ്റ് – Malayalam" lang="ml" hreflang="ml" data-title="സെൻട്രൽ പ്രൊസസിങ് യൂണിറ്റ്" data-language-autonym="മലയാളം" data-language-local-name="Malayalam" class="interlanguage-link-target"><span>മലയാളം</span></a></li><li class="interlanguage-link interwiki-arz mw-list-item"><a href="https://arz.wikipedia.org/wiki/%D8%A8%D8%B1%D9%88%D8%B3%D9%8A%D8%B3%D9%88%D8%B1" title="بروسيسور – Egyptian Arabic" lang="arz" hreflang="arz" data-title="بروسيسور" data-language-autonym="مصرى" data-language-local-name="Egyptian Arabic" class="interlanguage-link-target"><span>مصرى</span></a></li><li class="interlanguage-link interwiki-ms mw-list-item"><a href="https://ms.wikipedia.org/wiki/Unit_pemprosesan_pusat" title="Unit pemprosesan pusat – Malay" lang="ms" hreflang="ms" data-title="Unit pemprosesan pusat" data-language-autonym="Bahasa Melayu" data-language-local-name="Malay" class="interlanguage-link-target"><span>Bahasa Melayu</span></a></li><li class="interlanguage-link interwiki-mn mw-list-item"><a href="https://mn.wikipedia.org/wiki/%D0%A2%D3%A9%D0%B2_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Төв процессор – Mongolian" lang="mn" hreflang="mn" data-title="Төв процессор" data-language-autonym="Монгол" data-language-local-name="Mongolian" class="interlanguage-link-target"><span>Монгол</span></a></li><li class="interlanguage-link interwiki-my mw-list-item"><a href="https://my.wikipedia.org/wiki/%E1%80%85%E1%80%AE%E1%80%95%E1%80%AE%E1%80%9A%E1%80%B0" title="စီပီယူ – Burmese" lang="my" hreflang="my" data-title="စီပီယူ" data-language-autonym="မြန်မာဘာသာ" data-language-local-name="Burmese" class="interlanguage-link-target"><span>မြန်မာဘာသာ</span></a></li><li class="interlanguage-link interwiki-nl badge-Q70894304 mw-list-item" title=""><a href="https://nl.wikipedia.org/wiki/CPU" title="CPU – Dutch" lang="nl" hreflang="nl" data-title="CPU" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/CPU" title="CPU – Japanese" lang="ja" hreflang="ja" data-title="CPU" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/CPU" title="CPU – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="CPU" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/CPU" title="CPU – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="CPU" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-oc mw-list-item"><a href="https://oc.wikipedia.org/wiki/Processor_central" title="Processor central – Occitan" lang="oc" hreflang="oc" data-title="Processor central" data-language-autonym="Occitan" data-language-local-name="Occitan" class="interlanguage-link-target"><span>Occitan</span></a></li><li class="interlanguage-link interwiki-mhr mw-list-item"><a href="https://mhr.wikipedia.org/wiki/%D0%A0%D3%B1%D0%B4%D3%A7_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Рӱдӧ процессор – Eastern Mari" lang="mhr" hreflang="mhr" data-title="Рӱдӧ процессор" data-language-autonym="Олык марий" data-language-local-name="Eastern Mari" class="interlanguage-link-target"><span>Олык марий</span></a></li><li class="interlanguage-link interwiki-pa mw-list-item"><a href="https://pa.wikipedia.org/wiki/%E0%A8%B8%E0%A9%88%E0%A8%82%E0%A8%9F%E0%A8%B0%E0%A8%B2_%E0%A8%AA%E0%A9%8D%E0%A8%B0%E0%A9%8B%E0%A8%B8%E0%A9%88%E0%A8%B8%E0%A8%BF%E0%A9%B0%E0%A8%97_%E0%A8%AF%E0%A9%82%E0%A8%A8%E0%A8%BF%E0%A8%9F" title="ਸੈਂਟਰਲ ਪ੍ਰੋਸੈਸਿੰਗ ਯੂਨਿਟ – Punjabi" lang="pa" hreflang="pa" data-title="ਸੈਂਟਰਲ ਪ੍ਰੋਸੈਸਿੰਗ ਯੂਨਿਟ" data-language-autonym="ਪੰਜਾਬੀ" data-language-local-name="Punjabi" class="interlanguage-link-target"><span>ਪੰਜਾਬੀ</span></a></li><li class="interlanguage-link interwiki-pnb mw-list-item"><a href="https://pnb.wikipedia.org/wiki/%D9%BE%D8%B1%D9%88%D8%B3%DB%8C%D8%B3%D8%B1" title="پروسیسر – Western Punjabi" lang="pnb" hreflang="pnb" data-title="پروسیسر" data-language-autonym="پنجابی" data-language-local-name="Western Punjabi" class="interlanguage-link-target"><span>پنجابی</span></a></li><li class="interlanguage-link interwiki-km mw-list-item"><a href="https://km.wikipedia.org/wiki/%E1%9E%A2%E1%9E%84%E1%9F%92%E1%9E%82%E1%9E%97%E1%9E%B6%E1%9E%96%E1%9E%8A%E1%9F%86%E1%9E%8E%E1%9E%BE%E1%9E%9A%E1%9E%80%E1%9E%B6%E1%9E%9A%E1%9E%80%E1%9E%8E%E1%9F%92%E1%9E%8F%E1%9E%B6%E1%9E%9B" title="អង្គភាពដំណើរការកណ្តាល – Khmer" lang="km" hreflang="km" data-title="អង្គភាពដំណើរការកណ្តាល" data-language-autonym="ភាសាខ្មែរ" data-language-local-name="Khmer" class="interlanguage-link-target"><span>ភាសាខ្មែរ</span></a></li><li class="interlanguage-link interwiki-pms mw-list-item"><a href="https://pms.wikipedia.org/wiki/CPU" title="CPU – Piedmontese" lang="pms" hreflang="pms" data-title="CPU" data-language-autonym="Piemontèis" data-language-local-name="Piedmontese" class="interlanguage-link-target"><span>Piemontèis</span></a></li><li class="interlanguage-link interwiki-nds mw-list-item"><a href="https://nds.wikipedia.org/wiki/Perzesser" title="Perzesser – Low German" lang="nds" hreflang="nds" data-title="Perzesser" data-language-autonym="Plattdüütsch" data-language-local-name="Low German" class="interlanguage-link-target"><span>Plattdüütsch</span></a></li><li class="interlanguage-link interwiki-pl badge-Q70894304 mw-list-item" title=""><a href="https://pl.wikipedia.org/wiki/CPU" title="CPU – Polish" lang="pl" hreflang="pl" data-title="CPU" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pnt mw-list-item"><a href="https://pnt.wikipedia.org/wiki/%CE%9A%CE%B5%CE%BD%CF%84%CF%81%CE%B9%CE%BA%CF%8C%CE%BD_%CE%BC%CE%BF%CE%BD%CE%AC%CE%B4%CE%B1_%CE%B5%CF%80%CE%B5%CE%BE%CE%B5%CF%81%CE%B3%CE%B1%CF%83%CE%AF%CE%B1%CF%82" title="Κεντρικόν μονάδα επεξεργασίας – Pontic" lang="pnt" hreflang="pnt" data-title="Κεντρικόν μονάδα επεξεργασίας" data-language-autonym="Ποντιακά" data-language-local-name="Pontic" class="interlanguage-link-target"><span>Ποντιακά</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Unidade_central_de_processamento" title="Unidade central de processamento – Portuguese" lang="pt" hreflang="pt" data-title="Unidade central de processamento" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Unitate_central%C4%83_de_prelucrare" title="Unitate centrală de prelucrare – Romanian" lang="ro" hreflang="ro" data-title="Unitate centrală de prelucrare" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-qu mw-list-item"><a href="https://qu.wikipedia.org/wiki/Chawpi_thatkichiy_hukkay" title="Chawpi thatkichiy hukkay – Quechua" lang="qu" hreflang="qu" data-title="Chawpi thatkichiy hukkay" data-language-autonym="Runa Simi" data-language-local-name="Quechua" class="interlanguage-link-target"><span>Runa Simi</span></a></li><li class="interlanguage-link interwiki-rue mw-list-item"><a href="https://rue.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D0%BD%D1%8B%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Централный процесор – Rusyn" lang="rue" hreflang="rue" data-title="Централный процесор" data-language-autonym="Русиньскый" data-language-local-name="Rusyn" class="interlanguage-link-target"><span>Русиньскый</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D1%8C%D0%BD%D1%8B%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Центральный процессор – Russian" lang="ru" hreflang="ru" data-title="Центральный процессор" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sah mw-list-item"><a href="https://sah.wikipedia.org/wiki/%D0%9A%D0%B8%D0%B8%D0%BD_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D1%81%D0%BE%D1%80" title="Киин процессор – Yakut" lang="sah" hreflang="sah" data-title="Киин процессор" data-language-autonym="Саха тыла" data-language-local-name="Yakut" class="interlanguage-link-target"><span>Саха тыла</span></a></li><li class="interlanguage-link interwiki-sq mw-list-item"><a href="https://sq.wikipedia.org/wiki/Nj%C3%ABsia_qendrore_e_p%C3%ABrpunimit" title="Njësia qendrore e përpunimit – Albanian" lang="sq" hreflang="sq" data-title="Njësia qendrore e përpunimit" data-language-autonym="Shqip" data-language-local-name="Albanian" class="interlanguage-link-target"><span>Shqip</span></a></li><li class="interlanguage-link interwiki-si mw-list-item"><a href="https://si.wikipedia.org/wiki/%E0%B6%B8%E0%B6%B0%E0%B7%8A%E2%80%8D%E0%B6%BA%E0%B6%B8_%E0%B7%83%E0%B7%90%E0%B6%9A%E0%B7%83%E0%B7%94%E0%B6%B8%E0%B7%8A_%E0%B6%92%E0%B6%9A%E0%B6%9A%E0%B6%BA" title="මධ්‍යම සැකසුම් ඒකකය – Sinhala" lang="si" hreflang="si" data-title="මධ්‍යම සැකසුම් ඒකකය" data-language-autonym="සිංහල" data-language-local-name="Sinhala" class="interlanguage-link-target"><span>සිංහල</span></a></li><li class="interlanguage-link interwiki-simple mw-list-item"><a href="https://simple.wikipedia.org/wiki/Central_processing_unit" title="Central processing unit – Simple English" lang="en-simple" hreflang="en-simple" data-title="Central processing unit" data-language-autonym="Simple English" data-language-local-name="Simple English" class="interlanguage-link-target"><span>Simple English</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/CPU" title="CPU – Slovak" lang="sk" hreflang="sk" data-title="CPU" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sl mw-list-item"><a href="https://sl.wikipedia.org/wiki/Centralni_procesor" title="Centralni procesor – Slovenian" lang="sl" hreflang="sl" data-title="Centralni procesor" data-language-autonym="Slovenščina" data-language-local-name="Slovenian" class="interlanguage-link-target"><span>Slovenščina</span></a></li><li class="interlanguage-link interwiki-so mw-list-item"><a href="https://so.wikipedia.org/wiki/CPU" title="CPU – Somali" lang="so" hreflang="so" data-title="CPU" data-language-autonym="Soomaaliga" data-language-local-name="Somali" class="interlanguage-link-target"><span>Soomaaliga</span></a></li><li class="interlanguage-link interwiki-ckb mw-list-item"><a href="https://ckb.wikipedia.org/wiki/%DB%8C%DB%95%DA%A9%DB%95%DB%8C_%D9%86%D8%A7%D9%88%DB%95%D9%86%D8%AF%DB%8C%DB%8C_%D9%BE%DB%8E%D9%88%DB%95%D8%A6%D8%A7%DA%98%DB%86%DB%8C%DB%8C" title="یەکەی ناوەندیی پێوەئاژۆیی – Central Kurdish" lang="ckb" hreflang="ckb" data-title="یەکەی ناوەندیی پێوەئاژۆیی" data-language-autonym="کوردی" data-language-local-name="Central Kurdish" class="interlanguage-link-target"><span>کوردی</span></a></li><li class="interlanguage-link interwiki-sr mw-list-item"><a href="https://sr.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D0%BD%D0%B0_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80%D1%81%D0%BA%D0%B0_%D1%98%D0%B5%D0%B4%D0%B8%D0%BD%D0%B8%D1%86%D0%B0" title="Централна процесорска јединица – Serbian" lang="sr" hreflang="sr" data-title="Централна процесорска јединица" data-language-autonym="Српски / srpski" data-language-local-name="Serbian" class="interlanguage-link-target"><span>Српски / srpski</span></a></li><li class="interlanguage-link interwiki-sh mw-list-item"><a href="https://sh.wikipedia.org/wiki/Centralna_procesorska_jedinica" title="Centralna procesorska jedinica – Serbo-Croatian" lang="sh" hreflang="sh" data-title="Centralna procesorska jedinica" data-language-autonym="Srpskohrvatski / српскохрватски" data-language-local-name="Serbo-Croatian" class="interlanguage-link-target"><span>Srpskohrvatski / српскохрватски</span></a></li><li class="interlanguage-link interwiki-su mw-list-item"><a href="https://su.wikipedia.org/wiki/CPU" title="CPU – Sundanese" lang="su" hreflang="su" data-title="CPU" data-language-autonym="Sunda" data-language-local-name="Sundanese" class="interlanguage-link-target"><span>Sunda</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Suoritin" title="Suoritin – Finnish" lang="fi" hreflang="fi" data-title="Suoritin" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Processor" title="Processor – Swedish" lang="sv" hreflang="sv" data-title="Processor" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tl mw-list-item"><a href="https://tl.wikipedia.org/wiki/CPU" title="CPU – Tagalog" lang="tl" hreflang="tl" data-title="CPU" data-language-autonym="Tagalog" data-language-local-name="Tagalog" class="interlanguage-link-target"><span>Tagalog</span></a></li><li class="interlanguage-link interwiki-ta mw-list-item"><a href="https://ta.wikipedia.org/wiki/%E0%AE%AE%E0%AF%88%E0%AE%AF%E0%AE%9A%E0%AF%8D_%E0%AE%9A%E0%AF%86%E0%AE%AF%E0%AE%B1%E0%AF%8D%E0%AE%AA%E0%AE%95%E0%AF%81%E0%AE%A4%E0%AE%BF" title="மையச் செயற்பகுதி – Tamil" lang="ta" hreflang="ta" data-title="மையச் செயற்பகுதி" data-language-autonym="தமிழ்" data-language-local-name="Tamil" class="interlanguage-link-target"><span>தமிழ்</span></a></li><li class="interlanguage-link interwiki-tt badge-Q17437796 badge-featuredarticle mw-list-item" title="featured article badge"><a href="https://tt.wikipedia.org/wiki/%D2%AE%D0%B7%D3%99%D0%BA_%D1%8D%D1%88%D0%BA%D3%99%D1%80%D1%82%D0%BA%D0%B5%D1%87_%D2%97%D0%B0%D0%B9%D0%BB%D0%B0%D0%BD%D0%BC%D0%B0" title="Үзәк эшкәрткеч җайланма – Tatar" lang="tt" hreflang="tt" data-title="Үзәк эшкәрткеч җайланма" data-language-autonym="Татарча / tatarça" data-language-local-name="Tatar" class="interlanguage-link-target"><span>Татарча / tatarça</span></a></li><li class="interlanguage-link interwiki-th mw-list-item"><a href="https://th.wikipedia.org/wiki/%E0%B8%AB%E0%B8%99%E0%B9%88%E0%B8%A7%E0%B8%A2%E0%B8%9B%E0%B8%A3%E0%B8%B0%E0%B8%A1%E0%B8%A7%E0%B8%A5%E0%B8%9C%E0%B8%A5%E0%B8%81%E0%B8%A5%E0%B8%B2%E0%B8%87" title="หน่วยประมวลผลกลาง – Thai" lang="th" hreflang="th" data-title="หน่วยประมวลผลกลาง" data-language-autonym="ไทย" data-language-local-name="Thai" class="interlanguage-link-target"><span>ไทย</span></a></li><li class="interlanguage-link interwiki-tg mw-list-item"><a href="https://tg.wikipedia.org/wiki/%D0%92%D0%BE%D2%B3%D0%B8%D0%B4%D0%B8_%D0%BF%D0%B0%D1%80%D0%B4%D0%BE%D0%B7%D0%B8%D1%88%D0%B8_%D0%BC%D0%B0%D1%80%D0%BA%D0%B0%D0%B7%D3%A3" title="Воҳиди пардозиши марказӣ – Tajik" lang="tg" hreflang="tg" data-title="Воҳиди пардозиши марказӣ" data-language-autonym="Тоҷикӣ" data-language-local-name="Tajik" class="interlanguage-link-target"><span>Тоҷикӣ</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/Merkez%C3%AE_i%C5%9Flem_birimi" title="Merkezî işlem birimi – Turkish" lang="tr" hreflang="tr" data-title="Merkezî işlem birimi" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/%D0%A6%D0%B5%D0%BD%D1%82%D1%80%D0%B0%D0%BB%D1%8C%D0%BD%D0%B8%D0%B9_%D0%BF%D1%80%D0%BE%D1%86%D0%B5%D1%81%D0%BE%D1%80" title="Центральний процесор – Ukrainian" lang="uk" hreflang="uk" data-title="Центральний процесор" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-ur mw-list-item"><a href="https://ur.wikipedia.org/wiki/%D8%B3%DB%8C_%D9%BE%DB%8C_%DB%8C%D9%88" title="سی پی یو – Urdu" lang="ur" hreflang="ur" data-title="سی پی یو" data-language-autonym="اردو" data-language-local-name="Urdu" class="interlanguage-link-target"><span>اردو</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/CPU" title="CPU – Vietnamese" lang="vi" hreflang="vi" data-title="CPU" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-war mw-list-item"><a href="https://war.wikipedia.org/wiki/Central_processing_unit" title="Central processing unit – Waray" lang="war" hreflang="war" data-title="Central processing unit" data-language-autonym="Winaray" data-language-local-name="Waray" class="interlanguage-link-target"><span>Winaray</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/%E4%B8%AD%E5%A4%AE%E5%A4%84%E7%90%86%E5%99%A8" title="中央处理器 – Wu" lang="wuu" hreflang="wuu" data-title="中央处理器" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-yi mw-list-item"><a href="https://yi.wikipedia.org/wiki/%D7%A4%D7%A8%D7%90%D7%A6%D7%A2%D7%A1%D7%90%D7%A8" title="פראצעסאר – Yiddish" lang="yi" hreflang="yi" data-title="פראצעסאר" data-language-autonym="ייִדיש" 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class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Central computer component which executes instructions</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"CPU" redirects here. For other uses, see <a href="/wiki/CPU_(disambiguation)" class="mw-disambig" title="CPU (disambiguation)">CPU (disambiguation)</a>.</div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Intel_Xeon_3060_Conroe_(Reshoot)_-_Flickr_-_cole8888.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0b/Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg/280px-Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg" decoding="async" width="280" height="214" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0b/Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg/420px-Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0b/Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg/560px-Intel_Xeon_3060_Conroe_%28Reshoot%29_-_Flickr_-_cole8888.jpg 2x" data-file-width="32723" data-file-height="24971" /></a><figcaption>Inside a central processing unit: The <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> of <a href="/wiki/Intel" title="Intel">Intel</a>'s <a href="/wiki/List_of_Intel_Xeon_processors_(Core-based)#ark27205" title="List of Intel Xeon processors (Core-based)">Xeon 3060</a>, first manufactured in 2006</figcaption></figure> <p>A <b>central processing unit</b> (<b>CPU</b>), also called a <b>central processor</b>, <b>main processor</b>, or just <b>processor</b>, is the most important <a href="/wiki/Processor_(computing)" title="Processor (computing)">processor</a> in a given <a href="/wiki/Computer" title="Computer">computer</a>.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Its <a href="/wiki/Electronic_circuit" title="Electronic circuit">electronic circuitry</a> executes <a href="/wiki/Instruction_(computing)" class="mw-redirect" title="Instruction (computing)">instructions</a> of a <a href="/wiki/Computer_program" title="Computer program">computer program</a>, such as <a href="/wiki/Arithmetic" title="Arithmetic">arithmetic</a>, logic, controlling, and <a href="/wiki/Input/output" title="Input/output">input/output</a> (I/O) operations.<sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> This role contrasts with that of external components, such as <a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a> and I/O circuitry,<sup id="cite_ref-kuck_6-0" class="reference"><a href="#cite_note-kuck-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> and specialized <a href="/wiki/Coprocessor" title="Coprocessor">coprocessors</a> such as <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing units</a> (GPUs). </p><p>The form, <a href="/wiki/CPU_design" class="mw-redirect" title="CPU design">design</a>, and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Principal components of a CPU include the <a href="/wiki/Arithmetic%E2%80%93logic_unit" class="mw-redirect" title="Arithmetic–logic unit">arithmetic–logic unit</a> (ALU) that performs <a href="/wiki/Arithmetic_operation" class="mw-redirect" title="Arithmetic operation">arithmetic</a> and <a href="/wiki/Bitwise_operation" title="Bitwise operation">logic operations</a>, <a href="/wiki/Processor_register" title="Processor register">processor registers</a> that supply <a href="/wiki/Operand" title="Operand">operands</a> to the ALU and store the results of ALU operations, and a <a href="/wiki/Control_unit" title="Control unit">control unit</a> that orchestrates the <a href="#Fetch">fetching (from memory)</a>, <a href="#Decode">decoding</a> and <a href="#Execute">execution (of instructions)</a> by directing the coordinated operations of the ALU, registers, and other components. Modern CPUs devote a lot of semiconductor area to <a href="/wiki/Cache_(computing)" title="Cache (computing)">caches</a> and <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a> to increase performance and to <a href="/wiki/CPU_modes" title="CPU modes">CPU modes</a> to support <a href="/wiki/Operating_system" title="Operating system">operating systems</a> and <a href="/wiki/Virtualization" title="Virtualization">virtualization</a>. </p><p>Most modern CPUs are implemented on <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) <a href="/wiki/Microprocessor" title="Microprocessor">microprocessors</a>, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are called <i><a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processors</a></i>.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> The individual physical CPUs, called <i><b>processor cores</b></i>, can also be <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multithreaded</a> to support CPU-level multithreading.<sup id="cite_ref-intel-pcm_9-0" class="reference"><a href="#cite_note-intel-pcm-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>An IC that contains a CPU may also contain <a href="/wiki/Computer_memory" title="Computer memory">memory</a>, <a href="/wiki/Peripheral" title="Peripheral">peripheral</a> interfaces, and other components of a computer;<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> such integrated devices are variously called <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> or <a href="/wiki/System_on_a_chip" title="System on a chip">systems on a chip</a> (SoC). </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Edvac.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/Edvac.jpg/220px-Edvac.jpg" decoding="async" width="220" height="285" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/Edvac.jpg/330px-Edvac.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/17/Edvac.jpg/440px-Edvac.jpg 2x" data-file-width="2925" data-file-height="3795" /></a><figcaption><a href="/wiki/EDVAC" title="EDVAC">EDVAC</a>, one of the first stored-program computers</figcaption></figure> <p>Early computers such as the <a href="/wiki/ENIAC" title="ENIAC">ENIAC</a> had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers".<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> The "central processing unit" term has been in use since as early as 1955.<sup id="cite_ref-weik1955_12-0" class="reference"><a href="#cite_note-weik1955-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-weik1961_13-0" class="reference"><a href="#cite_note-weik1961-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> Since the term "CPU" is generally defined as a device for <a href="/wiki/Software" title="Software">software</a> (computer program) execution, the earliest devices that could rightly be called CPUs came with the advent of the <a href="/wiki/Stored-program_computer" title="Stored-program computer">stored-program computer</a>. </p><p>The idea of a stored-program computer had been already present in the design of <a href="/wiki/J._Presper_Eckert" title="J. Presper Eckert">John Presper Eckert</a> and <a href="/wiki/John_William_Mauchly" class="mw-redirect" title="John William Mauchly">John William Mauchly</a>'s <a href="/wiki/ENIAC" title="ENIAC">ENIAC</a>, but was initially omitted so that it could be finished sooner.<sup id="cite_ref-14" class="reference"><a href="#cite_note-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> On June 30, 1945, before ENIAC was made, mathematician <a href="/wiki/John_von_Neumann" title="John von Neumann">John von Neumann</a> distributed a paper entitled <i><a href="/wiki/First_Draft_of_a_Report_on_the_EDVAC" title="First Draft of a Report on the EDVAC">First Draft of a Report on the EDVAC</a></i>. It was the outline of a stored-program computer that would eventually be completed in August 1949.<sup id="cite_ref-15" class="reference"><a href="#cite_note-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> <a href="/wiki/EDVAC" title="EDVAC">EDVAC</a> was designed to perform a certain number of instructions (or operations) of various types. Significantly, the programs written for EDVAC were to be stored in high-speed <a href="/wiki/Memory_(computers)" class="mw-redirect" title="Memory (computers)">computer memory</a> rather than specified by the physical wiring of the computer.<sup id="cite_ref-16" class="reference"><a href="#cite_note-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> This overcame a severe limitation of ENIAC, which was the considerable time and effort required to reconfigure the computer to perform a new task.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> With von Neumann's design, the program that EDVAC ran could be changed simply by changing the contents of the memory. EDVAC was not the first stored-program computer; the <a href="/wiki/Manchester_Baby" title="Manchester Baby">Manchester Baby</a>, which was a small-scale experimental stored-program computer, ran its first program on 21 June 1948<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> and the <a href="/wiki/Manchester_Mark_1" title="Manchester Mark 1">Manchester Mark 1</a> ran its first program during the night of 16–17 June 1949.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>Early CPUs were custom designs used as part of a larger and sometimes distinctive computer.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup> However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete <a href="/wiki/Transistor" title="Transistor">transistor</a> <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframes</a> and <a href="/wiki/Minicomputer" title="Minicomputer">minicomputers</a>, and has rapidly accelerated with the popularization of the <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of <a href="/wiki/Nanometre" title="Nanometre">nanometers</a>.<sup id="cite_ref-nobel_21-0" class="reference"><a href="#cite_note-nobel-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles<sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> to cellphones,<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup> and sometimes even in toys.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> </p><p>While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the <a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">von Neumann architecture</a>, others before him, such as <a href="/wiki/Konrad_Zuse" title="Konrad Zuse">Konrad Zuse</a>, had suggested and implemented similar ideas.<sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> The so-called <a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a> of the <a href="/wiki/Harvard_Mark_I" title="Harvard Mark I">Harvard Mark I</a>, which was completed before EDVAC,<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-28" class="reference"><a href="#cite_note-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup> also used a stored-program design using <a href="/wiki/Punched_tape" title="Punched tape">punched paper tape</a> rather than electronic memory.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup> The key difference between the von Neumann and Harvard architectures is that the latter separates the storage and treatment of CPU instructions and data, while the former uses the same memory space for both.<sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the <a href="/wiki/Atmel_AVR" class="mw-redirect" title="Atmel AVR">Atmel AVR</a> microcontrollers are Harvard-architecture processors.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup> </p><p><a href="/wiki/Relay" title="Relay">Relays</a> and <a href="/wiki/Vacuum_tube" title="Vacuum tube">vacuum tubes</a> (thermionic tubes) were commonly used as switching elements;<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup> a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. <a href="/wiki/Vacuum-tube_computer" title="Vacuum-tube computer">Vacuum-tube computers</a> such as EDVAC tended to average eight hours between failures, whereas relay computers—such as the slower but earlier <a href="/wiki/Harvard_Mark_I" title="Harvard Mark I">Harvard Mark I</a>—failed very rarely.<sup id="cite_ref-weik1961_13-1" class="reference"><a href="#cite_note-weik1961-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low <a href="/wiki/Clock_rate" title="Clock rate">clock rates</a> compared to modern microelectronic designs. Clock signal frequencies ranging from 100 <a href="/wiki/Hertz" title="Hertz">kHz</a> to 4 MHz were very common at this time, limited largely by the speed of the switching devices they were built with.<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Transistor_CPUs">Transistor CPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=2" title="Edit section: Transistor CPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:IBM_PPC604e_200.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a7/IBM_PPC604e_200.jpg/220px-IBM_PPC604e_200.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a7/IBM_PPC604e_200.jpg/330px-IBM_PPC604e_200.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a7/IBM_PPC604e_200.jpg/440px-IBM_PPC604e_200.jpg 2x" data-file-width="852" data-file-height="852" /></a><figcaption>IBM PowerPC 604e processor</figcaption></figure> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Transistor_computer" title="Transistor computer">Transistor computer</a></div> <p>The design complexity of CPUs increased as various technologies facilitated the building of smaller and more reliable electronic devices. The first such improvement came with the advent of the <a href="/wiki/Transistor" title="Transistor">transistor</a>. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements, like <a href="/wiki/Vacuum_tube" title="Vacuum tube">vacuum tubes</a> and <a href="/wiki/Relay" title="Relay">relays</a>.<sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> With this improvement, more complex and reliable CPUs were built onto one or several <a href="/wiki/Printed_circuit_board" title="Printed circuit board">printed circuit boards</a> containing discrete (individual) components. </p><p>In 1964, <a href="/wiki/IBM" title="IBM">IBM</a> introduced its <a href="/wiki/IBM_System/360" title="IBM System/360">IBM System/360</a> computer architecture that was used in a series of computers capable of running the same programs with different speeds and performances.<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup> This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a <a href="/wiki/Microprogram" class="mw-redirect" title="Microprogram">microprogram</a> (often called "microcode"), which still sees widespread use in modern CPUs.<sup id="cite_ref-amdahl1964_37-0" class="reference"><a href="#cite_note-amdahl1964-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> The System/360 architecture was so popular that it dominated the <a href="/wiki/Mainframe_computer" title="Mainframe computer">mainframe computer</a> market for decades and left a legacy that is continued by similar modern computers like the IBM <a href="/wiki/IBM_System_z" class="mw-redirect" title="IBM System z">zSeries</a>.<sup id="cite_ref-38" class="reference"><a href="#cite_note-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-39" class="reference"><a href="#cite_note-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> In 1965, <a href="/wiki/Digital_Equipment_Corporation" title="Digital Equipment Corporation">Digital Equipment Corporation</a> (DEC) introduced another influential computer aimed at the scientific and research markets—the <a href="/wiki/PDP-8" title="PDP-8">PDP-8</a>.<sup id="cite_ref-40" class="reference"><a href="#cite_note-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/220px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/330px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c8/Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG/440px-Board_with_SPARC64_VIIIfx_processors_on_display_in_Fujitsu_HQ.JPG 2x" data-file-width="3448" data-file-height="4592" /></a><figcaption>Fujitsu board with SPARC64 VIIIfx processors</figcaption></figure> <p>Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay.<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup> The increased reliability and dramatically increased speed of the switching elements, which were almost exclusively transistors by this time; CPU clock rates in the tens of megahertz were easily obtained during this period.<sup id="cite_ref-pcgamer_42-0" class="reference"><a href="#cite_note-pcgamer-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup> Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">single instruction, multiple data</a> (SIMD) <a href="/wiki/Vector_processor" title="Vector processor">vector processors</a> began to appear.<sup id="cite_ref-patterson_43-0" class="reference"><a href="#cite_note-patterson-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> These early experimental designs later gave rise to the era of specialized <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> like those made by <a href="/wiki/Cray" title="Cray">Cray Inc</a> and <a href="/wiki/Fujitsu" title="Fujitsu">Fujitsu Ltd</a>.<sup id="cite_ref-patterson_43-1" class="reference"><a href="#cite_note-patterson-43"><span class="cite-bracket">[</span>43<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Small-scale_integration_CPUs">Small-scale integration CPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=3" title="Edit section: Small-scale integration CPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:PDP-8i_cpu.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/03/PDP-8i_cpu.jpg/220px-PDP-8i_cpu.jpg" decoding="async" width="220" height="165" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/03/PDP-8i_cpu.jpg/330px-PDP-8i_cpu.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/03/PDP-8i_cpu.jpg/440px-PDP-8i_cpu.jpg 2x" data-file-width="1600" data-file-height="1200" /></a><figcaption>CPU, <a href="/wiki/Magnetic-core_memory" title="Magnetic-core memory">core memory</a> and <a href="/wiki/External_bus" class="mw-redirect" title="External bus">external bus</a> interface of a DEC <a href="/wiki/PDP-8" title="PDP-8">PDP-8</a>/I, made of medium-scale integrated circuits</figcaption></figure> <p>During this period, a method of manufacturing many interconnected transistors in a compact space was developed. The <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuit</a> (IC) allowed a large number of transistors to be manufactured on a single <a href="/wiki/Semiconductor" title="Semiconductor">semiconductor</a>-based <a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">die</a>, or "chip". At first, only very basic non-specialized digital circuits such as <a href="/wiki/NOR_gate" title="NOR gate">NOR gates</a> were miniaturized into ICs.<sup id="cite_ref-44" class="reference"><a href="#cite_note-44"><span class="cite-bracket">[</span>44<span class="cite-bracket">]</span></a></sup> CPUs based on these "building block" ICs are generally referred to as "small-scale integration" (SSI) devices. SSI ICs, such as the ones used in the <a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">Apollo Guidance Computer</a>, usually contained up to a few dozen transistors. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete transistor designs.<sup id="cite_ref-45" class="reference"><a href="#cite_note-45"><span class="cite-bracket">[</span>45<span class="cite-bracket">]</span></a></sup> </p><p>IBM's <a href="/wiki/System/370" class="mw-redirect" title="System/370">System/370</a>, follow-on to the System/360, used SSI ICs rather than <a href="/wiki/Solid_Logic_Technology" title="Solid Logic Technology">Solid Logic Technology</a> discrete-transistor modules.<sup id="cite_ref-46" class="reference"><a href="#cite_note-46"><span class="cite-bracket">[</span>46<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-47" class="reference"><a href="#cite_note-47"><span class="cite-bracket">[</span>47<span class="cite-bracket">]</span></a></sup> DEC's <a href="/wiki/PDP-8" title="PDP-8">PDP-8</a>/I and KI10 <a href="/wiki/PDP-10" title="PDP-10">PDP-10</a> also switched from the individual transistors used by the PDP-8 and PDP-10 to SSI ICs,<sup id="cite_ref-48" class="reference"><a href="#cite_note-48"><span class="cite-bracket">[</span>48<span class="cite-bracket">]</span></a></sup> and their extremely popular <a href="/wiki/PDP-11" title="PDP-11">PDP-11</a> line was originally built with SSI ICs, but was eventually implemented with LSI components once these became practical. </p> <div class="mw-heading mw-heading3"><h3 id="Large-scale_integration_CPUs">Large-scale integration CPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=4" title="Edit section: Large-scale integration CPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Lee Boysel published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of <a href="/wiki/Large-scale_integration" class="mw-redirect" title="Large-scale integration">large-scale integration</a> circuits (LSI).<sup id="cite_ref-49" class="reference"><a href="#cite_note-49"><span class="cite-bracket">[</span>49<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-shirriff_50-0" class="reference"><a href="#cite_note-shirriff-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a <a href="/wiki/MOSFET" title="MOSFET">metal–oxide–semiconductor</a> (MOS) <a href="/wiki/Semiconductor_manufacturing_process" class="mw-redirect" title="Semiconductor manufacturing process">semiconductor manufacturing process</a> (either <a href="/wiki/PMOS_logic" title="PMOS logic">PMOS logic</a>, <a href="/wiki/NMOS_logic" title="NMOS logic">NMOS logic</a>, or <a href="/wiki/CMOS" title="CMOS">CMOS</a> logic). However, some companies continued to build processors out of bipolar <a href="/wiki/Transistor%E2%80%93transistor_logic" title="Transistor–transistor logic">transistor–transistor logic</a> (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as <a href="/wiki/Datapoint" title="Datapoint">Datapoint</a> continued to build processors out of TTL chips until the early 1980s).<sup id="cite_ref-shirriff_50-1" class="reference"><a href="#cite_note-shirriff-50"><span class="cite-bracket">[</span>50<span class="cite-bracket">]</span></a></sup> In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power.<sup id="cite_ref-51" class="reference"><a href="#cite_note-51"><span class="cite-bracket">[</span>51<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-52" class="reference"><a href="#cite_note-52"><span class="cite-bracket">[</span>52<span class="cite-bracket">]</span></a></sup> Following the development of <a href="/wiki/Silicon-gate" class="mw-redirect" title="Silicon-gate">silicon-gate</a> MOS technology by <a href="/wiki/Federico_Faggin" title="Federico Faggin">Federico Faggin</a> at Fairchild Semiconductor in 1968, MOS ICs largely replaced bipolar TTL as the standard chip technology in the early 1970s.<sup id="cite_ref-53" class="reference"><a href="#cite_note-53"><span class="cite-bracket">[</span>53<span class="cite-bracket">]</span></a></sup> </p><p>As the <a href="/wiki/Microelectronic" class="mw-redirect" title="Microelectronic">microelectronic</a> technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs.<sup id="cite_ref-54" class="reference"><a href="#cite_note-54"><span class="cite-bracket">[</span>54<span class="cite-bracket">]</span></a></sup> In stark contrast with its SSI and MSI predecessors, the first LSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits.<sup id="cite_ref-55" class="reference"><a href="#cite_note-55"><span class="cite-bracket">[</span>55<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Microprocessors">Microprocessors</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=5" title="Edit section: Microprocessors"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></div> <style data-mw-deduplicate="TemplateStyles:r1237032888/mw-parser-output/.tmulti">.mw-parser-output .tmulti .multiimageinner{display:flex;flex-direction:column}.mw-parser-output .tmulti .trow{display:flex;flex-direction:row;clear:left;flex-wrap:wrap;width:100%;box-sizing:border-box}.mw-parser-output .tmulti .tsingle{margin:1px;float:left}.mw-parser-output .tmulti .theader{clear:both;font-weight:bold;text-align:center;align-self:center;background-color:transparent;width:100%}.mw-parser-output .tmulti .thumbcaption{background-color:transparent}.mw-parser-output .tmulti .text-align-left{text-align:left}.mw-parser-output .tmulti .text-align-right{text-align:right}.mw-parser-output .tmulti .text-align-center{text-align:center}@media all and (max-width:720px){.mw-parser-output .tmulti .thumbinner{width:100%!important;box-sizing:border-box;max-width:none!important;align-items:center}.mw-parser-output .tmulti .trow{justify-content:center}.mw-parser-output .tmulti .tsingle{float:none!important;max-width:100%!important;box-sizing:border-box;text-align:center}.mw-parser-output .tmulti .tsingle .thumbcaption{text-align:left}.mw-parser-output .tmulti .trow>.thumbcaption{text-align:center}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .tmulti .multiimageinner img{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .tmulti .multiimageinner img{background-color:white}}</style><div class="thumb tmulti tright"><div class="thumbinner multiimageinner" style="width:224px;max-width:224px"><div class="trow"><div class="tsingle" style="width:222px;max-width:222px"><div class="thumbimage"><span typeof="mw:File"><a href="/wiki/File:80486dx2-large.jpg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/220px-80486dx2-large.jpg" decoding="async" width="220" height="164" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/330px-80486dx2-large.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/440px-80486dx2-large.jpg 2x" data-file-width="1341" data-file-height="1002" /></a></span></div><div class="thumbcaption"><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> of an <a href="/wiki/Intel_80486DX2" class="mw-redirect" title="Intel 80486DX2">Intel 80486DX2</a> microprocessor (actual size: 12 × 6.75 mm) in its packaging</div></div></div><div class="trow"><div class="tsingle" style="width:222px;max-width:222px"><div class="thumbimage"><span typeof="mw:File"><a href="/wiki/File:EBIntel_Corei5.JPG" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/commons/thumb/5/52/EBIntel_Corei5.JPG/220px-EBIntel_Corei5.JPG" decoding="async" width="220" height="176" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/52/EBIntel_Corei5.JPG/330px-EBIntel_Corei5.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/52/EBIntel_Corei5.JPG/440px-EBIntel_Corei5.JPG 2x" data-file-width="3716" data-file-height="2974" /></a></span></div><div class="thumbcaption"><a href="/wiki/Intel" title="Intel">Intel</a> Core i5 CPU on a <a href="/wiki/Sony_Vaio_E_series" title="Sony Vaio E series">Vaio E series</a> laptop motherboard (on the right, beneath the <a href="/wiki/Heat_pipe" title="Heat pipe">heat pipe</a>)</div></div></div></div></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Laptop-intel-core2duo-t5500.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/220px-Laptop-intel-core2duo-t5500.jpg" decoding="async" width="220" height="293" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/330px-Laptop-intel-core2duo-t5500.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/Laptop-intel-core2duo-t5500.jpg/440px-Laptop-intel-core2duo-t5500.jpg 2x" data-file-width="1536" data-file-height="2048" /></a><figcaption>Inside of a laptop, with the CPU removed from socket</figcaption></figure> <p>Since microprocessors were first introduced they have almost completely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the <a href="/wiki/Intel_4004" title="Intel 4004">Intel 4004</a>, and the first widely used microprocessor, made in 1974, was the <a href="/wiki/Intel_8080" title="Intel 8080">Intel 8080</a>. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older <a href="/wiki/Computer_architecture" title="Computer architecture">computer architectures</a>, and eventually produced <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set</a> compatible microprocessors that were backward-compatible with their older hardware and software. Combined with the advent and eventual success of the ubiquitous <a href="/wiki/Personal_computer" title="Personal computer">personal computer</a>, the term <i>CPU</i> is now applied almost exclusively<sup id="cite_ref-56" class="reference"><a href="#cite_note-56"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup> to microprocessors. Several CPUs (denoted <i>cores</i>) can be combined in a single processing chip.<sup id="cite_ref-57" class="reference"><a href="#cite_note-57"><span class="cite-bracket">[</span>56<span class="cite-bracket">]</span></a></sup> </p><p><span class="anchor" id="DISCRETE-PROCESSOR"></span> Previous generations of CPUs were implemented as <a href="/wiki/Discrete_components" class="mw-redirect" title="Discrete components">discrete components</a> and numerous small <a href="/wiki/Integrated_circuit" title="Integrated circuit">integrated circuits</a> (ICs) on one or more circuit boards.<sup id="cite_ref-58" class="reference"><a href="#cite_note-58"><span class="cite-bracket">[</span>57<span class="cite-bracket">]</span></a></sup> Microprocessors, on the other hand, are CPUs manufactured on a very small number of ICs; usually just one.<sup id="cite_ref-Osborne80_59-0" class="reference"><a href="#cite_note-Osborne80-59"><span class="cite-bracket">[</span>58<span class="cite-bracket">]</span></a></sup> The overall smaller CPU size, as a result of being implemented on a single die, means faster switching time because of physical factors like decreased gate <a href="/wiki/Parasitic_capacitance" title="Parasitic capacitance">parasitic capacitance</a>.<sup id="cite_ref-60" class="reference"><a href="#cite_note-60"><span class="cite-bracket">[</span>59<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-61" class="reference"><a href="#cite_note-61"><span class="cite-bracket">[</span>60<span class="cite-bracket">]</span></a></sup> This has allowed synchronous microprocessors to have clock rates ranging from tens of megahertz to several gigahertz. Additionally, the ability to construct exceedingly small transistors on an IC has increased the complexity and number of transistors in a single CPU many fold. This widely observed trend is described by <a href="/wiki/Moore%27s_law" title="Moore's law">Moore's law</a>, which had proven to be a fairly accurate predictor of the growth of CPU (and other IC) complexity until 2016.<sup id="cite_ref-62" class="reference"><a href="#cite_note-62"><span class="cite-bracket">[</span>61<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-MooresLaw_63-0" class="reference"><a href="#cite_note-MooresLaw-63"><span class="cite-bracket">[</span>62<span class="cite-bracket">]</span></a></sup> </p><p>While the complexity, size, construction and general form of CPUs have changed enormously since 1950,<sup id="cite_ref-64" class="reference"><a href="#cite_note-64"><span class="cite-bracket">[</span>63<span class="cite-bracket">]</span></a></sup> the basic design and function has not changed much at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines.<sup id="cite_ref-65" class="reference"><a href="#cite_note-65"><span class="cite-bracket">[</span>64<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-67" class="reference"><a href="#cite_note-67"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> As Moore's law no longer holds, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of <a href="/wiki/Logic_gate" title="Logic gate">electronic gates</a> is causing the effects of phenomena like <a href="/wiki/Electromigration" title="Electromigration">electromigration</a> and <a href="/wiki/Subthreshold_leakage" class="mw-redirect" title="Subthreshold leakage">subthreshold leakage</a> to become much more significant.<sup id="cite_ref-68" class="reference"><a href="#cite_note-68"><span class="cite-bracket">[</span>66<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-69" class="reference"><a href="#cite_note-69"><span class="cite-bracket">[</span>67<span class="cite-bracket">]</span></a></sup> These newer concerns are among the many factors causing researchers to investigate new methods of computing such as the <a href="/wiki/Quantum_computer" class="mw-redirect" title="Quantum computer">quantum computer</a>, as well as to expand the use of <a href="/wiki/Parallel_computing" title="Parallel computing">parallelism</a> and other methods that extend the usefulness of the classical von Neumann model. </p> <div class="mw-heading mw-heading2"><h2 id="Operation">Operation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=6" title="Edit section: Operation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored <a href="/wiki/Instruction_(computing)" class="mw-redirect" title="Instruction (computing)">instructions</a> that is called a program. The instructions to be executed are kept in some kind of <a href="/wiki/Memory_(computers)" class="mw-redirect" title="Memory (computers)">computer memory</a>. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the <a href="/wiki/Instruction_cycle" title="Instruction cycle">instruction cycle</a>. </p><p>After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the <a href="/wiki/Program_counter" title="Program counter">program counter</a>. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "<a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">classic RISC pipeline</a>", which is quite common among the simple CPUs used in many electronic devices (often called microcontrollers). It largely ignores the important role of CPU cache, and therefore the access stage of the pipeline. </p><p>Some instructions manipulate the program counter rather than producing result data directly; such instructions are generally called "jumps" and facilitate program behavior like <a href="/wiki/Control_flow#Loops" title="Control flow">loops</a>, conditional program execution (through the use of a conditional jump), and existence of <a href="/wiki/Subroutine" class="mw-redirect" title="Subroutine">functions</a>.<sup id="cite_ref-70" class="reference"><a href="#cite_note-70"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> In some processors, some other instructions change the state of bits in a <a href="/wiki/Status_register" title="Status register">"flags" register</a>. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, in such processors a "compare" instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal; one of these flags could then be used by a later jump instruction to determine program flow. </p> <div class="mw-heading mw-heading3"><h3 id="Fetch">Fetch</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=7" title="Edit section: Fetch"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Fetch involves retrieving an <a href="/wiki/Instruction_(computing)" class="mw-redirect" title="Instruction (computing)">instruction</a> (which is represented by a number or sequence of numbers) from program memory. The instruction's location (address) in program memory is determined by the <a href="/wiki/Program_counter" title="Program counter">program counter</a> (PC; called the "instruction pointer" in <a href="/wiki/X86" title="X86">Intel x86 microprocessors</a>), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence.<sup id="cite_ref-71" class="reference"><a href="#cite_note-71"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below). </p> <div class="mw-heading mw-heading3"><h3 id="Decode">Decode</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=8" title="Edit section: Decode"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/Instruction_set_architecture#Instruction_encoding" title="Instruction set architecture">Instruction set architecture § Instruction encoding</a></div> <p>The instruction that the CPU fetches from memory determines what the CPU will do. In the decode step, performed by <a href="/wiki/Binary_decoder" title="Binary decoder">binary decoder</a> circuitry known as the <i>instruction decoder</i>, the instruction is converted into signals that control other parts of the CPU. </p><p>The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA).<sup id="cite_ref-72" class="reference"><a href="#cite_note-72"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup> Often, one group of bits (that is, a "field") within the instruction, called the opcode, indicates which operation is to be performed, while the remaining fields usually provide supplemental information required for the operation, such as the operands. Those operands may be specified as a constant value (called an immediate value), or as the location of a value that may be a <a href="/wiki/Processor_register" title="Processor register">processor register</a> or a memory address, as determined by some <a href="/wiki/Addressing_mode" title="Addressing mode">addressing mode</a>. </p><p>In some CPU designs, the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a <a href="/wiki/Microprogram" class="mw-redirect" title="Microprogram">microprogram</a> is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions. </p> <div class="mw-heading mw-heading3"><h3 id="Execute">Execute</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=9" title="Edit section: Execute"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>After the fetch and decode steps, the execute step is performed. Depending on the CPU architecture, this may consist of a single action or a sequence of actions. During each action, control signals electrically enable or disable various parts of the CPU so they can perform all or part of the desired operation. The action is then completed, typically in response to a clock pulse. Very often the results are written to an internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but less expensive and higher capacity <a href="/wiki/Random-access_memory" title="Random-access memory">main memory</a>. </p><p>For example, if an instruction that performs addition is to be executed, registers containing operands (numbers to be summed) are activated, as are the parts of the <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">arithmetic logic unit</a> (ALU) that perform addition. When the clock pulse occurs, the operands flow from the source registers into the ALU, and the sum appears at its output. On subsequent clock pulses, other components are enabled (and disabled) to move the output (the sum of the operation) to storage (e.g., a register or memory). If the resulting sum is too large (i.e., it is larger than the ALU's output word size), an arithmetic overflow flag will be set, influencing the next operation. </p> <div class="mw-heading mw-heading2"><h2 id="Structure_and_implementation">Structure and implementation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=10" title="Edit section: Structure and implementation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/Processor_design" title="Processor design">Processor design</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:ABasicComputer.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/ABasicComputer.svg/370px-ABasicComputer.svg.png" decoding="async" width="370" height="253" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/ABasicComputer.svg/555px-ABasicComputer.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3a/ABasicComputer.svg/740px-ABasicComputer.svg.png 2x" data-file-width="640" data-file-height="438" /></a><figcaption>Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions.</figcaption></figure> <p>Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set</a>. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a different part of a program. Each instruction is represented by a unique combination of <a href="/wiki/Bit" title="Bit">bits</a>, known as the machine language <a href="/wiki/Opcode" title="Opcode">opcode</a>. While processing an instruction, the CPU decodes the opcode (via a <a href="/wiki/Binary_decoder" title="Binary decoder">binary decoder</a>) into control signals, which orchestrate the behavior of the CPU. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers to be summed in the case of an addition operation). Going up the complexity scale, a machine language program is a collection of machine language instructions that the CPU executes. </p><p>The actual mathematical operation for each instruction is performed by a <a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a> circuit within the CPU's processor known as the <a href="/wiki/Arithmetic%E2%80%93logic_unit" class="mw-redirect" title="Arithmetic–logic unit">arithmetic–logic unit</a> or ALU. In general, a CPU executes an instruction by fetching it from memory, using its ALU to perform an operation, and then storing the result to memory. Besides the instructions for integer mathematics and logic operations, various other machine instructions exist, such as those for loading data from memory and storing it back, branching operations, and mathematical operations on floating-point numbers performed by the CPU's <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU).<sup id="cite_ref-73" class="reference"><a href="#cite_note-73"><span class="cite-bracket">[</span>68<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Control_unit">Control unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=11" title="Edit section: Control unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Control_unit" title="Control unit">Control unit</a></div> <p>The <b>control unit</b> (CU) is a component of the CPU that directs the operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor. </p><p>It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. <a href="/wiki/John_von_Neumann" title="John von Neumann">John von Neumann</a> included the control unit as part of the <a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">von Neumann architecture</a>. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<sup id="cite_ref-74" class="reference"><a href="#cite_note-74"><span class="cite-bracket">[</span>69<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Arithmetic_logic_unit">Arithmetic logic unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=12" title="Edit section: Arithmetic logic unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:ALU_block.gif" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/ALU_block.gif/290px-ALU_block.gif" decoding="async" width="290" height="160" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/0f/ALU_block.gif/435px-ALU_block.gif 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/0f/ALU_block.gif/580px-ALU_block.gif 2x" data-file-width="1569" data-file-height="866" /></a><figcaption>Symbolic representation of an ALU and its input and output signals</figcaption></figure> <p>The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and <a href="/wiki/Bitwise_logic" class="mw-redirect" title="Bitwise logic">bitwise logic</a> operations. The inputs to the ALU are the data words to be operated on (called <a href="/wiki/Operands" class="mw-redirect" title="Operands">operands</a>), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from <a href="/wiki/Processor_register" title="Processor register">internal CPU registers</a>, external memory, or constants generated by the ALU itself. </p><p>When all input signals have settled and propagated through the ALU circuitry, the result of the performed operation appears at the ALU's outputs. The result consists of both a data word, which may be stored in a register or memory, and status information that is typically stored in a special, internal CPU register reserved for this purpose. </p><p>Modern CPUs typically contain more than one ALU to improve performance. </p> <div class="mw-heading mw-heading3"><h3 id="Address_generation_unit">Address generation unit</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=13" title="Edit section: Address generation unit"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a></div> <p>The address generation unit (AGU), sometimes also called the address computation unit (ACU),<sup id="cite_ref-75" class="reference"><a href="#cite_note-75"><span class="cite-bracket">[</span>70<span class="cite-bracket">]</span></a></sup> is an <a href="/wiki/Execution_unit" title="Execution unit">execution unit</a> inside the CPU that calculates <a href="/wiki/Memory_address" title="Memory address">addresses</a> used by the CPU to access <a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a>. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of <a href="/wiki/CPU_cycle" class="mw-redirect" title="CPU cycle">CPU cycles</a> required for executing various <a href="/wiki/Machine_instruction" class="mw-redirect" title="Machine instruction">machine instructions</a> can be reduced, bringing performance improvements. </p><p>While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of <a href="/wiki/Array_element" class="mw-redirect" title="Array element">array elements</a> must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different <a href="/wiki/Integer_arithmetic_operation" class="mw-redirect" title="Integer arithmetic operation">integer arithmetic operations</a>, such as addition, subtraction, <a href="/wiki/Modulo_operation" class="mw-redirect" title="Modulo operation">modulo operations</a>, or <a href="/wiki/Bit_shift" class="mw-redirect" title="Bit shift">bit shifts</a>. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily <a href="/wiki/Instruction_cycle" title="Instruction cycle">decode and execute</a> quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle. </p><p>Capabilities of an AGU depend on a particular CPU and its <a href="/wiki/Computer_architecture" title="Computer architecture">architecture</a>. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple <a href="/wiki/Operand" title="Operand">operands</a> at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> nature of advanced CPU designs. For example, <a href="/wiki/Intel" title="Intel">Intel</a> incorporates multiple AGUs into its <a href="/wiki/Sandy_Bridge_(microarchitecture)" class="mw-redirect" title="Sandy Bridge (microarchitecture)">Sandy Bridge</a> and <a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitectures</a>, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel. </p> <div class="mw-heading mw-heading3"><h3 id="Memory_management_unit_(MMU)"><span id="Memory_management_unit_.28MMU.29"></span>Memory management unit (MMU)</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=14" title="Edit section: Memory management unit (MMU)"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></div> <p>Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit, translating logical addresses into physical RAM addresses, providing <a href="/wiki/Memory_protection" title="Memory protection">memory protection</a> and <a href="/wiki/Paging" class="mw-redirect" title="Paging">paging</a> abilities, useful for <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a>. Simpler processors, especially <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a>, usually don't include an MMU. </p> <div class="mw-heading mw-heading3"><h3 id="Cache">Cache</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=15" title="Edit section: Cache"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>A <a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a><sup id="cite_ref-76" class="reference"><a href="#cite_note-76"><span class="cite-bracket">[</span>71<span class="cite-bracket">]</span></a></sup> is a <a href="/wiki/Hardware_cache" class="mw-redirect" title="Hardware cache">hardware cache</a> used by the central processing unit (CPU) of a <a href="/wiki/Computer" title="Computer">computer</a> to reduce the average cost (time or energy) to access <a href="/wiki/Data_(computing)" class="mw-redirect" title="Data (computing)">data</a> from the <a href="/wiki/Main_memory" class="mw-redirect" title="Main memory">main memory</a>. A cache is a smaller, faster memory, closer to a <a href="/wiki/Processor_core" class="mw-redirect" title="Processor core">processor core</a>, which stores copies of the data from frequently used main <a href="/wiki/Memory_location" class="mw-redirect" title="Memory location">memory locations</a>. Most CPUs have different independent caches, including <a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">instruction</a> and <a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">data caches</a>, where the data cache is usually organized as a hierarchy of more cache levels (L1, L2, L3, L4, etc.). </p><p>All modern (fast) CPUs (with few specialized exceptions<sup id="cite_ref-77" class="reference"><a href="#cite_note-77"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup>) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a> has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on <a href="/wiki/Dynamic_random-access_memory" title="Dynamic random-access memory">dynamic random-access memory</a> (DRAM), rather than on <a href="/wiki/Static_random-access_memory" title="Static random-access memory">static random-access memory</a> (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently. </p><p>Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the <a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">translation lookaside buffer</a> (TLB) that is part of the <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) that most CPUs have. </p><p>Caches are generally sized in powers of two: 2, 8, 16 etc. <a href="/wiki/Kibibyte" class="mw-redirect" title="Kibibyte">KiB</a> or <a href="/wiki/Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> (for larger non-L1) sizes, although the <a href="/wiki/IBM_z13_(microprocessor)" class="mw-redirect" title="IBM z13 (microprocessor)">IBM z13</a> has a 96 KiB L1 instruction cache.<sup id="cite_ref-78" class="reference"><a href="#cite_note-78"><span class="cite-bracket">[</span>72<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Clock_rate">Clock rate</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=16" title="Edit section: Clock rate"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></div> <p>Most CPUs are <a href="/wiki/Synchronous_circuit" title="Synchronous circuit">synchronous circuits</a>, which means they employ a <a href="/wiki/Clock_signal" title="Clock signal">clock signal</a> to pace their sequential operations. The clock signal is produced by an external <a href="/wiki/Electronic_oscillator" title="Electronic oscillator">oscillator circuit</a> that generates a consistent number of pulses each second in the form of a periodic <a href="/wiki/Square_wave" title="Square wave">square wave</a>. The frequency of the clock pulses determines the rate at which a CPU executes instructions and, consequently, the faster the clock, the more instructions the CPU will execute each second. </p><p>To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU. In setting the clock period to a value well above the worst-case <a href="/wiki/Propagation_delay" title="Propagation delay">propagation delay</a>, it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below). </p><p>However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clock signals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue, as clock rates increase dramatically, is the amount of heat that is <a href="/wiki/CPU_power_dissipation" class="mw-redirect" title="CPU power dissipation">dissipated by the CPU</a>. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state. Therefore, as clock rate increases, so does energy consumption, causing the CPU to require more <a href="/wiki/Heat_dissipation" class="mw-redirect" title="Heat dissipation">heat dissipation</a> in the form of <a href="/wiki/CPU_cooling" class="mw-redirect" title="CPU cooling">CPU cooling</a> solutions. </p><p>One method of dealing with the switching of unneeded components is called <a href="/wiki/Clock_gating" title="Clock gating">clock gating</a>, which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs. One notable recent CPU design that uses extensive clock gating is the IBM <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a>-based <a href="/wiki/Xenon_(processor)" title="Xenon (processor)">Xenon</a> used in the <a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a>; this reduces the power requirements of the Xbox 360.<sup id="cite_ref-79" class="reference"><a href="#cite_note-79"><span class="cite-bracket">[</span>73<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Clockless_CPUs">Clockless CPUs</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=17" title="Edit section: Clockless CPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and <a href="/wiki/Heat_dissipation" class="mw-redirect" title="Heat dissipation">heat dissipation</a> in comparison with similar synchronous designs. While somewhat uncommon, entire <a href="/wiki/Asynchronous_circuit#Asynchronous_CPU" title="Asynchronous circuit">asynchronous CPUs</a> have been built without using a global clock signal. Two notable examples of this are the <a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a> compliant <a href="/wiki/AMULET_microprocessor" class="mw-redirect" title="AMULET microprocessor">AMULET</a> and the <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> R3000 compatible MiniMIPS.<sup id="cite_ref-:2_80-0" class="reference"><a href="#cite_note-:2-80"><span class="cite-bracket">[</span>74<span class="cite-bracket">]</span></a></sup> </p><p>Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">ALUs</a> in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for <a href="/wiki/Embedded_computer" class="mw-redirect" title="Embedded computer">embedded computers</a>.<sup id="cite_ref-81" class="reference"><a href="#cite_note-81"><span class="cite-bracket">[</span>75<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Voltage_regulator_module">Voltage regulator module</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=18" title="Edit section: Voltage regulator module"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Voltage_regulator_module" title="Voltage regulator module">Voltage regulator module</a></div> <p>Many modern CPUs have a die-integrated power managing module which regulates on-demand voltage supply to the CPU circuitry allowing it to keep balance between performance and power consumption. </p> <div class="mw-heading mw-heading3"><h3 id="Integer_range">Integer range</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=19" title="Edit section: Integer range"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar <a href="/wiki/Decimal" title="Decimal">decimal</a> (base 10) <a href="/wiki/Numeral_system" title="Numeral system">numeral system</a> values, and others have employed more unusual representations such as <a href="/wiki/Balanced_ternary" title="Balanced ternary">ternary</a> (base three). Nearly all modern CPUs represent numbers in <a href="/wiki/Binary_numeral_system" class="mw-redirect" title="Binary numeral system">binary</a> form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" <a href="/wiki/Volt" title="Volt">voltage</a>.<sup id="cite_ref-82" class="reference"><a href="#cite_note-82"><span class="cite-bracket">[</span>g<span class="cite-bracket">]</span></a></sup> </p> <figure class="mw-default-size mw-halign-left" typeof="mw:File/Thumb"><a href="/wiki/File:Binary_Forty.PNG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/25/Binary_Forty.PNG/220px-Binary_Forty.PNG" decoding="async" width="220" height="57" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/25/Binary_Forty.PNG/330px-Binary_Forty.PNG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/25/Binary_Forty.PNG/440px-Binary_Forty.PNG 2x" data-file-width="773" data-file-height="199" /></a><figcaption>A six-bit word containing the binary encoded representation of decimal value 40. Most modern CPUs employ word sizes that are a power of two, for example 8, 16, 32 or 64 bits.</figcaption></figure> <p>Related to numeric representation is the size and precision of integer numbers that a CPU can represent. In the case of a binary CPU, this is measured by the number of bits (significant digits of a binary encoded integer) that the CPU can process in one operation, which is commonly called <a href="/wiki/Word_(data_type)" class="mw-redirect" title="Word (data type)"><i>word size</i></a>, <i>bit width</i>, <i>data path width</i>, <i>integer precision</i>, or <i>integer size</i>. A CPU's integer size determines the range of integer values on which it can directly operate.<sup id="cite_ref-83" class="reference"><a href="#cite_note-83"><span class="cite-bracket">[</span>h<span class="cite-bracket">]</span></a></sup> For example, an <a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a> CPU can directly manipulate integers represented by eight bits, which have a range of 256 (2<sup>8</sup>) discrete integer values. </p><p>Integer range can also affect the number of memory locations the CPU can directly address (an address is an integer value representing a specific memory location). For example, if a binary CPU uses 32 bits to represent a memory address then it can directly address 2<sup>32</sup> memory locations. To circumvent this limitation and for various other reasons, some CPUs use mechanisms (such as <a href="/wiki/Bank_switching" title="Bank switching">bank switching</a>) that allow additional memory to be addressed. </p><p>CPUs with larger word sizes require more circuitry and consequently are physically larger, cost more and consume more power (and therefore generate more heat). As a result, smaller 4- or 8-bit <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a> are commonly used in modern applications even though CPUs with much larger word sizes (such as 16, 32, 64, even 128-bit) are available. When higher performance is required, however, the benefits of a larger word size (larger data ranges and address spaces) may outweigh the disadvantages. A CPU can have internal data paths shorter than the word size to reduce size and cost. For example, even though the <a href="/wiki/IBM_System/360" title="IBM System/360">IBM System/360</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> was a 32-bit instruction set, the System/360 <a href="/wiki/IBM_System/360_Model_30" title="IBM System/360 Model 30">Model 30</a> and <a href="/wiki/IBM_System/360_Model_40" title="IBM System/360 Model 40">Model 40</a> had 8-bit data paths in the arithmetic logical unit, so that a 32-bit add required four cycles, one for each 8 bits of the operands, and, even though the <a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a> instruction set was a 32-bit instruction set, the <a href="/wiki/Motorola_68000" title="Motorola 68000">Motorola 68000</a> and <a href="/wiki/Motorola_68010" title="Motorola 68010">Motorola 68010</a> had 16-bit data paths in the arithmetic logical unit, so that a 32-bit add required two cycles. </p><p>To gain some of the advantages afforded by both lower and higher bit lengths, many <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction sets</a> have different bit widths for integer and floating-point data, allowing CPUs implementing that instruction set to have different bit widths for different portions of the device. For example, the IBM <a href="/wiki/System/360" class="mw-redirect" title="System/360">System/360</a> instruction set was primarily 32 bit, but supported 64-bit <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point</a> values to facilitate greater accuracy and range in floating-point numbers.<sup id="cite_ref-amdahl1964_37-1" class="reference"><a href="#cite_note-amdahl1964-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup> The System/360 Model 65 had an 8-bit adder for decimal and fixed-point binary arithmetic and a 60-bit adder for floating-point arithmetic.<sup id="cite_ref-84" class="reference"><a href="#cite_note-84"><span class="cite-bracket">[</span>76<span class="cite-bracket">]</span></a></sup> Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose use where a reasonable balance of integer and floating-point capability is required. </p> <div class="mw-heading mw-heading3"><h3 id="Parallelism">Parallelism</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=20" title="Edit section: Parallelism"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Parallel_computing" title="Parallel computing">Parallel computing</a></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Nopipeline.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2c/Nopipeline.png/440px-Nopipeline.png" decoding="async" width="440" height="79" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2c/Nopipeline.png/660px-Nopipeline.png 1.5x, //upload.wikimedia.org/wikipedia/commons/2/2c/Nopipeline.png 2x" data-file-width="876" data-file-height="157" /></a><figcaption>Model of a subscalar CPU, in which it takes fifteen clock cycles to complete three instructions</figcaption></figure> <p>The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as <i>subscalar</i>, operates on and executes one instruction on one or two pieces of data at a time, that is less than one <a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">instruction per clock cycle</a> (<span class="nowrap">IPC < 1</span>). </p><p>This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second <a href="/wiki/Execution_unit" title="Execution unit">execution unit</a> (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach <i>scalar</i> performance (one instruction per clock cycle, <span class="nowrap">IPC = 1</span>). However, the performance is nearly always subscalar (less than one instruction per clock cycle, <span class="nowrap">IPC < 1</span>). </p><p>Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques: </p> <ul><li><i><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">instruction-level parallelism</a></i> (ILP), which seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the use of on-die execution resources);</li> <li><i><a href="/wiki/Task-level_parallelism" class="mw-redirect" title="Task-level parallelism">task-level parallelism</a></i> (TLP), which purposes to increase the number of <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> or <a href="/wiki/Process_(computing)" title="Process (computing)">processes</a> that a CPU can execute simultaneously.</li></ul> <p>Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.<sup id="cite_ref-85" class="reference"><a href="#cite_note-85"><span class="cite-bracket">[</span>i<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading4"><h4 id="Instruction-level_parallelism">Instruction-level parallelism</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=21" title="Edit section: Instruction-level parallelism"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction-level parallelism</a></div> <figure class="mw-default-size mw-halign-left" typeof="mw:File/Thumb"><a href="/wiki/File:Fivestagespipeline.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/21/Fivestagespipeline.png/330px-Fivestagespipeline.png" decoding="async" width="330" height="96" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/21/Fivestagespipeline.png/495px-Fivestagespipeline.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/21/Fivestagespipeline.png/660px-Fivestagespipeline.png 2x" data-file-width="972" data-file-height="282" /></a><figcaption>Basic five-stage pipeline. In the best case scenario, this pipeline can sustain a completion rate of one instruction per clock cycle.</figcaption></figure> <p>One of the simplest methods for increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is a technique known as <a href="/wiki/Instruction_pipelining" title="Instruction pipelining">instruction pipelining</a>, and is used in almost all modern general-purpose CPUs. Pipelining allows multiple instruction to be executed at a time by breaking the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired. </p><p>Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. Therefore, pipelined processors must check for these sorts of conditions and delay a portion of the pipeline if necessary. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage). </p> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Superscalarpipeline.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/46/Superscalarpipeline.svg/330px-Superscalarpipeline.svg.png" decoding="async" width="330" height="193" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/46/Superscalarpipeline.svg/495px-Superscalarpipeline.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/46/Superscalarpipeline.svg/660px-Superscalarpipeline.svg.png 2x" data-file-width="978" data-file-height="571" /></a><figcaption>A simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per clock cycle can be completed.</figcaption></figure> <p>Improvements in instruction pipelining led to further decreases in the idle time of CPU components. Designs that are said to be superscalar include a long instruction pipeline and multiple identical <a href="/wiki/Execution_unit" title="Execution unit">execution units</a>, such as <a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">load–store units</a>, <a href="/wiki/Arithmetic%E2%80%93logic_unit" class="mw-redirect" title="Arithmetic–logic unit">arithmetic–logic units</a>, <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point units</a> and <a href="/wiki/Address_generation_unit" title="Address generation unit">address generation units</a>.<sup id="cite_ref-86" class="reference"><a href="#cite_note-86"><span class="cite-bracket">[</span>77<span class="cite-bracket">]</span></a></sup> In a superscalar pipeline, instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so, they are dispatched to execution units, resulting in their simultaneous execution. In general, the number of instructions that a superscalar CPU will complete in a cycle is dependent on the number of instructions it is able to dispatch simultaneously to execution units. </p><p>Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and requires significant amounts of <a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a>. It also makes <a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">hazard</a>-avoiding techniques like <a href="/wiki/Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a>, <a href="/wiki/Speculative_execution" title="Speculative execution">speculative execution</a>, <a href="/wiki/Register_renaming" title="Register renaming">register renaming</a>, <a href="/wiki/Out-of-order_execution" title="Out-of-order execution">out-of-order execution</a> and <a href="/wiki/Transactional_memory" title="Transactional memory">transactional memory</a> crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies. Also in case of <a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">single instruction stream, multiple data stream</a>, a case when a lot of data from the same type has to be processed, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monotonous program engines such as video creation software and photo processing. </p><p>When a fraction of the CPU is superscalar, the part that is not suffers a performance penalty due to scheduling stalls. The Intel <a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a> <a href="/wiki/Pentium" title="Pentium">Pentium</a> had two superscalar ALUs which could accept one instruction per clock cycle each, but its FPU could not. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5 architecture, <a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a>, added superscalar abilities to its floating-point features. </p><p>Simple pipelining and superscalar design increase a CPU's ILP by allowing it to execute instructions at rates surpassing one instruction per clock cycle. Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA). The strategy of the <a href="/wiki/Very_long_instruction_word" title="Very long instruction word">very long instruction word</a> (VLIW) causes some ILP to become implied directly by the software, reducing the CPU's work in boosting ILP and thereby reducing design complexity. </p> <div class="mw-heading mw-heading4"><h4 id="Task-level_parallelism">Task-level parallelism</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=22" title="Edit section: Task-level parallelism"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a> and <a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core processor</a></div> <p>Another strategy of achieving performance is to execute multiple <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> or <a href="/wiki/Process_(computing)" title="Process (computing)">processes</a> in parallel. This area of research is known as <a href="/wiki/Parallel_computing" title="Parallel computing">parallel computing</a>.<sup id="cite_ref-87" class="reference"><a href="#cite_note-87"><span class="cite-bracket">[</span>78<span class="cite-bracket">]</span></a></sup> In <a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a>, this strategy is known as <a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">multiple instruction stream, multiple data stream</a> (MIMD).<sup id="cite_ref-88" class="reference"><a href="#cite_note-88"><span class="cite-bracket">[</span>79<span class="cite-bracket">]</span></a></sup> </p><p>One technology used for this purpose is <a href="/wiki/Multiprocessing" title="Multiprocessing">multiprocessing</a> (MP).<sup id="cite_ref-89" class="reference"><a href="#cite_note-89"><span class="cite-bracket">[</span>80<span class="cite-bracket">]</span></a></sup> The initial type of this technology is known as <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as <a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">non-uniform memory access</a> (NUMA) and <a href="/wiki/Directory-based_coherence_protocols" class="mw-redirect" title="Directory-based coherence protocols">directory-based coherence protocols</a> were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processor</a>. </p><p>It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented <a href="/wiki/Input/output" title="Input/output">input/output</a> processing such as <a href="/wiki/Direct_memory_access" title="Direct memory access">direct memory access</a> as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as <a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">multi-threading</a> (MT). The approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU are replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as <a href="/wiki/Temporal_multithreading" title="Temporal multithreading">temporal multithreading</a>, where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the <a href="/wiki/UltraSPARC_T1" title="UltraSPARC T1">UltraSPARC T1</a>. Another type of MT is <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a>, where instructions from multiple threads are executed in parallel within one CPU clock cycle. </p><p>For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel <a href="/wiki/Pentium_4" title="Pentium 4">Pentium 4</a>. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP techniques due to the growing disparity between CPU operating frequencies and main memory operating frequencies as well as escalating CPU power dissipation owing to more esoteric ILP techniques. </p><p>CPU designers then borrowed ideas from commercial computing markets such as <a href="/wiki/Transaction_processing" title="Transaction processing">transaction processing</a>, where the aggregate performance of multiple programs, also known as <a href="/wiki/Throughput" class="mw-redirect" title="Throughput">throughput</a> computing, was more important than the performance of a single thread or process. </p><p>This reversal of emphasis is evidenced by the proliferation of dual and more core processor designs and notably, Intel's newer designs resembling its less superscalar <a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> architecture. Late designs in several processor families exhibit CMP, including the <a href="/wiki/X86-64" title="X86-64">x86-64</a> <a href="/wiki/Opteron" title="Opteron">Opteron</a> and <a href="/wiki/Athlon_64_X2" title="Athlon 64 X2">Athlon 64 X2</a>, the <a href="/wiki/SPARC" title="SPARC">SPARC</a> <a href="/wiki/UltraSPARC_T1" title="UltraSPARC T1">UltraSPARC T1</a>, IBM <a href="/wiki/POWER4" title="POWER4">POWER4</a> and <a href="/wiki/POWER5" title="POWER5">POWER5</a>, as well as several <a href="/wiki/Video_game_console" title="Video game console">video game console</a> CPUs like the <a href="/wiki/Xbox_360" title="Xbox 360">Xbox 360</a>'s triple-core PowerPC design, and the <a href="/wiki/PlayStation_3" title="PlayStation 3">PlayStation 3</a>'s 7-core <a href="/wiki/Cell_(microprocessor)" class="mw-redirect" title="Cell (microprocessor)">Cell microprocessor</a>. </p> <div class="mw-heading mw-heading4"><h4 id="Data_parallelism">Data parallelism</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=23" title="Edit section: Data parallelism"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main articles: <a href="/wiki/Vector_processor" title="Vector processor">Vector processor</a> and <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a></div> <p>A less common but increasingly important paradigm of processors (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device.<sup id="cite_ref-90" class="reference"><a href="#cite_note-90"><span class="cite-bracket">[</span>j<span class="cite-bracket">]</span></a></sup> As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Using <a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a>, these two schemes of dealing with data are generally referred to as <i>single instruction</i> stream, <i>multiple data</i> stream (<a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a>) and <i>single instruction</i> stream, <i>single data</i> stream (<a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a>), respectively. The great utility in creating processors that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a <a href="/wiki/Dot_product" title="Dot product">dot product</a>) to be performed on a large set of data. Some classic examples of these types of tasks include <a href="/wiki/Multimedia" title="Multimedia">multimedia</a> applications (images, video and sound), as well as many types of <a href="/wiki/Scientific_computing" class="mw-redirect" title="Scientific computing">scientific</a> and engineering tasks. Whereas a scalar processor must complete the entire process of fetching, decoding and executing each instruction and value in a set of data, a vector processor can perform a single operation on a comparatively large set of data with one instruction. This is only possible when the application tends to require many steps which apply one operation to a large set of data. </p><p>Most early vector processors, such as the <a href="/wiki/Cray-1" title="Cray-1">Cray-1</a>, were associated almost exclusively with scientific research and <a href="/wiki/Cryptography" title="Cryptography">cryptography</a> applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose processors has become significant. Shortly after inclusion of <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point units</a> started to become commonplace in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose processors.<sup class="noprint Inline-Template" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Manual_of_Style/Dates_and_numbers#Chronological_items" title="Wikipedia:Manual of Style/Dates and numbers"><span title="The time period mentioned near this tag is ambiguous. (September 2016)">when?</span></a></i>]</sup> Some of these early SIMD specifications – like HP's <a href="/wiki/Multimedia_Acceleration_eXtensions" title="Multimedia Acceleration eXtensions">Multimedia Acceleration eXtensions</a> (MAX) and Intel's <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> – were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point</a> numbers. Progressively, developers refined and remade these early designs into some of the common modern SIMD specifications, which are usually associated with one <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA). Some notable modern examples include Intel's <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE) and the PowerPC-related <a href="/wiki/AltiVec" title="AltiVec">AltiVec</a> (also known as VMX).<sup id="cite_ref-91" class="reference"><a href="#cite_note-91"><span class="cite-bracket">[</span>k<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Hardware_performance_counter">Hardware performance counter</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=24" title="Edit section: Hardware performance counter"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/Hardware_performance_counter" title="Hardware performance counter">Hardware performance counter</a></div> <p>Many modern architectures (including embedded ones) often include <a href="/wiki/Hardware_performance_counter" title="Hardware performance counter">hardware performance counters</a> (HPC), which enables low-level (instruction-level) collection, <a href="/wiki/Benchmark_(computing)" title="Benchmark (computing)">benchmarking</a>, debugging or analysis of running software metrics.<sup id="cite_ref-92" class="reference"><a href="#cite_note-92"><span class="cite-bracket">[</span>81<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-93" class="reference"><a href="#cite_note-93"><span class="cite-bracket">[</span>82<span class="cite-bracket">]</span></a></sup> HPC may also be used to discover and analyze unusual or suspicious activity of the software, such as <a href="/wiki/Return-oriented_programming" title="Return-oriented programming">return-oriented programming</a> (ROP) or <a href="/wiki/Sigreturn-oriented_programming" title="Sigreturn-oriented programming">sigreturn-oriented programming</a> (SROP) exploits etc.<sup id="cite_ref-94" class="reference"><a href="#cite_note-94"><span class="cite-bracket">[</span>83<span class="cite-bracket">]</span></a></sup> This is usually done by software-security teams to assess and find malicious binary programs.<sup id="cite_ref-95" class="reference"><a href="#cite_note-95"><span class="cite-bracket">[</span>84<span class="cite-bracket">]</span></a></sup> </p><p>Many major vendors (such as <a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/Intel" title="Intel">Intel</a>, <a href="/wiki/AMD" title="AMD">AMD</a>, and <a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a>) provide software interfaces (usually written in C/C++) that can be used to collect data from the CPU's <a href="/wiki/Hardware_register" title="Hardware register">registers</a> in order to get metrics.<sup id="cite_ref-96" class="reference"><a href="#cite_note-96"><span class="cite-bracket">[</span>85<span class="cite-bracket">]</span></a></sup> Operating system vendors also provide software like <code><a href="/wiki/Perf_(Linux)" title="Perf (Linux)">perf</a></code> (Linux) to record, <a href="/wiki/Benchmark_(computing)" title="Benchmark (computing)">benchmark</a>, or <a href="/wiki/Tracing_(software)" title="Tracing (software)">trace</a> CPU events running kernels and applications. </p><p>Hardware counters provide a low-overhead method for collecting comprehensive performance metrics related to a CPU's core elements (functional units, caches, main memory, etc.) – a significant advantage over software profilers.<sup id="cite_ref-97" class="reference"><a href="#cite_note-97"><span class="cite-bracket">[</span>86<span class="cite-bracket">]</span></a></sup> Additionally, they generally eliminate the need to modify the underlying source code of a program.<sup id="cite_ref-98" class="reference"><a href="#cite_note-98"><span class="cite-bracket">[</span>87<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-99" class="reference"><a href="#cite_note-99"><span class="cite-bracket">[</span>88<span class="cite-bracket">]</span></a></sup> Because hardware designs differ between architectures, the specific types and interpretations of hardware counters will also change. </p> <div class="mw-heading mw-heading2"><h2 id="Privileged_modes">Privileged modes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=25" title="Edit section: Privileged modes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Most modern CPUs have <a href="/wiki/Supervisor_mode" class="mw-redirect" title="Supervisor mode">privileged modes</a> to support operating systems and virtualization. </p><p><a href="/wiki/Cloud_computing" title="Cloud computing">Cloud computing</a> can use virtualization to provide <b>virtual central processing units</b><sup id="cite_ref-100" class="reference"><a href="#cite_note-100"><span class="cite-bracket">[</span>89<span class="cite-bracket">]</span></a></sup> (<b>vCPU</b>s) for separate users.<sup id="cite_ref-101" class="reference"><a href="#cite_note-101"><span class="cite-bracket">[</span>90<span class="cite-bracket">]</span></a></sup> </p><p>A host is the virtual equivalent of a physical machine, on which a virtual system is operating.<sup id="cite_ref-102" class="reference"><a href="#cite_note-102"><span class="cite-bracket">[</span>91<span class="cite-bracket">]</span></a></sup> When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a <a href="/wiki/Computer_cluster" title="Computer cluster">cluster</a>. In some systems, it is possible to dynamically add and remove from a cluster. Resources available at a host and cluster level can be partitioned into <a href="/wiki/Pool_(computer_science)" title="Pool (computer science)">resources pools</a> with fine <a href="/wiki/Granularity_(parallel_computing)" title="Granularity (parallel computing)">granularity</a>. </p> <div class="mw-heading mw-heading2"><h2 id="Performance"><span class="anchor" id="PCM"></span>Performance</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=26" title="Edit section: Performance"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Further information: <a href="/wiki/Computer_performance" title="Computer performance">Computer performance</a> and <a href="/wiki/Benchmark_(computing)" title="Benchmark (computing)">Benchmark (computing)</a></div> <p>The <i>performance</i> or <i>speed</i> of a processor depends on, among many other factors, the clock rate (generally given in multiples of <a href="/wiki/Hertz" title="Hertz">hertz</a>) and the instructions per clock (IPC), which together are the factors for the <a href="/wiki/Instructions_per_second" title="Instructions per second">instructions per second</a> (IPS) that the CPU can perform.<sup id="cite_ref-Freq_103-0" class="reference"><a href="#cite_note-Freq-103"><span class="cite-bracket">[</span>92<span class="cite-bracket">]</span></a></sup> Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the <a href="/wiki/Memory_hierarchy" title="Memory hierarchy">memory hierarchy</a> also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, various standardized tests, often called <a href="/wiki/Benchmark_(computing)" title="Benchmark (computing)">"benchmarks"</a> for this purpose‍—‌ such as <a href="/wiki/SPECint" title="SPECint">SPECint</a>‍—‌have been developed to attempt to measure the real effective performance in commonly used applications. </p><p>Processing performance of computers is increased by using <a href="/wiki/Multi-core_processor" title="Multi-core processor">multi-core processors</a>, which essentially is plugging two or more individual processors (called <i>cores</i> in this sense) into one integrated circuit.<sup id="cite_ref-tt_104-0" class="reference"><a href="#cite_note-tt-104"><span class="cite-bracket">[</span>93<span class="cite-bracket">]</span></a></sup> Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is far smaller, only about 50%, due to imperfect software algorithms and implementation.<sup id="cite_ref-105" class="reference"><a href="#cite_note-105"><span class="cite-bracket">[</span>94<span class="cite-bracket">]</span></a></sup> Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floor handling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough to handle the information. Multi-core CPUs enhance a computer's ability to run several tasks simultaneously by providing additional processing power. However, the increase in speed is not directly proportional to the number of cores added. This is because the cores need to interact through specific channels, and this inter-core communication consumes a portion of the available processing speed.<sup id="cite_ref-106" class="reference"><a href="#cite_note-106"><span class="cite-bracket">[</span>95<span class="cite-bracket">]</span></a></sup> </p><p>Due to specific capabilities of modern CPUs, such as <a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">simultaneous multithreading</a> and <a href="/wiki/Uncore" title="Uncore">uncore</a>, which involve sharing of actual CPU resources while aiming at increased utilization, monitoring performance levels and hardware use gradually became a more complex task.<sup id="cite_ref-107" class="reference"><a href="#cite_note-107"><span class="cite-bracket">[</span>96<span class="cite-bracket">]</span></a></sup> As a response, some CPUs implement additional hardware logic that monitors actual use of various parts of a CPU and provides various counters accessible to software; an example is Intel's <i>Performance Counter Monitor</i> technology.<sup id="cite_ref-intel-pcm_9-1" class="reference"><a href="#cite_note-intel-pcm-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=27" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239009302">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output .portalbox-image{display:table-cell;padding:0.2em;vertical-align:middle;text-align:center}.mw-parser-output .portalbox-link{display:table-cell;padding:0.2em 0.2em 0.2em 0.3em;vertical-align:middle}@media(min-width:720px){.mw-parser-output .portalleft{clear:left;float:left;margin:0.5em 1em 0.5em 0}.mw-parser-output .portalright{clear:right;float:right;margin:0.5em 0 0.5em 1em}}</style><ul role="navigation" aria-label="Portals" class="noprint portalbox portalborder portalright"> <li class="portalbox-entry"><span class="portalbox-image"><span class="noviewer" typeof="mw:File"><a href="/wiki/File:Noun-technology.svg" class="mw-file-description"><img alt="icon" src="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/29px-Noun-technology.svg.png" decoding="async" width="29" height="28" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/43px-Noun-technology.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/a/a9/Noun-technology.svg/57px-Noun-technology.svg.png 2x" data-file-width="90" data-file-height="88" /></a></span></span><span class="portalbox-link"><a href="/wiki/Portal:Technology" title="Portal:Technology">Technology portal</a></span></li></ul> <style data-mw-deduplicate="TemplateStyles:r1184024115">.mw-parser-output .div-col{margin-top:0.3em;column-width:30em}.mw-parser-output .div-col-small{font-size:90%}.mw-parser-output .div-col-rules{column-rule:1px solid #aaa}.mw-parser-output .div-col dl,.mw-parser-output .div-col ol,.mw-parser-output .div-col ul{margin-top:0}.mw-parser-output .div-col li,.mw-parser-output .div-col dd{page-break-inside:avoid;break-inside:avoid-column}</style><div class="div-col" style="column-width: 20em;"> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing mode</a></li> <li><a href="/wiki/AMD_Accelerated_Processing_Unit" class="mw-redirect" title="AMD Accelerated Processing Unit">AMD Accelerated Processing Unit</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">Complex instruction set computer</a></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Computer bus</a></li> <li><a href="/wiki/Computer_engineering" title="Computer engineering">Computer engineering</a></li> <li><a href="/wiki/CPU_core_voltage" title="CPU core voltage">CPU core voltage</a></li> <li><a href="/wiki/CPU_socket" title="CPU socket">CPU socket</a></li> <li><a href="/wiki/Data_processing_unit" title="Data processing unit">Data processing unit</a></li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison of instruction set architectures</a></li> <li><a href="/wiki/Protection_ring" title="Protection ring">Protection ring</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream processing</a></li> <li><a href="/wiki/True_Performance_Index" class="mw-redirect" title="True Performance Index">True Performance Index</a></li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a></li> <li><a href="/wiki/Wait_state" title="Wait state">Wait state</a></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=28" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-columns references-column-width reflist-lower-alpha" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-56"><span class="mw-cite-backlink"><b><a href="#cite_ref-56">^</a></b></span> <span class="reference-text">Integrated circuits are now used to implement all CPUs, except for a few machines designed to withstand large electromagnetic pulses, say from a nuclear weapon.</span> </li> <li id="cite_note-67"><span class="mw-cite-backlink"><b><a href="#cite_ref-67">^</a></b></span> <span class="reference-text">The so-called "von Neumann" memo expounded the idea of stored programs,<sup id="cite_ref-66" class="reference"><a href="#cite_note-66"><span class="cite-bracket">[</span>65<span class="cite-bracket">]</span></a></sup> which for example may be stored on <a href="/wiki/Punched_card" title="Punched card">punched cards</a>, paper tape, or magnetic tape.</span> </li> <li id="cite_note-70"><span class="mw-cite-backlink"><b><a href="#cite_ref-70">^</a></b></span> <span class="reference-text">Some early computers, like the Harvard Mark I, did not support any kind of "jump" instruction, effectively limiting the complexity of the programs they could run. It is largely for this reason that these computers are often not considered to contain a proper CPU, despite their close similarity to stored-program computers.</span> </li> <li id="cite_note-71"><span class="mw-cite-backlink"><b><a href="#cite_ref-71">^</a></b></span> <span class="reference-text">Since the program counter counts <i>memory addresses</i> and not <i>instructions</i>, it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word ISAs, this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the PC by four (except in the case of jumps). ISAs that use variable-length instruction words increment the PC by the number of memory words corresponding to the last instruction's length.</span> </li> <li id="cite_note-72"><span class="mw-cite-backlink"><b><a href="#cite_ref-72">^</a></b></span> <span class="reference-text">Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. A system can execute a different ISA by running an emulator.</span> </li> <li id="cite_note-77"><span class="mw-cite-backlink"><b><a href="#cite_ref-77">^</a></b></span> <span class="reference-text">A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software managed. In e.g. microcontrollers it can be better for hard real-time use, to have that or at least no cache, as with one level of memory latencies of loads are predictable.</span> </li> <li id="cite_note-82"><span class="mw-cite-backlink"><b><a href="#cite_ref-82">^</a></b></span> <span class="reference-text">The physical concept of <a href="/wiki/Voltage" title="Voltage">voltage</a> is an analog one by nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, two specific ranges of voltages are defined, one for logic '0' and another for logic '1'. These ranges are dictated by design considerations such as noise margins and characteristics of the devices used to create the CPU.</span> </li> <li id="cite_note-83"><span class="mw-cite-backlink"><b><a href="#cite_ref-83">^</a></b></span> <span class="reference-text">While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set</a> will even facilitate operations on integers larger than it can natively represent by providing instructions to make large integer arithmetic relatively quick. This method of dealing with large integers is slower than utilizing a CPU with higher integer size, but is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See <a href="/wiki/Arbitrary-precision_arithmetic" title="Arbitrary-precision arithmetic">Arbitrary-precision arithmetic</a> for more details on purely software-supported arbitrary-sized integers.</span> </li> <li id="cite_note-85"><span class="mw-cite-backlink"><b><a href="#cite_ref-85">^</a></b></span> <span class="reference-text">Neither <a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">ILP</a> nor <a href="/wiki/Task-level_parallelism" class="mw-redirect" title="Task-level parallelism">TLP</a> is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "<a href="/wiki/Embarrassingly_parallel" title="Embarrassingly parallel">embarrassingly parallel</a> problems". Frequently, a computational problem that can be solved quickly with high TLP design strategies like <a href="/wiki/Symmetric_multiprocessing" title="Symmetric multiprocessing">symmetric multiprocessing</a> takes significantly more time on high ILP devices like superscalar CPUs, and vice versa.</span> </li> <li id="cite_note-90"><span class="mw-cite-backlink"><b><a href="#cite_ref-90">^</a></b></span> <span class="reference-text">Earlier the term <i>scalar</i> was used to compare the IPC count afforded by various ILP methods. Here the term is used in the strictly mathematical sense to contrast with vectors. See <a href="/wiki/Scalar_(mathematics)" title="Scalar (mathematics)">scalar (mathematics)</a> and <a href="/wiki/Vector_(geometric)" class="mw-redirect" title="Vector (geometric)">vector (geometric)</a>.</span> </li> <li id="cite_note-91"><span class="mw-cite-backlink"><b><a href="#cite_ref-91">^</a></b></span> <span class="reference-text">Although SSE/SSE2/SSE3 have superseded MMX in Intel's general-purpose processors, later <a href="/wiki/IA-32" title="IA-32">IA-32</a> designs still support MMX. This is usually done by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instruction sets.</span> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Central_processing_unit&action=edit&section=29" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFTeam" class="citation book cs1">Team, YCT Expert. <a rel="nofollow" class="external text" href="https://books.google.com/books?id=O_fZEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA425"><i>Engineering Drawing & Basic Science</i></a>. Youth Competition Times. p. 425.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Engineering+Drawing+%26+Basic+Science&rft.pages=425&rft.pub=Youth+Competition+Times&rft.aulast=Team&rft.aufirst=YCT+Expert&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DO_fZEAAAQBAJ%26dq%3DA%2Bcentral%2Bprocessing%2Bunit%2B%28CPU%29%25E2%2580%2594also%2Bcalled%2Ba%2Bcentral%2Bprocessor%2Bor%2Bmain%2Bprocessor%25E2%2580%2594is%2Bthe%2Bmost%2Bimportant%2Bprocessor%2Bin%2Ba%2Bgiven%2Bcomputer.%26pg%3DPA425&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFNagpal2008" class="citation book cs1">Nagpal, D. P. (2008). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=LAsbEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA33"><i>Computer Fundamentals</i></a>. S. Chand Publishing. p. 33. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-81-219-2388-0" title="Special:BookSources/978-81-219-2388-0"><bdi>978-81-219-2388-0</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computer+Fundamentals&rft.pages=33&rft.pub=S.+Chand+Publishing&rft.date=2008&rft.isbn=978-81-219-2388-0&rft.aulast=Nagpal&rft.aufirst=D.+P.&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DLAsbEAAAQBAJ%26dq%3DA%2Bcentral%2Bprocessing%2Bunit%2B%28CPU%29%25E2%2580%2594also%2Bcalled%2Ba%2Bcentral%2Bprocessor%2Bor%2Bmain%2Bprocessor%25E2%2580%2594is%2Bthe%2Bmost%2Bimportant%2Bprocessor%2Bin%2Ba%2Bgiven%2Bcomputer.%26pg%3DPA33&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techtarget.com/whatis/definition/processor">"What is processor (CPU)? A definition from WhatIs.com"</a>. <i>WhatIs</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-03-15</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=WhatIs&rft.atitle=What+is+processor+%28CPU%29%3F+A+definition+from+WhatIs.com&rft_id=https%3A%2F%2Fwww.techtarget.com%2Fwhatis%2Fdefinition%2Fprocessor&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFChesalov2023" class="citation book cs1">Chesalov, Alexander (2023-04-12). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=VlG5EAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT54"><i>The fourth industrial revolution glossarium: over 1500 of the hottest terms you will use to create the future</i></a>. Litres. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-5-04-541163-9" title="Special:BookSources/978-5-04-541163-9"><bdi>978-5-04-541163-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=The+fourth+industrial+revolution+glossarium%3A+over+1500+of+the+hottest+terms+you+will+use+to+create+the+future&rft.pub=Litres&rft.date=2023-04-12&rft.isbn=978-5-04-541163-9&rft.aulast=Chesalov&rft.aufirst=Alexander&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DVlG5EAAAQBAJ%26dq%3Dcpu%2Belectronic%2Bcircuitry%2Bexecutes%2Binstructions%2Bof%2Ba%2Bcomputer%2Bprogram%2C%2Bsuch%2Bas%2Barithmetic%2C%2Blogic%2C%2Bcontrolling%2C%2Band%2Binput%2Foutput%2B%28I%2FO%29%2Boperations%26pg%3DPT54&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFJagare2022" class="citation book cs1">Jagare, Ulrika (2022-04-19). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=ZwxsEAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT91"><i>Operating AI: Bridging the Gap Between Technology and Business</i></a>. John Wiley & Sons. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1-119-83321-5" title="Special:BookSources/978-1-119-83321-5"><bdi>978-1-119-83321-5</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Operating+AI%3A+Bridging+the+Gap+Between+Technology+and+Business&rft.pub=John+Wiley+%26+Sons&rft.date=2022-04-19&rft.isbn=978-1-119-83321-5&rft.aulast=Jagare&rft.aufirst=Ulrika&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DZwxsEAAAQBAJ%26dq%3Dcpu%2Belectronic%2Bcircuitry%2Bexecutes%2Binstructions%2Bof%2Ba%2Bcomputer%2Bprogram%2C%2Bsuch%2Bas%2Barithmetic%2C%2Blogic%2C%2Bcontrolling%2C%2Band%2Binput%2Foutput%2B%28I%2FO%29%2Boperations%26pg%3DPT91&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-kuck-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-kuck_6-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFKuck1978" class="citation book cs1">Kuck, David (1978). <i>Computers and Computations, Vol 1</i>. John Wiley & Sons, Inc. p. 12. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0471027164" title="Special:BookSources/978-0471027164"><bdi>978-0471027164</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Computers+and+Computations%2C+Vol+1&rft.pages=12&rft.pub=John+Wiley+%26+Sons%2C+Inc.&rft.date=1978&rft.isbn=978-0471027164&rft.aulast=Kuck&rft.aufirst=David&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-7"><span class="mw-cite-backlink"><b><a href="#cite_ref-7">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFPrabhat2023" class="citation book cs1">Prabhat, Team (2023-04-13). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=sbqcEAAAQBAJ&dq=design,+and+implementation+of+CPUs+have+changed+over+time,+but+their+fundamental+operation+remains+almost+unchanged.&pg=PA95"><i>Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English: Bestseller Book by Team Prabhat: Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English</i></a>. Prabhat Prakashan. p. 95. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-93-5488-527-3" title="Special:BookSources/978-93-5488-527-3"><bdi>978-93-5488-527-3</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Ultimate+Guide+to+SSC+CGL+Combined+Graduate+Level+Tier-I+%26+Tier+II+Prelims+%26+Mains+%28with+Latest+Solved+Question+Papers%29+Guide+Book+English%3A+Bestseller+Book+by+Team+Prabhat%3A+Ultimate+Guide+to+SSC+CGL+Combined+Graduate+Level+Tier-I+%26+Tier+II+Prelims+%26+Mains+%28with+Latest+Solved+Question+Papers%29+Guide+Book+English&rft.pages=95&rft.pub=Prabhat+Prakashan&rft.date=2023-04-13&rft.isbn=978-93-5488-527-3&rft.aulast=Prabhat&rft.aufirst=Team&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DsbqcEAAAQBAJ%26dq%3Ddesign%2C%2Band%2Bimplementation%2Bof%2BCPUs%2Bhave%2Bchanged%2Bover%2Btime%2C%2Bbut%2Btheir%2Bfundamental%2Boperation%2Bremains%2Balmost%2Bunchanged.%26pg%3DPA95&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-8"><span class="mw-cite-backlink"><b><a href="#cite_ref-8">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.techtarget.com/searchdatacenter/definition/multi-core-processor">"What is a multicore processor and how does it work?"</a>. <i>Data Center</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-03-15</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Data+Center&rft.atitle=What+is+a+multicore+processor+and+how+does+it+work%3F&rft_id=https%3A%2F%2Fwww.techtarget.com%2Fsearchdatacenter%2Fdefinition%2Fmulti-core-processor&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-intel-pcm-9"><span class="mw-cite-backlink">^ <a href="#cite_ref-intel-pcm_9-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-intel-pcm_9-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWillhalmDementievFay2014" class="citation web cs1">Willhalm, Thomas; Dementiev, Roman; Fay, Patrick (December 18, 2014). <a rel="nofollow" class="external text" href="https://software.intel.com/en-us/articles/intel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization">"Intel Performance Counter Monitor – A better way to measure CPU utilization"</a>. <i>software.intel.com</i>. <a rel="nofollow" class="external text" href="https://web.archive.org/web/20170222150312/https://software.intel.com/en-us/articles/intel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization">Archived</a> from the original on February 22, 2017<span class="reference-accessdate">. Retrieved <span class="nowrap">February 17,</span> 2015</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=software.intel.com&rft.atitle=Intel+Performance+Counter+Monitor+%E2%80%93+A+better+way+to+measure+CPU+utilization&rft.date=2014-12-18&rft.aulast=Willhalm&rft.aufirst=Thomas&rft.au=Dementiev%2C+Roman&rft.au=Fay%2C+Patrick&rft_id=https%3A%2F%2Fsoftware.intel.com%2Fen-us%2Farticles%2Fintel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-10"><span class="mw-cite-backlink"><b><a href="#cite_ref-10">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFHerres2020" class="citation book cs1">Herres, David (2020-10-06). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=RYoBEAAAQBAJ&dq=An+IC+that+contains+a+CPU+may+also+contain+memory&pg=PA130"><i>Oscilloscopes: A Manual for Students, Engineers, and Scientists</i></a>. Springer Nature. p. 130. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-3-030-53885-9" title="Special:BookSources/978-3-030-53885-9"><bdi>978-3-030-53885-9</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Oscilloscopes%3A+A+Manual+for+Students%2C+Engineers%2C+and+Scientists&rft.pages=130&rft.pub=Springer+Nature&rft.date=2020-10-06&rft.isbn=978-3-030-53885-9&rft.aulast=Herres&rft.aufirst=David&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3DRYoBEAAAQBAJ%26dq%3DAn%2BIC%2Bthat%2Bcontains%2Ba%2BCPU%2Bmay%2Balso%2Bcontain%2Bmemory%26pg%3DPA130&rfr_id=info%3Asid%2Fen.wikipedia.org%3ACentral+processing+unit" class="Z3988"></span></span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFRegan2008" class="citation book cs1">Regan, Gerard (2008). <a rel="nofollow" class="external text" href="https://books.google.com/books?isbn=1848000839"><i>A Brief History of Computing</i></a>. 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.navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Processor_technologies" title="Template:Processor technologies"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Processor_technologies" title="Template talk:Processor technologies"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Processor_technologies" title="Special:EditPage/Template:Processor technologies"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Processor_technologies" style="font-size:114%;margin:0 4em"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Processor technologies</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Model_of_computation" title="Model of computation">Models</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Abstract_machine" title="Abstract machine">Abstract machine</a></li> <li><a href="/wiki/Stored-program_computer" title="Stored-program computer">Stored-program computer</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">with datapath</a></li> <li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical</a></li> <li><a href="/wiki/Deterministic_finite_automaton" title="Deterministic finite automaton">Deterministic finite automaton</a></li> <li><a href="/wiki/Queue_automaton" title="Queue automaton">Queue automaton</a></li> <li><a href="/wiki/Cellular_automaton" title="Cellular automaton">Cellular automaton</a></li> <li><a href="/wiki/Quantum_cellular_automaton" title="Quantum cellular automaton">Quantum cellular automaton</a></li></ul></li> <li><a href="/wiki/Turing_machine" title="Turing machine">Turing machine</a> <ul><li><a href="/wiki/Alternating_Turing_machine" title="Alternating Turing machine">Alternating Turing machine</a></li> <li><a href="/wiki/Universal_Turing_machine" title="Universal Turing machine">Universal</a></li> <li><a href="/wiki/Post%E2%80%93Turing_machine" title="Post–Turing machine">Post–Turing</a></li> <li><a href="/wiki/Quantum_Turing_machine" title="Quantum Turing machine">Quantum</a></li> <li><a href="/wiki/Nondeterministic_Turing_machine" title="Nondeterministic Turing machine">Nondeterministic Turing machine</a></li> <li><a href="/wiki/Probabilistic_Turing_machine" title="Probabilistic Turing machine">Probabilistic Turing machine</a></li> <li><a href="/wiki/Hypercomputation" title="Hypercomputation">Hypercomputation</a></li> <li><a href="/wiki/Zeno_machine" title="Zeno machine">Zeno machine</a></li></ul></li> <li><a href="/wiki/History_of_general-purpose_CPUs#Belt_machine_architecture" title="History of general-purpose CPUs">Belt machine</a></li> <li><a href="/wiki/Stack_machine" title="Stack machine">Stack machine</a></li> <li><a href="/wiki/Register_machine" title="Register machine">Register machines</a> <ul><li><a href="/wiki/Counter_machine" title="Counter machine">Counter</a></li> <li><a href="/wiki/Pointer_machine" title="Pointer machine">Pointer</a></li> <li><a href="/wiki/Random-access_machine" title="Random-access machine">Random-access</a></li> <li><a href="/wiki/Random-access_stored-program_machine" title="Random-access stored-program machine">Random-access stored program</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_architecture" title="Computer architecture">Architecture</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></li> <li><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von Neumann</a></li> <li><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a> <ul><li><a href="/wiki/Modified_Harvard_architecture" title="Modified Harvard architecture">modified</a></li></ul></li> <li><a href="/wiki/Dataflow_architecture" title="Dataflow architecture">Dataflow</a></li> <li><a href="/wiki/Transport_triggered_architecture" title="Transport triggered architecture">Transport-triggered</a></li> <li><a href="/wiki/Cellular_architecture" title="Cellular architecture">Cellular</a></li> <li><a href="/wiki/Endianness" title="Endianness">Endianness</a></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Memory access</a> <ul><li><a href="/wiki/Non-uniform_memory_access" title="Non-uniform memory access">NUMA</a></li> <li><a href="/wiki/Uniform_memory_access" title="Uniform memory access">HUMA</a></li> <li><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></li> <li><a href="/wiki/Register%E2%80%93memory_architecture" title="Register–memory architecture">Register/memory</a></li></ul></li> <li><a href="/wiki/Cache_hierarchy" title="Cache hierarchy">Cache hierarchy</a></li> <li><a href="/wiki/Memory_hierarchy" title="Memory hierarchy">Memory hierarchy</a> <ul><li><a href="/wiki/Virtual_memory" title="Virtual memory">Virtual memory</a></li> <li><a href="/wiki/Secondary_storage" class="mw-redirect" title="Secondary storage">Secondary storage</a></li></ul></li> <li><a href="/wiki/Heterogeneous_System_Architecture" title="Heterogeneous System Architecture">Heterogeneous</a></li> <li><a href="/wiki/Fabric_computing" title="Fabric computing">Fabric</a></li> <li><a href="/wiki/Multiprocessing" title="Multiprocessing">Multiprocessing</a></li> <li><a href="/wiki/Cognitive_computing" title="Cognitive computing">Cognitive</a></li> <li><a href="/wiki/Neuromorphic_engineering" class="mw-redirect" title="Neuromorphic engineering">Neuromorphic</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set<br />architectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Types</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Orthogonal_instruction_set" title="Orthogonal instruction set">Orthogonal instruction set</a></li> <li><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></li> <li><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">Application-specific</a></li> <li><a href="/wiki/Explicit_data_graph_execution" title="Explicit data graph execution">EDGE</a> <ul><li><a href="/wiki/TRIPS_architecture" title="TRIPS architecture">TRIPS</a></li></ul></li> <li><a href="/wiki/Very_long_instruction_word" title="Very long instruction word">VLIW</a> <ul><li><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></li></ul></li> <li><a href="/wiki/Minimal_instruction_set_computer" title="Minimal instruction set computer">MISC</a></li> <li><a href="/wiki/One-instruction_set_computer" title="One-instruction set computer">OISC</a></li> <li><a href="/wiki/No_instruction_set_computing" title="No instruction set computing">NISC</a></li> <li><a href="/wiki/Zero_instruction_set_computer" class="mw-redirect" title="Zero instruction set computer">ZISC</a></li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Quantum_computing" title="Quantum computing">Quantum computing</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Comparison</a> <ul><li><a href="/wiki/Addressing_mode" title="Addressing mode">Addressing modes</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Instruction<br />sets</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">Motorola 68000 series</a></li> <li><a href="/wiki/VAX" title="VAX">VAX</a></li> <li><a href="/wiki/PDP-11_architecture" title="PDP-11 architecture">PDP-11</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li>Power <ul><li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li></ul></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper architecture</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/DEC_Alpha" title="DEC Alpha">DEC Alpha</a></li> <li><a href="/wiki/ETRAX_CRIS" title="ETRAX CRIS">ETRAX CRIS</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/IA-64" title="IA-64">Itanium</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/Little_man_computer" title="Little man computer">LMC</a></li> <li>System/3x0 <ul><li><a href="/wiki/IBM_System/360_architecture" title="IBM System/360 architecture">S/360</a></li> <li><a href="/wiki/IBM_System/370" title="IBM System/370">S/370</a></li> <li><a href="/wiki/IBM_System/390" title="IBM System/390">S/390</a></li> <li><a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a></li></ul></li> <li>Tilera ISA</li> <li><a href="/wiki/VISC_architecture" title="VISC architecture">VISC architecture</a></li> <li><a href="/wiki/Adapteva#Products" class="mw-redirect" title="Adapteva">Epiphany architecture</a></li> <li><a href="/wiki/Comparison_of_instruction_set_architectures" title="Comparison of instruction set architectures">Others</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_cycle" title="Instruction cycle">Execution</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipelining</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Pipeline_stall" title="Pipeline stall">Pipeline stall</a></li> <li><a href="/wiki/Operand_forwarding" title="Operand forwarding">Operand forwarding</a></li> <li><a href="/wiki/Classic_RISC_pipeline" title="Classic RISC pipeline">Classic RISC pipeline</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hazard_(computer_architecture)" title="Hazard (computer architecture)">Hazards</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Data_dependency" title="Data dependency">Data dependency</a></li> <li><a href="/wiki/Structural_hazard" class="mw-redirect" title="Structural hazard">Structural</a></li> <li><a href="/wiki/Control_hazard" class="mw-redirect" title="Control hazard">Control</a></li> <li><a href="/wiki/False_sharing" title="False sharing">False sharing</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Out-of-order_execution" title="Out-of-order execution">Out-of-order</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Scoreboarding" title="Scoreboarding">Scoreboarding</a></li> <li><a href="/wiki/Tomasulo%27s_algorithm" title="Tomasulo's algorithm">Tomasulo's algorithm</a> <ul><li><a href="/wiki/Reservation_station" title="Reservation station">Reservation station</a></li> <li><a href="/wiki/Re-order_buffer" title="Re-order buffer">Re-order buffer</a></li></ul></li> <li><a href="/wiki/Register_renaming" title="Register renaming">Register renaming</a></li> <li><a href="/wiki/Wide-issue" title="Wide-issue">Wide-issue</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Speculative_execution" title="Speculative execution">Speculative</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch prediction</a></li> <li><a href="/wiki/Memory_dependence_prediction" title="Memory dependence prediction">Memory dependence prediction</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Parallel_computing" title="Parallel computing">Parallelism</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Level</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bit-level_parallelism" title="Bit-level parallelism">Bit</a> <ul><li><a href="/wiki/Bit-serial_architecture" title="Bit-serial architecture">Bit-serial</a></li> <li><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word</a></li></ul></li> <li><a href="/wiki/Instruction-level_parallelism" title="Instruction-level parallelism">Instruction</a></li> <li><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Pipelining</a> <ul><li><a href="/wiki/Scalar_processor" title="Scalar processor">Scalar</a></li> <li><a href="/wiki/Superscalar_processor" title="Superscalar processor">Superscalar</a></li></ul></li> <li><a href="/wiki/Task_parallelism" title="Task parallelism">Task</a> <ul><li><a href="/wiki/Thread_(computing)" title="Thread (computing)">Thread</a></li> <li><a href="/wiki/Process_(computing)" title="Process (computing)">Process</a></li></ul></li> <li><a href="/wiki/Data_parallelism" title="Data parallelism">Data</a> <ul><li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li></ul></li> <li><a href="/wiki/Memory-level_parallelism" title="Memory-level parallelism">Memory</a></li> <li><a href="/wiki/Distributed_architecture" class="mw-redirect" title="Distributed architecture">Distributed</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Multithreading_(computer_architecture)" title="Multithreading (computer architecture)">Multithreading</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Temporal_multithreading" title="Temporal multithreading">Temporal</a></li> <li><a href="/wiki/Simultaneous_multithreading" title="Simultaneous multithreading">Simultaneous</a> <ul><li><a href="/wiki/Hyper-threading" title="Hyper-threading">Hyperthreading</a></li> <li><a href="/wiki/Simultaneous_and_heterogeneous_multithreading" title="Simultaneous and heterogeneous multithreading">Simultaneous and heterogenous</a></li></ul></li> <li><a href="/wiki/Speculative_multithreading" title="Speculative multithreading">Speculative</a></li> <li><a href="/wiki/Preemption_(computing)" title="Preemption (computing)">Preemptive</a></li> <li><a href="/wiki/Cooperative_multitasking" title="Cooperative multitasking">Cooperative</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Flynn%27s_taxonomy" title="Flynn's taxonomy">Flynn's taxonomy</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single_instruction,_single_data" title="Single instruction, single data">SISD</a></li> <li><a href="/wiki/Single_instruction,_multiple_data" title="Single instruction, multiple data">SIMD</a> <ul><li><a href="/wiki/Single_instruction,_multiple_threads" title="Single instruction, multiple threads">Array processing (SIMT)</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Pipelined_processor" title="Flynn's taxonomy">Pipelined processing</a></li> <li><a href="/wiki/Flynn%27s_taxonomy#Associative_processor" title="Flynn's taxonomy">Associative processing</a></li> <li><a href="/wiki/SWAR" title="SWAR">SWAR</a></li></ul></li> <li><a href="/wiki/Multiple_instruction,_single_data" title="Multiple instruction, single data">MISD</a></li> <li><a href="/wiki/Multiple_instruction,_multiple_data" title="Multiple instruction, multiple data">MIMD</a> <ul><li><a href="/wiki/Single_program,_multiple_data" title="Single program, multiple data">SPMD</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_performance" title="Computer performance">Processor<br />performance</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor_count" title="Transistor count">Transistor count</a></li> <li><a href="/wiki/Instructions_per_cycle" title="Instructions per cycle">Instructions per cycle</a> (IPC) <ul><li><a href="/wiki/Cycles_per_instruction" title="Cycles per instruction">Cycles per instruction</a> (CPI)</li></ul></li> <li><a href="/wiki/Instructions_per_second" title="Instructions per second">Instructions per second</a> (IPS)</li> <li><a href="/wiki/FLOPS" class="mw-redirect" title="FLOPS">Floating-point operations per second</a> (FLOPS)</li> <li><a href="/wiki/Transactions_per_second" title="Transactions per second">Transactions per second</a> (TPS)</li> <li><a href="/wiki/SUPS" title="SUPS">Synaptic updates per second</a> (SUPS)</li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li> <li><a href="/wiki/Cache_performance_measurement_and_metric" title="Cache performance measurement and metric">Cache performance metrics</a></li> <li><a href="/wiki/Computer_performance_by_orders_of_magnitude" title="Computer performance by orders of magnitude">Computer performance by orders of magnitude</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Processor_(computing)" title="Processor (computing)">Types</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">Central processing unit</a> (CPU)</li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU) <ul><li><a href="/wiki/General-purpose_computing_on_graphics_processing_units" title="General-purpose computing on graphics processing units">GPGPU</a></li></ul></li> <li><a href="/wiki/Vector_processor" title="Vector processor">Vector</a></li> <li><a href="/wiki/Barrel_processor" title="Barrel processor">Barrel</a></li> <li><a href="/wiki/Stream_processing" title="Stream processing">Stream</a></li> <li><a href="/wiki/Tile_processor" title="Tile processor">Tile processor</a></li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a></li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">FPOA</a></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Multi-chip_module" title="Multi-chip module">Multi-chip module</a> (MCM)</li> <li><a href="/wiki/System_in_a_package" title="System in a package">System in a package</a> (SiP)</li> <li><a href="/wiki/Package_on_a_package" title="Package on a package">Package on a package</a> (PoP)</li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">By application</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li> <li><a href="/wiki/Microcontroller" title="Microcontroller">Microcontroller</a></li> <li><a href="/wiki/Mobile_processor" title="Mobile processor">Mobile</a></li> <li><a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">Ultra-low-voltage</a></li> <li><a href="/wiki/Application-specific_instruction_set_processor" title="Application-specific instruction set processor">ASIP</a></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Systems<br />on chip</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/System_on_a_chip" title="System on a chip">System on a chip</a> (SoC)</li> <li><a href="/wiki/Multiprocessor_system_on_a_chip" class="mw-redirect" title="Multiprocessor system on a chip">Multiprocessor</a> (MPSoC)</li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">Cypress PSoC</a></li> <li><a href="/wiki/Network_on_a_chip" title="Network on a chip">Network on a chip</a> (NoC)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware<br />accelerators</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Coprocessor" title="Coprocessor">Coprocessor</a></li> <li><a href="/wiki/AI_accelerator" title="AI accelerator">AI accelerator</a></li> <li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">Graphics processing unit</a> (GPU)</li> <li><a href="/wiki/Image_processor" title="Image processor">Image processor</a></li> <li><a href="/wiki/Vision_processing_unit" title="Vision processing unit">Vision processing unit</a> (VPU)</li> <li><a href="/wiki/Physics_processing_unit" title="Physics processing unit">Physics processing unit</a> (PPU)</li> <li><a href="/wiki/Digital_signal_processor" title="Digital signal processor">Digital signal processor</a> (DSP)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li> <li><a href="/wiki/Secure_cryptoprocessor" title="Secure cryptoprocessor">Secure cryptoprocessor</a></li> <li><a href="/wiki/Network_processor" title="Network processor">Network processor</a></li> <li><a href="/wiki/Baseband_processor" title="Baseband processor">Baseband processor</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word size</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/1-bit_computing" title="1-bit computing">1-bit</a></li> <li><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></li> <li><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></li> <li><a href="/wiki/12-bit_computing" title="12-bit computing">12-bit</a></li> <li><a href="/wiki/Apollo_Guidance_Computer" title="Apollo Guidance Computer">15-bit</a></li> <li><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></li> <li><a href="/wiki/24-bit_computing" title="24-bit computing">24-bit</a></li> <li><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></li> <li><a href="/wiki/48-bit_computing" title="48-bit computing">48-bit</a></li> <li><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></li> <li><a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a></li> <li><a href="/wiki/256-bit_computing" title="256-bit computing">256-bit</a></li> <li><a href="/wiki/512-bit_computing" title="512-bit computing">512-bit</a></li> <li><a href="/wiki/Bit_slicing" title="Bit slicing">bit slicing</a></li> <li><a href="/wiki/Word_(computer_architecture)#Table_of_word_sizes" title="Word (computer architecture)">others</a> <ul><li><a href="/wiki/Word_(computer_architecture)#Variable-word_architectures" title="Word (computer architecture)">variable</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Core count</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-core" title="Single-core">Single-core</a></li> <li><a href="/wiki/Multi-core_processor" title="Multi-core processor">Multi-core</a></li> <li><a href="/wiki/Manycore_processor" title="Manycore processor">Manycore</a></li> <li><a href="/wiki/Heterogeneous_computing" title="Heterogeneous computing">Heterogeneous architecture</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Components</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">Core</a></li> <li><a href="/wiki/Cache_(computing)" title="Cache (computing)">Cache</a> <ul><li><a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a></li> <li><a href="/wiki/Scratchpad_memory" title="Scratchpad memory">Scratchpad memory</a></li> <li><a href="/wiki/Data_cache" class="mw-redirect" title="Data cache">Data cache</a></li> <li><a href="/wiki/Instruction_cache" class="mw-redirect" title="Instruction cache">Instruction cache</a></li> <li><a href="/wiki/Cache_replacement_policies" title="Cache replacement policies">replacement policies</a></li> <li><a href="/wiki/Cache_coherence" title="Cache coherence">coherence</a></li></ul></li> <li><a href="/wiki/Bus_(computing)" title="Bus (computing)">Bus</a></li> <li><a href="/wiki/Clock_rate" title="Clock rate">Clock rate</a></li> <li><a href="/wiki/Clock_signal" title="Clock signal">Clock signal</a></li> <li><a href="/wiki/FIFO_(computing_and_electronics)" title="FIFO (computing and electronics)">FIFO</a></li></ul> </div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Execution_unit" title="Execution unit">Functional<br />units</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">Arithmetic logic unit</a> (ALU)</li> <li><a href="/wiki/Address_generation_unit" title="Address generation unit">Address generation unit</a> (AGU)</li> <li><a href="/wiki/Floating-point_unit" title="Floating-point unit">Floating-point unit</a> (FPU)</li> <li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a> (MMU) <ul><li><a href="/wiki/Load%E2%80%93store_unit" title="Load–store unit">Load–store unit</a></li> <li><a href="/wiki/Translation_lookaside_buffer" title="Translation lookaside buffer">Translation lookaside buffer</a> (TLB)</li></ul></li> <li><a href="/wiki/Branch_predictor" title="Branch predictor">Branch predictor</a></li> <li><a href="/wiki/Branch_target_predictor" title="Branch target predictor">Branch target predictor</a></li> <li><a href="/wiki/Memory_controller" title="Memory controller">Integrated memory controller</a> (IMC) <ul><li><a href="/wiki/Memory_management_unit" title="Memory management unit">Memory management unit</a></li></ul></li> <li><a href="/wiki/Instruction_decoder" class="mw-redirect" title="Instruction decoder">Instruction decoder</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Logic_gate" title="Logic gate">Logic</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential</a></li> <li><a href="/wiki/Glue_logic" title="Glue logic">Glue</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a> <ul><li><a href="/wiki/Quantum_logic_gate" title="Quantum logic gate">Quantum</a></li> <li><a href="/wiki/Gate_array" title="Gate array">Array</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_register" title="Hardware register">Registers</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Processor_register" title="Processor register">Processor register</a></li> <li><a href="/wiki/Status_register" title="Status register">Status register</a></li> <li><a href="/wiki/Stack_register" title="Stack register">Stack register</a></li> <li><a href="/wiki/Register_file" title="Register file">Register file</a></li> <li><a href="/wiki/Memory_buffer_register" title="Memory buffer register">Memory buffer</a></li> <li><a href="/wiki/Memory_address_register" title="Memory address register">Memory address register</a></li> <li><a href="/wiki/Program_counter" title="Program counter">Program counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Control_unit" title="Control unit">Control unit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Hardwired_control_unit" class="mw-redirect" title="Hardwired control unit">Hardwired control unit</a></li> <li><a href="/wiki/Instruction_unit" title="Instruction unit">Instruction unit</a></li> <li><a href="/wiki/Data_buffer" title="Data buffer">Data buffer</a></li> <li><a href="/wiki/Write_buffer" title="Write buffer">Write buffer</a></li> <li><a href="/wiki/Microcode" title="Microcode">Microcode</a> <a href="/wiki/ROM_image" title="ROM image">ROM</a></li> <li><a href="/wiki/Counter_(digital)" title="Counter (digital)">Counter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Datapath" title="Datapath">Datapath</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Multiplexer" title="Multiplexer">Multiplexer</a></li> <li><a href="/wiki/Demultiplexer" class="mw-redirect" title="Demultiplexer">Demultiplexer</a></li> <li><a href="/wiki/Adder_(electronics)" title="Adder (electronics)">Adder</a></li> <li><a href="/wiki/Binary_multiplier" title="Binary multiplier">Multiplier</a> <ul><li><a href="/wiki/CPU_multiplier" title="CPU multiplier">CPU</a></li></ul></li> <li><a href="/wiki/Binary_decoder" title="Binary decoder">Binary decoder</a> <ul><li><a href="/wiki/Address_decoder" title="Address decoder">Address decoder</a></li> <li><a href="/wiki/Sum-addressed_decoder" title="Sum-addressed decoder">Sum-addressed decoder</a></li></ul></li> <li><a href="/wiki/Barrel_shifter" title="Barrel shifter">Barrel shifter</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Electronic_circuit" title="Electronic circuit">Circuitry</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> <ul><li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">3D</a></li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal</a></li> <li><a href="/wiki/Power_management_integrated_circuit" title="Power management integrated circuit">Power management</a></li></ul></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean</a></li> <li><a href="/wiki/Circuit_(computer_science)" title="Circuit (computer science)">Digital</a></li> <li><a href="/wiki/Analogue_electronics" title="Analogue electronics">Analog</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum</a></li> <li><a href="/wiki/Switch#Electronic_switches" title="Switch">Switch</a></li></ul> </div></td></tr></tbody></table><div> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Power_management" title="Power management">Power<br />management</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Power_Management_Unit" title="Power Management Unit">PMU</a></li> <li><a href="/wiki/Advanced_Power_Management" title="Advanced Power Management">APM</a></li> <li><a href="/wiki/ACPI" title="ACPI">ACPI</a></li> <li><a href="/wiki/Dynamic_frequency_scaling" title="Dynamic frequency scaling">Dynamic frequency scaling</a></li> <li><a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">Dynamic voltage scaling</a></li> <li><a href="/wiki/Clock_gating" title="Clock gating">Clock gating</a></li> <li><a href="/wiki/Performance_per_watt" title="Performance per watt">Performance per watt</a> (PPW)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_general-purpose_CPUs" title="History of general-purpose CPUs">History of general-purpose CPUs</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li> <li><a href="/wiki/Processor_design" title="Processor design">Processor design</a></li> <li><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></li> <li><a href="/wiki/Hardware_security_module" title="Hardware security module">Hardware security module</a></li> <li><a href="/wiki/Semiconductor_device_fabrication" title="Semiconductor device fabrication">Semiconductor device fabrication</a></li> <li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Pin_grid_array" title="Pin grid array">Pin grid array</a></li> <li><a href="/wiki/Chip_carrier" title="Chip carrier">Chip carrier</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Basic_computer_components" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Basic_computer_components" title="Template:Basic computer components"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Basic_computer_components" title="Template talk:Basic computer components"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Basic_computer_components" title="Special:EditPage/Template:Basic computer components"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Basic_computer_components" style="font-size:114%;margin:0 4em">Basic <a href="/wiki/Computer" title="Computer">computer</a> <a href="/wiki/Computer_hardware" title="Computer hardware">components</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Input_device" title="Input device">Input devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Pointing_device" title="Pointing device">Pointing devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Graphics_tablet" title="Graphics tablet">Graphics tablet</a></li> <li><a href="/wiki/Game_controller" title="Game controller">Game controller</a></li> <li><a href="/wiki/Light_pen" title="Light pen">Light pen</a></li> <li><a href="/wiki/Computer_mouse" title="Computer mouse">Mouse</a> <ul><li><a href="/wiki/Optical_mouse" title="Optical mouse">Optical</a></li></ul></li> <li><a href="/wiki/Optical_trackpad" title="Optical trackpad">Optical trackpad</a></li> <li><a href="/wiki/Pointing_stick" title="Pointing stick">Pointing stick</a></li> <li><a href="/wiki/Touchpad" title="Touchpad">Touchpad</a></li> <li><a href="/wiki/Touchscreen" title="Touchscreen">Touchscreen</a></li> <li><a href="/wiki/Trackball" title="Trackball">Trackball</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_keyboard" title="Computer keyboard">Keyboard</a></li> <li><a href="/wiki/Image_scanner" title="Image scanner">Image scanner</a></li> <li><a href="/wiki/Graphics_card" title="Graphics card">Graphics card</a> <ul><li><a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">GPU</a></li></ul></li> <li><a href="/wiki/Microphone" title="Microphone">Microphone</a></li> <li><a href="/wiki/Refreshable_braille_display" title="Refreshable braille display">Refreshable braille display</a></li> <li><a href="/wiki/Sound_card" title="Sound card">Sound card</a> <ul><li><a href="/wiki/Sound_chip" title="Sound chip">Sound chip</a></li></ul></li> <li><a href="/wiki/Webcam" title="Webcam">Webcam</a> <ul><li><a href="/wiki/Softcam" title="Softcam">Softcam</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Output_device" title="Output device">Output devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_monitor" title="Computer monitor">Monitor</a> <ul><li><a href="/wiki/Electronic_visual_display" title="Electronic visual display">Screen</a></li></ul></li> <li><a href="/wiki/Refreshable_braille_display" title="Refreshable braille display">Refreshable braille display</a></li> <li><a href="/wiki/Printer_(computing)" title="Printer (computing)">Printer</a> <ul><li><a href="/wiki/Plotter" title="Plotter">Plotter</a></li></ul></li> <li><a href="/wiki/Computer_speakers" title="Computer speakers">Speakers</a></li> <li><a href="/wiki/Sound_card" title="Sound card">Sound card</a></li> <li><a href="/wiki/Graphics_card" title="Graphics card">Graphics card</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Removable_media" title="Removable media">Removable <br /> data storage</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Disk_pack" title="Disk pack">Disk pack</a></li> <li><a href="/wiki/Floppy_disk" title="Floppy disk">Floppy disk</a></li> <li><a href="/wiki/Optical_disc" title="Optical disc">Optical disc</a> <ul><li><a href="/wiki/Compact_disc" title="Compact disc">CD</a></li> <li><a href="/wiki/DVD" title="DVD">DVD</a></li> <li><a href="/wiki/Blu-ray" title="Blu-ray">Blu-ray</a></li></ul></li> <li><a href="/wiki/Flash_memory" title="Flash memory">Flash memory</a> <ul><li><a href="/wiki/Memory_card" title="Memory card">Memory card</a></li> <li><a href="/wiki/USB_flash_drive" title="USB flash drive">USB flash drive</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_case" title="Computer case">Computer case</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a class="mw-selflink selflink">Central processing unit</a> <ul><li><a href="/wiki/Microprocessor" title="Microprocessor">Microprocessor</a></li></ul></li> <li><a href="/wiki/Motherboard" title="Motherboard">Motherboard</a></li> <li><a href="/wiki/Computer_memory" title="Computer memory">Memory</a> <ul><li><a href="/wiki/Random-access_memory" title="Random-access memory">RAM</a></li> <li><a href="/wiki/Nonvolatile_BIOS_memory" title="Nonvolatile BIOS memory">BIOS</a></li></ul></li> <li><a href="/wiki/Computer_data_storage" title="Computer data storage">Data storage</a> <ul><li><a href="/wiki/Hard_disk_drive" title="Hard disk drive">HDD</a></li> <li><a href="/wiki/Solid-state_drive" title="Solid-state drive">SSD</a> (<a href="/wiki/SATA" title="SATA">SATA</a> / <a href="/wiki/NVM_Express" title="NVM Express">NVMe</a>)</li> <li><a href="/wiki/Solid-state_hybrid_drive" class="mw-redirect" title="Solid-state hybrid drive">SSHD</a></li></ul></li> <li><a href="/wiki/Power_supply_unit_(computer)" title="Power supply unit (computer)">Power supply</a> <ul><li><a href="/wiki/Switched-mode_power_supply" title="Switched-mode power supply">SMPS</a></li></ul></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOSFET</a> <ul><li><a href="/wiki/Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li> <li><a href="/wiki/Voltage_regulator_module" title="Voltage regulator module">VRM</a></li></ul></li> <li><a href="/wiki/Network_interface_controller" title="Network interface controller">Network interface controller</a></li> <li><a href="/wiki/Fax_modem" title="Fax modem">Fax modem</a></li> <li><a href="/wiki/Expansion_card" title="Expansion card">Expansion card</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Computer_port_(hardware)" title="Computer port (hardware)">Ports</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Current</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Ethernet" title="Ethernet">Ethernet</a></li> <li><a href="/wiki/USB" title="USB">USB</a></li> <li><a href="/wiki/Thunderbolt_(interface)" title="Thunderbolt (interface)">Thunderbolt</a></li> <li><a href="/wiki/Phone_connector_(audio)" title="Phone connector (audio)">Analog audio jack</a></li> <li><a href="/wiki/DisplayPort" title="DisplayPort">DisplayPort</a></li> <li><a href="/wiki/HDMI" title="HDMI">HDMI</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Obsolete</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IEEE_1394" title="IEEE 1394">FireWire</a> (IEEE 1394)</li> <li><a href="/wiki/Parallel_port" title="Parallel port">Parallel port</a></li> <li><a href="/wiki/Serial_port" title="Serial port">Serial port</a></li> <li><a href="/wiki/Game_port" title="Game port">Game port</a></li> <li><a href="/wiki/PS/2_port" title="PS/2 port">PS/2 port</a></li> <li><a href="/wiki/Serial_ATA#eSATA" class="mw-redirect" title="Serial ATA">eSATA</a></li> <li><a href="/wiki/Digital_Visual_Interface" title="Digital Visual Interface">DVI</a></li> <li><a href="/wiki/VGA_connector" title="VGA connector">VGA</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/History_of_computing_hardware" title="History of computing hardware">History of computing hardware</a></li> <li><a href="/wiki/History_of_computing_hardware_(1960s%E2%80%93present)" title="History of computing hardware (1960s–present)">History of computing hardware (1960s–present)</a></li> <li><a href="/wiki/List_of_pioneers_in_computer_science" title="List of pioneers in computer science">List of pioneers in computer science</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Digital_electronics" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Digital_electronics" title="Template:Digital electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Digital_electronics" title="Template talk:Digital electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Digital_electronics" title="Special:EditPage/Template:Digital electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Digital_electronics" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a href="/wiki/Register-transfer_level" title="Register-transfer level">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital audio</a> <ul><li><a href="/wiki/Digital_radio" title="Digital radio">radio</a></li></ul></li> <li><a href="/wiki/Digital_photography" title="Digital photography">Digital photography</a></li> <li><a href="/wiki/Telephony#Digital_telephony" title="Telephony">Digital telephone</a></li> <li><a href="/wiki/Digital_video" title="Digital video">Digital video</a> <ul><li><a href="/wiki/Digital_cinematography" title="Digital cinematography">cinematography</a></li> <li><a href="/wiki/Digital_television" title="Digital television">television</a></li></ul></li> <li><a href="/wiki/Electronic_literature" title="Electronic literature">Electronic literature</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Design issues</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Metastability_(electronics)" title="Metastability (electronics)">Metastability</a></li> <li><a href="/wiki/Runt_pulse" title="Runt pulse">Runt pulse</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Electronic_components" style="padding:3px"><table class="nowraplinks mw-collapsible mw-collapsed navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Electronic_components" title="Template:Electronic components"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Electronic_components" title="Template talk:Electronic components"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Electronic_components" title="Special:EditPage/Template:Electronic components"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Electronic_components" style="font-size:114%;margin:0 4em"><a href="/wiki/Electronic_component" title="Electronic component">Electronic components</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Semiconductor_device" title="Semiconductor device">Semiconductor<br />devices</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/MOSFET" title="MOSFET">MOS <br />transistors</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/NMOS_logic" title="NMOS logic">NMOS</a></li> <li><a href="/wiki/PMOS_logic" title="PMOS logic">PMOS</a></li> <li><a href="/wiki/BiCMOS" title="BiCMOS">BiCMOS</a></li> <li><a href="/wiki/Bio-FET" title="Bio-FET">BioFET</a></li> <li><a href="/wiki/Chemical_field-effect_transistor" title="Chemical field-effect transistor">Chemical field-effect transistor</a> (ChemFET)</li> <li><a href="/wiki/CMOS" title="CMOS">Complementary MOS</a> (CMOS)</li> <li><a href="/wiki/Depletion-load_NMOS_logic" title="Depletion-load NMOS logic">Depletion-load NMOS</a></li> <li><a href="/wiki/FinFET" class="mw-redirect" title="FinFET">Fin field-effect transistor</a> (FinFET)</li> <li><a href="/wiki/Floating-gate_MOSFET" title="Floating-gate MOSFET">Floating-gate MOSFET</a> (FGMOS)</li> <li><a href="/wiki/Insulated-gate_bipolar_transistor" title="Insulated-gate bipolar transistor">Insulated-gate bipolar transistor</a> (IGBT)</li> <li><a href="/wiki/ISFET" title="ISFET">ISFET</a></li> <li><a href="/wiki/LDMOS" title="LDMOS">LDMOS</a></li> <li><a href="/wiki/MOSFET" title="MOSFET">MOS field-effect transistor</a> (MOSFET)</li> <li><a href="/wiki/Multigate_device" title="Multigate device">Multi-gate field-effect transistor</a> (MuGFET)</li> <li><a href="/wiki/Power_MOSFET" title="Power MOSFET">Power MOSFET</a></li> <li><a href="/wiki/Thin-film_transistor" title="Thin-film transistor">Thin-film transistor</a> (TFT)</li> <li><a href="/wiki/VMOS" title="VMOS">VMOS</a></li> <li><a href="/wiki/Power_MOSFET#UMOS" title="Power MOSFET">UMOS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Transistor" title="Transistor">Other <br />transistors</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bipolar_junction_transistor" title="Bipolar junction transistor">Bipolar junction transistor</a> (BJT)</li> <li><a href="/wiki/Darlington_transistor" title="Darlington transistor">Darlington transistor</a></li> <li><a href="/wiki/Diffused_junction_transistor" title="Diffused junction transistor">Diffused junction transistor</a></li> <li><a href="/wiki/Field-effect_transistor" title="Field-effect transistor">Field-effect transistor</a> (FET) <ul><li><a href="/wiki/JFET" title="JFET">Junction Gate FET (JFET)</a></li> <li><a href="/wiki/Organic_field-effect_transistor" title="Organic field-effect transistor">Organic FET (OFET)</a></li></ul></li> <li><a href="/wiki/Light-emitting_transistor" title="Light-emitting transistor">Light-emitting transistor</a> (LET) <ul><li><a href="/wiki/Organic_light-emitting_transistor" title="Organic light-emitting transistor">Organic LET (OLET)</a></li></ul></li> <li><a href="/wiki/Pentode_transistor" title="Pentode transistor">Pentode transistor</a></li> <li><a href="/wiki/Point-contact_transistor" title="Point-contact transistor">Point-contact transistor</a></li> <li><a href="/wiki/Programmable_unijunction_transistor" title="Programmable unijunction transistor">Programmable unijunction transistor</a> (PUT)</li> <li><a href="/wiki/Static_induction_transistor" title="Static induction transistor">Static induction transistor</a> (SIT)</li> <li><a href="/wiki/Tetrode_transistor" title="Tetrode transistor">Tetrode transistor</a></li> <li><a href="/wiki/Unijunction_transistor" title="Unijunction transistor">Unijunction transistor</a> (UJT)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Diode" title="Diode">Diodes</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Avalanche_diode" title="Avalanche diode">Avalanche diode</a></li> <li><a href="/wiki/Constant-current_diode" title="Constant-current diode">Constant-current diode</a> (CLD, CRD)</li> <li><a href="/wiki/Gunn_diode" title="Gunn diode">Gunn diode</a></li> <li><a href="/wiki/Laser_diode" title="Laser diode">Laser diode</a> (LD)</li> <li><a href="/wiki/Light-emitting_diode" title="Light-emitting diode">Light-emitting diode</a> (LED)</li> <li><a href="/wiki/OLED" title="OLED">Organic light-emitting diode</a> (OLED)</li> <li><a href="/wiki/Photodiode" title="Photodiode">Photodiode</a></li> <li><a href="/wiki/PIN_diode" title="PIN diode">PIN diode</a></li> <li><a href="/wiki/Schottky_diode" title="Schottky diode">Schottky diode</a></li> <li><a href="/wiki/Step_recovery_diode" title="Step recovery diode">Step recovery diode</a></li> <li><a href="/wiki/Zener_diode" title="Zener diode">Zener diode</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other <br />devices</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/DIAC" title="DIAC">DIAC</a></li> <li><a href="/wiki/Heterostructure_barrier_varactor" title="Heterostructure barrier varactor">Heterostructure barrier varactor</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a></li> <li><a href="/wiki/Light_emitting_capacitor" class="mw-redirect" title="Light emitting capacitor">Light emitting capacitor</a> (LEC)</li> <li><a href="/wiki/Memistor" title="Memistor">Memistor</a></li> <li><a href="/wiki/Memristor" title="Memristor">Memristor</a></li> <li><a href="/wiki/Memtransistor" title="Memtransistor">Memtransistor</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Metal-oxide_varistor" class="mw-redirect" title="Metal-oxide varistor">Metal-oxide varistor</a> (MOV)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/MOS_integrated_circuit" class="mw-redirect" title="MOS integrated circuit">MOS integrated circuit</a> (MOS IC)</li> <li><a href="/wiki/Organic_semiconductor" title="Organic semiconductor">Organic semiconductor</a></li> <li><a href="/wiki/Photodetector" title="Photodetector">Photodetector</a></li> <li><a href="/wiki/Quantum_circuit" title="Quantum circuit">Quantum circuit</a></li> <li><a href="/wiki/RF_CMOS" title="RF CMOS">RF CMOS</a></li> <li><a href="/wiki/Silicon_controlled_rectifier" title="Silicon controlled rectifier">Silicon controlled rectifier</a> (SCR)</li> <li><a href="/wiki/Solaristor" title="Solaristor">Solaristor</a></li> <li><a href="/wiki/Static_induction_thyristor" title="Static induction thyristor">Static induction thyristor</a> (SITh)</li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Thyristor" title="Thyristor">Thyristor</a></li> <li><a href="/wiki/Trancitor" title="Trancitor">Trancitor</a></li> <li><a href="/wiki/TRIAC" title="TRIAC">TRIAC</a></li> <li><a href="/wiki/Varicap" title="Varicap">Varicap</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Voltage_regulator" title="Voltage regulator">Voltage regulators</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Linear_regulator" title="Linear regulator">Linear regulator</a></li> <li><a href="/wiki/Low-dropout_regulator" title="Low-dropout regulator">Low-dropout regulator</a></li> <li><a href="/wiki/Switching_regulator" class="mw-redirect" title="Switching regulator">Switching regulator</a></li> <li><a href="/wiki/Buck_converter" title="Buck converter">Buck</a></li> <li><a href="/wiki/Boost_converter" title="Boost converter">Boost</a></li> <li><a href="/wiki/Buck%E2%80%93boost_converter" title="Buck–boost converter">Buck–boost</a></li> <li><a href="/wiki/Split-pi_topology" title="Split-pi topology">Split-pi</a></li> <li><a href="/wiki/%C4%86uk_converter" title="Ćuk converter">Ćuk</a></li> <li><a href="/wiki/Single-ended_primary-inductor_converter" title="Single-ended primary-inductor converter">SEPIC</a></li> <li><a href="/wiki/Charge_pump" title="Charge pump">Charge pump</a></li> <li><a href="/wiki/Switched_capacitor" title="Switched capacitor">Switched capacitor</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Vacuum_tube" title="Vacuum tube">Vacuum tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Acorn_tube" title="Acorn tube">Acorn tube</a></li> <li><a href="/wiki/Audion" title="Audion">Audion</a></li> <li><a href="/wiki/Beam_tetrode" title="Beam tetrode">Beam tetrode</a></li> <li><a href="/wiki/Hot-wire_barretter" title="Hot-wire barretter">Barretter</a></li> <li><a href="/wiki/Compactron" title="Compactron">Compactron</a></li> <li><a href="/wiki/Vacuum_diode" class="mw-redirect" title="Vacuum diode">Diode</a></li> <li><a href="/wiki/Fleming_valve" title="Fleming valve">Fleming valve</a></li> <li><a href="/wiki/Neutron_generator" title="Neutron generator">Neutron tube</a></li> <li><a href="/wiki/Nonode" title="Nonode">Nonode</a></li> <li><a href="/wiki/Nuvistor" title="Nuvistor">Nuvistor</a></li> <li><a href="/wiki/Pentagrid_converter" title="Pentagrid converter">Pentagrid</a> (Hexode, Heptode, Octode)</li> <li><a href="/wiki/Pentode" title="Pentode">Pentode</a></li> <li><a href="/wiki/Photomultiplier_tube" title="Photomultiplier tube">Photomultiplier</a></li> <li><a href="/wiki/Phototube" title="Phototube">Phototube</a></li> <li><a href="/wiki/Tetrode" title="Tetrode">Tetrode</a></li> <li><a href="/wiki/Triode" title="Triode">Triode</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Vacuum_tube" title="Vacuum tube">Vacuum tubes</a> (<a href="/wiki/Electromagnetic_radiation" title="Electromagnetic radiation">RF</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Backward-wave_oscillator" title="Backward-wave oscillator">Backward-wave oscillator</a> (BWO)</li> <li><a href="/wiki/Cavity_magnetron" title="Cavity magnetron">Cavity magnetron</a></li> <li><a href="/wiki/Crossed-field_amplifier" title="Crossed-field amplifier">Crossed-field amplifier</a> (CFA)</li> <li><a href="/wiki/Gyrotron" title="Gyrotron">Gyrotron</a></li> <li><a href="/wiki/Inductive_output_tube" title="Inductive output tube">Inductive output tube</a> (IOT)</li> <li><a href="/wiki/Klystron" title="Klystron">Klystron</a></li> <li><a href="/wiki/Maser" title="Maser">Maser</a></li> <li><a href="/wiki/Sutton_tube" title="Sutton tube">Sutton tube</a></li> <li><a href="/wiki/Traveling-wave_tube" title="Traveling-wave tube">Traveling-wave tube</a> (TWT)</li> <li><a href="/wiki/X-ray_tube" title="X-ray tube">X-ray tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Cathode-ray_tube" title="Cathode-ray tube">Cathode-ray tubes</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Beam_deflection_tube" title="Beam deflection tube">Beam deflection tube</a></li> <li><a href="/wiki/Charactron" title="Charactron">Charactron</a></li> <li><a href="/wiki/Iconoscope" title="Iconoscope">Iconoscope</a></li> <li><a href="/wiki/Magic_eye_tube" title="Magic eye tube">Magic eye tube</a></li> <li><a href="/wiki/Monoscope" title="Monoscope">Monoscope</a></li> <li><a href="/wiki/Selectron_tube" title="Selectron tube">Selectron tube</a></li> <li><a href="/wiki/Storage_tube" title="Storage tube">Storage tube</a></li> <li><a href="/wiki/Trochotron" class="mw-redirect" title="Trochotron">Trochotron</a></li> <li><a href="/wiki/Video_camera_tube" title="Video camera tube">Video camera tube</a></li> <li><a href="/wiki/Williams_tube" title="Williams tube">Williams tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Gas-filled_tube" title="Gas-filled tube">Gas-filled tubes</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Cold_cathode" title="Cold cathode">Cold cathode</a></li> <li><a href="/wiki/Crossatron" title="Crossatron">Crossatron</a></li> <li><a href="/wiki/Dekatron" title="Dekatron">Dekatron</a></li> <li><a href="/wiki/Ignitron" title="Ignitron">Ignitron</a></li> <li><a href="/wiki/Krytron" title="Krytron">Krytron</a></li> <li><a href="/wiki/Mercury-arc_valve" title="Mercury-arc valve">Mercury-arc valve</a></li> <li><a href="/wiki/Neon_lamp" title="Neon lamp">Neon lamp</a></li> <li><a href="/wiki/Nixie_tube" title="Nixie tube">Nixie tube</a></li> <li><a href="/wiki/Thyratron" title="Thyratron">Thyratron</a></li> <li><a href="/wiki/Trigatron" title="Trigatron">Trigatron</a></li> <li><a href="/wiki/Voltage-regulator_tube" title="Voltage-regulator tube">Voltage-regulator tube</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Adjustable</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Potentiometer" title="Potentiometer">Potentiometer</a> <ul><li><a href="/wiki/Digital_potentiometer" title="Digital potentiometer">digital</a></li></ul></li> <li><a href="/wiki/Variable_capacitor" title="Variable capacitor">Variable capacitor</a></li> <li><a href="/wiki/Varicap" title="Varicap">Varicap</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Passive</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Connector <ul><li><a href="/wiki/Audio_and_video_interfaces_and_connectors" title="Audio and video interfaces and connectors">audio and video</a></li> <li><a href="/wiki/AC_power_plugs_and_sockets" title="AC power plugs and sockets">electrical power</a></li> <li><a href="/wiki/RF_connector" title="RF connector">RF</a></li></ul></li> <li><a href="/wiki/Electrolytic_detector" title="Electrolytic detector">Electrolytic detector</a></li> <li><a href="/wiki/Ferrite_core" title="Ferrite core">Ferrite</a></li> <li><a href="/wiki/Antifuse" title="Antifuse">Antifuse</a></li> <li><a href="/wiki/Fuse_(electrical)" title="Fuse (electrical)">Fuse</a> <ul><li><a href="/wiki/Resettable_fuse" title="Resettable fuse">resettable</a></li> <li><a href="/wiki/EFUSE" class="mw-redirect" title="EFUSE">eFUSE</a></li></ul></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Switch" title="Switch">Switch</a></li> <li><a href="/wiki/Thermistor" title="Thermistor">Thermistor</a></li> <li><a href="/wiki/Transformer" title="Transformer">Transformer</a></li> <li><a href="/wiki/Varistor" title="Varistor">Varistor</a></li> <li><a href="/wiki/Wire" title="Wire">Wire</a> <ul><li><a href="/wiki/Wollaston_wire" title="Wollaston wire">Wollaston wire</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electrical_reactance" title="Electrical reactance">Reactive</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a> <ul><li><a href="/wiki/Capacitor_types" title="Capacitor types">types</a></li></ul></li> <li><a href="/wiki/Ceramic_resonator" title="Ceramic resonator">Ceramic resonator</a></li> <li><a href="/wiki/Crystal_oscillator" title="Crystal oscillator">Crystal oscillator</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Parametron" title="Parametron">Parametron</a></li> <li><a href="/wiki/Relay" title="Relay">Relay</a> <ul><li><a href="/wiki/Reed_relay" title="Reed relay">reed relay</a></li> <li><a href="/wiki/Mercury_relay" title="Mercury relay">mercury relay</a></li></ul></li></ul> </div></td></tr></tbody></table></div>    </div><noscript><img src="https://login.wikimedia.org/wiki/Special:CentralAutoLogin/start?type=1x1" alt="" width="1" height="1" style="border: none; position: absolute;"></noscript> <div class="printfooter" data-nosnippet="">Retrieved from "<a dir="ltr" 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