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class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#License"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.1</span> <span>License</span> </div> </a> <ul id="toc-License-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Silicon_customization" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Silicon_customization"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.2</span> <span>Silicon customization</span> </div> </a> <ul id="toc-Silicon_customization-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Instruction_sets" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Instruction_sets"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.3</span> <span>Instruction sets</span> </div> </a> <ul id="toc-Instruction_sets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Deprecations" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Deprecations"> <div class="vector-toc-text"> <span class="vector-toc-numb">1.4</span> <span>Deprecations</span> </div> </a> <ul id="toc-Deprecations-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M0" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M0"> <div class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>Cortex-M0</span> </div> </a> <button aria-controls="toc-Cortex-M0-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M0 subsection</span> </button> <ul id="toc-Cortex-M0-sublist" class="vector-toc-list"> <li id="toc-Chips" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M0+" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M0+"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Cortex-M0+</span> </div> </a> <button aria-controls="toc-Cortex-M0+-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M0+ subsection</span> </button> <ul id="toc-Cortex-M0+-sublist" class="vector-toc-list"> <li id="toc-Chips_2" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_2"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_2-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M1" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M1"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Cortex-M1</span> </div> </a> <button aria-controls="toc-Cortex-M1-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M1 subsection</span> </button> <ul id="toc-Cortex-M1-sublist" class="vector-toc-list"> <li id="toc-Chips_3" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_3"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_3-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M3" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M3"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Cortex-M3</span> </div> </a> <button aria-controls="toc-Cortex-M3-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M3 subsection</span> </button> <ul id="toc-Cortex-M3-sublist" class="vector-toc-list"> <li id="toc-Chips_4" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_4"> <div class="vector-toc-text"> <span class="vector-toc-numb">5.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_4-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M4" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M4"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Cortex-M4</span> </div> </a> <button aria-controls="toc-Cortex-M4-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M4 subsection</span> </button> <ul id="toc-Cortex-M4-sublist" class="vector-toc-list"> <li id="toc-Chips_5" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_5"> <div class="vector-toc-text"> <span class="vector-toc-numb">6.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_5-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M7" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M7"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>Cortex-M7</span> </div> </a> <button aria-controls="toc-Cortex-M7-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M7 subsection</span> </button> <ul id="toc-Cortex-M7-sublist" class="vector-toc-list"> <li id="toc-Chips_6" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_6"> <div class="vector-toc-text"> <span class="vector-toc-numb">7.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_6-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M23" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M23"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Cortex-M23</span> </div> </a> <button aria-controls="toc-Cortex-M23-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M23 subsection</span> </button> <ul id="toc-Cortex-M23-sublist" class="vector-toc-list"> <li id="toc-Chips_7" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_7"> <div class="vector-toc-text"> <span class="vector-toc-numb">8.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_7-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M33" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M33"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Cortex-M33</span> </div> </a> <button aria-controls="toc-Cortex-M33-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M33 subsection</span> </button> <ul id="toc-Cortex-M33-sublist" class="vector-toc-list"> <li id="toc-Chips_8" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_8"> <div class="vector-toc-text"> <span class="vector-toc-numb">9.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_8-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M35P" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M35P"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>Cortex-M35P</span> </div> </a> <button aria-controls="toc-Cortex-M35P-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M35P subsection</span> </button> <ul id="toc-Cortex-M35P-sublist" class="vector-toc-list"> <li id="toc-Chips_9" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_9"> <div class="vector-toc-text"> <span class="vector-toc-numb">10.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_9-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M52" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M52"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>Cortex-M52</span> </div> </a> <button aria-controls="toc-Cortex-M52-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M52 subsection</span> </button> <ul id="toc-Cortex-M52-sublist" class="vector-toc-list"> <li id="toc-Chips_10" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_10"> <div class="vector-toc-text"> <span class="vector-toc-numb">11.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_10-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M55" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M55"> <div class="vector-toc-text"> <span class="vector-toc-numb">12</span> <span>Cortex-M55</span> </div> </a> <button aria-controls="toc-Cortex-M55-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M55 subsection</span> </button> <ul id="toc-Cortex-M55-sublist" class="vector-toc-list"> <li id="toc-Chips_11" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_11"> <div class="vector-toc-text"> <span class="vector-toc-numb">12.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_11-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Cortex-M85" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Cortex-M85"> <div class="vector-toc-text"> <span class="vector-toc-numb">13</span> <span>Cortex-M85</span> </div> </a> <button aria-controls="toc-Cortex-M85-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Cortex-M85 subsection</span> </button> <ul id="toc-Cortex-M85-sublist" class="vector-toc-list"> <li id="toc-Chips_12" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Chips_12"> <div class="vector-toc-text"> <span class="vector-toc-numb">13.1</span> <span>Chips</span> </div> </a> <ul id="toc-Chips_12-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Development_tools" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Development_tools"> <div class="vector-toc-text"> <span class="vector-toc-numb">14</span> <span>Development tools</span> </div> </a> <ul id="toc-Development_tools-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Documentation" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Documentation"> <div class="vector-toc-text"> <span class="vector-toc-numb">15</span> <span>Documentation</span> </div> </a> <ul id="toc-Documentation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">16</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">17</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">18</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">19</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" 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RISC processor cores</div> <style data-mw-deduplicate="TemplateStyles:r1236090951">.mw-parser-output .hatnote{font-style:italic}.mw-parser-output div.hatnote{padding-left:1.6em;margin-bottom:0.5em}.mw-parser-output .hatnote i{font-style:normal}.mw-parser-output .hatnote+link+.hatnote{margin-top:-0.5em}@media print{body.ns-0 .mw-parser-output .hatnote{display:none!important}}</style><div role="note" class="hatnote navigation-not-searchable">"Bit-banding" redirects here. For the direct port bit software access method, see <a href="/wiki/Bit-banging" class="mw-redirect" title="Bit-banging">Bit-banging</a>. For the construction of processors from <i>n</i>-bit-wide modules, see <a href="/wiki/Bit-slicing" class="mw-redirect" title="Bit-slicing">Bit-slicing</a>.</div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg/360px-ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg" decoding="async" width="360" height="122" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3d/ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg/540px-ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3d/ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg/720px-ARM_Cortex-M0_and_M3_ICs_in_SMD_Packages.jpg 2x" data-file-width="1480" data-file-height="500" /></a><figcaption>ARM Cortex-M0 and Cortex-M3 microcontroller ICs from <a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> and Silicon Labs (<a href="/wiki/Energy_Micro" title="Energy Micro">Energy Micro</a>)</figcaption></figure> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:STM32F100C4T6B-HD.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/6/67/STM32F100C4T6B-HD.jpg/220px-STM32F100C4T6B-HD.jpg" decoding="async" width="220" height="241" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/6/67/STM32F100C4T6B-HD.jpg/330px-STM32F100C4T6B-HD.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/6/67/STM32F100C4T6B-HD.jpg/440px-STM32F100C4T6B-HD.jpg 2x" data-file-width="3498" data-file-height="3828" /></a><figcaption><a href="/wiki/Die_(integrated_circuit)" title="Die (integrated circuit)">Die</a> from a STM32F100C4T6B IC.<br />24 <a href="/wiki/Hertz" title="Hertz">MHz</a> ARM Cortex-M3 <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a> with 16 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a>, 4 KB RAM. Manufactured by <a href="/wiki/STMicroelectronics" title="STMicroelectronics">STMicroelectronics</a>.</figcaption></figure> <p>The <b>ARM Cortex-M</b> is a group of <a href="/wiki/32-bit" class="mw-redirect" title="32-bit">32-bit</a> <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a> <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> processor cores licensed by <a href="/wiki/Arm_(company)" class="mw-redirect" title="Arm (company)">ARM Limited</a>. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> Though they are most often the main component of <a href="/wiki/Microcontroller" title="Microcontroller">microcontroller</a> chips, sometimes they are embedded inside other types of chips too. The Cortex-M family consists of Cortex-M0,<sup id="cite_ref-M0-Home_2-0" class="reference"><a href="#cite_note-M0-Home-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Cortex-M0+,<sup id="cite_ref-M0+-Home_3-0" class="reference"><a href="#cite_note-M0+-Home-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Cortex-M1,<sup id="cite_ref-M1-Home_4-0" class="reference"><a href="#cite_note-M1-Home-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> Cortex-M3,<sup id="cite_ref-M3-Home_5-0" class="reference"><a href="#cite_note-M3-Home-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> Cortex-M4,<sup id="cite_ref-M4-Home_6-0" class="reference"><a href="#cite_note-M4-Home-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> Cortex-M7,<sup id="cite_ref-M7-Home_7-0" class="reference"><a href="#cite_note-M7-Home-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> Cortex-M23,<sup id="cite_ref-M23-Home_8-0" class="reference"><a href="#cite_note-M23-Home-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> Cortex-M33,<sup id="cite_ref-M33-Home_9-0" class="reference"><a href="#cite_note-M33-Home-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> Cortex-M35P,<sup id="cite_ref-M35P-Home_10-0" class="reference"><a href="#cite_note-M35P-Home-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> Cortex-M52,<sup id="cite_ref-M52-Home_11-0" class="reference"><a href="#cite_note-M52-Home-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Cortex-M55,<sup id="cite_ref-M55-Home_12-0" class="reference"><a href="#cite_note-M55-Home-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> Cortex-M85.<sup id="cite_ref-M85-Home_13-0" class="reference"><a href="#cite_note-M85-Home-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> A <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU) option is available for Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 cores, and when included in the silicon these cores are sometimes known as "Cortex-MxF", where 'x' is the core variant. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=1" title="Edit section: Overview"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <table class="wikitable" style="float:right; margin-left:9px;"> <tbody><tr> <th colspan="2">32-bit </th></tr> <tr> <th>Year</th> <th>Core </th></tr> <tr> <td>2004</td> <td><a href="#Cortex-M3">Cortex-M3</a> </td></tr> <tr> <td>2007</td> <td><a href="#Cortex-M1">Cortex-M1</a> </td></tr> <tr> <td>2009</td> <td><a href="#Cortex-M0">Cortex-M0</a> </td></tr> <tr> <td>2010</td> <td><a href="#Cortex-M4">Cortex-M4</a> </td></tr> <tr> <td>2012</td> <td><a href="#Cortex-M0+">Cortex-M0+</a> </td></tr> <tr> <td>2014</td> <td><a href="#Cortex-M7">Cortex-M7</a> </td></tr> <tr> <td>2016</td> <td><a href="#Cortex-M23">Cortex-M23</a> </td></tr> <tr> <td>2016</td> <td><a href="#Cortex-M33">Cortex-M33</a> </td></tr> <tr> <td>2018</td> <td><a href="#Cortex-M35P">Cortex-M35P</a> </td></tr> <tr> <td>2020</td> <td><a href="#Cortex-M55">Cortex-M55</a> </td></tr> <tr> <td>2022</td> <td><a href="#Cortex-M85">Cortex-M85</a> </td></tr> <tr> <td>2023</td> <td><a href="#Cortex-M52">Cortex-M52</a> </td></tr></tbody></table> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architecture</a> and <a href="/wiki/List_of_ARM_cores" class="mw-redirect" title="List of ARM cores">List of ARM cores</a></div> <p>The ARM Cortex-M family are ARM microprocessor cores that are designed for use in <a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a>, <a href="/wiki/ASIC" class="mw-redirect" title="ASIC">ASICs</a>, <a href="/wiki/Application-specific_standard_product" class="mw-redirect" title="Application-specific standard product">ASSPs</a>, <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGAs</a>, and <a href="/wiki/System_on_a_chip" title="System on a chip">SoCs</a>. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensor controllers. </p><p>The main difference from <a href="/wiki/ARM_Cortex-A" title="ARM Cortex-A">Cortex-A</a> cores is that Cortex-M cores have no <a href="/wiki/Memory_management_unit" title="Memory management unit">memory management unit</a> (MMU) for <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a>, considered essential for "full-fledged" <a href="/wiki/Operating_systems" class="mw-redirect" title="Operating systems">operating systems</a>. Cortex-M programs instead run <a href="/wiki/Bare_metal" class="mw-redirect" title="Bare metal">bare metal</a> or on one of the many <a href="/wiki/Real-time_operating_system" title="Real-time operating system">real-time operating systems</a> which <a href="/wiki/Comparison_of_real-time_operating_systems" title="Comparison of real-time operating systems">support a Cortex-M</a>. </p><p>Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as <a href="/wiki/ARM7" title="ARM7">ARM7</a> and <a href="/wiki/ARM9" title="ARM9">ARM9</a>. </p> <div class="mw-heading mw-heading3"><h3 id="License">License</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=2" title="Edit section: License"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p><a href="/wiki/Arm_(company)" class="mw-redirect" title="Arm (company)">ARM Limited</a> neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured <a href="/wiki/Silicon" title="Silicon">silicon</a> containing the ARM CPU. </p> <div class="mw-heading mw-heading3"><h3 id="Silicon_customization">Silicon customization</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=3" title="Edit section: Silicon customization"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Integrated Device Manufacturers (IDM) receive the ARM Processor <a href="/wiki/Intellectual_property" title="Intellectual property">IP</a> as <a href="/wiki/Logic_synthesis" title="Logic synthesis">synthesizable</a> <a href="/wiki/Register_transfer_level" class="mw-redirect" title="Register transfer level">RTL</a> (written in <a href="/wiki/Verilog" title="Verilog">Verilog</a>). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions (including floating point), optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation. </p><p>Some of the silicon options for the Cortex-M cores are: </p> <ul><li>SysTick timer: A 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.<sup id="cite_ref-ARMv6-M-Manual_14-0" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-0" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AppNote179_16-0" class="reference"><a href="#cite_note-AppNote179-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> Though the SysTick timer is optional for the M0/M0+/M1/M23, it is extremely rare to find a Cortex-M microcontroller without it. If a Cortex-M33/M35P/M52/M55/M85 microcontroller has the Security Extension option, then it optionally can have two SysTicks (one Secure, one Non-secure).</li> <li><span class="anchor" id="Bit-band"></span>Bit-Band: Maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bit-band region. This allows every individual bit in the bit-band region to be directly accessible from a word-aligned address. In particular, individual bits can be set, cleared, or toggled from C/C++ without performing a read-modify-write sequence of instructions.<sup id="cite_ref-ARMv6-M-Manual_14-1" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-1" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AppNote179_16-1" class="reference"><a href="#cite_note-AppNote179-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> Though the bit-band is optional, it is less common to find a Cortex-M3 and Cortex-M4 microcontroller without it. Some Cortex-M0 and Cortex-M0+ microcontrollers have bit-band.</li> <li>Memory Protection Unit (MPU): Provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to sixteen different regions, each of which can be split further into equal-size sub-regions.<sup id="cite_ref-ARMv6-M-Manual_14-2" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-2" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-AppNote179_16-2" class="reference"><a href="#cite_note-AppNote179-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li> <li>Tightly-Coupled Memory (TCM): Low-latency (zero <a href="/wiki/Wait_state" title="Wait state">wait state</a>) <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a> that can be used to hold the <a href="/wiki/Call_stack" title="Call stack">call stack</a>, RTOS control structures, interrupt data structures, <a href="/wiki/Interrupt_handler" title="Interrupt handler">interrupt handler</a> code, and speed critical code. Other than <a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a>, TCM is the fastest memory in an ARM Cortex-M microcontroller. Since TCM isn't cached and accessible at the same speed as the processor and cache, it could be conceptually described as "addressable cache". There is an ITCM (Instruction TCM) and a DTCM (Data TCM) to allow a <a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard architecture</a> processor to read from both simultaneously. The DTCM can't contain any instructions, but the ITCM can contain data. Since TCM is tightly connected to the processor core, <a href="/wiki/Direct_memory_access" title="Direct memory access">DMA</a> engines might not be able to access TCM on some implementations.</li></ul> <table class="wikitable"> <caption><big>ARM Cortex-M optional components</big> </caption> <tbody><tr> <th>ARM Core</th> <th>Cortex<br />M0<sup id="cite_ref-M0-TRM_17-0" class="reference"><a href="#cite_note-M0-TRM-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M0+<sup id="cite_ref-M0+-TRM_18-0" class="reference"><a href="#cite_note-M0+-TRM-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M1<sup id="cite_ref-M1-TRM_19-0" class="reference"><a href="#cite_note-M1-TRM-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M3<sup id="cite_ref-M3-TRM_20-0" class="reference"><a href="#cite_note-M3-TRM-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M4<sup id="cite_ref-M4-TRM_21-0" class="reference"><a href="#cite_note-M4-TRM-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M7<sup id="cite_ref-M7-TRM_22-0" class="reference"><a href="#cite_note-M7-TRM-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M23<sup id="cite_ref-M23-TRM_23-0" class="reference"><a href="#cite_note-M23-TRM-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M33<sup id="cite_ref-M33-TRM_24-0" class="reference"><a href="#cite_note-M33-TRM-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M35P<sup id="cite_ref-M35P-Home_10-1" class="reference"><a href="#cite_note-M35P-Home-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M52<sup id="cite_ref-M52-TRM_25-0" class="reference"><a href="#cite_note-M52-TRM-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M55<sup id="cite_ref-M55-TRM_26-0" class="reference"><a href="#cite_note-M55-TRM-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M85<sup id="cite_ref-M85-TRM_27-0" class="reference"><a href="#cite_note-M85-TRM-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <td>SysTick 24-bit <a href="/wiki/Programmable_interval_timer" title="Programmable interval timer">Timer</a></td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 1, 2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1, 2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1, 2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1, 2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1, 2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1, 2) </td></tr> <tr> <td>Single-cycle I/O port</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>Bit-Band memory</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-Cortex-M-SDK_28-0" class="reference"><a href="#cite_note-Cortex-M-SDK-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-Cortex-M-SDK_28-1" class="reference"><a href="#cite_note-Cortex-M-SDK-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No*</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No </td></tr> <tr> <td>Memory Protection<br />Unit (<a href="/wiki/Memory_protection_unit" title="Memory protection unit">MPU</a>)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 8)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(0,8)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 8)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 8, 16)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8, 12, 16)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8, 12, 16)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16)*</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8, 12, 16)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8, 12, 16)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8, 12, 16) </td></tr> <tr> <td><a href="/wiki/ARM_architecture#Security_extensions" class="mw-redirect" title="ARM architecture">Security</a> Attribution<br />Unit (SAU) and<br /><a href="/wiki/Stack_overflow" title="Stack overflow">Stack Limits</a></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 8)*</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8)</td> <td style="background: yellow; text-align: center;">Optional<br />(0, 4, 8) </td></tr> <tr> <td><a href="/wiki/CPU_cache" title="CPU cache">Instruction Cache</a></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-0" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-1" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-2" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-3" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-4" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 KB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB) </td></tr> <tr> <td><a href="/wiki/CPU_cache" title="CPU cache">Data Cache</a></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-5" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-6" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-7" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-8" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No<sup id="cite_ref-AppNote321_29-9" class="reference"><a href="#cite_note-AppNote321-29"><span class="cite-bracket">[</span>29<span class="cite-bracket">]</span></a></sup></td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 64 KB) </td></tr> <tr> <td>Instruction TCM<br />(ITCM) Memory</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 1 MB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB) </td></tr> <tr> <td>Data TCM<br />(DTCM) Memory</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 1 MB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB)</td> <td style="background: yellow; text-align: center;">Optional<br />(up to 16 MB) </td></tr> <tr> <td><a href="/wiki/ECC_memory" title="ECC memory">ECC</a> for TCM<br />and Cache</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td><a href="/wiki/Interrupt_vector_table" title="Interrupt vector table">Vector Table</a> Offset<br />Register (VTOR)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1)</td> <td style="background: yellow; text-align: center;">Optional<br />(0,1,2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1,2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1,2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1,2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1,2)</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes<br />(1,2) </td></tr></tbody></table> <ul><li>Note: Most Cortex-M3 and M4 chips have bit-band and MPU. The bit-band option can be added to the M0/M0+ using the Cortex-M System Design Kit.<sup id="cite_ref-Cortex-M-SDK_28-2" class="reference"><a href="#cite_note-Cortex-M-SDK-28"><span class="cite-bracket">[</span>28<span class="cite-bracket">]</span></a></sup></li> <li>Note: Software should validate the existence of each feature before attempting to use it.<sup id="cite_ref-AppNote179_16-3" class="reference"><a href="#cite_note-AppNote179-16"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup></li> <li>Note: Limited public information is available for the Cortex-M35P until its <i>Technical Reference Manual</i> is released.</li></ul> <p><i>Additional silicon options:</i><sup id="cite_ref-ARMv6-M-Manual_14-3" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-3" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <ul><li>Data endianness: Little-endian or big-endian. Unlike legacy ARM cores, the Cortex-M is permanently fixed in silicon as one of these choices.</li> <li>Interrupts: 1 to 32 (M0/M0+/M1), 1 to 240 (M3/M4/M7/M23), 1 to 480 (M33/M35P/M52/M55/M85).</li> <li>Wake-up interrupt controller: Optional.</li> <li>Vector Table Offset Register: Optional. (not available for M0).</li> <li>Instruction fetch width: 16-bit only, or mostly 32-bit.</li> <li>User/privilege support: Optional.</li> <li>Reset all registers: Optional.</li> <li>Single-cycle I/O port: Optional. (M0+/M23).</li> <li>Debug Access Port (DAP): None, <a href="/wiki/Serial_Wire_Debug" class="mw-redirect" title="Serial Wire Debug">SWD</a>, <a href="/wiki/JTAG" title="JTAG">JTAG</a> and SWD. (optional for all Cortex-M cores)</li> <li>Halting debug support: Optional.</li> <li>Number of watchpoint comparators: 0 to 2 (M0/M0+/M1), 0 to 4 (M3/M4/M7/M23/M33/M35P/M52/M55/M85).</li> <li>Number of breakpoint comparators: 0 to 4 (M0/M0+/M1/M23), 0 to 8 (M3/M4/M7/M33/M35P/M52/M55/M85).</li></ul> <div class="mw-heading mw-heading3"><h3 id="Instruction_sets"><span class="anchor" id="ARMv6-M"></span><span class="anchor" id="ARMv7-M"></span><span class="anchor" id="ARMv7E-M"></span><span class="anchor" id="ARMv8-M"></span><span class="anchor" id="ARMv8.1-M"></span>Instruction sets</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=4" title="Edit section: Instruction sets"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">See also: <a href="/wiki/ARM_architecture#Instruction_set" class="mw-redirect" title="ARM architecture">ARM architecture § Instruction set</a></div> <p>The Cortex-M0 / M0+ / M1 implement the <b>ARMv6-M</b> architecture,<sup id="cite_ref-ARMv6-M-Manual_14-4" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> the Cortex-M3 implements the <b>ARMv7-M</b> architecture,<sup id="cite_ref-ARMv7-M-Manual_15-4" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> the Cortex-M4 / Cortex-M7 implements the <b>ARMv7E-M</b> architecture,<sup id="cite_ref-ARMv7-M-Manual_15-5" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> the Cortex-M23 / M33 / M35P implement the <b>ARMv8-M</b> architecture,<sup id="cite_ref-ARMv8-M-Manual_30-0" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> and the Cortex-M52 / M55 / M85 implements the <b>ARMv8.1-M</b> architecture.<sup id="cite_ref-ARMv8-M-Manual_30-1" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P.<sup id="cite_ref-ARMv6-M-Manual_14-5" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-6" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported. </p><p>All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family. </p><p>The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).<sup id="cite_ref-ARMv6-M-Manual_14-6" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and <a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">saturation arithmetic</a> instructions. The Cortex-M4 adds <a href="/wiki/Digital_signal_processor" title="Digital signal processor">DSP</a> instructions and an optional single-precision <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).<sup id="cite_ref-M7-TRM_22-1" class="reference"><a href="#cite_note-M7-TRM-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-7" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> The Cortex-M23 / M33 / M35P / M52 / M55 / M85 add <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> instructions. </p> <table class="wikitable"> <caption><big>ARM Cortex-M instruction variations</big> </caption> <tbody><tr> <th>Arm Core</th> <th>Cortex<br />M0<sup id="cite_ref-M0-TRM_17-1" class="reference"><a href="#cite_note-M0-TRM-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M0+<sup id="cite_ref-M0+-TRM_18-1" class="reference"><a href="#cite_note-M0+-TRM-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M1<sup id="cite_ref-M1-TRM_19-1" class="reference"><a href="#cite_note-M1-TRM-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M3<sup id="cite_ref-M3-TRM_20-1" class="reference"><a href="#cite_note-M3-TRM-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M4<sup id="cite_ref-M4-TRM_21-1" class="reference"><a href="#cite_note-M4-TRM-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M7<sup id="cite_ref-M7-TRM_22-2" class="reference"><a href="#cite_note-M7-TRM-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M23<sup id="cite_ref-M23-TRM_23-1" class="reference"><a href="#cite_note-M23-TRM-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M33<sup id="cite_ref-M33-TRM_24-1" class="reference"><a href="#cite_note-M33-TRM-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M35P</th> <th>Cortex<br />M52<sup id="cite_ref-M52-TRM_25-1" class="reference"><a href="#cite_note-M52-TRM-25"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M55<sup id="cite_ref-M55-TRM_26-1" class="reference"><a href="#cite_note-M55-TRM-26"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup></th> <th>Cortex<br />M85<sup id="cite_ref-M85-TRM_27-1" class="reference"><a href="#cite_note-M85-TRM-27"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </th></tr> <tr> <td><a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM architecture</a></td> <td style="text-align: center;">ARMv6-M<br /><sup id="cite_ref-ARMv6-M-Manual_14-7" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv6-M<br /><sup id="cite_ref-ARMv6-M-Manual_14-8" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv6-M<br /><sup id="cite_ref-ARMv6-M-Manual_14-9" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv7-M<br /><sup id="cite_ref-ARMv7-M-Manual_15-8" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv7E-M<br /><sup id="cite_ref-ARMv7-M-Manual_15-9" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv7E-M<br /><sup id="cite_ref-ARMv7-M-Manual_15-10" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv8-M<br />Baseline<sup id="cite_ref-ARMv8-M-Manual_30-2" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv8-M<br />Mainline<sup id="cite_ref-ARMv8-M-Manual_30-3" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">ARMv8-M<br />Mainline<sup id="cite_ref-ARMv8-M-Manual_30-4" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">Armv8.1-M<br />Mainline<sup id="cite_ref-ARMv8-M-Manual_30-5" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">Armv8.1-M<br />Mainline<sup id="cite_ref-ARMv8-M-Manual_30-6" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></td> <td style="text-align: center;">Armv8.1-M<br />Mainline<sup id="cite_ref-ARMv8-M-Manual_30-7" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></td> <td style="text-align: center;"><a href="/wiki/Von_Neumann_architecture" title="Von Neumann architecture">Von<br />Neumann</a></td> <td style="text-align: center;">Von<br />Neumann</td> <td style="text-align: center;">Von<br />Neumann</td> <td style="text-align: center;"><a href="/wiki/Harvard_architecture" title="Harvard architecture">Harvard</a></td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Von<br />Neumann</td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Harvard</td> <td style="text-align: center;">Harvard </td></tr> <tr> <td><a href="/wiki/Instruction_pipelining" title="Instruction pipelining">Instruction pipeline</a></td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">2 stages</td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">6 stages</td> <td style="text-align: center;">2 stages</td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">3 stages</td> <td style="text-align: center;">4 stages</td> <td style="text-align: center;">4-5 stages</td> <td style="text-align: center;">7 stages </td></tr> <tr> <td><a href="/wiki/Interrupt_latency" title="Interrupt latency">Interrupt latency</a><br />(zero <a href="/wiki/Wait_state" title="Wait state">wait state</a> memory)</td> <td style="text-align: center;">16 cycles</td> <td style="text-align: center;">15 cycles</td> <td style="text-align: center;">23 for NMI,<br />26 for IRQ</td> <td style="text-align: center;">12 cycles</td> <td style="text-align: center;">12 cycles</td> <td style="text-align: center;">12 cycles,<br />14 worst<br />case</td> <td style="text-align: center;">15 cycles,<br />24 secure<br />to NS IRQ</td> <td style="text-align: center;">12 cycles,<br />21 secure<br />to NS IRQ</td> <td style="background: grey; text-align: center;">TBD</td> <td style="background: grey; text-align: center;">TBD</td> <td style="background: grey; text-align: center;">TBD</td> <td style="background: grey; text-align: center;">TBD </td></tr> <tr> <td><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a> instructions</td> <td style="background: cyan; text-align: center;">Most</td> <td style="background: cyan; text-align: center;">Most</td> <td style="background: cyan; text-align: center;">Most</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background: cyan; text-align: center;">Most</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire </td></tr> <tr> <td><a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a> instructions</td> <td style="background: cyan; text-align: center;">Some</td> <td style="background: cyan; text-align: center;">Some</td> <td style="background: cyan; text-align: center;">Some</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background: cyan; text-align: center;">Some</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Entire </td></tr> <tr> <td><a href="/wiki/Multiplication_algorithm" title="Multiplication algorithm">Multiply</a> instructions<br />32×32 = 32-bit result</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td>Multiply instructions<br />32×32 = 64-bit result</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a href="/wiki/Division_algorithm" title="Division algorithm">Divide</a> instructions<br />32/32 = 32-bit quotient</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a> math instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: cyan; text-align: center;">Some</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a href="/wiki/Digital_signal_processor" title="Digital signal processor">DSP</a> instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">Half-Precision</a> (HP)<br /><a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point</a> instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td><a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">Single-Precision</a> (SP)<br />floating-point instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td><a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">Double-Precision</a> (DP)<br />floating-point instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td>Helium vector instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td><a href="/wiki/Coprocessor" title="Coprocessor">Co-processor</a> instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td>ARM Custom Instructions (ACI)</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td>Pointer Authentication and Branch Target<br />Identification (PACBTI) instructions</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional </td></tr></tbody></table> <ul><li>Note: Interrupt latency cycle count assumes: 1) stack located in zero-wait state RAM, 2) another interrupt function not currently executing, 3) Security Extension option doesn't exist, because it adds additional cycles. The Cortex-M cores with a Harvard computer architecture have a shorter interrupt latency than Cortex-M cores with a Von Neumann computer architecture.</li> <li>Note: The Cortex-M series includes three new 16-bit <b>Thumb-1</b> instructions for sleep mode: SEV, WFE, WFI.</li> <li>Note: The Cortex-M0 / M0+ / M1 doesn't include these 16-bit <b>Thumb-1</b> instructions: CBZ, CBNZ, IT.<sup id="cite_ref-ARMv6-M-Manual_14-10" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-11" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>Note: The Cortex-M0 / M0+ / M1 only include these 32-bit <b>Thumb-2</b> instructions: BL, DMB, DSB, ISB, MRS, MSR.<sup id="cite_ref-ARMv6-M-Manual_14-11" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-12" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>Note: The Cortex-M0 / M0+ / M1 / M23 only has 32-bit <b>multiply</b> instructions with a lower-32-bit result (32 bit × 32 bit = lower 32 bit), where as the Cortex-M3 / M4 / M7 / M33 / M35P includes additional 32-bit multiply instructions with 64-bit results (32 bit × 32 bit = 64 bit). The Cortex-M4 / M7 (optionally M33 / M35P) include DSP instructions for (16 bit × 16 bit = 32 bit), (32 bit × 16 bit = upper 32 bit), (32 bit × 32 bit = upper 32 bit) multiplications.<sup id="cite_ref-ARMv6-M-Manual_14-12" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-13" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>Note: The number of cycles to complete multiply and divide instructions vary across ARM Cortex-M core designs. Some cores have a silicon option for the choice of fast speed or small size (slow speed), so cores have the option of using less silicon with the downside of higher cycle count. An interrupt occurring during the execution of a divide instruction or slow-iterative multiply instruction will cause the processor to abandon the instruction, then restart it after the interrupt returns. <ul><li>Multiply instructions "32-bit result" –  Cortex-M0/M0+/M23 is 1 or 32 cycle silicon option, Cortex-M1 is 3 or 33 cycle silicon option, Cortex-M3/M4/M7/M33/M35P is 1 cycle.</li> <li>Multiply instructions "64-bit result" –  Cortex-M3 is 3–5 cycles (depending on values), Cortex-M4/M7/M33/M35P is 1 cycle.</li> <li>Divide instructions –  Cortex-M3/M4 is 2–12 cycles (depending on values), Cortex-M7 is 3–20 cycles (depending on values), Cortex-M23 is 17 or 34 cycle option, Cortex-M33 is 2–11 cycles (depending on values), Cortex-M35P is TBD.</li></ul></li> <li>Note: Some Cortex-M cores have silicon options for various types of floating point units (<b>FPU</b>). The Cortex-M55 / M85 has an option for <a href="/wiki/Half-precision_floating-point_format" title="Half-precision floating-point format">half-precision</a> (<b>HP</b>), the Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 has an option for <a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">single-precision</a> (<b>SP</b>), the Cortex-M7 / M52 / M55 / M85 has an option for <a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision</a> (<b>DP</b>). When an FPU is included, the core is sometimes referred as "Cortex-MxF", where 'x' is the core variant, such as Cortex-M4<b>F</b>.<sup id="cite_ref-ARMv6-M-Manual_14-13" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-14" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li></ul> <table class="wikitable"> <caption><big>ARM Cortex-M instruction groups</big> </caption> <tbody><tr> <th>Group</th> <th>Instr<br />bits</th> <th>Instructions</th> <th>Cortex<br />M0, M0+, M1</th> <th>Cortex<br />M3</th> <th>Cortex<br />M4</th> <th>Cortex<br />M7</th> <th>Cortex<br />M23</th> <th>Cortex<br />M33</th> <th>Cortex<br />M35P</th> <th>Cortex<br />M52</th> <th>Cortex<br />M55</th> <th>Cortex<br />M85 </th></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-1</span></td> <td style="text-align: center;">16</td> <td>ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-1</span></td> <td style="text-align: center;">16</td> <td>CBNZ, CBZ</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-1</span></td> <td style="text-align: center;">16</td> <td>IT</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-2</span></td> <td style="text-align: center;">32</td> <td>BL, DMB, DSB, ISB, MRS, MSR</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-2</span></td> <td style="text-align: center;">32</td> <td>SDIV, UDIV, MOVT, MOVW, B.W, LDREX, LDREXB, LDREXH, STREX, STREXB, STREXH</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><span class="nowrap">Thumb-2</span></td> <td style="text-align: center;">32</td> <td>ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, <a href="/wiki/Find_first_set#CLZ" title="Find first set">CLZ</a>, CMN, CMP, DBG, EOR, LDC, LDM, LDR, LDRB, LDRBT, LDRD, LDRH, LDRHT, LDRSB, LDRSBT, LDRSH, LDRSHT, LDRT, LSL, LSR, MCR, MCRR, MLA, MLS, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SEV, SMLAL, SMULL, SSAT, STC, STM, STR, STRB, STRBT, STRD, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><a href="/wiki/Digital_signal_processor" title="Digital signal processor">DSP</a></td> <td style="text-align: center;">32</td> <td>PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;"><a href="/wiki/Single-precision_floating-point_format" title="Single-precision floating-point format">SP Float</a></td> <td style="text-align: center;">32</td> <td>VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td style="text-align: center;"><a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">DP Float</a></td> <td style="text-align: center;">32</td> <td>VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSEL</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td style="text-align: center;">Acquire/Release</td> <td style="text-align: center;">32</td> <td>LDA, LDAB, LDAH, LDAEX, LDAEXB, LDAEXH, STL, STLB, STLH, STLEX, STLEXB, STLEXH</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td rowspan="2" style="text-align: center;"><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a></td> <td style="text-align: center;">16</td> <td>BLXNS, BXNS</td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td rowspan="2" style="background: yellow; text-align: center;">Optional</td> <td rowspan="2" style="background: yellow; text-align: center;">Optional</td> <td rowspan="2" style="background: yellow; text-align: center;">Optional</td> <td rowspan="2" style="background: yellow; text-align: center;">Optional</td> <td rowspan="2" style="background: yellow; text-align: center;">Optional</td> <td rowspan="2" style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Yes </td></tr> <tr> <td style="text-align: center;">32</td> <td>SG, TT, TTT, TTA, TTAT </td></tr> <tr> <td style="text-align: center;"><a href="/wiki/Coprocessor" title="Coprocessor">Co-processor</a></td> <td style="text-align: center;">16</td> <td>CDP, CDP2, MCR, MCR2, MCRR, MCRR2, MRC, MRC2, MRRC, MRRC2</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td style="text-align: center;">ACI</td> <td style="text-align: center;">32</td> <td>CX1, CX1A, CX2, CX2A, CX3, CX3A, CX1D, CX1DA, CX2D, CX2DA, CX3D, CX3DA, VCX1, VCX1A, VCX2, VCX2A, VCX3, VCX3A</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background: yellow; text-align: center;">Optional </td></tr> <tr> <td style="text-align: center;">PACBTI</td> <td style="text-align: center;">32</td> <td>AUT, AUTG, BTI, BXAUT, PAC, PACBTI, PACG</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">No</td> <td style="background: yellow; text-align: center;">Optional </td></tr></tbody></table> <ul><li>Note: MOVW is an alias that means 32-bit "wide" MOV instruction.</li> <li>Note: B.W is a long-distance unconditional branch (similar in encoding, operation, and range to BL, minus setting of the LR register).</li> <li>Note: For Cortex-M1, WFE / WFI / SEV instructions exist, but execute as a NOP instruction.</li> <li>Note: The half-precision (HP) FPU instructions are valid in the Cortex-M52 / M55 / M85 only when the HP FPU option exists in the silicon.</li> <li>Note: The single-precision (SP) FPU instructions are valid in the Cortex-M4 / M7 / M33 / M35P / M52 / M55 / M85 only when the SP FPU option exists in the silicon.</li> <li>Note: The double-precision (DP) FPU instructions are valid in the Cortex-M7 / M52 / M55 / M85 only when the DP FPU option exists in the silicon.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Deprecations">Deprecations</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=5" title="Edit section: Deprecations"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:<sup id="cite_ref-ARMv6-M-Manual_14-14" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-ARMv7-M-Manual_15-15" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> </p> <ul><li>The 32-bit ARM instruction set is not included in Cortex-M cores.</li> <li>Endianness is chosen at silicon implementation in Cortex-M cores. Legacy cores allowed "on-the-fly" changing of the data <a href="/wiki/Endianness" title="Endianness">endian</a> mode.</li> <li><a href="/wiki/Coprocessor" title="Coprocessor">Co-processors</a> were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.</li></ul> <p>The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature: </p> <ul><li>The SWP and SWPB (swap) ARM instructions don't have a similar feature in Cortex-M.</li></ul> <p>The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy <a href="/wiki/ARM7" title="ARM7">ARM7T</a> cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores: </p> <ul><li>The "BLX <immediate>" instruction doesn't exist because it was used to switch from Thumb-1 to ARM instruction set. The "BLX <register>" instruction is still available in the Cortex-M.</li> <li>SETEND doesn't exist because on-the-fly switching of data endian mode is no longer supported.</li> <li>Co-processor instructions were not supported on Cortex-M cores, until the silicon option was reintroduced in "ARMv8-M Mainline" for ARM Cortex-M33/M35P cores.</li> <li>The SWI instruction was renamed to SVC, though the instruction binary coding is the same. However, the SVC handler code is different from the SWI handler code, because of changes to the exception models.</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M0">Cortex-M0</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=6" title="Edit section: Cortex-M0"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">Cortex-M0</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data">ARMv6-M (<a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a> (most),<br /><a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a> (some))</td></tr></tbody></table> <p>The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.<sup id="cite_ref-M0-Home_2-1" class="reference"><a href="#cite_note-M0-Home-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M0 core are:<sup id="cite_ref-M0-TRM_17-2" class="reference"><a href="#cite_note-M0-TRM-17"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv6-M architecture<sup id="cite_ref-ARMv6-M-Manual_14-15" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li> <li>3-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a></li> <li>Instruction sets: <ul><li>Thumb-1 (most), missing CBZ, CBNZ, IT</li> <li>Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR</li> <li>32-bit hardware integer multiply with 32-bit result</li></ul></li> <li>1 to 32 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a></li></ul> <p><b>Silicon options:</b> </p> <ul><li>Hardware integer multiply speed: 1 or 32 cycles.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=7" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg/220px-M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg/330px-M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3f/M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg/440px-M2_Health_Bracelet_-_controller_board_-_Nordic_N51822-0627.jpg 2x" data-file-width="1609" data-file-height="1609" /></a><figcaption>nRF51822</figcaption></figure> <p>The following microcontrollers are based on the Cortex-M0 core: </p> <ul><li>ABOV AC30M1x64</li> <li><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a> PSoC 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M</li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a> <a href="/wiki/Infineon_XMC" title="Infineon XMC">XMC1100</a>, XMC1200, XMC1300, XMC1400, TLE984x</li> <li><a href="/wiki/Dialog_Semiconductor" title="Dialog Semiconductor">Dialog</a> DA1458x, DA1468x</li> <li><a href="/wiki/Nordic_Semiconductor" title="Nordic Semiconductor">Nordic</a> <a href="/wiki/NRF51" class="mw-redirect" title="NRF51">nRF51</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> <a href="/wiki/LPC1100" class="mw-redirect" title="LPC1100">LPC1100</a>, <a href="/wiki/LPC1200" class="mw-redirect" title="LPC1200">LPC1200</a></li> <li><a href="/wiki/Nuvoton" title="Nuvoton">Nuvoton</a> NuMicro</li> <li>Sonix SN32F700</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32#STM32_F0" title="STM32">STM32 F0</a></li> <li><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> TX00</li> <li>Vorago VA10800 (extreme temperature), VA10820 (radiation hardened)</li></ul> <p>The following chips have a Cortex-M0 as a secondary core: </p> <ul><li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> <a href="/wiki/LPC4300" class="mw-redirect" title="LPC4300">LPC4300</a> (one Cortex-M4F + one Cortex-M0)</li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> SimpleLink Wireless MCUs CC1310 and CC2650 (one programmable Cortex-M3 + one Cortex-M0 network processor + one proprietary Sensor Controller Engine)</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M0+"><span id="Cortex-M0.2B"></span>Cortex-M0+</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=8" title="Edit section: Cortex-M0+"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M0+</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv6-M</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1 (most)</a>,<br /><a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2 (some)</a></td></tr></tbody></table> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_(ARM_Cortex-M0%2B_MCU).JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG/220px-Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG" decoding="async" width="220" height="127" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG/330px-Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG/440px-Freescale_FRDM-KL25Z_board_with_KL25Z128VLK_%28ARM_Cortex-M0%2B_MCU%29.JPG 2x" data-file-width="2271" data-file-height="1311" /></a><figcaption> <a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) FRDM-KL25Z Board with KL25Z128VLK (Kinetis L)</figcaption></figure> <p>The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage and increases performance (higher average IPC due to branches taking one fewer cycle). In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the <a href="/wiki/Memory_protection" title="Memory protection">memory protection</a> unit (MPU) and the vector table relocation.<sup id="cite_ref-M0+-TRM_18-2" class="reference"><a href="#cite_note-M0+-TRM-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M0+ core are:<sup id="cite_ref-M0+-TRM_18-3" class="reference"><a href="#cite_note-M0+-TRM-18"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv6-M architecture<sup id="cite_ref-ARMv6-M-Manual_14-16" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li> <li>2-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> (one fewer than Cortex-M0)</li> <li>Instruction sets: (same as Cortex-M0) <ul><li>Thumb-1 (most), missing CBZ, CBNZ, IT</li> <li>Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR</li> <li>32-bit hardware integer multiply with 32-bit result</li></ul></li> <li>1 to 32 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a></li></ul> <p><b>Silicon options:</b> </p> <ul><li>Hardware integer multiply speed: 1 or 32 cycles</li> <li>8-region memory protection unit (MPU) (same as M3 and M4)</li> <li>Vector table relocation (same as M3, M4)</li> <li>Single-cycle I/O port (available in M0+/M23)</li> <li>Micro Trace Buffer (MTB) (available in M0+/M23/M33/M35P)</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_2">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=9" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M0+ core: </p> <ul><li>ABOV Semiconductor A31G11x, A31G12x, A31G314</li> <li><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a> PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+</li> <li><a href="/wiki/Epson" title="Epson">Epson</a> S1C31W74, S1C31D01, S1C31D50</li> <li><a href="/wiki/Holtek" title="Holtek">Holtek</a> HT32F52000</li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip</a> <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> C2, D0, D1, D2, DA, L2, R2, R3; and <a href="/wiki/PIC_microcontrollers" title="PIC microcontrollers">PIC32CM</a> JH and MC<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>31<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> <a href="/wiki/LPC800" class="mw-redirect" title="LPC800">LPC800</a>, LPC11E60, LPC11U60</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) Kinetis E, EA, L, M, V1, W0, S32K11x</li> <li><a href="/wiki/Raspberry_Pi_Foundation" title="Raspberry Pi Foundation">Raspberry Pi</a> <a href="/wiki/RP2040" title="RP2040">RP2040</a> (two M0+ cores)</li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> S124, S128, RE, RE01</li> <li><a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a> (<a href="/wiki/Energy_Micro" title="Energy Micro">Energy Micro</a>) <a href="/wiki/EFM32" title="EFM32">EFM32</a> Zero, Happy</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32#STM32_L0" title="STM32">STM32 L0</a>, <a href="/wiki/STM32#STM32_G0" title="STM32">G0</a>, <a href="/wiki/STM32#STM32_C0" title="STM32">C0</a>, <a href="/wiki/STM32#STM32_WL" title="STM32">WL (one Cortex-M4 + one Cortex-M0+)</a></li></ul> <p>The following chips have a Cortex-M0+ as a secondary core: </p> <ul><li><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a> PSoC 6200 (one Cortex-M4F + one Cortex-M0+)</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> WB (one Cortex-M4F + one Cortex-M0+)</li></ul> <p>The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm in a <a href="/wiki/Chip-scale_package" title="Chip-scale package">chip-scale package</a> is Kinetis KL03).<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>32<span class="cite-bracket">]</span></a></sup> </p><p>On 21 June 2018, the "<a href="/wiki/Microcontroller#Smallest_computer" title="Microcontroller">world's smallest computer'</a>", or computer device was announced –  based on the ARM Cortex-M0+ (and including RAM and <a href="/wiki/Wireless_networking" class="mw-redirect" title="Wireless networking">wireless transmitters and receivers</a> based on <a href="/wiki/Photovoltaics" title="Photovoltaics">photovoltaics</a>) –  by <a href="/wiki/University_of_Michigan" title="University of Michigan">University of Michigan</a> researchers at the 2018 Symposia on VLSI Technology and Circuits with the paper "A 0.04mm<sup>3</sup> 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement." The device is one-tenth the size of IBM's previously claimed world-record-sized computer from months back in March 2018, which is smaller than a grain of salt. </p> <div class="mw-heading mw-heading2"><h2 id="Cortex-M1">Cortex-M1</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=10" title="Edit section: Cortex-M1"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M1</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv6-M</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1 (most)</a>,<br /><a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2 (some)</a></td></tr></tbody></table> <p>The Cortex-M1 is an optimized core especially designed to be loaded into <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a> chips.<sup id="cite_ref-M1-Home_4-1" class="reference"><a href="#cite_note-M1-Home-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M1 core are:<sup id="cite_ref-M1-TRM_19-2" class="reference"><a href="#cite_note-M1-TRM-19"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv6-M architecture<sup id="cite_ref-ARMv6-M-Manual_14-17" class="reference"><a href="#cite_note-ARMv6-M-Manual-14"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup></li> <li>3-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a>.</li> <li>Instruction sets: <ul><li>Thumb-1 (most), missing CBZ, CBNZ, IT.</li> <li>Thumb-2 (some), only BL, DMB, DSB, ISB, MRS, MSR.</li> <li>32-bit hardware integer multiply with 32-bit result.</li></ul></li> <li>1 to 32 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a>.</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Hardware integer multiply speed: 3 or 33 cycles.</li> <li>Optional Tightly-Coupled Memory (TCM): 0 to 1 MB instruction-TCM, 0 to 1 MB data-TCM, each with optional ECC.</li> <li>External interrupts: 0, 1, 8, 16, 32.</li> <li>Debug: none, reduced, full.</li> <li>Data endianness: little-endian or BE-8 big-endian.</li> <li>OS extension: present or absent.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_3">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=11" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following vendors support the Cortex-M1 as soft-cores on their FPGA chips: </p> <ul><li><a href="/wiki/Altera" title="Altera">Altera</a> Cyclone-II, Cyclone-III, Stratix-II, Stratix-III</li> <li>GOWIN M1<sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>33<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Actel" title="Actel">Actel</a>/<a href="/wiki/Microsemi" title="Microsemi">Microsemi</a>/<a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip</a> Fusion, IGLOO/e, ProASIC3L, ProASIC3/E</li> <li><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7<sup id="cite_ref-34" class="reference"><a href="#cite_note-34"><span class="cite-bracket">[</span>34<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M3">Cortex-M3</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=12" title="Edit section: Cortex-M3"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M3</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv7-M</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /> <a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a> (some), Divide</td></tr></tbody></table> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:ArduinoDue_Front.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/ArduinoDue_Front.jpg/300px-ArduinoDue_Front.jpg" decoding="async" width="300" height="160" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/36/ArduinoDue_Front.jpg/450px-ArduinoDue_Front.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/36/ArduinoDue_Front.jpg/600px-ArduinoDue_Front.jpg 2x" data-file-width="1024" data-file-height="546" /></a><figcaption><a href="/wiki/Arduino" title="Arduino">Arduino</a> Due board with Atmel ATSAM3X8E (<a href="/wiki/ARM_Cortex-M3" class="mw-redirect" title="ARM Cortex-M3">ARM Cortex-M3</a> core) microcontroller</figcaption></figure> <figure typeof="mw:File/Thumb"><a href="/wiki/File:LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_(ARM_Cortex-M3)_MCU.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/76/LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg/300px-LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg" decoding="async" width="300" height="78" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/76/LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg/450px-LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/76/LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg/600px-LPCXpresso_DevelopmentBoard_with_NXP_LPC1343_%28ARM_Cortex-M3%29_MCU.jpg 2x" data-file-width="1980" data-file-height="512" /></a><figcaption><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> LPCXpresso Development Board with LPC1343</figcaption></figure> <p>Key features of the Cortex-M3 core are:<sup id="cite_ref-M3-TRM_20-2" class="reference"><a href="#cite_note-M3-TRM-20"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-35" class="reference"><a href="#cite_note-35"><span class="cite-bracket">[</span>35<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv7-M architecture<sup id="cite_ref-ARMv7-M-Manual_15-16" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>3-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> with <a href="/wiki/Branch_predictor" title="Branch predictor">branch speculation</a>.</li> <li>Instruction sets: <ul><li>Thumb-1 (entire).</li> <li>Thumb-2 (entire).</li> <li>32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit multiply is 1 cycle, but 64-bit multiply and MAC instructions require extra cycles.</li> <li>32-bit hardware integer divide (2–12 cycles).</li> <li><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">saturation arithmetic</a> support.</li></ul></li> <li>1 to 240 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a>.</li> <li>12 cycle interrupt latency.</li> <li>Integrated sleep modes.</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Optional Memory Protection Unit (MPU): 0 or 8 regions.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_4">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=13" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M3 core: </p> <ul><li>ABOV AC33Mx128, AC33Mx064</li> <li><a href="/wiki/Actel" title="Actel">Actel</a>/<a href="/wiki/Microsemi" title="Microsemi">Microsemi</a>/<a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip</a> <a href="/wiki/Actel_SmartFusion" title="Actel SmartFusion">SmartFusion, SmartFusion 2</a> (FPGA)</li> <li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> ADUCM360, ADUCM361, ADUCM3029</li> <li><a href="/wiki/Broadcom_Corporation" title="Broadcom Corporation">Broadcom</a> Wi-Fi Chip BCM4319XKUBG</li> <li><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a> <a href="/wiki/PSoC" class="mw-redirect" title="PSoC">PSoC</a> 5000, 5000LP, FM3</li> <li><a href="/wiki/Holtek" title="Holtek">Holtek</a> HT32F</li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a> TLE9860, TLE987x</li> <li><a href="/wiki/Atmel" title="Atmel">Microchip (Atmel)</a> <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> 3A, 3N, 3S, 3U, 3X</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> <a href="/wiki/LPC1300" class="mw-redirect" title="LPC1300">LPC1300</a>, <a href="/wiki/LPC1700" class="mw-redirect" title="LPC1700">LPC1700</a>, <a href="/wiki/LPC1800" class="mw-redirect" title="LPC1800">LPC1800</a></li> <li><a href="/wiki/ON_Semiconductor" class="mw-redirect" title="ON Semiconductor">ON</a> Q32M210</li> <li><a href="/wiki/Realtek" title="Realtek">Realtek</a> RTL8710</li> <li><a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a> Precision32</li> <li><a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a> (<a href="/wiki/Energy_Micro" title="Energy Micro">Energy Micro</a>) <a href="/wiki/EFM32" title="EFM32">EFM32 Tiny, Gecko, Leopard, Giant</a></li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32" title="STM32">STM32</a> F1, F2, L1, W</li> <li>TDK-Micronas HVC4223F</li> <li>Texas Instruments F28, LM3, TMS470, <a href="/wiki/OMAP#OMAP_4" title="OMAP">OMAP 4</a>, SimpleLink Wireless MCUs (CC1310 Sub-GHz and CC2650 <a href="/wiki/Bluetooth_Smart" class="mw-redirect" title="Bluetooth Smart">BLE</a>+<a href="/wiki/Zigbee" title="Zigbee">Zigbee</a>+<a href="/wiki/6LoWPAN" title="6LoWPAN">6LoWPAN</a>)</li> <li><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> TX03</li> <li><a href="/w/index.php?title=Mindmotion&action=edit&redlink=1" class="new" title="Mindmotion (page does not exist)">mindmotion</a> mindmotion MM32</li></ul> <p>The following chips have a Cortex-M3 as a secondary core: </p> <ul><li><a href="/wiki/Apple_A9" title="Apple A9">Apple A9</a> (Cortex-M3 as integrated <a href="/wiki/Apple_motion_coprocessors" title="Apple motion coprocessors">M9 motion co-processor</a>)</li> <li><a href="/wiki/CSR_plc" title="CSR plc">CSR</a> Quatro 5300 (Cortex-M3 as co-processor)</li> <li><a href="/wiki/Samsung" title="Samsung">Samsung</a> <a href="/wiki/Exynos" title="Exynos">Exynos</a> 7420 (Cortex-M3 as a <a href="/wiki/Dynamic_voltage_scaling" title="Dynamic voltage scaling">DVS</a> microcontroller)<sup id="cite_ref-36" class="reference"><a href="#cite_note-36"><span class="cite-bracket">[</span>36<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> F28, LM3, TMS470, <a href="/wiki/OMAP#OMAP_4" title="OMAP">OMAP 4470</a> (one <a href="/wiki/ARM_Cortex-A9_MPCore" class="mw-redirect" title="ARM Cortex-A9 MPCore">Cortex-A9</a> + two Cortex-M3)</li> <li><a href="/wiki/XMOS" title="XMOS">XMOS</a> XS1-XA (seven xCORE + one Cortex-M3)</li></ul> <p>The following FPGAs include a Cortex-M3 core: </p> <ul><li><a href="/wiki/Microsemi" title="Microsemi">Microsemi</a> SmartFusion2 SoC</li></ul> <p>The following vendors support the Cortex-M3 as soft-cores on their FPGA chips: </p> <ul><li><a href="/wiki/Altera" title="Altera">Altera</a> Cyclone-II, Cyclone-III, Stratix-II, Stratix-III</li> <li><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> Spartan-3, Virtex-2, Virtex-3, Virtex-4, Artix-7<sup id="cite_ref-37" class="reference"><a href="#cite_note-37"><span class="cite-bracket">[</span>37<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M4">Cortex-M4</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=14" title="Edit section: Cortex-M4"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M4</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv7E-M</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (SP)</td></tr></tbody></table> <figure class="mw-default-size mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_(ARM_Cortex-M4F)_MCU.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/da/Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG/220px-Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG" decoding="async" width="220" height="103" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/da/Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG/330px-Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/da/Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG/440px-Energy_Micro_Woder_Gecko_STK_showing_EFM32WG990F256_%28ARM_Cortex-M4F%29_MCU.JPG 2x" data-file-width="3884" data-file-height="1812" /></a><figcaption>Silicon Labs (<a href="/wiki/Energy_Micro" title="Energy Micro">Energy Micro</a>) Wonder Gecko STK Board with <a href="/wiki/EFM32" title="EFM32">EFM32</a>WG990</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:TI_Stellaris_Launchpad_showing_LM4F120H_(ARM_Cortex-M4F)_MCU.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG/220px-TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG" decoding="async" width="220" height="243" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3a/TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG/330px-TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3a/TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG/440px-TI_Stellaris_Launchpad_showing_LM4F120H_%28ARM_Cortex-M4F%29_MCU.JPG 2x" data-file-width="1533" data-file-height="1692" /></a><figcaption><a href="/wiki/Texas_Instruments" title="Texas Instruments">TI</a> Stellaris Launchpad Board with LM4F120</figcaption></figure> <p>Conceptually the Cortex-M4 is a Cortex-M3 plus <a href="/wiki/Digital_signal_processor" title="Digital signal processor">DSP</a> instructions, and optional floating-point unit (FPU). A core with an FPU is known as Cortex-M4F. </p><p>Key features of the Cortex-M4 core are:<sup id="cite_ref-M4-TRM_21-2" class="reference"><a href="#cite_note-M4-TRM-21"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv7E-M architecture<sup id="cite_ref-ARMv7-M-Manual_15-17" class="reference"><a href="#cite_note-ARMv7-M-Manual-15"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup></li> <li>3-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> with <a href="/wiki/Branch_predictor" title="Branch predictor">branch speculation</a>.</li> <li>Instruction sets: <ul><li>Thumb-1 (entire).</li> <li>Thumb-2 (entire).</li> <li>32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.</li> <li>32-bit hardware integer divide (2–12 cycles).</li> <li><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturation arithmetic</a> support.</li> <li>DSP extension: Single cycle 16/32-bit <a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">MAC</a>, single cycle dual 16-bit MAC, 8/16-bit <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> arithmetic.</li></ul></li> <li>1 to 240 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a>.</li> <li>12 cycle interrupt latency.</li> <li>Integrated sleep modes.</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Optional floating-point unit (FPU): single-precision only <a href="/wiki/IEEE-754" class="mw-redirect" title="IEEE-754">IEEE-754</a> compliant. It is called the FPv4-SP extension.</li> <li>Optional memory protection unit (MPU): 0 or 8 regions.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_5">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=15" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Micro-bit_v2_(cropped)_nRF52833.JPG" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/10/Micro-bit_v2_%28cropped%29_nRF52833.JPG/170px-Micro-bit_v2_%28cropped%29_nRF52833.JPG" decoding="async" width="170" height="170" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/1/10/Micro-bit_v2_%28cropped%29_nRF52833.JPG 1.5x" data-file-width="250" data-file-height="250" /></a><figcaption>nRF52833 on a <a href="/wiki/Micro:bit" class="mw-redirect" title="Micro:bit">micro bit</a> v2</figcaption></figure> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Embedded_World_2016,_M32F407_(cropped)_STM_M32F407IG.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/21/Embedded_World_2016%2C_M32F407_%28cropped%29_STM_M32F407IG.jpg/170px-Embedded_World_2016%2C_M32F407_%28cropped%29_STM_M32F407IG.jpg" decoding="async" width="170" height="170" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/2/21/Embedded_World_2016%2C_M32F407_%28cropped%29_STM_M32F407IG.jpg 1.5x" data-file-width="250" data-file-height="250" /></a><figcaption>STM32F407IGH6</figcaption></figure> <p>The following microcontrollers are based on the Cortex-M4 core: </p> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> ADSP-CM40x</li> <li><a href="/wiki/Atmel" title="Atmel">Microchip (Atmel)</a> <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> 4L, 4N, 4S</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) Kinetis K, W2</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> (<a href="/wiki/STM32" title="STM32">STM32</a>) WL (one Cortex-M4 + one Cortex-M0+)</li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> SimpleLink <a href="/wiki/Wi-Fi" title="Wi-Fi">Wi-Fi</a> CC32xx, CC32xxMOD</li></ul> <p>The following microcontrollers are based on the Cortex-M4F (M4 + <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPU</a>) core: </p> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> ADUCM4050</li> <li><a href="/wiki/Cypress_Semiconductor" title="Cypress Semiconductor">Cypress</a> 6200 (one Cortex-M4F + one Cortex-M0+), FM4</li> <li><a href="/wiki/Infineon" class="mw-redirect" title="Infineon">Infineon</a> <a href="/wiki/Infineon_XMC4000" class="mw-redirect" title="Infineon XMC4000">XMC4000</a></li> <li><a href="/wiki/Maxim_Integrated" title="Maxim Integrated">Maxim</a> Darwin</li> <li><a href="/wiki/Atmel" title="Atmel">Microchip (Atmel)</a> SAM4C (Dual core: one Cortex-M4F + one Cortex-M4), SAM4E, SAM4L, SAM4N, SAM4S, SAMG5, SAMD5/E5x</li> <li><a href="/wiki/Nordic_Semiconductor" title="Nordic Semiconductor">Nordic</a> nRF52</li> <li><a href="/wiki/Nuvoton" title="Nuvoton">Nuvoton</a> NuMicro M480</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> <a href="/wiki/LPC4000" class="mw-redirect" title="LPC4000">LPC4000</a>, <a href="/wiki/LPC4300" class="mw-redirect" title="LPC4300">LPC4300</a> (one Cortex-M4F + one Cortex-M0), LPC54000</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) Kinetis K, V3, V4, S32K14x</li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> S3, S5, S7, RA4, RA6</li> <li><a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a> (<a href="/wiki/Energy_Micro" title="Energy Micro">Energy Micro</a>) <a href="/wiki/EFM32" title="EFM32">EFM32 Wonder</a></li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32" title="STM32">STM32</a> F3, F4, L4, L4+, G4, WB (one Cortex-M4F + one Cortex-M0+)</li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> LM4F, TM4C, <a href="/wiki/TI_MSP432" title="TI MSP432">MSP432</a>, CC13x2R, CC1352P, CC26x2R</li> <li><a href="/wiki/Toshiba" title="Toshiba">Toshiba</a> TX04</li></ul> <p>The following chips have either a Cortex-M4 or M4F as a secondary core: </p> <ul><li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/Vybrid_Series" title="Vybrid Series">Vybrid</a> VF6 (one Cortex-A5 + one Cortex-M4F)</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/I.MX" title="I.MX">i.MX 6</a> SoloX (one Cortex-A9 + one Cortex-M4F)</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/I.MX" title="I.MX">i.MX 7</a> Solo/Dual (one or two Cortex-A7 + one Cortex-M4F)</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/I.MX#i.MX_8_series" title="I.MX">i.MX 8</a> (two <a href="/wiki/Cortex-A72" class="mw-redirect" title="Cortex-A72">Cortex-A72</a> + four <a href="/wiki/Cortex-A53" class="mw-redirect" title="Cortex-A53">Cortex-A53</a> + two Cortex-M4F)</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/I.MX#i.MX_8_series" title="I.MX">i.MX 8M</a> and 8M Mini (four <a href="/wiki/Cortex-A53" class="mw-redirect" title="Cortex-A53">Cortex-A53</a> + one Cortex-M4F)</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>) <a href="/wiki/I.MX#i.MX_8_series" title="I.MX">i.MX 8X</a> (four <a href="/wiki/Cortex-A35" class="mw-redirect" title="Cortex-A35">Cortex-A35</a> + one Cortex-M4F)</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> STM32MP1 (one or two <a href="/wiki/Cortex-A7" class="mw-redirect" title="Cortex-A7">Cortex-A7</a> + one Cortex-M4)</li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> <a href="/wiki/OMAP#OMAP_5" title="OMAP">OMAP 5</a> (two <a href="/wiki/ARM_Cortex-A15" title="ARM Cortex-A15">Cortex-A15s</a> + two Cortex-M4)</li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a> <a href="/wiki/Sitara_ARM_Processor" class="mw-redirect" title="Sitara ARM Processor">Sitara AM5700</a> (one or two <a href="/wiki/ARM_Cortex-A15" title="ARM Cortex-A15">Cortex-A15s</a> + two Cortex-M4s as image processing units + two Cortex-M4s as general purpose units)</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M7">Cortex-M7</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=16" title="Edit section: Cortex-M7"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M7</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv7E-M</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (SP & DP)</td></tr></tbody></table> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Arduino_Giga_R1_WiFi.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/99/Arduino_Giga_R1_WiFi.png/302px-Arduino_Giga_R1_WiFi.png" decoding="async" width="302" height="226" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/99/Arduino_Giga_R1_WiFi.png/453px-Arduino_Giga_R1_WiFi.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/99/Arduino_Giga_R1_WiFi.png/604px-Arduino_Giga_R1_WiFi.png 2x" data-file-width="643" data-file-height="482" /></a><figcaption>Arduino GIGA R1 WiFi board with (dual core ARM Cortex-M7 + ARM Cortex-M4) <a rel="nofollow" class="external text" href="https://www.st.com/en/microcontrollers-microprocessors/stm32h747xi.html">STM32H747XIH6</a> microcontroller</figcaption></figure> <p>The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4.<sup id="cite_ref-M7-Home_7-1" class="reference"><a href="#cite_note-M7-Home-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> It features a 6-stage <a href="/wiki/Superscalar" class="mw-redirect" title="Superscalar">superscalar</a> pipeline with <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction</a> and an optional floating-point unit capable of single-precision and optionally <a href="/wiki/Double-precision_floating-point_format" title="Double-precision floating-point format">double-precision</a> operations.<sup id="cite_ref-M7-Home_7-2" class="reference"><a href="#cite_note-M7-Home-7"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-M7-PressRelease_38-0" class="reference"><a href="#cite_note-M7-PressRelease-38"><span class="cite-bracket">[</span>38<span class="cite-bracket">]</span></a></sup> The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7. </p><p>Key features of the Cortex-M7 core are:<sup id="cite_ref-M7-TRM_22-3" class="reference"><a href="#cite_note-M7-TRM-22"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv7E-M architecture.</li> <li>6-stage <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a> with <a href="/wiki/Branch_predictor" title="Branch predictor">branch speculation</a>. Second-longest of all ARM Cortex-M cores, with the first being Cortex-M85.</li> <li>Instruction sets: <ul><li>Thumb-1 (entire).</li> <li>Thumb-2 (entire).</li> <li>32-bit hardware integer multiply with 32-bit or 64-bit result, signed or unsigned, add or subtract after the multiply. 32-bit Multiply and MAC are 1 cycle.</li> <li>32-bit hardware integer divide (2–12 cycles).</li> <li><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturation arithmetic</a> support.</li> <li>DSP extension: Single cycle 16/32-bit <a href="/wiki/Multiply%E2%80%93accumulate_operation" title="Multiply–accumulate operation">MAC</a>, single cycle dual 16-bit MAC, 8/16-bit <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> arithmetic.</li></ul></li> <li>1 to 240 <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>, plus <a href="/wiki/Non-maskable_interrupt" title="Non-maskable interrupt">NMI</a>.</li> <li>12 cycle interrupt latency.</li> <li>Integrated sleep modes.</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Optional floating-point unit (FPU): (single precision) or (single and double-precision), both IEEE-754-2008 compliant. It is called the FPv5 extension.</li> <li>Optional <a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a>: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional <a href="/wiki/ECC_memory" title="ECC memory">ECC</a>.</li> <li>Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.</li> <li>Optional Memory Protection Unit (MPU): 8 or 16 regions.</li> <li>Optional Embedded Trace Macrocell (ETM): instruction-only, or instruction and data.</li> <li>Optional Retention Mode (with Arm Power Management Kit) for Sleep Modes.</li> <li>Optional <a href="/wiki/Dual_modular_redundancy" title="Dual modular redundancy">dual-redundant</a> <a href="/wiki/Lockstep_(computing)" title="Lockstep (computing)">lock-step</a> operation.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_6">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=17" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M7 core: </p> <ul><li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> E7, S7, V7</li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> (<a href="/wiki/Freescale_Semiconductor" title="Freescale Semiconductor">Freescale</a>) Kinetis KV5x, i.MX RT, S32K3xx</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32" title="STM32">STM32</a> F7, H7</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M23">Cortex-M23</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=18" title="Edit section: Cortex-M23"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M23</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8-M Baseline</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1 (most)</a>,<br /><a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2 (some)</a>,<br />Divide, <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a></td></tr></tbody></table> <p>The Cortex-M23 core was announced in October 2016<sup id="cite_ref-Cortex-M23-M33-PR_39-0" class="reference"><a href="#cite_note-Cortex-M23-M33-PR-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> and based on the <a href="/wiki/ARM_architecture#Armv8-R_and_Armv8-M" class="mw-redirect" title="ARM architecture">ARMv8-M architecture</a> that was previously announced in November 2015.<sup id="cite_ref-ARMv8-M-PR_40-0" class="reference"><a href="#cite_note-ARMv8-M-PR-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a>.<sup id="cite_ref-M23-Home_8-1" class="reference"><a href="#cite_note-M23-Home-8"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M23 core are:<sup id="cite_ref-M23-TRM_23-2" class="reference"><a href="#cite_note-M23-TRM-23"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Cortex-M23-M33-PR_39-1" class="reference"><a href="#cite_note-Cortex-M23-M33-PR-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv8-M Baseline architecture.<sup id="cite_ref-ARMv8-M-Manual_30-8" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>2-stage pipeline. (similar to Cortex-M0+)</li> <li><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security instructions.</li> <li>32-bit hardware integer divide (17 or 34 cycles).(slower than divide in all other cores)</li> <li>Stack limit boundaries. (available only with SAU option)</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Hardware integer multiply speed: 1 or 32 cycles.</li> <li>Hardware integer divide speed: 17 or 34 cycles maximum. Depending on divisor, instruction may complete in fewer cycles.</li> <li>Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.</li> <li>Optional Security Attribution Unit (SAU): 0, 4, 8 regions.</li> <li>Single-cycle I/O port (available in M0+/M23).</li> <li>Micro Trace Buffer (MTB)</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_7">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=19" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M23 core: </p> <ul><li><a href="/wiki/GigaDevice" title="GigaDevice">GigaDevice</a> GD32E2xx</li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip</a> SAM L10, L11, and PIC 32CM-LE 32CM-LS</li> <li><a href="/wiki/Nuvoton" title="Nuvoton">Nuvoton</a> M23xx family, M2xx family, NUC1262, M2L31</li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> S1JA, RA2A1, RA2L1, RA2E1, RA2E2</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M33">Cortex-M33</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=20" title="Edit section: Cortex-M33"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M33</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8-M Mainline</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (SP),<br /><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a>, Co-processor</td></tr></tbody></table> <p>The Cortex-M33 core was announced in October 2016<sup id="cite_ref-Cortex-M23-M33-PR_39-2" class="reference"><a href="#cite_note-Cortex-M23-M33-PR-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> and based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARMv8-M architecture</a> that was previously announced in November 2015.<sup id="cite_ref-ARMv8-M-PR_40-1" class="reference"><a href="#cite_note-ARMv8-M-PR-40"><span class="cite-bracket">[</span>40<span class="cite-bracket">]</span></a></sup> Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Cortex-M23, and also has a 3-stage <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">instruction pipeline</a>.<sup id="cite_ref-M33-Home_9-1" class="reference"><a href="#cite_note-M33-Home-9"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M33 core are:<sup id="cite_ref-M33-TRM_24-2" class="reference"><a href="#cite_note-M33-TRM-24"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-Cortex-M23-M33-PR_39-3" class="reference"><a href="#cite_note-Cortex-M23-M33-PR-39"><span class="cite-bracket">[</span>39<span class="cite-bracket">]</span></a></sup> </p> <ul><li>ARMv8-M Mainline architecture.<sup id="cite_ref-ARMv8-M-Manual_30-9" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>3-stage pipeline.</li> <li><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security instructions.</li> <li>32-bit hardware integer divide (11 cycles maximum).</li> <li>Stack limit boundaries. (available only with SAU option)</li></ul> <p><b>Silicon options:</b> </p> <ul><li>Optional Floating-Point Unit (FPU): single-precision only <a href="/wiki/IEEE-754" class="mw-redirect" title="IEEE-754">IEEE-754</a> compliant. It is called the FPv5 extension.</li> <li>Optional Memory Protection Unit (MPU): 0, 4, 8, 12, 16 regions.</li> <li>Optional Security Attribution Unit (SAU): 0, 4, 8 regions.</li> <li>Micro Trace Buffer (MTB)</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_8">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=21" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M33 core: </p> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> ADUCM4</li> <li><a href="/wiki/Dialog_Semiconductor" title="Dialog Semiconductor">Dialog</a> DA1469x</li> <li><a href="/wiki/GigaDevice" title="GigaDevice">GigaDevice</a> GD32E5, GD32W5</li> <li><a href="/wiki/Nordic_Semiconductor" title="Nordic Semiconductor">Nordic</a> nRF91, nRF5340, nRF54, nRF54H20<sup id="cite_ref-41" class="reference"><a href="#cite_note-41"><span class="cite-bracket">[</span>41<span class="cite-bracket">]</span></a></sup></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a> LPC5500, i.MX RT600, MCX N94x/54x (dual core)</li> <li><a href="/wiki/ON_Semiconductor" class="mw-redirect" title="ON Semiconductor">ON</a> RSL15</li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> RA4, RA6</li> <li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">ST</a> <a href="/wiki/STM32" title="STM32">STM32</a> H5, L5, U5, WBA</li> <li><a href="/wiki/Silicon_Labs" title="Silicon Labs">Silicon Labs</a> Wireless Gecko Series 2</li> <li><a href="/wiki/Raspberry_Pi" title="Raspberry Pi">Raspberry Pi</a> <a href="/wiki/RP2350" title="RP2350">RP2350</a></li></ul> <p>The following chips have a Cortex-M33 or M33F as a secondary core: </p> <ul><li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a> <a href="/wiki/PSoC" class="mw-redirect" title="PSoC">PSoC</a> Edge</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M35P">Cortex-M35P</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=22" title="Edit section: Cortex-M35P"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M35P</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8-M Mainline</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (SP),<br /><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a>, Co-processor</td></tr></tbody></table> <p>The Cortex-M35P core was announced in May 2018 and based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">Armv8-M architecture</a>. It is conceptually a Cortex-M33 core with a new instruction cache, plus new tamper-resistant hardware concepts borrowed from the ARM SecurCore family, and configurable parity and ECC features.<sup id="cite_ref-M35P-Home_10-2" class="reference"><a href="#cite_note-M35P-Home-10"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p>Currently, information about the Cortex-M35P is limited, because its <i>Technical Reference Manual</i> and <i>Generic User Guide</i> haven't been released yet. </p> <div class="mw-heading mw-heading3"><h3 id="Chips_9">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=23" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex-M35P core: </p> <ul><li><a href="/wiki/STMicroelectronics" title="STMicroelectronics">STMicroelectronics</a> ST33K</li></ul> <div style="clear:both;" class=""></div> <div class="mw-heading mw-heading2"><h2 id="Cortex-M52">Cortex-M52</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=24" title="Edit section: Cortex-M52"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M52</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8.1-M Mainline Helium</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (VFPv5),<br /><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a>, Coprocessor, MVE</td></tr></tbody></table> <p>The Cortex-M52 core was announced in November 2023 and based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">Armv8.1-M architecture</a>. Conceptually, it can be seen as a cross between the Cortex-M33 and the Cortex-M55. Key differences are that its Helium co-processor is single beat (the M55 is dual beat), and it has a 32-bit main bus similar to the M33 to ease transition of applications. It has a 4 stage instruction pipeline.<sup id="cite_ref-M52-Home_11-1" class="reference"><a href="#cite_note-M52-Home-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M52 core include: </p> <ul><li>ARMv8.1-M Mainline/Helium architecture.<sup id="cite_ref-ARMv8-M-Manual_30-10" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>4-stage pipeline.</li> <li>Stack limit boundaries (available only with SAU option).</li> <li>32-bit main bus (AHB or AXI)<sup id="cite_ref-M52-Home_11-2" class="reference"><a href="#cite_note-M52-Home-11"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup></li></ul> <p><b>Silicon options:</b> </p> <ul><li>Helium (M-Profile Vector Extension, MVE)</li> <li>Pointer Authentication and Branch Target Identification Extension</li> <li>Single-Precision and Double-Precision floating-point</li> <li>Digital Signal Processing (DSP) extension support</li> <li><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security extension support</li> <li>Safety and reliability (RAS) support</li> <li>Coprocessor support</li> <li>Secure and Non-secure MPU with 0, 4, 8, 12, or 16 regions</li> <li>SAU with 0, 4, or 8 regions</li> <li>Instruction cache with size of up to 64 KB</li> <li>Data cache with size of up to 64 KB</li> <li>ECC on caches and TCMs</li> <li>1–480 interrupts</li> <li>3–8 exception priority bits</li> <li>Internal and external WIC options, optional CTI, ITM, and DWT</li> <li>ARM Custom Instructions</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_10">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=25" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The following microcontrollers are based on the Cortex M52 core </p> <ul><li>Geehy Semiconductor G32R5<sup id="cite_ref-42" class="reference"><a href="#cite_note-42"><span class="cite-bracket">[</span>42<span class="cite-bracket">]</span></a></sup></li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M55">Cortex-M55</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=26" title="Edit section: Cortex-M55"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M55</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8.1-M Mainline Helium</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (VFPv5),<br /><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a>, Coprocessor, MVE</td></tr></tbody></table> <p>The Cortex-M55 core was announced in February 2020 and based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">Armv8.1-M architecture</a>. It has a 4 or 5 stage instruction pipeline.<sup id="cite_ref-M55-Home_12-1" class="reference"><a href="#cite_note-M55-Home-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>Key features of the Cortex-M55 core include: </p> <ul><li>ARMv8.1-M Mainline/Helium architecture.<sup id="cite_ref-ARMv8-M-Manual_30-11" class="reference"><a href="#cite_note-ARMv8-M-Manual-30"><span class="cite-bracket">[</span>30<span class="cite-bracket">]</span></a></sup></li> <li>4-stage pipeline.</li> <li>Stack limit boundaries (available only with SAU option).</li> <li>64-bit AXI main bus<sup id="cite_ref-M55-Home_12-2" class="reference"><a href="#cite_note-M55-Home-12"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup></li></ul> <p><b>Silicon options:</b> </p> <ul><li>Helium (M-Profile Vector Extension, MVE)</li> <li>Single-Precision and Double-Precision floating-point</li> <li>Digital Signal Processing (DSP) extension support</li> <li><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> security extension support</li> <li>Safety and reliability (RAS) support</li> <li>Coprocessor support</li> <li>Secure and Non-secure MPU with 0, 4, 8, 12, or 16 regions</li> <li>SAU with 0, 4, or 8 regions</li> <li>Instruction cache with size of 4 KB, 8 KB, 16 KB, 32 KB, 64 KB</li> <li>Data cache with size of 4 KB, 8 KB, 16 KB, 32 KB, 64 KB</li> <li>ECC on caches and TCMs</li> <li>1–480 interrupts</li> <li>3–8 exception priority bits</li> <li>Internal and external WIC options, optional CTI, ITM, and DWT</li> <li>ARM Custom Instructions</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_11">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=27" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="https://alifsemi.com/products/ensemble/">Alif Semiconductor</a> Ensemble MCU families offer single or dual Cortex-M55 cores, each paired with Ethos-U55 NPUs</li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a> <a href="/wiki/PSoC" class="mw-redirect" title="PSoC">PSoC</a> Edge</li></ul> <div class="mw-heading mw-heading2"><h2 id="Cortex-M85">Cortex-M85</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=28" title="Edit section: Cortex-M85"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1257001546"><table class="infobox"><caption class="infobox-title">Cortex-M85</caption><tbody><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Microarchitecture" title="Microarchitecture">Microarchitecture</a></th><td class="infobox-data">ARMv8.1-M Mainline Helium</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/ARM_architecture#Thumb" class="mw-redirect" title="ARM architecture">Thumb-1</a>, <a href="/wiki/ARM_architecture#Thumb-2" class="mw-redirect" title="ARM architecture">Thumb-2</a>,<br /><a href="/wiki/Saturation_arithmetic" title="Saturation arithmetic">Saturated</a>, <a href="/wiki/ARM_architecture#DSP_enhancement_instructions" class="mw-redirect" title="ARM architecture">DSP</a>,<br />Divide, <a href="/wiki/ARM_architecture#Floating-point_(VFP)" class="mw-redirect" title="ARM architecture">FPU</a> (VFPv5),<br /><a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a>, Coprocessor, MVE</td></tr></tbody></table> <p>The Cortex-M85 core was announced in April 2022 and based on the <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">Armv8.1-M architecture</a>. It has a 7-stage instruction pipeline.<sup id="cite_ref-M85-Home_13-1" class="reference"><a href="#cite_note-M85-Home-13"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> </p><p><b>Silicon options:</b> </p> <ul><li>Optional <a href="/wiki/CPU_cache" title="CPU cache">CPU cache</a>: 0 to 64 KB instruction-cache, 0 to 64 KB data-cache, each with optional <a href="/wiki/ECC_memory" title="ECC memory">ECC</a>.</li> <li>Optional Tightly-Coupled Memory (TCM): 0 to 16 MB instruction-TCM, 0 to 16 MB data-TCM, each with optional ECC.</li> <li>Optional Memory Protection Unit (MPU): 16 regions. Can have separate ones for secure and non-secure mode if <a href="/wiki/TrustZone" class="mw-redirect" title="TrustZone">TrustZone</a> is implemented.</li> <li>Up to 480 interrupts and NMI</li> <li>3–8 exception priority bits</li> <li>Optional <a href="/wiki/Dual_modular_redundancy" title="Dual modular redundancy">dual-redundant</a> <a href="/wiki/Lockstep_(computing)" title="Lockstep (computing)">lock-step</a> operation.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Chips_12">Chips</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=29" title="Edit section: Chips"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> RA8</li></ul> <div style="clear:both;" class=""></div> <div class="mw-heading mw-heading2"><h2 id="Development_tools">Development tools</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=30" title="Edit section: Development tools"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236090951"><div role="note" class="hatnote navigation-not-searchable">Main article: <a href="/wiki/List_of_ARM_Cortex-M_development_tools" title="List of ARM Cortex-M development tools">List of ARM Cortex-M development tools</a></div> <div class="mw-heading mw-heading2"><h2 id="Documentation">Documentation</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=31" title="Edit section: Documentation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The documentation for ARM chips is extensive. In the past, 8-bit microcontroller documentation would typically fit in a single document, but as microcontrollers have evolved, so has everything required to support them. A documentation package for ARM chips typically consists of a collection of documents from the IC manufacturer as well as the CPU core vendor (<a href="/wiki/Arm_(company)" class="mw-redirect" title="Arm (company)">ARM Limited</a>). </p><p>A typical top-down documentation tree is: </p> <dl><dt>Documentation tree (top to bottom)</dt></dl> <ol><li>IC manufacturer website.</li> <li>IC manufacturer marketing slides.</li> <li>IC manufacturer datasheet for the exact physical chip.</li> <li>IC manufacturer reference manual that describes common peripherals and aspects of a physical chip family.</li> <li>ARM core website.</li> <li>ARM core generic user guide.</li> <li>ARM core technical reference manual.</li> <li>ARM architecture reference manual.</li></ol> <p>IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See <a href="#External_links">External links</a> section for links to official Arm documents. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=32" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1259569809">.mw-parser-output .portalbox{padding:0;margin:0.5em 0;display:table;box-sizing:border-box;max-width:175px;list-style:none}.mw-parser-output .portalborder{border:1px solid var(--border-color-base,#a2a9b1);padding:0.1em;background:var(--background-color-neutral-subtle,#f8f9fa)}.mw-parser-output .portalbox-entry{display:table-row;font-size:85%;line-height:110%;height:1.9em;font-style:italic;font-weight:bold}.mw-parser-output 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class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=33" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.arm.com/products/processors/cortex-m">ARM Cortex-M website; ARM Limited.</a></span> </li> <li id="cite_note-M0-Home-2"><span class="mw-cite-backlink">^ <a href="#cite_ref-M0-Home_2-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M0-Home_2-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M0">"Cortex-M0 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M0+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M0&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M0+-Home-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-M0+-Home_3-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M0+">"Cortex-M0+ Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M0%2B+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M0%2B&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M1-Home-4"><span class="mw-cite-backlink">^ <a href="#cite_ref-M1-Home_4-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M1-Home_4-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M1">"Cortex-M1 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M1+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M1&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M3-Home-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-M3-Home_5-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M3">"Cortex-M3 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M3+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M3&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M4-Home-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-M4-Home_6-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M4">"Cortex-M4 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M4+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M4&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M7-Home-7"><span class="mw-cite-backlink">^ <a href="#cite_ref-M7-Home_7-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M7-Home_7-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M7-Home_7-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M7">"Cortex-M7 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M7+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M7&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M23-Home-8"><span class="mw-cite-backlink">^ <a href="#cite_ref-M23-Home_8-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M23-Home_8-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M23">"Cortex-M23 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M23+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M23&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M33-Home-9"><span class="mw-cite-backlink">^ <a href="#cite_ref-M33-Home_9-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M33-Home_9-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M33">"Cortex-M33 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M33+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M33&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M35P-Home-10"><span class="mw-cite-backlink">^ <a href="#cite_ref-M35P-Home_10-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M35P-Home_10-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M35P-Home_10-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M35P">"Cortex-M35P Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M35P+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M35P&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M52-Home-11"><span class="mw-cite-backlink">^ <a href="#cite_ref-M52-Home_11-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M52-Home_11-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M52-Home_11-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M52">"Cortex-M52 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M52+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M52&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M55-Home-12"><span class="mw-cite-backlink">^ <a href="#cite_ref-M55-Home_12-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M55-Home_12-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M55-Home_12-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M55">"Cortex-M55 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M55+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M55&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M85-Home-13"><span class="mw-cite-backlink">^ <a href="#cite_ref-M85-Home_13-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M85-Home_13-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M85">"Cortex-M85 Home"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M85+Home&rft_id=https%3A%2F%2Fdeveloper.arm.com%2FProcessors%2FCortex-M85&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-ARMv6-M-Manual-14"><span class="mw-cite-backlink">^ <a href="#cite_ref-ARMv6-M-Manual_14-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-7"><sup><i><b>h</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-8"><sup><i><b>i</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-9"><sup><i><b>j</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-10"><sup><i><b>k</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-11"><sup><i><b>l</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-12"><sup><i><b>m</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-13"><sup><i><b>n</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-14"><sup><i><b>o</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-15"><sup><i><b>p</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-16"><sup><i><b>q</b></i></sup></a> <a href="#cite_ref-ARMv6-M-Manual_14-17"><sup><i><b>r</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0419/latest/">"ARMv6-M Architecture Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=ARMv6-M+Architecture+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fddi0419%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-ARMv7-M-Manual-15"><span class="mw-cite-backlink">^ <a href="#cite_ref-ARMv7-M-Manual_15-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-3"><sup><i><b>d</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-4"><sup><i><b>e</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-5"><sup><i><b>f</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-6"><sup><i><b>g</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-7"><sup><i><b>h</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-8"><sup><i><b>i</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-9"><sup><i><b>j</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-10"><sup><i><b>k</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-11"><sup><i><b>l</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-12"><sup><i><b>m</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-13"><sup><i><b>n</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-14"><sup><i><b>o</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-15"><sup><i><b>p</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-16"><sup><i><b>q</b></i></sup></a> <a href="#cite_ref-ARMv7-M-Manual_15-17"><sup><i><b>r</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0403/latest/">"ARMv7-M Architecture Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=ARMv7-M+Architecture+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fddi0403%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-AppNote179-16"><span class="mw-cite-backlink">^ <a href="#cite_ref-AppNote179_16-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-AppNote179_16-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-AppNote179_16-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-AppNote179_16-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://infocenter.arm.com/help/topic/com.arm.doc.dai0179b/AppsNote179.pdf">Cortex-M3 Embedded Software Development; App Note 179; ARM Limited.</a></span> </li> <li id="cite_note-M0-TRM-17"><span class="mw-cite-backlink">^ <a href="#cite_ref-M0-TRM_17-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M0-TRM_17-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M0-TRM_17-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0432/latest/">"Cortex-M0 Technical Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M0+Technical+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fddi0432%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M0+-TRM-18"><span class="mw-cite-backlink">^ <a href="#cite_ref-M0+-TRM_18-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M0+-TRM_18-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M0+-TRM_18-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-M0+-TRM_18-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0484/latest/">"Cortex-M0+ Technical Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M0%2B+Technical+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fddi0484%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M1-TRM-19"><span class="mw-cite-backlink">^ <a href="#cite_ref-M1-TRM_19-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M1-TRM_19-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M1-TRM_19-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0413/latest/">"Cortex-M1 Technical Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M1+Technical+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2Fddi0413%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M3-TRM-20"><span class="mw-cite-backlink">^ <a href="#cite_ref-M3-TRM_20-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M3-TRM_20-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-M3-TRM_20-2"><sup><i><b>c</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100165/latest/">"Cortex-M3 Technical Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M3+Technical+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2F100165%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M4-TRM-21"><span class="mw-cite-backlink">^ <a href="#cite_ref-M4-TRM_21-0"><sup><i><b>a</b></i></sup></a> <a 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class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100230/latest/">"Cortex-M33 Technical Reference Manual"</a>. <i>ARM Limited</i>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=ARM+Limited&rft.atitle=Cortex-M33+Technical+Reference+Manual&rft_id=https%3A%2F%2Fdeveloper.arm.com%2Fdocumentation%2F100230%2Flatest%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-M52-TRM-25"><span class="mw-cite-backlink">^ <a href="#cite_ref-M52-TRM_25-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-M52-TRM_25-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a 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Retrieved <span class="nowrap">2015-06-15</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Samsung+Exynos+7420+Deep+Dive+-+Inside+a+Modern+14nm+SoC&rft.pub=AnandTech&rft_id=https%3A%2F%2Fwww.anandtech.com%2Fshow%2F9330%2Fexynos-7420-deep-dive%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-37"><span class="mw-cite-backlink"><b><a href="#cite_ref-37">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://silver.arm.com/browse/AT426">Cortex-M3 DesignStart FPGA XilinxEdition</a></span> </li> <li id="cite_note-M7-PressRelease-38"><span class="mw-cite-backlink"><b><a href="#cite_ref-M7-PressRelease_38-0">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://arm.com/about/newsroom/arm-supercharges-mcu-market-with-high-performance-cortex-m7-processor.php">"ARM Supercharges MCU Market with High Performance Cortex-M7 Processor"</a>. <i>ARM Limited</i> (Press release). September 24, 2014.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=ARM+Supercharges+MCU+Market+with+High+Performance+Cortex-M7+Processor&rft.date=2014-09-24&rft_id=https%3A%2F%2Farm.com%2Fabout%2Fnewsroom%2Farm-supercharges-mcu-market-with-high-performance-cortex-m7-processor.php&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-Cortex-M23-M33-PR-39"><span class="mw-cite-backlink">^ <a href="#cite_ref-Cortex-M23-M33-PR_39-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-Cortex-M23-M33-PR_39-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-Cortex-M23-M33-PR_39-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-Cortex-M23-M33-PR_39-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://www.arm.com/files/pdf/cortex_m23_and_cortex_m33.pdf">New ARM Cortex-M processors offer the next industry standard for secure IoT; ARM Limited; October 25, 2016.</a></span> </li> <li id="cite_note-ARMv8-M-PR-40"><span class="mw-cite-backlink">^ <a href="#cite_ref-ARMv8-M-PR_40-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-ARMv8-M-PR_40-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://www.arm.com/about/newsroom/armv8-m-architecture-simplifies-security-for-smart-embedded-devices.php">ARMv8-M Architecture Simplifies Security for Smart Embedded Devices; ARM Limited; November 10, 2015.</a></span> </li> <li id="cite_note-41"><span class="mw-cite-backlink"><b><a href="#cite_ref-41">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.nordicsemi.com/Products/nRF54H20">"nRF54H20 - Nordic Semiconductor"</a>. <i>www.nordicsemi.com</i><span class="reference-accessdate">. Retrieved <span class="nowrap">2024-10-30</span></span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.nordicsemi.com&rft.atitle=nRF54H20+-+Nordic+Semiconductor&rft_id=https%3A%2F%2Fwww.nordicsemi.com%2FProducts%2FnRF54H20&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> <li id="cite_note-42"><span class="mw-cite-backlink"><b><a href="#cite_ref-42">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://geehy.com/about/news_detail/341">"The World's First Dual-Core Real-Time Control MCU Featuring Cortex-M52 Processor Unveiled at Electronica China 2024"</a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+World%27s+First+Dual-Core+Real-Time+Control+MCU+Featuring+Cortex-M52+Processor+Unveiled+at+Electronica+China+2024&rft_id=https%3A%2F%2Fgeehy.com%2Fabout%2Fnews_detail%2F341&rfr_id=info%3Asid%2Fen.wikipedia.org%3AARM+Cortex-M" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=34" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><i>Designer's Guide to the Cortex-M Processor Family</i>; 3rd Ed; Trevor Martin; 648 pages; 2022; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0323854948" title="Special:BookSources/978-0323854948">978-0323854948</a>.</li> <li><i>Definitive Guide to the ARM Cortex-M0 and Cortex-M0+ Processors</i>; 2nd Ed; Joseph Yiu; 784 pages; 2015; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0128032770" title="Special:BookSources/978-0128032770">978-0128032770</a>.</li> <li><i>Definitive Guide to the ARM Cortex-M3 and Cortex-M4 Processors</i>; 3rd Ed; Joseph Yiu; 864 pages; 2013; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0124080829" title="Special:BookSources/978-0124080829">978-0124080829</a>.</li> <li><i>Definitive Guide to the ARM Cortex-M23 and Cortex-M33 Processors</i>; 1st Ed; Joseph Yiu; 928 pages; 2020; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0128207352" title="Special:BookSources/978-0128207352">978-0128207352</a>.</li> <li><i>Microcontrollers with C: Cortex-M and Beyond</i>; 1st Ed; Klaus Elk; 227 pages; 2023; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/979-8862003437" title="Special:BookSources/979-8862003437">979-8862003437</a>.</li> <li><i>Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language and C</i>; 4th Ed; Yifeng Zhu; 730 pages; 2023; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0982692677" title="Special:BookSources/978-0982692677">978-0982692677</a>.</li> <li><i>ARM Assembly for Embedded Applications</i>; 5th Ed; Daniel Lewis; 379 pages; 2019; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1092542234" title="Special:BookSources/978-1092542234">978-1092542234</a>.</li> <li><i>Assembly Language Programming: ARM Cortex-M3</i>; 1st Ed; Vincent Mahout; 256 pages; 2012; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1848213296" title="Special:BookSources/978-1848213296">978-1848213296</a>.</li> <li><i>Digital Signal Processing and Applications Using the ARM Cortex-M4</i>; 1st Ed; Donald Reay; 320 pages; 2015; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1118859049" title="Special:BookSources/978-1118859049">978-1118859049</a>.</li> <li><i>Hands-On RTOS with Microcontrollers</i>; 1st Ed; Brian Amos; 496 pages; 2020; <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-1838826734" title="Special:BookSources/978-1838826734">978-1838826734</a>.</li></ul> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=ARM_Cortex-M&action=edit&section=35" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output .side-box-abovebelow,.mw-parser-output .side-box-text{padding:0.25em 0.9em}.mw-parser-output .side-box-image{padding:2px 0 2px 0.9em;text-align:center}.mw-parser-output .side-box-imageright{padding:2px 0.9em 2px 0;text-align:center}@media(min-width:500px){.mw-parser-output .side-box-flex{display:flex;align-items:center}.mw-parser-output .side-box-text{flex:1;min-width:0}}@media(min-width:720px){.mw-parser-output .side-box{width:238px}.mw-parser-output .side-box-right{clear:right;float:right;margin-left:1em}.mw-parser-output .side-box-left{margin-right:1em}}</style><style data-mw-deduplicate="TemplateStyles:r1237033735">@media print{body.ns-0 .mw-parser-output .sistersitebox{display:none!important}}@media screen{html.skin-theme-clientpref-night .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .sistersitebox img[src*="Wiktionary-logo-en-v2.svg"]{background-color:white}}</style><div class="side-box side-box-right plainlinks sistersitebox"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style> <div class="side-box-flex"> <div class="side-box-image"><span class="noviewer" typeof="mw:File"><span><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/30px-Commons-logo.svg.png" decoding="async" width="30" height="40" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/45px-Commons-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/4/4a/Commons-logo.svg/59px-Commons-logo.svg.png 2x" data-file-width="1024" data-file-height="1376" /></span></span></div> <div class="side-box-text plainlist">Wikimedia Commons has media related to <span style="font-weight: bold; font-style: italic;"><a href="https://commons.wikimedia.org/wiki/Category:ARM_Cortex-M" class="extiw" title="commons:Category:ARM Cortex-M">ARM Cortex-M</a></span>.</div></div> </div> <dl><dt>ARM Cortex-M official documents</dt></dl> <ul><li><a rel="nofollow" class="external text" href="https://www.arm.com/products/silicon-ip-cpu?families=cortex-m&showall=true">ARM Cortex-M official website</a></li> <li><a rel="nofollow" class="external text" href="https://community.arm.com/cfs-file/__key/telligent-evolution-components-attachments/01-2142-00-00-00-00-52-96/White-Paper-_2D00_-Cortex_2D00_M-for-Beginners-_2D00_-2016-_2800_final-v3_2900_.pdf">Cortex-M for Beginners</a> arm.com</li> <li><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ecm0359818/latest/">ARMv8-M Security Extensions</a> arm.com</li> <li><a rel="nofollow" class="external text" href="https://arm-software.github.io/CMSIS_5/Core/html/index.html">Cortex Microcontroller Software Interface Standard (CMSIS)</a> arm.com</li></ul> <dl><dd><table class="wikitable"> <tbody><tr> <th>ARM<br />core</th> <th>Bit<br />width</th> <th>ARM<br />website</th> <th>ARM generic<br />user guide</th> <th>ARM technical<br />reference manual</th> <th>ARM architecture<br />reference manual </th></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M0">Cortex-M0</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M0">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0497/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0432/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0419/latest/">ARMv6-M</a> </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M0+">Cortex-M0+</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M0-Plus">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0662/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0484/latest/">Link</a></td> <td style="text-align: center;">ARMv6-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M1">Cortex-M1</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M1">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0395/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0413/latest/">Link</a></td> <td style="text-align: center;">ARMv6-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M3">Cortex-M3</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M3">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0552/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100165/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0403/latest/">ARMv7-M</a> </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M4">Cortex-M4</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M4">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0553/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100166/latest/">Link</a></td> <td style="text-align: center;">ARMv7E-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M7">Cortex-M7</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M7">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui0646/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0489/latest/">Link</a></td> <td style="text-align: center;">ARMv7E-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M23">Cortex-M23</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M23">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dui1095/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0550/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/ddi0553/latest/">ARMv8-M</a> </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M33">Cortex-M33</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M33">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100235/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/100230/latest/">Link</a></td> <td style="text-align: center;">ARMv8-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M35P">Cortex-M35P</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M35P">Link</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><a href="/wiki/N/A" title="N/A">N/A</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><a href="/wiki/N/A" title="N/A">N/A</a></td> <td style="text-align: center;">ARMv8-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M52">Cortex-M52</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M52">Link</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"><a href="/wiki/N/A" title="N/A">N/A</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/102776/latest/">Link</a></td> <td style="text-align: center;">ARMv8.1-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M55">Cortex-M55</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M55">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/101273/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/101051/latest/">Link</a></td> <td style="text-align: center;">ARMv8.1-M </td></tr> <tr> <td style="background: LightCyan; text-align: center;"><a href="#Cortex-M85">Cortex-M85</a></td> <td style="text-align: center;">32</td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/Processors/Cortex-M85">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/101928/latest/">Link</a></td> <td style="text-align: center;"><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/101924/latest/">Link</a></td> <td style="text-align: center;">ARMv8.1-M </td></tr></tbody></table></dd></dl> <dl><dt>Quick reference cards</dt></dl> <ul><li>Instructions: Thumb-1 (<a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/qrc0006/latest/">1</a>), ARM and Thumb-2 (<a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/qrc0001/latest/">2</a>), Vector Floating-Point (<a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/qrc0007/latest/">3</a>) arm.com</li> <li>Opcodes: Thumb-1 (<a rel="nofollow" class="external text" href="https://re-eject.gbadev.org/files/ThumbRefV2-beta.pdf">1</a>, <a rel="nofollow" class="external text" href="http://www.mechcore.net/files/docs/ThumbRefV2-beta.pdf">2</a>), ARM (<a rel="nofollow" class="external text" href="https://re-eject.gbadev.org/files/armref.pdf">3</a>, <a rel="nofollow" class="external text" href="http://www.mechcore.net/files/docs/armref.pdf">4</a>), GNU Assembler Directives (<a rel="nofollow" class="external text" href="https://re-eject.gbadev.org/files/GasARMRef.pdf">5</a>).</li></ul> <dl><dt>Migrating</dt></dl> <ul><li><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dai0237/latest/">Migrating from 8051 to Cortex-M3</a> – arm.com</li> <li><a rel="nofollow" class="external text" href="https://developer.arm.com/documentation/dai0234/latest/">Migrating from PIC to Cortex-M3</a> – arm.com</li> <li><a rel="nofollow" class="external text" href="https://web.archive.org/web/20210308164831/https://www.arm.com/zh/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf">Migrating from ARM7TDMI to Cortex-M3</a> – arm.com</li> <li><a rel="nofollow" class="external text" href="https://www.keil.com/appnotes/files/apnt_270.pdf">Migrating from Cortex-M4 to Cortex-M7</a> – keil.com</li></ul> <dl><dt>Other</dt></dl> <ul><li><a rel="nofollow" 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class="navbox-group" style="width:1%">Embedded<br /><a href="/wiki/Microcontroller" title="Microcontroller">microcontrollers</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M0" class="mw-redirect" title="ARM Cortex-M0">Cortex-M0</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Cypress <a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a> 4000, 4100, 4100M, 4200, 4200DS, 4200L, 4200M</li> <li>Infineon <a href="/wiki/Infineon_XMC" title="Infineon XMC">XMC1000</a></li> <li>Nordic nRF51</li> <li>NXP <a href="/wiki/NXP_LPC" title="NXP LPC">LPC1100, LPC1200</a></li> <li>nuvoTon NuMicro</li> <li>Sonix SN32F700</li> <li>STMicroelectronics <a href="/wiki/STM32" title="STM32">STM32</a> F0</li> <li>Toshiba TX00</li> <li>Vorago VA108x0</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M0%2B" class="mw-redirect" title="ARM Cortex-M0+">Cortex-M0+</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Cypress PSoC 4000S, 4100S, 4100S+, 4100PS, 4700S, FM0+</li> <li>Holtek HT32F52000</li> <li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> C2, D0, D1, D2, DA, L2, R2, R3</li> <li>NXP <a href="/wiki/NXP_LPC" title="NXP LPC">LPC800, LPC11E60, LPC11U60</a></li> <li>NXP (Freescale) Kinetis E, EA, L, M, V1, W0</li> <li>Raspberry Pi <a href="/wiki/RP2040" title="RP2040">RP2040</a></li> <li>Renesas Synergy S1</li> <li>Silicon Labs (Energy Micro) <a href="/wiki/EFM32" title="EFM32">EFM32</a> Zero, Happy</li> <li>STMicroelectronics <a href="/wiki/STM32" title="STM32">STM32</a> L0</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M1" class="mw-redirect" title="ARM Cortex-M1">Cortex-M1</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Altera FPGAs Cyclone-II, Cyclone-III, Stratix-II, Stratix-III</li> <li><a href="/wiki/Microsemi" title="Microsemi">Microsemi</a> (<a href="/wiki/Actel" title="Actel">Actel</a>) FPGAs Fusion, IGLOO/e, ProASIC3L, ProASIC3/E</li> <li>Xilinx FPGAs Spartan-3, Virtex-2-3-4</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M3" class="mw-redirect" title="ARM Cortex-M3">Cortex-M3</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Actel <a href="/wiki/Actel_SmartFusion" title="Actel SmartFusion">SmartFusion, SmartFusion 2</a></li> <li>Analog Devices ADuCM300</li> <li>Cypress <a href="/wiki/PSoC" class="mw-redirect" title="PSoC">PSoC</a> 5000, 5000LP, FM3</li> <li>Fujitsu FM3</li> <li>Holtek HT32F</li> <li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> 3A, 3N, 3S, 3U, 3X</li> <li>NXP <a href="/wiki/NXP_LPC" title="NXP LPC">LPC1300, LPC1700, LPC1800</a></li> <li>ON Semiconductor Q32M210</li> <li>Silicon Labs Precision32</li> <li>Silicon Labs (Energy Micro) <a href="/wiki/EFM32" title="EFM32">EFM32 Tiny, Gecko, Leopard, Giant</a></li> <li>STMicroelectronics <a href="/wiki/STM32" title="STM32">STM32</a> F1, F2, L1</li> <li>Texas Instruments F28, LM3, TMS470, <a href="/wiki/OMAP#OMAP_4" title="OMAP">OMAP 4</a></li> <li>Toshiba TX03</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M4" class="mw-redirect" title="ARM Cortex-M4">Cortex-M4</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> 4L, 4N, 4S</li> <li>NXP (Freescale) Kinetis K, W2</li> <li>Renesas RA4W1, RA6M1, RA6M2, RA6M3, RA6T1</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M4" class="mw-redirect" title="ARM Cortex-M4">Cortex-M4F</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Cypress 6200, FM4</li> <li>Infineon <a href="/wiki/Infineon_XMC4000" class="mw-redirect" title="Infineon XMC4000">XMC4000</a></li> <li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> 4C, 4E, D5, E5, G5</li> <li>Microchip CEC1302</li> <li>Nordic nRF52</li> <li>NXP <a href="/wiki/NXP_LPC" title="NXP LPC">LPC4000, LPC4300</a></li> <li>NXP (Freescale) Kinetis K, V3, V4</li> <li>Renesas Synergy S3, S5, S7</li> <li>Silicon Labs (Energy Micro) <a href="/wiki/EFM32" title="EFM32">EFM32</a> Wonder</li> <li>STMicroelectronics <a href="/wiki/STM32" title="STM32">STM32</a> F3, F4, L4, L4+, WB</li> <li>Texas Instruments LM4F/TM4C, <a href="/wiki/TI_MSP432" title="TI MSP432">MSP432</a></li> <li>Toshiba TX04</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M7" class="mw-redirect" title="ARM Cortex-M7">Cortex-M7F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> E7, S7, V7</li> <li>NXP (Freescale) Kinetis KV5x, i.MX RT 10xx, i.MX RT 11xx, S32K3xx</li> <li>STMicroelectronics <a href="/wiki/STM32" title="STM32">STM32</a> F7, H7</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M23" class="mw-redirect" title="ARM Cortex-M23">Cortex-M23</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>GigaDevice CD32E2xx</li> <li>Microchip (Atmel) <a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a> L10, L11, and PIC 32CM-LE 32CM-LS</li> <li>Nuvoton M23xx family, M2xx family, NUC1262, M2L31</li> <li>Renesas S1JA, RA2A1, RA2L1, RA2E1, RA2E2</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M33" class="mw-redirect" title="ARM Cortex-M33">Cortex-M33F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Analog Devices ADUCM4</li> <li>Dialog DA1469x</li> <li>GigaDevice GD32E5, GD32W5</li> <li>Nordic nRF91, nRF5340, nRF54</li> <li>NXP <a href="/wiki/NXP_LPC" title="NXP LPC">LPC5500</a>, i.MX RT600</li> <li>ON RSL15</li> <li>Renesas RA4, RA6</li> <li>ST <a href="/wiki/STM32" title="STM32">STM32</a> H5, L5, U5, WBA</li> <li>Silicon Labs Wireless Gecko Series 2</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M35P" class="mw-redirect" title="ARM Cortex-M35P">Cortex-M35P</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>STMicroelectronics ST33K</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M55" class="mw-redirect" title="ARM Cortex-M55">Cortex-M55F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Alif Semiconductor Ensemble</li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a> <a href="/wiki/PSoC" class="mw-redirect" title="PSoC">PSoC</a> Edge</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-M85" class="mw-redirect" title="ARM Cortex-M85">Cortex-M85F</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Renesas RA8</li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Real-time_computing" title="Real-time computing">Real-time</a><br />microprocessors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-R4" class="mw-redirect" title="ARM Cortex-R4">Cortex-R4F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Texas Instruments RM4, TMS570</li> <li>Renesas RZ/T1</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-R5" class="mw-redirect" title="ARM Cortex-R5">Cortex-R5F</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Scaleo OLEA</li> <li>Texas Instruments RM57, AM2</li> <li>Xilinx <a href="/wiki/Xilinx#Versal" title="Xilinx">Versal</a>, <a href="/wiki/Xilinx#Zynq" title="Xilinx">ZynqMP</a>, <a href="/wiki/Xilinx#Zynq" title="Xilinx">ZynqRF</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-R7" class="mw-redirect" title="ARM Cortex-R7">Cortex-R7F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Renesas RZ/G2E, RZ/G2H, RZ/G2M, RZ/G2N</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-R52" class="mw-redirect" title="ARM Cortex-R52">Cortex-R52F</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>NXP S32Z, S32E</li> <li>Renesas RZ/N2L, RZ/T2L, RZ/T2M</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM_Cortex-R52%2B" class="mw-redirect" title="ARM Cortex-R52+">Cortex-R52+F</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>STMicroelectronics Stellar G, Stellar P</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Classic_ARM-based_chips" style="padding:3px"><table class="nowraplinks hlist mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Classic_ARM-based_chips" title="Template:Classic ARM-based chips"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Classic_ARM-based_chips" title="Template talk:Classic ARM-based chips"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Classic_ARM-based_chips" title="Special:EditPage/Template:Classic ARM-based chips"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Classic_ARM-based_chips" style="font-size:114%;margin:0 4em">Classic ARM-based chips</div></th></tr><tr><td class="navbox-abovebelow" colspan="2"><div> <ul><li><a href="/wiki/ARM_Holdings" class="mw-redirect" title="ARM Holdings">ARM Holdings</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM architecture family</a></li> <li><a href="/wiki/List_of_ARM_cores" class="mw-redirect" title="List of ARM cores">List of ARM cores</a></li> <li><a href="/wiki/ARM_Cortex-A" title="ARM Cortex-A">ARM Cortex-A</a></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a class="mw-selflink selflink">ARM Cortex-M</a></li> <li><a href="/wiki/List_of_ARM_Cortex-M_development_tools" title="List of ARM Cortex-M development tools">List of ARM Cortex-M development tools</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Classic<br />processors</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM7" title="ARM7">ARM7</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Atmel <a href="/wiki/AT91SAM7" class="mw-redirect" title="AT91SAM7">SAM7L, SAM7S, SAM7SE, SAM7X, SAM7XC</a>, <a href="/wiki/AT91CAP7" class="mw-redirect" title="AT91CAP7">AT91CAP7</a>, AT91M, AT91R</li> <li>Cirrus Logic PS7xxx, EP7xxx</li> <li>Mediatek MT62xx</li> <li>NXP <a href="/wiki/NXP_LPC#LPC2000_series" title="NXP LPC">LPC2100, LPC2200, LPC2300, LPC2400</a>, LH7</li> <li>STMicroelectronics STR7</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM9" title="ARM9">ARM9</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Aspeed AST2400</li> <li>Atmel <a href="/wiki/AT91SAM9" class="mw-redirect" title="AT91SAM9">SAM9G, SAM9M, SAM9N, SAM9R, SAM9X, SAM9XE, SAM926x</a>, <a href="/wiki/AT91CAP9" class="mw-redirect" title="AT91CAP9">AT91CAP9</a></li> <li>Cirrus Logic EP9xxx</li> <li>Freescale <a href="/wiki/I.MX#i.MX1x_series" title="I.MX">i.MX1x, i.MX2x</a></li> <li>Nuvoton NUC900</li> <li>NXP <a href="/wiki/NXP_LPC#LPC2900" title="NXP LPC">LPC2900</a>, <a href="/wiki/NXP_LPC#LPC3000_series" title="NXP LPC">LPC3000</a>, LH7A</li> <li>Philips <a href="/wiki/Nexperia_(processor)" title="Nexperia (processor)">Nexperia PNX4008</a></li> <li>Rockchip <a href="/wiki/Rockchip#RK27xx_series" title="Rockchip">RK27xx, RK28xx</a></li> <li>Samsung <a href="/wiki/List_of_Samsung_system-on-a-chips" class="mw-redirect" title="List of Samsung system-on-a-chips">S3C24xx</a></li> <li>STMicroelectronics <a href="/wiki/Nomadik" title="Nomadik">Nomadik STn881x</a></li> <li>STMicroelectronics STR9</li> <li>Texas Instruments <a href="/wiki/OMAP#OMAP_1" title="OMAP">OMAP 1</a>, <a href="/wiki/Sitara_ARM_Processor" class="mw-redirect" title="Sitara ARM Processor">AM1x</a>, <a href="/wiki/Texas_Instruments_DaVinci" title="Texas Instruments DaVinci">DaVinci</a></li> <li>VIA WonderMedia <a href="/wiki/WonderMedia" title="WonderMedia">WM8505/8650</a></li> <li>ZiiLABS <a href="/wiki/ZiiLABS" title="ZiiLABS">ZMS-05</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/ARM11" title="ARM11">ARM11</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Broadcom <a href="/wiki/BCM2835" class="mw-redirect" title="BCM2835">BCM2835</a></li> <li>Cavium CNS3xxx</li> <li>Freescale <a href="/wiki/I.MX#i.MX3x_series" title="I.MX">i.MX3x</a></li> <li>Infotmic IMAPX210/220</li> <li><a href="/wiki/Mindspeed_Technologies" title="Mindspeed Technologies">Mindspeed</a> Comcerto 1000</li> <li>Nvidia <a href="/wiki/Tegra" title="Tegra">Tegra APX, 6xx</a></li> <li>Qualcomm <a href="/wiki/MSM7000" title="MSM7000">MSM7000</a>, <a href="/wiki/Snapdragon_(system_on_chip)#Snapdragon_S1" class="mw-redirect" title="Snapdragon (system on chip)">Snapdragon S1</a></li> <li>Samsung <a href="/wiki/List_of_Samsung_system-on-a-chips" class="mw-redirect" title="List of Samsung system-on-a-chips">S3C64xx, S5P64xx</a></li> <li>ST-NXP Wireless <a href="/wiki/Nomadik" title="Nomadik">Nomadik STn882x</a></li> <li>Telechips TCC8902</li> <li>Texas Instruments <a href="/wiki/OMAP#OMAP_2" title="OMAP">OMAP 2</a></li> <li>VIA WonderMedia <a href="/wiki/WonderMedia" title="WonderMedia">WM87x0</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">ARMv2a<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Amber_(processor)" title="Amber (processor)">Amber</a> (open FPGA core)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">ARMv4<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Faraday_Technology" title="Faraday Technology">Faraday</a> FA526, FA626</li> <li>DEC/Intel <a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">ARMv5TE<br />compatible</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li>Intel/Marvell <a href="/wiki/XScale" title="XScale">XScale</a></li> <li><a href="/wiki/Marvell_Technology_Group" class="mw-redirect" title="Marvell Technology Group">Marvell</a> Sheeva, Feroceon, Jolteon, Mohawk</li> <li>Faraday FA606TE, FA616TE, FA626TE, FA726TE</li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Microcontrollers" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Microcontrollers" title="Template:Microcontrollers"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Microcontrollers" title="Template talk:Microcontrollers"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Microcontrollers" title="Special:EditPage/Template:Microcontrollers"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Microcontrollers" style="font-size:114%;margin:0 4em"><a href="/wiki/Microcontroller" title="Microcontroller">Microcontrollers</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Main</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-board_microcontroller" title="Single-board microcontroller">Single-board microcontroller</a></li> <li><a href="/wiki/Special_function_register" title="Special function register">Special function register</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Microarchitecture" title="Microarchitecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">68000</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MPS430</a></li> <li><a href="/wiki/PIC_microcontrollers" title="PIC microcontrollers">PIC</a></li> <li><a href="/wiki/RISC-V" title="RISC-V">RISC-V</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word length</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am2900" title="AMD Am2900">Am2900</a></li> <li><a href="/wiki/COP400" title="COP400">COP400</a></li> <li>MARC4</li> <li><a href="/wiki/Rockwell_PPS-4" title="Rockwell PPS-4">PPS-4</a></li> <li><a href="/wiki/S1C6x" title="S1C6x">S1C6x</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-47</a></li> <li><a href="/wiki/Texas_Instruments_TMS1000" title="Texas Instruments TMS1000">TMS1000</a></li> <li><a href="/wiki/%CE%9CCOM-4" class="mw-redirect" title="ΜCOM-4">μCOM-4</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_6800" title="Motorola 6800">6800</a> <ul><li><a href="/wiki/Motorola_68HC05" title="Motorola 68HC05">68HC05</a></li> <li><a href="/wiki/Motorola_68HC08" title="Motorola 68HC08">68HC08</a></li> <li><a href="/wiki/Motorola_68HC11" title="Motorola 68HC11">68HC11</a></li> <li><a href="/wiki/Freescale_S08" class="mw-redirect" title="Freescale S08">S08</a></li> <li><a href="/wiki/Freescale_RS08" title="Freescale RS08">RS08</a></li></ul></li> <li><a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">6502</a> <ul><li><a href="/wiki/WDC_65C134" title="WDC 65C134">65C134</a></li> <li><a href="/wiki/WDC_65C265" title="WDC 65C265">65C265</a></li> <li><a href="/wiki/Mitsubishi_740" title="Mitsubishi 740">MELPS 740</a></li></ul></li> <li><a href="/wiki/78K" title="78K">78K</a></li> <li><a href="/wiki/Intel_MCS-48" title="Intel MCS-48">8048</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a> <ul><li><a href="/wiki/XC800_family" title="XC800 family">XC800</a></li></ul></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/COP8" title="COP8">COP8</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8</a></li> <li><a href="/wiki/PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC10/12/16/17/18</a></li> <li><a href="/wiki/ST6_and_ST7" title="ST6 and ST7">ST6/ST7</a></li> <li><a href="/wiki/STM8" title="STM8">STM8</a></li> <li><a href="/wiki/Zilog_Z8" title="Zilog Z8">Z8</a></li> <li><a href="/wiki/Zilog_Z80" title="Zilog Z80">Z80</a> <ul><li><a href="/wiki/Zilog_eZ80" title="Zilog eZ80">eZ80</a></li> <li><a href="/wiki/Rabbit_2000" title="Rabbit 2000">Rabbit 2000</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-870</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/WDC_65C816" title="WDC 65C816">65C816</a></li> <li><a href="/wiki/Freescale_68HC12" class="mw-redirect" title="Freescale 68HC12">68HC12</a>/<a href="/wiki/Freescale_68HC16" class="mw-redirect" title="Freescale 68HC16">16</a></li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a></li> <li><a href="/wiki/C166_family" title="C166 family">C166</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16/C</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8S</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MSP430</a></li> <li><a href="/wiki/PIC_microcontroller#PIC24_and_dsPIC" class="mw-redirect" title="PIC microcontroller">PIC24/dsPIC</a></li> <li><a href="/wiki/R8C" title="R8C">R8C</a></li> <li><a href="/wiki/RL78" title="RL78">RL78</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Zilog_Z8000" title="Zilog Z8000">Z8000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am29000" title="AMD Am29000">Am29000</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/List_of_applications_of_ARM_cores" class="mw-redirect" title="List of applications of ARM cores">ARM</a> <a class="mw-selflink selflink">Cortex-M</a> <ul><li><a href="/wiki/EFM32" title="EFM32">EFM32</a></li> <li><a href="/wiki/NXP_LPC" title="NXP LPC">LPC</a></li> <li><a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a></li> <li><a href="/wiki/STM32" title="STM32">STM32</a></li> <li><a href="/wiki/Infineon_XMC" title="Infineon XMC">XMC</a></li></ul></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CRX</a></li> <li><a href="/wiki/Fujitsu_FR" title="Fujitsu FR">FR</a></li> <li><a href="/wiki/FR-V_(microprocessor)" title="FR-V (microprocessor)">FR-V</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8SX</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/MN103" title="MN103">MN103</a></li> <li><a href="/wiki/Motorola_68000" title="Motorola 68000">68000</a> <ul><li><a href="/wiki/NXP_ColdFire" title="NXP ColdFire">ColdFire</a></li></ul></li> <li><a href="/wiki/PIC_microcontroller#PIC32MX" class="mw-redirect" title="PIC microcontroller">PIC32</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <ul><li><a href="/wiki/MPC5xx" title="MPC5xx">MPC5xx</a></li></ul></li> <li><a href="/wiki/Parallax_Propeller" title="Parallax Propeller">Propeller</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Infineon_TriCore" title="Infineon TriCore">TriCore</a></li> <li><a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/RX_microcontroller_family" class="mw-redirect" title="RX microcontroller family">RX</a></li> <li><a href="/wiki/Tensilica" title="Tensilica">Xtensa</a></li> <li><a href="/wiki/Zilog_Z80000" title="Zilog Z80000">Z80000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/PowerPC#64-bit_PowerPC" title="PowerPC">PowerPC64</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Interfaces</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Programming</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/In-system_programming" title="In-system programming">In-circuit serial programming</a> (ICSP)</li> <li><a href="/wiki/In-system_programming" title="In-system programming">In-system programming</a> (ISP)</li> <li><a href="/wiki/AVR_microcontrollers#PDI" title="AVR microcontrollers">Program and Debug Interface</a> (PDI)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_serial" title="AVR microcontrollers">High-voltage serial programming</a> (HVSP)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_parallel" title="AVR microcontrollers">High voltage parallel programming</a> (HVPP)</li> <li><a href="/wiki/AVR_microcontrollers#Bootloader" title="AVR microcontrollers">Bootloader</a></li> <li><a href="/wiki/AVR_microcontrollers#ROM" title="AVR microcontrollers">ROM</a></li> <li><a href="/wiki/AVR_microcontrollers#aWire" title="AVR microcontrollers">aWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Debugging</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nexus_(standard)" title="Nexus (standard)">Nexus (standard)</a></li> <li><a href="/wiki/JTAG" title="JTAG">Joint Test Action Group</a> (JTAG) <ul><li><a href="/wiki/DebugWIRE" title="DebugWIRE">debugWIRE</a> (Atmel)</li></ul></li> <li><a href="/wiki/PIC_microcontroller#In-circuit_debugging" class="mw-redirect" title="PIC microcontroller">In-circuit debugging</a> (ICD)</li> <li><a href="/wiki/In-circuit_emulation" title="In-circuit emulation">In-circuit emulator</a> (ICE)</li> <li><a href="/wiki/In-target_probe" title="In-target probe">In-target probe</a> (ITP)</li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_common_microcontrollers" title="List of common microcontrollers">List of common microcontrollers</a></li> <li>By manufacturer <ul><li><a href="/wiki/Intel_microprocessor#Microcontrollers" class="mw-redirect" title="Intel microprocessor">Intel</a></li> <li><a href="/wiki/List_of_Freescale_products#Microcontrollers" class="mw-redirect" title="List of Freescale products">NXP/Freescale</a></li> <li><a href="/wiki/List_of_common_microcontrollers#Infineon" title="List of common microcontrollers">Infineon</a></li> <li><a href="/wiki/Renesas_Electronics#Products" title="Renesas Electronics">Renesas Electronics</a></li></ul></li> <li><a href="/wiki/List_of_Wi-Fi_microcontrollers" title="List of Wi-Fi microcontrollers">List of Wi-Fi microcontrollers</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">See also</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Programmable_logic_controller" title="Programmable logic controller">Programmable logic controller</a></li> <li><a href="/wiki/List_of_microprocessors" title="List of microprocessors">List of microprocessors</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Programmable_logic" title="Template:Programmable logic"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Programmable_logic" title="Template talk:Programmable logic"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Programmable_logic" title="Special:EditPage/Template:Programmable logic"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Programmable_logic" style="font-size:114%;margin:0 4em"><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> <ul><li><a href="/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual<br />property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a class="mw-selflink selflink">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 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