{"title":"Modified Montgomery for RSA Cryptosystem","authors":"Rupali Verma, Maitreyee Dutta, Renu Vig","volume":84,"journal":"International Journal of Computer and Information Engineering","pagesStart":1593,"pagesEnd":1598,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/9996895","abstract":"<p>Encryption and decryption in RSA are done by modular exponentiation which is achieved by repeated modular multiplication. Hence efficiency of modular multiplication directly determines the efficiency of RSA cryptosystem. This paper designs a Modified Montgomery Modular Multiplication in which addition of operands is computed by 4:2 compressor. The basic logic operations in addition are partitioned over two iterations such that parallel computations are performed. This reduces the critical path delay of proposed Montgomery design. The proposed design and RSA are implemented on Virtex 2 and Virtex 5 FPGAs. The two factors partitioning and parallelism have improved the frequency and throughput of proposed design.<\/p>\r\n","references":"[1]\tR. Rivest et al., \"A method for obtaining digital signatures and public key cryptosystems,\u201d Commun. ACM, vol 21, issue 2, Feb 1978, pp. 120-126.\r\n[2]\tP.L. Montgomery, \"Modular multiplication without trial division,\u201d Math Comput, vol 44, Apr. 1985, pp. 519-521.\r\n[3]\tC.D. Walter, \"Systolic modular multiplication,\u201d IEEE Trans. Comput, vol 42, no 3, Mar 1993, pp. 376-378.\r\n[4]\tS.E. Elridge et al., \"Hardware implementation of Montgomery\u2019s modular multiplication algorithm,\u201d IEEE Trans. Comput., vol. 42, no. 6, Jun 1993, pp. 693-699. \r\n[5]\tC. McIvor et al., \"Fast Montgomery modular multiplication and RSA Cryptographic processor architectures,\u201d Proc. 37th Asilomar Conf. Signals, Syst. Comput., vol. 1, Nov. 2003, pp. 379-384.\r\n[6]\tC. McIvor et al., \"Modified Montgomery modular multiplication and RSA exponentiation techniques,\u201d Proc. IEEE Comput. Digit. Techniques, vol. 151, no.6, Nov. 2004, pp. 402-408. \r\n[7]\tK. Manochehri et al., \"Fast Montgomery modular multiplication by pipelined CSA architecture,\u201d Proc. IEEE Int. Conf. Microelectron, Dec. 2004, pp. 144-147.\r\n[8]\tK. Manochehri et al., \"Modified Radix 2 Montgomery Modular Multiplication to Make It Faster and Simpler,\u201d In Proc. Int. Conference on Information Technology: Coding and Computing, Apr 2005, pp. 598-602.\r\n[9]\tH. Thapliyal et al., \"Modified Montgomery Modular Multiplication Using 4:2 Compressor and CSA Adder,\u201d In Proc. Of Third Int. Workshop on Electronic Design, Test and Applications, 2005.\r\n[10]\tY. Y Zhang et al., \"An efficient CSA architecture for Montgomery modular multiplication,\u201d Microprocessors and Microsystems, vol 31, no. 7, Nov.2007, pp. 456-459.\r\n[11]\tM.D. Shieh et al., \"A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem,\u201d IEEE Trans. On Very Large Scale Integration Systems, vol. 16, no. 9, Sept 2008, pp. 1151-1161. \r\n[12]\tC.D. Walter, \"Montgomery exponentiation needs no final subtractions,\u201d Electron. Lett., vol. 32, no. 21, Oct. 1999, pp. 1831-1832.\r\n[13]\tR. Verma et al., \"Modified Montgomery Modular Multiplication for RSA Cryptosystem,\u201d Int. Journal of Computational Intelligence and Information Security, vol 2, no. 9., Sept 2011, pp. 39-47.\r\n[14]\tS. Veeramachaneni et al., \"Novel Architectures for High Speed and Low Power 3-2, 4-2 and 5-2 Compressors,\u201d In 20th Int. Conf. on VLSI design, 2007.\r\n[15]\tP.B. Minev et al., \"The Virtex 5 Routing and Logic Architecture,\u201d Electronics-ET 2009, 14-17 Sept, Sozopol, Bulgaria.\r\n[16]\tM.D. Shieh et al., \"A New Algorithm for High Speed Modular Multiplication Design,\u201d IEEE Trans. On Circuits and Systems-I: Regular Papers, vol. 56, no. 9, Sept. 2009, pp. 2009-2019.\r\n[17]\tB. Schneier, Applied Cryptography Protocols, Algorithms and Source Code in C: Second edition, Wiley.\r\n","publisher":"World Academy of Science, Engineering and Technology","index":"Open Science Index 84, 2013"}