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architecture</title> <meta name="description" content="Search results for: VLSI architecture"> <meta name="keywords" content="VLSI architecture"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none 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action="https://publications.waset.org/search"> <div id="custom-search-input"> <div class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="VLSI architecture"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 914</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: VLSI architecture</h1> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">914</span> New VLSI Architecture for Motion Estimation Algorithm</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=V.%20S.%20K.%20Reddy">V. S. K. Reddy</a>, <a href="https://publications.waset.org/search?q=S.%20Sengupta"> S. Sengupta</a>, <a href="https://publications.waset.org/search?q=Y.%20M.%20Latha"> Y. M. Latha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents an efficient VLSI architecture design to achieve real time video processing using Full-Search Block Matching (FSBM) algorithm. The design employs parallel bank architecture with minimum latency, maximum throughput, and full hardware utilization. We use nine parallel processors in our architecture and each controlled by a state machine. State machine control implementation makes the design very simple and cost effective. The design is implemented using VHDL and the programming techniques we incorporated makes the design completely programmable in the sense that the search ranges and the block sizes can be varied to suit any given requirements. The design can operate at frequencies up to 36 MHz and it can function in QCIF and CIF video resolution at 1.46 MHz and 5.86 MHz, respectively. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Video%20Coding" title="Video Coding">Video Coding</a>, <a href="https://publications.waset.org/search?q=Motion%20Estimation" title=" Motion Estimation"> Motion Estimation</a>, <a href="https://publications.waset.org/search?q=Full-Search" title=" Full-Search"> Full-Search</a>, <a href="https://publications.waset.org/search?q=Block-Matching" title="Block-Matching">Block-Matching</a>, <a href="https://publications.waset.org/search?q=VLSI%20Architecture." title=" VLSI Architecture."> VLSI Architecture.</a> </p> <a href="https://publications.waset.org/14718/new-vlsi-architecture-for-motion-estimation-algorithm" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/14718/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/14718/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/14718/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/14718/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/14718/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/14718/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/14718/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/14718/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/14718/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/14718/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/14718.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1807</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">913</span> High Performance VLSI Architecture of 2D Discrete Wavelet Transform with Scalable Lattice Structure</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Juyoung%20Kim">Juyoung Kim</a>, <a href="https://publications.waset.org/search?q=Taegeun%20Park"> Taegeun Park</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, we propose a fully-utilized, block-based 2D DWT (discrete wavelet transform) architecture, which consists of four 1D DWT filters with two-channel QMF lattice structure. The proposed architecture requires about 2MN-3N registers to save the intermediate results for higher level decomposition, where M and N stand for the filter length and the row width of the image respectively. Furthermore, the proposed 2D DWT processes in horizontal and vertical directions simultaneously without an idle period, so that it computes the DWT for an N×N image in a period of N2(1-2-2J)/3. Compared to the existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rates. To mitigate the long critical path delay due to the cascaded lattices, we can apply the pipeline technique with four stages, while retaining 100% of hardware utilization. The proposed architecture can be applied in real-time video signal processing.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=discrete%20wavelet%20transform" title="discrete wavelet transform">discrete wavelet transform</a>, <a href="https://publications.waset.org/search?q=VLSI%20architecture" title=" VLSI architecture"> VLSI architecture</a>, <a href="https://publications.waset.org/search?q=QMF%20lattice%20filter" title=" QMF lattice filter"> QMF lattice filter</a>, <a href="https://publications.waset.org/search?q=pipelining." title=" pipelining."> pipelining.</a> </p> <a href="https://publications.waset.org/7661/high-performance-vlsi-architecture-of-2d-discrete-wavelet-transform-with-scalable-lattice-structure" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/7661/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/7661/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/7661/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/7661/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/7661/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/7661/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/7661/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/7661/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/7661/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/7661/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/7661.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1781</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">912</span> Mapping Complex, Large – Scale Spiking Networks on Neural VLSI</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Christian%20Mayr">Christian Mayr</a>, <a href="https://publications.waset.org/search?q=Matthias%20Ehrlich"> Matthias Ehrlich</a>, <a href="https://publications.waset.org/search?q=Stephan%20Henker"> Stephan Henker</a>, <a href="https://publications.waset.org/search?q=Karsten%20Wendt"> Karsten Wendt</a>, <a href="https://publications.waset.org/search?q=Ren%C3%A9%20Sch%C3%BCffny"> René Schüffny</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Traditionally, VLSI implementations of spiking neural nets have featured large neuron counts for fixed computations or small exploratory, configurable nets. This paper presents the system architecture of a large configurable neural net system employing a dedicated mapping algorithm for projecting the targeted biology-analog nets and dynamics onto the hardware with its attendant constraints. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Large%20scale%20VLSI%20neural%20net" title="Large scale VLSI neural net">Large scale VLSI neural net</a>, <a href="https://publications.waset.org/search?q=topology%20mapping" title=" topology mapping"> topology mapping</a>, <a href="https://publications.waset.org/search?q=complex%20pulse%20communication." title=" complex pulse communication."> complex pulse communication.</a> </p> <a href="https://publications.waset.org/8669/mapping-complex-large-scale-spiking-networks-on-neural-vlsi" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/8669/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/8669/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/8669/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/8669/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/8669/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/8669/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/8669/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/8669/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/8669/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/8669/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/8669.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1685</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">911</span> A Novel VLSI Architecture for Image Compression Model Using Low power Discrete Cosine Transform</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Vijaya%20Prakash.A.M">Vijaya Prakash.A.M</a>, <a href="https://publications.waset.org/search?q=K.S.Gurumurthy"> K.S.Gurumurthy</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In Image processing the Image compression can improve the performance of the digital systems by reducing the cost and time in image storage and transmission without significant reduction of the Image quality. This paper describes hardware architecture of low complexity Discrete Cosine Transform (DCT) architecture for image compression[6]. In this DCT architecture, common computations are identified and shared to remove redundant computations in DCT matrix operation. Vector processing is a method used for implementation of DCT. This reduction in computational complexity of 2D DCT reduces power consumption. The 2D DCT is performed on 8x8 matrix using two 1-Dimensional Discrete cosine transform blocks and a transposition memory [7]. Inverse discrete cosine transform (IDCT) is performed to obtain the image matrix and reconstruct the original image. The proposed image compression algorithm is comprehended using MATLAB code. The VLSI design of the architecture is implemented Using Verilog HDL. The proposed hardware architecture for image compression employing DCT was synthesized using RTL complier and it was mapped using 180nm standard cells. . The Simulation is done using Modelsim. The simulation results from MATLAB and Verilog HDL are compared. Detailed analysis for power and area was done using RTL compiler from CADENCE. Power consumption of DCT core is reduced to 1.027mW with minimum area[1]. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Discrete%20Cosine%20Transform%20%28DCT%29" title="Discrete Cosine Transform (DCT)">Discrete Cosine Transform (DCT)</a>, <a href="https://publications.waset.org/search?q=Inverse%20DiscreteCosine%20Transform%20%28IDCT%29" title=" Inverse DiscreteCosine Transform (IDCT)"> Inverse DiscreteCosine Transform (IDCT)</a>, <a href="https://publications.waset.org/search?q=Joint%20Photographic%20Expert%20Group%20%28JPEG%29" title=" Joint Photographic Expert Group (JPEG)"> Joint Photographic Expert Group (JPEG)</a>, <a href="https://publications.waset.org/search?q=Low%20Power%20Design" title="Low Power Design">Low Power Design</a>, <a href="https://publications.waset.org/search?q=Very%20Large%20Scale%20Integration%20%28VLSI%29%20." title=" Very Large Scale Integration (VLSI) ."> Very Large Scale Integration (VLSI) .</a> </p> <a href="https://publications.waset.org/6447/a-novel-vlsi-architecture-for-image-compression-model-using-low-power-discrete-cosine-transform" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/6447/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/6447/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/6447/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/6447/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/6447/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/6447/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/6447/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/6447/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/6447/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/6447/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/6447.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">3139</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">910</span> Simulation Based VLSI Implementation of Fast Efficient Lossless Image Compression System Using Adjusted Binary Code & Golumb Rice Code</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=N.%20Muthukumaran">N. Muthukumaran</a>, <a href="https://publications.waset.org/search?q=R.%20Ravi"> R. Ravi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>The Simulation based VLSI Implementation of FELICS (Fast Efficient Lossless Image Compression System) Algorithm is proposed to provide the lossless image compression and is implemented in simulation oriented VLSI (Very Large Scale Integrated). To analysis the performance of Lossless image compression and to reduce the image without losing image quality and then implemented in VLSI based FELICS algorithm. In FELICS algorithm, which consists of simplified adjusted binary code for Image compression and these compression image is converted in pixel and then implemented in VLSI domain. This parameter is used to achieve high processing speed and minimize the area and power. The simplified adjusted binary code reduces the number of arithmetic operation and achieved high processing speed. The color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Although VLSI based FELICS Algorithm provides effective solution for hardware architecture design for regular pipelining data flow parallelism with four stages. With two level parallelisms, consecutive pixels can be classified into even and odd samples and the individual hardware engine is dedicated for each one. This method can be further enhanced by multilevel parallelisms.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Image%20compression" title="Image compression">Image compression</a>, <a href="https://publications.waset.org/search?q=Pixel" title=" Pixel"> Pixel</a>, <a href="https://publications.waset.org/search?q=Compression%20Ratio" title=" Compression Ratio"> Compression Ratio</a>, <a href="https://publications.waset.org/search?q=Adjusted%20Binary%20code" title=" Adjusted Binary code"> Adjusted Binary code</a>, <a href="https://publications.waset.org/search?q=Golumb%20Rice%20code" title=" Golumb Rice code"> Golumb Rice code</a>, <a href="https://publications.waset.org/search?q=High%20Definition%20display" title=" High Definition display"> High Definition display</a>, <a href="https://publications.waset.org/search?q=VLSI%20Implementation." title=" VLSI Implementation."> VLSI Implementation.</a> </p> <a href="https://publications.waset.org/10000321/simulation-based-vlsi-implementation-of-fast-efficient-lossless-image-compression-system-using-adjusted-binary-code-golumb-rice-code" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10000321/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10000321/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10000321/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10000321/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10000321/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10000321/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10000321/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10000321/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10000321/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10000321/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10000321.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2073</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">909</span> Cellular Automata Based Robust Watermarking Architecture towards the VLSI Realization</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=V.%20H.%20Mankar">V. H. Mankar</a>, <a href="https://publications.waset.org/search?q=T.%20S.%20Das"> T. S. Das</a>, <a href="https://publications.waset.org/search?q=S.%20K.%20Sarkar"> S. K. Sarkar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, we have proposed a novel blind watermarking architecture towards its hardware implementation in VLSI. In order to facilitate this hardware realization, cellular automata (CA) concept is introduced. The CA has been already accepted as an attractive structure for VLSI implementation because of its modularity, parallelism, high performance and reliability. The hardware realizable multiresolution spread spectrum watermarking techniques are very few in numbers in spite of their best ever resiliency against signal impairments. This is because of the computational cost and complexity associated with their different filter banks and lifting techniques. The concept of cellular automata theory in order to form a new transform domain technique i.e. Cellular Automata Transform (CAT) have been incorporated. Since CA provides spreading sequences having very low cross-correlation properties, the CA based pseudorandom sequence generator is considered in the present work. Considering the watermarking technique as a digital communication process, an error control coding (ECC) must be incorporated in the data hiding schemes. Besides the hardware implementation of entire CA based data hiding technique, the individual blocks of the algorithm using CA provide the best result than that of some other methods irrespective of the hardware and software technique. The Cellular Automata Transform, CA based PN sequence generator, and CA ECC are the requisite blocks that are developed not only to meet the reliable hardware requirements but also for the basic spread spectrum watermarking features. The proposed algorithm shows statistical invisibility and resiliency against various common signal-processing operations. This algorithmic design utilizes the existing allocated bandwidth in the data transmission channel in a more efficient manner.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Cellular%20automata" title="Cellular automata">Cellular automata</a>, <a href="https://publications.waset.org/search?q=watermarking" title=" watermarking"> watermarking</a>, <a href="https://publications.waset.org/search?q=error%20control%20coding" title=" error control coding"> error control coding</a>, <a href="https://publications.waset.org/search?q=PN%20sequence" title=" PN sequence"> PN sequence</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI."> VLSI.</a> </p> <a href="https://publications.waset.org/15454/cellular-automata-based-robust-watermarking-architecture-towards-the-vlsi-realization" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/15454/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/15454/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/15454/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/15454/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/15454/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/15454/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/15454/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/15454/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/15454/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/15454/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/15454.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2067</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">908</span> VLSI Design of 2-D Discrete Wavelet Transform for Area-Efficient and High-Speed Image Computing</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Mountassar%20Maamoun">Mountassar Maamoun</a>, <a href="https://publications.waset.org/search?q=Mehdi%20Neggazi"> Mehdi Neggazi</a>, <a href="https://publications.waset.org/search?q=Abdelhamid%20Meraghni"> Abdelhamid Meraghni</a>, <a href="https://publications.waset.org/search?q=Daoud%20Berkani"> Daoud Berkani</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a VLSI design approach of a highspeed and real-time 2-D Discrete Wavelet Transform computing. The proposed architecture, based on new and fast convolution approach, reduces the hardware complexity in addition to reduce the critical path to the multiplier delay. Furthermore, an advanced twodimensional (2-D) discrete wavelet transform (DWT) implementation, with an efficient memory area, is designed to produce one output in every clock cycle. As a result, a very highspeed is attained. The system is verified, using JPEG2000 coefficients filters, on Xilinx Virtex-II Field Programmable Gate Array (FPGA) device without accessing any external memory. The resulting computing rate is up to 270 M samples/s and the (9,7) 2-D wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out memory) with 256×256 image size. In this way, the developed design requests reduced memory and provide very high-speed processing as well as high PSNR quality. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Discrete%20Wavelet%20Transform%20%28DWT%29" title="Discrete Wavelet Transform (DWT)">Discrete Wavelet Transform (DWT)</a>, <a href="https://publications.waset.org/search?q=Fast%0AConvolution" title=" Fast Convolution"> Fast Convolution</a>, <a href="https://publications.waset.org/search?q=FPGA" title=" FPGA"> FPGA</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI."> VLSI.</a> </p> <a href="https://publications.waset.org/6132/vlsi-design-of-2-d-discrete-wavelet-transform-for-area-efficient-and-high-speed-image-computing" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/6132/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/6132/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/6132/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/6132/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/6132/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/6132/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/6132/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/6132/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/6132/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/6132/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/6132.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1966</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">907</span> A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Sunil%20Jadav">Sunil Jadav</a>, <a href="https://publications.waset.org/search?q=Rajeevan%20Chandel%20Munish%20Vashishath"> Rajeevan Chandel Munish Vashishath</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Current%20Mode" title="Current Mode">Current Mode</a>, <a href="https://publications.waset.org/search?q=Voltage%20Mode" title=" Voltage Mode"> Voltage Mode</a>, <a href="https://publications.waset.org/search?q=VLSI%20Interconnect." title=" VLSI Interconnect."> VLSI Interconnect.</a> </p> <a href="https://publications.waset.org/10001108/a-superior-delay-estimation-model-for-vlsi-interconnect-in-current-mode-signaling" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10001108/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10001108/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10001108/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10001108/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10001108/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10001108/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10001108/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10001108/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10001108/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10001108/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10001108.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2450</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">906</span> LFSR Counter Implementation in CMOS VLSI</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Doshi%20N.%20A.">Doshi N. A.</a>, <a href="https://publications.waset.org/search?q=Dhobale%20S.%20B."> Dhobale S. B.</a>, <a href="https://publications.waset.org/search?q=Kakade%20S.%20R."> Kakade S. R.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> As chip manufacturing technology is suddenly on the threshold of major evaluation, which shrinks chip in size and performance, LFSR (Linear Feedback Shift Register) is implemented in layout level which develops the low power consumption chip, using recent CMOS, sub-micrometer layout tools. Thus LFSR counter can be a new trend setter in cryptography and is also beneficial as compared to GRAY & BINARY counter and variety of other applications. This paper compares 3 architectures in terms of the hardware implementation, CMOS layout and power consumption, using Microwind CMOS layout tool. Thus it provides solution to a low power architecture implementation of LFSR in CMOS VLSI. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Chip%20technology" title="Chip technology">Chip technology</a>, <a href="https://publications.waset.org/search?q=Layout%20level" title=" Layout level"> Layout level</a>, <a href="https://publications.waset.org/search?q=LFSR" title=" LFSR"> LFSR</a>, <a href="https://publications.waset.org/search?q=Pass%20transistor" title=" Pass transistor"> Pass transistor</a> </p> <a href="https://publications.waset.org/4463/lfsr-counter-implementation-in-cmos-vlsi" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/4463/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/4463/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/4463/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/4463/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/4463/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/4463/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/4463/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/4463/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/4463/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/4463/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/4463.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">4513</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">905</span> Adaptive Distributed Genetic Algorithms and Its VLSI Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Kazutaka%20Kobayashi">Kazutaka Kobayashi</a>, <a href="https://publications.waset.org/search?q=Norihiko%20Yoshida"> Norihiko Yoshida</a>, <a href="https://publications.waset.org/search?q=Shuji%20Narazaki"> Shuji Narazaki</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper presents a dynamic adaptation scheme for the frequency of inter-deme migration in distributed genetic algorithms (GA), and its VLSI hardware design. Distributed GA, or multi-deme-based GA, uses multiple populations which evolve concurrently. The purpose of dynamic adaptation is to improve convergence performance so as to obtain better solutions. Through simulation experiments, we proved that our scheme achieves better performance than fixed frequency migration schemes. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Genetic%20algorithms" title="Genetic algorithms">Genetic algorithms</a>, <a href="https://publications.waset.org/search?q=dynamic%20adaptation" title=" dynamic adaptation"> dynamic adaptation</a>, <a href="https://publications.waset.org/search?q=VLSI%20hardware." title=" VLSI hardware."> VLSI hardware.</a> </p> <a href="https://publications.waset.org/645/adaptive-distributed-genetic-algorithms-and-its-vlsi-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/645/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/645/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/645/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/645/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/645/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/645/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/645/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/645/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/645/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/645/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/645.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1669</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">904</span> Pulsed Multi-Layered Image Filtering: A VLSI Implementation</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Christian%20Mayr">Christian Mayr</a>, <a href="https://publications.waset.org/search?q=Holger%20Eisenreich"> Holger Eisenreich</a>, <a href="https://publications.waset.org/search?q=Stephan%20Henker"> Stephan Henker</a>, <a href="https://publications.waset.org/search?q=Ren%C3%A9%20Sch%C3%BCffny"> René Schüffny</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Image convolution similar to the receptive fields found in mammalian visual pathways has long been used in conventional image processing in the form of Gabor masks. However, no VLSI implementation of parallel, multi-layered pulsed processing has been brought forward which would emulate this property. We present a technical realization of such a pulsed image processing scheme. The discussed IC also serves as a general testbed for VLSI-based pulsed information processing, which is of interest especially with regard to the robustness of representing an analog signal in the phase or duration of a pulsed, quasi-digital signal, as well as the possibility of direct digital manipulation of such an analog signal. The network connectivity and processing properties are reconfigurable so as to allow adaptation to various processing tasks. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Neural%20image%20processing" title="Neural image processing">Neural image processing</a>, <a href="https://publications.waset.org/search?q=pulse%20computation%0D%0Aapplication" title=" pulse computation application"> pulse computation application</a>, <a href="https://publications.waset.org/search?q=pulsed%20Gabor%20convolution" title=" pulsed Gabor convolution"> pulsed Gabor convolution</a>, <a href="https://publications.waset.org/search?q=VLSI%20pulse%20routing." title=" VLSI pulse routing."> VLSI pulse routing.</a> </p> <a href="https://publications.waset.org/3099/pulsed-multi-layered-image-filtering-a-vlsi-implementation" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/3099/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/3099/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/3099/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/3099/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/3099/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/3099/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/3099/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/3099/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/3099/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/3099/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/3099.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1391</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">903</span> A Survey of Various Algorithms for Vlsi Physical Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Rajine%20Swetha%20R">Rajine Swetha R</a>, <a href="https://publications.waset.org/search?q=B.%20Shekar%20Babu"> B. Shekar Babu</a>, <a href="https://publications.waset.org/search?q=Sumithra%20Devi%20K.A"> Sumithra Devi K.A</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Electronic Systems are the core of everyday lives. They form an integral part in financial networks, mass transit, telephone systems, power plants and personal computers. Electronic systems are increasingly based on complex VLSI (Very Large Scale Integration) integrated circuits. Initial electronic design automation is concerned with the design and production of VLSI systems. The next important step in creating a VLSI circuit is Physical Design. The input to the physical design is a logical representation of the system under design. The output of this step is the layout of a physical package that optimally or near optimally realizes the logical representation. Physical design problems are combinatorial in nature and of large problem sizes. Darwin observed that, as variations are introduced into a population with each new generation, the less-fit individuals tend to extinct in the competition of basic necessities. This survival of fittest principle leads to evolution in species. The objective of the Genetic Algorithms (GA) is to find an optimal solution to a problem .Since GA-s are heuristic procedures that can function as optimizers, they are not guaranteed to find the optimum, but are able to find acceptable solutions for a wide range of problems. This survey paper aims at a study on Efficient Algorithms for VLSI Physical design and observes the common traits of the superior contributions. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Genetic%20Algorithms" title="Genetic Algorithms">Genetic Algorithms</a>, <a href="https://publications.waset.org/search?q=Physical%20Design" title=" Physical Design"> Physical Design</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI."> VLSI.</a> </p> <a href="https://publications.waset.org/9265/a-survey-of-various-algorithms-for-vlsi-physical-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/9265/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/9265/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/9265/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/9265/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/9265/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/9265/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/9265/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/9265/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/9265/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/9265/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/9265.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1740</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">902</span> Efficient Power-Delay Product Modulo 2n+1 Adder Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Yavar%20Safaei%20Mehrabani">Yavar Safaei Mehrabani</a>, <a href="https://publications.waset.org/search?q=Mehdi%20Hosseinzadeh"> Mehdi Hosseinzadeh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Computer%20arithmetic" title="Computer arithmetic">Computer arithmetic</a>, <a href="https://publications.waset.org/search?q=modulo%202n%2B1%20adders" title=" modulo 2n+1 adders"> modulo 2n+1 adders</a>, <a href="https://publications.waset.org/search?q=Residue%20Number%20System%20%28RNS%29" title="Residue Number System (RNS)">Residue Number System (RNS)</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI."> VLSI.</a> </p> <a href="https://publications.waset.org/11718/efficient-power-delay-product-modulo-2n1-adder-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/11718/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/11718/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/11718/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/11718/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/11718/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/11718/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/11718/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/11718/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/11718/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/11718/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/11718.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1801</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">901</span> Comparative Study of Evolutionary Model and Clustering Methods in Circuit Partitioning Pertaining to VLSI Design </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=K.%20A.%20Sumitra%20Devi">K. A. Sumitra Devi</a>, <a href="https://publications.waset.org/search?q=N.%20P.%20Banashree"> N. P. Banashree</a>, <a href="https://publications.waset.org/search?q=Annamma%20Abraham"> Annamma Abraham</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits its often essential to sub-divide multi -million transistor design into manageable Pieces. This paper looks at the various partitioning techniques aspects of VLSI CAD, targeted at various applications. We proposed an evolutionary time-series model and a statistical glitch prediction system using a neural network with selection of global feature by making use of clustering method model, for partitioning a circuit. For evolutionary time-series model, we made use of genetic, memetic & neuro-memetic techniques. Our work focused in use of clustering methods - K-means & EM methodology. A comparative study is provided for all techniques to solve the problem of circuit partitioning pertaining to VLSI design. The performance of all approaches is compared using benchmark data provided by MCNC standard cell placement benchmark net lists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then other model in recognizing sub-circuits with minimum amount of interconnections between them.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=VLSI" title="VLSI">VLSI</a>, <a href="https://publications.waset.org/search?q=circuit%20partitioning" title=" circuit partitioning"> circuit partitioning</a>, <a href="https://publications.waset.org/search?q=memetic%20algorithm" title=" memetic algorithm"> memetic algorithm</a>, <a href="https://publications.waset.org/search?q=genetic%20algorithm." title="genetic algorithm.">genetic algorithm.</a> </p> <a href="https://publications.waset.org/4003/comparative-study-of-evolutionary-model-and-clustering-methods-in-circuit-partitioning-pertaining-to-vlsi-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/4003/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/4003/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/4003/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/4003/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/4003/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/4003/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/4003/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/4003/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/4003/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/4003/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/4003.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1637</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">900</span> A Novel VLSI Architecture of Hybrid Image Compression Model based on Reversible Blockade Transform</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=C.%20Hemasundara%20Rao">C. Hemasundara Rao</a>, <a href="https://publications.waset.org/search?q=M.%20Madhavi%20Latha"> M. Madhavi Latha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Image compression can improve the performance of the digital systems by reducing time and cost in image storage and transmission without significant reduction of the image quality. Furthermore, the discrete cosine transform has emerged as the new state-of-the art standard for image compression. In this paper, a hybrid image compression technique based on reversible blockade transform coding is proposed. The technique, implemented over regions of interest (ROIs), is based on selection of the coefficients that belong to different transforms, depending on the coefficients is proposed. This method allows: (1) codification of multiple kernals at various degrees of interest, (2) arbitrary shaped spectrum,and (3) flexible adjustment of the compression quality of the image and the background. No standard modification for JPEG2000 decoder was required. The method was applied over different types of images. Results show a better performance for the selected regions, when image coding methods were employed for the whole set of images. We believe that this method is an excellent tool for future image compression research, mainly on images where image coding can be of interest, such as the medical imaging modalities and several multimedia applications. Finally VLSI implementation of proposed method is shown. It is also shown that the kernal of Hartley and Cosine transform gives the better performance than any other model. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=VLSI" title="VLSI">VLSI</a>, <a href="https://publications.waset.org/search?q=Discrete%20Cosine%20Transform" title=" Discrete Cosine Transform"> Discrete Cosine Transform</a>, <a href="https://publications.waset.org/search?q=JPEG" title=" JPEG"> JPEG</a>, <a href="https://publications.waset.org/search?q=Hartleytransform" title=" Hartleytransform"> Hartleytransform</a>, <a href="https://publications.waset.org/search?q=Radon%20Transform" title=" Radon Transform"> Radon Transform</a> </p> <a href="https://publications.waset.org/15094/a-novel-vlsi-architecture-of-hybrid-image-compression-model-based-on-reversible-blockade-transform" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/15094/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/15094/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/15094/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/15094/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/15094/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/15094/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/15094/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/15094/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/15094/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/15094/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/15094.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1836</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">899</span> Comparative Study of Ant Colony and Genetic Algorithms for VLSI Circuit Partitioning</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Sandeep%20Singh%20Gill">Sandeep Singh Gill</a>, <a href="https://publications.waset.org/search?q=Rajeevan%20Chandel"> Rajeevan Chandel</a>, <a href="https://publications.waset.org/search?q=Ashwani%20Chandel"> Ashwani Chandel</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>This paper presents a comparative study of Ant Colony and Genetic Algorithms for VLSI circuit bi-partitioning. Ant colony optimization is an optimization method based on behaviour of social insects [27] whereas Genetic algorithm is an evolutionary optimization technique based on Darwinian Theory of natural evolution and its concept of survival of the fittest [19]. Both the methods are stochastic in nature and have been successfully applied to solve many Non Polynomial hard problems. Results obtained show that Genetic algorithms out perform Ant Colony optimization technique when tested on the VLSI circuit bi-partitioning problem.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Partitioning" title="Partitioning">Partitioning</a>, <a href="https://publications.waset.org/search?q=genetic%20algorithm" title=" genetic algorithm"> genetic algorithm</a>, <a href="https://publications.waset.org/search?q=ant%20colony%20optimization" title=" ant colony optimization"> ant colony optimization</a>, <a href="https://publications.waset.org/search?q=non-polynomial%20hard" title=" non-polynomial hard"> non-polynomial hard</a>, <a href="https://publications.waset.org/search?q=netlist" title=" netlist"> netlist</a>, <a href="https://publications.waset.org/search?q=mutation." title=" mutation."> mutation.</a> </p> <a href="https://publications.waset.org/14013/comparative-study-of-ant-colony-and-genetic-algorithms-for-vlsi-circuit-partitioning" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/14013/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/14013/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/14013/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/14013/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/14013/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/14013/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/14013/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/14013/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/14013/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/14013/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/14013.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2248</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">898</span> Fast and Efficient On-Chip Interconnection Modeling for High Speed VLSI Systems</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=A.R.%20Aswatha">A.R. Aswatha</a>, <a href="https://publications.waset.org/search?q=T.%20Basavaraju"> T. Basavaraju</a>, <a href="https://publications.waset.org/search?q=S.%20Sandeep%20Kumar"> S. Sandeep Kumar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed IC-s. This paper presents closed–form expressions for RC and RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of these analytical models is several orders of magnitude faster than simulation using SPICE. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=IC%20design" title="IC design">IC design</a>, <a href="https://publications.waset.org/search?q=RC%2FRLC%20Interconnection" title=" RC/RLC Interconnection"> RC/RLC Interconnection</a>, <a href="https://publications.waset.org/search?q=VLSI%20Systems." title=" VLSI Systems."> VLSI Systems.</a> </p> <a href="https://publications.waset.org/3788/fast-and-efficient-on-chip-interconnection-modeling-for-high-speed-vlsi-systems" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/3788/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/3788/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/3788/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/3788/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/3788/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/3788/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/3788/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/3788/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/3788/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/3788/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/3788.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1507</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">897</span> Evaluation of Fuzzy ARTMAP with DBSCAN in VLSI Application</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=K.%20A.%20Sumithradevi">K. A. Sumithradevi</a>, <a href="https://publications.waset.org/search?q=Vijayalakshmi.%20M.%20N."> Vijayalakshmi. M. N.</a>, <a href="https://publications.waset.org/search?q=Annamma%20Abraham."> Annamma Abraham.</a>, <a href="https://publications.waset.org/search?q=Dr.%20Vasanta"> Dr. Vasanta</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The various applications of VLSI circuits in highperformance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. This paper describes a new model for partitioning a circuit using DBSCAN and fuzzy ARTMAP neural network. The first step is concerned with feature extraction, where we had make use DBSCAN algorithm. The second step is the classification and is composed of a fuzzy ARTMAP neural network. The performance of both approaches is compared using benchmark data provided by MCNC standard cell placement benchmark netlists. Analysis of the investigational results proved that the fuzzy ARTMAP with DBSCAN model achieves greater performance then only fuzzy ARTMAP in recognizing sub-circuits with lowest amount of interconnections between them The recognition rate using fuzzy ARTMAP with DBSCAN is 97.7% compared to only fuzzy ARTMAP. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=VLSI" title="VLSI">VLSI</a>, <a href="https://publications.waset.org/search?q=Circuit%20partitioning" title=" Circuit partitioning"> Circuit partitioning</a>, <a href="https://publications.waset.org/search?q=DBSCAN" title=" DBSCAN"> DBSCAN</a>, <a href="https://publications.waset.org/search?q=fuzzyARTMAP." title=" fuzzyARTMAP."> fuzzyARTMAP.</a> </p> <a href="https://publications.waset.org/11850/evaluation-of-fuzzy-artmap-with-dbscan-in-vlsi-application" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/11850/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/11850/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/11850/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/11850/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/11850/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/11850/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/11850/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/11850/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/11850/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/11850/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/11850.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1463</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">896</span> Music-Inspired Harmony Search Algorithm for Fixed Outline Non-Slicing VLSI Floorplanning</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=K.%20Sivasubramanian">K. Sivasubramanian</a>, <a href="https://publications.waset.org/search?q=K.%20B.%20Jayanthi"> K. B. Jayanthi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Floorplanning plays a vital role in the physical design process of Very Large Scale Integrated (VLSI) chips. It is an essential design step to estimate the chip area prior to the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, many optimization techniques were adopted in the literature. In this work, a music-inspired Harmony Search (HS) algorithm is used for the fixed die outline constrained floorplanning, with the aim of reducing the total chip area. HS draws inspiration from the musical improvisation process of searching for a perfect state of harmony. Initially, B*-tree is used to generate the primary floorplan for the given rectangular hard modules and then HS algorithm is applied to obtain an optimal solution for the efficient floorplan. The experimental results of the HS algorithm are obtained for the MCNC benchmark circuits. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Floor%20planning" title="Floor planning">Floor planning</a>, <a href="https://publications.waset.org/search?q=harmony%20search" title=" harmony search"> harmony search</a>, <a href="https://publications.waset.org/search?q=non-slicing%0D%0Afloorplan" title=" non-slicing floorplan"> non-slicing floorplan</a>, <a href="https://publications.waset.org/search?q=very%20large%20scale%20integrated%20circuits." title=" very large scale integrated circuits."> very large scale integrated circuits.</a> </p> <a href="https://publications.waset.org/10001831/music-inspired-harmony-search-algorithm-for-fixed-outline-non-slicing-vlsi-floorplanning" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10001831/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10001831/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10001831/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10001831/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10001831/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10001831/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10001831/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10001831/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10001831/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10001831/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10001831.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1956</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">895</span> A Four Method Framework for Fighting Software Architecture Erosion</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Sundus%20Ayyaz">Sundus Ayyaz</a>, <a href="https://publications.waset.org/search?q=Saad%20Rehman"> Saad Rehman</a>, <a href="https://publications.waset.org/search?q=Usman%20Qamar"> Usman Qamar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Software Architecture is the basic structure of software that states the development and advancement of a software system. Software architecture is also considered as a significant tool for the construction of high quality software systems. A clean design leads to the control, value and beauty of software resulting in its longer life while a bad design is the cause of architectural erosion where a software evolution completely fails. This paper discusses the occurrence of software architecture erosion and presents a set of methods for the detection, declaration and prevention of architecture erosion. The causes and symptoms of architecture erosion are observed with the examples of prescriptive and descriptive architectures and the practices used to stop this erosion are also discussed by considering different types of software erosion and their affects. Consequently finding and devising the most suitable approach for fighting software architecture erosion and in some way reducing its affect is evaluated and tested on different scenarios.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Software%20Architecture" title="Software Architecture">Software Architecture</a>, <a href="https://publications.waset.org/search?q=Architecture%20Erosion" title=" Architecture Erosion"> Architecture Erosion</a>, <a href="https://publications.waset.org/search?q=Prescriptive%20Architecture" title=" Prescriptive Architecture"> Prescriptive Architecture</a>, <a href="https://publications.waset.org/search?q=Descriptive%20Architecture." title=" Descriptive Architecture."> Descriptive Architecture.</a> </p> <a href="https://publications.waset.org/10000232/a-four-method-framework-for-fighting-software-architecture-erosion" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10000232/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10000232/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10000232/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10000232/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10000232/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10000232/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10000232/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10000232/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10000232/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10000232/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10000232.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2152</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">894</span> Design of a CMOS Differential Operational Transresistance Amplifier in 90 nm CMOS Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Hafiz%20Muhammad%20Obaid">Hafiz Muhammad Obaid</a>, <a href="https://publications.waset.org/search?q=Umais%20Tayyab"> Umais Tayyab</a>, <a href="https://publications.waset.org/search?q=Shabbir%20Majeed%20Ch."> Shabbir Majeed Ch.</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>In this paper, a CMOS differential operational transresistance amplifier (OTRA) is presented. The amplifier is designed and implemented in a standard umc90-nm CMOS technology. The differential OTRA provides wider bandwidth at high gain. It also shows much better rise and fall time and exhibits a very good input current dynamic range of 50 to 50 μA. The OTRA can be used in many analog VLSI applications. The presented amplifier has high gain bandwidth product of 617.6 THz Ω. The total power dissipation of the presented amplifier is also very low and it is 0.21 mW.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=CMOS" title="CMOS">CMOS</a>, <a href="https://publications.waset.org/search?q=differential" title=" differential"> differential</a>, <a href="https://publications.waset.org/search?q=operational%20transresistance%20amplifier" title=" operational transresistance amplifier"> operational transresistance amplifier</a>, <a href="https://publications.waset.org/search?q=OTRA" title=" OTRA"> OTRA</a>, <a href="https://publications.waset.org/search?q=90%20nm" title=" 90 nm"> 90 nm</a>, <a href="https://publications.waset.org/search?q=VLSI." title=" VLSI. "> VLSI. </a> </p> <a href="https://publications.waset.org/10007961/design-of-a-cmos-differential-operational-transresistance-amplifier-in-90-nm-cmos-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10007961/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10007961/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10007961/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10007961/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10007961/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10007961/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10007961/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10007961/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10007961/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10007961/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10007961.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1138</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">893</span> Accurate Crosstalk Analysis for RLC On-Chip VLSI Interconnect</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Susmita%20Sahoo">Susmita Sahoo</a>, <a href="https://publications.waset.org/search?q=Madhumanti%20Datta"> Madhumanti Datta</a>, <a href="https://publications.waset.org/search?q=Rajib%20Kar"> Rajib Kar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Crosstalk" title="Crosstalk">Crosstalk</a>, <a href="https://publications.waset.org/search?q=distributed%20RLC%20segments" title=" distributed RLC segments"> distributed RLC segments</a>, <a href="https://publications.waset.org/search?q=On-Chip%20interconnect" title=" On-Chip interconnect"> On-Chip interconnect</a>, <a href="https://publications.waset.org/search?q=output%20response" title=" output response"> output response</a>, <a href="https://publications.waset.org/search?q=VLSI" title=" VLSI"> VLSI</a>, <a href="https://publications.waset.org/search?q=noise%20peak" title=" noise peak"> noise peak</a>, <a href="https://publications.waset.org/search?q=noise%20width." title=" noise width."> noise width.</a> </p> <a href="https://publications.waset.org/5164/accurate-crosstalk-analysis-for-rlc-on-chip-vlsi-interconnect" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/5164/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/5164/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/5164/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/5164/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/5164/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/5164/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/5164/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/5164/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/5164/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/5164/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/5164.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1645</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">892</span> Considering the Relationship between Architecture and Philosophy: Toyo Ito’s Conceptual Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Serap%20Durmus">Serap Durmus</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The aim of this paper is to exemplify the relation of architecture and philosophy over the Japanese architect Toyo Ito’s conceptual architecture. The study is practiced in ‘Architecture and Philosophy Readings’ elective course with 22 sophomore architecture students in Karadeniz Technical University Department of Architecture. It is planned as a workshop, which discusses the design philosophy of Toyo Ito’s buildings and the reflections of concept in his intellectual architecture. So, the paper contains Toyo Ito’s philosophy, his discourses and buildings and also thinking similarities with philosopher Gilles Deleuze. Thus, the workshop of course is about architecture and philosophy relationship. With this aspect, a holistic graphic representation is aimed for Toyo Ito who thinks that everything composes a whole. As a result, it can be said that architect and philosopher interaction in architecture and philosophy relation supports creative thinking. Conceptual architecture of Toyo Ito has philosophical roots and his philosophy can be read over his buildings and can be represent totally via a holistic pattern. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Architecture" title="Architecture">Architecture</a>, <a href="https://publications.waset.org/search?q=philosophy" title=" philosophy"> philosophy</a>, <a href="https://publications.waset.org/search?q=Toyo%20Ito" title=" Toyo Ito"> Toyo Ito</a>, <a href="https://publications.waset.org/search?q=conceptual%20architecture" title=" conceptual architecture"> conceptual architecture</a>, <a href="https://publications.waset.org/search?q=Gilles%20Deleuze." title=" Gilles Deleuze."> Gilles Deleuze.</a> </p> <a href="https://publications.waset.org/10005102/considering-the-relationship-between-architecture-and-philosophy-toyo-itos-conceptual-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10005102/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10005102/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10005102/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10005102/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10005102/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10005102/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10005102/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10005102/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10005102/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10005102/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10005102.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">5281</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">891</span> Islamic Architecture and Its Challenges</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Mohammad%20Torabiyan">Mohammad Torabiyan</a>, <a href="https://publications.waset.org/search?q=Kazem%20Mosawi%20Nejad"> Kazem Mosawi Nejad</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Today architecture has become as a powerful media for introducing cultures to the world, which in turn brings about a change in the global insight, power gaining, investment, and development. Islamic architecture is based on the language of Koran and shows the depth and richness of Islam through the spiritual soul. This is in a way that belief in monotheism and faith in Islamic teachings are manifested as Islam's aesthetic thought in Islamic architecture. Unfortunately, Islamic architecture has been damaged a lot due to the lack of the necessary information, and also successive wars that have overtaken the Moslems as well as the dominance of colonizing counties. Islamic architecture is rooted in the history, culture and civilization of Moslems, but its deficiencies and shortcomings should be removed through systematizing the Islamic architecture researchers. Islamic countries should act in a way that the art of Islamic architecture shows its true place in different architecture eras and makes everybody aware that Islamic architecture has a historical root and is connected eternally to the genuineness, religious art, and Moslems' culture and civilization.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Art" title="Art">Art</a>, <a href="https://publications.waset.org/search?q=culture%20and%20civilization" title=" culture and civilization"> culture and civilization</a>, <a href="https://publications.waset.org/search?q=Islamic%20architecture" title=" Islamic architecture"> Islamic architecture</a>, <a href="https://publications.waset.org/search?q=Moslems." title=" Moslems."> Moslems.</a> </p> <a href="https://publications.waset.org/10001900/islamic-architecture-and-its-challenges" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10001900/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10001900/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10001900/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10001900/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10001900/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10001900/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10001900/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10001900/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10001900/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10001900/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10001900.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2853</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">890</span> Architecture Exception Governance</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Ondruska%20Marek">Ondruska Marek</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The article presents the whole model of IS/IT architecture exception governance. As first, the assumptions of presented model are set. As next, there is defined a generic governance model that serves as a basis for the architecture exception governance. The architecture exception definition and its attributes follow. The model respects well known approaches to the area that are described in the text, but it adopts higher granularity in description and expands the process view with all the next necessary governance components as roles, principles and policies, tools to enable the implementation of the model into organizations. The architecture exception process is decomposed into a set of processes related to the architecture exception lifecycle consisting of set of phases and architecture exception states. Finally, there is information about my future research related to this area. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Architecture" title="Architecture">Architecture</a>, <a href="https://publications.waset.org/search?q=dispensation" title=" dispensation"> dispensation</a>, <a href="https://publications.waset.org/search?q=exception" title=" exception"> exception</a>, <a href="https://publications.waset.org/search?q=governance" title=" governance"> governance</a>, <a href="https://publications.waset.org/search?q=model" title=" model"> model</a> </p> <a href="https://publications.waset.org/8841/architecture-exception-governance" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/8841/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/8841/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/8841/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/8841/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/8841/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/8841/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/8841/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/8841/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/8841/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/8841/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/8841.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">2475</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">889</span> Bode Stability Analysis for Single Wall Carbon Nanotube Interconnects Used in 3D-VLSI Circuits</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Saeed%20H.%20Nasiri">Saeed H. Nasiri</a>, <a href="https://publications.waset.org/search?q=Rahim%20Faez"> Rahim Faez</a>, <a href="https://publications.waset.org/search?q=Bita%20Davoodi"> Bita Davoodi</a>, <a href="https://publications.waset.org/search?q=Maryam%20Farrokhi"> Maryam Farrokhi</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Bode stability analysis based on transmission line modeling (TLM) for single wall carbon nanotube (SWCNT) interconnects used in 3D-VLSI circuits is investigated for the first time. In this analysis, the dependence of the degree of relative stability for SWCNT interconnects on the geometry of each tube has been acquired. It is shown that, increasing the length and diameter of each tube, SWCNT interconnects become more stable. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Bode%20stability%20criterion" title="Bode stability criterion">Bode stability criterion</a>, <a href="https://publications.waset.org/search?q=Interconnects" title=" Interconnects"> Interconnects</a>, <a href="https://publications.waset.org/search?q=Interlayer%0Avia" title=" Interlayer via"> Interlayer via</a>, <a href="https://publications.waset.org/search?q=Single%20wall%20carbon%20nanotubes" title=" Single wall carbon nanotubes"> Single wall carbon nanotubes</a>, <a href="https://publications.waset.org/search?q=Transmission%20line%20method" title=" Transmission line method"> Transmission line method</a>, <a href="https://publications.waset.org/search?q=Time%0Adomain%20analysis" title=" Time domain analysis"> Time domain analysis</a> </p> <a href="https://publications.waset.org/8373/bode-stability-analysis-for-single-wall-carbon-nanotube-interconnects-used-in-3d-vlsi-circuits" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/8373/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/8373/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/8373/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/8373/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/8373/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/8373/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/8373/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/8373/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/8373/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/8373/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/8373.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1831</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">888</span> Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency Shift Technique</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=J.V.R.Ravindra">J.V.R.Ravindra</a>, <a href="https://publications.waset.org/search?q=M.B.Srinivas">M.B.Srinivas</a>, <a href="https://publications.waset.org/search?q="></a> </p> <p class="card-text"><strong>Abstract:</strong></p> Accurate modeling of high speed RLC interconnects has become a necessity to address signal integrity issues in current VLSI design. To accurately model a dispersive system of interconnects at higher frequencies; a full-wave analysis is required. However, conventional circuit simulation of interconnects with full wave models is extremely CPU expensive. We present an algorithm for reducing large VLSI circuits to much smaller ones with similar input-output behavior. A key feature of our method, called Frequency Shift Technique, is that it is capable of reducing linear time-varying systems. This enables it to capture frequency-translation and sampling behavior, important in communication subsystems such as mixers, RF components and switched-capacitor filters. Reduction is obtained by projecting the original system described by linear differential equations into a lower dimension. Experiments have been carried out using Cadence Design Simulator cwhich indicates that the proposed technique achieves more % reduction with less CPU time than the other model order reduction techniques existing in literature. We also present applications to RF circuit subsystems, obtaining size reductions and evaluation speedups of orders of magnitude with insignificant loss of accuracy. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Model%20order%20Reduction" title="Model order Reduction">Model order Reduction</a>, <a href="https://publications.waset.org/search?q=RLC" title=" RLC"> RLC</a>, <a href="https://publications.waset.org/search?q=crosstalk" title=" crosstalk"> crosstalk</a> </p> <a href="https://publications.waset.org/15247/model-order-reduction-of-linear-time-variant-high-speed-vlsi-interconnects-using-frequency-shift-technique" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/15247/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/15247/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/15247/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/15247/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/15247/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/15247/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/15247/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/15247/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/15247/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/15247/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/15247.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1652</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">887</span> Toward An Agreement on Semantic Web Architecture</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Haytham%20Al-Feel">Haytham Al-Feel</a>, <a href="https://publications.waset.org/search?q=M.A.Koutb"> M.A.Koutb</a>, <a href="https://publications.waset.org/search?q=Hoda%20Suoror"> Hoda Suoror</a> </p> <p class="card-text"><strong>Abstract:</strong></p> There are many problems associated with the World Wide Web: getting lost in the hyperspace; the web content is still accessible only to humans and difficulties of web administration. The solution to these problems is the Semantic Web which is considered to be the extension for the current web presents information in both human readable and machine processable form. The aim of this study is to reach new generic foundation architecture for the Semantic Web because there is no clear architecture for it, there are four versions, but still up to now there is no agreement for one of these versions nor is there a clear picture for the relation between different layers and technologies inside this architecture. This can be done depending on the idea of previous versions as well as Gerber-s evaluation method as a step toward an agreement for one Semantic Web architecture. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Semantic%20Web%20Architecture" title="Semantic Web Architecture">Semantic Web Architecture</a>, <a href="https://publications.waset.org/search?q=XML" title=" XML"> XML</a>, <a href="https://publications.waset.org/search?q=RDF%20and%0AOntology." title=" RDF and Ontology."> RDF and Ontology.</a> </p> <a href="https://publications.waset.org/11355/toward-an-agreement-on-semantic-web-architecture" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/11355/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/11355/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/11355/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/11355/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/11355/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/11355/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/11355/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/11355/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/11355/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/11355/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/11355.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1702</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">886</span> Identifying Chaotic Architecture: Origins of Nonlinear Design Theory</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Mohammadsadegh%20Zanganehfar">Mohammadsadegh Zanganehfar</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>Through the emergence of modern architecture, an aggressive desire for new design theories appeared through the works of architects and critics. The discourse of complexity and volumetric composition happened to be an important and controversial issue in the discipline of architecture which was discussed through a general point of view in Robert Venturi and Denise Scott Brown's book “Complexity and contradiction in architecture” in 1966, this paper attempts to identify chaos theory as a scientific model of complexity and its relation to architecture design theory by conducting a qualitative analysis and multidisciplinary critical approach through architecture and basic sciences resources. Accordingly, we identify chaotic architecture as the correlation between chaos theory and the discipline of architecture, and as an independent nonlinear design theory with specific characteristics and properties.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Architecture%20complexity" title="Architecture complexity">Architecture complexity</a>, <a href="https://publications.waset.org/search?q=chaos%20theory" title=" chaos theory"> chaos theory</a>, <a href="https://publications.waset.org/search?q=fractals" title=" fractals"> fractals</a>, <a href="https://publications.waset.org/search?q=nonlinear%20dynamic%20systems" title=" nonlinear dynamic systems"> nonlinear dynamic systems</a>, <a href="https://publications.waset.org/search?q=nonlinear%20ontology." title=" nonlinear ontology."> nonlinear ontology.</a> </p> <a href="https://publications.waset.org/10012445/identifying-chaotic-architecture-origins-of-nonlinear-design-theory" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/10012445/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a href="https://publications.waset.org/10012445/bibtex" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">BibTeX</a> <a href="https://publications.waset.org/10012445/chicago" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Chicago</a> <a href="https://publications.waset.org/10012445/endnote" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">EndNote</a> <a href="https://publications.waset.org/10012445/harvard" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">Harvard</a> <a href="https://publications.waset.org/10012445/json" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">JSON</a> <a href="https://publications.waset.org/10012445/mla" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">MLA</a> <a href="https://publications.waset.org/10012445/ris" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">RIS</a> <a href="https://publications.waset.org/10012445/xml" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">XML</a> <a href="https://publications.waset.org/10012445/iso690" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">ISO 690</a> <a href="https://publications.waset.org/10012445.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">1075</span> </span> </div> </div> <div class="card publication-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">885</span> Sigma-Delta ADCs Converter a Study Case</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/search?q=Thiago%20Brito%20Bezerra">Thiago Brito Bezerra</a>, <a href="https://publications.waset.org/search?q=Mauro%20Lopes%20de%20Freitas"> Mauro Lopes de Freitas</a>, <a href="https://publications.waset.org/search?q=Waldir%20Sabino%20da%20Silva%20J%C3%BAnior"> Waldir Sabino da Silva Júnior</a> </p> <p class="card-text"><strong>Abstract:</strong></p> <p>The Sigma-Delta A/D converters have been proposed as a practical application for A/D conversion at high rates because of its simplicity and robustness to imperfections in the circuit, also because the traditional converters are more difficult to implement in VLSI technology. These difficulties with conventional conversion methods need precise analog components in their filters and conversion circuits, and are more vulnerable to noise and interference. This paper aims to analyze the architecture, function and application of Analog-Digital converters (A/D) Sigma-Delta to overcome these difficulties, showing some simulations using the Simulink software and Multisim.</p> <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/search?q=Analysis" title="Analysis">Analysis</a>, <a href="https://publications.waset.org/search?q=Oversampling%20Modulator" title=" Oversampling Modulator"> Oversampling Modulator</a>, <a href="https://publications.waset.org/search?q=A%2FD%20converters" title=" A/D converters"> A/D converters</a>, <a href="https://publications.waset.org/search?q=Sigma-Delta." title=" Sigma-Delta."> Sigma-Delta.</a> </p> <a href="https://publications.waset.org/9999647/sigma-delta-adcs-converter-a-study-case" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/9999647/apa" target="_blank" rel="nofollow" class="btn btn-primary btn-sm">APA</a> <a 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