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aria-controls="toc-Design-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Design subsection </button> <ul id="toc-Design-sublist" class="vector-toc-list"> <li id="toc-ISA_base_and_extensions" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#ISA_base_and_extensions"> <div class="vector-toc-text"> 4.1 ISA base and extensions </div> </a> <ul id="toc-ISA_base_and_extensions-sublist" class="vector-toc-list"> <li id="toc-Profiles_and_platforms" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Profiles_and_platforms"> <div class="vector-toc-text"> 4.1.1 Profiles and platforms </div> </a> <ul id="toc-Profiles_and_platforms-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Register_sets" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Register_sets"> <div class="vector-toc-text"> 4.2 Register sets </div> </a> <ul id="toc-Register_sets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Memory_access" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Memory_access"> <div class="vector-toc-text"> 4.3 Memory access </div> </a> <ul id="toc-Memory_access-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Immediates" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Immediates"> <div class="vector-toc-text"> 4.4 Immediates </div> </a> <ul id="toc-Immediates-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Subroutine_calls,_jumps,_and_branches" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Subroutine_calls,_jumps,_and_branches"> <div class="vector-toc-text"> 4.5 Subroutine calls, jumps, and branches </div> </a> <ul id="toc-Subroutine_calls,_jumps,_and_branches-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Arithmetic_and_logic_sets" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Arithmetic_and_logic_sets"> <div class="vector-toc-text"> 4.6 Arithmetic and logic sets </div> </a> <ul id="toc-Arithmetic_and_logic_sets-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Atomic_memory_operations" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Atomic_memory_operations"> <div class="vector-toc-text"> 4.7 Atomic memory operations </div> </a> <ul id="toc-Atomic_memory_operations-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Compressed_subset" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Compressed_subset"> <div class="vector-toc-text"> 4.8 Compressed subset </div> </a> <ul id="toc-Compressed_subset-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Embedded_subset" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Embedded_subset"> <div class="vector-toc-text"> 4.9 Embedded subset </div> </a> <ul id="toc-Embedded_subset-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Privileged_instruction_set" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Privileged_instruction_set"> <div class="vector-toc-text"> 4.10 Privileged instruction set </div> </a> <ul id="toc-Privileged_instruction_set-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Bit_manipulation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Bit_manipulation"> <div class="vector-toc-text"> 4.11 Bit manipulation </div> </a> <ul id="toc-Bit_manipulation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Packed_SIMD" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Packed_SIMD"> <div class="vector-toc-text"> 4.12 Packed SIMD </div> </a> <ul id="toc-Packed_SIMD-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Vector_set" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Vector_set"> <div class="vector-toc-text"> 4.13 Vector set </div> </a> <ul id="toc-Vector_set-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_debug_system" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#External_debug_system"> <div class="vector-toc-text"> 4.14 External debug system </div> </a> <ul id="toc-External_debug_system-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Implementations" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Implementations"> <div class="vector-toc-text"> 5 Implementations </div> </a> <button aria-controls="toc-Implementations-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> Toggle Implementations subsection </button> <ul id="toc-Implementations-sublist" class="vector-toc-list"> <li id="toc-Existing" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Existing"> <div class="vector-toc-text"> 5.1 Existing </div> </a> <ul id="toc-Existing-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-In_development" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#In_development"> <div class="vector-toc-text"> 5.2 In development </div> </a> <ul id="toc-In_development-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Open_source" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Open_source"> <div class="vector-toc-text"> 5.3 Open source </div> </a> <ul id="toc-Open_source-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-End-user_hardware" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#End-user_hardware"> <div class="vector-toc-text"> 6 End-user hardware </div> </a> <ul id="toc-End-user_hardware-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Software" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Software"> <div class="vector-toc-text"> 7 Software </div> </a> <ul id="toc-Software-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Development_tools" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Development_tools"> <div class="vector-toc-text"> 8 Development tools </div> </a> <ul id="toc-Development_tools-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> 9 See also </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> 10 Notes </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> 11 References </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> 12 Further reading </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> 13 External links </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown 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Available in 29 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-29" aria-hidden="true" > 29 languages </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%B1%D9%8A%D8%B3%D9%83-%D9%81%D8%A7%D9%8A%D9%81" title="ريسك-فايف – Arabic" lang="ar" hreflang="ar" data-title="ريسك-فايف" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target">العربية</a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/RISC-V" title="RISC-V – Catalan" lang="ca" hreflang="ca" data-title="RISC-V" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target">Català</a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/RISC-V" title="RISC-V – Czech" lang="cs" hreflang="cs" data-title="RISC-V" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target">Čeština</a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/RISC-V" title="RISC-V – German" lang="de" hreflang="de" data-title="RISC-V" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target">Deutsch</a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/RISC-V" title="RISC-V – Estonian" lang="et" hreflang="et" data-title="RISC-V" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target">Eesti</a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/RISC-V" title="RISC-V – Greek" lang="el" hreflang="el" data-title="RISC-V" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target">Ελληνικά</a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/RISC-V" title="RISC-V – Spanish" lang="es" hreflang="es" data-title="RISC-V" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target">Español</a></li><li class="interlanguage-link interwiki-eu mw-list-item"><a href="https://eu.wikipedia.org/wiki/RISC-V" title="RISC-V – Basque" lang="eu" hreflang="eu" data-title="RISC-V" data-language-autonym="Euskara" data-language-local-name="Basque" class="interlanguage-link-target">Euskara</a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B1%DB%8C%D8%B3%DA%A9_%D9%BE%D9%86%D8%AC" title="ریسک پنج – Persian" lang="fa" hreflang="fa" data-title="ریسک پنج" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target">فارسی</a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/RISC-V" title="RISC-V – French" lang="fr" hreflang="fr" data-title="RISC-V" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target">Français</a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/RISC-V" title="RISC-V – Korean" lang="ko" hreflang="ko" data-title="RISC-V" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target">한국어</a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/RISC-V" title="RISC-V – Italian" lang="it" hreflang="it" data-title="RISC-V" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target">Italiano</a></li><li class="interlanguage-link interwiki-he mw-list-item"><a href="https://he.wikipedia.org/wiki/RISC-V" title="RISC-V – Hebrew" lang="he" hreflang="he" data-title="RISC-V" data-language-autonym="עברית" data-language-local-name="Hebrew" class="interlanguage-link-target">עברית</a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/RISC-V" title="RISC-V – Hungarian" lang="hu" hreflang="hu" data-title="RISC-V" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target">Magyar</a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/RISC-V" title="RISC-V – Dutch" lang="nl" hreflang="nl" data-title="RISC-V" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target">Nederlands</a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/RISC-V" title="RISC-V – Japanese" lang="ja" hreflang="ja" data-title="RISC-V" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target">日本語</a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/RISC-V" title="RISC-V – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="RISC-V" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target">Norsk bokmål</a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/RISC-V" title="RISC-V – Polish" lang="pl" hreflang="pl" data-title="RISC-V" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target">Polski</a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/RISC-V" title="RISC-V – Portuguese" lang="pt" hreflang="pt" data-title="RISC-V" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target">Português</a></li><li class="interlanguage-link interwiki-qu mw-list-item"><a href="https://qu.wikipedia.org/wiki/RISC-V" title="RISC-V – Quechua" lang="qu" hreflang="qu" data-title="RISC-V" data-language-autonym="Runa Simi" data-language-local-name="Quechua" class="interlanguage-link-target">Runa Simi</a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/RISC-V" title="RISC-V – Russian" lang="ru" hreflang="ru" data-title="RISC-V" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target">Русский</a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/RISC-V" title="RISC-V – Finnish" lang="fi" hreflang="fi" data-title="RISC-V" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target">Suomi</a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/RISC-V" title="RISC-V – Swedish" lang="sv" hreflang="sv" data-title="RISC-V" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target">Svenska</a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/RISC-V" title="RISC-V – Turkish" lang="tr" hreflang="tr" data-title="RISC-V" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target">Türkçe</a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/RISC-V" title="RISC-V – Ukrainian" lang="uk" hreflang="uk" data-title="RISC-V" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target">Українська</a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/RISC-V" title="RISC-V – Vietnamese" lang="vi" hreflang="vi" data-title="RISC-V" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target">Tiếng Việt</a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/RISC-V" title="RISC-V – Wu" lang="wuu" hreflang="wuu" data-title="RISC-V" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target">吴语</a></li><li class="interlanguage-link interwiki-zh-yue mw-list-item"><a href="https://zh-yue.wikipedia.org/wiki/RISC-V" title="RISC-V – Cantonese" lang="yue" hreflang="yue" data-title="RISC-V" data-language-autonym="粵語" data-language-local-name="Cantonese" class="interlanguage-link-target">粵語</a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/RISC-V" title="RISC-V – Chinese" lang="zh" hreflang="zh" data-title="RISC-V" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target">中文</a></li> </ul> <div class="after-portlet after-portlet-lang"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q17637401#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li id="ca-nstab-main" class="selected vector-tab-noicon mw-list-item"><a href="/wiki/RISC-V" title="View the content page [c]" accesskey="c">Article</a></li><li id="ca-talk" class="vector-tab-noicon mw-list-item"><a href="/wiki/Talk:RISC-V" rel="discussion" title="Discuss improvements to the content page [t]" accesskey="t">Talk</a></li> </ul> </div> </div> <div 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.infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">RISC-V</caption><tbody><tr><td colspan="2" class="infobox-image"><a href="/wiki/File:RISC-V-logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9a/RISC-V-logo.svg/220px-RISC-V-logo.svg.png" decoding="async" width="220" height="35" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9a/RISC-V-logo.svg/330px-RISC-V-logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9a/RISC-V-logo.svg/440px-RISC-V-logo.svg.png 2x" data-file-width="512" data-file-height="81" /></a></td></tr><tr><th scope="row" class="infobox-label">Designer</th><td class="infobox-data"><a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a></td></tr><tr><th scope="row" class="infobox-label">Bits</th><td class="infobox-data"><a href="/wiki/32-bit_computing" title="32-bit computing">32</a>, <a href="/wiki/64-bit_computing" title="64-bit computing">64</a>, <a href="/wiki/128-bit_computing" title="128-bit computing">128</a></td></tr><tr><th scope="row" class="infobox-label">Introduced</th><td class="infobox-data">6 August 2014 (10 years ago) (2014-08-06)<a href="#cite_note-1">[1]</a></td></tr><tr><th scope="row" class="infobox-label">Version</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"> <ul><li>unprivileged ISA 20191213,<a href="#cite_note-isa20191213-2">[2]</a></li> <li>privileged ISA 20211203<a href="#cite_note-priv-isa-3">[3]</a></li></ul> </div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Computer_architecture" title="Computer architecture">Design</a></th><td class="infobox-data"><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></td></tr><tr><th scope="row" class="infobox-label">Type</th><td class="infobox-data"><a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">Load–store</a></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">Encoding</a></th><td class="infobox-data">Variable</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Branch_(computer_science)" title="Branch (computer science)">Branching</a></th><td class="infobox-data">Compare-and-branch</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Endianness" title="Endianness">Endianness</a></th><td class="infobox-data">Little<a href="#cite_note-isa20191213-2">[2]</a>: 9 <a href="#cite_note-4">[a]</a></td></tr><tr><th scope="row" class="infobox-label">Page size</th><td class="infobox-data">4 KiB</td></tr><tr><th scope="row" class="infobox-label">Extensions</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>M: Multiplication</li> <li>A: Atomics – LR/SC & fetch-and-op</li> <li>F: Floating point (32-bit)</li> <li>D: <abbr title="Floating point">FP</abbr> Double (64-bit)</li> <li>Q: <abbr title="Floating point">FP</abbr> Quad (128-bit)</li> <li>Zicsr: Control and status register support</li> <li>Zifencei: <a href="/wiki/Memory_barrier" title="Memory barrier">Load/store fence</a></li> <li>C: Compressed instructions (16-bit)</li> <li>J: Interpreted or JIT-compiled languages support</li></ul> </div></td></tr><tr><th scope="row" class="infobox-label">Open</th><td class="infobox-data">Yes, royalty free</td></tr><tr><th colspan="2" class="infobox-header"><a href="/wiki/Processor_register" title="Processor register">Registers</a></th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/General-purpose_register" class="mw-redirect" title="General-purpose register">General-purpose</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>16</li> <li>32</li></ul> </div> (Includes one <a href="/wiki/Always-zero_register" class="mw-redirect" title="Always-zero register">always-zero register</a>)</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Floating_point" class="mw-redirect" title="Floating point">Floating point</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"> <ul><li>32</li></ul> </div> (Optional. Width depends on available extensions)</td></tr></tbody></table> RISC-V<a href="#cite_note-6">[b]</a> (pronounced "risk-five"<a href="#cite_note-isa20191213-2">[2]</a>: 1 ) is an <a href="/wiki/Open_standard" title="Open standard">open standard</a> <a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">instruction set architecture</a> (ISA) based on established <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) principles. The project began in 2010 at the <a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a>, transferred to the RISC-V Foundation in 2015, and on to RISC-V International, a Swiss non-profit entity, in November 2019.<a href="#cite_note-7">[5]</a><a href="#cite_note-8">[6]</a> Like several other RISC ISAs, e.g. <a href="/wiki/Amber_(processor)" title="Amber (processor)">Amber (ARMv2)</a> or <a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a>, RISC-V is offered under <a href="/wiki/Royalty-free" title="Royalty-free">royalty-free</a> <a href="/wiki/Open-source_license" title="Open-source license">open-source licenses</a>.<a href="#cite_note-9">[7]</a> The documents defining the RISC-V instruction set architecture (ISA) are offered under a <a href="/wiki/Creative_Commons_license" title="Creative Commons license">Creative Commons license</a> or a <a href="/wiki/BSD_licenses" title="BSD licenses">BSD License</a>. Mainline support for RISC-V was added to the Linux 5.17 kernel, in 2022, along with its <a href="/wiki/Toolchain" title="Toolchain">toolchain</a>.<a href="#cite_note-10">[8]</a> In July 2023, RISC-V, in its <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> variant called riscv64,<a href="#cite_note-11">[9]</a> was included as an official architecture of Linux distribution <a href="/wiki/Debian" title="Debian">Debian</a>, in its <a href="/wiki/Debian_version_history#Naming_convention" title="Debian version history">unstable</a> version.<a href="#cite_note-12">[10]</a> The goal of this project was "to have Debian ready to install and run on systems implementing a variant of the RISC-V ISA."<a href="#cite_note-13">[11]</a> Some RISC-V International members, such as <a href="/wiki/SiFive" title="SiFive">SiFive</a>, <a href="/wiki/Andes_Technology" title="Andes Technology">Andes Technology</a>, <a href="/wiki/Synopsys" title="Synopsys">Synopsys</a>, Alibaba's <a href="/wiki/Alibaba_Group#Cloud_computing_and_artificial_intelligence_technology" title="Alibaba Group">Damo Academy</a>, <a href="/wiki/Raspberry_Pi" title="Raspberry Pi">Raspberry Pi</a>, and Akeana,<a href="#cite_note-14">[12]</a><a href="#cite_note-15">[13]</a> are offering or have announced commercial <a href="/wiki/System_on_a_chip" title="System on a chip">systems on a chip</a> (SoCs) that incorporate one or more RISC-V compatible CPU cores.<a href="#cite_note-:5-16">[14]</a> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="Overview">Overview</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=1" title="Edit section: Overview">edit</a>]</div> As a RISC architecture, the RISC-V ISA is a <a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">load–store architecture</a>. Its floating-point instructions use <a href="/wiki/IEEE_754" title="IEEE 754">IEEE 754</a> floating-point. Notable features of the RISC-V ISA include: instruction bit field locations chosen to simplify the use of <a href="/wiki/Multiplexer#Digital_multiplexers" title="Multiplexer">multiplexers</a> in a CPU,<a href="#cite_note-isa20191213-2">[2]</a>: 17  a design that is architecturally neutral,[<a href="/wiki/Wikipedia:Accuracy_dispute#Disputed_statement" title="Wikipedia:Accuracy dispute">dubious</a> – <a href="/wiki/Talk:RISC-V" title="Talk:RISC-V">discuss</a>] and a fixed location for the sign bit of <a href="/wiki/Immediate_value" class="mw-redirect" title="Immediate value">immediate values</a> to speed up <a href="/wiki/Sign_extension" title="Sign extension">sign extension</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 17  The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> naturally aligned instructions, and the ISA supports variable length extensions where each instruction can be any number of <a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a> parcels in length.<a href="#cite_note-isa20191213-2">[2]</a>: 7–10  Extensions support small <a href="/wiki/Embedded_system" title="Embedded system">embedded systems</a>, <a href="/wiki/Personal_computer" title="Personal computer">personal computers</a>, <a href="/wiki/Supercomputer" title="Supercomputer">supercomputers</a> with vector processors, and warehouse-scale <a href="/wiki/Parallel_computing" title="Parallel computing">parallel computers</a>. The instruction set specification defines 32-bit and <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> <a href="/wiki/Address_space" title="Address space">address space</a> variants. The specification includes a description of a <a href="/wiki/128-bit_computing" title="128-bit computing">128-bit</a> flat address space variant, as an extrapolation of 32- and 64-bit variants, but the 128-bit ISA remains "not frozen" intentionally, because as of 2023<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, there is still little practical experience with such large memory systems.<a href="#cite_note-isa20191213-2">[2]</a>: 41  Unlike other academic designs which are typically optimized only for simplicity of exposition, the designers intended that the RISC-V instruction set be usable for practical computers. As of June 2019, version 2.2 of the user-space ISA<a href="#cite_note-isa2.2-17">[15]</a> and version 1.11 of the privileged ISA<a href="#cite_note-priv-isa-3">[3]</a> are <a href="/wiki/Freeze_(software_engineering)" title="Freeze (software engineering)">frozen</a>, permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213.<a href="#cite_note-isa20191213-2">[2]</a> An external debug specification is available as a draft, version 0.13.2.<a href="#cite_note-external-debug-18">[16]</a> <div class="mw-heading mw-heading2"><h2 id="Rationale">Rationale</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=2" title="Edit section: Rationale">edit</a>]</div> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Yunsup_Lee_holding_RISC_V_prototype_chip.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/7a/Yunsup_Lee_holding_RISC_V_prototype_chip.jpg/220px-Yunsup_Lee_holding_RISC_V_prototype_chip.jpg" decoding="async" width="220" height="147" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/7a/Yunsup_Lee_holding_RISC_V_prototype_chip.jpg/330px-Yunsup_Lee_holding_RISC_V_prototype_chip.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/7a/Yunsup_Lee_holding_RISC_V_prototype_chip.jpg/440px-Yunsup_Lee_holding_RISC_V_prototype_chip.jpg 2x" data-file-width="4776" data-file-height="3187" /></a><figcaption>RISC-V processor prototype, January 2013</figcaption></figure> <a href="/wiki/CPU_design" class="mw-redirect" title="CPU design">CPU design</a> requires design expertise in several specialties: electronic <a href="/wiki/Logic_gate" title="Logic gate">digital logic</a>, <a href="/wiki/Compiler" title="Compiler">compilers</a>, and <a href="/wiki/Operating_system" title="Operating system">operating systems</a>. To cover the costs of such a team, commercial vendors of processor intellectual property (IP), such as <a href="/wiki/Arm_Ltd." class="mw-redirect" title="Arm Ltd.">Arm Ltd.</a> and <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a>, charge <a href="/wiki/Royalty_payment" title="Royalty payment">royalties</a> for the use of their designs and <a href="/wiki/Patent" title="Patent">patents</a>.<a href="#cite_note-19">[17]</a><a href="#cite_note-20">[18]</a><a href="#cite_note-21">[19]</a> They also often require <a href="/wiki/Non-disclosure_agreement" title="Non-disclosure agreement">non-disclosure agreements</a> before releasing documents that describe their designs' detailed advantages. In many cases, they never describe the reasons for their design choices. RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties.<a href="#cite_note-isa20191213-2">[2]</a>: 1 <a href="#cite_note-isasbfree-22">[20]</a> Also, justifying rationales for each design decision of the project are explained, at least in broad terms. The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially <a href="/wiki/Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a>. RISC-V was originated in part to aid all such projects.<a href="#cite_note-isa20191213-2">[2]</a>: 1 <a href="#cite_note-isasbfree-22">[20]</a> To build a large, continuing community of users and thereby accumulate designs and software, the RISC-V ISA designers intentionally support a wide variety of practical use cases: compact, performance, and low-power real-world implementations<a href="#cite_note-isa20191213-2">[2]</a>: 1–2, 153–154 <a href="#cite_note-rocketsspeed-23">[21]</a> without over-architecting for a given <a href="/wiki/Microarchitecture" title="Microarchitecture">microarchitecture</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 1 <a href="#cite_note-sodor-24">[22]</a><a href="#cite_note-shakti-25">[23]</a><a href="#cite_note-boom-26">[24]</a> The requirements of a large base of contributors is part of the reason why RISC-V was engineered to address many possible uses. The designers' primary assertion is that the instruction set is the key interface in a computer as it is situated at the interface between the hardware and the software. If a good instruction set were open and available for use by all, then it can dramatically reduce the cost of software by enabling far more reuse. It should also trigger increased competition among hardware providers, who can then devote more resources toward design and less for software support.<a href="#cite_note-isasbfree-22">[20]</a> The designers maintain that new principles are becoming rare in instruction set design, as the most successful designs of the last forty years have grown increasingly similar. Of those that failed, most did so because their sponsoring companies were financially unsuccessful, not because the instruction sets were technically poor. Thus, a well-designed open instruction set designed using well-established principles should attract long-term support by many vendors.<a href="#cite_note-isasbfree-22">[20]</a> RISC-V also encourages academic usage. The simplicity of the integer subset permits basic student exercises, and is a simple enough ISA to enable software to control research machines. The variable-length ISA provides room for instruction set extensions for both student exercises and research,<a href="#cite_note-isa20191213-2">[2]</a>: 7  and the separated privileged instruction set permits research in operating system support without redesigning compilers.<a href="#cite_note-priv-isa-3">[3]</a> RISC-V's open intellectual property paradigm allows derivative designs to be published, reused, and modified.<a href="#cite_note-isa2.1-27">[25]</a> <div class="mw-heading mw-heading2"><h2 id="History">History</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=3" title="Edit section: History">edit</a>]</div> The term <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a> dates from about 1980.<a href="#cite_note-riscstart-28">[26]</a> Before then, there was some knowledge (see <a href="/wiki/John_Cocke_(computer_scientist)" title="John Cocke (computer scientist)">John Cocke</a>) that simpler computers can be effective, but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set <a href="/wiki/DLX" title="DLX">DLX</a> for the first edition of Computer Architecture: A Quantitative Approach in 1990 of which <a href="/wiki/David_Patterson_(computer_scientist)" title="David Patterson (computer scientist)">David Patterson</a> was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using <a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">field-programmable gate arrays</a> (FPGA), but it was never truly intended for commercial deployment. <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a> CPUs, versions 2 and earlier, had a public-domain instruction set and are still supported by the <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a> (GCC), a popular <a href="/wiki/Free_software" title="Free software">free-software</a> compiler. Three open-source <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">cores</a> exist for this ISA, but were never manufactured.<a href="#cite_note-amber-29">[27]</a><a href="#cite_note-arm4u-30">[28]</a> <a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a>, <a href="/wiki/OpenPOWER" class="mw-redirect" title="OpenPOWER">OpenPOWER</a>, and <a href="/wiki/OpenSPARC" title="OpenSPARC">OpenSPARC</a> / <a href="/wiki/LEON" title="LEON">LEON</a> cores are offered, by a number of vendors, and have mainline GCC and <a href="/wiki/Linux" title="Linux">Linux</a> kernel support.<a href="#cite_note-31">[29]</a><a href="#cite_note-32">[30]</a><a href="#cite_note-33">[31]</a> <a href="/wiki/Krste_Asanovi%C4%87" title="Krste Asanović">Krste Asanović</a> at the <a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a>, had a research requirement for an open-source computer system, and in 2010, he decided to develop and publish one in a "short, three-month project over the summer" with several of his graduate students. The plan was to aid both academic and industrial users.<a href="#cite_note-isasbfree-22">[20]</a> David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC,<a href="#cite_note-riscstart-28">[26]</a> and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects at the University of California, Berkeley (<a href="/wiki/Berkeley_RISC#RISC_I" title="Berkeley RISC">RISC-I</a> and <a href="/wiki/Berkeley_RISC#RISC_II" title="Berkeley RISC">RISC-II</a> published in 1981 by Patterson, who refers<a href="#cite_note-geneology-34">[32]</a> to the SOAR architecture<a href="#cite_note-35">[33]</a> from 1984 as "RISC-III" and the SPUR architecture<a href="#cite_note-36">[34]</a> from 1988 as "RISC-IV"). At this stage, students provided initial software, simulations, and CPU designs.<a href="#cite_note-contributors-37">[35]</a> <figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:Raven1ST28_June12BWRC.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Raven1ST28_June12BWRC.jpg/220px-Raven1ST28_June12BWRC.jpg" decoding="async" width="220" height="294" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Raven1ST28_June12BWRC.jpg/330px-Raven1ST28_June12BWRC.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/e/e9/Raven1ST28_June12BWRC.jpg/440px-Raven1ST28_June12BWRC.jpg 2x" data-file-width="2390" data-file-height="3199" /></a><figcaption>First Raven1 bring up ST28nm at <a href="/w/index.php?title=Berkeley_Wireless_Research_Center&action=edit&redlink=1" class="new" title="Berkeley Wireless Research Center (page does not exist)">Berkeley Wireless Research Center</a> (BWRC) June 2012</figcaption></figure> The RISC-V authors and their institution originally sourced the ISA documents<a href="#cite_note-originalisa-38">[36]</a> and several CPU designs under <a href="/wiki/BSD_licenses" title="BSD licenses">BSD licenses</a>, which allow derivative works—such as RISC-V chip designs—to be either open and free, or closed and proprietary. The ISA specification itself (i.e., the encoding of the instruction set) was published in 2011 as open source,<a href="#cite_note-39">[37]</a> with all rights reserved. The actual technical report (an expression of the specification) was later placed under a <a href="/wiki/Creative_Commons_license" title="Creative Commons license">Creative Commons license</a> to permit enhancement by external contributors through the RISC-V Foundation, and later RISC-V International. A full history of RISC-V has been published on the RISC-V International website.<a href="#cite_note-history-40">[38]</a> <div class="mw-heading mw-heading3"><h3 id="RISC-V_Foundation_and_RISC-V_International">RISC-V Foundation and RISC-V International</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=4" title="Edit section: RISC-V Foundation and RISC-V International">edit</a>]</div> Commercial users require an ISA to be stable before they can use it in a product that may last many years. To address this issue, the RISC-V Foundation was formed in 2015 to own, maintain, and publish intellectual property related to RISC-V's definition.<a href="#cite_note-41">[39]</a> The original authors and owners have surrendered their rights to the foundation.[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] The foundation is led by CEO <a href="/wiki/Calista_Redmond" title="Calista Redmond">Calista Redmond</a>, who took on the role in 2019 after leading open infrastructure projects at <a href="/wiki/IBM" title="IBM">IBM</a>.<a href="#cite_note-42">[40]</a>[<a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">failed verification</a>] The founding members of RISC-V were: Andes, Antmicro, Bluespec, CEVA, Codasip, Cortus, Esperanto, Espressif, ETH Zurich, Google, IBM, ICT, IIT Madras, Lattice, lowRISC, Microchip, MIT (Csail), Qualcomm, Rambus, Rumble, SiFive, Syntacore and Technolution.<a href="#cite_note-43">[41]</a> In November 2019, the RISC-V Foundation announced that it would relocate to Switzerland, citing concerns over U.S. trade regulations.<a href="#cite_note-44">[42]</a><a href="#cite_note-45">[43]</a> As of March 2020, the organization was named RISC-V International, a Swiss nonprofit business association.<a href="#cite_note-46">[44]</a> As of 2019<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, RISC-V International freely publishes the documents defining RISC-V and permits unrestricted use of the ISA for design of software and hardware. However, only members of RISC-V International can vote to approve changes, and only member organizations use the <a href="/wiki/Trademark" title="Trademark">trademarked</a> compatibility logo.<a href="#cite_note-47">[45]</a> <div class="mw-heading mw-heading3"><h3 id="Awards">Awards</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=5" title="Edit section: Awards">edit</a>]</div> <ul><li>2017: The Linley Group's Analyst's Choice Award for Best Technology (for the instruction set)<a href="#cite_note-48">[46]</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Design">Design</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=6" title="Edit section: Design">edit</a>]</div> <div class="mw-heading mw-heading3"><h3 id="ISA_base_and_extensions">ISA base and extensions</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=7" title="Edit section: ISA base and extensions">edit</a>]</div> RISC-V has a modular design, consisting of alternative base parts, with added optional extensions. The ISA base and its extensions are developed in a collective effort between industry, the research community and educational institutions. The base specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logic (i.e., integer) manipulation, and ancillaries. The base alone can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler. The standard extensions are specified to work with all of the standard bases, and with each other without conflict. Many RISC-V computers might implement the compressed instructions extension to reduce power consumption, code size, and memory use.<a href="#cite_note-isa20191213-2">[2]</a>: 97–99  There are also future plans to support <a href="/wiki/Hypervisor" title="Hypervisor">hypervisors</a> and <a href="/wiki/Virtualization" title="Virtualization">virtualization</a>.<a href="#cite_note-priv-isa-3">[3]</a> Together with the supervisor extension, S, an RVGC instruction set, which includes one of the RV base instruction sets, the G collection of extensions (which includes "I", meaning that the base is non-embedded), and the C extension, defines all instructions needed to conveniently support a general purpose <a href="/wiki/Operating_system" title="Operating system">operating system</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 129, 154  <table class="wikitable plainrowheaders"> <caption>ISA base and extensions </caption> <tbody><tr> <th scope="col">Name </th> <th scope="col">Description </th> <th scope="col">Version </th> <th scope="col">Status<a href="#cite_note-frozen-49">[A]</a> </th> <th>Instruction count </th></tr> <tr> <th colspan="5">Base </th></tr> <tr> <th scope="row"><style data-mw-deduplicate="TemplateStyles:r886049734">.mw-parser-output .monospaced{font-family:monospace,monospace}</style>RVWMO </th> <td>Weak memory ordering</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32I </th> <td>Base integer instruction set, 32-bit</td> <td>2.1</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>40 </td></tr> <tr> <th scope="row"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32E </th> <td>Base integer instruction set (embedded), 32-bit, 16 registers</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>40 </td></tr> <tr> <th scope="row"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64I </th> <td>Base integer instruction set, 64-bit</td> <td>2.1</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>15 </td></tr> <tr> <th scope="row"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64E </th> <td>Base integer instruction set (embedded), 64-bit</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV128I </th> <td>Base integer instruction set, 128-bit</td> <td>1.7</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td>15 </td></tr> <tr> <th colspan="5">Extension </th></tr> <tr> <th scope="row">M </th> <td>Standard extension for integer multiplication and division</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> 8 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32) 13 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64) </td></tr> <tr> <th scope="row">A </th> <td>Standard extension for atomic instructions</td> <td>2.1</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>11 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32) 22 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64) </td></tr> <tr> <th scope="row">F </th> <td>Standard extension for single-precision floating-point</td> <td>2.2</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>26 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32) 30 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64) </td></tr> <tr> <th scope="row">D </th> <td>Standard extension for double-precision floating-point</td> <td>2.2</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>26 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32) 32 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64) </td></tr> <tr> <th scope="row">Zicsr </th> <td>Control and status register (CSR) instructions</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>6 </td></tr> <tr> <th scope="row">Zifencei </th> <td>Instruction-fetch fence</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>1 </td></tr> <tr> <th scope="row">G </th> <td>Shorthand for the IMAFD_Zicsr_Zifencei base and extensions<a href="#cite_note-isa20191213-2">[2]</a>: 129 </td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">—</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na">— </td> <td> </td></tr> <tr> <th scope="row">Q </th> <td>Standard extension for quad-precision floating-point</td> <td>2.2</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>28 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32) 32 (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64) </td></tr> <tr> <th scope="row">L </th> <td>Standard extension for decimal floating-point</td> <td>0.0</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td> </td></tr> <tr> <th scope="row">C </th> <td>Standard extension for compressed instructions</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>40 </td></tr> <tr> <th scope="row">B </th> <td>Standard extension for bit manipulation</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>43<a href="#cite_note-bitmanip_1_0-50">[47]</a> </td></tr> <tr> <th scope="row">J </th> <td>Standard extension for dynamically translated languages</td> <td>0.0</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td> </td></tr> <tr> <th scope="row">T </th> <td>Standard extension for transactional memory</td> <td>0.0</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td> </td></tr> <tr> <th scope="row">P </th> <td>Standard extension for packed-SIMD instructions</td> <td>0.9.10</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td> </td></tr> <tr> <th scope="row">V </th> <td>Standard extension for vector operations</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>187<a href="#cite_note-51">[48]</a> </td></tr> <tr> <th scope="row">Zk </th> <td>Standard extension for scalar cryptography</td> <td>1.0.1</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>49<a href="#cite_note-scalar_crypto_1_0_1-52">[49]</a> </td></tr> <tr> <th scope="row">H </th> <td>Standard extension for hypervisor</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>15 </td></tr> <tr> <th scope="row">S </th> <td>Standard extension for supervisor-level instructions</td> <td>1.12</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td>4 </td></tr> <tr> <th scope="row">Zam </th> <td>Misaligned atomics</td> <td>0.1</td> <td style="background:#FFC7C7;color:black;vertical-align:middle;text-align:center;" class="table-no">Open </td> <td> </td></tr> <tr> <th scope="row">Zihintpause </th> <td>Pause hint</td> <td>2.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zihintntl </th> <td>Non-temporal locality hints</td> <td>0.3</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zfa </th> <td>Additional floating-point instructions</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zfh </th> <td>Half-precision floating-point</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zfhmin </th> <td>Minimal half-precision floating-point</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zfinx </th> <td>Single-precision floating-point in integer register</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zdinx </th> <td>Double-precision floating-point in integer register</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zhinx </th> <td>Half-precision floating-point in integer register</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zhinxmin </th> <td>Minimal half-precision floating-point in integer register</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Zmmul </th> <td>Multiplication subset of the M extension</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr> <tr> <th scope="row">Ztso </th> <td>Total store ordering</td> <td>1.0</td> <td style="background:#9EFF9E;color:black;vertical-align:middle;text-align:center;" class="table-yes">Ratified </td> <td> </td></tr></tbody></table> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-upper-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-frozen-49"><a href="#cite_ref-frozen_49-0">^</a> Frozen parts are expected to have their final feature set and to receive only clarifications before being ratified. </li> </ol></div></div> <div style="overflow: auto"> <table class="wikitable" style="text-align:center;"> <caption>32-bit RISC-V instruction formats </caption> <tbody><tr> <th rowspan="2">Format </th> <th colspan="32">Bit </th></tr> <tr> <th>31</th> <th>30</th> <th>29</th> <th>28</th> <th>27</th> <th>26</th> <th>25</th> <th>24</th> <th>23</th> <th>22</th> <th>21</th> <th>20</th> <th>19</th> <th>18</th> <th>17</th> <th>16</th> <th>15</th> <th>14</th> <th>13</th> <th>12</th> <th>11</th> <th>10</th> <th>9</th> <th>8</th> <th>7</th> <th>6</th> <th>5</th> <th>4</th> <th>3</th> <th>2</th> <th>1</th> <th>0 </th></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Register/register </td> <td colspan="7" style="background:#FFCBDB;">funct7 </td> <td colspan="5" style="background:#dfd;">rs2 </td> <td colspan="5" style="background:#dfd;">rs1 </td> <td colspan="3" style="background:#FFCBDB;">funct3 </td> <td colspan="5" style="background:#ffb7b7;">rd </td> <td colspan="7" style="background:#FFFDD0;"><a href="/wiki/Opcode" title="Opcode">opcode</a> </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Immediate </td> <td colspan="12" style="background:#def;">imm[11:0] </td> <td colspan="5" style="background:#dfd;">rs1 </td> <td colspan="3" style="background:#FFCBDB;">funct3 </td> <td colspan="5" style="background:#ffb7b7;">rd </td> <td colspan="7" style="background:#FFFDD0;">opcode </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Store </td> <td colspan="7" style="background:#def;">imm[11:5] </td> <td colspan="5" style="background:#dfd;">rs2 </td> <td colspan="5" style="background:#dfd;">rs1 </td> <td colspan="3" style="background:#FFCBDB;">funct3 </td> <td colspan="5" style="background:#def;">imm[4:0] </td> <td colspan="7" style="background:#FFFDD0;">opcode </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Branch </td> <td style="background:#def; font-size: 75%;">[12] </td> <td colspan="6" style="background:#def;">imm[10:5] </td> <td colspan="5" style="background:#dfd;">rs2 </td> <td colspan="5" style="background:#dfd;">rs1 </td> <td colspan="3" style="background:#FFCBDB;">funct3 </td> <td colspan="4" style="background:#def;">imm[4:1] </td> <td style="background:#def; font-size: 75%;">[11] </td> <td colspan="7" style="background:#FFFDD0;">opcode </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Upper immediate </td> <td colspan="20" style="background:#def;">imm[31:12] </td> <td colspan="5" style="background:#ffb7b7;">rd </td> <td colspan="7" style="background:#FFFDD0;">opcode </td></tr> <tr> <td style="background: #ececec; color: black; font-weight: bold; vertical-align: middle; text-align: left;" class="table-rh">Jump </td> <td style="background:#def; font-size: 75%;">[20] </td> <td colspan="10" style="background:#def;">imm[10:1] </td> <td style="background:#def; font-size: 75%;">[11] </td> <td colspan="8" style="background:#def;">imm[19:12] </td> <td colspan="5" style="background:#ffb7b7;">rd </td> <td colspan="7" style="background:#FFFDD0;">opcode </td></tr> <tr> <td colspan="33" style="text-align:left; font-size:85%;"> <ul><li>opcode (7 bits): Partially specifies one of the 6 types of instruction formats.</li> <li>funct7 (7 bits) and funct3 (3 bits): These two fields extend the opcode field to specify the operation to be performed.</li> <li>rs1 (5 bits) and rs2 (5 bits): Specify, by index, the first and second operand registers respectively (i.e., source registers).</li> <li>rd (5 bits): Specifies, by index, the destination register to which the computation result will be directed.</li></ul> </td></tr></tbody></table> </div> To name the combinations of functions that may be implemented, a nomenclature is defined to specify them in Chapter 27 of the current ratified Unprivileged ISA Specification. The instruction set base is specified first, coding for RISC-V, the register bit-width, and the variant; e.g., <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64I or <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32E. Then follows letters specifying implemented extensions, in the order of the above table. Each letter may be followed by a major optionally followed by "p" and a minor option number. It defaults to 0 if a minor version number is absent, and 1.0 if all of a version number is absent. Thus <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64IMAFD may be written as <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64I1p0M1p0A1p0F1p0D1p0 or more simply as <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64I1M1A1F1D1. Underscores may be used between extensions for readability, for example <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32I2_M2_A2. <figure typeof="mw:File/Thumb"><a href="/wiki/File:RV32IMAC_Instruction_Set.svg" class="mw-file-description"><img alt="A diagram of the modular instruction set of the RV32IMAC variant, showing all instructions in the base integer ISA and the extensions for Integer Multiplication and Division, Atomic Instructions, and Compressed Instructions." src="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/RV32IMAC_Instruction_Set.svg/600px-RV32IMAC_Instruction_Set.svg.png" decoding="async" width="600" height="385" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/fe/RV32IMAC_Instruction_Set.svg/900px-RV32IMAC_Instruction_Set.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/fe/RV32IMAC_Instruction_Set.svg/1200px-RV32IMAC_Instruction_Set.svg.png 2x" data-file-width="994" data-file-height="638" /></a><figcaption>The modular instruction set of the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32IMAC variant. This is a 32-bit CPU with the Base Integer ISA (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32I) and the ISA extensions for Integer Multiplication and Division (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32M), Atomic Instructions (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32A), and Compressed Instructions (<link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32C).</figcaption></figure> The base, extended integer & floating-point calculations, with synchronization primitives for multi-core computing, are considered to be necessary for general-purpose computing, and thus we have the shorthand, "G". A small 32-bit computer for an embedded system might be <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV32EC. A large 64-bit computer might be <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64GC; i.e., <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">RV64IMAFDCZicsr_Zifencei. With the growth in the number of extensions, the standard now provides for extensions to be named by a single "Z" followed by an alphabetical name and an optional version number. For example, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">Zifencei names the instruction-fetch extension. <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">Zifencei2 and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">Zifencei2p0 name version 2.0 of the same. The first letter following the "Z" by convention indicates the most closely related alphabetical extension category, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">IMAFDQLCBJTPVN. Thus the Zam extension for misaligned atomics relates to the "A" standard extension. Unlike single character extensions, Z extensions must be separated by underscores, grouped by category and then alphabetically within each category. For example, <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">Zicsr_Zifencei_Zam. Extensions specific to supervisor privilege level are named in the same way using "S" for prefix. Extensions specific to hypervisor level are named using "H" for prefix. Machine level extensions are prefixed with the three letters "Zxm". Supervisor, hypervisor and machine level instruction set extensions are named after less privileged extensions. RISC-V developers may create their own non-standard instruction set extensions. These follow the "Z" naming convention, but with "X" as the prefix. They should be specified after all standard extensions, and if multiple non-standard extensions are listed, they should be listed alphabetically. <div class="mw-heading mw-heading4"><h4 id="Profiles_and_platforms">Profiles and platforms</h4>[<a href="/w/index.php?title=RISC-V&action=edit&section=8" title="Edit section: Profiles and platforms">edit</a>]</div> Profiles and platforms for standard ISA choice lists are under discussion. <style data-mw-deduplicate="TemplateStyles:r1244412712">.mw-parser-output .templatequote{overflow:hidden;margin:1em 0;padding:0 32px}.mw-parser-output .templatequotecite{line-height:1.5em;text-align:left;margin-top:0}@media(min-width:500px){.mw-parser-output .templatequotecite{padding-left:1.6em}}</style><blockquote class="templatequote">... This flexibility can be used to highly optimize a specialized design by including only the exact set of ISA features required for an application, but the same flexibility also leads to a combinatorial explosion in possible ISA choices. Profiles specify a much smaller common set of ISA choices that capture the most value for most users, and which thereby enable the software community to focus resources on building a rich software ecosystem. <a href="#cite_note-53">[50]</a></blockquote> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1244412712"><blockquote class="templatequote">The platform specification defines a set of platforms that specify requirements for interoperability between software and hardware. The Platform Policy defines the various terms used in this platform specification. The platform policy also provides the needed detail regarding the scope, coverage, naming, versioning, structure, life cycle and compatibility claims for the platform specification. <a href="#cite_note-54">[51]</a></blockquote> <div class="mw-heading mw-heading3"><h3 id="Register_sets">Register sets</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=9" title="Edit section: Register sets">edit</a>]</div> <table class="wikitable" style="float:right; font-size:84%;"> <caption><a href="/wiki/Assembler_mnemonics" class="mw-redirect" title="Assembler mnemonics">Assembler mnemonics</a> for RISC-V integer and floating-point registers, and their role in the first standard calling convention.<a href="#cite_note-isa20191213-2">[2]</a>: 137  </caption> <tbody><tr> <th>Register name</th> <th>Symbolic name</th> <th>Description</th> <th>Saved by </th></tr> <tr> <th colspan="4">32 <a href="/wiki/Integer_(computing)" class="mw-redirect" title="Integer (computing)">integer</a> registers </th></tr> <tr> <td>x0</td> <td>zero</td> <td>Always zero</td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"> </td></tr> <tr> <td>x1</td> <td>ra</td> <td><a href="/wiki/Return_statement" title="Return statement">Return address</a></td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>x2</td> <td>sp</td> <td><a href="/wiki/Stack_pointer" class="mw-redirect" title="Stack pointer">Stack pointer</a></td> <td style="background:#def;">Callee </td></tr> <tr> <td>x3</td> <td>gp</td> <td><a href="/w/index.php?title=Global_pointer&action=edit&redlink=1" class="new" title="Global pointer (page does not exist)">Global pointer</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"> </td></tr> <tr> <td>x4</td> <td>tp</td> <td><a href="/wiki/Thread_pointer" class="mw-redirect" title="Thread pointer">Thread pointer</a></td> <td data-sort-value="" style="background: var(--background-color-interactive, #ececec); color: var(--color-base, inherit); vertical-align: middle; text-align: center;" class="table-na"> </td></tr> <tr> <td>x5</td> <td>t0</td> <td>Temporary / alternate return address</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>x6–7</td> <td>t1–2</td> <td>Temporaries</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>x8</td> <td>s0/fp</td> <td>Saved register / <a href="/wiki/Frame_pointer" class="mw-redirect" title="Frame pointer">frame pointer</a></td> <td style="background:#def;">Callee </td></tr> <tr> <td>x9</td> <td>s1</td> <td>Saved register</td> <td style="background:#def;">Callee </td></tr> <tr> <td>x10–11</td> <td>a0–1</td> <td><a href="/wiki/Argument_(computer_programming)" class="mw-redirect" title="Argument (computer programming)">Function arguments</a> / return values</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>x12–17</td> <td>a2–7</td> <td>Function arguments</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>x18–27</td> <td>s2–11</td> <td>Saved registers</td> <td style="background:#def;">Callee </td></tr> <tr> <td>x28–31</td> <td>t3–6</td> <td>Temporaries</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <th colspan="4">32 <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point</a> extension registers </th></tr> <tr> <td>f0–7</td> <td>ft0–7</td> <td>Floating-point temporaries</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>f8–9</td> <td>fs0–1</td> <td>Floating-point saved registers</td> <td style="background:#def;">Callee </td></tr> <tr> <td>f10–11</td> <td>fa0–1</td> <td>Floating-point arguments/return values</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>f12–17</td> <td>fa2–7</td> <td>Floating-point arguments</td> <td style="background:#fffdd0;">Caller </td></tr> <tr> <td>f18–27</td> <td>fs2–11</td> <td>Floating-point saved registers</td> <td style="background:#def;">Callee </td></tr> <tr> <td>f28–31</td> <td>ft8–11</td> <td>Floating-point temporaries</td> <td style="background:#fffdd0;">Caller </td></tr></tbody></table> RISC-V has 32 <a href="/wiki/Integer" title="Integer">integer</a> registers (or 16 in the embedded variant),<a href="#cite_note-isa20191213-2">[2]</a>: 13, 33  and when the floating-point extension is implemented, an additional 32 <a href="/wiki/Floating-point_arithmetic" title="Floating-point arithmetic">floating-point</a> registers.<a href="#cite_note-isa20191213-2">[2]</a>: 63  Except for memory access instructions, instructions address only <a href="/wiki/Processor_register" title="Processor register">registers</a>. The first integer register is a <a href="/wiki/Zero_register" title="Zero register">zero register</a>, and the remainder are general-purpose registers. A store to the zero register has no effect, and a read always provides 0. Using the zero register as a placeholder makes for a simpler instruction set. Control and status registers exist, but user-mode programs can access only those used for performance measurement and floating-point management. No instructions exist to save and restore multiple registers. Those were thought to be needless, too complex, and perhaps too slow.<a href="#cite_note-isa2.1-27">[25]</a> <div class="mw-heading mw-heading3"><h3 id="Memory_access">Memory access</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=10" title="Edit section: Memory access">edit</a>]</div> Like many RISC designs, RISC-V is a <a href="/wiki/Load%E2%80%93store_architecture" title="Load–store architecture">load–store architecture</a>: instructions address only registers, with load and store instructions conveying data to and from memory. Most load and store instructions include a 12-bit offset and two register identifiers. One register is the base register. The other register is the destination (for a load) or the source (for a store). The offset is added to a base register to get the address.<a href="#cite_note-isa20191213-2">[2]</a>: 24  Forming the address as a base register plus offset allows single instructions to access data structures. For example, if the base register points to the top of a stack, single instructions can access a subroutine's local variables in the stack. Likewise the load and store instructions can access a record-style structure or a memory-mapped I/O device. Using the constant zero register as a base address allows single instructions to access memory near address zero. Memory is addressed as 8-bit bytes, with instructions being in <a href="/wiki/Little-endian" class="mw-redirect" title="Little-endian">little-endian</a> order,<a href="#cite_note-isa20191213-2">[2]</a>: 9–10  and with data being in the byte order defined by the execution environment interface in which code is running.<a href="#cite_note-isa20191213-2">[2]</a>: 3, 9–10, 24  Words, up to the register size, can be accessed with the load and store instructions. RISC-V was originally specified as little-endian to resemble other familiar, successful computers, for example, <a href="/wiki/X86" title="X86">x86</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 9–10  This also reduces a CPU's complexity and costs slightly less because it reads all sizes of words in the same order. For example, the RISC-V instruction set decodes starting at the lowest-addressed byte of the instruction. Big-endian and bi-endian variants were defined for support of legacy code bases that assume big-endianness.<a href="#cite_note-isa20191213-2">[2]</a>: 9–10  The privileged ISA defines bits in the <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">mstatus and <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r886049734">mstatush registers that indicate and, optionally, control whether M-mode, S-mode, and U-mode memory accesses other than instruction fetches are little-endian or big-endian; those bits may be read-only, in which case the endianness of the implementation is hardwired, or may be writable.<a href="#cite_note-priv-isa-3">[3]</a>: 23–24  An execution environment interface may allow accessed memory addresses not to be aligned to their word width, but accesses to aligned addresses may be faster; for example, simple CPUs may implement unaligned accesses with slow software emulation driven from an alignment failure <a href="/wiki/Interrupt" title="Interrupt">interrupt</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 3, 24–25  Like many RISC instruction sets (and some <a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">complex instruction set computer</a> (CISC) instruction sets, such as <a href="/wiki/X86" title="X86">x86</a> and <a href="/wiki/IBM_System/360" title="IBM System/360">IBM System/360</a> and its successors through <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a>), RISC-V lacks address-modes that write back to the registers. For example, it does not auto-increment.<a href="#cite_note-isa20191213-2">[2]</a>: 24  RISC-V manages memory systems that are shared between CPUs or <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a> by ensuring a thread of execution always sees its memory operations in the programmed order. But between threads and I/O devices, RISC-V is simplified: it doesn't guarantee the order of memory operations, except by specific instructions, such as <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code>. A <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code> instruction guarantees that the results of predecessor operations are visible to successor operations of other threads or I/O devices. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code> can guarantee the order of combinations of both memory and memory-mapped I/O operations. E.g. it can separate memory read and write operations, without affecting I/O operations. Or, if a system can operate I/O devices in parallel with memory, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code> doesn't force them to wait for each other. One CPU with one thread may decode <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code> as <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">nop</code>. Some RISC CPUs (such as <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a>, <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a>, <a href="/wiki/DLX" title="DLX">DLX</a>, and Berkeley's RISC-I) place 16 bits of offset in the loads and stores. They set the upper 16 bits by a load upper word instruction. This permits upper-halfword values to be set easily, without shifting bits. However, most use of the upper half-word instruction makes 32-bit constants, like addresses. RISC-V uses a <a href="/wiki/SPARC" title="SPARC">SPARC</a>-like combination of 12-bit offsets and 20-bit set upper instructions. The smaller 12-bit offset helps compact, 32-bit load and store instructions select two of 32 registers yet still have enough bits to support RISC-V's variable-length instruction coding.<a href="#cite_note-isa20191213-2">[2]</a>: 16  <div class="mw-heading mw-heading3"><h3 id="Immediates">Immediates</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=11" title="Edit section: Immediates">edit</a>]</div> RISC-V handles 32-bit constants and addresses with instructions that set the upper 20 bits of a 32-bit register. Load upper immediate <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lui</code> loads 20 bits into bits 31 through 12. Then a second instruction such as <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">addi</code> can set the bottom 12 bits. Small numbers or addresses can be formed by using the zero register instead of <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lui</code>. This method is extended to permit <a href="/wiki/Position-independent_code" title="Position-independent code">position-independent code</a> by adding an instruction, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">auipc</code> that generates 20 upper address bits by adding an offset to the program counter and storing the result into a base register. This permits a program to generate 32-bit addresses that are relative to the program counter. The base register can often be used as-is with the 12-bit offsets of the loads and stores. If needed, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">addi</code> can set the lower 12 bits of a register. In 64-bit and 128-bit ISAs,<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lui</code> and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">auipc</code> sign-extend the result to get the larger address.<a href="#cite_note-isa20191213-2">[2]</a>: 37  Some fast CPUs may interpret combinations of instructions as single fused instructions. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lui</code> or <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">auipc</code> are good candidates to fuse with <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code>, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">addi</code>, loads or stores. <div class="mw-heading mw-heading3"><h3 id="Subroutine_calls,_jumps,_and_branches">Subroutine calls, jumps, and branches</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=12" title="Edit section: Subroutine calls, jumps, and branches">edit</a>]</div> RISC-V's subroutine call <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code> (jump and link) places its return address in a register. This is faster in many computer designs, because it saves a memory access compared to systems that push a return address directly on a stack in memory. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code> has a 20-bit signed (<a href="/wiki/Two%27s_complement" title="Two's complement">two's complement</a>) offset. The offset is multiplied by 2, then added to the PC (program counter) to generate a relative address to a 32-bit instruction. If the resulting address is not 32-bit aligned (i.e. evenly divisible by 4), the CPU may force an <a href="/wiki/Exception_handling" title="Exception handling">exception</a>.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  RISC-V CPUs jump to calculated addresses using a jump and link-register, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code> instruction. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code> is similar to <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code>, but gets its destination address by adding a 12-bit offset to a base register. (In contrast,<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code> adds a larger 20-bit offset to the PC.) <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code>'s bit format is like the register-relative loads and stores. Like them, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code> can be used with the instructions that set the upper 20 bits of a base register to make 32-bit branches, either to an absolute address (using <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lui</code>) or a PC-relative one (using <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">auipc</code> for position-independent code). (Using a constant zero base address allows single-instruction calls to a small (the offset), fixed positive or negative address.) RISC-V recycles <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code> and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code> to get unconditional 20-bit PC-relative jumps and unconditional register-based 12-bit jumps. Jumps just make the linkage register 0 so that no return address is saved.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  RISC-V also recycles <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code> to return from a subroutine: To do this, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code>'s base register is set to be the linkage register saved by <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jal</code> or <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code>. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">jalr</code>'s offset is zero and the linkage register is zero, so that there is no offset, and no return address is saved. Like many RISC designs, in a subroutine call, a RISC-V compiler must use individual instructions to save registers to the stack at the start, and then restore these from the stack on exit. RISC-V has no save multiple or restore multiple register instructions. These were thought to make the CPU too complex, and possibly slow.<a href="#cite_note-riscvc-55">[52]</a> This can take more code space. Designers planned to reduce code size with library routines to save and restore registers.<a href="#cite_note-isacompressed-56">[53]</a> RISC-V has no <a href="/wiki/Condition_code_register" class="mw-redirect" title="Condition code register">condition code register</a> or <a href="/wiki/Carry_bit" class="mw-redirect" title="Carry bit">carry bit</a>. The designers believed that condition codes make fast CPUs more complex by forcing interactions between instructions in different stages of execution. This choice makes multiple-precision arithmetic more complex. Also, a few numerical tasks need more energy. As a result, <a href="/wiki/Predication_(computer_architecture)" title="Predication (computer architecture)">predication</a> (the conditional execution of instructions) is not supported. The designers claim that very fast, out-of-order CPU designs do predication anyway, by doing the comparison branch and conditional code in parallel, then discarding the unused path's effects. They also claim that even in simpler CPUs, predication is less valuable than <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction</a>, which can prevent most stalls associated with conditional branches. Code without predication is larger, with more branches, but they also claim that a <a href="/wiki/Compressed_instruction_set" title="Compressed instruction set">compressed instruction set</a> (such as RISC-V's set C) solves that problem in most cases.<a href="#cite_note-isa2.1-27">[25]</a>[<a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">failed verification</a>] Instead, RISC-V has short branches that perform comparisons: equal, not-equal, less-than, unsigned less-than, greater-than or equal and unsigned greater-than or equal. Ten comparison-branch operations are implemented with only six instructions, by reversing the order of operands in the <a href="/wiki/Assembly_language" title="Assembly language">assembler</a>. For example, branch if greater than can be done by less-than with a reversed order of operands.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  The comparing branches have a twelve-bit signed range, and jump relative to the PC.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  Unlike some RISC architectures, RISC-V does not include a <a href="/wiki/Branch_delay_slot" class="mw-redirect" title="Branch delay slot">branch delay slot</a>, a position after a branch instruction that can be filled with an instruction that is executed whether or not the branch is taken.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  RISC-V omits a branch delay slot because it complicates multicycle CPUs, superscalar CPUs, and long pipelines. Dynamic <a href="/wiki/Branch_predictor" title="Branch predictor">branch predictors</a> have succeeded well enough to reduce the need for delayed branches.<a href="#cite_note-isa2.1-27">[25]</a> On the first encounter with a branch, RISC-V CPUs should assume that a negative relative branch (i.e. the sign bit of the offset is "1") will be taken.<a href="#cite_note-isa20191213-2">[2]</a>: 20–23, Section 2.5  This assumes that a backward branch is a loop, and provides a default direction so that simple pipelined CPUs can fill their pipeline of instructions. Other than this, RISC-V does not require <a href="/wiki/Branch_prediction" class="mw-redirect" title="Branch prediction">branch prediction</a>, but core implementations are allowed to add it. RV32I reserves a "HINT" instruction space that presently does not contain any hints on branches;<a href="#cite_note-isa20191213-2">[2]</a>: 28–29, Section 2.9  RV64I does the same.<a href="#cite_note-isa20191213-2">[2]</a>: 38–39, Section 5.4  <div class="mw-heading mw-heading3"><h3 id="Arithmetic_and_logic_sets">Arithmetic and logic sets</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=13" title="Edit section: Arithmetic and logic sets">edit</a>]</div> RISC-V segregates math into a minimal set of <a href="/wiki/Integer" title="Integer">integer</a> instructions (set I) with <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">add, subtract, shift, bitwise logic</a> and comparing-branches. These can simulate most of the other RISC-V instruction sets with software. (The atomic instructions are a notable exception.) RISC-V integer instructions lack the count leading zero and bit-field operations normally used to speed software floating-point in a pure-integer processor, However, while nominally in the bit manipulation extension, the ratified Zbb, Zba and Zbs extensions contain further integer instructions including a count leading zero instruction. The integer multiplication instructions (set M) include signed and unsigned multiply and divide. Double-precision integer multiplies and divides are included, as multiplies and divides that produce the high word of the result. The ISA document recommends that implementors of CPUs and compilers fuse a standardized sequence of high and low multiply and divide instructions to one operation if possible.<a href="#cite_note-isa20191213-2">[2]</a>: 43–45  The <a href="/wiki/Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> instructions (set F) include single-precision arithmetic and also comparison-branches similar to the integer arithmetic. It requires an additional set of 32 floating-point registers. These are separate from the integer registers. The double-precision floating point instructions (set D) generally assume that the floating-point registers are 64-bit (i.e., double-width), and the F subset is coordinated with the D set. A quad-precision 128-bit floating-point ISA (Q) is also defined.<a href="#cite_note-isa20191213-2">[2]</a>: 63–82  RISC-V computers without floating-point can use a floating-point software library. RISC-V does not cause <a href="/wiki/Exception_handling" title="Exception handling">exceptions</a> on arithmetic errors, including <a href="/wiki/Overflow_flag" title="Overflow flag">overflow</a>,<a href="#cite_note-isa20191213-2">[2]</a>: 17–20  underflow, subnormal, and divide by zero.<a href="#cite_note-isa20191213-2">[2]</a>: 44–45  Instead, both integer and floating-point arithmetic produce reasonable default values, and floating-point instructions set status bits.<a href="#cite_note-isa20191213-2">[2]</a>: 66  Divide-by-zero can be discovered by one branch after the division.<a href="#cite_note-isa20191213-2">[2]</a>: 44–45  The status bits can be tested by an operating system or periodic interrupt. <div class="mw-heading mw-heading3"><h3 id="Atomic_memory_operations">Atomic memory operations</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=14" title="Edit section: Atomic memory operations">edit</a>]</div> RISC-V supports computers that share memory between multiple CPUs and <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>. RISC-V's standard memory consistency model is <a href="/wiki/Release_consistency" title="Release consistency">release consistency</a>. That is, loads and stores may generally be reordered, but some loads may be designated as acquire operations which must precede later memory accesses, and some stores may be designated as release operations which must follow earlier memory accesses.<a href="#cite_note-isa20191213-2">[2]</a>: 83–94  The base instruction set includes minimal support in the form of a <a href="/wiki/Fence_instruction" class="mw-redirect" title="Fence instruction"><code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence</code> instruction</a> to enforce memory ordering.<a href="#cite_note-isa20191213-2">[2]</a>: 26–27  Although this is sufficient (<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence r, rw</code> provides acquire and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">fence rw, w</code> provides release), combined operations can be more efficient.<a href="#cite_note-isa20191213-2">[2]</a>: Chapter 8  The atomic memory operation extension supports two types of atomic memory operations for release consistency. First, it provides general purpose <a href="/wiki/Load-link/store-conditional" title="Load-link/store-conditional">load-reserved <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lr</code> and store-conditional <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">sc</code></a> instructions. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lr</code> performs a load, and tries to reserve that address for its thread. A later store-conditional <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">sc</code> to the reserved address will be performed only if the reservation is not broken by an intervening store from another source. If the store succeeds, a zero is placed in a register. If it failed, a non-zero value indicates that software needs to retry the operation. In either case, the reservation is released.<a href="#cite_note-isa20191213-2">[2]</a>: Chapter 8  The second group of atomic instructions perform <a href="/wiki/Read-modify-write" class="mw-redirect" title="Read-modify-write">read-modify-write</a> sequences: a load (which is optionally a load-acquire) to a destination register, then an operation between the loaded value and a source register, then a store of the result (which may optionally be a store-release). Making the memory barriers optional permits combining the operations. The optional operations are enabled by acquire and release bits which are present in every atomic instruction. RISC-V defines nine possible operations: swap (use source register value directly); add; bitwise and, or, and exclusive-or; and signed and unsigned minimum and maximum.<a href="#cite_note-isa20191213-2">[2]</a>: Chapter 8  A system design may optimize these combined operations more than <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lr</code> and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">sc</code>. For example, if the destination register for a swap is the constant zero, the load may be skipped. If the value stored is unmodified since the load, the store may be skipped.<a href="#cite_note-isa2.2-17">[15]</a>: 44  The <a href="/wiki/IBM_System/370" title="IBM System/370">IBM System/370</a> and its successors including <a href="/wiki/Z/Architecture" title="Z/Architecture">z/Architecture</a>, and <a href="/wiki/X86" title="X86">x86</a>, both implement a <a href="/wiki/Compare-and-swap" title="Compare-and-swap">compare-and-swap</a> (<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code>) instruction, which tests and conditionally updates a location in memory: if the location contains an expected old value, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code> replaces it with a given new value; it then returns an indication of whether it made the change. However, a simple load-type instruction is usually performed before the <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code> to fetch the old value. The classic problem is that if a thread reads (loads) a value A, calculates a new value C, and then uses (<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code>) to replace A with C, it has no way to know whether concurrent activity in another thread has replaced A with some other value B and then restored the A in between. In some algorithms (e.g., ones in which the values in memory are pointers to dynamically allocated blocks), this <a href="/wiki/ABA_problem" title="ABA problem">ABA problem</a> can lead to incorrect results. The most common solution employs a double-wide <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code> instruction to update both the pointer and an adjacent counter; unfortunately, such an instruction requires a special instruction format to specify multiple registers, performs several reads and writes, and can have complex bus operation.<a href="#cite_note-isa20191213-2">[2]</a>: 48–49  The <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lr</code>/<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">sc</code> alternative is more efficient. It usually requires only one memory load, and minimizing slow memory operations is desirable. It's also exact: it controls all accesses to the memory cell, rather than just assuring a bit pattern. However, unlike <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">cas</code>, it can permit <a href="/wiki/Livelock" class="mw-redirect" title="Livelock">livelock</a>, in which two or more threads repeatedly cause each other's instructions to fail. RISC-V guarantees forward progress (no livelock) if the code follows rules on the timing and sequence of instructions: 1) It must use only the I subset. 2) To prevent repetitive cache misses, the code (including the retry loop) must occupy no more than 16 consecutive instructions. 3) It must include no system or fence instructions, or taken backward branches between the <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">lr</code> and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">sc</code>. 4) The backward branch to the retry loop must be to the original sequence.<a href="#cite_note-isa20191213-2">[2]</a>: 48–49  The specification gives an example of how to use the read-modify-write atomic instructions to lock a data structure.<a href="#cite_note-isa20191213-2">[2]</a>: 54  <div class="mw-heading mw-heading3"><h3 id="Compressed_subset">Compressed subset</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=15" title="Edit section: Compressed subset">edit</a>]</div> The standard RISC-V ISA specifies that all instructions are 32 bits. This makes for a particularly simple implementation, but like other RISC processors with 32-bit instruction encoding, results in larger code size than in instruction sets with variable-length instructions.<a href="#cite_note-isa20191213-2">[2]</a>: 99 <a href="#cite_note-riscvc-55">[52]</a> To compensate, RISC-V's 32-bit instructions are actually 30 bits; <style data-mw-deduplicate="TemplateStyles:r1154941027">.mw-parser-output .frac{white-space:nowrap}.mw-parser-output .frac .num,.mw-parser-output .frac .den{font-size:80%;line-height:0;vertical-align:super}.mw-parser-output .frac .den{vertical-align:sub}.mw-parser-output .sr-only{border:0;clip:rect(0,0,0,0);clip-path:polygon(0px 0px,0px 0px,0px 0px);height:1px;margin:-1px;overflow:hidden;padding:0;position:absolute;width:1px}</style>3⁄4 of the <a href="/wiki/Opcode" title="Opcode">opcode</a> space is reserved for an optional (but recommended) variable-length compressed instruction set, RVC, that includes 16-bit instructions. As in <a href="/wiki/ARM_Thumb" class="mw-redirect" title="ARM Thumb">ARM Thumb</a> and <a href="/wiki/MIPS_architecture#Application-specific_extensions" title="MIPS architecture">MIPS16</a>, the compressed instructions are simply alternative encodings for a subset of the larger instructions. Unlike the ARM or MIPS compressed sets, space was reserved from the start so there is no separate operating mode. Standard and compressed instructions may be intermixed freely.<a href="#cite_note-isa20191213-2">[2]</a>: 97 <a href="#cite_note-riscvc-55">[52]</a> (Extension letter is C.)<a href="#cite_note-isa20191213-2">[2]</a>: 97  Because (like Thumb-1 and MIPS16) the compressed instructions are simply alternate encodings (aliases) for a selected subset of larger instructions, the compression can be implemented in the assembler, and it is not essential for the compiler to even know about it. A prototype of RVC was tested in 2011.<a href="#cite_note-riscvc-55">[52]</a> The prototype code was 20% smaller than an <a href="/wiki/X86" title="X86">x86</a> PC and <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a> compressed code, and 2% larger than ARM <a href="/wiki/Thumb-2" class="mw-redirect" title="Thumb-2">Thumb-2</a> code.<a href="#cite_note-riscvc-55">[52]</a> It also substantially reduced both the needed cache memory and the estimated power use of the memory system.<a href="#cite_note-riscvc-55">[52]</a> The researcher intended to reduce the code's binary size for small computers, especially <a href="/wiki/Embedded_computer" class="mw-redirect" title="Embedded computer">embedded computer</a> systems. The prototype included 33 of the most frequently used instructions, recoded as compact 16-bit formats using operation codes previously reserved for the compressed set.<a href="#cite_note-riscvc-55">[52]</a> The compression was done in the <a href="/wiki/Assembly_language" title="Assembly language">assembler</a>, with no changes to the compiler. Compressed instructions omitted fields that are often zero, used small immediate values or accessed subsets (16 or 8) of the registers. <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">addi</code> is very common and often compressible.<a href="#cite_note-riscvc-55">[52]</a> Much of the difference in size compared to ARM's Thumb set occurred because RISC-V, and the prototype, have no instructions to save and restore multiple registers. Instead, the compiler generated conventional instructions that access the stack. The prototype RVC assembler then often converted these to compressed forms that were half the size. However, this still took more code space than the ARM instructions that save and restore multiple registers. The researcher proposed to modify the compiler to call library routines to save and restore registers. These routines would tend to remain in a code cache and thus run fast, though probably not as fast as a save-multiple instruction.<a href="#cite_note-riscvc-55">[52]</a> Standard RVC requires occasional use of 32-bit instructions. Several nonstandard RVC proposals are complete, requiring no 32-bit instructions, and are said to have higher densities than standard RVC.<a href="#cite_note-auto-57">[54]</a><a href="#cite_note-Brussee-58">[55]</a> Another proposal builds on these, and claims to use less coding range as well.<a href="#cite_note-59">[56]</a> <div class="mw-heading mw-heading3"><h3 id="Embedded_subset">Embedded subset</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=16" title="Edit section: Embedded subset">edit</a>]</div> An instruction set for the smallest embedded CPUs (set E) is reduced in other ways: Only 16 of the 32 integer registers are supported.<a href="#cite_note-isa20191213-2">[2]</a>: Chapter 4  All current extensions may be used; a floating-point extension to use the integer registers for floating-point values is being considered. The privileged instruction set supports only machine mode, user mode and memory schemes that use base-and-bound address relocation.<a href="#cite_note-priv-isa-3">[3]</a> Discussion has occurred for a microcontroller profile for RISC-V, to ease development of deeply embedded systems. It centers on faster, simple C-language support for interrupts, simplified security modes and a simplified <a href="/wiki/POSIX" title="POSIX">POSIX</a> application binary interface.<a href="#cite_note-60">[57]</a> Correspondents have also proposed smaller, non-standard, 16-bit RV16E ISAs: Several serious proposals would use the 16-bit C instructions with 8 × 16-bit registers.<a href="#cite_note-Brussee-58">[55]</a><a href="#cite_note-auto-57">[54]</a> An April fools' joke proposed a very practical arrangement: Utilize 16 × 16-bit integer registers, with the standard EIMC ISAs (including 32-bit instructions.) The joke was to use <a href="/wiki/Bank_switching" title="Bank switching">bank switching</a> when a 32-bit CPU would be clearly superior with the larger address space.<a href="#cite_note-61">[58]</a> <div class="mw-heading mw-heading3"><h3 id="Privileged_instruction_set">Privileged instruction set</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=17" title="Edit section: Privileged instruction set">edit</a>]</div> RISC-V's ISA includes a separate privileged instruction set specification, which mostly describes three privilege levels plus an orthogonal hypervisor mode. As of December 2021<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, version 1.12 is ratified by RISC-V International.<a href="#cite_note-priv-isa-3">[3]</a> Version 1.12 of the specification supports several types of computer systems: <ol><li>Systems that have only machine mode, perhaps for simple embedded systems,</li> <li>Systems with both machine mode (for a simple <a href="/wiki/Supervisory_program" title="Supervisory program">supervisor</a>) and user-mode to implement relatively secure embedded systems,</li> <li>Systems with machine-mode, supervisor mode (for operating system) and user-modes for typical operating systems.</li></ol> These correspond roughly to systems with up to four rings of privilege and security, at most: machine, hypervisor, supervisor and user. Each layer also is expected to have a thin layer of standardized supporting software that communicates to a more-privileged layer, or hardware.<a href="#cite_note-priv-isa-3">[3]</a> The ISA also includes a hypervisor mode that is <a href="/wiki/Orthogonality_(programming)" title="Orthogonality (programming)">orthogonal</a> to the user and supervisor modes.<a href="#cite_note-62">[59]</a> The basic feature is a configuration bit that either permits supervisor-level code to access hypervisor registers, or causes an interrupt on accesses. This bit lets supervisor mode directly handle the hardware needed by a hypervisor. This simplifies the implementation of hypervisors that are hosted by an operating system. This is a popular mode to run warehouse-scale computers. To support non-hosted hypervisors, the bit can cause these accesses to interrupt to a hypervisor. The design also simplifies nesting of hypervisors, in which a hypervisor runs under a hypervisor, and if necessary it lets the kernel use hypervisor features within its own kernel code. As a result, the hypervisor form of the ISA supports five modes: machine, supervisor, user, supervisor-under-hypervisor and user-under-supervisor. The privileged instruction set specification explicitly defines hardware <a href="/wiki/Thread_(computing)" title="Thread (computing)">threads</a>, or harts. Multiple hardware threads are a common practice in more-capable computers. When one thread is stalled, waiting for memory, others can often proceed. Hardware threads can help make better use of the large number of registers and execution units in fast out-of-order CPUs. Finally, hardware threads can be a simple, powerful way to handle <a href="/wiki/Interrupt" title="Interrupt">interrupts</a>: No saving or restoring of registers is required, simply executing a different hardware thread. However, the only hardware thread required in a RISC-V computer is thread zero.<a href="#cite_note-priv-isa-3">[3]</a> Interrupts and exceptions are handled together. Exceptions are caused by instruction execution including illegal instructions and system calls, while interrupts are caused by external events. The existing control and status register definitions support RISC-V's error and memory exceptions, and a small number of interrupts, typically via an "advanced core local interruptor" (ACLINT).<a href="#cite_note-63">[60]</a> For systems with more interrupts, the specification also defines a <a href="/w/index.php?title=Platform-level_interrupt_controller&action=edit&redlink=1" class="new" title="Platform-level interrupt controller (page does not exist)">platform-level interrupt controller</a> (PLIC) to coordinate large number of interrupts among multiple processors. Interrupts always start at the highest-privileged machine level, and the control registers of each level have explicit forwarding bits to route interrupts to less-privileged code. For example, the hypervisor need not include software that executes on each interrupt to forward an interrupt to an operating system. Instead, on set-up, it can set bits to forward the interrupt.<a href="#cite_note-priv-isa-3">[3]</a> Several memory systems are supported in the specification. Physical-only is suited to the simplest embedded systems. There are also four <a href="/wiki/UNIX" class="mw-redirect" title="UNIX">UNIX</a>-style <a href="/wiki/Virtual_memory" title="Virtual memory">virtual memory</a> systems for memory cached in mass-storage systems. The virtual memory systems support <a href="/wiki/Memory_management_unit" title="Memory management unit">MMU</a> with four sizes, with addresses sized 32, 39, 48 and 57 bits. All virtual memory systems support 4 KiB pages, multilevel page-table trees and use very similar algorithms to walk the page table trees. All are designed for either hardware or software page-table walking. To optionally reduce the cost of page table walks, super-sized pages may be leaf pages in higher levels of a system's page table tree. SV32 is only supported on 32-bit implementations, has a two-layer page table tree and supports 4 MiB superpages. SV39 has a three level page table, and supports 2 MiB superpages and 1 GiB gigapages. SV48 is required to support SV39. It also has a 4-level page table and supports 2 MiB superpages, 1 GiB gigapages, and 512 GiB terapages. SV57 has a 5-level page table and supports 2 MiB superpages, 1 GiB gigapages, 512 GiB terapages and 256 TiB petapages. Superpages are aligned on the page boundaries for the next-lowest size of page.<a href="#cite_note-priv-isa-3">[3]</a> <div class="mw-heading mw-heading3"><h3 id="Bit_manipulation">Bit manipulation</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=18" title="Edit section: Bit manipulation">edit</a>]</div> Some bit-manipulation ISA extensions were ratified in November 2021 (Zba, Zbb, Zbc, Zbs).<a href="#cite_note-bitmanip_1_0-50">[47]</a> The Zba, Zbb, and Zbs extensions are arguably extensions of the standard I integer instructions: Zba contains instructions to speed up the computation of the addresses of array elements in arrays of datatypes of size 2, 4, or 8 bytes (sh1add, sh2add, sh3add), and for 64 (and 128) bit processors when indexed with unsigned integers (add.uw, sh1add.uw, sh2add.uw, sh3add.uw and slli.uw). The Zbb instructions contains operations to count leading, trailing 0 bits or all 1 bits in a full and 32 word operations (clz, clzw, ctz, ctzw, cpop, cpopw), byte order reversion (rev8), logical instructions with negation of the second input (andn,orn, xnor), sign and zero extension (sext.b, sext.h, zext.h) that could not be provided as special cases of other instructions (andi, addiw, add.wu), min and max of (signed and unsigned) integers, (left and right) rotation of bits in a register and 32-bit words (rori,roriw, ror, rorw, rol, rolw), and a byte wise "or combine" operation which allows detection of a zero byte in a full register, useful for handling C-style null terminated strings functions. The Zbs extension allows setting, getting, clearing, and toggling individual bits in a register by their index (bseti, bset, bexti, bext, bclri, bclr, binvi,binv). The Zbc extension has instructions for "carryless multiplication", which does the multiplication of <a href="/wiki/Polynomials" class="mw-redirect" title="Polynomials">polynomials</a> over the <a href="/wiki/Galois_field" class="mw-redirect" title="Galois field">Galois field</a> GF(2) (clmul, clmulh, clmulr). These are useful for cryptography and CRC checks of data integrity. Done well, a more specialised bit-manipulation subset can aid cryptographic, graphic, and mathematical operations. Further instructions that have been discussed include instructions to shift in ones, a generalized bit-reverse, shuffle and crossbar permutations, bit-field place, extract and deposit pack two words, bytes or halfwords in one register, CRC instructions, bit-matrix operations (RV64 only), conditional mix, conditional move, funnel shifts. The criteria for inclusion documented in the draft were compliant with RISC-V philosophies and ISA formats, substantial improvements in code density or speed (i.e., at least a 3-for-1 reduction in instructions), and substantial real-world applications, including preexisting compiler support. Version 0.93 of the bit-manipulation extension includes those instructions;<a href="#cite_note-64">[61]</a> some of them are now in version 1.0.1 of the scalar and <a href="/wiki/Entropy_source" class="mw-redirect" title="Entropy source">entropy source</a> instructions cryptography extension.<a href="#cite_note-scalar_crypto_1_0_1-52">[49]</a> <div class="mw-heading mw-heading3"><h3 id="Packed_SIMD">Packed SIMD</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=19" title="Edit section: Packed SIMD">edit</a>]</div> Packed-SIMD instructions are widely used by commercial CPUs to inexpensively accelerate multimedia and other <a href="/wiki/Digital_signal_processing" title="Digital signal processing">digital signal processing</a>.<a href="#cite_note-isa2.1-27">[25]</a> For simple, cost-reduced RISC-V systems, the base ISA's specification proposed to use the floating-point registers' bits to perform parallel single instruction, multiple data (<a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a>) sub-word arithmetic. In 2017 a vendor published a more detailed proposal to the mailing list, and this can be cited as version 0.1.<a href="#cite_note-andes_simd-65">[62]</a> As of 2019<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, the efficiency of this proposed ISA varies from 2x to 5x a base CPU for a variety of DSP codecs.<a href="#cite_note-66">[63]</a> The proposal lacked instruction formats and a license assignment to RISC-V International, but it was reviewed by the mailing list.<a href="#cite_note-andes_simd-65">[62]</a> Some unpopular parts of this proposal were that it added a condition code, the first in a RISC-V design, linked adjacent registers (also a first), and has a loop counter that can be difficult to implement in some microarchitectures. <div class="mw-heading mw-heading3"><h3 id="Vector_set">Vector set</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=20" title="Edit section: Vector set">edit</a>]</div> The proposed <a href="/wiki/Vector_processor" title="Vector processor">vector-processing</a> instruction set may make the packed <a href="/wiki/SIMD" class="mw-redirect" title="SIMD">SIMD</a> set obsolete. The designers hope to have enough flexibility that a CPU can implement vector instructions in a standard processor's registers. This would enable minimal implementations with similar performance to a multimedia ISA, as above. However, a true vector coprocessor could execute the same code with higher performance.<a href="#cite_note-vect-67">[64]</a> As of 19 September 2021<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, the vector extension is at version 1.0.<a href="#cite_note-vect-1.0-68">[65]</a> It is a conservative, flexible design of a general-purpose mixed-precision vector processor, suitable to execute <a href="/wiki/Compute_kernel" title="Compute kernel">compute kernels</a>. Code would port easily to CPUs with differing vector lengths, ideally without recompiling.<a href="#cite_note-vect-67">[64]</a> In contrast, short-vector SIMD extensions are less convenient. These are used in <a href="/wiki/X86" title="X86">x86</a>, ARM and <a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a>. In these, a change in word-width forces a change to the instruction set to expand the vector registers (in the case of x86, from 64-bit <a href="/wiki/MMX_(instruction_set)" title="MMX (instruction set)">MMX</a> registers to 128-bit <a href="/wiki/Streaming_SIMD_Extensions" title="Streaming SIMD Extensions">Streaming SIMD Extensions</a> (SSE), to 256-bit <a href="/wiki/Advanced_Vector_Extensions" title="Advanced Vector Extensions">Advanced Vector Extensions</a> (AVX), and <a href="/wiki/AVX-512" title="AVX-512">AVX-512</a>). The result is a growing instruction set, and a need to port working code to the new instructions. In the RISC-V vector ISA, rather than fix the vector length in the architecture, instructions (<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">vsetvli</code>, <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">vsetivli</code>, and <code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">vsetvl</code>) are available which take a requested size and sets the vector length to the minimum of the hardware limit and the requested size. So, the RISC-V proposal is more like a <a href="/wiki/Cray-1" title="Cray-1">Cray</a>'s long-vector design or ARM's Scalable Vector Extension. That is, each vector in up to 32 vectors is the same length.<a href="#cite_note-vect-1.0-68">[65]</a>: 25  The application specifies the total vector width it requires, and the processor determines the vector length it can provide with available on-chip resources. This takes the form of an instruction (<code class="mw-highlight mw-highlight-lang-text mw-content-ltr" style="" dir="ltr">vsetcfg</code>) with four immediate operands, specifying the number of vector registers of each available width needed. The total must be no more than the addressable limit of 32, but may be less if the application does not require them all. The vector length is limited by the available on-chip storage divided by the number of bytes of storage needed for each entry. (Added hardware limits may also exist, which in turn may permit SIMD-style implementations.)<a href="#cite_note-vect-67">[64]</a> Outside of vector loops, the application can zero the number of requested vector registers, saving the operating system the work of preserving them on <a href="/wiki/Context_switch" title="Context switch">context switches</a>.<a href="#cite_note-vect-67">[64]</a> The vector length is not only architecturally variable, but designed to vary at run time also. To achieve this flexibility, the instruction set is likely to use variable-width data paths and variable-type operations using polymorphic overloading.<a href="#cite_note-vect-67">[64]</a> The plan is that these can reduce the size and complexity of the ISA and compiler.<a href="#cite_note-vect-67">[64]</a> Recent experimental vector processors with variable-width data paths also show profitable increases in operations per: second (speed), area (lower cost), and watt (longer battery life).<a href="#cite_note-69">[66]</a> Unlike a typical modern <a href="/wiki/Graphics_processing_unit" title="Graphics processing unit">graphics processing unit</a>, there are no plans to provide special hardware to support <a href="/wiki/Branch_predication" class="mw-redirect" title="Branch predication">branch predication</a>. Instead, lower cost compiler-based predication will be used.<a href="#cite_note-vect-67">[64]</a><a href="#cite_note-70">[67]</a> <div class="mw-heading mw-heading3"><h3 id="External_debug_system">External debug system</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=21" title="Edit section: External debug system">edit</a>]</div> There is a preliminary specification for RISC-V's hardware-assisted <a href="/wiki/Debugger" title="Debugger">debugger</a>. The debugger will use a transport system such as Joint Test Action Group (<a href="/wiki/JTAG" title="JTAG">JTAG</a>) or Universal Serial Bus (<a href="/wiki/USB" title="USB">USB</a>) to access debug registers. A standard hardware debug interface may support either a standardized abstract interface or instruction feeding.<a href="#cite_note-debug-71">[68]</a><a href="#cite_note-72">[69]</a> As of January 2017<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, the exact form of the abstract interface remains undefined, but proposals include a memory mapped system with standardized addresses for the registers of debug devices or a command register and a data register accessible to the communication system.<a href="#cite_note-debug-71">[68]</a> Correspondents claim that similar systems are used by <a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a>'s <a href="/wiki/Background_debug_mode_interface" title="Background debug mode interface">background debug mode interface</a> (BDM) for some CPUs, <a href="/wiki/ARM_architecture" class="mw-redirect" title="ARM architecture">ARM</a>, <a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a>, and <a href="/wiki/Aeroflex" title="Aeroflex">Aeroflex</a>'s <a href="/wiki/LEON" title="LEON">LEON</a>.<a href="#cite_note-debug-71">[68]</a> In instruction feeding, the CPU will process a debug exception to execute individual instructions written to a register. This may be supplemented with a data-passing register and a module to directly access the memory. Instruction feeding lets the debugger access the computer exactly as software would. It also minimizes changes in the CPU, and adapts to many types of CPU. This was said to be especially apt for RISC-V because it is designed explicitly for many types of computers. The data-passing register allows a debugger to write a data-movement loop to RAM, and then execute the loop to move data into or out of the computer at a speed near the maximum speed of the debug system's data channel.<a href="#cite_note-debug-71">[68]</a> Correspondents say that similar systems are used by <a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a> <a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a>, <a href="/wiki/Intel_Quark" title="Intel Quark">Intel Quark</a>, <a href="/wiki/Tensilica" title="Tensilica">Tensilica</a>'s <a href="/wiki/Xtensa" class="mw-redirect" title="Xtensa">Xtensa</a>, and for <a href="/wiki/Freescale" class="mw-redirect" title="Freescale">Freescale</a> <a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> CPUs' <a href="/wiki/Background_debug_mode_interface" title="Background debug mode interface">background debug mode interface</a> (BDM).<a href="#cite_note-debug-71">[68]</a> A vendor proposed a hardware trace subsystem for standardization, donated a conforming design, and initiated a review.<a href="#cite_note-73">[70]</a><a href="#cite_note-74">[71]</a> The proposal is for a hardware module that can trace code execution on most RISC-V CPUs. To reduce the data rate, and permit simpler or less-expensive paths for the trace data, the proposal does not generate trace data that can be calculated from a binary image of the code. It sends only data that indicates "uninferrable" paths through the program, such as which conditional branches are taken. To reduce the data rates, branches that can be calculated, such as unconditional branches, are not traced. The proposed interface between the module and the control unit is a logic signal for each uninferrable type of instruction. Addresses and other data are to be provided in a specialized bus attached to appropriate data sources in a CPU. The data structure sent to an external trace unit is a series of short messages with the needed data. The details of the data channel are intentionally not described in the proposal, because several are likely to make sense. <div class="mw-heading mw-heading2"><h2 id="Implementations">Implementations</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=22" title="Edit section: Implementations">edit</a>]</div> The RISC-V organization maintains a list of RISC-V CPU and SoC implementations.<a href="#cite_note-75">[72]</a> Due to trade wars and possible sanctions that would prevent China from accessing proprietary ISAs, as of 2023 the country was planning to shift most of its CPU and MCU architectures to RISC-V cores.<a href="#cite_note-76">[73]</a> In 2023, the European Union was set to provide 270 million euros within a so-called Framework Partnership Agreement (FPA) to a single company that was able and willing to carry out a RISC-V CPU development project aimed at supercomputers, servers, and data centers.<a href="#cite_note-77">[74]</a> The European Union's aim was to become independent from political developments in other countries and to "strengthen its digital sovereignty and set standards, rather than following those of others."<a href="#cite_note-78">[75]</a> <div class="mw-heading mw-heading3"><h3 id="Existing">Existing</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=23" title="Edit section: Existing">edit</a>]</div> Existing proprietary implementations include: <ul><li><a href="/wiki/Allwinner_Technology" title="Allwinner Technology">Allwinner Technology</a> has implemented the XuanTie C906 CPU into their D1 Application Processor.<a href="#cite_note-79">[76]</a></li> <li><a href="/wiki/Andes_Technology" title="Andes Technology">Andes Technology Corporation</a> of Hsinchu, Taiwan, a Founding Premier member of RISC-V International.<a href="#cite_note-:1-80">[77]</a> Its RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, vector, superscalar, and/or multicore capabilities.</li> <li>Bouffalo Lab has a series of MCUs based on RISC-V (RV32IMACF, BL60x/BL70x series).<a href="#cite_note-81">[78]</a></li> <li>CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.<a href="#cite_note-82">[79]</a></li> <li><a href="/wiki/Codasip" title="Codasip">Codasip</a> of Munich, Germany, a founding member of RISC-V International,<a href="#cite_note-:1-80">[77]</a> started developing a range of low-power embedded, high-performance embedded and application processor cores in 2015.<a href="#cite_note-83">[80]</a><a href="#cite_note-84">[81]</a><a href="#cite_note-85">[82]</a></li> <li>Cortus, an original founding Platinum member of the RISC-V foundation and the RISC-V International,<a href="#cite_note-:1-80">[77]</a> has several RISC-V implementations. Cortus offers ASIC design services using its large IP portfolio including RISC-V 32/64-bit processors from low-end to very high performance RISC-V OoO processors, digital, analog, RF, security and a complete IDE/toolchain/debug eco-system.</li> <li>Espressif added a RISC-V ULP coprocessor to their <a href="/wiki/ESP32-S2" class="mw-redirect" title="ESP32-S2">ESP32-S2</a> microcontroller.<a href="#cite_note-86">[83]</a> In November 2020 Espressif announced their ESP32-C3, a single-core, 32-bit, RISC-V (RV32IMC) based MCU.<a href="#cite_note-87">[84]</a></li> <li><a href="/wiki/Fraunhofer_Society" title="Fraunhofer Society">Fraunhofer</a> IPMS was the first organization to develop a RISC-V core that can meet functional safety requirements. The IP Core EMSA5 is a 32-bit processor with a five-stage pipeline and is available as a general purpose variant (EMSA5-GP) and as a safety variant (EMSA5-FS) that can meet an <a href="/wiki/ISO_26262" title="ISO 26262">ISO 26262</a> <a href="/wiki/Automotive_Safety_Integrity_Level" title="Automotive Safety Integrity Level">Automotive Safety Integrity Level</a>-D standard.<a href="#cite_note-88">[85]</a></li> <li><a href="/wiki/GigaDevice" title="GigaDevice">GigaDevice</a> of Beijing, China, developed a series of MCUs based on RISC-V (RV32IMAC, GD32V series) in 2019,<a href="#cite_note-89">[86]</a> with one of them used on the Longan Nano board produced by a Chinese electronic company Sipeed.<a href="#cite_note-90">[87]</a></li> <li><a href="/wiki/Google" title="Google">Google</a> has developed the <a href="/wiki/Titan_M" class="mw-redirect" title="Titan M">Titan M2</a> security module for the <a href="/wiki/Pixel_6" title="Pixel 6">Pixel 6</a> and <a href="/wiki/Pixel_7" title="Pixel 7">Pixel 7</a><a href="#cite_note-91">[88]</a></li> <li>GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC (RV32IMC) and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.<a href="#cite_note-92">[89]</a><a href="#cite_note-93">[90]</a><a href="#cite_note-94">[91]</a></li> <li><a href="/wiki/Imagination_Technologies" title="Imagination Technologies">Imagination Technologies</a> RTXM-2200<a href="#cite_note-95">[92]</a> is the first core from their Catapult range. It’s a real-time, deterministic, 32-bit embedded CPU</li> <li><a rel="nofollow" class="external text" href="https://www.fpga-cores.com/instant-soc/">Instant SoC</a> RISC-V cores from FPGA cores. <a href="/wiki/System_on_a_chip" title="System on a chip">System on chip</a>, including RISC-V cores, defined by C++.</li> <li>Micro Magic Inc. announced the world's fastest 64-bit RISC-V core achieving 5 GHz and 13,000 CoreMarks in October 2020.</li> <li><a href="/wiki/MIPS_Technologies" title="MIPS Technologies">MIPS Technologies</a> of San Jose, California, pivoted to developing RISC-V cores in 2021. It rolled out its first implementation eVocore P8700 in December 2022.<a href="#cite_note-96">[93]</a><a href="#cite_note-97">[94]</a></li> <li><a href="/wiki/Seagate_Technology" title="Seagate Technology">Seagate</a>, in December 2020 announced that it had developed two RISC-V general-purpose cores for use in upcoming controllers for its storage devices.<a href="#cite_note-98">[95]</a></li> <li><a href="/wiki/SiFive" title="SiFive">SiFive</a> of Santa Clara, California, was established specifically for developing RISC-V hardware and began releasing processor models in 2017.<a href="#cite_note-99">[96]</a><a href="#cite_note-100">[97]</a> These included a quad-core, 64-bit (RV64GC) <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a> (SoC) capable of running general-purpose operating systems such as <a href="/wiki/Linux" title="Linux">Linux</a>.<a href="#cite_note-101">[98]</a></li> <li>StarFive, an offshoot of SiFive based in China, offers two RISC-V implementations – one for big data applications and the other for computational storage.<a href="#cite_note-102">[99]</a><a href="#cite_note-103">[100]</a></li> <li>Syntacore,<a href="#cite_note-104">[101]</a> a founding member of RISC-V International and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018<a class="external text" href="https://en.wikipedia.org/w/index.php?title=RISC-V&action=edit">[update]</a>, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core (RV32I/E[MC]).<a href="#cite_note-scr1-105">[102]</a> First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.<a href="#cite_note-106">[103]</a></li> <li>WinChipHead (WCH), a Chinese semiconductor manufacturer of popular and inexpensive USB chips such as CH340 and ARM microcontrollers<a href="#cite_note-107">[104]</a> introduced a simple, inexpensive RISC-V microcontroller line CH32Vxxx, headed by US$0.10 CH32V003.<a href="#cite_note-108">[105]</a><a href="#cite_note-109">[106]</a></li> <li><a href="/wiki/Codasip" title="Codasip">Codasip</a> and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.<a href="#cite_note-110">[107]</a></li> <li>As of 2020, the Indian defence and strategic sector started using the 64-bit RISC-V based 100-350 MHz <a href="/wiki/SHAKTI_-_Microprocessor_%26_Microcontroller#Risecreek" class="mw-redirect" title="SHAKTI - Microprocessor & Microcontroller">Risecreek</a> processor[<a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed">citation needed</a>] developed by <a href="/wiki/IIT_Madras" title="IIT Madras">IIT Madras</a> which is fabricated by <a href="/wiki/Intel" title="Intel">Intel</a> with 22 nm <a href="/wiki/FinFET" class="mw-redirect" title="FinFET">FinFET</a> process.<a href="#cite_note-111">[108]</a><a href="#cite_note-:0-112">[109]</a></li> <li>RIES v3.0d development boards are the first to use DIR-V <a href="/wiki/VEGA_Microprocessors#VEGA" title="VEGA Microprocessors">VEGA</a> RISC-V processors. It contains the VEGA ET1031, a 32-bit RISC-V CPU with three <a href="/wiki/UART" class="mw-redirect" title="UART">UART</a> serial ports, four <a href="/wiki/Serial_Peripheral_Interface" title="Serial Peripheral Interface">Serial Peripheral Interface</a> ports, two megabytes of <a href="/wiki/Flash_memory" title="Flash memory">flash memory</a>, 256KB of <a href="/wiki/Static_random-access_memory" title="Static random-access memory">SRAM</a>, and three 32-bit timers. It operates at 100 MHz. It is advised for usage in wearables, toys, small IoT devices, and sensors by <a href="/wiki/C-DAC" class="mw-redirect" title="C-DAC">C-DAC</a> in Indian market.<a href="#cite_note-113">[110]</a></li></ul> <div class="mw-heading mw-heading3"><h3 id="In_development">In development</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=24" title="Edit section: In development">edit</a>]</div> <ul><li>ASTC developed a RISC-V CPU for embedded ICs.<a href="#cite_note-114">[111]</a></li> <li><a href="/wiki/Centre_for_Development_of_Advanced_Computing" title="Centre for Development of Advanced Computing">Centre for Development of Advanced Computing</a> (C-DAC) in India is developing a single core 32-bit in-order, a single core 64-bit in-order and three out-of-order single, dual and quad-core RISC-V processor under <a href="/wiki/VEGA_Microprocessors" title="VEGA Microprocessors">VEGA Microprocessors</a> series.<a href="#cite_note-115">[112]</a><a href="#cite_note-116">[113]</a><a href="#cite_note-117">[114]</a></li> <li><a href="/wiki/Cobham_plc" class="mw-redirect" title="Cobham plc">Cobham Gaisler</a> NOEL-V 64-bit.<a href="#cite_note-118">[115]</a></li> <li><a href="/wiki/Computer_Laboratory,_University_of_Cambridge" class="mw-redirect" title="Computer Laboratory, University of Cambridge">Computer Laboratory, University of Cambridge</a>, in collaboration with the <a href="/wiki/FreeBSD" title="FreeBSD">FreeBSD</a> Project, has ported that operating system to 64-bit RISC-V to use as a hardware-software research platform.<a href="#cite_note-freebsdriscv-committed-119">[116]</a></li> <li>Esperanto Technologies announced that they are developing three RISC-V based processors: the ET-Maxion high-performance core, ET-Minion energy-efficient core, and ET-Graphics graphics processor.<a href="#cite_note-120">[117]</a> <ul><li>Esperanto ET-SoC-1, a 200 TOPS "kilocore" supercomputer on a chip, with 1088 small 64-bit in-order ET-Minion cores with tensor/vector units and 4 big 64-bit out-of-order ET-Maxion cores<a href="#cite_note-121">[118]</a></li></ul></li> <li><a href="/wiki/ETH_Zurich" title="ETH Zurich">ETH Zurich</a> and the <a href="/wiki/University_of_Bologna" title="University of Bologna">University of Bologna</a> have cooperatively developed the open-source RISC-V PULPino processor<a href="#cite_note-122">[119]</a> as part of the Parallel Ultra-Low Power (PULP) project for energy-efficient IoT computing.<a href="#cite_note-123">[120]</a></li> <li><a href="/wiki/European_Processor_Initiative" title="European Processor Initiative">European Processor Initiative</a> (EPI), RISC-V Accelerator Stream.<a href="#cite_note-124">[121]</a><a href="#cite_note-125">[122]</a><figure class="mw-default-size" typeof="mw:File/Thumb"><a href="/wiki/File:RISC-V_EPAC.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/RISC-V_EPAC.png/220px-RISC-V_EPAC.png" decoding="async" width="220" height="220" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/RISC-V_EPAC.png/330px-RISC-V_EPAC.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/17/RISC-V_EPAC.png/440px-RISC-V_EPAC.png 2x" data-file-width="2000" data-file-height="2000" /></a><figcaption>Illustration of <a href="/wiki/European_Processor_Initiative" title="European Processor Initiative">EPI</a>'s first working RISC-V chip sample in 2021.</figcaption></figure></li> <li>Reconfigurable Intelligent Systems Engineering Group (RISE) of <a href="/wiki/IIT_Madras" title="IIT Madras">IIT-Madras</a> is developing six <a href="/wiki/SHAKTI_-_Microprocessor_%26_Microcontroller" class="mw-redirect" title="SHAKTI - Microprocessor & Microcontroller">Shakti</a> series RISC-V open-source CPU designs for six distinct uses, from a small <a href="/wiki/32-bit_CPU" class="mw-redirect" title="32-bit CPU">32-bit CPU</a> for the <a href="/wiki/Internet_of_things" title="Internet of things">Internet of things</a> (IoT) to large, <a href="/wiki/64-bit_CPU" class="mw-redirect" title="64-bit CPU">64-bit CPUs</a> designed for warehouse-scale computers such as <a href="/wiki/Server_farm" title="Server farm">server farms</a> based on <a href="/wiki/RapidIO" title="RapidIO">RapidIO</a> and <a href="/wiki/Hybrid_Memory_Cube" title="Hybrid Memory Cube">Hybrid Memory Cube</a> technologies.<a href="#cite_note-126">[123]</a><a href="#cite_note-shakti-25">[23]</a><a href="#cite_note-iitmadrasospp-127">[124]</a> 32-bit Moushik successfully booted by RISE for the application of credit cards, <a href="/wiki/Electronic_voting_machine" title="Electronic voting machine">electronic voting machines</a> (EVMs), surveillance cameras, safe locks, personalized health management systems.<a href="#cite_note-:0-112">[109]</a><a href="#cite_note-128">[125]</a></li> <li><a href="/wiki/LowRISC" title="LowRISC">lowRISC</a> is a non profit project to implement a fully <a href="/wiki/Open-source_hardware" title="Open-source hardware">open-source hardware</a> <a href="/wiki/System_on_a_chip" title="System on a chip">system on a chip</a> (SoC) based on the 64-bit RISC-V ISA.<a href="#cite_note-lowrisc-129">[126]</a></li> <li><a href="/wiki/Nvidia" title="Nvidia">Nvidia</a> plans to use RISC-V to replace their Falcon processor on their <a href="/wiki/GeForce" title="GeForce">GeForce</a> graphics cards.<a href="#cite_note-130">[127]</a></li> <li>RV64X consortium is working on a set of graphics extensions to RISC-V and has announced that they are developing an open source RISC-V core with a GPU unit.<a href="#cite_note-131">[128]</a></li> <li><a href="/wiki/SiFive" title="SiFive">SiFive</a> announced their first RISC-V <a href="/wiki/Out-of-order_execution#Out-of-order_processors" title="Out-of-order execution">out-of-order</a> high performance CPU core, the U8 Series Processor IP.<a href="#cite_note-132">[129]</a></li> <li>Ventana revealed they are developing high performance RISC-V CPU IP and chiplet technology targeting data center applications.<a href="#cite_note-133">[130]</a><a href="#cite_note-134">[131]</a></li></ul> <div class="mw-heading mw-heading3"><h3 id="Open_source">Open source</h3>[<a href="/w/index.php?title=RISC-V&action=edit&section=25" title="Edit section: Open source">edit</a>]</div> <ul><li>DAMO Academy,<a href="#cite_note-135">[132]</a><a href="#cite_note-136">[133]</a> the research arm of <a href="/wiki/Alibaba_Group" title="Alibaba Group">Alibaba Group</a>, in July 2019 announced the 2.5 GHz 16-core 64-bit (RV64GC) Xuantie 910 <a href="/wiki/Out-of-order_execution#Out-of-order_processors" title="Out-of-order execution">out-of-order</a> processor.<a href="#cite_note-137">[134]</a> In October 2021 the Xuantie 910 was released as an open-source design.<a href="#cite_note-138">[135]</a> In November 2023, DAMO unveiled three updated processors: the Xuantie C920, Xuantie C907 and Xuantie R910; these processors were aimed at a variety of application areas, including autonomous vehicles, artificial intelligence (AI), enterprise hard drives, and network communications.<a href="#cite_note-139">[136]</a> The server-grade CPU Xuantie C930 was expected to be launched in 2024.<a href="#cite_note-140">[137]</a></li> <li>The Berkeley CPUs are implemented in a unique hardware design language, <a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a>, and some are named for famous train engines: <ul><li>64-bit Rocket.<a href="#cite_note-141">[138]</a> Rocket may suit compact, low-power intermediate computers such as personal devices. Named for <a href="/wiki/Stephenson%27s_Rocket" title="Stephenson's Rocket">Stephenson's Rocket</a>.</li> <li>The <a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a> Berkeley Out of Order Machine (BOOM).<a href="#cite_note-142">[139]</a> The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language. BOOM uses much of the infrastructure created for Rocket, and may be usable for personal, supercomputer, and warehouse-scale computers.</li> <li>Five <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> Sodor CPU designs from Berkeley, designed for student projects.<a href="#cite_note-sodor-24">[22]</a> <a href="/wiki/Sodor_(fictional_island)" title="Sodor (fictional island)">Sodor</a> is the fictional island of trains in children's stories about <a href="/wiki/Thomas_the_Tank_Engine" title="Thomas the Tank Engine">Thomas the Tank Engine</a>.</li></ul></li></ul> <ul><li>The Institute of Computing Technology of the <a href="/wiki/Chinese_Academy_of_Sciences" title="Chinese Academy of Sciences">Chinese Academy of Sciences</a> (ICT CAS) in June 2020 launched the XiangShan high-performance RISC-V processor project.<a href="#cite_note-143">[140]</a><a href="#cite_note-144">[141]</a> In summer 2021, a CPU prototype produced at <a href="/wiki/TSMC" title="TSMC">TSMC</a> on a 28nm process node, with speeds of up to 1.3 GHz, was presented at a RISC-V conference in China.<a href="#cite_note-145">[142]</a> An updated prototype was to be produced at <a href="/wiki/Semiconductor_Manufacturing_International_Corporation" title="Semiconductor Manufacturing International Corporation">SMIC</a> on a 14nm process node with speeds of up to 2 GHz.<a href="#cite_note-146">[143]</a> The capabilities of the second XiangShan processor, called “Nanhu”, which was released in August 2022, may have surpassed those of the ARM <a href="/wiki/ARM_Cortex-A76" title="ARM Cortex-A76">Cortex-A76</a>, a current CPU at the time, making Nanhu the most powerful open-source CPU in the world in 2023.<a href="#cite_note-:4-147">[144]</a><a href="#cite_note-148">[145]</a> For 2022 the Institute of Computing Technology was planning to announce a new XiangShan design with the RISC-V Vector extension for applications such as AI acceleration; in the future it hoped to find a "<a href="/wiki/Red_Hat" title="Red Hat">Red Hat</a>" type company that would engage in commericalization of its XiangShan cores.<a href="#cite_note-:4-147">[144]</a></li> <li>PicoRV32 by <style data-mw-deduplicate="TemplateStyles:r1238216509">.mw-parser-output .vanchor>:target~.vanchor-text{background-color:#b1d2ff}@media screen{html.skin-theme-clientpref-night .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .vanchor>:target~.vanchor-text{background-color:#0f4dc9}}</style>Claire Wolf,<a href="#cite_note-149">[146]</a> a 32-bit <a href="/wiki/Microcontroller_unit" class="mw-redirect" title="Microcontroller unit">microcontroller unit</a> (MCU) class RV32IMC implementation in <a href="/wiki/Verilog" title="Verilog">Verilog</a>.</li> <li>SCR1 from Syntacore,<a href="#cite_note-scr1-105">[102]</a> a 32-bit microcontroller unit (MCU) class RV32IMC implementation in <a href="/wiki/Verilog" title="Verilog">Verilog</a>.</li> <li>MIPT-MIPS<a href="#cite_note-150">[147]</a> by MIPT-ILab (<a href="/wiki/Moscow_Institute_of_Physics_and_Technology" title="Moscow Institute of Physics and Technology">MIPT</a> Lab for CPU Technologies created with help of <a href="/wiki/Intel" title="Intel">Intel</a>). MIPT-MIPS is a cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs. It measures performance of program running on CPU. Among key features are: compatibility with interactive MARS system calls,<a href="#cite_note-151">[148]</a> interactive simulation with <a href="/wiki/GNU_Debugger" title="GNU Debugger">GDB</a>, configurable <a href="/wiki/Branch_predictor" title="Branch predictor">branch prediction unit</a> with several prediction algorithms and instruction cache and interstage data bypassing. Implementation in C++.</li> <li>SERV<a href="#cite_note-152">[149]</a> by Olof Kindgren, a physically small, validated bit-serial RV32I core in <a href="/wiki/Verilog" title="Verilog">Verilog</a>, is the world's smallest RISC-V CPU. It is integrated with both the LiteX and FuseSoC SoC construction systems. An FPGA implementation<a href="#cite_note-:2-153">[150]</a> was 125 <a href="/wiki/Lookup_table#Hardware_LUTs" title="Lookup table">lookup tables</a> (LUTs) and 164 <a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">flip-flops</a>, running at 1.5 <a href="/wiki/Million_instructions_per_second" class="mw-redirect" title="Million instructions per second">MIPS</a>, In a 130 nm-node ASIC, it was 2.1<a href="/wiki/Gate_equivalent" title="Gate equivalent">kGE</a><a href="#cite_note-:2-153">[150]</a> and a high-end FPGA could hold 10,000 cores.<a href="#cite_note-154">[151]</a></li> <li>PULPino (Riscy and Zero-Riscy) from ETH Zürich / University of Bologna.<a href="#cite_note-pulpino-155">[152]</a> The <a href="/wiki/Semiconductor_intellectual_property_core" title="Semiconductor intellectual property core">cores</a> in PULPino implement a simple RV32IMC ISA for microcontrollers (Zero-Riscy) or a more powerful RV32IMFC ISA with custom DSP extensions for embedded signal processing.</li> <li><a href="/wiki/Western_Digital" title="Western Digital">Western Digital</a>, in December 2018 announced an RV32IMC core called SweRV EH1 featuring an in-order 2-way superscalar and nine-stage pipeline design. In December 2019, WD announced the SweRV EH2 an in-order core with two hardware threads and a nine-stage pipeline and the SweRV EL2 a single issue core with a 4-stage pipeline<a href="#cite_note-156">[153]</a> WD plans to use SweRV based processors in their flash controllers and SSDs, and released it as open-source to third parties in January 2019.<a href="#cite_note-157">[154]</a><a href="#cite_note-158">[155]</a><a href="#cite_note-159">[156]</a></li> <li>NEORV32 by Stephan Nolting,<a href="#cite_note-160">[157]</a> a highly-configurable 32-bit microcontroller unit (MCU) class RV32[I/E]MACUX_Zbb_Zfinx_Zicsr_Zifencei CPU with on-chip debugger support written in platform-independent <a href="/wiki/VHDL" title="VHDL">VHDL</a>. The project includes a microcontroller-like SoC that already includes common modules like UART, timers, SPI, TWI, a TRNG and embedded memories.</li> <li>Hazard3 by Luke Wren, a RV32I processor with a three-stage pipeline.<a href="#cite_note-161">[158]</a> Two Hazard3 cores are implemented in the <a href="/wiki/RP2350" title="RP2350">RP2350</a> microcontroller.<a href="#cite_note-162">[159]</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="End-user_hardware">End-user hardware</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=26" title="Edit section: End-user hardware">edit</a>]</div> DeepComputing of Hong Kong announced the release on 13 April 2023 of the "world's first laptop with RISC-V processor"; the notebook, called "ROMA", was delivered to its first customers in August 2023<a href="#cite_note-163">[160]</a> and came pre-installed with the Chinese <a href="/wiki/Kylin_(operating_system)" title="Kylin (operating system)">openKylin</a> Linux operating system.<a href="#cite_note-164">[161]</a> The device's basic model, available from <a href="/wiki/Alibaba_Group" title="Alibaba Group">Alibaba</a>, was still expensive at roughly US$1500<a href="#cite_note-165">[162]</a> considering it was powered by the not very fast<a href="#cite_note-166">[163]</a> Alibaba (DAMO) CPU "XuanTie C910". An upgrade in June 2024 doubled the core count to 8 cores and increased the clock speed to 2 GHz (from 1.5 GHz), while dropping the price to US$1,000.<a href="#cite_note-167">[164]</a> The processor used was a SpacemiT SoC K1.<a href="#cite_note-168">[165]</a><a href="#cite_note-169">[166]</a> A collaboration with <a href="/wiki/Canonical_(company)" title="Canonical (company)">Canonical</a><a href="#cite_note-170">[167]</a> meant that the ROMA II came pre-installed with the major international Linux distribution <a href="/wiki/Ubuntu" title="Ubuntu">Ubuntu</a>.<a href="#cite_note-171">[168]</a> <div class="mw-heading mw-heading2"><h2 id="Software">Software</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=27" title="Edit section: Software">edit</a>]</div> A normal problem for a new instruction set is both a lack of CPU designs and of software, which limit its usability and reduce adoption.<a href="#cite_note-isasbfree-22">[20]</a> In addition to already having a large number of CPU hardware designs, RISC-V is also supported by toolchains, operating systems (e.g. <a href="/wiki/Linux" title="Linux">Linux</a>), <a href="/wiki/Middleware" title="Middleware">middleware</a>[<a href="/wiki/Wikipedia:Vagueness" title="Wikipedia:Vagueness">vague</a>] and design software. Available RISC-V software tools include a <a href="/wiki/GNU_Compiler_Collection" title="GNU Compiler Collection">GNU Compiler Collection</a> (GCC) toolchain (with <a href="/wiki/GNU_Debugger" title="GNU Debugger">GDB</a>, the debugger), an <a href="/wiki/LLVM" title="LLVM">LLVM</a> toolchain, the <a href="/wiki/OVPsim" title="OVPsim">OVPsim</a> simulator (and library of RISC-V Fast Processor Models), the Spike simulator, and a simulator in <a href="/wiki/QEMU" title="QEMU">QEMU</a> (RV32GC/RV64GC). <a rel="nofollow" class="external text" href="https://openjdk.java.net/jeps/422">JEP 422: Linux/RISC-V Port</a> is already integrated into mainline <a href="/wiki/OpenJDK" title="OpenJDK">OpenJDK</a> repository. Java 21+ Temurin OpenJDK builds for RISC-V are available from <a href="/wiki/Adoptium" title="Adoptium">Adoptium</a>. Operating system support exists for the <a href="/wiki/Linux" title="Linux">Linux</a> kernel, <a href="/wiki/FreeBSD" title="FreeBSD">FreeBSD</a>, <a href="/wiki/NetBSD" title="NetBSD">NetBSD</a>, and <a href="/wiki/OpenBSD" title="OpenBSD">OpenBSD</a> but the supervisor-mode instructions were unstandardized before version 1.11 of the privileged ISA specification,<a href="#cite_note-priv-isa-3">[3]</a> so this support is provisional. The preliminary FreeBSD port to the RISC-V architecture was upstreamed in February 2016, and shipped in FreeBSD 11.0.<a href="#cite_note-freebsdriscv-172">[169]</a><a href="#cite_note-freebsdriscv-committed-119">[116]</a> Ports of the <a href="/wiki/Debian" title="Debian">Debian</a><a href="#cite_note-173">[170]</a><a href="#cite_note-174">[171]</a> and <a href="/wiki/Fedora_(operating_system)" class="mw-redirect" title="Fedora (operating system)">Fedora</a><a href="#cite_note-175">[172]</a> <a href="/wiki/Linux_distribution" title="Linux distribution">Linux distributions</a>, and a port of <a href="/wiki/Haiku_(operating_system)" title="Haiku (operating system)">Haiku</a>,<a href="#cite_note-176">[173]</a> are stabilizing (all only support 64-bit RISC-V, with no plans to support the 32-bit version). In June 2024, Hong Kong company DeepComputing announced the commercial availability of the first RISC-V laptop in the world to run the popular Linux operating system <a href="/wiki/Ubuntu" title="Ubuntu">Ubuntu</a> in its standard form ("out of the box").<a href="#cite_note-:5-16">[14]</a> "As RISC-V is becoming a competitive ISA in multiple markets, porting Ubuntu to RISC-V to become the reference OS [operating system] for early adopters was a natural choice," Ubuntu-developer <a href="/wiki/Canonical_(company)" title="Canonical (company)">Canonical</a> stated in June 2024.<a href="#cite_note-177">[174]</a> A port of <a href="/wiki/Das_U-Boot" title="Das U-Boot">Das U-Boot</a> exists.<a href="#cite_note-178">[175]</a> UEFI Spec v2.7 has defined the RISC-V binding and a <a href="/wiki/TianoCore" class="mw-redirect" title="TianoCore">TianoCore</a> port has been done by <a href="/wiki/Hewlett_Packard_Enterprise" title="Hewlett Packard Enterprise">HPE</a> engineers<a href="#cite_note-179">[176]</a> and is expected to be upstreamed. There is a preliminary port of <a href="/wiki/SeL4" class="mw-redirect" title="SeL4">the seL4 microkernel</a>.<a href="#cite_note-180">[177]</a><a href="#cite_note-181">[178]</a> Hex Five released the first Secure IoT Stack for RISC-V with <a href="/wiki/FreeRTOS" title="FreeRTOS">FreeRTOS</a> support.<a href="#cite_note-182">[179]</a> Also <a href="/wiki/Xv6" title="Xv6">xv6</a>, a modern reimplementation of <a href="/wiki/Version_6_Unix" title="Version 6 Unix">Sixth Edition Unix</a> in <a href="/wiki/ANSI_C" title="ANSI C">ANSI C</a> used for pedagogical purposes in <a href="/wiki/Massachusetts_Institute_of_Technology" title="Massachusetts Institute of Technology">MIT</a>, was ported. Pharos RTOS has been ported to 64-bit RISC-V<a href="#cite_note-Pharos-183">[180]</a> (including time and memory protection). Also see <a href="/wiki/Comparison_of_real-time_operating_systems" title="Comparison of real-time operating systems">Comparison of real-time operating systems</a>. A simulator exists to run a RISC-V Linux system on a <a href="/wiki/Web_browser" title="Web browser">web browser</a> using <a href="/wiki/JavaScript" title="JavaScript">JavaScript</a>.<a href="#cite_note-184">[181]</a><a href="#cite_note-185">[182]</a><a href="#cite_note-186">[183]</a> <a href="/wiki/QEMU" title="QEMU">QEMU</a> supports running (using <a href="/wiki/Binary_translation" title="Binary translation">binary translation</a>) 32- and 64-bit RISC-V systems (e.g. Linux) with many emulated or virtualized devices (serial, parallel, USB, network, storage, real time clock, watchdog, audio), as well as running RISC-V Linux binaries (translating syscalls to the host kernel). It does support multi-core emulation (SMP).<a href="#cite_note-187">[184]</a> The Creator simulator is portable and allows the user to learn various assembly languages of different processors (Creator has examples with an implementation of RISC-V and MIPS32 instructions).<a href="#cite_note-188">[185]</a><a href="#cite_note-189">[186]</a><a href="#cite_note-190">[187]</a><a href="#cite_note-191">[188]</a><a href="#cite_note-192">[189]</a> Several languages have been applied to creating RISC-V IP cores including a <a href="/wiki/Scala_(programming_language)" title="Scala (programming language)">Scala</a>-based hardware description language, <a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a>,<a href="#cite_note-chisel-193">[190]</a> which can reduce the designs to <a href="/wiki/Verilog" title="Verilog">Verilog</a> for use in devices, and the CodAL processor description language which has been used in to describe RISC-V processor cores and to generate corresponding HDKs (<a href="/wiki/Register-transfer_level" title="Register-transfer level">RTL</a>, testbench and <a href="/wiki/Universal_Verification_Methodology" title="Universal Verification Methodology">UVM</a>) and SDKs.<a href="#cite_note-194">[191]</a> The RISC-V International Compliance Task Group has a GitHub repository for RV32IMC.<a href="#cite_note-195">[192]</a> <div class="mw-heading mw-heading2"><h2 id="Development_tools">Development tools</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=28" title="Edit section: Development tools">edit</a>]</div> <ul><li><a href="/wiki/IAR_Systems" title="IAR Systems">IAR Systems</a> released the first version of IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions in the first version. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.</li> <li><a href="/wiki/Lauterbach_(company)" title="Lauterbach (company)">Lauterbach</a> added support for RISC-V to their TRACE32 <a href="/wiki/JTAG" title="JTAG">JTAG</a> debuggers.<a href="#cite_note-196">[193]</a><a href="#cite_note-197">[194]</a> Lauterbach also announced<a href="#cite_note-198">[195]</a> support for <a href="/wiki/SiFive" title="SiFive">SiFives</a> RISC-V <a href="/wiki/Nexus_(standard)" title="Nexus (standard)">NEXUS</a> based processor trace.</li> <li><a href="/wiki/Segger_Microcontroller_Systems#Debug_and_trace_probes" title="Segger Microcontroller Systems">SEGGER</a> released a new product named "J-Trace PRO RISC-V", added support for RISC-V cores to their <a href="/wiki/Segger_Microcontroller_Systems#J-Link" title="Segger Microcontroller Systems">J-Link</a> debugging probe family,<a href="#cite_note-199">[196]</a> their integrated development environment Embedded Studio,<a href="#cite_note-200">[197]</a> and their RTOS <a href="/wiki/EmbOS" class="mw-redirect" title="EmbOS">embOS</a> and embedded software.<a href="#cite_note-201">[198]</a></li> <li><a rel="nofollow" class="external text" href="https://www.ultrasoc.com/technology-2/risc-v/">UltraSOC</a>, now part of Siemens,<a href="#cite_note-202">[199]</a> proposed a standard trace system and donated an implementation.</li></ul> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=29" title="Edit section: See also">edit</a>]</div> <ul><li><a href="/wiki/List_of_open-source_computing_hardware" class="mw-redirect" title="List of open-source computing hardware">List of open-source computing hardware</a></li> <li><a href="/wiki/Microprocessor_chronology" title="Microprocessor chronology">Microprocessor chronology</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=30" title="Edit section: Notes">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-4"><a href="#cite_ref-4">^</a> Big and bi-endianness supported through non-standard variants; instructions are always little-endian.<a href="#cite_note-isa20191213-2">[2]</a>: vi, 9–10  </li> <li id="cite_note-6"><a href="#cite_ref-6">^</a> The designation V (Roman numeral '5') represents RISC-V as the 5th generation <a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">reduced instruction set computer</a> (RISC) <a href="/wiki/Computer_architecture" title="Computer architecture">architecture</a> that was developed at the <a href="/wiki/University_of_California,_Berkeley" title="University of California, Berkeley">University of California, Berkeley</a> since 1981.<a href="#cite_note-5">[4]</a> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="References">References</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=31" title="Edit section: References">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist reflist-columns references-column-width" style="column-width: 30em;"> <ol class="references"> <li id="cite_note-1"><a href="#cite_ref-1">^</a> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFAsanovićPatterson2014" class="citation conference cs1"><a href="/wiki/Krste_Asanovi%C4%87" title="Krste Asanović">Asanović, Krste</a>; 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Retrieved 19 February 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=Codasip&rft.atitle=Codasip+Studio&rft_id=https%3A%2F%2Fcodasip.com%2Fcodasip-studio%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-195"><a href="#cite_ref-195">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://github.com/riscv/riscv-compliance">riscv/riscv-compliance</a>, RISC-V, 12 February 2021, retrieved 19 February 2021</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=riscv%2Friscv-compliance&rft.pub=RISC-V&rft.date=2021-02-12&rft_id=https%3A%2F%2Fgithub.com%2Friscv%2Friscv-compliance&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-196"><a href="#cite_ref-196">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.lauterbach.com/frames.html?bdmriscv.html">"RISC-V Debugger"</a>. www.lauterbach.com TRACE32 Debugger for RISC-V.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.lauterbach.com+TRACE32+Debugger+for+RISC-V&rft.atitle=RISC-V+Debugger&rft_id=https%3A%2F%2Fwww.lauterbach.com%2Fframes.html%3Fbdmriscv.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-197"><a href="#cite_ref-197">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.sifive.com/press/lauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores">"Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores"</a>. www.sifive.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.sifive.com&rft.atitle=Lauterbach+and+SiFive+Bring+TRACE32+Support+for+High-Performance+RISC-V+Cores&rft_id=https%3A%2F%2Fwww.sifive.com%2Fpress%2Flauterbach-and-sifive-bring-trace32-support-for-high-performance-risc-v-cores&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-198"><a href="#cite_ref-198">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20220602223446/https://www.lauterbach.com/frames.html?news_514.html">"TRACE32 supports SiFive's RISC-V trace"</a>. www.lauterbach.com. Archived from <a rel="nofollow" class="external text" href="https://www.lauterbach.com/frames.html?news_514.html">the original</a> on 2 June 2022. Retrieved 6 March 2021.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=www.lauterbach.com&rft.atitle=TRACE32+supports+SiFive%27s+RISC-V+trace&rft_id=https%3A%2F%2Fwww.lauterbach.com%2Fframes.html%3Fnews_514.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-199"><a href="#cite_ref-199">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.segger.com/news/segger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe/">"SEGGER Adds Support for SiFive's Coreplex IP to Its Industry Leading J-Link Debug Probe"</a>. Retrieved 19 September 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=SEGGER+Adds+Support+for+SiFive%27s+Coreplex+IP+to+Its+Industry+Leading+J-Link+Debug+Probe&rft_id=https%3A%2F%2Fwww.segger.com%2Fnews%2Fsegger-adds-support-for-sifives-coreplex-ip-to-its-industry-leading-j-link-debug-probe%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-200"><a href="#cite_ref-200">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.segger.com/news/segger-embedded-studio-supports-risc-v-architecture/">"PR: SEGGER Embedded Studio supports RISC-V architecture"</a>. Retrieved 23 November 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PR%3A+SEGGER+Embedded+Studio+supports+RISC-V+architecture&rft_id=https%3A%2F%2Fwww.segger.com%2Fnews%2Fsegger-embedded-studio-supports-risc-v-architecture%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-201"><a href="#cite_ref-201">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.segger.com/news/segger-presents-rtos-stacks-middleware-for-risc-v/">"PR: SEGGER presents RTOS, stacks, middleware for RISC-V"</a>. Retrieved 8 December 2017.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=PR%3A+SEGGER+presents+RTOS%2C+stacks%2C+middleware+for+RISC-V&rft_id=https%3A%2F%2Fwww.segger.com%2Fnews%2Fsegger-presents-rtos-stacks-middleware-for-risc-v%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> <li id="cite_note-202"><a href="#cite_ref-202">^</a> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDahad2020" class="citation web cs1">Dahad, Nitin (23 June 2020). <a rel="nofollow" class="external text" href="https://www.eetimes.com/siemens-acquires-ultrasoc-for-soc-lifecycle-product-suite/">"Siemens Acquires UltraSoC for SoC Lifecycle Product Suite"</a>. EE Times. Retrieved 12 July 2023.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EE+Times&rft.atitle=Siemens+Acquires+UltraSoC+for+SoC+Lifecycle+Product+Suite&rft.date=2020-06-23&rft.aulast=Dahad&rft.aufirst=Nitin&rft_id=https%3A%2F%2Fwww.eetimes.com%2Fsiemens-acquires-ultrasoc-for-soc-lifecycle-product-suite%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"> </li> </ol></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=32" title="Edit section: Further reading">edit</a>]</div> <style data-mw-deduplicate="TemplateStyles:r1235681985">.mw-parser-output .side-box{margin:4px 0;box-sizing:border-box;border:1px solid #aaa;font-size:88%;line-height:1.25em;background-color:var(--background-color-interactive-subtle,#f8f9fa);display:flow-root}.mw-parser-output .side-box-abovebelow,.mw-parser-output .side-box-text{padding:0.25em 0.9em}.mw-parser-output .side-box-image{padding:2px 0 2px 0.9em;text-align:center}.mw-parser-output .side-box-imageright{padding:2px 0.9em 2px 0;text-align:center}@media(min-width:500px){.mw-parser-output .side-box-flex{display:flex;align-items:center}.mw-parser-output .side-box-text{flex:1;min-width:0}}@media(min-width:720px){.mw-parser-output .side-box{width:238px}.mw-parser-output .side-box-right{clear:right;float:right;margin-left:1em}.mw-parser-output .side-box-left{margin-right:1em}}</style><div class="side-box metadata side-box-right"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"> <div class="side-box-abovebelow"> <a href="/wiki/Wikipedia:The_Wikipedia_Library" title="Wikipedia:The Wikipedia Library">Library resources</a> about RISC-V <hr /></div> <div class="side-box-flex"> <div class="side-box-text plainlist"><ul><li><a class="external text" href="https://ftl.toolforge.org/cgi-bin/ftl?st=wp&su=RISC-V">Resources in your library</a></li> <li><a class="external text" href="https://ftl.toolforge.org/cgi-bin/ftl?st=wp&su=RISC-V&library=0CHOOSE0">Resources in other libraries</a></li> </ul></div></div> </div> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://riscv.org/technical/specifications/">"The RISC-V Instruction Set Manual"</a>. RISC-V International.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=The+RISC-V+Instruction+Set+Manual&rft.pub=RISC-V+International&rft_id=https%3A%2F%2Friscv.org%2Ftechnical%2Fspecifications%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li></ul> <style data-mw-deduplicate="TemplateStyles:r1239549316">.mw-parser-output .refbegin{margin-bottom:0.5em}.mw-parser-output .refbegin-hanging-indents>ul{margin-left:0}.mw-parser-output .refbegin-hanging-indents>ul>li{margin-left:0;padding-left:3.2em;text-indent:-3.2em}.mw-parser-output .refbegin-hanging-indents ul,.mw-parser-output .refbegin-hanging-indents ul li{list-style:none}@media(max-width:720px){.mw-parser-output .refbegin-hanging-indents>ul>li{padding-left:1.6em;text-indent:-1.6em}}.mw-parser-output .refbegin-columns{margin-top:0.3em}.mw-parser-output .refbegin-columns ul{margin-top:0}.mw-parser-output .refbegin-columns li{page-break-inside:avoid;break-inside:avoid-column}@media screen{.mw-parser-output .refbegin{font-size:90%}}</style><div class="refbegin" style=""> <ul><li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://github.com/johnwinans/rvalp">"RISC-V Assembly Language Programming"</a>. GitHub. 8 November 2019.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=GitHub&rft.atitle=RISC-V+Assembly+Language+Programming&rft.date=2019-11-08&rft_id=https%3A%2F%2Fgithub.com%2Fjohnwinans%2Frvalp&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWaterman2016" class="citation web cs1">Waterman, Andrew (January 2016). <a rel="nofollow" class="external text" href="https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.pdf">"Design of the RISC-V Instruction Set Architecture"</a> (PDF). EECS Department, University of California, Berkeley. EECS-2016-1.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EECS+Department%2C+University+of+California%2C+Berkeley&rft.atitle=Design+of+the+RISC-V+Instruction+Set+Architecture&rft.date=2016-01&rft.aulast=Waterman&rft.aufirst=Andrew&rft_id=https%3A%2F%2Fwww2.eecs.berkeley.edu%2FPubs%2FTechRpts%2F2016%2FEECS-2016-1.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFAsanovićPatterson2014" class="citation web cs1"><a href="/wiki/Krste_Asanovi%C4%87" title="Krste Asanović">Asanović, Krste</a>; <a href="/wiki/David_Patterson_(computer_scientist)" title="David Patterson (computer scientist)">Patterson, David A.</a> (6 August 2014). <a rel="nofollow" class="external text" href="https://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.html">"Instruction Sets Should Be Free: The Case For RISC-V"</a>. EECS Department, University of California, Berkeley. UCB/EECS-2014-146.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=EECS+Department%2C+University+of+California%2C+Berkeley&rft.atitle=Instruction+Sets+Should+Be+Free%3A+The+Case+For+RISC-V&rft.date=2014-08-06&rft.aulast=Asanovi%C4%87&rft.aufirst=Krste&rft.au=Patterson%2C+David+A.&rft_id=https%3A%2F%2Fwww.eecs.berkeley.edu%2FPubs%2FTechRpts%2F2014%2FEECS-2014-146.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWatermanLeeAvizienisCook2013" class="citation conference cs1">Waterman, Andrew; Lee, Yunsup; Avizienis, Rimas; Cook, Henry; <a href="/wiki/David_Patterson_(computer_scientist)" title="David Patterson (computer scientist)">Patterson, David A.</a>; <a href="/wiki/Krste_Asanovi%C4%87" title="Krste Asanović">Asanović, Krste</a> (25–27 August 2013). <a rel="nofollow" class="external text" href="https://www.hotchips.org/wp-content/uploads/hc_archives/hc25/HC25-posters/HC25.26.p70-RISC-V-Warterman-UCB.pdf">The RISC-V Instruction Set</a> (PDF). <a rel="nofollow" class="external text" href="https://www.hotchips.org/archives/2010s/hc25/">Hot Chips 25</a>. Stanford University, Palo Alto, California, USA.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=The+RISC-V+Instruction+Set&rft.place=Stanford+University%2C+Palo+Alto%2C+California%2C+USA&rft.date=2013-08-25%2F2013-08-27&rft.aulast=Waterman&rft.aufirst=Andrew&rft.au=Lee%2C+Yunsup&rft.au=Avizienis%2C+Rimas&rft.au=Cook%2C+Henry&rft.au=Patterson%2C+David+A.&rft.au=Asanovi%C4%87%2C+Krste&rft_id=https%3A%2F%2Fwww.hotchips.org%2Fwp-content%2Fuploads%2Fhc_archives%2Fhc25%2FHC25-posters%2FHC25.26.p70-RISC-V-Warterman-UCB.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFDabbelt2015" class="citation conference cs1">Dabbelt, Palmer (7–11 February 2015). <a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2015/02/riscv-software-toolchain-tutorial-hpca2015.pdf">RISC-V Software Ecosystem</a> (PDF). <a rel="nofollow" class="external text" href="http://darksilicon.org/hpca/">High-Performance Computer Architecture (HPCA) 2015</a>. San Francisco, California, USA.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=RISC-V+Software+Ecosystem&rft.place=San+Francisco%2C+California%2C+USA&rft.date=2015-02-07%2F2015-02-11&rft.aulast=Dabbelt&rft.aufirst=Palmer&rft_id=https%3A%2F%2Friscv.org%2Fwp-content%2Fuploads%2F2015%2F02%2Friscv-software-toolchain-tutorial-hpca2015.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLee2015" class="citation conference cs1">Lee, Yunsup (7–11 February 2015). <a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2015/02/riscv-rocket-chip-generator-tutorial-hpca2015.pdf">RISC-V "Rocket Chip" SoC Generator in Chisel</a> (PDF). <a rel="nofollow" class="external text" href="http://darksilicon.org/hpca/">High-Performance Computer Architecture (HPCA) 2015</a>. San Francisco, California, USA.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=conference&rft.btitle=RISC-V+%22Rocket+Chip%22+SoC+Generator+in+Chisel&rft.place=San+Francisco%2C+California%2C+USA&rft.date=2015-02-07%2F2015-02-11&rft.aulast=Lee&rft.aufirst=Yunsup&rft_id=https%3A%2F%2Friscv.org%2Fwp-content%2Fuploads%2F2015%2F02%2Friscv-rocket-chip-generator-tutorial-hpca2015.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li> <li><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFWatermanLeePattersonAsanović2015" class="citation web cs1">Waterman, Andrew; Lee, Yunsup; <a href="/wiki/David_Patterson_(computer_scientist)" title="David Patterson (computer scientist)">Patterson, David A.</a>; <a href="/wiki/Krste_Asanovi%C4%87" title="Krste Asanović">Asanović, Krste</a> (5 November 2015). <a rel="nofollow" class="external text" href="https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf">"The RISC-V Compressed Instruction Set Manual Version 1.9 (draft)"</a> (PDF). RISC-V.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=RISC-V&rft.atitle=The+RISC-V+Compressed+Instruction+Set+Manual+Version+1.9+%28draft%29&rft.date=2015-11-05&rft.aulast=Waterman&rft.aufirst=Andrew&rft.au=Lee%2C+Yunsup&rft.au=Patterson%2C+David+A.&rft.au=Asanovi%C4%87%2C+Krste&rft_id=https%3A%2F%2Friscv.org%2Fwp-content%2Fuploads%2F2015%2F11%2Friscv-compressed-spec-v1.9.pdf&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARISC-V" class="Z3988"></li></ul> </div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2>[<a href="/w/index.php?title=RISC-V&action=edit&section=33" title="Edit section: External links">edit</a>]</div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1235681985"><style data-mw-deduplicate="TemplateStyles:r1237033735">@media print{body.ns-0 .mw-parser-output .sistersitebox{display:none!important}}@media screen{html.skin-theme-clientpref-night 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li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:RISC_architectures" title="Template:RISC architectures"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:RISC_architectures" title="Template talk:RISC architectures"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:RISC_architectures" title="Special:EditPage/Template:RISC architectures"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Reduced_instruction_set_computer_(RISC)_architectures" style="font-size:114%;margin:0 4em"><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">Reduced instruction set computer</a> (RISC) architectures</div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Origins</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/IBM_801" title="IBM 801">IBM 801</a></li> <li><a href="/wiki/Berkeley_RISC" title="Berkeley RISC">Berkeley RISC</a></li> <li><a href="/wiki/Stanford_MIPS" title="Stanford MIPS">Stanford MIPS</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">In active development</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Analog_Devices" title="Analog Devices">Analog Devices</a> <a href="/wiki/Blackfin" title="Blackfin">Blackfin</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/ESi-RISC" title="ESi-RISC">eSi-RISC</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a>, <a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a></li> <li><a href="/wiki/Renesas_Electronics" title="Renesas Electronics">Renesas</a> <a href="/wiki/M32R" title="M32R">M32R</a>, <a href="/wiki/SuperH" title="SuperH">SuperH</a>, <a href="/wiki/V850" title="V850">V850</a></li> <li><a class="mw-selflink selflink">RISC-V</a></li> <li><a href="/wiki/SPARC" title="SPARC">SPARC</a></li> <li><a href="/wiki/Sunway_(processor)" title="Sunway (processor)">Sunway</a></li> <li><a href="/wiki/Unicore" title="Unicore">Unicore</a></li> <li><a href="/wiki/Xilinx" title="Xilinx">Xilinx</a> <a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a>, <a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Development discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/DEC_Alpha" title="DEC Alpha">Alpha</a></li> <li><a href="/wiki/AMD_Am29000" title="AMD Am29000">AMD Am29000</a></li> <li><a href="/wiki/Apollo_PRISM" title="Apollo PRISM">Apollo PRISM</a></li> <li><a href="/wiki/Atmel" title="Atmel">Atmel</a> <a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/Clipper_architecture" title="Clipper architecture">Clipper</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16</a></li> <li><a href="/wiki/AT%26T_Hobbit" title="AT&T Hobbit">CRISP</a></li> <li><a href="/wiki/DEC_PRISM" title="DEC PRISM">DEC PRISM</a></li> <li><a href="/wiki/Intel_i860" title="Intel i860">Intel i860</a>, <a href="/wiki/Intel_i960" title="Intel i960">i960</a></li> <li><a href="/wiki/Imagination_META" title="Imagination META">META</a></li> <li><a href="/wiki/MIPS-X" title="MIPS-X">MIPS-X</a></li> <li><a href="/wiki/Motorola_88000" title="Motorola 88000">Motorola 88000</a>, <a href="/wiki/M%C2%B7CORE" title="M·CORE">M·CORE</a></li> <li><a href="/wiki/PA-RISC" title="PA-RISC">PA-RISC</a></li> <li><a href="/wiki/IBM_POWER_architecture" title="IBM POWER architecture">POWER</a>, <a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> (active use in space exploration as <a href="/wiki/RAD750" title="RAD750">RAD750</a>), <a href="/wiki/IBM_ROMP" title="IBM ROMP">ROMP</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Programmable_logic" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Programmable_logic" title="Template:Programmable logic"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Programmable_logic" title="Template talk:Programmable logic"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Programmable_logic" title="Special:EditPage/Template:Programmable logic"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Programmable_logic" style="font-size:114%;margin:0 4em"><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Concepts</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a></li> <li><a href="/wiki/System_on_a_chip" title="System on a chip">SoC</a></li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">FPGA</a> <ul><li><a href="/wiki/Logic_block" title="Logic block">Logic block</a></li></ul></li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">CPLD</a></li> <li><a href="/wiki/Programmable_logic_device#EPLDs" title="Programmable logic device">EPLD</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">PLA</a></li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">PAL</a></li> <li><a href="/wiki/Generic_array_logic" class="mw-redirect" title="Generic array logic">GAL</a></li> <li><a href="/wiki/Cypress_PSoC" title="Cypress PSoC">PSoC</a></li> <li><a href="/wiki/Reconfigurable_computing" title="Reconfigurable computing">Reconfigurable computing</a> <ul><li><a href="/wiki/Xputer" title="Xputer">Xputer</a></li></ul></li> <li><a href="/wiki/Soft_microprocessor" title="Soft microprocessor">Soft microprocessor</a></li> <li><a href="/wiki/Circuit_underutilization" title="Circuit underutilization">Circuit underutilization</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li> <li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Hardware_description_language" title="Hardware description language">Languages</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Verilog" title="Verilog">Verilog</a> <ul><li><a href="/wiki/Verilog-A" title="Verilog-A">A</a></li> <li><a href="/wiki/Verilog-AMS" title="Verilog-AMS">AMS</a></li></ul></li> <li><a href="/wiki/VHDL" title="VHDL">VHDL</a> <ul><li><a href="/wiki/VHDL-AMS" title="VHDL-AMS">AMS</a></li> <li><a href="/wiki/VHDL-VITAL" title="VHDL-VITAL">VITAL</a></li></ul></li> <li><a href="/wiki/SystemVerilog" title="SystemVerilog">SystemVerilog</a> <ul><li><a href="/wiki/SystemVerilog_DPI" title="SystemVerilog DPI">DPI</a></li></ul></li> <li><a href="/wiki/SystemC" title="SystemC">SystemC</a></li> <li><a href="/wiki/Altera_Hardware_Description_Language" title="Altera Hardware Description Language">AHDL</a></li> <li><a href="/wiki/Handel-C" title="Handel-C">Handel-C</a></li> <li><a href="/wiki/Lola_(computing)" title="Lola (computing)">Lola</a></li> <li><a href="/wiki/Property_Specification_Language" title="Property Specification Language">PSL</a></li> <li><a href="/wiki/Unified_Power_Format" title="Unified Power Format">UPF</a></li> <li><a href="/wiki/PALASM" title="PALASM">PALASM</a></li> <li><a href="/wiki/Advanced_Boolean_Expression_Language" title="Advanced Boolean Expression Language">ABEL</a></li> <li><a href="/wiki/Programmable_Array_Logic#CUPL" title="Programmable Array Logic">CUPL</a></li> <li><a href="/wiki/C_to_HDL" title="C to HDL">C to HDL</a></li> <li><a href="/wiki/Flow_to_HDL" title="Flow to HDL">Flow to HDL</a></li> <li><a href="/wiki/MyHDL" title="MyHDL">MyHDL</a></li> <li><a href="/wiki/ELLA_(programming_language)" title="ELLA (programming language)">ELLA</a></li> <li><a href="/wiki/Chisel_(programming_language)" title="Chisel (programming language)">Chisel</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Companies</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Accellera" title="Accellera">Accellera</a></li> <li><a href="/wiki/Achronix" title="Achronix">Achronix</a></li> <li><a href="/wiki/AMD" title="AMD">AMD</a></li> <li><a href="/wiki/Aldec" title="Aldec">Aldec</a></li> <li><a href="/wiki/Arm_Holdings" title="Arm Holdings">Arm</a></li> <li><a href="/wiki/Cadence_Design_Systems" title="Cadence Design Systems">Cadence</a></li> <li><a href="/wiki/Infineon_Technologies" title="Infineon Technologies">Infineon</a></li> <li><a href="/wiki/Intel" title="Intel">Intel</a></li> <li><a href="/wiki/Lattice_Semiconductor" title="Lattice Semiconductor">Lattice</a></li> <li><a href="/wiki/Microchip_Technology" title="Microchip Technology">Microchip Technology</a></li> <li><a href="/wiki/NXP_Semiconductors" title="NXP Semiconductors">NXP</a></li> <li><a href="/wiki/Siemens" title="Siemens">Siemens</a></li> <li><a href="/wiki/Synopsys" title="Synopsys">Synopsys</a></li> <li><a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Hardware</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ICE_(FPGA)" title="ICE (FPGA)">iCE</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/Virtex_(FPGA)" title="Virtex (FPGA)">Virtex</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Software</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Quartus_Prime" title="Intel Quartus Prime">Intel Quartus Prime</a></li> <li><a href="/wiki/Xilinx_ISE" title="Xilinx ISE">Xilinx ISE</a></li> <li><a href="/wiki/Vivado" title="Vivado">Vivado</a></li> <li><a href="/wiki/ModelSim" title="ModelSim">ModelSim</a></li> <li><a href="/wiki/Verilog-to-Routing" title="Verilog-to-Routing">VTR</a></li> <li><a href="/wiki/List_of_HDL_simulators" title="List of HDL simulators">Simulators</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Intellectual_property" title="Intellectual property">Intellectual property</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Proprietary_hardware" title="Proprietary hardware">Proprietary</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">ARM Cortex-M</a></li> <li><a href="/wiki/LEON" title="LEON">LEON</a></li> <li><a href="/wiki/LatticeMico8" title="LatticeMico8">LatticeMico8</a></li> <li><a href="/wiki/MicroBlaze" title="MicroBlaze">MicroBlaze</a></li> <li><a href="/wiki/PicoBlaze" title="PicoBlaze">PicoBlaze</a></li> <li><a href="/wiki/Nios_embedded_processor" title="Nios embedded processor">Nios</a></li> <li><a href="/wiki/Nios_II" title="Nios II">Nios II</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Open-source_hardware" title="Open-source hardware">Open-source</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Java_Optimized_Processor" title="Java Optimized Processor">JOP</a></li> <li><a href="/wiki/LatticeMico32" title="LatticeMico32">LatticeMico32</a></li> <li><a href="/wiki/OpenCores" title="OpenCores">OpenCores</a></li> <li><a href="/wiki/OpenRISC" title="OpenRISC">OpenRISC</a> <ul><li><a href="/wiki/OpenRISC_1200" title="OpenRISC 1200">1200</a></li></ul></li> <li><a href="/wiki/Power_ISA" title="Power ISA">Power ISA</a> <ul><li><a href="/wiki/Libre-SOC" title="Libre-SOC">Libre-SOC</a></li> <li><a href="/wiki/OpenPOWER_Microwatt" title="OpenPOWER Microwatt">Microwatt</a></li></ul></li> <li><a class="mw-selflink selflink">RISC-V</a></li> <li><a href="/wiki/Zet_(hardware)" title="Zet (hardware)">Zet</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr></tbody></table><div></div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Microcontrollers" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Microcontrollers" title="Template:Microcontrollers"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Microcontrollers" title="Template talk:Microcontrollers"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Microcontrollers" title="Special:EditPage/Template:Microcontrollers"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Microcontrollers" style="font-size:114%;margin:0 4em"><a href="/wiki/Microcontroller" title="Microcontroller">Microcontrollers</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Main</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Single-board_microcontroller" title="Single-board microcontroller">Single-board microcontroller</a></li> <li><a href="/wiki/Special_function_register" title="Special function register">Special function register</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Microarchitecture" title="Microarchitecture">Architectures</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_68000_series" title="Motorola 68000 series">68000</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_architecture_family" title="ARM architecture family">ARM</a></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/MIPS_architecture" title="MIPS architecture">MIPS</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MPS430</a></li> <li><a href="/wiki/PIC_microcontrollers" title="PIC microcontrollers">PIC</a></li> <li><a class="mw-selflink selflink">RISC-V</a></li> <li><a href="/wiki/X86" title="X86">x86</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Word_(computer_architecture)" title="Word (computer architecture)">Word length</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am2900" title="AMD Am2900">Am2900</a></li> <li><a href="/wiki/COP400" title="COP400">COP400</a></li> <li>MARC4</li> <li><a href="/wiki/Rockwell_PPS-4" title="Rockwell PPS-4">PPS-4</a></li> <li><a href="/wiki/S1C6x" title="S1C6x">S1C6x</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-47</a></li> <li><a href="/wiki/Texas_Instruments_TMS1000" title="Texas Instruments TMS1000">TMS1000</a></li> <li><a href="/wiki/%CE%9CCOM-4" class="mw-redirect" title="ΜCOM-4">μCOM-4</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Motorola_6800" title="Motorola 6800">6800</a> <ul><li><a href="/wiki/Motorola_68HC05" title="Motorola 68HC05">68HC05</a></li> <li><a href="/wiki/Motorola_68HC08" title="Motorola 68HC08">68HC08</a></li> <li><a href="/wiki/Motorola_68HC11" title="Motorola 68HC11">68HC11</a></li> <li><a href="/wiki/Freescale_S08" class="mw-redirect" title="Freescale S08">S08</a></li> <li><a href="/wiki/Freescale_RS08" title="Freescale RS08">RS08</a></li></ul></li> <li><a href="/wiki/MOS_Technology_6502" title="MOS Technology 6502">6502</a> <ul><li><a href="/wiki/WDC_65C134" title="WDC 65C134">65C134</a></li> <li><a href="/wiki/WDC_65C265" title="WDC 65C265">65C265</a></li> <li><a href="/wiki/Mitsubishi_740" title="Mitsubishi 740">MELPS 740</a></li></ul></li> <li><a href="/wiki/78K" title="78K">78K</a></li> <li><a href="/wiki/Intel_MCS-48" title="Intel MCS-48">8048</a></li> <li><a href="/wiki/Intel_8051" class="mw-redirect" title="Intel 8051">8051</a> <ul><li><a href="/wiki/XC800_family" title="XC800 family">XC800</a></li></ul></li> <li><a href="/wiki/AVR_microcontrollers" title="AVR microcontrollers">AVR</a></li> <li><a href="/wiki/COP8" title="COP8">COP8</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8</a></li> <li><a href="/wiki/PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">PIC10/12/16/17/18</a></li> <li><a href="/wiki/ST6_and_ST7" title="ST6 and ST7">ST6/ST7</a></li> <li><a href="/wiki/STM8" title="STM8">STM8</a></li> <li><a href="/wiki/Zilog_Z8" title="Zilog Z8">Z8</a></li> <li><a href="/wiki/Zilog_Z80" title="Zilog Z80">Z80</a> <ul><li><a href="/wiki/Zilog_eZ80" title="Zilog eZ80">eZ80</a></li> <li><a href="/wiki/Rabbit_2000" title="Rabbit 2000">Rabbit 2000</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-870</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/WDC_65C816" title="WDC 65C816">65C816</a></li> <li><a href="/wiki/Freescale_68HC12" class="mw-redirect" title="Freescale 68HC12">68HC12</a>/<a href="/wiki/Freescale_68HC16" class="mw-redirect" title="Freescale 68HC16">16</a></li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a></li> <li><a href="/wiki/C166_family" title="C166 family">C166</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CR16/C</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8S</a></li> <li><a href="/wiki/TI_MSP430" title="TI MSP430">MSP430</a></li> <li><a href="/wiki/PIC_microcontroller#PIC24_and_dsPIC" class="mw-redirect" title="PIC microcontroller">PIC24/dsPIC</a></li> <li><a href="/wiki/R8C" title="R8C">R8C</a></li> <li><a href="/wiki/RL78" title="RL78">RL78</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Zilog_Z8000" title="Zilog Z8000">Z8000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/AMD_Am29000" title="AMD Am29000">Am29000</a></li> <li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/List_of_applications_of_ARM_cores" class="mw-redirect" title="List of applications of ARM cores">ARM</a> <a href="/wiki/ARM_Cortex-M" title="ARM Cortex-M">Cortex-M</a> <ul><li><a href="/wiki/EFM32" title="EFM32">EFM32</a></li> <li><a href="/wiki/NXP_LPC" title="NXP LPC">LPC</a></li> <li><a href="/wiki/Atmel_ARM-based_processors" title="Atmel ARM-based processors">SAM</a></li> <li><a href="/wiki/STM32" title="STM32">STM32</a></li> <li><a href="/wiki/Infineon_XMC" title="Infineon XMC">XMC</a></li></ul></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/AVR32" title="AVR32">AVR32</a></li> <li><a href="/wiki/CompactRISC" title="CompactRISC">CRX</a></li> <li><a href="/wiki/Fujitsu_FR" title="Fujitsu FR">FR</a></li> <li><a href="/wiki/FR-V_(microprocessor)" title="FR-V (microprocessor)">FR-V</a></li> <li><a href="/wiki/H8_Family" title="H8 Family">H8SX</a></li> <li><a href="/wiki/M32R" title="M32R">M32R</a></li> <li><a href="/wiki/MN103" title="MN103">MN103</a></li> <li><a href="/wiki/Motorola_68000" title="Motorola 68000">68000</a> <ul><li><a href="/wiki/NXP_ColdFire" title="NXP ColdFire">ColdFire</a></li></ul></li> <li><a href="/wiki/PIC_microcontroller#PIC32MX" class="mw-redirect" title="PIC microcontroller">PIC32</a></li> <li><a href="/wiki/PowerPC" title="PowerPC">PowerPC</a> <ul><li><a href="/wiki/MPC5xx" title="MPC5xx">MPC5xx</a></li></ul></li> <li><a href="/wiki/Parallax_Propeller" title="Parallax Propeller">Propeller</a></li> <li><a href="/wiki/SuperH" title="SuperH">SuperH</a></li> <li><a href="/wiki/Toshiba_TLCS" title="Toshiba TLCS">TLCS-900</a></li> <li><a href="/wiki/Infineon_TriCore" title="Infineon TriCore">TriCore</a></li> <li><a href="/wiki/V850" title="V850">V850</a></li> <li><a href="/wiki/RX_microcontroller_family" class="mw-redirect" title="RX microcontroller family">RX</a></li> <li><a href="/wiki/Tensilica" title="Tensilica">Xtensa</a></li> <li><a href="/wiki/Zilog_Z80000" title="Zilog Z80000">Z80000</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a></th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/ARC_(processor)" title="ARC (processor)">ARC</a></li> <li><a href="/wiki/ARM_Cortex-R" title="ARM Cortex-R">ARM Cortex-R</a></li> <li><a href="/wiki/PowerPC#64-bit_PowerPC" title="PowerPC">PowerPC64</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Interfaces</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%">Programming</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/In-system_programming" title="In-system programming">In-circuit serial programming</a> (ICSP)</li> <li><a href="/wiki/In-system_programming" title="In-system programming">In-system programming</a> (ISP)</li> <li><a href="/wiki/AVR_microcontrollers#PDI" title="AVR microcontrollers">Program and Debug Interface</a> (PDI)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_serial" title="AVR microcontrollers">High-voltage serial programming</a> (HVSP)</li> <li><a href="/wiki/AVR_microcontrollers#High_voltage_parallel" title="AVR microcontrollers">High voltage parallel programming</a> (HVPP)</li> <li><a href="/wiki/AVR_microcontrollers#Bootloader" title="AVR microcontrollers">Bootloader</a></li> <li><a href="/wiki/AVR_microcontrollers#ROM" title="AVR microcontrollers">ROM</a></li> <li><a href="/wiki/AVR_microcontrollers#aWire" title="AVR microcontrollers">aWire</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Debugging</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Nexus_(standard)" title="Nexus (standard)">Nexus (standard)</a></li> <li><a href="/wiki/JTAG" title="JTAG">Joint Test Action Group</a> (JTAG) <ul><li><a href="/wiki/DebugWIRE" title="DebugWIRE">debugWIRE</a> (Atmel)</li></ul></li> <li><a href="/wiki/PIC_microcontroller#In-circuit_debugging" class="mw-redirect" title="PIC microcontroller">In-circuit debugging</a> (ICD)</li> <li><a href="/wiki/In-circuit_emulation" title="In-circuit emulation">In-circuit emulator</a> (ICE)</li> <li><a href="/wiki/In-target_probe" title="In-target probe">In-target probe</a> (ITP)</li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_common_microcontrollers" title="List of common microcontrollers">List of common microcontrollers</a></li> <li>By manufacturer <ul><li><a href="/wiki/Intel_microprocessor#Microcontrollers" class="mw-redirect" title="Intel microprocessor">Intel</a></li> <li><a href="/wiki/List_of_Freescale_products#Microcontrollers" class="mw-redirect" title="List of Freescale products">NXP/Freescale</a></li> <li><a href="/wiki/List_of_common_microcontrollers#Infineon" title="List of common microcontrollers">Infineon</a></li> <li><a href="/wiki/Renesas_Electronics#Products" title="Renesas Electronics">Renesas Electronics</a></li></ul></li> <li><a href="/wiki/List_of_Wi-Fi_microcontrollers" title="List of Wi-Fi microcontrollers">List of Wi-Fi microcontrollers</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">See also</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Embedded_system" title="Embedded system">Embedded system</a></li> <li><a href="/wiki/Programmable_logic_controller" title="Programmable logic controller">Programmable logic controller</a></li> <li><a href="/wiki/List_of_microprocessors" title="List of microprocessors">List of microprocessors</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"></div><div role="navigation" class="navbox" aria-labelledby="Linux_Foundation" style="padding:3px"><table class="nowraplinks mw-collapsible autocollapse navbox-inner" style="border-spacing:0;background:transparent;color:inherit"><tbody><tr><th scope="col" class="navbox-title" colspan="2"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239400231"><div class="navbar plainlinks hlist navbar-mini"><ul><li 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