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<span>Improvements</span> </div> </a> <button aria-controls="toc-Improvements-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Improvements subsection</span> </button> <ul id="toc-Improvements-sublist" class="vector-toc-list"> <li id="toc-Differences_between_i386_and_i486" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Differences_between_i386_and_i486"> <div class="vector-toc-text"> <span class="vector-toc-numb">2.1</span> <span>Differences between i386 and i486</span> </div> </a> <ul id="toc-Differences_between_i386_and_i486-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Models" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Models"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Models</span> </div> </a> <ul id="toc-Models-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Other_makers_of_486-like_CPUs" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Other_makers_of_486-like_CPUs"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>Other makers of 486-like CPUs</span> </div> </a> <ul id="toc-Other_makers_of_486-like_CPUs-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Motherboards_and_buses" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Motherboards_and_buses"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>Motherboards and buses</span> </div> </a> <ul id="toc-Motherboards_and_buses-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Obsolescence" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Obsolescence"> <div class="vector-toc-text"> <span class="vector-toc-numb">6</span> <span>Obsolescence</span> </div> </a> <ul id="toc-Obsolescence-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">7</span> <span>See also</span> </div> </a> <ul id="toc-See_also-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Notes" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Notes"> <div class="vector-toc-text"> <span class="vector-toc-numb">8</span> <span>Notes</span> </div> </a> <ul id="toc-Notes-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Further_reading" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Further_reading"> <div class="vector-toc-text"> <span class="vector-toc-numb">9</span> <span>Further reading</span> </div> </a> <ul id="toc-Further_reading-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">10</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-External_links" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#External_links"> <div class="vector-toc-text"> <span class="vector-toc-numb">11</span> <span>External links</span> </div> </a> <ul id="toc-External_links-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav 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class="firstHeading mw-first-heading">i486</h1> <div id="p-lang-btn" class="vector-dropdown mw-portlet mw-portlet-lang" > <input type="checkbox" id="p-lang-btn-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-p-lang-btn" class="vector-dropdown-checkbox mw-interlanguage-selector" aria-label="Go to an article in another language. Available in 30 languages" > <label id="p-lang-btn-label" for="p-lang-btn-checkbox" class="vector-dropdown-label cdx-button cdx-button--fake-button cdx-button--fake-button--enabled cdx-button--weight-quiet cdx-button--action-progressive mw-portlet-lang-heading-30" aria-hidden="true" ><span class="vector-icon mw-ui-icon-language-progressive mw-ui-icon-wikimedia-language-progressive"></span> <span class="vector-dropdown-label-text">30 languages</span> </label> <div class="vector-dropdown-content"> <div class="vector-menu-content"> <ul class="vector-menu-content-list"> <li class="interlanguage-link interwiki-ar mw-list-item"><a href="https://ar.wikipedia.org/wiki/%D8%A5%D9%86%D8%AA%D9%84_80486" title="إنتل 80486 – Arabic" lang="ar" hreflang="ar" data-title="إنتل 80486" data-language-autonym="العربية" data-language-local-name="Arabic" class="interlanguage-link-target"><span>العربية</span></a></li><li class="interlanguage-link interwiki-ca mw-list-item"><a href="https://ca.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Catalan" lang="ca" hreflang="ca" data-title="Intel 80486" data-language-autonym="Català" data-language-local-name="Catalan" class="interlanguage-link-target"><span>Català</span></a></li><li class="interlanguage-link interwiki-cs mw-list-item"><a href="https://cs.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Czech" lang="cs" hreflang="cs" data-title="Intel 80486" data-language-autonym="Čeština" data-language-local-name="Czech" class="interlanguage-link-target"><span>Čeština</span></a></li><li class="interlanguage-link interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – German" lang="de" hreflang="de" data-title="Intel 80486" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-et mw-list-item"><a href="https://et.wikipedia.org/wiki/Intel_i486" title="Intel i486 – Estonian" lang="et" hreflang="et" data-title="Intel i486" data-language-autonym="Eesti" data-language-local-name="Estonian" class="interlanguage-link-target"><span>Eesti</span></a></li><li class="interlanguage-link interwiki-el mw-list-item"><a href="https://el.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Greek" lang="el" hreflang="el" data-title="Intel 80486" data-language-autonym="Ελληνικά" data-language-local-name="Greek" class="interlanguage-link-target"><span>Ελληνικά</span></a></li><li class="interlanguage-link interwiki-es mw-list-item"><a href="https://es.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Spanish" lang="es" hreflang="es" data-title="Intel 80486" data-language-autonym="Español" data-language-local-name="Spanish" class="interlanguage-link-target"><span>Español</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – French" lang="fr" hreflang="fr" data-title="Intel 80486" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EC%9D%B8%ED%85%94_80486" title="인텔 80486 – Korean" lang="ko" hreflang="ko" data-title="인텔 80486" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-hr mw-list-item"><a href="https://hr.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Croatian" lang="hr" hreflang="hr" data-title="Intel 80486" data-language-autonym="Hrvatski" data-language-local-name="Croatian" class="interlanguage-link-target"><span>Hrvatski</span></a></li><li class="interlanguage-link interwiki-id mw-list-item"><a href="https://id.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Indonesian" lang="id" hreflang="id" data-title="Intel 80486" data-language-autonym="Bahasa Indonesia" data-language-local-name="Indonesian" class="interlanguage-link-target"><span>Bahasa Indonesia</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Italian" lang="it" hreflang="it" data-title="Intel 80486" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-hu mw-list-item"><a href="https://hu.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Hungarian" lang="hu" hreflang="hu" data-title="Intel 80486" data-language-autonym="Magyar" data-language-local-name="Hungarian" class="interlanguage-link-target"><span>Magyar</span></a></li><li class="interlanguage-link interwiki-nl mw-list-item"><a href="https://nl.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Dutch" lang="nl" hreflang="nl" data-title="Intel 80486" data-language-autonym="Nederlands" data-language-local-name="Dutch" class="interlanguage-link-target"><span>Nederlands</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/Intel486" title="Intel486 – Japanese" lang="ja" hreflang="ja" data-title="Intel486" data-language-autonym="日本語" data-language-local-name="Japanese" class="interlanguage-link-target"><span>日本語</span></a></li><li class="interlanguage-link interwiki-no mw-list-item"><a href="https://no.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Norwegian Bokmål" lang="nb" hreflang="nb" data-title="Intel 80486" data-language-autonym="Norsk bokmål" data-language-local-name="Norwegian Bokmål" class="interlanguage-link-target"><span>Norsk bokmål</span></a></li><li class="interlanguage-link interwiki-nn mw-list-item"><a href="https://nn.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Norwegian Nynorsk" lang="nn" hreflang="nn" data-title="Intel 80486" data-language-autonym="Norsk nynorsk" data-language-local-name="Norwegian Nynorsk" class="interlanguage-link-target"><span>Norsk nynorsk</span></a></li><li class="interlanguage-link interwiki-pl mw-list-item"><a href="https://pl.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Polish" lang="pl" hreflang="pl" data-title="Intel 80486" data-language-autonym="Polski" data-language-local-name="Polish" class="interlanguage-link-target"><span>Polski</span></a></li><li class="interlanguage-link interwiki-pt mw-list-item"><a href="https://pt.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Portuguese" lang="pt" hreflang="pt" data-title="Intel 80486" data-language-autonym="Português" data-language-local-name="Portuguese" class="interlanguage-link-target"><span>Português</span></a></li><li class="interlanguage-link interwiki-ro mw-list-item"><a href="https://ro.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Romanian" lang="ro" hreflang="ro" data-title="Intel 80486" data-language-autonym="Română" data-language-local-name="Romanian" class="interlanguage-link-target"><span>Română</span></a></li><li class="interlanguage-link interwiki-ru mw-list-item"><a href="https://ru.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Russian" lang="ru" hreflang="ru" data-title="Intel 80486" data-language-autonym="Русский" data-language-local-name="Russian" class="interlanguage-link-target"><span>Русский</span></a></li><li class="interlanguage-link interwiki-sk mw-list-item"><a href="https://sk.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Slovak" lang="sk" hreflang="sk" data-title="Intel 80486" data-language-autonym="Slovenčina" data-language-local-name="Slovak" class="interlanguage-link-target"><span>Slovenčina</span></a></li><li class="interlanguage-link interwiki-sh mw-list-item"><a href="https://sh.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Serbo-Croatian" lang="sh" hreflang="sh" data-title="Intel 80486" data-language-autonym="Srpskohrvatski / српскохрватски" data-language-local-name="Serbo-Croatian" class="interlanguage-link-target"><span>Srpskohrvatski / српскохрватски</span></a></li><li class="interlanguage-link interwiki-fi mw-list-item"><a href="https://fi.wikipedia.org/wiki/Intel_i486" title="Intel i486 – Finnish" lang="fi" hreflang="fi" data-title="Intel i486" data-language-autonym="Suomi" data-language-local-name="Finnish" class="interlanguage-link-target"><span>Suomi</span></a></li><li class="interlanguage-link interwiki-sv mw-list-item"><a href="https://sv.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Swedish" lang="sv" hreflang="sv" data-title="Intel 80486" data-language-autonym="Svenska" data-language-local-name="Swedish" class="interlanguage-link-target"><span>Svenska</span></a></li><li class="interlanguage-link interwiki-tr mw-list-item"><a href="https://tr.wikipedia.org/wiki/%C4%B0486" title="İ486 – Turkish" lang="tr" hreflang="tr" data-title="İ486" data-language-autonym="Türkçe" data-language-local-name="Turkish" class="interlanguage-link-target"><span>Türkçe</span></a></li><li class="interlanguage-link interwiki-uk mw-list-item"><a href="https://uk.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Ukrainian" lang="uk" hreflang="uk" data-title="Intel 80486" data-language-autonym="Українська" data-language-local-name="Ukrainian" class="interlanguage-link-target"><span>Українська</span></a></li><li class="interlanguage-link interwiki-vi mw-list-item"><a href="https://vi.wikipedia.org/wiki/I486" title="I486 – Vietnamese" lang="vi" hreflang="vi" data-title="I486" data-language-autonym="Tiếng Việt" data-language-local-name="Vietnamese" class="interlanguage-link-target"><span>Tiếng Việt</span></a></li><li class="interlanguage-link interwiki-wuu mw-list-item"><a href="https://wuu.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Wu" lang="wuu" hreflang="wuu" data-title="Intel 80486" data-language-autonym="吴语" data-language-local-name="Wu" class="interlanguage-link-target"><span>吴语</span></a></li><li class="interlanguage-link interwiki-zh mw-list-item"><a href="https://zh.wikipedia.org/wiki/Intel_80486" title="Intel 80486 – Chinese" lang="zh" hreflang="zh" data-title="Intel 80486" data-language-autonym="中文" data-language-local-name="Chinese" class="interlanguage-link-target"><span>中文</span></a></li> </ul> <div class="after-portlet after-portlet-lang"><span class="wb-langlinks-edit wb-langlinks-link"><a href="https://www.wikidata.org/wiki/Special:EntityPage/Q213423#sitelinks-wikipedia" title="Edit interlanguage links" class="wbc-editpage">Edit links</a></span></div> </div> </div> </div> </header> <div class="vector-page-toolbar"> <div class="vector-page-toolbar-container"> <div id="left-navigation"> <nav aria-label="Namespaces"> <div id="p-associated-pages" class="vector-menu vector-menu-tabs mw-portlet mw-portlet-associated-pages" > <div class="vector-menu-content"> <ul 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class="vector-body" aria-labelledby="firstHeading" data-mw-ve-target-container> <div class="vector-body-before-content"> <div class="mw-indicators"> </div> <div id="siteSub" class="noprint">From Wikipedia, the free encyclopedia</div> </div> <div id="contentSub"><div id="mw-content-subtitle"><span class="mw-redirectedfrom">(Redirected from <a href="/w/index.php?title=Intel_80486&redirect=no" class="mw-redirect" title="Intel 80486">Intel 80486</a>)</span></div></div> <div id="mw-content-text" class="mw-body-content"><div class="mw-content-ltr mw-parser-output" lang="en" dir="ltr"><div class="shortdescription nomobile noexcerpt noprint searchaux" style="display:none">Successor to the Intel 386</div> <p class="mw-empty-elt"> </p> <style data-mw-deduplicate="TemplateStyles:r1257001546">.mw-parser-output .infobox-subbox{padding:0;border:none;margin:-3px;width:auto;min-width:100%;font-size:100%;clear:none;float:none;background-color:transparent}.mw-parser-output .infobox-3cols-child{margin:auto}.mw-parser-output .infobox .navbar{font-size:100%}@media screen{html.skin-theme-clientpref-night .mw-parser-output .infobox-full-data:not(.notheme)>div:not(.notheme)[style]{background:#1f1f23!important;color:#f8f9fa}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .infobox-full-data:not(.notheme) div:not(.notheme){background:#1f1f23!important;color:#f8f9fa}}@media(min-width:640px){body.skin--responsive .mw-parser-output .infobox-table{display:table!important}body.skin--responsive .mw-parser-output .infobox-table>caption{display:table-caption!important}body.skin--responsive .mw-parser-output .infobox-table>tbody{display:table-row-group}body.skin--responsive .mw-parser-output .infobox-table tr{display:table-row!important}body.skin--responsive .mw-parser-output .infobox-table th,body.skin--responsive .mw-parser-output .infobox-table td{padding-left:inherit;padding-right:inherit}}</style><table class="infobox"><caption class="infobox-title">i486</caption><tbody><tr><td colspan="2" class="infobox-image"><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:Intel_i486_logo.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Intel_i486_logo.svg/110px-Intel_i486_logo.svg.png" decoding="async" width="110" height="48" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Intel_i486_logo.svg/165px-Intel_i486_logo.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/1f/Intel_i486_logo.svg/220px-Intel_i486_logo.svg.png 2x" data-file-width="873" data-file-height="381" /></a></span><div class="paragraphbreak" style="margin-top:0.5em"></div><span class="mw-default-size" typeof="mw:File/Frameless"><a href="/wiki/File:80486dx2-large.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/220px-80486dx2-large.jpg" decoding="async" width="220" height="164" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/330px-80486dx2-large.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/02/80486dx2-large.jpg/440px-80486dx2-large.jpg 2x" data-file-width="1341" data-file-height="1002" /></a></span><div class="infobox-caption">The exposed die of an Intel 486DX2</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">April 10, 1989<sup id="cite_ref-Lewnes,_Ann_1989,_page_2_2-0" class="reference"><a href="#cite_note-Lewnes,_Ann_1989,_page_2-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">September 28, 2007<sup id="cite_ref-i486LastShipment2007_1-0" class="reference"><a href="#cite_note-i486LastShipment2007-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Designed by</th><td class="infobox-data"><a href="/wiki/Intel" title="Intel">Intel</a>, with <a href="/wiki/Pat_Gelsinger" title="Pat Gelsinger">Pat Gelsinger</a> as chief architect</td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">.mw-parser-output .plainlist ol,.mw-parser-output .plainlist ul{line-height:inherit;list-style:none;margin:0;padding:0}.mw-parser-output .plainlist ol li,.mw-parser-output .plainlist ul li{margin-bottom:0}</style><div class="plainlist"><ul><li>Intel, <a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/AMD" title="AMD">AMD</a>, <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, <a href="/wiki/Harris_Semiconductor" class="mw-redirect" title="Harris Semiconductor">Harris Semiconductor</a>, <a href="/wiki/United_Microelectronics_Corporation" title="United Microelectronics Corporation">UMC</a>, <a href="/wiki/STMicroelectronics" title="STMicroelectronics">SGS Thomson</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="/wiki/Central_processing_unit" title="Central processing unit">CPU</a> <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">16  to 100 MHz<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>a<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Front-side_bus" title="Front-side bus">FSB</a> speeds</th><td class="infobox-data">16 MHz to 50 MHz</td></tr><tr><th scope="row" class="infobox-label">Data width</th><td class="infobox-data">32 bits<sup id="cite_ref-486ref_3-0" class="reference"><a href="#cite_note-486ref-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Address width</th><td class="infobox-data">32 bits<sup id="cite_ref-486ref_3-1" class="reference"><a href="#cite_note-486ref-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></td></tr><tr><th scope="row" class="infobox-label">Virtual address width</th><td class="infobox-data">32 bits (linear); 46 bits (logical)<sup id="cite_ref-486ref_3-2" class="reference"><a href="#cite_note-486ref-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup></td></tr><tr><th colspan="2" class="infobox-header">Cache</th></tr><tr><th scope="row" class="infobox-label">L1 <a href="/wiki/CPU_cache" title="CPU cache">cache</a></th><td class="infobox-data">8 KB to 16 KB</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data">1 μm to 600 nm</td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="/wiki/X86-16" class="mw-redirect" title="X86-16">x86-16</a>, <a href="/wiki/IA-32" title="IA-32">IA-32</a> including <a href="/wiki/X87" title="X87">x87</a> (except for "<a href="/wiki/I486SX" title="I486SX">SX</a>" models)</td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Transistor_count" title="Transistor count">Transistors</a></th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>1.2<sup id="cite_ref-Lewnes,_Ann_1989,_page_2_2-1" class="reference"><a href="#cite_note-Lewnes,_Ann_1989,_page_2-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup>–1.6 million</li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="/wiki/Co-processor" class="mw-redirect" title="Co-processor">Co-processor</a></th><td class="infobox-data"><a href="/wiki/Intel_80487SX" class="mw-redirect" title="Intel 80487SX">Intel 80487SX</a></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>168-pin <a href="/wiki/Pin_grid_array" title="Pin grid array">PGA</a>, 196-pin <a href="/wiki/PQFP" class="mw-redirect" title="PQFP">PQFP</a>, 208-pin <a href="/wiki/SQFP" class="mw-redirect" title="SQFP">SQFP</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1126788409"><div class="plainlist"><ul><li>PGA168, <a href="/wiki/Socket_1" title="Socket 1">Socket 1</a>, <a href="/wiki/Socket_2" title="Socket 2">2</a>, <a href="/wiki/Socket_3" title="Socket 3">3</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="/wiki/I386" title="I386">Intel 386</a></td></tr><tr><th scope="row" class="infobox-label">Successor</th><td class="infobox-data"><a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium/i586 (P5)</a></td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table> <p>The <a href="/wiki/Intel" title="Intel">Intel</a> <b>486</b>, officially named <b>i486</b> and also known as <b>80486</b>, is a <a href="/wiki/Microprocessor" title="Microprocessor">microprocessor</a> introduced in 1989. It is a higher-performance follow-up to the <a href="/wiki/I386" title="I386">Intel 386</a>. It represents the fourth generation of <a href="/wiki/Binary_compatible" class="mw-redirect" title="Binary compatible">binary compatible</a> CPUs following the <a href="/wiki/Intel_8086" title="Intel 8086">8086</a> of 1978, the <a href="/wiki/Intel_80286" title="Intel 80286">Intel 80286</a> of 1982, and 1985's <a href="/wiki/I386" title="I386">i386</a>. </p><p>It was the first tightly-<a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipelined</a><sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>c<span class="cite-bracket">]</span></a></sup> <a href="/wiki/X86" title="X86">x86</a> design as well as the first x86 chip to include more than one million transistors. It offered a large on-chip <a href="/wiki/Cache_(computing)" title="Cache (computing)">cache</a> and an integrated <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a>. When it was announced, the initial performance was originally published between 15 and 20 <a href="/wiki/VAX_Unit_of_Performance" title="VAX Unit of Performance">VAX MIPS</a>, between 37,000 and 49,000 <a href="/wiki/Dhrystone" title="Dhrystone">dhrystones per second</a>, and between 6.1 and 8.2 double-precision <a href="/wiki/Whetstone_(benchmark)" title="Whetstone (benchmark)">megawhetstones per second</a> for both 25 and 33 MHz version.<sup id="cite_ref-Lewnes,_Ann_1989,_page_2_2-2" class="reference"><a href="#cite_note-Lewnes,_Ann_1989,_page_2-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> A typical 50 MHz i486 executes 41 million <a href="/wiki/Instructions_per_second" title="Instructions per second">instructions per second</a> Dhrystone MIPS and <a href="/wiki/SPECint" title="SPECint">SPEC integer</a> rating of 27.9.<sup id="cite_ref-7" class="reference"><a href="#cite_note-7"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup> It is approximately twice as fast as the i386 or i286 per <a href="/wiki/Clock_signal" title="Clock signal">clock cycle</a>. The i486's improved performance is thanks to its five-stage pipeline with all stages bound to a single cycle. The enhanced FPU unit on the chip was significantly faster than the <a href="/wiki/I387" class="mw-redirect" title="I387">i387</a> FPU per cycle. The i387 FPU was a separate, optional math coprocessor installed in a motherboard socket alongside the i386.<sup id="cite_ref-8" class="reference"><a href="#cite_note-8"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup> </p><p>The i486 was succeeded by the <a href="/wiki/Pentium_(original)" title="Pentium (original)">original Pentium</a>. Orders were discontinued for the i486 on March 30, 2007 and the last shipments were on September 28, 2007.<sup id="cite_ref-i486LastShipment2007_1-1" class="reference"><a href="#cite_note-i486LastShipment2007-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="History">History</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=1" title="Edit section: History"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The concept of this microprocessor generation was discussed with Pat Gelsinger and <a href="/wiki/John_Crawford_(engineer)" title="John Crawford (engineer)">John Crawford</a> shortly after the release of <a href="/wiki/I386" title="I386">386 processor</a> in 1985. The team started the computer simulation in early 1987. They finalized the logic and microcode function during 1988. The team finalized the database in February 1989 until the <a href="/wiki/Tape-out" title="Tape-out">tape out</a> on March 1. They received the first silicon from the fabrication on March 20.<sup id="cite_ref-Chen,_Allan_1989,_page_12_9-0" class="reference"><a href="#cite_note-Chen,_Allan_1989,_page_12-9"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> </p><p>The i486 was announced at Spring <a href="/wiki/COMDEX" title="COMDEX">Comdex</a> in April 10, 1989.<sup id="cite_ref-Lewnes,_Ann_1989,_page_2_2-3" class="reference"><a href="#cite_note-Lewnes,_Ann_1989,_page_2-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> At the announcement, Intel stated that samples would be available in the third quarter and production quantities would ship in the fourth quarter.<sup id="cite_ref-10" class="reference"><a href="#cite_note-10"><span class="cite-bracket">[</span>7<span class="cite-bracket">]</span></a></sup> The first i486-based PCs were announced in late 1989.<sup id="cite_ref-11" class="reference"><a href="#cite_note-11"><span class="cite-bracket">[</span>8<span class="cite-bracket">]</span></a></sup> </p><p>In fall of 1991, Intel introduced the 50 MHz i486 DX using the three layer <a href="/wiki/800_nm_process" title="800 nm process">800 nm process</a> <a href="/wiki/CHMOS" title="CHMOS">CHMOS-V</a> technology. They were available for US$665 in 1,000-unit quantities.<sup id="cite_ref-12" class="reference"><a href="#cite_note-12"><span class="cite-bracket">[</span>9<span class="cite-bracket">]</span></a></sup> </p><p>In that season, Intel introduced low-power 25 MHz Intel486 DX microprocessor. This one was available for US$471. Also, there were low-power 16, 20, and 25 MHz Intel486 SX microprocessors. They were available at $235, $266, and $366 for these frequency range respectively. All pricing were in quantities of 1,000 pieces. These low-power microprocessors have power consumption reduced by 50–75% compared to similar regular versions of these CPUs.<sup id="cite_ref-13" class="reference"><a href="#cite_note-13"><span class="cite-bracket">[</span>10<span class="cite-bracket">]</span></a></sup> </p><p>The first major update to the i486 design came in March 1992 with the release of the clock-doubled <a href="/wiki/Intel_DX2" title="Intel DX2">486DX2</a> series.<sup id="cite_ref-:0_14-0" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> It was the first time that the CPU core clock frequency was separated from the <a href="/wiki/System_bus" title="System bus">system bus</a> clock frequency by using a dual clock multiplier, supporting 486DX2 chips at 40 and 50 MHz. The faster 66 MHz 486DX2-66 was released that August.<sup id="cite_ref-:0_14-1" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>The fifth-generation <a href="/wiki/Pentium_(original)" title="Pentium (original)">Pentium</a> processor launched in 1993, while Intel continued to produce i486 processors, including the triple-clock-rate <a href="/wiki/Intel_DX4" title="Intel DX4">486DX4-100</a> with a 100 MHz clock speed and a L1 cache doubled to 16 KB.<sup id="cite_ref-:0_14-2" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>Earlier, Intel had decided not to share its 80386 and 80486 technologies with AMD. However, AMD believed that their technology sharing agreement extended to the 80386 as a derivative of the 80286.<sup id="cite_ref-:0_14-3" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> AMD reverse-engineered the 386 and produced the 40 MHz <a href="/wiki/Am386" title="Am386">Am386DX-40</a> chip, which was cheaper and had lower power consumption than Intel's best 33 MHz version.<sup id="cite_ref-:0_14-4" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Intel attempted to prevent AMD from selling the processor, but AMD won in court, which allowed it to establish itself as a competitor.<sup id="cite_ref-:1_15-0" class="reference"><a href="#cite_note-:1-15"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> </p><p>AMD continued to create clones, releasing the first-generation <a href="/wiki/Am486" title="Am486">Am486</a> chip in April 1993 with clock frequencies of 25, 33 and 40 MHz. Second-generation Am486DX2 chips with 50, 66 and 80 MHz clock frequencies were released the following year.<sup id="cite_ref-:0_14-5" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> The Am486 series was completed with a 120 MHz DX4 chip in 1995.<sup id="cite_ref-:0_14-6" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>AMD's long-running 1987 arbitration lawsuit against Intel was settled in 1995, and AMD gained access to Intel's 80486 microcode.<sup id="cite_ref-:0_14-7" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> This led to the creation of two versions of AMD's 486 processor –  one reverse-engineered from Intel's microcode, while the other used AMD's microcode in a <a href="/wiki/Clean-room_design" title="Clean-room design">clean-room design</a> process. However, the settlement also concluded that the 80486 would be AMD's last Intel clone.<sup id="cite_ref-:0_14-8" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>Another 486 clone manufacturer was <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a>, which was a <a href="/wiki/Fabless_manufacturing" title="Fabless manufacturing">fabless</a> co-processor chip maker for 80286/386 systems. The first <a href="/wiki/Cyrix_Cx486" title="Cyrix Cx486">Cyrix 486</a> processors, the 486SLC and 486DLC, were released in 1992 and used the 80386 package.<sup id="cite_ref-:0_14-9" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Both <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a>-manufactured Cyrix processors were pin-compatible with 386SX/DX systems, which allowed them to become an upgrade option.<sup id="cite_ref-:1_15-1" class="reference"><a href="#cite_note-:1-15"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> However, these chips could not match the Intel 486 processors, having only 1 KB of cache memory and no built-in math coprocessor. In 1993, Cyrix released its own Cx486DX and DX2 processors, which were closer in performance to Intel's counterparts. Intel and Cyrix sued each other, with Intel filing for <a href="/wiki/Patent_infringement" title="Patent infringement">patent infringement</a>, and Cyrix for <a href="/wiki/Antitrust" class="mw-redirect" title="Antitrust">antitrust</a> claims. In 1994, Cyrix won the patent infringement case and dropped its antitrust claim.<sup id="cite_ref-:0_14-10" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>In 1995, both Cyrix and AMD began looking at a ready market for users wanting to upgrade their processors. Cyrix released a derivative 486 processor called the <a href="/wiki/Cyrix_5x86" title="Cyrix 5x86">5x86</a>, based on the Cyrix M1 core, which was clocked up to 120 MHz and was an option for 486 Socket 3 motherboards.<sup id="cite_ref-:0_14-11" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:1_15-2" class="reference"><a href="#cite_note-:1-15"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> AMD released a 133 MHz <a href="/wiki/Am5x86" title="Am5x86">Am5x86</a> upgrade chip, which was essentially an improved 80486 with double the cache and a quad multiplier that also worked with the original 486DX motherboards.<sup id="cite_ref-:0_14-12" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> Am5x86 was the first processor to use AMD's performance rating and was marketed as Am5x86-P75, with claims that it was equivalent to the Pentium 75.<sup id="cite_ref-:1_15-3" class="reference"><a href="#cite_note-:1-15"><span class="cite-bracket">[</span>12<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Kingston_Technology" title="Kingston Technology">Kingston Technology</a> launched a "TurboChip" 486 system upgrade that used a 133 MHz Am5x86.<sup id="cite_ref-:0_14-13" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p><p>Intel responded by making a <a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">Pentium OverDrive</a> upgrade chip for 486 motherboards, which was a modified Pentium core that ran up to 83 MHz on boards with a 25 or 33 MHz front-side bus clock. OverDrive wasn't popular due to speed and price.<sup id="cite_ref-:0_14-14" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> New computers equipped with 486 processors in discount warehouses became scarce, and an <a href="/wiki/IBM" title="IBM">IBM</a> spokesperson called it a "dinosaur".<sup id="cite_ref-chauvet-1996_16-0" class="reference"><a href="#cite_note-chauvet-1996-16"><span class="cite-bracket">[</span>13<span class="cite-bracket">]</span></a></sup> Even after the Pentium series of processors gained a foothold in the market, however, Intel continued to produce 486 cores for industrial embedded applications. Intel discontinued production of i486 processors in late 2007.<sup id="cite_ref-i486LastShipment2007_1-2" class="reference"><a href="#cite_note-i486LastShipment2007-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-:0_14-15" class="reference"><a href="#cite_note-:0-14"><span class="cite-bracket">[</span>11<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="Improvements">Improvements</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=2" title="Edit section: Improvements"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:80486DX2_arch.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/4/42/80486DX2_arch.svg/300px-80486DX2_arch.svg.png" decoding="async" width="300" height="217" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/4/42/80486DX2_arch.svg/450px-80486DX2_arch.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/4/42/80486DX2_arch.svg/600px-80486DX2_arch.svg.png 2x" data-file-width="1477" data-file-height="1069" /></a><figcaption>The 486DX2 architecture</figcaption></figure> <table class="infobox" style="font-size:88%;width:34em;"> <caption>i486 registers </caption> <tbody><tr> <td> <table style="font-size:88%"> <tbody><tr> <td style="width:10px; text-align:center"><sup>3</sup><sub>1</sub> </td> <td style="width:120px; text-align:center">... </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>5</sub> </td> <td style="width:50px; text-align:center">... </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>7</sub> </td> <td style="width:35px; text-align:center">... </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>0</sub> </td> <td style="width:auto; background:white; color:black"><i>(bit position)</i> </td></tr> <tr> <td colspan="8"><b>Main registers</b> <i>(8/16/32 bits)</i> </td></tr> <tr style="background:silver;color:black;text-align:left"> <td style="text-align:center" colspan="2">EAX </td> <td style="text-align:center" colspan="2">AH </td> <td style="text-align:center" colspan="3">AL </td> <td style="background:white; color:black"><b>A</b> register </td></tr> <tr style="background:silver;color:black;text-align:left"> <td style="text-align:center" colspan="2">EBX </td> <td style="text-align:center" colspan="2">BH </td> <td style="text-align:center" colspan="3">BL </td> <td style="background:white; color:black"><b>B</b> register </td></tr> <tr style="background:silver;color:black;text-align:left"> <td style="text-align:center" colspan="2">ECX </td> <td style="text-align:center" colspan="2">CH </td> <td style="text-align:center" colspan="3">CL </td> <td style="background:white; color:black"><b>C</b> register </td></tr> <tr style="background:silver;color:black;text-align:left"> <td style="text-align:center" colspan="2">EDX </td> <td style="text-align:center" colspan="2">DH </td> <td style="text-align:center" colspan="3">DL </td> <td style="background:white; color:black"><b>D</b> register </td></tr> <tr> <td colspan="8"><b>Index registers</b> <i>(16/32 bits)</i> </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center" colspan="2">ESI </td> <td style="text-align:center" colspan="5">SI </td> <td style="background:white; color:black"><b>S</b>ource <b>I</b>ndex </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center" colspan="2">EDI </td> <td style="text-align:center" colspan="5">DI </td> <td style="background:white; color:black"><b>D</b>estination <b>I</b>ndex </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center" colspan="2">EBP </td> <td style="text-align:center" colspan="5">BP </td> <td style="background:white; color:black"><b>B</b>ase <b>P</b>ointer </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center" colspan="2">ESP </td> <td style="text-align:center" colspan="5">SP </td> <td style="background:white; color:black"><b>S</b>tack <b>P</b>ointer </td></tr> <tr> <td colspan="8"><b>Program counter</b> <i>(16/32 bits)</i> </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center" colspan="2">EIP </td> <td style="text-align:center" colspan="5">IP </td> <td style="background:white; color:black"><b>I</b>nstruction <b>P</b>ointer </td></tr> <tr> <td colspan="8"><b>Segment selectors</b> <i>(16 bits)</i> </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">CS </td> <td style="background:white; color:black"><b>C</b>ode <b>S</b>egment </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">DS </td> <td style="background:white; color:black"><b>D</b>ata <b>S</b>egment </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">ES </td> <td style="background:white; color:black"><b>E</b>xtra <b>S</b>egment </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">FS </td> <td style="background:white; color:black"><b>F</b> <b>S</b>egment </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">GS </td> <td style="background:white; color:black"><b>G</b> <b>S</b>egment </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF" colspan="2">  </td> <td style="text-align:center" colspan="5">SS </td> <td style="background:white; color:black"><b>S</b>tack <b>S</b>egment </td></tr></tbody></table> </td></tr> <tr> <td> <table style="font-size:88%"> <tbody><tr> <td colspan="20"><b>Status register</b> </td></tr> <tr> <td style="width:20px; text-align:center">  </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>7</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>6</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>5</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>4</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>3</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>2</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>1</sub> </td> <td style="width:10px; text-align:center"><sup>1</sup><sub>0</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>9</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>8</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>7</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>6</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>5</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>4</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>3</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>2</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>1</sub> </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>0</sub> </td> <td style="width:auto; background:white; color:black"><i>(bit position)</i> </td></tr> <tr style="background:silver;color:black"> <td style="text-align:center;background:#FFF">  </td> <td style="text-align:center"><a href="/wiki/Virtual_8086_mode" title="Virtual 8086 mode">V</a> </td> <td style="text-align:center">R </td> <td style="text-align:center">0 </td> <td style="text-align:center">N </td> <td style="text-align:center" colspan="2"><a href="/wiki/IOPL" class="mw-redirect" title="IOPL">IOPL</a> </td> <td style="text-align:center"><a href="/wiki/Overflow_flag" title="Overflow flag">O</a> </td> <td style="text-align:center"><a href="/wiki/Direction_flag" title="Direction flag">D</a> </td> <td style="text-align:center"><a href="/wiki/IF_(x86_flag)" class="mw-redirect" title="IF (x86 flag)">I</a> </td> <td style="text-align:center"><a href="/wiki/Trap_flag" title="Trap flag">T</a> </td> <td style="text-align:center"><a href="/wiki/Sign_flag" class="mw-redirect" title="Sign flag">S</a> </td> <td style="text-align:center"><a href="/wiki/Zero_flag" title="Zero flag">Z</a> </td> <td style="text-align:center">0 </td> <td style="text-align:center"><a href="/wiki/Adjust_flag" class="mw-redirect" title="Adjust flag">A</a> </td> <td style="text-align:center">0 </td> <td style="text-align:center"><a href="/wiki/Parity_flag" title="Parity flag">P</a> </td> <td style="text-align:center">1 </td> <td style="text-align:center"><a href="/wiki/Carry_flag" title="Carry flag">C</a> </td> <td style="background:white; color:black"><a href="/wiki/FLAGS_register" title="FLAGS register">EFlags</a> </td></tr></tbody></table> </td></tr> <tr> <td> <table style="font-size:88%"> <tbody><tr> <td colspan="3"><b>Floating-point registers</b> <i>(80 bits)</i> </td></tr> <tr> <td style="width:10px; text-align:center"><sup>7</sup><sub>9</sub> </td> <td style="width:245px; text-align:center">... </td> <td style="width:10px; text-align:center"><sup>0</sup><sub>0</sub> </td> <td style="width:auto; background:white; color:black"><i>(bit position)</i> </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST0 </td> <td style="background:white; color:black"><b>ST</b>ack register 0 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST1 </td> <td style="background:white; color:black"><b>ST</b>ack register 1 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST2 </td> <td style="background:white; color:black"><b>ST</b>ack register 2 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST3 </td> <td style="background:white; color:black"><b>ST</b>ack register 3 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST4 </td> <td style="background:white; color:black"><b>ST</b>ack register 4 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST5 </td> <td style="background:white; color:black"><b>ST</b>ack register 5 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST6 </td> <td style="background:white; color:black"><b>ST</b>ack register 6 </td></tr> <tr style="background:silver"> <td style="text-align:center" colspan="3">ST7 </td> <td style="background:white; color:black"><b>ST</b>ack register 7 </td></tr></tbody></table> </td></tr></tbody></table> <p>The <a href="/wiki/Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> of the i486 is very similar to the i386, with the addition of a few extra instructions, such as CMPXCHG, a <a href="/wiki/Compare-and-swap" title="Compare-and-swap">compare-and-swap</a> <a href="/wiki/Atomic_operation" class="mw-redirect" title="Atomic operation">atomic operation</a>, and XADD, a <a href="/wiki/Fetch-and-add" title="Fetch-and-add">fetch-and-add</a> atomic operation that returned the original value (unlike a standard ADD, which returns flags only). This generation CPU has brought up to 156 different instructions listing.<sup id="cite_ref-17" class="reference"><a href="#cite_note-17"><span class="cite-bracket">[</span>14<span class="cite-bracket">]</span></a></sup> </p><p>The i486's performance architecture is a vast improvement over the i386. It has an on-chip unified instruction and data <a href="/wiki/CPU_cache" title="CPU cache">cache</a>, an on-chip <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU) and an enhanced <a href="/wiki/Computer_bus" class="mw-redirect" title="Computer bus">bus</a> interface unit.<sup id="cite_ref-18" class="reference"><a href="#cite_note-18"><span class="cite-bracket">[</span>15<span class="cite-bracket">]</span></a></sup> Due to the tight pipelining, sequences of simple instructions (such as <code>ALU reg,reg</code> and <code>ALU reg,im</code>) could sustain single-clock-cycle throughput (one instruction completed every clock). In other words, it was running about 1.8 clocks per instruction.<sup id="cite_ref-Chen,_Allan_1989,_page_12_9-1" class="reference"><a href="#cite_note-Chen,_Allan_1989,_page_12-9"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> These improvements yielded a rough doubling in integer <a href="/wiki/Arithmetic_logic_unit" title="Arithmetic logic unit">ALU</a> performance over the i386 at the same <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a>. A 16 MHz i486 therefore had performance similar to a 33 MHz i386. With the combination both CPU and NPU house in the die would have bus utilization rate of 50% for the 25 MHz Intel486 version.<sup id="cite_ref-19" class="reference"><a href="#cite_note-19"><span class="cite-bracket">[</span>16<span class="cite-bracket">]</span></a></sup> In other words, with the combination of both CPU and MCP (math coprocessor) provides 40% more performance than with both Intel386 DX and Intel387 DX math coprocessor combined.<sup id="cite_ref-20" class="reference"><a href="#cite_note-20"><span class="cite-bracket">[</span>17<span class="cite-bracket">]</span></a></sup> The older design had to reach 50 MHz to be comparable with a 25 MHz i486 part.<sup id="cite_ref-21" class="reference"><a href="#cite_note-21"><span class="cite-bracket">[</span>d<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading3"><h3 id="Differences_between_i386_and_i486">Differences between i386 and i486</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=3" title="Edit section: Differences between i386 and i486"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>An 8 <a href="/wiki/Kilobyte" title="Kilobyte">KB</a> on-chip (level 1) <a href="/wiki/Static_random_access_memory" class="mw-redirect" title="Static random access memory">SRAM</a> <a href="/wiki/CPU_cache" title="CPU cache">cache</a> stores the most recently used instructions and data (16 KB and/or <a href="/wiki/Cache_(computing)#Operation" title="Cache (computing)">write-back</a> on some later models). The <a href="/wiki/I386" title="I386">i386</a> had no internal cache but supported a slower off-chip cache (not officially a <a href="/wiki/Level_2_cache" class="mw-redirect" title="Level 2 cache">level 2 cache</a> because i386 had no internal level 1 cache).</li> <li>An enhanced external bus protocol to enable cache coherency and a new burst mode for memory accesses to fill a cache line of 16 bytes within five bus cycles. The 386 needed eight bus cycles to transfer the same amount of data.</li> <li>Tightly coupled<sup id="cite_ref-fn1_5-1" class="reference"><a href="#cite_note-fn1-5"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Instruction_pipeline" class="mw-redirect" title="Instruction pipeline">pipelining</a> completes a simple instruction like ALU <i>reg,reg</i> or ALU <i>reg,im</i> every clock cycle (after a latency of several cycles). The i386 needed two clock cycles.</li> <li>Integrated <a href="/wiki/Floating_point_unit" class="mw-redirect" title="Floating point unit">FPU</a> (disabled or absent in <a href="/wiki/Intel_80486SX" class="mw-redirect" title="Intel 80486SX">SX models</a>) with a dedicated <a href="/wiki/Local_bus" title="Local bus">local bus</a>; together with faster algorithms on more extensive hardware than in the i387, this performed floating-point calculations faster than the <a href="/wiki/I386" title="I386">i386</a>/<a href="/wiki/I387" class="mw-redirect" title="I387">i387</a> combination.</li> <li>Improved <a href="/wiki/Memory_management_unit" title="Memory management unit">MMU</a> performance.</li> <li>New instructions: XADD, BSWAP, CMPXCHG, INVD, WBINVD, INVLPG.</li></ul> <p>Just as in the i386, a flat 4 GB memory model could be implemented. All "segment selector" registers could be set to a neutral value in <a href="/wiki/Protected_mode" title="Protected mode">protected mode</a>, or to zero in <a href="/wiki/Real_mode" title="Real mode">real mode</a>, and using only the 32-bit "offset registers" (x86-terminology for general CPU registers used as address registers) as a linear 32-bit virtual address bypassing the segmentation logic. Virtual addresses were then normally mapped onto physical addresses by the paging system except when it was disabled (<i>real</i> mode had no <i>virtual</i> addresses). Just as with the i386, circumventing memory segmentation could substantially improve performance for some <a href="/wiki/Operating_systems" class="mw-redirect" title="Operating systems">operating systems</a> and applications. </p><p>On a typical PC <a href="/wiki/Motherboard" title="Motherboard">motherboard</a>, either four matched 30-pin (8-bit) <a href="/wiki/SIMM" title="SIMM">SIMMs</a> or one 72-pin (32-bit) SIMM per bank were required to fit the i486's <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> <a href="/wiki/Bus_(computing)" title="Bus (computing)">data bus</a>. The <a href="/wiki/Address_bus" class="mw-redirect" title="Address bus">address bus</a> used 30-bits (A31..A2) complemented by four byte-select pins (instead of A0,A1) to allow for any 8/16/32-bit selection. This meant that the limit of directly addressable physical memory was 4 <a href="/wiki/Gigabyte" title="Gigabyte">gigabytes</a> as well (2<sup>30</sup> <i>32-bit</i> words = 2<sup>32</sup> <i>8-bit</i> words). </p> <div class="mw-heading mw-heading2"><h2 id="Models">Models</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=4" title="Edit section: Models"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>Intel offered several suffixes and variants (see table). Variants include: </p> <ul><li><i><a href="/wiki/RapidCAD" title="RapidCAD">Intel RapidCAD</a></i>: a specially packaged Intel 486DX and a dummy <a href="/wiki/Floating-point_unit" title="Floating-point unit">floating-point unit</a> (FPU) designed as pin-compatible replacements for an <a href="/wiki/I386" title="I386">i386</a> processor and <a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387</a> FPU.</li> <li><i>i486SL-NM</i>: i486SL based on i486SX.</li> <li><i><a href="/wiki/Intel_80487SX" class="mw-redirect" title="Intel 80487SX">i487SX (P23N)</a></i>: i486DX with one extra pin sold as an FPU upgrade to <a href="/wiki/I486SX" title="I486SX">i486SX</a> systems; When the i487SX was installed, it ensured that an i486SX was present on the <a href="/wiki/Motherboard" title="Motherboard">motherboard</a> but disabled it, taking over all of its functions.</li> <li><i><a href="/wiki/Intel_80486_OverDrive" class="mw-redirect" title="Intel 80486 OverDrive">i486 OverDrive (P23T/P24T)</a></i>: i486SX, i486SX2, i486DX2 or i486DX4. Marked as upgrade processors, some models had different pinouts or voltage-handling abilities from "standard" chips of the same speed. Fitted to a coprocessor or "OverDrive" socket on the motherboard, they worked the same as the i487SX.</li></ul> <p>The maximal internal clock frequency (on Intel's versions) ranged from 16 to 100 MHz. The 16 MHz i486SX model was used by <a href="/wiki/Dell_Computers" class="mw-redirect" title="Dell Computers">Dell Computers</a>. </p><p>One of the few i486 models specified for a 50 MHz bus (486DX-50) initially had overheating problems and was moved to the 0.8-<a href="/wiki/Micrometre" title="Micrometre">micrometer</a> fabrication process. However, problems continued when the 486DX-50 was installed in local-bus systems due to the high bus speed, making it unpopular with mainstream consumers. Local-bus video was considered a requirement at the time, though it remained popular with users of <a href="/wiki/Extended_Industry_Standard_Architecture" title="Extended Industry Standard Architecture">EISA</a> systems. The 486DX-50 was soon eclipsed by the clock-doubled <a href="/wiki/Intel_80486DX2" class="mw-redirect" title="Intel 80486DX2">i486DX2</a>, which although running the internal CPU logic at twice the external bus speed (50 MHz), was nevertheless slower because the external bus ran at only 25 MHz. The i486DX2 at 66 MHz (with 33 MHz external bus) was faster than the 486DX-50, overall. </p><p>More powerful i486 iterations such as the OverDrive and <a href="/wiki/DX4" class="mw-redirect" title="DX4">DX4</a> were less popular (the latter available as an OEM part only), as they came out after Intel had released the <a href="/wiki/Pentium_(original)" title="Pentium (original)">next-generation Pentium</a> processor family. Certain steppings of the DX4 also officially supported 50 MHz bus operation, but it was a seldom-used feature. </p> <dl><dd><table class="wikitable"> <tbody><tr> <th></th> <th>Model</th> <th>CPU/bus<br />clock speed</th> <th><a href="/wiki/VCore" class="mw-redirect" title="VCore">Voltage</a></th> <th><a href="/wiki/L1_cache" class="mw-redirect" title="L1 cache">L1 cache</a><sup id="cite_ref-22" class="reference"><a href="#cite_note-22"><span class="cite-bracket">[</span>e<span class="cite-bracket">]</span></a></sup></th> <th>Introduced </th> <th width="520px">Notes </th></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:Intel_i486_DX_25MHz_SX328.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/Intel_i486_DX_25MHz_SX328.jpg/80px-Intel_i486_DX_25MHz_SX328.jpg" decoding="async" width="80" height="80" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/17/Intel_i486_DX_25MHz_SX328.jpg/120px-Intel_i486_DX_25MHz_SX328.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/17/Intel_i486_DX_25MHz_SX328.jpg/160px-Intel_i486_DX_25MHz_SX328.jpg 2x" data-file-width="1100" data-file-height="1100" /></a></span><span typeof="mw:File"><a href="/wiki/File:Intel_i486_DX-33.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_i486_DX-33.jpg/80px-Intel_i486_DX-33.jpg" decoding="async" width="80" height="74" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_i486_DX-33.jpg/120px-Intel_i486_DX-33.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3f/Intel_i486_DX-33.jpg/160px-Intel_i486_DX-33.jpg 2x" data-file-width="1024" data-file-height="953" /></a></span><span typeof="mw:File"><a href="/wiki/File:Intel_i486_dx_50mhz_2007_03_27.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/Intel_i486_dx_50mhz_2007_03_27.jpg/80px-Intel_i486_dx_50mhz_2007_03_27.jpg" decoding="async" width="80" height="53" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/b/bd/Intel_i486_dx_50mhz_2007_03_27.jpg/120px-Intel_i486_dx_50mhz_2007_03_27.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/b/bd/Intel_i486_dx_50mhz_2007_03_27.jpg/160px-Intel_i486_dx_50mhz_2007_03_27.jpg 2x" data-file-width="2232" data-file-height="1488" /></a></span></td> <td>i486DX (P4)</td> <td>20, 25 MHz<br />33 MHz<br />50 MHz</td> <td>5 V</td> <td>8 KB WT</td> <td>April 1989<br />May 1990<br />June 1991</td> <td>The original chip without clock multiplier </td></tr> <tr> <td><span class="anchor" id="486SL"></span><span typeof="mw:File"><a href="/wiki/File:KL_Intel_486SL.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/1/14/KL_Intel_486SL.jpg/80px-KL_Intel_486SL.jpg" decoding="async" width="80" height="83" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/1/14/KL_Intel_486SL.jpg/120px-KL_Intel_486SL.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/1/14/KL_Intel_486SL.jpg/160px-KL_Intel_486SL.jpg 2x" data-file-width="1089" data-file-height="1134" /></a></span></td> <td>i486SL</td> <td>20, 25, 33 MHz</td> <td>5 V or 3.3 V</td> <td>8 KB WT</td> <td>November 1992</td> <td>Low-power version of the i486DX, reduced VCore, SMM (<a href="/wiki/System_Management_Mode" title="System Management Mode">System Management Mode</a>), stop clock, and power-saving features — mainly for use in portable computers </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:Intel_i486_sx_33mhz_2007_03_27.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/5/50/Intel_i486_sx_33mhz_2007_03_27.jpg/80px-Intel_i486_sx_33mhz_2007_03_27.jpg" decoding="async" width="80" height="53" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/5/50/Intel_i486_sx_33mhz_2007_03_27.jpg/120px-Intel_i486_sx_33mhz_2007_03_27.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/5/50/Intel_i486_sx_33mhz_2007_03_27.jpg/160px-Intel_i486_sx_33mhz_2007_03_27.jpg 2x" data-file-width="2178" data-file-height="1452" /></a></span></td> <td>i486SX (P23)</td> <td>16, 20, 25 MHz<br />33 MHz</td> <td>5 V</td> <td>8 KB WT</td> <td>September 1991<br />September 1992</td> <td>An i486DX with the FPU part disabled; later versions had the FPU removed from the <a href="/wiki/Integrated_circuit" title="Integrated circuit">die</a> to reduce area and hence cost. </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:Intel_i486_dx2_66mhz_2007_03_27.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/76/Intel_i486_dx2_66mhz_2007_03_27.jpg/80px-Intel_i486_dx2_66mhz_2007_03_27.jpg" decoding="async" width="80" height="53" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/76/Intel_i486_dx2_66mhz_2007_03_27.jpg/120px-Intel_i486_dx2_66mhz_2007_03_27.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/76/Intel_i486_dx2_66mhz_2007_03_27.jpg/160px-Intel_i486_dx2_66mhz_2007_03_27.jpg 2x" data-file-width="2142" data-file-height="1428" /></a></span></td> <td>i486DX2 (P24)</td> <td>40/20, 50/25 MHz<br />66/33 MHz</td> <td>5 V</td> <td>8 KB WT</td> <td>March 1992<br />August 1992</td> <td>The internal processor clock runs at twice the <a href="/wiki/Clock_rate" title="Clock rate">clock rate</a> of the external bus clock </td></tr> <tr> <td></td> <td>i486DX-S (P4S)</td> <td>33 MHz; 50 MHz</td> <td>5 V or 3.3 V</td> <td>8 KB WT</td> <td>June 1993</td> <td>SL Enhanced 486DX </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:KL_Intel_i486DX2_PQFP.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2b/KL_Intel_i486DX2_PQFP.jpg/80px-KL_Intel_i486DX2_PQFP.jpg" decoding="async" width="80" height="80" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2b/KL_Intel_i486DX2_PQFP.jpg/120px-KL_Intel_i486DX2_PQFP.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2b/KL_Intel_i486DX2_PQFP.jpg/160px-KL_Intel_i486DX2_PQFP.jpg 2x" data-file-width="1020" data-file-height="1020" /></a></span></td> <td>i486DX2-S (P24S)</td> <td>40/20 MHz,<br />50/25 MHz,<br />(<i>66/33 MHz</i>)</td> <td>5 V or 3.3 V</td> <td>8 KB WT</td> <td>June 1993</td> <td>SL Enhanced 486DX2 </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:KL_Intel_i486SX_PQFP.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/35/KL_Intel_i486SX_PQFP.jpg/80px-KL_Intel_i486SX_PQFP.jpg" decoding="async" width="80" height="80" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/35/KL_Intel_i486SX_PQFP.jpg/120px-KL_Intel_i486SX_PQFP.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/35/KL_Intel_i486SX_PQFP.jpg/160px-KL_Intel_i486SX_PQFP.jpg 2x" data-file-width="1023" data-file-height="1017" /></a></span></td> <td>i486SX-S (P23S)</td> <td>25, 33 MHz</td> <td>5 V or 3.3 V</td> <td>8 KB WT</td> <td>June 1993</td> <td>SL Enhanced 486SX </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:KL_intel_i486SX2.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/78/KL_intel_i486SX2.jpg/80px-KL_intel_i486SX2.jpg" decoding="async" width="80" height="80" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/78/KL_intel_i486SX2.jpg/120px-KL_intel_i486SX2.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/78/KL_intel_i486SX2.jpg/160px-KL_intel_i486SX2.jpg 2x" data-file-width="1353" data-file-height="1350" /></a></span></td> <td>i486SX2</td> <td>50/25, 66/33 MHz</td> <td>5 V</td> <td>8 KB WT</td> <td>March 1994</td> <td>i486DX2 with the FPU disabled. Early version used the 800 nm process technology.<sup id="cite_ref-23" class="reference"><a href="#cite_note-23"><span class="cite-bracket">[</span>18<span class="cite-bracket">]</span></a></sup> </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/d/db/FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg/80px-FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg" decoding="async" width="80" height="80" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/d/db/FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg/120px-FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/d/db/FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg/160px-FC80486DX4-75_AK_SX883_USA_1995_01_WT.jpg 2x" data-file-width="512" data-file-height="512" /></a></span><span typeof="mw:File"><a href="/wiki/File:Intel_i486_DX4_100_MHz_SK051.jpeg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_i486_DX4_100_MHz_SK051.jpeg/80px-Intel_i486_DX4_100_MHz_SK051.jpeg" decoding="async" width="80" height="73" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_i486_DX4_100_MHz_SK051.jpeg/120px-Intel_i486_DX4_100_MHz_SK051.jpeg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/c/c4/Intel_i486_DX4_100_MHz_SK051.jpeg/160px-Intel_i486_DX4_100_MHz_SK051.jpeg 2x" data-file-width="1024" data-file-height="932" /></a></span></td> <td>IntelDX4 (P24C)</td> <td>75/25, 100/33 MHz</td> <td>3.3 V</td> <td>16 KB WT</td> <td>March 1994</td> <td>Designed to run at triple clock rate (not quadruple, as often believed; the DX3, which was meant to run at 2.5× the clock speed, was never released). DX4 models that featured write-back cache were identified by an "&EW" laser-etched into their top surface, while the write-through models were identified by "&E". </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:Intel_i486_DX2_66_CPU_SX955.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel_i486_DX2_66_CPU_SX955.jpg/80px-Intel_i486_DX2_66_CPU_SX955.jpg" decoding="async" width="80" height="82" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel_i486_DX2_66_CPU_SX955.jpg/120px-Intel_i486_DX2_66_CPU_SX955.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/3/3b/Intel_i486_DX2_66_CPU_SX955.jpg/160px-Intel_i486_DX2_66_CPU_SX955.jpg 2x" data-file-width="557" data-file-height="574" /></a></span></td> <td>i486DX2WB (P24D)</td> <td>50/25 MHz,<br />66/33 MHz</td> <td>5 V</td> <td>8 KB WB</td> <td>October 1994</td> <td>Enabled write-back cache. </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:Intel_i486_dx4_100mhz_2007_03_27.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/77/Intel_i486_dx4_100mhz_2007_03_27.jpg/80px-Intel_i486_dx4_100mhz_2007_03_27.jpg" decoding="async" width="80" height="53" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/77/Intel_i486_dx4_100mhz_2007_03_27.jpg/120px-Intel_i486_dx4_100mhz_2007_03_27.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/77/Intel_i486_dx4_100mhz_2007_03_27.jpg/160px-Intel_i486_dx4_100mhz_2007_03_27.jpg 2x" data-file-width="2142" data-file-height="1428" /></a></span></td> <td>IntelDX4WB</td> <td>100/33 MHz</td> <td>3.3 V</td> <td>16 KB WB</td> <td>October 1994</td> <td> </td></tr> <tr> <td></td> <td>i486DX2 (P24LM)</td> <td>90/30 MHz,<br />100/33 MHz</td> <td>2.5–2.9 V</td> <td>8 KB WT</td> <td>1994</td> <td> </td></tr> <tr> <td><span typeof="mw:File"><a href="/wiki/File:KL_Intel_i486GX.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/KL_Intel_i486GX.jpg/80px-KL_Intel_i486GX.jpg" decoding="async" width="80" height="78" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/f/f6/KL_Intel_i486GX.jpg/120px-KL_Intel_i486GX.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/f/f6/KL_Intel_i486GX.jpg/160px-KL_Intel_i486GX.jpg 2x" data-file-width="912" data-file-height="894" /></a></span></td> <td>i486GX</td> <td>up to 33 MHz</td> <td>3.3 V</td> <td>8 KB WT</td> <td></td> <td>Embedded ultra-low-power CPU with all features of the i486SX and 16-bit external data bus. This CPU is for embedded battery-operated and hand-held applications. </td></tr></tbody></table></dd></dl> <div class="mw-heading mw-heading2"><h2 id="Other_makers_of_486-like_CPUs">Other makers of 486-like CPUs</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=5" title="Edit section: Other makers of 486-like CPUs"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure typeof="mw:File/Thumb"><a href="/wiki/File:KL_STMicroelectronics_ST486DX2-40.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/7/71/KL_STMicroelectronics_ST486DX2-40.jpg/150px-KL_STMicroelectronics_ST486DX2-40.jpg" decoding="async" width="150" height="151" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/7/71/KL_STMicroelectronics_ST486DX2-40.jpg/225px-KL_STMicroelectronics_ST486DX2-40.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/7/71/KL_STMicroelectronics_ST486DX2-40.jpg/300px-KL_STMicroelectronics_ST486DX2-40.jpg 2x" data-file-width="1374" data-file-height="1380" /></a><figcaption>STMicroelectronics' ST ST486DX2-40</figcaption></figure> <figure typeof="mw:File/Thumb"><a href="/wiki/File:KL_UMC_U5SX.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/2/2e/KL_UMC_U5SX.jpg/150px-KL_UMC_U5SX.jpg" decoding="async" width="150" height="159" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/2/2e/KL_UMC_U5SX.jpg/225px-KL_UMC_U5SX.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/2/2e/KL_UMC_U5SX.jpg/300px-KL_UMC_U5SX.jpg 2x" data-file-width="1254" data-file-height="1332" /></a><figcaption><a href="/wiki/UMC_Green_CPU" title="UMC Green CPU">UMC Green CPU</a> U5SX</figcaption></figure> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:KL_Cyrix_486DRx2.jpg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/KL_Cyrix_486DRx2.jpg/150px-KL_Cyrix_486DRx2.jpg" decoding="async" width="150" height="162" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/9/9c/KL_Cyrix_486DRx2.jpg/225px-KL_Cyrix_486DRx2.jpg 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/9/9c/KL_Cyrix_486DRx2.jpg/300px-KL_Cyrix_486DRx2.jpg 2x" data-file-width="1020" data-file-height="1101" /></a><figcaption>Cyrix Cx486DRx²</figcaption></figure> <p>Processors compatible with the i486 were produced by companies such as <a href="/wiki/IBM" title="IBM">IBM</a>, <a href="/wiki/Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, <a href="/wiki/AMD" title="AMD">AMD</a>, <a href="/wiki/Cyrix" title="Cyrix">Cyrix</a>, <a href="/wiki/United_Microelectronics_Corporation" title="United Microelectronics Corporation">UMC</a>, and <a href="/wiki/STMicroelectronics" title="STMicroelectronics">STMicroelectronics</a> (formerly SGS-Thomson). Some were clones (identical at the microarchitectural level), others were <a href="/wiki/Clean_room_design" class="mw-redirect" title="Clean room design">clean room implementations</a> of the Intel instruction set. (IBM's multiple-source requirement was one of the reasons behind its x86 manufacturing since the 80286.) The i486 was, however, covered by many Intel patents, including from the prior i386. Intel and IBM had broad cross-licenses of these patents, and AMD was granted rights to the relevant patents in the 1995 settlement of a lawsuit between the companies.<sup id="cite_ref-24" class="reference"><a href="#cite_note-24"><span class="cite-bracket">[</span>19<span class="cite-bracket">]</span></a></sup> </p><p>AMD produced several clones using a 40 MHz bus (486DX-40, 486DX/2-80, and 486DX/4-120) which had no Intel equivalent, as well as a part specified for 90 MHz, using a 30 MHz external clock, that was sold only to OEMs. The fastest running i486-compatible CPU, the <a href="/wiki/Am5x86" title="Am5x86">Am5x86</a>, ran at 133 MHz and was released by AMD in 1995. 150 MHz and 160 MHz parts were planned but never officially released. </p><p>Cyrix made a variety of i486-compatible processors, positioned at the cost-sensitive desktop and low-power (laptop) markets. Unlike AMD's 486 clones, the Cyrix processors were the result of clean-room reverse engineering. Cyrix's early offerings included the 486DLC and 486SLC, two hybrid chips that plugged into 386DX or SX sockets respectively, and offered 1 KB of cache (versus 8 KB for the then-current Intel/AMD parts). Cyrix also made "real" 486 processors, which plugged into the i486's socket and offered 2 or 8 KB of cache. Clock-for-clock, the Cyrix-made chips were generally slower than their Intel/AMD equivalents, though later products with 8 KB caches were more competitive, albeit late to market. </p><p>The <a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a>, while not i486 compatible, was often positioned as its equivalent in features and performance. Clock-for-clock basis the <a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a> could significantly outperform the Intel chip.<sup id="cite_ref-25" class="reference"><a href="#cite_note-25"><span class="cite-bracket">[</span>20<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-26" class="reference"><a href="#cite_note-26"><span class="cite-bracket">[</span>21<span class="cite-bracket">]</span></a></sup> However, the i486 had the ability to be clocked significantly faster without overheating. <a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a> performance lagged behind the later production i486 systems.<sup class="noprint Inline-Template Template-Fact" style="white-space:nowrap;">[<i><a href="/wiki/Wikipedia:Citation_needed" title="Wikipedia:Citation needed"><span title="This claim needs references to reliable sources. (July 2015)">citation needed</span></a></i>]</sup> </p> <div class="mw-heading mw-heading2"><h2 id="Motherboards_and_buses">Motherboards and buses</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=6" title="Edit section: Motherboards and buses"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1251242444">.mw-parser-output .ambox{border:1px solid #a2a9b1;border-left:10px solid #36c;background-color:#fbfbfb;box-sizing:border-box}.mw-parser-output .ambox+link+.ambox,.mw-parser-output .ambox+link+style+.ambox,.mw-parser-output .ambox+link+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+style+.ambox,.mw-parser-output .ambox+.mw-empty-elt+link+link+.ambox{margin-top:-1px}html body.mediawiki .mw-parser-output .ambox.mbox-small-left{margin:4px 1em 4px 0;overflow:hidden;width:238px;border-collapse:collapse;font-size:88%;line-height:1.25em}.mw-parser-output .ambox-speedy{border-left:10px solid #b32424;background-color:#fee7e6}.mw-parser-output .ambox-delete{border-left:10px solid #b32424}.mw-parser-output .ambox-content{border-left:10px solid #f28500}.mw-parser-output .ambox-style{border-left:10px solid #fc3}.mw-parser-output .ambox-move{border-left:10px solid #9932cc}.mw-parser-output .ambox-protection{border-left:10px solid #a2a9b1}.mw-parser-output .ambox .mbox-text{border:none;padding:0.25em 0.5em;width:100%}.mw-parser-output .ambox .mbox-image{border:none;padding:2px 0 2px 0.5em;text-align:center}.mw-parser-output .ambox .mbox-imageright{border:none;padding:2px 0.5em 2px 0;text-align:center}.mw-parser-output .ambox .mbox-empty-cell{border:none;padding:0;width:1px}.mw-parser-output .ambox .mbox-image-div{width:52px}@media(min-width:720px){.mw-parser-output .ambox{margin:0 10%}}@media print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-Unreferenced_section plainlinks metadata ambox ambox-content ambox-Unreferenced" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This section <b>does not <a href="/wiki/Wikipedia:Citing_sources" title="Wikipedia:Citing sources">cite</a> any <a href="/wiki/Wikipedia:Verifiability" title="Wikipedia:Verifiability">sources</a></b>.<span class="hide-when-compact"> Please help <a href="/wiki/Special:EditPage/I486" title="Special:EditPage/I486">improve this section</a> by <a href="/wiki/Help:Referencing_for_beginners" title="Help:Referencing for beginners">adding citations to reliable sources</a>. Unsourced material may be challenged and <a href="/wiki/Wikipedia:Verifiability#Burden_of_evidence" title="Wikipedia:Verifiability">removed</a>.</span> <span class="date-container"><i>(<span class="date">March 2021</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <figure typeof="mw:File/Thumb"><a href="/wiki/File:Byte_magazine_September_1989_cover.png" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/en/thumb/3/3b/Byte_magazine_September_1989_cover.png/200px-Byte_magazine_September_1989_cover.png" decoding="async" width="200" height="285" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/3/3b/Byte_magazine_September_1989_cover.png 1.5x" data-file-width="264" data-file-height="376" /></a><figcaption>The <a href="/wiki/Apricot_Computers" title="Apricot Computers">first 486 system from the UK</a> on the cover of BYTE, September 1989</figcaption></figure> <p>Early i486-based computers were equipped with several <a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">ISA</a> slots (using an <a href="/wiki/Emulated" class="mw-redirect" title="Emulated">emulated</a> <a href="/wiki/Industry_Standard_Architecture" title="Industry Standard Architecture">PC/AT-bus</a>) and sometimes one or two <a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>-only slots (compatible with the PC/XT-bus).<sup id="cite_ref-27" class="reference"><a href="#cite_note-27"><span class="cite-bracket">[</span>f<span class="cite-bracket">]</span></a></sup> Many <a href="/wiki/Motherboard" title="Motherboard">motherboards</a> enabled overclocking of these from the default 6 or 8 MHz to perhaps 16.7 or 20 MHz (half the i486 bus clock) in several steps, often from within the <a href="/wiki/BIOS" title="BIOS">BIOS</a> setup. Especially older peripheral cards normally worked well at such speeds as they often used standard MSI chips instead of slower (at the time) custom <a href="/wiki/VLSI" class="mw-redirect" title="VLSI">VLSI</a> designs. This could give significant performance gains (such as for old video cards moved from a 386 or 286 computer, for example). However, operation beyond 8 or 10 MHz could sometimes lead to stability problems, at least in systems equipped with <a href="/wiki/SCSI" title="SCSI">SCSI</a> or <a href="/wiki/Sound_cards" class="mw-redirect" title="Sound cards">sound cards</a>. </p><p>Some motherboards came equipped with a <a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> EISA bus that was backward compatible with the ISA-standard. EISA offered attractive features such as increased bandwidth, extended addressing, IRQ sharing, and card configuration through software (rather than through jumpers, DIP switches, etc.) However, EISA cards were expensive and therefore mostly employed in servers and workstations. Consumer desktops often used the simpler, faster <a href="/wiki/VESA_Local_Bus" title="VESA Local Bus">VESA Local Bus</a> (VLB). Unfortunately prone to electrical and timing-based instability; typical consumer desktops had ISA slots combined with a single VLB slot for a video card. VLB was gradually replaced by <a href="/wiki/Peripheral_Component_Interconnect" title="Peripheral Component Interconnect">PCI</a> during the final years of the i486 period. Few <a href="/wiki/Pentium_class" class="mw-redirect" title="Pentium class">Pentium class</a> motherboards had VLB support as VLB was based directly on the i486 bus; much different from the P5 Pentium-bus. ISA persisted through the P5 Pentium generation and was not completely displaced by PCI until the Pentium III era, although ISA persisted well into the Pentium 4 era, especially among industrial PCs. </p><p>Late i486 boards were normally equipped with both PCI and ISA slots, and sometimes a single VLB slot. In this configuration, VLB or PCI throughput suffered depending on how buses were bridged. Initially, the VLB slot in these systems was usually fully compatible only with video cards (fitting as "VESA" stands for <i><a href="/wiki/VESA" class="mw-redirect" title="VESA">Video Electronics Standards Association</a></i>); VLB-IDE, multi I/O, or SCSI cards could have problems on motherboards with PCI slots. The VL-Bus operated at the same clock speed as the i486-bus (basically a local bus) while the PCI bus also usually depended on the i486 clock but sometimes had a divider setting available via the BIOS. This could be set to 1/1 or 1/2, sometimes even 2/3 (for 50 MHz CPU clocks). Some motherboards limited the PCI clock to the specified maximum of 33 MHz and certain network cards depended on this frequency for correct bit-rates. The ISA clock was typically generated by a divider of the CPU/VLB/PCI clock. </p><p>One of the earliest complete systems to use the i486 chip was the Apricot VX FT, produced by British hardware manufacturer <a href="/wiki/Apricot_Computers" title="Apricot Computers">Apricot Computers</a>.<sup id="cite_ref-byte198909_apricot_28-0" class="reference"><a href="#cite_note-byte198909_apricot-28"><span class="cite-bracket">[</span>22<span class="cite-bracket">]</span></a></sup> Even overseas in the United States it was popularized as "The World's First 486". </p><p>Later i486 boards supported <a href="/wiki/Plug-And-Play" class="mw-redirect" title="Plug-And-Play">Plug-And-Play</a>, a specification designed by <a href="/wiki/Microsoft" title="Microsoft">Microsoft</a> that began as a part of <a href="/wiki/Windows_95" title="Windows 95">Windows 95</a> to make component installation easier for consumers. </p> <div class="mw-heading mw-heading2"><h2 id="Obsolescence">Obsolescence</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=7" title="Edit section: Obsolescence"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The <a href="/wiki/AMD_Am5x86" class="mw-redirect" title="AMD Am5x86">AMD Am5x86</a> and <a href="/wiki/Cyrix_Cx5x86" class="mw-redirect" title="Cyrix Cx5x86">Cyrix Cx5x86</a> were the last i486 processors often used in late-generation i486 motherboards. They came with PCI slots and 72-pin SIMMs that were designed to run <a href="/wiki/Windows_95" title="Windows 95">Windows 95</a>, and also used for 80486 motherboards upgrades. While the <a href="/wiki/Cyrix_Cx5x86" class="mw-redirect" title="Cyrix Cx5x86">Cyrix Cx5x86</a> faded when the <a href="/wiki/Cyrix_6x86" title="Cyrix 6x86">Cyrix 6x86</a> took over, the <a href="/wiki/AMD_Am5x86" class="mw-redirect" title="AMD Am5x86">AMD Am5x86</a> remained important given <a href="/wiki/AMD_K5" title="AMD K5">AMD K5</a> delays. </p><p>Computers based on the i486 remained popular through the late 1990s, serving as low-end processors for entry-level PCs. Production for traditional desktop and laptop systems ceased in 1998, when Intel introduced the <a href="/wiki/Celeron" title="Celeron">Celeron</a> brand, though it continued to be produced for <a href="/wiki/Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a> through the late 2000s. </p><p>In the general-purpose desktop computer role, i486-based machines remained in use into the early 2000s, especially as Windows 95 through <a href="/wiki/Windows_98" title="Windows 98">98</a> and <a href="/wiki/Windows_NT_4.0" title="Windows NT 4.0">Windows NT 4.0</a> were the last Microsoft operating systems to officially support i486-based systems.<sup id="cite_ref-29" class="reference"><a href="#cite_note-29"><span class="cite-bracket">[</span>23<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-30" class="reference"><a href="#cite_note-30"><span class="cite-bracket">[</span>24<span class="cite-bracket">]</span></a></sup> <a href="/wiki/Windows_2000" title="Windows 2000">Windows 2000</a> could run on a i486-based machine, although with a less than optimal performance, due to the minimum hardware requirement of a Pentium processor.<sup id="cite_ref-31" class="reference"><a href="#cite_note-31"><span class="cite-bracket">[</span>25<span class="cite-bracket">]</span></a></sup> However, as they were overtaken by newer operating systems, i486 systems fell out of use except for <a href="/wiki/Backward_compatibility" title="Backward compatibility">backward compatibility</a> with older programs (most notably games), especially given problems running on newer operating systems. However, <a href="/wiki/DOSBox" title="DOSBox">DOSBox</a> was available for later operating systems and provides emulation of the i486 instruction set, as well as full compatibility with most DOS-based programs.<sup id="cite_ref-32" class="reference"><a href="#cite_note-32"><span class="cite-bracket">[</span>26<span class="cite-bracket">]</span></a></sup> </p><p>The i486 was eventually overtaken by the Pentium for <a href="/wiki/Personal_computer" title="Personal computer">personal computer</a> applications, although Intel continued production for use in <a href="/wiki/Embedded_systems" class="mw-redirect" title="Embedded systems">embedded systems</a>. In May 2006, Intel announced that production of the i486 would stop at the end of September 2007.<sup id="cite_ref-i486LastShipment2007_1-3" class="reference"><a href="#cite_note-i486LastShipment2007-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-33" class="reference"><a href="#cite_note-33"><span class="cite-bracket">[</span>27<span class="cite-bracket">]</span></a></sup> </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=8" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/List_of_Intel_microprocessors" class="mw-redirect" title="List of Intel microprocessors">List of Intel microprocessors</a></li> <li><a href="/wiki/Motorola_68040" title="Motorola 68040">Motorola 68040</a>, although not compatible, was often positioned as the <a href="/wiki/Motorola" title="Motorola">Motorola</a> equivalent to the Intel 486 in terms of performance and features.</li> <li>VL86C020, <a href="/wiki/ARM3" class="mw-redirect" title="ARM3">ARM3</a> core of similar time frame and comparable MIPS performance on integer code (25 MHz for both), with 310,000 transistors (in a 1.5 μm process) instead of 1 million</li></ul> <div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=9" title="Edit section: Notes"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist reflist-lower-alpha"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text">AMD versions up to <a href="/wiki/Am486" title="Am486">120</a> and <a href="/wiki/Am5x86" title="Am5x86">160</a> MHz.</span> </li> <li id="cite_note-fn1-5"><span class="mw-cite-backlink">^ <a href="#cite_ref-fn1_5-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-fn1_5-1"><sup><i><b>b</b></i></sup></a></span> <span class="reference-text">The 386, 286, and even the 8086 all had overlapping fetch, decode, execution (calculation), and write back; however, <b>tightly pipelined</b> usually means that all stages perform their respective duties within the same length time slot. In contrast <b>loosely pipelined</b> implies that some kind of buffering is used to decouple the units and allow them to work more independently. Both the original 8086 and the x86-chips of today are "loosely pipelined" in this sense, while the i486 and the original Pentium worked in a "tightly pipelined" manner for typical instructions. This included most "<a href="/wiki/Complex_instruction_set_computing" class="mw-redirect" title="Complex instruction set computing">CISC</a>" type instructions as well as the simple load/store-free "<a href="/wiki/RISC" class="mw-redirect" title="RISC">RISC</a>-like" ones, although the most complex also used some dedicated <a href="/wiki/Microcode" title="Microcode">microcode</a> control.</span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text">Simple instructions spend only a single clock cycle at each pipeline stage.<sup id="cite_ref-fn1_5-0" class="reference"><a href="#cite_note-fn1-5"><span class="cite-bracket">[</span>b<span class="cite-bracket">]</span></a></sup></span> </li> <li id="cite_note-21"><span class="mw-cite-backlink"><b><a href="#cite_ref-21">^</a></b></span> <span class="reference-text">The pre-DX2 i486 parts did not use a clock multiplier and are therefore comparable to a twice-higher clocked 386/286.</span> </li> <li id="cite_note-22"><span class="mw-cite-backlink"><b><a href="#cite_ref-22">^</a></b></span> <span class="reference-text"><i>WT</i> = write-through cache strategy, <i>WB</i> = write-back cache strategy.</span> </li> <li id="cite_note-27"><span class="mw-cite-backlink"><b><a href="#cite_ref-27">^</a></b></span> <span class="reference-text">In general, 8-bit ISA slots in these systems were implemented just by leaving off the shorter "C"/"D" connector of the slot, though the copper traces for a 16-bit slot were still there on the motherboard; the computer could tell no difference between an 8-bit ISA adapter in such a slot and the same adapter in a 16-bit slot, and there were still enough 8-bit adapters in circulation that vendors figured they could save money on a few connectors this way. Also, leaving off the 16-bit extension to the ISA connector allowed use of some early 8-bit ISA cards that otherwise could not be used due to the PCB "skirt" hanging down into that 16-bit extension space. IBM was the first to do this in the IBM AT.</span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="Further_reading">Further reading</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=10" title="Edit section: Further reading"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFGamer2023" class="citation web cs1">Gamer, Brassic (January 1, 2023). <a rel="nofollow" class="external text" href="https://brassicgamer.blogspot.com/2023/01/the-almost-definitive-486dx50-article.html">"The Brassic Gamer: The (Almost) Definitive 486DX/50 Article"</a>. <i>The Brassic Gamer</i><span class="reference-accessdate">. Retrieved <span class="nowrap">January 3,</span> 2023</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=The+Brassic+Gamer&rft.atitle=The+Brassic+Gamer%3A+The+%28Almost%29+Definitive+486DX%2F50+Article&rft.date=2023-01-01&rft.aulast=Gamer&rft.aufirst=Brassic&rft_id=https%3A%2F%2Fbrassicgamer.blogspot.com%2F2023%2F01%2Fthe-almost-definitive-486dx50-article.html&rfr_id=info%3Asid%2Fen.wikipedia.org%3AI486" class="Z3988"></span></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=11" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1239543626"><div class="reflist"> <div class="mw-references-wrap mw-references-columns"><ol class="references"> <li id="cite_note-i486LastShipment2007-1"><span class="mw-cite-backlink">^ <a href="#cite_ref-i486LastShipment2007_1-0"><sup><i><b>a</b></i></sup></a> <a href="#cite_ref-i486LastShipment2007_1-1"><sup><i><b>b</b></i></sup></a> <a href="#cite_ref-i486LastShipment2007_1-2"><sup><i><b>c</b></i></sup></a> <a href="#cite_ref-i486LastShipment2007_1-3"><sup><i><b>d</b></i></sup></a></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20061009060120/http://developer.intel.com/design/pcn/Processors/D0106013.pdf">"Product Change Notification"</a> <span class="cs1-format">(PDF)</span>. Intel. May 2, 2006. p. 2. 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(Intel Corp.) (product announcement) EDN, May 11, 1989, Pryce, Dave.</span> </li> <li id="cite_note-11"><span class="mw-cite-backlink"><b><a href="#cite_ref-11">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFLewis1989" class="citation news cs1">Lewis, Peter H. (October 22, 1989). <a rel="nofollow" class="external text" href="https://www.nytimes.com/1989/10/22/business/the-executive-computer-the-race-to-market-a-486-machine.html?pagewanted=1">"The Executive Computer; The Race to Market a 486 Machine"</a>. <i>The New York Times</i><span class="reference-accessdate">. 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WinHistory.de.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Windows+NT+4.0+Workstation&rft.pub=WinHistory.de&rft_id=http%3A%2F%2Fwww.winhistory.de%2Fmore%2Fnt4.htm&rfr_id=info%3Asid%2Fen.wikipedia.org%3AI486" class="Z3988"></span></span> </li> <li id="cite_note-31"><span class="mw-cite-backlink"><b><a href="#cite_ref-31">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.youtube.com/watch?v=d33rIWdgc_A&t=380s&ab_channel=HARDWARECOP">"World Record*: Windows 2000 running on Intel i486 SX 25 MHz"</a>. <i><a href="/wiki/YouTube" title="YouTube">YouTube</a></i>. July 29, 2013.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=unknown&rft.jtitle=YouTube&rft.atitle=World+Record%2A%3A+Windows+2000+running+on+Intel+i486+SX+25+MHz&rft.date=2013-07-29&rft_id=https%3A%2F%2Fwww.youtube.com%2Fwatch%3Fv%3Dd33rIWdgc_A%26t%3D380s%26ab_channel%3DHARDWARECOP&rfr_id=info%3Asid%2Fen.wikipedia.org%3AI486" class="Z3988"></span></span> </li> <li id="cite_note-32"><span class="mw-cite-backlink"><b><a href="#cite_ref-32">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.dosbox.com/wiki/System_Requirements">"System Requirements"</a>. DOSBox.com.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=System+Requirements&rft.pub=DOSBox.com&rft_id=http%3A%2F%2Fwww.dosbox.com%2Fwiki%2FSystem_Requirements&rfr_id=info%3Asid%2Fen.wikipedia.org%3AI486" class="Z3988"></span></span> </li> <li id="cite_note-33"><span class="mw-cite-backlink"><b><a href="#cite_ref-33">^</a></b></span> <span class="reference-text"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1238218222"><cite id="CITEREFTony_Smith2006" class="citation web cs1">Tony Smith (May 18, 2006). <a rel="nofollow" class="external text" href="https://web.archive.org/web/20110813073335/http://www.reghardware.com/2006/05/18/intel_cans_386_486_960_cpus/">"Intel cashes in ancient chips. i386, i486, i960 finally for the chop"</a>. <a href="/wiki/The_Register" title="The Register">The Register</a> Hardware. Archived from <a rel="nofollow" class="external text" href="http://www.reghardware.co.uk/2006/05/18/intel_cans_386_486_960_cpus/">the original</a> on August 13, 2011<span class="reference-accessdate">. Retrieved <span class="nowrap">May 20,</span> 2012</span>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=unknown&rft.btitle=Intel+cashes+in+ancient+chips.+i386%2C+i486%2C+i960+finally+for+the+chop&rft.pub=The+Register+Hardware&rft.date=2006-05-18&rft.au=Tony+Smith&rft_id=http%3A%2F%2Fwww.reghardware.co.uk%2F2006%2F05%2F18%2Fintel_cans_386_486_960_cpus%2F&rfr_id=info%3Asid%2Fen.wikipedia.org%3AI486" class="Z3988"></span></span> </li> </ol></div></div> <div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=I486&action=edit&section=12" title="Edit section: External links"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/486/datashts">Intel486 datasheets</a> <ul><li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/486/datashts/241199-002.pdf">Low power SX and DX with variable freq. Dec 1992</a></li> <li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/486/datashts/27273102.PDF">EMBEDDED ULTRA-LOW POWER Intel 486 SX</a></li> <li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/486/datashts/27277101.pdf">Embedded Write-Back Enhanced Intel DX4. Oct 1995</a></li></ul></li> <li><a rel="nofollow" class="external text" href="http://www.cpu-collection.de/?l0=co&l1=Intel&l2=i486%20DX">Intel i486 DX images and descriptions at cpu-collection.de</a></li> <li><a rel="nofollow" class="external text" href="http://download.intel.com/newsroom/kits/40thanniversary/gallery/images/80486_die.jpg">Die photo of Intel 386DX</a></li></ul> <div class="navbox-styles"><style data-mw-deduplicate="TemplateStyles:r1129693374">.mw-parser-output .hlist dl,.mw-parser-output .hlist ol,.mw-parser-output .hlist ul{margin:0;padding:0}.mw-parser-output .hlist dd,.mw-parser-output .hlist dt,.mw-parser-output .hlist li{margin:0;display:inline}.mw-parser-output .hlist.inline,.mw-parser-output .hlist.inline dl,.mw-parser-output .hlist.inline ol,.mw-parser-output .hlist.inline ul,.mw-parser-output .hlist dl dl,.mw-parser-output .hlist dl ol,.mw-parser-output .hlist dl ul,.mw-parser-output .hlist ol dl,.mw-parser-output .hlist ol ol,.mw-parser-output .hlist ol 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.navbar a>abbr{text-decoration:inherit}.mw-parser-output .navbar-mini abbr{font-variant:small-caps;border-bottom:none;text-decoration:none;cursor:inherit}.mw-parser-output .navbar-ct-full{font-size:114%;margin:0 7em}.mw-parser-output .navbar-ct-mini{font-size:114%;margin:0 4em}html.skin-theme-clientpref-night .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Intel_processors" title="Template:Intel processors"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Intel_processors" title="Template talk:Intel processors"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Intel_processors" title="Special:EditPage/Template:Intel processors"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Intel_processors" style="font-size:114%;margin:0 4em"><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/List_of_Intel_processors" title="List of Intel processors">Processors</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors" title="List of Intel Atom processors">Atom</a></li> <li><a href="/wiki/List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li> <li><a href="/wiki/List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a> <ul><li><a href="/wiki/List_of_Intel_Pentium_Pro_processors" title="List of Intel Pentium Pro processors">Pro</a></li> <li><a href="/wiki/List_of_Intel_Pentium_II_processors" title="List of Intel Pentium II processors">II</a></li> <li><a href="/wiki/List_of_Intel_Pentium_III_processors" title="List of Intel Pentium III processors">III</a></li> <li><a href="/wiki/List_of_Intel_Pentium_4_processors" title="List of Intel Pentium 4 processors">4</a></li> <li><a href="/wiki/List_of_Intel_Pentium_D_processors" title="List of Intel Pentium D processors">D</a></li> <li><a href="/wiki/List_of_Intel_Pentium_M_processors" title="List of Intel Pentium M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Core_processors" title="List of Intel Core processors">Core</a> <ul><li><a href="/wiki/List_of_Intel_Core_2_processors" class="mw-redirect" title="List of Intel Core 2 processors">2</a></li> <li><a href="/wiki/List_of_Intel_Core_i3_processors" class="mw-redirect" title="List of Intel Core i3 processors">i3</a></li> <li><a href="/wiki/List_of_Intel_Core_i5_processors" class="mw-redirect" title="List of Intel Core i5 processors">i5</a></li> <li><a href="/wiki/List_of_Intel_Core_i7_processors" class="mw-redirect" title="List of Intel Core i7 processors">i7</a></li> <li><a href="/wiki/List_of_Intel_Core_i9_processors" class="mw-redirect" title="List of Intel Core i9 processors">i9</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/List_of_Intel_Xeon_processors" title="List of Intel Xeon processors">Xeon</a></li> <li><a href="/wiki/Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li> <li><a href="/wiki/List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li> <li><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li> <li><a href="/wiki/List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/P5_(microarchitecture)" class="mw-redirect" title="P5 (microarchitecture)">P5</a></li> <li><a href="/wiki/P6_(microarchitecture)" title="P6 (microarchitecture)">P6</a> <ul><li><a href="/wiki/Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li> <li><a href="/wiki/Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li> <li><a href="/wiki/NetBurst" title="NetBurst">NetBurst</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Core_(microarchitecture)" title="Intel Core (microarchitecture)">Core</a> <ul><li><a href="/wiki/Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li> <li><a href="/wiki/Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a> <ul><li><a href="/wiki/Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li> <li><a href="/wiki/Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a> <ul><li><a href="/wiki/Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li> <li><a href="/wiki/Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a> <ul><li><a href="/wiki/Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li> <li><a href="/wiki/Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a> <ul><li><a href="/wiki/Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li> <li><a href="/wiki/Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a> <ul><li><a href="/wiki/Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li> <li><a href="/wiki/Willow_Cove" title="Willow Cove">Willow Cove</a></li> <li><a href="/wiki/Golden_Cove" title="Golden Cove">Golden Cove</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86" title="X86">x86</a> <a href="/wiki/Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a> <ul><li><a href="/wiki/Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li> <li><a href="/wiki/Silvermont" title="Silvermont">Silvermont</a></li></ul></li> <li><a href="/wiki/Goldmont" title="Goldmont">Goldmont</a> <ul><li><a href="/wiki/Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li> <li><a href="/wiki/Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a> <ul><li><a href="/wiki/Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)" scope="row" class="navbox-group" style="width:8.5em"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/Intel_Core#12th_generation" title="Intel Core">12th gen</a></li> <li><a href="/wiki/Intel_Core#13th_generation" title="Intel Core">13th gen</a></li> <li><a href="/wiki/Intel_Core#14th_generation" title="Intel Core">14th gen</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a></li></ul> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="/wiki/4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_4004" title="Intel 4004">4004</a> (1971)</li> <li><a href="/wiki/Intel_4040" title="Intel 4040">4040</a> (1974)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="/wiki/8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8008" title="Intel 8008">8008</a> (1972)</li> <li><a href="/wiki/Intel_8080" title="Intel 8080">8080</a> (1974)</li> <li><a href="/wiki/Intel_8085" title="Intel 8085">8085</a> (1977)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="/wiki/X86" title="X86">x86</a> (<a href="/wiki/16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_8086" title="Intel 8086">8086</a> (1978)</li> <li><a href="/wiki/Intel_8088" title="Intel 8088">8088</a> (1979)</li> <li><a href="/wiki/Intel_80186" title="Intel 80186">80186</a> (1982)</li> <li><a href="/wiki/Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (1982)</li> <li><a href="/wiki/Intel_80286" title="Intel 80286">80286</a> (1982)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X87" title="X87">x87</a> (external <a href="/wiki/Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt>8/16-bit databus</dt> <dd><a href="/wiki/Intel_8087" title="Intel 8087">8087</a> (1980)</dd> <dt>16-bit databus</dt> <dd><a href="/wiki/Intel_80C187" class="mw-redirect" title="Intel 80C187">80C187</a></dd> <dd><a href="/wiki/Intel_80287" class="mw-redirect" title="Intel 80287">80287</a></dd> <dd><a href="/wiki/Intel_80387SX" title="Intel 80387SX">80387SX</a></dd> <dt>32-bit databus</dt> <dd><a href="/wiki/Intel_80387" class="mw-redirect" title="Intel 80387">80387DX</a></dd> <dd><a href="/wiki/Intel_80487" class="mw-redirect" title="Intel 80487">80487</a></dd></dl> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/IA-32" title="IA-32">IA-32</a> (<a href="/wiki/32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/I386" title="I386">i386</a> <ul><li><a href="/wiki/Intel_80386SX" class="mw-redirect" title="Intel 80386SX">SX</a></li> <li><a href="/wiki/Intel_80376" title="Intel 80376">376</a></li> <li><a href="/wiki/Intel_80386EX" title="Intel 80386EX">EX</a></li></ul></li> <li><a class="mw-selflink selflink">i486</a> <ul><li><a href="/wiki/I486SX" title="I486SX">SX</a></li> <li><a href="/wiki/Intel_DX2" title="Intel DX2">DX2</a></li> <li><a href="/wiki/Intel_DX4" title="Intel DX4">DX4</a></li> <li><a href="/wiki/I486SL" title="I486SL">SL</a></li> <li><a href="/wiki/RapidCAD" title="RapidCAD">RapidCAD</a></li> <li><a href="/wiki/I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li> <li><a href="/wiki/Stealey" title="Stealey">A100/A110</a></li> <li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li> <li><a href="/wiki/Atom_(system_on_a_chip)" title="Atom (system on a chip)">SoC</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> (1998) <ul><li><a href="/wiki/Celeron#P6-based_Mobile_Celerons" title="Celeron">M</a></li> <li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a> (2004)</li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_(original)" title="Pentium (original)">Original i586</a></li> <li><a href="/wiki/Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li> <li><a href="/wiki/Pentium_Pro" title="Pentium Pro">Pro</a></li> <li><a href="/wiki/Pentium_II" title="Pentium II">II</a></li> <li><a href="/wiki/Pentium_III" title="Pentium III">III</a></li> <li><a href="/wiki/Pentium_4" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_M" title="Pentium M">M</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li> <li><a href="/wiki/List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li> <li><a href="/wiki/List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li> <li><a href="/wiki/Intel_Quark" title="Intel Quark">Quark</a></li> <li><a href="/wiki/Tolapai" title="Tolapai">Tolapai</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="/wiki/X86-64" title="X86-64">x86-64</a> (<a href="/wiki/64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Intel_Atom" title="Intel Atom">Atom</a> <ul><li><a href="/wiki/Atom_(system_on_chip)" class="mw-redirect" title="Atom (system on chip)">SoC</a></li> <li><a href="/wiki/List_of_Intel_Atom_processors#CE_SoCs" title="List of Intel Atom processors">CE</a></li></ul></li> <li><a href="/wiki/Celeron" title="Celeron">Celeron</a> <ul><li><a href="/wiki/Celeron#Prescott-256" title="Celeron">D</a></li> <li><a href="/wiki/Celeron#Celeron_Dual-Core" title="Celeron">Dual-Core</a></li></ul></li> <li><a href="/wiki/Pentium" title="Pentium">Pentium</a> <ul><li><a href="/wiki/Pentium_4#Prescott_2M_(Extreme_Edition)" title="Pentium 4">4</a></li> <li><a href="/wiki/Pentium_D" title="Pentium D">D</a></li> <li><a href="/wiki/Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li> <li><a href="/wiki/Pentium_Dual-Core" title="Pentium Dual-Core">Dual-Core</a></li></ul></li> <li><a href="/wiki/Intel_Core" title="Intel Core">Core</a> <ul><li><a href="/wiki/Intel_Core_2" title="Intel Core 2">2</a></li> <li><a href="/wiki/Intel_Core#1st_generation" title="Intel Core">1st gen</a></li> <li><a href="/wiki/Intel_Core#2nd_generation" title="Intel Core">2nd gen</a></li> <li><a href="/wiki/Intel_Core#3rd_generation" title="Intel Core">3rd gen</a></li> <li><a href="/wiki/Intel_Core#4th_generation" title="Intel Core">4th gen</a></li> <li><a href="/wiki/Intel_Core#5th_generation" title="Intel Core">5th gen</a></li> <li><a href="/wiki/Intel_Core#6th_generation" title="Intel Core">6th gen</a></li> <li><a href="/wiki/Intel_Core#7th_generation" title="Intel Core">7th gen</a></li> <li><a href="/wiki/Intel_Core#8th_generation" title="Intel Core">8th gen</a></li> <li><a href="/wiki/Intel_Core#9th_generation" title="Intel Core">9th gen</a></li> <li><a href="/wiki/Intel_Core#10th_generation" title="Intel Core">10th gen</a></li> <li><a href="/wiki/Intel_Core#11th_generation" title="Intel Core">11th gen</a></li> <li><a href="/wiki/List_of_Intel_Core_M_processors" class="mw-redirect" title="List of Intel Core M processors">M</a></li></ul></li> <li><a href="/wiki/Xeon" title="Xeon">Xeon</a> <ul><li><a href="/wiki/List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li> <li><a href="/wiki/List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em"> <dl><dt><a href="/wiki/Complex_instruction_set_computer" title="Complex instruction set computer">CISC</a></dt> <dd><a href="/wiki/Intel_iAPX_432" title="Intel iAPX 432">iAPX 432</a></dd> <dt><a href="/wiki/Explicitly_parallel_instruction_computing" title="Explicitly parallel instruction computing">EPIC</a></dt> <dd><a href="/wiki/Itanium" title="Itanium">Itanium</a></dd> <dt><a href="/wiki/Reduced_instruction_set_computer" title="Reduced instruction set computer">RISC</a></dt> <dd><a href="/wiki/Intel_i860" title="Intel i860">i860</a></dd> <dd><a href="/wiki/Intel_i960" title="Intel i960">i960</a></dd> <dd><a href="/wiki/StrongARM" title="StrongARM">StrongARM</a></dd> <dd><a href="/wiki/XScale" title="XScale">XScale</a></dd></dl> </div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li> <li><a href="/wiki/Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li> <li><a href="/wiki/List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a> <ul><li><a href="/wiki/Intel_GMA" title="Intel GMA">GMA</a></li> <li><a href="/wiki/Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li> <li><a href="/wiki/Intel_Xe" title="Intel Xe">Xe</a></li> <li><a href="/wiki/Intel_Arc" title="Intel Arc">Arc</a></li></ul></li> <li><a href="/wiki/Platform_Controller_Hub" title="Platform Controller Hub">PCHs</a></li> <li><a href="/wiki/System_Controller_Hub" title="System Controller Hub">SCHs</a></li> <li><a href="/wiki/I/O_Controller_Hub" title="I/O Controller Hub">ICHs</a></li> <li><a href="/wiki/PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li> <li><a href="/wiki/Stratix" title="Stratix">Stratix</a></li> <li><a href="/wiki/List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li> <li><a href="/wiki/Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul> </div></td></tr></tbody></table></div> <div class="navbox-styles"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1129693374"><link rel="mw-deduplicated-inline-style" href="mw-data:TemplateStyles:r1236075235"><style data-mw-deduplicate="TemplateStyles:r1038841319">.mw-parser-output .tooltip-dotted{border-bottom:1px dotted;cursor:help}</style></div><div role="navigation" class="navbox authority-control" aria-label="Navbox" style="padding:3px"><table class="nowraplinks hlist navbox-inner" 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