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<meta name="description" content="Search results for: VLSI"> <meta name="keywords" content="VLSI"> <meta name="viewport" content="width=device-width, initial-scale=1, minimum-scale=1, maximum-scale=1, user-scalable=no"> <meta charset="utf-8"> <link href="https://cdn.waset.org/favicon.ico" type="image/x-icon" rel="shortcut icon"> <link href="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/css/bootstrap.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/plugins/fontawesome/css/all.min.css" rel="stylesheet"> <link href="https://cdn.waset.org/static/css/site.css?v=150220211555" rel="stylesheet"> </head> <body> <header> <div class="container"> <nav class="navbar navbar-expand-lg navbar-light"> <a class="navbar-brand" href="https://waset.org"> <img src="https://cdn.waset.org/static/images/wasetc.png" alt="Open Science Research Excellence" title="Open Science Research Excellence" /> </a> <button class="d-block d-lg-none navbar-toggler ml-auto" type="button" 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class="input-group"> <i class="fas fa-search"></i> <input type="text" class="search-query" name="q" placeholder="Author, Title, Abstract, Keywords" value="VLSI"> <input type="submit" class="btn_search" value="Search"> </div> </div> </form> </div> </div> <div class="row mt-3"> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Commenced</strong> in January 2007</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Frequency:</strong> Monthly</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Edition:</strong> International</div> </div> </div> <div class="col-sm-3"> <div class="card"> <div class="card-body"><strong>Paper Count:</strong> 18</div> </div> </div> </div> <h1 class="mt-3 mb-3 text-center" style="font-size:1.6rem;">Search results for: VLSI</h1> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">18</span> Timing and Noise Data Mining Algorithm and Software Tool in Very Large Scale Integration (VLSI) Design</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Qing%20K.%20Zhu">Qing K. Zhu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Very Large Scale Integration (VLSI) design becomes very complex due to the continuous integration of millions of gates in one chip based on Moore’s law. Designers have encountered numerous report files during design iterations using timing and noise analysis tools. This paper presented our work using data mining techniques combined with HTML tables to extract and represent critical timing/noise data. When we apply this data-mining tool in real applications, the running speed is important. The software employs table look-up techniques in the programming for the reasonable running speed based on performance testing results. We added several advanced features for the application in one industry chip design. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=VLSI%20design" title="VLSI design">VLSI design</a>, <a href="https://publications.waset.org/abstracts/search?q=data%20mining" title=" data mining"> data mining</a>, <a href="https://publications.waset.org/abstracts/search?q=big%20data" title=" big data"> big data</a>, <a href="https://publications.waset.org/abstracts/search?q=HTML%20forms" title=" HTML forms"> HTML forms</a>, <a href="https://publications.waset.org/abstracts/search?q=web" title=" web"> web</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI" title=" VLSI"> VLSI</a>, <a href="https://publications.waset.org/abstracts/search?q=EDA" title=" EDA"> EDA</a>, <a href="https://publications.waset.org/abstracts/search?q=timing" title=" timing"> timing</a>, <a href="https://publications.waset.org/abstracts/search?q=noise" title=" noise"> noise</a> </p> <a href="https://publications.waset.org/abstracts/90483/timing-and-noise-data-mining-algorithm-and-software-tool-in-very-large-scale-integration-vlsi-design" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/90483.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">254</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">17</span> Signal Integrity Performance Analysis in Capacitive and Inductively Coupled Very Large Scale Integration Interconnect Models</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mudavath%20Raju">Mudavath Raju</a>, <a href="https://publications.waset.org/abstracts/search?q=Bhaskar%20Gugulothu"> Bhaskar Gugulothu</a>, <a href="https://publications.waset.org/abstracts/search?q=B.%20Rajendra%20Naik"> B. Rajendra Naik</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The rapid advances in Very Large Scale Integration (VLSI) technology has resulted in the reduction of minimum feature size to sub-quarter microns and switching time in tens of picoseconds or even less. As a result, the degradation of high-speed digital circuits due to signal integrity issues such as coupling effects, clock feedthrough, crosstalk noise and delay uncertainty noise. Crosstalk noise in VLSI interconnects is a major concern and reduction in VLSI interconnect has become more important for high-speed digital circuits. It is the most effectively considered in Deep Sub Micron (DSM) and Ultra Deep Sub Micron (UDSM) technology. Increasing spacing in-between aggressor and victim line is one of the technique to reduce the crosstalk. Guard trace or shield insertion in-between aggressor and victim is also one of the prominent options for the minimization of crosstalk. In this paper, far end crosstalk noise is estimated with mutual inductance and capacitance RLC interconnect model. Also investigated the extent of crosstalk in capacitive and inductively coupled interconnects to minimizes the same through shield insertion technique. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=VLSI" title="VLSI">VLSI</a>, <a href="https://publications.waset.org/abstracts/search?q=interconnects" title=" interconnects"> interconnects</a>, <a href="https://publications.waset.org/abstracts/search?q=signal%20integrity" title=" signal integrity"> signal integrity</a>, <a href="https://publications.waset.org/abstracts/search?q=crosstalk" title=" crosstalk"> crosstalk</a>, <a href="https://publications.waset.org/abstracts/search?q=shield%20insertion" title=" shield insertion"> shield insertion</a>, <a href="https://publications.waset.org/abstracts/search?q=guard%20trace" title=" guard trace"> guard trace</a>, <a href="https://publications.waset.org/abstracts/search?q=deep%20sub%20micron" title=" deep sub micron"> deep sub micron</a> </p> <a href="https://publications.waset.org/abstracts/87200/signal-integrity-performance-analysis-in-capacitive-and-inductively-coupled-very-large-scale-integration-interconnect-models" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/87200.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">185</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">16</span> Performance Analysis of Carbon Nanotube for VLSI Interconnects and Their Comparison with Copper Interconnects</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Gagnesh%20Kumar">Gagnesh Kumar</a>, <a href="https://publications.waset.org/abstracts/search?q=Prashant%20Gupta"> Prashant Gupta</a> </p> <p class="card-text"><strong>Abstract:</strong></p> This paper investigates the performance of the bundle of single wall carbon nanotubes (SWCNT) for low-power and high-speed interconnects for future VLSI applications. The power dissipation, delay and power delay product (PDP) of SWCNT bundle interconnects are examined and compared with that of the Cu interconnects at 22 nm technology node for both intermediate and global interconnects. The results show that SWCNT bundle consume less power and also faster than Cu for intermediate and global interconnects. It is concluded that the metallic SWCNT has been regarded as a viable candidate for intermediate and global interconnects in future technologies. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=carbon%20nanotube" title="carbon nanotube">carbon nanotube</a>, <a href="https://publications.waset.org/abstracts/search?q=SWCNT" title=" SWCNT"> SWCNT</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=delay" title=" delay"> delay</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20delay%20product" title=" power delay product"> power delay product</a>, <a href="https://publications.waset.org/abstracts/search?q=global%20and%20intermediate%20interconnects" title=" global and intermediate interconnects"> global and intermediate interconnects</a> </p> <a href="https://publications.waset.org/abstracts/9055/performance-analysis-of-carbon-nanotube-for-vlsi-interconnects-and-their-comparison-with-copper-interconnects" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/9055.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">320</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">15</span> Application of Carbon Nanotube and Nanowire FET Devices in Future VLSI</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Saurabh%20Chaudhury">Saurabh Chaudhury</a>, <a href="https://publications.waset.org/abstracts/search?q=Sanjeet%20Kumar%20Sinha"> Sanjeet Kumar Sinha</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The MOSFET has been the main building block in high performance and low power VLSI chips for the last several decades. Device scaling is fundamental to technological advancements, which allows more devices to be integrated on a single die providing greater functionality per chip. Ultimately, the goal of scaling is to build an individual transistor that is smaller, faster, cheaper, and consumes less power. Scaling continued following Moore's law initially and now we see an exponential growth in today's nano scaled chip. However, device scaling to deep nano meter regime leads to exponential increase in leakage currents and excessive heat generation. Moreover, fabrication process variability causing a limitation to further scaling. Researchers believe that with a mix of chemistry, physics, and engineering, nano electronics may provide a solution to increasing fabrication costs and may allow integrated circuits to be scaled beyond the limits of the modern transistor. Carbon nano tube (CNT) and nano wires (NW) based FETs have been analyzed and characterized in laboratory and also been demonstrated as prototypes. This work presents an extensive simulation based study and analysis of CNTFET and NW-FET devices and comparison of the results with conventional MOSFET. From this study, we can conclude that these devices have got some excellent properties and favorable characteristics which will definitely lead the future semiconductor devices in post silicon era. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=carbon%20nanotube" title="carbon nanotube">carbon nanotube</a>, <a href="https://publications.waset.org/abstracts/search?q=nanowire%20FET" title=" nanowire FET"> nanowire FET</a>, <a href="https://publications.waset.org/abstracts/search?q=low%20power" title=" low power"> low power</a>, <a href="https://publications.waset.org/abstracts/search?q=nanoscaled%20devices" title=" nanoscaled devices"> nanoscaled devices</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI" title=" VLSI"> VLSI</a> </p> <a href="https://publications.waset.org/abstracts/15828/application-of-carbon-nanotube-and-nanowire-fet-devices-in-future-vlsi" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/15828.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">411</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">14</span> Energy Saving Techniques for MIMO Decoders </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Zhuofan%20Cheng">Zhuofan Cheng</a>, <a href="https://publications.waset.org/abstracts/search?q=Qiongda%20Hu"> Qiongda Hu</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammed%20El-Hajjar"> Mohammed El-Hajjar</a>, <a href="https://publications.waset.org/abstracts/search?q=Basel%20Halak"> Basel Halak</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Multiple-input multiple-output (MIMO) systems can allow significantly higher data rates compared to single-antenna-aided systems. They are expected to be a prominent part of the 5G communication standard. However, these decoders suffer from high power consumption. This work presents a design technique in order to improve the energy efficiency of MIMO systems; this facilitates their use in the next generation of battery-operated communication devices such as mobile phones and tablets. The proposed optimization approach consists of the use of low complexity lattice reduction algorithm in combination with an adaptive VLSI implementation. The proposed design has been realized and verified in 65nm technology. The results show that the proposed design is significantly more energy-efficient than conventional K-best MIMO systems. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=energy" title="energy">energy</a>, <a href="https://publications.waset.org/abstracts/search?q=lattice%20reduction" title=" lattice reduction"> lattice reduction</a>, <a href="https://publications.waset.org/abstracts/search?q=MIMO" title=" MIMO"> MIMO</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI" title=" VLSI "> VLSI </a> </p> <a href="https://publications.waset.org/abstracts/45939/energy-saving-techniques-for-mimo-decoders" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/45939.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">328</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">13</span> Design of Speedy, Scanty Adder for Lossy Application Using QCA</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=T.%20Angeline%20Priyanka">T. Angeline Priyanka</a>, <a href="https://publications.waset.org/abstracts/search?q=R.%20Ganesan"> R. Ganesan</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Recent trends in microelectronics technology have gradually changed the strategies used in very large scale integration (VLSI) circuits. Complementary Metal Oxide Semiconductor (CMOS) technology has been the industry standard for implementing VLSI device for the past two decades, but due to scale-down issues of ultra-low dimension achievement is not achieved so far. Hence it paved a way for Quantum Cellular Automata (QCA). It is only one of the many alternative technologies proposed as a replacement solution to the fundamental limit problem that CMOS technology will impose in the years to come. In this brief, presented a new adder that possesses high speed of operation occupying less area is proposed. This adder is designed especially for error tolerant application. Hence in the proposed adder, the overall area (cell count) and simulation time are reduced by 88 and 73 percent respectively. Various results of the proposed adder are shown and described. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=quantum%20cellular%20automata" title="quantum cellular automata">quantum cellular automata</a>, <a href="https://publications.waset.org/abstracts/search?q=carry%20look%20ahead%20adder" title=" carry look ahead adder"> carry look ahead adder</a>, <a href="https://publications.waset.org/abstracts/search?q=ripple%20carry%20adder" title=" ripple carry adder"> ripple carry adder</a>, <a href="https://publications.waset.org/abstracts/search?q=lossy%20application" title=" lossy application"> lossy application</a>, <a href="https://publications.waset.org/abstracts/search?q=majority%20gate" title=" majority gate"> majority gate</a>, <a href="https://publications.waset.org/abstracts/search?q=crossover" title=" crossover"> crossover</a> </p> <a href="https://publications.waset.org/abstracts/32396/design-of-speedy-scanty-adder-for-lossy-application-using-qca" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/32396.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">556</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">12</span> Optimizing Power in Sequential Circuits by Reducing Leakage Current Using Enhanced Multi Threshold CMOS </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Patikineti%20Sreenivasulu">Patikineti Sreenivasulu</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20srinivasa%20Rao"> K. srinivasa Rao</a>, <a href="https://publications.waset.org/abstracts/search?q=A.%20Vinaya%20Babu"> A. Vinaya Babu</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The demand for portability, performance and high functional integration density of digital devices leads to the scaling of complementary metal oxide semiconductor (CMOS) devices inevitable. The increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. MTCMOS technology provides low leakage and high performance operation by utilizing high speed, low Vt (LVT) transistors for logic cells and low leakage, high Vt (HVT) devices as sleep transistors. Sleep transistors disconnect logic cells from the supply and/or ground to reduce the leakage in the sleep mode. In this technology, energy consumption while doing the mode transition and minimum time required to turn ON the circuit upon receiving the wake up signal are issues to be considered because these can adversely impact the performance of VLSI circuit. In this paper we are introducing an enhancing method of MTCMOS technology to optimize the power in MTCMOS sequential circuits. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=power%20consumption" title="power consumption">power consumption</a>, <a href="https://publications.waset.org/abstracts/search?q=ultra-low%20power" title=" ultra-low power"> ultra-low power</a>, <a href="https://publications.waset.org/abstracts/search?q=leakage" title=" leakage"> leakage</a>, <a href="https://publications.waset.org/abstracts/search?q=sub%20threshold" title=" sub threshold"> sub threshold</a>, <a href="https://publications.waset.org/abstracts/search?q=MTCMOS" title=" MTCMOS"> MTCMOS</a> </p> <a href="https://publications.waset.org/abstracts/35180/optimizing-power-in-sequential-circuits-by-reducing-leakage-current-using-enhanced-multi-threshold-cmos" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/35180.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">406</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">11</span> Sigma-Delta ADCs Converter a Study Case</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Thiago%20Brito%20Bezerra">Thiago Brito Bezerra</a>, <a href="https://publications.waset.org/abstracts/search?q=Mauro%20Lopes%20de%20Freitas"> Mauro Lopes de Freitas</a>, <a href="https://publications.waset.org/abstracts/search?q=Waldir%20Sabino%20da%20Silva%20J%C3%BAnior"> Waldir Sabino da Silva Júnior</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The Sigma-Delta A/D converters have been proposed as a practical application for A/D conversion at high rates because of its simplicity and robustness to imperfections in the circuit, also because the traditional converters are more difficult to implement in VLSI technology. These difficulties with conventional conversion methods need precise analog components in their filters and conversion circuits, and are more vulnerable to noise and interference. This paper aims to analyze the architecture, function and application of Analog-Digital converters (A/D) Sigma-Delta to overcome these difficulties, showing some simulations using the Simulink software and Multisim. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=analysis" title="analysis">analysis</a>, <a href="https://publications.waset.org/abstracts/search?q=oversampling%20modulator" title=" oversampling modulator"> oversampling modulator</a>, <a href="https://publications.waset.org/abstracts/search?q=A%2FD%20converters" title=" A/D converters"> A/D converters</a>, <a href="https://publications.waset.org/abstracts/search?q=sigma-delta" title=" sigma-delta"> sigma-delta</a> </p> <a href="https://publications.waset.org/abstracts/12643/sigma-delta-adcs-converter-a-study-case" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/12643.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">328</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">10</span> Fractional Residue Number System</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Parisa%20Khoshvaght">Parisa Khoshvaght</a>, <a href="https://publications.waset.org/abstracts/search?q=Mehdi%20Hosseinzadeh"> Mehdi Hosseinzadeh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> During the past few years, the Residue Number System (RNS) has been receiving considerable interest due to its parallel and fault-tolerant properties. This system is a useful tool for Digital Signal Processing (DSP) since it can support parallel, carry-free, high-speed and low power arithmetic. One of the drawbacks of Residue Number System is the fractional numbers, that is, the corresponding circuit is very hard to realize in conventional CMOS technology. In this paper, we propose a method in which the numbers of transistors are significantly reduced. The related delay is extremely diminished, in the first glance we use this method to solve concerning problem of one decimal functional number some how this proposition can be extended to generalize the idea. Another advantage of this method is the independency on the kind of moduli. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=computer%20arithmetic" title="computer arithmetic">computer arithmetic</a>, <a href="https://publications.waset.org/abstracts/search?q=residue%20number%20system" title=" residue number system"> residue number system</a>, <a href="https://publications.waset.org/abstracts/search?q=number%20system" title=" number system"> number system</a>, <a href="https://publications.waset.org/abstracts/search?q=one-Hot" title=" one-Hot"> one-Hot</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI" title=" VLSI"> VLSI</a> </p> <a href="https://publications.waset.org/abstracts/30341/fractional-residue-number-system" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/30341.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">495</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">9</span> An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ch.%20Ashok%20Babu">Ch. Ashok Babu</a>, <a href="https://publications.waset.org/abstracts/search?q=J.%20V.%20R.%20Ravindra"> J. V. R. Ravindra</a>, <a href="https://publications.waset.org/abstracts/search?q=K.%20Lalkishore"> K. Lalkishore</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Power has became a burning issue in modern VLSI design. As the technology advances especially below 45nm, technology of leakage power became a big problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder, DTMOS full adder. This paper shows different types of adders and their power consumption, area, and delay. All the experiments have been carried out using Cadence® Virtuoso® design lay out editor which shows power consumption of different types of adders. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=average%20power" title="average power">average power</a>, <a href="https://publications.waset.org/abstracts/search?q=leakage%20power" title=" leakage power"> leakage power</a>, <a href="https://publications.waset.org/abstracts/search?q=delay" title=" delay"> delay</a>, <a href="https://publications.waset.org/abstracts/search?q=DTMOS" title=" DTMOS"> DTMOS</a>, <a href="https://publications.waset.org/abstracts/search?q=PDP" title=" PDP "> PDP </a> </p> <a href="https://publications.waset.org/abstracts/2018/an-adder-with-novel-pmos-and-nmos-for-ultra-low-power-applications-in-deep-submicron-technology" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/2018.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">389</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">8</span> Design and Implementation of 2D Mesh Network on Chip Using VHDL</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Boudjedra%20Abderrahim">Boudjedra Abderrahim</a>, <a href="https://publications.waset.org/abstracts/search?q=Toumi%20Salah"> Toumi Salah</a>, <a href="https://publications.waset.org/abstracts/search?q=Boutalbi%20Mostefa"> Boutalbi Mostefa</a>, <a href="https://publications.waset.org/abstracts/search?q=Frihi%20Mohammed"> Frihi Mohammed</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Nowadays, using the advancement of technology in semiconductor device fabrication, many transistors can be integrated to a single chip (VLSI). Although the growth chip density potentially eases systems-on-chip (SoCs) integrating thousands of processing element (PE) such as memory, processor, interfaces cores, system complexity, high-performance interconnect and scalable on-chip communication architecture become most challenges for many digital and embedded system designers. Networks-on-chip (NoCs) becomes a new paradigm that makes possible integrating heterogeneous devices and allows many communication constraints and performances. In this paper, we are interested for good performance and low area for implementation and a behavioral modeling of network on chip mesh topology design using VHDL hardware description language with performance evaluation and FPGA implementation results. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=design" title="design">design</a>, <a href="https://publications.waset.org/abstracts/search?q=implementation" title=" implementation"> implementation</a>, <a href="https://publications.waset.org/abstracts/search?q=communication%20system" title=" communication system"> communication system</a>, <a href="https://publications.waset.org/abstracts/search?q=network%20on%20chip" title=" network on chip"> network on chip</a>, <a href="https://publications.waset.org/abstracts/search?q=VHDL" title=" VHDL"> VHDL</a> </p> <a href="https://publications.waset.org/abstracts/3993/design-and-implementation-of-2d-mesh-network-on-chip-using-vhdl" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/3993.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">378</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">7</span> A New Full Adder Cell for High Performance Low Power Applications</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mahdiar%20Hosseighadiry">Mahdiar Hosseighadiry</a>, <a href="https://publications.waset.org/abstracts/search?q=Farnaz%20Fotovatikhah"> Farnaz Fotovatikhah</a>, <a href="https://publications.waset.org/abstracts/search?q=Razali%20Ismail"> Razali Ismail</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohsen%20Khaledian"> Mohsen Khaledian</a>, <a href="https://publications.waset.org/abstracts/search?q=Mehdi%20Saeidemanesh"> Mehdi Saeidemanesh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> In this paper, a new low-power high-performance full adder is presented based on a new design method. The proposed method relies on pass gate design and provides full-swing circuits with minimum number of transistors. The method has been applied on SUM, COUT and XOR-XNOR modules resulting on rail-to-rail intermediate and output signals with no feedback transistors. The presented full adder cell has been simulated in 45 and 32 nm CMOS technologies using HSPICE considering parasitic capacitance and compared to several well-known designs from literature. In addition, the proposed cell has been extensively evaluated with different output loads, supply voltages, temperatures, threshold voltages, and operating frequencies. Results show that it functions properly under all mentioned conditions and exhibits less PDP compared to other design styles. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=full%20adders" title="full adders">full adders</a>, <a href="https://publications.waset.org/abstracts/search?q=low-power" title=" low-power"> low-power</a>, <a href="https://publications.waset.org/abstracts/search?q=high-performance" title=" high-performance"> high-performance</a>, <a href="https://publications.waset.org/abstracts/search?q=VLSI%20design" title=" VLSI design"> VLSI design</a> </p> <a href="https://publications.waset.org/abstracts/6812/a-new-full-adder-cell-for-high-performance-low-power-applications" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/6812.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">388</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">6</span> Identification of Promising Infant Clusters to Obtain Improved Block Layout Designs </h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Mustahsan%20Mir">Mustahsan Mir</a>, <a href="https://publications.waset.org/abstracts/search?q=Ahmed%20Hassanin"> Ahmed Hassanin</a>, <a href="https://publications.waset.org/abstracts/search?q=Mohammed%20A.%20Al-Saleh"> Mohammed A. Al-Saleh</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The layout optimization of building blocks of unequal areas has applications in many disciplines including VLSI floorplanning, macrocell placement, unequal-area facilities layout optimization, and plant or machine layout design. A number of heuristics and some analytical and hybrid techniques have been published to solve this problem. This paper presents an efficient high-quality building-block layout design technique especially suited for solving large-size problems. The higher efficiency and improved quality of optimized solutions are made possible by introducing the concept of Promising Infant Clusters in a constructive placement procedure. The results presented in the paper demonstrate the improved performance of the presented technique for benchmark problems in comparison with published heuristic, analytic, and hybrid techniques. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=block%20layout%20problem" title="block layout problem">block layout problem</a>, <a href="https://publications.waset.org/abstracts/search?q=building-block%20layout%20design" title=" building-block layout design"> building-block layout design</a>, <a href="https://publications.waset.org/abstracts/search?q=CAD" title=" CAD"> CAD</a>, <a href="https://publications.waset.org/abstracts/search?q=optimization" title=" optimization"> optimization</a>, <a href="https://publications.waset.org/abstracts/search?q=search%20techniques" title=" search techniques"> search techniques</a> </p> <a href="https://publications.waset.org/abstracts/38727/identification-of-promising-infant-clusters-to-obtain-improved-block-layout-designs" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/38727.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">386</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">5</span> Efficient Semi-Systolic Finite Field Multiplier Using Redundant Basis</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Hyun-Ho%20Lee">Hyun-Ho Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Kee-Won%20Kim"> Kee-Won Kim</a> </p> <p class="card-text"><strong>Abstract:</strong></p> The arithmetic operations over GF(2m) have been extensively used in error correcting codes and public-key cryptography schemes. Finite field arithmetic includes addition, multiplication, division and inversion operations. Addition is very simple and can be implemented with an extremely simple circuit. The other operations are much more complex. The multiplication is the most important for cryptosystems, such as the elliptic curve cryptosystem, since computing exponentiation, division, and computing multiplicative inverse can be performed by computing multiplication iteratively. In this paper, we present a parallel computation algorithm that operates Montgomery multiplication over finite field using redundant basis. Also, based on the multiplication algorithm, we present an efficient semi-systolic multiplier over finite field. The multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the multiplier saves at least 5% area, 50% time, and 53% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as inversion and division operation. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=finite%20field" title="finite field">finite field</a>, <a href="https://publications.waset.org/abstracts/search?q=Montgomery%20multiplication" title=" Montgomery multiplication"> Montgomery multiplication</a>, <a href="https://publications.waset.org/abstracts/search?q=systolic%20array" title=" systolic array"> systolic array</a>, <a href="https://publications.waset.org/abstracts/search?q=cryptography" title=" cryptography"> cryptography</a> </p> <a href="https://publications.waset.org/abstracts/55023/efficient-semi-systolic-finite-field-multiplier-using-redundant-basis" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/55023.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">294</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">4</span> Scalable Systolic Multiplier over Binary Extension Fields Based on Two-Level Karatsuba Decomposition</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Chiou-Yng%20Lee">Chiou-Yng Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Wen-Yo%20Lee"> Wen-Yo Lee</a>, <a href="https://publications.waset.org/abstracts/search?q=Chieh-Tsai%20Wu"> Chieh-Tsai Wu</a>, <a href="https://publications.waset.org/abstracts/search?q=Cheng-Chen%20Yang"> Cheng-Chen Yang</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Shifted polynomial basis (SPB) is a variation of polynomial basis representation. SPB has potential for efficient bit-level and digit-level implementations of multiplication over binary extension fields with subquadratic space complexity. For efficient implementation of pairing computation with large finite fields, this paper presents a new SPB multiplication algorithm based on Karatsuba schemes, and used that to derive a novel scalable multiplier architecture. Analytical results show that the proposed multiplier provides a trade-off between space and time complexities. Our proposed multiplier is modular, regular, and suitable for very-large-scale integration (VLSI) implementations. It involves less area complexity compared to the multipliers based on traditional decomposition methods. It is therefore, more suitable for efficient hardware implementation of pairing based cryptography and elliptic curve cryptography (ECC) in constraint driven applications. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=digit-serial%20systolic%20multiplier" title="digit-serial systolic multiplier">digit-serial systolic multiplier</a>, <a href="https://publications.waset.org/abstracts/search?q=elliptic%20curve%20cryptography%20%28ECC%29" title=" elliptic curve cryptography (ECC)"> elliptic curve cryptography (ECC)</a>, <a href="https://publications.waset.org/abstracts/search?q=Karatsuba%20algorithm%20%28KA%29" title=" Karatsuba algorithm (KA)"> Karatsuba algorithm (KA)</a>, <a href="https://publications.waset.org/abstracts/search?q=shifted%20polynomial%20basis%20%28SPB%29" title=" shifted polynomial basis (SPB)"> shifted polynomial basis (SPB)</a>, <a href="https://publications.waset.org/abstracts/search?q=pairing%20computation" title=" pairing computation"> pairing computation</a> </p> <a href="https://publications.waset.org/abstracts/8169/scalable-systolic-multiplier-over-binary-extension-fields-based-on-two-level-karatsuba-decomposition" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/8169.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">361</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">3</span> A Test Methodology to Measure the Open-Loop Voltage Gain of an Operational Amplifier</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Maninder%20Kaur%20Gill">Maninder Kaur Gill</a>, <a href="https://publications.waset.org/abstracts/search?q=Alpana%20Agarwal"> Alpana Agarwal</a> </p> <p class="card-text"><strong>Abstract:</strong></p> It is practically not feasible to measure the open-loop voltage gain of the operational amplifier in the open loop configuration. It is because the open-loop voltage gain of the operational amplifier is very large. In order to avoid the saturation of the output voltage, a very small input should be given to operational amplifier which is not possible to be measured practically by a digital multimeter. A test circuit for measurement of open loop voltage gain of an operational amplifier has been proposed and verified using simulation tools as well as by experimental methods on breadboard. The main advantage of this test circuit is that it is simple, fast, accurate, cost effective, and easy to handle even on a breadboard. The test circuit requires only the device under test (DUT) along with resistors. This circuit has been tested for measurement of open loop voltage gain for different operational amplifiers. The underlying goal is to design testable circuits for various analog devices that are simple to realize in VLSI systems, giving accurate results and without changing the characteristics of the original system. The DUTs used are LM741CN and UA741CP. For LM741CN, the simulated gain and experimentally measured gain (average) are calculated as 89.71 dB and 87.71 dB, respectively. For UA741CP, the simulated gain and experimentally measured gain (average) are calculated as 101.15 dB and 105.15 dB, respectively. These values are found to be close to the datasheet values. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=Device%20Under%20Test%20%28DUT%29" title="Device Under Test (DUT)">Device Under Test (DUT)</a>, <a href="https://publications.waset.org/abstracts/search?q=open%20loop%20voltage%20gain" title=" open loop voltage gain"> open loop voltage gain</a>, <a href="https://publications.waset.org/abstracts/search?q=operational%20amplifier" title=" operational amplifier"> operational amplifier</a>, <a href="https://publications.waset.org/abstracts/search?q=test%20circuit" title=" test circuit"> test circuit</a> </p> <a href="https://publications.waset.org/abstracts/63309/a-test-methodology-to-measure-the-open-loop-voltage-gain-of-an-operational-amplifier" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/63309.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">447</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">2</span> Overview of Multi-Chip Alternatives for 2.5 and 3D Integrated Circuit Packagings</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=Ching-Feng%20Chen">Ching-Feng Chen</a>, <a href="https://publications.waset.org/abstracts/search?q=Ching-Chih%20Tsai"> Ching-Chih Tsai</a> </p> <p class="card-text"><strong>Abstract:</strong></p> With the size of the transistor gradually approaching the physical limit, it challenges the persistence of Moore’s Law due to the development of the high numerical aperture (high-NA) lithography equipment and other issues such as short channel effects. In the context of the ever-increasing technical requirements of portable devices and high-performance computing, relying on the law continuation to enhance the chip density will no longer support the prospects of the electronics industry. Weighing the chip’s power consumption-performance-area-cost-cycle time to market (PPACC) is an updated benchmark to drive the evolution of the advanced wafer nanometer (nm). The advent of two and half- and three-dimensional (2.5 and 3D)- Very-Large-Scale Integration (VLSI) packaging based on Through Silicon Via (TSV) technology has updated the traditional die assembly methods and provided the solution. This overview investigates the up-to-date and cutting-edge packaging technologies for 2.5D and 3D integrated circuits (ICs) based on the updated transistor structure and technology nodes. The author concludes that multi-chip solutions for 2.5D and 3D IC packagings are feasible to prolong Moore’s Law. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=moore%E2%80%99s%20law" title="moore’s law">moore’s law</a>, <a href="https://publications.waset.org/abstracts/search?q=high%20numerical%20aperture" title=" high numerical aperture"> high numerical aperture</a>, <a href="https://publications.waset.org/abstracts/search?q=power%20consumption-performance-area-cost-cycle%20time%20to%20market" title=" power consumption-performance-area-cost-cycle time to market"> power consumption-performance-area-cost-cycle time to market</a>, <a href="https://publications.waset.org/abstracts/search?q=2.5%20and%203D-%20very-large-scale%20integration" title=" 2.5 and 3D- very-large-scale integration"> 2.5 and 3D- very-large-scale integration</a>, <a href="https://publications.waset.org/abstracts/search?q=packaging" title=" packaging"> packaging</a>, <a href="https://publications.waset.org/abstracts/search?q=through%20silicon%20via" title=" through silicon via"> through silicon via</a> </p> <a href="https://publications.waset.org/abstracts/155112/overview-of-multi-chip-alternatives-for-25-and-3d-integrated-circuit-packagings" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/155112.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">114</span> </span> </div> </div> <div class="card paper-listing mb-3 mt-3"> <h5 class="card-header" style="font-size:.9rem"><span class="badge badge-info">1</span> Designing Floor Planning in 2D and 3D with an Efficient Topological Structure</h5> <div class="card-body"> <p class="card-text"><strong>Authors:</strong> <a href="https://publications.waset.org/abstracts/search?q=V.%20Nagammai">V. Nagammai</a> </p> <p class="card-text"><strong>Abstract:</strong></p> Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. Development of technology increases the complexity in IC manufacturing which may vary the power consumption, increase the size and latency period. Topology defines a number of connections between network. In this project, NoC topology is generated using atlas tool which will increase performance in turn determination of constraints are effective. The routing is performed by XY routing algorithm and wormhole flow control. In NoC topology generation, the value of power, area and latency are predetermined. In previous work, placement, routing and shortest path evaluation is performed using an algorithm called floor planning with cluster reconstruction and path allocation algorithm (FCRPA) with the account of 4 3x3 switch, 6 4x4 switch, and 2 5x5 switches. The usage of the 4x4 and 5x5 switch will increase the power consumption and area of the block. In order to avoid the problem, this paper has used one 8x8 switch and 4 3x3 switches. This paper uses IPRCA which of 3 steps they are placement, clustering, and shortest path evaluation. The placement is performed using min – cut placement and clustering are performed using an algorithm called cluster generation. The shortest path is evaluated using an algorithm called Dijkstra's algorithm. The power consumption of each block is determined. The experimental result shows that the area, power, and wire length improved simultaneously. <p class="card-text"><strong>Keywords:</strong> <a href="https://publications.waset.org/abstracts/search?q=application%20specific%20noc" title="application specific noc">application specific noc</a>, <a href="https://publications.waset.org/abstracts/search?q=b%2A%20tree%20representation" title=" b* tree representation"> b* tree representation</a>, <a href="https://publications.waset.org/abstracts/search?q=floor%20planning" title=" floor planning"> floor planning</a>, <a href="https://publications.waset.org/abstracts/search?q=t%20tree%20representation" title=" t tree representation"> t tree representation</a> </p> <a href="https://publications.waset.org/abstracts/45379/designing-floor-planning-in-2d-and-3d-with-an-efficient-topological-structure" class="btn btn-primary btn-sm">Procedia</a> <a href="https://publications.waset.org/abstracts/45379.pdf" target="_blank" class="btn btn-primary btn-sm">PDF</a> <span class="bg-info text-light px-1 py-1 float-right rounded"> Downloads <span class="badge badge-light">393</span> </span> </div> </div> </div> </main> <footer> <div id="infolinks" class="pt-3 pb-2"> <div class="container"> <div style="background-color:#f5f5f5;" class="p-3"> <div class="row"> <div class="col-md-2"> <ul class="list-unstyled"> About <li><a href="https://waset.org/page/support">About Us</a></li> <li><a href="https://waset.org/page/support#legal-information">Legal</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/WASET-16th-foundational-anniversary.pdf">WASET celebrates its 16th foundational anniversary</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Account <li><a href="https://waset.org/profile">My Account</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Explore <li><a href="https://waset.org/disciplines">Disciplines</a></li> <li><a href="https://waset.org/conferences">Conferences</a></li> <li><a href="https://waset.org/conference-programs">Conference Program</a></li> <li><a href="https://waset.org/committees">Committees</a></li> <li><a href="https://publications.waset.org">Publications</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Research <li><a href="https://publications.waset.org/abstracts">Abstracts</a></li> <li><a href="https://publications.waset.org">Periodicals</a></li> <li><a href="https://publications.waset.org/archive">Archive</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Open Science <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Science-Philosophy.pdf">Open Science Philosophy</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Science-Award.pdf">Open Science Award</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Open-Society-Open-Science-and-Open-Innovation.pdf">Open Innovation</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Postdoctoral-Fellowship-Award.pdf">Postdoctoral Fellowship Award</a></li> <li><a target="_blank" rel="nofollow" href="https://publications.waset.org/static/files/Scholarly-Research-Review.pdf">Scholarly Research Review</a></li> </ul> </div> <div class="col-md-2"> <ul class="list-unstyled"> Support <li><a href="https://waset.org/page/support">Support</a></li> <li><a href="https://waset.org/profile/messages/create">Contact Us</a></li> <li><a href="https://waset.org/profile/messages/create">Report Abuse</a></li> </ul> </div> </div> </div> </div> </div> <div class="container text-center"> <hr style="margin-top:0;margin-bottom:.3rem;"> <a href="https://creativecommons.org/licenses/by/4.0/" target="_blank" class="text-muted small">Creative Commons Attribution 4.0 International License</a> <div id="copy" class="mt-2">© 2024 World Academy of Science, Engineering and Technology</div> </div> </footer> <a href="javascript:" id="return-to-top"><i class="fas fa-arrow-up"></i></a> <div class="modal" id="modal-template"> <div class="modal-dialog"> <div class="modal-content"> <div class="row m-0 mt-1"> <div class="col-md-12"> <button type="button" class="close" data-dismiss="modal" aria-label="Close"><span aria-hidden="true">×</span></button> </div> </div> <div class="modal-body"></div> </div> </div> </div> <script src="https://cdn.waset.org/static/plugins/jquery-3.3.1.min.js"></script> <script src="https://cdn.waset.org/static/plugins/bootstrap-4.2.1/js/bootstrap.bundle.min.js"></script> <script src="https://cdn.waset.org/static/js/site.js?v=150220211556"></script> <script> jQuery(document).ready(function() { /*jQuery.get("https://publications.waset.org/xhr/user-menu", function (response) { jQuery('#mainNavMenu').append(response); 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