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class="vector-toc-text"> <span class="vector-toc-numb">2</span> <span>RTL in the circuit design cycle</span> </div> </a> <ul id="toc-RTL_in_the_circuit_design_cycle-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Power_estimation_techniques_for_RTL" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#Power_estimation_techniques_for_RTL"> <div class="vector-toc-text"> <span class="vector-toc-numb">3</span> <span>Power estimation techniques for RTL</span> </div> </a> <button aria-controls="toc-Power_estimation_techniques_for_RTL-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle Power estimation techniques for RTL subsection</span> </button> <ul id="toc-Power_estimation_techniques_for_RTL-sublist" class="vector-toc-list"> <li id="toc-Motivation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Motivation"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.1</span> <span>Motivation</span> </div> </a> <ul id="toc-Motivation-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Advantages_of_doing_power_estimation_at_RTL_or_architectural_level" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Advantages_of_doing_power_estimation_at_RTL_or_architectural_level"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.2</span> <span>Advantages of doing power estimation at RTL or architectural level</span> </div> </a> <ul id="toc-Advantages_of_doing_power_estimation_at_RTL_or_architectural_level-sublist" class="vector-toc-list"> </ul> </li> <li id="toc-Gate_equivalents[4]" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Gate_equivalents[4]"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3</span> <span>Gate equivalents<sup><span>[</span>4<span>]</span></sup></span> </div> </a> <ul id="toc-Gate_equivalents[4]-sublist" class="vector-toc-list"> <li id="toc-Examples_of_gate_equivalent_technique" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Examples_of_gate_equivalent_technique"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.3.1</span> <span>Examples of gate equivalent technique</span> </div> </a> <ul id="toc-Examples_of_gate_equivalent_technique-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-Precharacterized_cell_libraries" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Precharacterized_cell_libraries"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4</span> <span>Precharacterized cell libraries</span> </div> </a> <ul id="toc-Precharacterized_cell_libraries-sublist" class="vector-toc-list"> <li id="toc-Example" class="vector-toc-list-item vector-toc-level-3"> <a class="vector-toc-link" href="#Example"> <div class="vector-toc-text"> <span class="vector-toc-numb">3.4.1</span> <span>Example</span> </div> </a> <ul id="toc-Example-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> </ul> </li> <li id="toc-See_also" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#See_also"> <div class="vector-toc-text"> <span class="vector-toc-numb">4</span> <span>See also</span> </div> </a> <button aria-controls="toc-See_also-sublist" class="cdx-button cdx-button--weight-quiet cdx-button--icon-only vector-toc-toggle"> <span class="vector-icon mw-ui-icon-wikimedia-expand"></span> <span>Toggle See also subsection</span> </button> <ul id="toc-See_also-sublist" class="vector-toc-list"> <li id="toc-Power_estimation" class="vector-toc-list-item vector-toc-level-2"> <a class="vector-toc-link" href="#Power_estimation"> <div class="vector-toc-text"> <span class="vector-toc-numb">4.1</span> <span>Power estimation</span> </div> </a> <ul id="toc-Power_estimation-sublist" class="vector-toc-list"> </ul> </li> </ul> </li> <li id="toc-References" class="vector-toc-list-item vector-toc-level-1 vector-toc-list-item-expanded"> <a class="vector-toc-link" href="#References"> <div class="vector-toc-text"> <span class="vector-toc-numb">5</span> <span>References</span> </div> </a> <ul id="toc-References-sublist" class="vector-toc-list"> </ul> </li> </ul> </div> </div> </nav> </div> </div> <div class="mw-content-container"> <main id="content" class="mw-body"> <header class="mw-body-header vector-page-titlebar"> <nav aria-label="Contents" class="vector-toc-landmark"> <div id="vector-page-titlebar-toc" class="vector-dropdown vector-page-titlebar-toc vector-button-flush-left" title="Table of Contents" > <input type="checkbox" id="vector-page-titlebar-toc-checkbox" role="button" aria-haspopup="true" data-event-name="ui.dropdown-vector-page-titlebar-toc" class="vector-dropdown-checkbox " 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interwiki-de mw-list-item"><a href="https://de.wikipedia.org/wiki/Registertransferebene" title="Registertransferebene – German" lang="de" hreflang="de" data-title="Registertransferebene" data-language-autonym="Deutsch" data-language-local-name="German" class="interlanguage-link-target"><span>Deutsch</span></a></li><li class="interlanguage-link interwiki-fa mw-list-item"><a href="https://fa.wikipedia.org/wiki/%D8%B3%D8%B7%D8%AD_%D8%A7%D9%86%D8%AA%D9%82%D8%A7%D9%84-%D8%AB%D8%A8%D8%A7%D8%AA" title="سطح انتقال-ثبات – Persian" lang="fa" hreflang="fa" data-title="سطح انتقال-ثبات" data-language-autonym="فارسی" data-language-local-name="Persian" class="interlanguage-link-target"><span>فارسی</span></a></li><li class="interlanguage-link interwiki-fr mw-list-item"><a href="https://fr.wikipedia.org/wiki/Register_Transfer_Level" title="Register Transfer Level – French" lang="fr" hreflang="fr" data-title="Register Transfer Level" data-language-autonym="Français" data-language-local-name="French" class="interlanguage-link-target"><span>Français</span></a></li><li class="interlanguage-link interwiki-ko mw-list-item"><a href="https://ko.wikipedia.org/wiki/%EB%A0%88%EC%A7%80%EC%8A%A4%ED%84%B0_%EC%A0%84%EC%86%A1_%EC%88%98%EC%A4%80" title="레지스터 전송 수준 – Korean" lang="ko" hreflang="ko" data-title="레지스터 전송 수준" data-language-autonym="한국어" data-language-local-name="Korean" class="interlanguage-link-target"><span>한국어</span></a></li><li class="interlanguage-link interwiki-it mw-list-item"><a href="https://it.wikipedia.org/wiki/Register_transfer_level" title="Register transfer level – Italian" lang="it" hreflang="it" data-title="Register transfer level" data-language-autonym="Italiano" data-language-local-name="Italian" class="interlanguage-link-target"><span>Italiano</span></a></li><li class="interlanguage-link interwiki-ja mw-list-item"><a href="https://ja.wikipedia.org/wiki/%E3%83%AC%E3%82%B8%E3%82%B9%E3%82%BF%E8%BB%A2%E9%80%81%E3%83%AC%E3%83%99%E3%83%AB" title="レジスタ転送レベル – Japanese" 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print{body.ns-0 .mw-parser-output .ambox{display:none!important}}</style><table class="box-More_citations_needed plainlinks metadata ambox ambox-content ambox-Refimprove" role="presentation"><tbody><tr><td class="mbox-image"><div class="mbox-image-div"><span typeof="mw:File"><a href="/wiki/File:Question_book-new.svg" class="mw-file-description"><img alt="" src="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/50px-Question_book-new.svg.png" decoding="async" width="50" height="39" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/75px-Question_book-new.svg.png 1.5x, //upload.wikimedia.org/wikipedia/en/thumb/9/99/Question_book-new.svg/100px-Question_book-new.svg.png 2x" data-file-width="512" data-file-height="399" /></a></span></div></td><td class="mbox-text"><div class="mbox-text-span">This article <b>needs additional citations for <a href="/wiki/Wikipedia:Verifiability" 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Unsourced material may be challenged and removed.<br /><small><span class="plainlinks"><i>Find sources:</i> <a rel="nofollow" class="external text" href="https://www.google.com/search?as_eq=wikipedia&q=%22Register-transfer+level%22">"Register-transfer level"</a> – <a rel="nofollow" class="external text" href="https://www.google.com/search?tbm=nws&q=%22Register-transfer+level%22+-wikipedia&tbs=ar:1">news</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?&q=%22Register-transfer+level%22&tbs=bkt:s&tbm=bks">newspapers</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.google.com/search?tbs=bks:1&q=%22Register-transfer+level%22+-wikipedia">books</a> <b>·</b> <a rel="nofollow" class="external text" href="https://scholar.google.com/scholar?q=%22Register-transfer+level%22">scholar</a> <b>·</b> <a rel="nofollow" class="external text" href="https://www.jstor.org/action/doBasicSearch?Query=%22Register-transfer+level%22&acc=on&wc=on">JSTOR</a></span></small></span> <span class="date-container"><i>(<span class="date">December 2009</span>)</i></span><span class="hide-when-compact"><i> (<small><a href="/wiki/Help:Maintenance_template_removal" title="Help:Maintenance template removal">Learn how and when to remove this message</a></small>)</i></span></div></td></tr></tbody></table> <p>In <a href="/wiki/Digital_circuit_design" class="mw-redirect" title="Digital circuit design">digital circuit design</a>, <b>register-transfer level</b> (<b>RTL</b>) is a design abstraction which models a <a href="/wiki/Synchronous_circuit" title="Synchronous circuit">synchronous</a> <a href="/wiki/Digital_circuit" class="mw-redirect" title="Digital circuit">digital circuit</a> in terms of the flow of digital signals (<a href="/wiki/Data" title="Data">data</a>) between <a href="/wiki/Hardware_register" title="Hardware register">hardware registers</a>, and the <a href="/wiki/Boolean_logic" class="mw-redirect" title="Boolean logic">logical operations</a> performed on those signals. </p><p>Register-transfer-level abstraction is used in <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description languages</a> (HDLs) like <a href="/wiki/Verilog" title="Verilog">Verilog</a> and <a href="/wiki/VHDL" title="VHDL">VHDL</a> to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.<sup id="cite_ref-1" class="reference"><a href="#cite_note-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> </p><p>Unlike in software compiler design, where the register-transfer level is an intermediate representation and at the lowest level, the RTL level is the usual input that circuit designers operate on. In fact, in circuit synthesis, an intermediate language between the input register transfer level representation and the target <a href="/wiki/Netlist" title="Netlist">netlist</a> is sometimes used. Unlike in netlist, constructs such as cells, functions, and multi-bit registers are available.<sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> Examples include FIRRTL and RTLIL. </p><p><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a> is a higher level of <a href="/wiki/Electronic_design_automation" title="Electronic design automation">electronic system design</a>. </p> <meta property="mw:PageProp/toc" /> <div class="mw-heading mw-heading2"><h2 id="RTL_description">RTL description</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=1" title="Edit section: RTL description"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <figure class="mw-halign-right" typeof="mw:File/Thumb"><a href="/wiki/File:Register_transfer_level_-_example_toggler.svg" class="mw-file-description"><img src="//upload.wikimedia.org/wikipedia/commons/thumb/0/01/Register_transfer_level_-_example_toggler.svg/300px-Register_transfer_level_-_example_toggler.svg.png" decoding="async" width="300" height="200" class="mw-file-element" srcset="//upload.wikimedia.org/wikipedia/commons/thumb/0/01/Register_transfer_level_-_example_toggler.svg/450px-Register_transfer_level_-_example_toggler.svg.png 1.5x, //upload.wikimedia.org/wikipedia/commons/thumb/0/01/Register_transfer_level_-_example_toggler.svg/600px-Register_transfer_level_-_example_toggler.svg.png 2x" data-file-width="300" data-file-height="200" /></a><figcaption>Example of a simple circuit with the output toggling at each rising edge of the input. The inverter forms the combinational logic in this circuit, and the register holds the state.</figcaption></figure> <p>A synchronous circuit consists of two kinds of elements: registers (sequential logic) and <a href="/wiki/Combinational_logic" title="Combinational logic">combinational logic</a>. Registers (usually implemented as <a href="/wiki/Flip-flop_(electronics)#D_flip-flop" title="Flip-flop (electronics)">D flip-flops</a>) synchronize the circuit's operation to the edges of the clock signal, and are the only elements in the circuit that have memory properties. Combinational logic performs all the logical functions in the circuit and it typically consists of <a href="/wiki/Logic_gate" title="Logic gate">logic gates</a>. </p><p>For example, a very simple synchronous circuit is shown in the figure. The <a href="/wiki/Inverter_(logic_gate)" title="Inverter (logic gate)">inverter</a> is connected from the output, Q, of a register to the register's input, D, to create a circuit that changes its state on each rising edge of the clock, clk. In this circuit, the combinational logic consists of the inverter. </p><p>When designing digital integrated circuits with a <a href="/wiki/Hardware_description_language" title="Hardware description language">hardware description language</a> (HDL), the designs are usually engineered at a higher level of abstraction than transistor level (<a href="/wiki/Logic_family" title="Logic family">logic families</a>) or logic gate level. In HDLs the designer declares the registers (which roughly correspond to variables in computer programming languages), and describes the combinational logic by using constructs that are familiar from programming languages such as if-then-else and arithmetic operations. This level is called <i>register-transfer level</i>. The term refers to the fact that RTL focuses on describing the flow of signals between registers. </p><p>As an example, the circuit mentioned above can be described in VHDL as follows: </p> <div class="mw-highlight mw-highlight-lang-vhdl mw-content-ltr" dir="ltr"><pre><span></span><span class="n">D</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="k">not</span><span class="w"> </span><span class="n">Q</span><span class="p">;</span> <span class="w"> </span> <span class="k">process</span><span class="p">(</span><span class="n">clk</span><span class="p">)</span> <span class="k">begin</span> <span class="w"> </span><span class="k">if</span><span class="w"> </span><span class="n">rising_edge</span><span class="p">(</span><span class="n">clk</span><span class="p">)</span><span class="w"> </span><span class="k">then</span> <span class="w"> </span><span class="n">Q</span><span class="w"> </span><span class="o"><=</span><span class="w"> </span><span class="n">D</span><span class="p">;</span> <span class="w"> </span><span class="k">end</span><span class="w"> </span><span class="k">if</span><span class="p">;</span> <span class="k">end</span><span class="w"> </span><span class="k">process</span><span class="p">;</span> </pre></div> <p>Using an <a href="/wiki/Electronic_design_automation" title="Electronic design automation">EDA</a> tool for synthesis, this description can usually be directly translated to an equivalent hardware implementation file for an <a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">ASIC</a> or an <a href="/wiki/FPGA" class="mw-redirect" title="FPGA">FPGA</a>. The <a href="/wiki/Logic_synthesis" title="Logic synthesis">synthesis</a> tool also performs <a href="/wiki/Logic_optimization" title="Logic optimization">logic optimization</a>. </p><p>At the register-transfer level, some types of circuits can be recognized. If there is a cyclic path of logic from a register's output to its input (or from a set of registers outputs to its inputs), the circuit is called a <a href="/wiki/Finite-state_machine" title="Finite-state machine">state machine</a> or can be said to be <a href="/wiki/Sequential_logic" title="Sequential logic">sequential logic</a>. If there are logic paths from a register to another without a cycle, it is called a <a href="/wiki/Pipeline_(computing)" title="Pipeline (computing)">pipeline</a>. </p> <div class="mw-heading mw-heading2"><h2 id="RTL_in_the_circuit_design_cycle">RTL in the circuit design cycle</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=2" title="Edit section: RTL in the circuit design cycle"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>RTL is used in the <a href="/wiki/Digital_logic" class="mw-redirect" title="Digital logic">logic design</a> phase of the <a href="/wiki/Integrated_circuit_design" title="Integrated circuit design">integrated circuit design</a> cycle. </p><p>An RTL description is usually converted to a <a href="/wiki/Netlist" title="Netlist">gate-level description</a> of the circuit by a <a href="/wiki/Logic_synthesis" title="Logic synthesis">logic synthesis</a> <a href="/wiki/Software_tool" class="mw-redirect" title="Software tool">tool</a>. The synthesis results are then used by <a href="/wiki/Placement_(EDA)" class="mw-redirect" title="Placement (EDA)">placement</a> and <a href="/wiki/Routing_(EDA)" class="mw-redirect" title="Routing (EDA)">routing</a> tools to create a physical <a href="/wiki/Integrated_circuit" title="Integrated circuit">layout</a>. </p><p><a href="/wiki/Logic_simulation" title="Logic simulation">Logic simulation</a> tools may use a design's RTL description to verify its correctness. </p> <div class="mw-heading mw-heading2"><h2 id="Power_estimation_techniques_for_RTL">Power estimation techniques for RTL</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=3" title="Edit section: Power estimation techniques for RTL"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>The most accurate power analysis tools are available for the circuit level but unfortunately, even with switch- rather than device-level modelling, tools at the circuit level have disadvantages like they are either too slow or require too much memory thus inhibiting large chip handling. The majority of these are simulators like <a href="/wiki/SPICE" title="SPICE">SPICE</a> and have been used by the designers for many years as performance analysis tools. Due to these disadvantages, gate-level power estimation tools have begun to gain some acceptance where faster, probabilistic techniques have begun to gain a foothold. But it also has its trade off as speedup is achieved on the cost of accuracy, especially in the presence of correlated signals. Over the years it has been realized that biggest wins in low power design cannot come from circuit- and gate-level optimizations whereas architecture, system, and algorithm optimizations tend to have the largest impact on power consumption. Therefore, there has been a shift in the incline of the tool developers towards high-level analysis and optimization tools for power. </p> <div class="mw-heading mw-heading3"><h3 id="Motivation">Motivation</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=4" title="Edit section: Motivation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>It is well known that more significant power reductions are possible if optimizations are made on levels of abstraction, like the architectural and algorithmic level, which are higher than the circuit or gate level <sup id="cite_ref-3" class="reference"><a href="#cite_note-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> This provides the required motivation for the developers to focus on the development of new architectural level power analysis tools. This in no way implies that lower level tools are unimportant. Instead, each layer of tools provides a foundation upon which the next level can be built. The abstractions of the estimation techniques at a lower level can be used on a higher level with slight modifications. </p> <div class="mw-heading mw-heading3"><h3 id="Advantages_of_doing_power_estimation_at_RTL_or_architectural_level">Advantages of doing power estimation at RTL or architectural level</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=5" title="Edit section: Advantages of doing power estimation at RTL or architectural level"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li>Designers use a register-transfer level (RTL) description of the design to make optimizations and trade-offs very early in the design flow.</li> <li>The presence of functional blocks in an RTL description makes the complexity of architectural design much more manageable even for large chips because RTL has granularity sufficiently larger than gate- or circuit-level descriptions.</li></ul> <div class="mw-heading mw-heading3"><h3 id="Gate_equivalents[4]"><span id="Gate_equivalents.5B4.5D"></span>Gate equivalents<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup></h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=6" title="Edit section: Gate equivalents[4]"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>It is a technique based on the concept of gate equivalents. The complexity of a chip architecture can be described approximately in terms of gate equivalents where <a href="/wiki/Gate_equivalent" title="Gate equivalent">gate equivalent</a> count specifies the average number of reference gates that are required to implement the particular function. The total power required for the particular function is estimated by multiplying the approximated number of gate equivalents with the average power consumed per gate. The reference gate can be any gate e.g. 2-input NAND gate. </p> <div class="mw-heading mw-heading4"><h4 id="Examples_of_gate_equivalent_technique">Examples of gate equivalent technique</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=7" title="Edit section: Examples of gate equivalent technique"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><b>Class-independent power modeling:</b> It is a technique which tries to estimate chip area, speed, and power dissipation based on information about the complexity of the design in terms of gate equivalents. The functionality is divided among different blocks but no distinction is made about the functionality of the blocks i.e. it is basically class independent. This is the technique used by the <i>chip estimation system</i> (CES).</li></ul> <dl><dd><dl><dd><b>Steps:</b> <ol><li>Identify the functional blocks such as counters, decoders, multipliers, memories, etc.</li> <li>Assign a complexity in terms of gate equivalents. The number of GE’s for each unit type are either taken directly as an input from the user or are fed from a library.</li></ol></dd></dl></dd></dl> <div style="text-align: center"> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \displaystyle P=\sum _{i\in {\text{fns}}}{\textit {GE}}_{i}(E_{\text{typ}}+C_{L}^{i}V_{\text{dd}}^{2})fA_{\text{int}}^{i}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mstyle displaystyle="true" scriptlevel="0"> <mi>P</mi> <mo>=</mo> <munder> <mo>∑</mo> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> <mo>∈</mo> <mrow class="MJX-TeXAtom-ORD"> <mtext>fns</mtext> </mrow> </mrow> </munder> <msub> <mrow class="MJX-TeXAtom-ORD"> <mrow class="MJX-TeXAtom-ORD"> <mtext class="MJX-tex-mathit" mathvariant="italic">GE</mtext> </mrow> </mrow> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> <mo stretchy="false">(</mo> <msub> <mi>E</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>typ</mtext> </mrow> </msub> <mo>+</mo> <msubsup> <mi>C</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>L</mi> </mrow> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msubsup> <msubsup> <mi>V</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>dd</mtext> </mrow> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msubsup> <mo stretchy="false">)</mo> <mi>f</mi> <msubsup> <mi>A</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>int</mtext> </mrow> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msubsup> </mstyle> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \displaystyle P=\sum _{i\in {\text{fns}}}{\textit {GE}}_{i}(E_{\text{typ}}+C_{L}^{i}V_{\text{dd}}^{2})fA_{\text{int}}^{i}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/428cb378aa17d457277340f1f3bcfca1c1ad0a80" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -3.171ex; width:33.847ex; height:5.676ex;" alt="{\displaystyle \displaystyle P=\sum _{i\in {\text{fns}}}{\textit {GE}}_{i}(E_{\text{typ}}+C_{L}^{i}V_{\text{dd}}^{2})fA_{\text{int}}^{i}}"></span></dd></dl> </div> <dl><dd><dl><dd>Where E<sub>typ</sub> is the assumed average dissipated energy by a gate equivalent, when active. The activity factor, A<sub>int</sub>, denotes the average percentage of gates switching per clock cycle and is allowed to vary from function to function. The capacitive load, C<sub>L</sub>, is a combination of fan-out loading as well as wiring. An estimate of the average wire length can be used to calculate the wiring capacitance. This is provided by the user and cross-checked by using a derivative of <a href="/wiki/Rent%27s_rule" title="Rent's rule">Rent’s rule</a>.</dd></dl></dd></dl> <dl><dd><dl><dd><b>Assumptions:</b> <ol><li>A single reference gate is taken as the basis for all the power estimates not taking into consideration different circuit styles, clocking strategies, or layout techniques.</li> <li>The percentage of gates switching per clock cycle denoted by activity factors are assumed to be fixed regardless of the input patterns.</li> <li>Typical gate switching energy is characterized by completely random uniform <a href="/wiki/White_noise" title="White noise">white noise</a> (UWN) distribution of the input data. This implies that the power estimation is same regardless of the circuit being idle or at maximum load as this UWN model ignores how different input distributions affect the power consumption of gates and modules.<sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup></li></ol></dd></dl></dd></dl> <ul><li><b>Class-dependent power modeling:</b> This approach is slightly better than the previous approach as it takes into account customized estimation techniques to the different types of functional blocks thus trying to increase the modelling accuracy which wasn’t the case in the previous technique such as logic, memory, interconnect, and clock hence the name. The power estimation is done in a very similar manner to the independent case. The basic switching energy is based on a three-input AND gate and is calculated from technology parameters e.g. gate width, tox, and metal width provided by the user.</li></ul> <div style="text-align: center"> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle P_{\text{bitlines}}={\dfrac {N_{\text{col}}}{2}}\cdot (L_{\text{col}}C_{\text{wire}}+N_{\text{row}}C_{\text{cell}})V_{\text{dd}}V_{\text{swing}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>P</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>bitlines</mtext> </mrow> </msub> <mo>=</mo> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mfrac> <msub> <mi>N</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>col</mtext> </mrow> </msub> <mn>2</mn> </mfrac> </mstyle> </mrow> <mo>⋅</mo> <mo stretchy="false">(</mo> <msub> <mi>L</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>col</mtext> </mrow> </msub> <msub> <mi>C</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>wire</mtext> </mrow> </msub> <mo>+</mo> <msub> <mi>N</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>row</mtext> </mrow> </msub> <msub> <mi>C</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>cell</mtext> </mrow> </msub> <mo stretchy="false">)</mo> <msub> <mi>V</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>dd</mtext> </mrow> </msub> <msub> <mi>V</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>swing</mtext> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle P_{\text{bitlines}}={\dfrac {N_{\text{col}}}{2}}\cdot (L_{\text{col}}C_{\text{wire}}+N_{\text{row}}C_{\text{cell}})V_{\text{dd}}V_{\text{swing}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/3aaee2f7713175b8ad860b687edd00ff7be002b6" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -1.838ex; width:48.102ex; height:5.176ex;" alt="{\displaystyle P_{\text{bitlines}}={\dfrac {N_{\text{col}}}{2}}\cdot (L_{\text{col}}C_{\text{wire}}+N_{\text{row}}C_{\text{cell}})V_{\text{dd}}V_{\text{swing}}}"></span></dd></dl> </div> <dl><dd><dl><dd>Where C<sub>wire</sub> denotes the bit line wiring capacitance per unit length and C<sub>cell</sub> denotes the loading due to a single cell hanging off the bit line. The clock capacitance is based on the assumption of an <a href="/wiki/H-tree" class="mw-redirect" title="H-tree">H-tree</a> distribution network. Activity is modelled using a UWN model. As can be seen by the equation the power consumption of each components is related to the number of columns (N<sub>col</sub>) and rows (N<sub>row</sub>) in the memory array.</dd></dl></dd></dl> <dl><dd><dl><dd><b>Disadvantages:</b> <ol><li>The circuit activities are not modeled accurately as an overall activity factor is assumed for the entire chip which is also not trustable as provided by the user. As a matter of fact activity factors will vary throughout the chip hence this is not very accurate and prone to error. This leads to the problem that even if the model gives a correct estimate for the total power consumption by the chip, the module wise power distribution is fairly inaccurate.</li> <li>The chosen activity factor gives the correct total power, but the breakdown of power into logic, clock, memory, etc. is less accurate. Therefore this tool is not much different or improved in comparison with CES.</li></ol></dd></dl></dd></dl> <div class="mw-heading mw-heading3"><h3 id="Precharacterized_cell_libraries">Precharacterized cell libraries</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=8" title="Edit section: Precharacterized cell libraries"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>This technique further customizes the power estimation of various functional blocks by having separate power model for logic, memory, and interconnect suggesting a <a href="/wiki/Power_factor" title="Power factor">power factor</a> approximation (PFA) method for individually characterizing an entire library of functional blocks such as multipliers, adders, etc. instead of a single gate-equivalent model for “logic” blocks. <br /> The power over the entire chip is approximated by the expression: </p> <div style="text-align: center"> <dl><dd><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \displaystyle P=\sum _{i\in {\text{all blocks}}}K_{i}G_{i}f_{i}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mstyle displaystyle="true" scriptlevel="0"> <mi>P</mi> <mo>=</mo> <munder> <mo>∑</mo> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> <mo>∈</mo> <mrow class="MJX-TeXAtom-ORD"> <mtext>all blocks</mtext> </mrow> </mrow> </munder> <msub> <mi>K</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> <msub> <mi>G</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> <msub> <mi>f</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> </mstyle> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \displaystyle P=\sum _{i\in {\text{all blocks}}}K_{i}G_{i}f_{i}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/fd5b584e2858048e5fd00d6dfc51184c38576ea9" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -3.171ex; width:20.989ex; height:5.676ex;" alt="{\displaystyle \displaystyle P=\sum _{i\in {\text{all blocks}}}K_{i}G_{i}f_{i}}"></span></dd></dl> </div> <p>Where K<sub>i</sub> is PFA proportionality constant that characterizes the i<sub>th</sub> functional element <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle G_{i}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>G</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle G_{i}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/0dd9fe8d455762608cc4e0a946b452492790ee5f" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:2.626ex; height:2.509ex;" alt="{\displaystyle G_{i}}"></span> is the measure of hardware complexity, and <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle f_{i}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>f</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>i</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle f_{i}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/65da883ca3d16b461e46c94777b0d9c4aa010e79" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:1.939ex; height:2.509ex;" alt="{\displaystyle f_{i}}"></span> denotes the activation frequency. </p> <div class="mw-heading mw-heading4"><h4 id="Example">Example</h4><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=9" title="Edit section: Example"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <p>G<sub>i</sub> denoting the hardware complexity of the multiplier is related to the square of the input word length i.e. N<sup>2</sup> where N is the word length. The activation frequency is the rate at which multiplies are performed by the algorithm denoted by <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle f_{mult}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>f</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>m</mi> <mi>u</mi> <mi>l</mi> <mi>t</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle f_{mult}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/a5570b3eb664598e52ee11e9a01ce1469c60a478" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:4.838ex; height:2.509ex;" alt="{\displaystyle f_{mult}}"></span> and the PFA constant, <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle K_{mult}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>K</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>m</mi> <mi>u</mi> <mi>l</mi> <mi>t</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle K_{mult}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/50b7e8e3993d57ed1f3274947a3dc328f4946a78" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:5.672ex; height:2.509ex;" alt="{\displaystyle K_{mult}}"></span>, is extracted empirically from past multiplier designs and shown to be about 15 fW/bit2-Hz for a 1.2 μm technology at 5V. The resulting power model for the multiplier on the basis of the above assumptions is:<br /> </p> <div style="text-align: center;"> <p><span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle \displaystyle P_{\text{mult}}=K_{\text{mult}}N^{2}f_{\text{mult}}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>P</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>mult</mtext> </mrow> </msub> <mo>=</mo> <msub> <mi>K</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>mult</mtext> </mrow> </msub> <msup> <mi>N</mi> <mrow class="MJX-TeXAtom-ORD"> <mn>2</mn> </mrow> </msup> <msub> <mi>f</mi> <mrow class="MJX-TeXAtom-ORD"> <mtext>mult</mtext> </mrow> </msub> </mstyle> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle \displaystyle P_{\text{mult}}=K_{\text{mult}}N^{2}f_{\text{mult}}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/f9c2d792d2abbdf3d33a2275a14eef4d8e62d82f" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:21.717ex; height:3.009ex;" alt="{\displaystyle \displaystyle P_{\text{mult}}=K_{\text{mult}}N^{2}f_{\text{mult}}}"></span> </p> </div> <p><b>Advantages:</b> </p> <ul><li>Customization is possible in terms of whatever complexity parameters which are appropriate for that block. E.g. for a multiplier the square of the word length was appropriate. For memory, the storage capacity in bits is used and for the I/O drivers the word length alone is adequate.</li></ul> <p><b>Weakness:</b> </p> <ul><li>There is the implicit assumption that the inputs do not affect the multiplier activity which is contradictory to the fact that the PFA constant <span class="mwe-math-element"><span class="mwe-math-mathml-inline mwe-math-mathml-a11y" style="display: none;"><math xmlns="http://www.w3.org/1998/Math/MathML" alttext="{\displaystyle K_{mult}}"> <semantics> <mrow class="MJX-TeXAtom-ORD"> <mstyle displaystyle="true" scriptlevel="0"> <msub> <mi>K</mi> <mrow class="MJX-TeXAtom-ORD"> <mi>m</mi> <mi>u</mi> <mi>l</mi> <mi>t</mi> </mrow> </msub> </mstyle> </mrow> <annotation encoding="application/x-tex">{\displaystyle K_{mult}}</annotation> </semantics> </math></span><img src="https://wikimedia.org/api/rest_v1/media/math/render/svg/50b7e8e3993d57ed1f3274947a3dc328f4946a78" class="mwe-math-fallback-image-inline mw-invert skin-invert" aria-hidden="true" style="vertical-align: -0.671ex; width:5.672ex; height:2.509ex;" alt="{\displaystyle K_{mult}}"></span> is intended to capture the intrinsic internal activity associated with the multiply operation as it is taken to be a constant.</li></ul> <p>The estimation error (relative to switch-level simulation) for a 16x16 multiplier is experimented and it is observed that when the dynamic range of the inputs does not fully occupy the word length of the multiplier, the UWN model becomes extremely inaccurate.<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> Granted, good designers attempt to maximize word length utilization. Still, errors in the range of 50-100% are not uncommon. The figure clearly suggests a flaw in the UWN model. </p> <div class="mw-heading mw-heading2"><h2 id="See_also">See also</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=10" title="Edit section: See also"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Datapath" title="Datapath">Datapath</a></li> <li><a href="/wiki/Electronic_design_automation" title="Electronic design automation">Electronic design automation</a> (EDA)</li> <li><a href="/wiki/Electronic_system-level" class="mw-redirect" title="Electronic system-level">Electronic system-level</a></li> <li><a href="/wiki/Finite-state_machine_with_datapath" class="mw-redirect" title="Finite-state machine with datapath">Finite-state machine with datapath</a></li> <li><a href="/wiki/Integrated_circuit_design" title="Integrated circuit design">Integrated circuit design</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous circuit</a></li> <li><a href="/wiki/Algorithmic_state_machine" title="Algorithmic state machine">Algorithmic state machine</a></li></ul> <div class="mw-heading mw-heading3"><h3 id="Power_estimation">Power estimation</h3><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=11" title="Edit section: Power estimation"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <ul><li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li> <li><a href="/wiki/Power_optimization_(EDA)" title="Power optimization (EDA)">Power optimization (EDA)</a></li> <li><a href="/wiki/Gaussian_noise" title="Gaussian noise">Gaussian noise</a></li></ul> <div class="mw-heading mw-heading2"><h2 id="References">References</h2><span class="mw-editsection"><span class="mw-editsection-bracket">[</span><a href="/w/index.php?title=Register-transfer_level&action=edit&section=12" title="Edit section: References"><span>edit</span></a><span class="mw-editsection-bracket">]</span></span></div> <style data-mw-deduplicate="TemplateStyles:r1239543626">.mw-parser-output .reflist{margin-bottom:0.5em;list-style-type:decimal}@media screen{.mw-parser-output .reflist{font-size:90%}}.mw-parser-output .reflist .references{font-size:100%;margin-bottom:0;list-style-type:inherit}.mw-parser-output .reflist-columns-2{column-width:30em}.mw-parser-output .reflist-columns-3{column-width:25em}.mw-parser-output .reflist-columns{margin-top:0.3em}.mw-parser-output .reflist-columns ol{margin-top:0}.mw-parser-output .reflist-columns li{page-break-inside:avoid;break-inside:avoid-column}.mw-parser-output .reflist-upper-alpha{list-style-type:upper-alpha}.mw-parser-output .reflist-upper-roman{list-style-type:upper-roman}.mw-parser-output .reflist-lower-alpha{list-style-type:lower-alpha}.mw-parser-output .reflist-lower-greek{list-style-type:lower-greek}.mw-parser-output .reflist-lower-roman{list-style-type:lower-roman}</style><div class="reflist"> <div class="mw-references-wrap"><ol class="references"> <li id="cite_note-1"><span class="mw-cite-backlink"><b><a href="#cite_ref-1">^</a></b></span> <span class="reference-text"> <style data-mw-deduplicate="TemplateStyles:r1238218222">.mw-parser-output cite.citation{font-style:inherit;word-wrap:break-word}.mw-parser-output .citation q{quotes:"\"""\"""'""'"}.mw-parser-output .citation:target{background-color:rgba(0,127,255,0.133)}.mw-parser-output .id-lock-free.id-lock-free a{background:url("//upload.wikimedia.org/wikipedia/commons/6/65/Lock-green.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-limited.id-lock-limited a,.mw-parser-output .id-lock-registration.id-lock-registration a{background:url("//upload.wikimedia.org/wikipedia/commons/d/d6/Lock-gray-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .id-lock-subscription.id-lock-subscription a{background:url("//upload.wikimedia.org/wikipedia/commons/a/aa/Lock-red-alt-2.svg")right 0.1em center/9px no-repeat}.mw-parser-output .cs1-ws-icon a{background:url("//upload.wikimedia.org/wikipedia/commons/4/4c/Wikisource-logo.svg")right 0.1em center/12px no-repeat}body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-free a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-limited a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-registration a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .id-lock-subscription a,body:not(.skin-timeless):not(.skin-minerva) .mw-parser-output .cs1-ws-icon a{background-size:contain;padding:0 1em 0 0}.mw-parser-output .cs1-code{color:inherit;background:inherit;border:none;padding:inherit}.mw-parser-output .cs1-hidden-error{display:none;color:var(--color-error,#d33)}.mw-parser-output .cs1-visible-error{color:var(--color-error,#d33)}.mw-parser-output .cs1-maint{display:none;color:#085;margin-left:0.3em}.mw-parser-output .cs1-kern-left{padding-left:0.2em}.mw-parser-output .cs1-kern-right{padding-right:0.2em}.mw-parser-output .citation .mw-selflink{font-weight:inherit}@media screen{.mw-parser-output .cs1-format{font-size:95%}html.skin-theme-clientpref-night .mw-parser-output .cs1-maint{color:#18911f}}@media screen and (prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .cs1-maint{color:#18911f}}</style><cite id="CITEREFFrank_Vahid2010" class="citation book cs1">Frank Vahid (2010). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=-YayRpmjc20C&pg=PA247"><i>Digital Design with RTL Design, Verilog and VHDL</i></a> (2nd ed.). John Wiley and Sons. p. 247. <a href="/wiki/ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <a href="/wiki/Special:BookSources/978-0-470-53108-2" title="Special:BookSources/978-0-470-53108-2"><bdi>978-0-470-53108-2</bdi></a>.</cite><span title="ctx_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=book&rft.btitle=Digital+Design+with+RTL+Design%2C+Verilog+and+VHDL&rft.pages=247&rft.edition=2nd&rft.pub=John+Wiley+and+Sons&rft.date=2010&rft.isbn=978-0-470-53108-2&rft.au=Frank+Vahid&rft_id=https%3A%2F%2Fbooks.google.com%2Fbooks%3Fid%3D-YayRpmjc20C%26pg%3DPA247&rfr_id=info%3Asid%2Fen.wikipedia.org%3ARegister-transfer+level" class="Z3988"></span></span> </li> <li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="https://yosys.readthedocs.io/_/downloads/en/latest/pdf/">Yosys Manual</a> (RTLIL)</span> </li> <li id="cite_note-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-3">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.eecg.toronto.edu/~najm/papers/iccad95-tutorial.pdf">"Power Estimation Techniques for Integrated Circuits "</a></span> </li> <li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.61.4551&rep=rep1&type=pdf">"Low-Power Architectural Design Methodologies "</a></span> </li> <li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://delivery.acm.org/10.1145/250000/244548/p158-raghunathan.pdf?ip=103.27.8.42&id=244548&acc=ACTIVE%20SERVICE&key=045416EF4DDA69D9%2EF8E7F338DF557316%2E4D4702B0C3E38B35%2E4D4702B0C3E38B35&CFID=504808115&CFTOKEN=79046804&__acm__=1429710434_0d9c0bce018bcd071c079ecb15be69e8">"Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption"</a></span> </li> <li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://delivery.acm.org/10.1145/270000/266171/p365-gupta.pdf?ip=103.27.8.42&id=266171&acc=ACTIVE%20SERVICE&key=045416EF4DDA69D9%2EF8E7F338DF557316%2E4D4702B0C3E38B35%2E4D4702B0C3E38B35&CFID=504808115&CFTOKEN=79046804&__acm__=1429710436_686f8f2ffb085b129fe587723a6ee130">"Power Macromodeling for High Level Power Estimation"</a></span> </li> </ol></div></div> <div class="navbox-styles"><style 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abbr{color:var(--color-base)!important}@media(prefers-color-scheme:dark){html.skin-theme-clientpref-os .mw-parser-output .navbar li a abbr{color:var(--color-base)!important}}@media print{.mw-parser-output .navbar{display:none!important}}</style><div class="navbar plainlinks hlist navbar-mini"><ul><li class="nv-view"><a href="/wiki/Template:Digital_electronics" title="Template:Digital electronics"><abbr title="View this template">v</abbr></a></li><li class="nv-talk"><a href="/wiki/Template_talk:Digital_electronics" title="Template talk:Digital electronics"><abbr title="Discuss this template">t</abbr></a></li><li class="nv-edit"><a href="/wiki/Special:EditPage/Template:Digital_electronics" title="Special:EditPage/Template:Digital electronics"><abbr title="Edit this template">e</abbr></a></li></ul></div><div id="Digital_electronics118" style="font-size:114%;margin:0 4em"><a href="/wiki/Digital_electronics" title="Digital electronics">Digital electronics</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronic_component" title="Electronic component">Components</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Transistor" title="Transistor">Transistor</a></li> <li><a href="/wiki/Resistor" title="Resistor">Resistor</a></li> <li><a href="/wiki/Inductor" title="Inductor">Inductor</a></li> <li><a href="/wiki/Capacitor" title="Capacitor">Capacitor</a></li> <li><a href="/wiki/Printed_electronics" title="Printed electronics">Printed electronics</a></li> <li><a href="/wiki/Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li> <li><a href="/wiki/Electronic_circuit" title="Electronic circuit">Electronic circuit</a></li> <li><a href="/wiki/Flip-flop_(electronics)" title="Flip-flop (electronics)">Flip-flop</a></li> <li><a href="/wiki/Memory_cell_(computing)" title="Memory cell (computing)">Memory cell</a></li> <li><a href="/wiki/Combinational_logic" title="Combinational logic">Combinational logic</a></li> <li><a href="/wiki/Sequential_logic" title="Sequential logic">Sequential logic</a></li> <li><a href="/wiki/Logic_gate" title="Logic gate">Logic gate</a></li> <li><a href="/wiki/Boolean_circuit" title="Boolean circuit">Boolean circuit</a></li> <li><a href="/wiki/Integrated_circuit" title="Integrated circuit">Integrated circuit</a> (IC)</li> <li><a href="/wiki/Hybrid_integrated_circuit" title="Hybrid integrated circuit">Hybrid integrated circuit</a> (HIC)</li> <li><a href="/wiki/Mixed-signal_integrated_circuit" title="Mixed-signal integrated circuit">Mixed-signal integrated circuit</a></li> <li><a href="/wiki/Three-dimensional_integrated_circuit" title="Three-dimensional integrated circuit">Three-dimensional integrated circuit</a> (3D IC)</li> <li><a href="/wiki/Emitter-coupled_logic" title="Emitter-coupled logic">Emitter-coupled logic</a> (ECL)</li> <li><a href="/wiki/Erasable_programmable_logic_device" class="mw-redirect" title="Erasable programmable logic device">Erasable programmable logic device</a> (EPLD)</li> <li><a href="/wiki/Macrocell_array" title="Macrocell array">Macrocell array</a></li> <li><a href="/wiki/Programmable_logic_array" title="Programmable logic array">Programmable logic array</a> (PLA)</li> <li><a href="/wiki/Programmable_logic_device" title="Programmable logic device">Programmable logic device</a> (PLD)</li> <li><a href="/wiki/Programmable_Array_Logic" title="Programmable Array Logic">Programmable Array Logic</a> (PAL)</li> <li><a href="/wiki/Generic_Array_Logic" title="Generic Array Logic">Generic Array Logic</a> (GAL)</li> <li><a href="/wiki/Complex_programmable_logic_device" title="Complex programmable logic device">Complex programmable logic device</a> (CPLD)</li> <li><a href="/wiki/Field-programmable_gate_array" title="Field-programmable gate array">Field-programmable gate array</a> (FPGA)</li> <li><a href="/wiki/Field-programmable_object_array" title="Field-programmable object array">Field-programmable object array</a> (FPOA)</li> <li><a href="/wiki/Application-specific_integrated_circuit" title="Application-specific integrated circuit">Application-specific integrated circuit</a> (ASIC)</li> <li><a href="/wiki/Tensor_Processing_Unit" title="Tensor Processing Unit">Tensor Processing Unit</a> (TPU)</li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Theory</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Digital_signal" title="Digital signal">Digital signal</a></li> <li><a href="/wiki/Boolean_algebra" title="Boolean algebra">Boolean algebra</a></li> <li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Logic_in_computer_science" title="Logic in computer science">Logic in computer science</a></li> <li><a href="/wiki/Computer_architecture" title="Computer architecture">Computer architecture</a></li> <li><a href="/wiki/Digital_signal_(signal_processing)" title="Digital signal (signal processing)">Digital signal</a> <ul><li><a href="/wiki/Digital_signal_processing" title="Digital signal processing">Digital signal processing</a></li></ul></li> <li><a href="/wiki/Circuit_minimization_for_Boolean_functions" class="mw-redirect" title="Circuit minimization for Boolean functions">Circuit minimization</a></li> <li><a href="/wiki/Switching_circuit_theory" title="Switching circuit theory">Switching circuit theory</a></li> <li><a href="/wiki/Gate_equivalent" title="Gate equivalent">Gate equivalent</a></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;"><a href="/wiki/Electronics_design" class="mw-redirect" title="Electronics design">Design</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Logic_synthesis" title="Logic synthesis">Logic synthesis</a></li> <li><a href="/wiki/Place_and_route" title="Place and route">Place and route</a> <ul><li><a href="/wiki/Placement_(electronic_design_automation)" title="Placement (electronic design automation)">Placement</a></li> <li><a href="/wiki/Routing_(electronic_design_automation)" title="Routing (electronic design automation)">Routing</a></li></ul></li> <li><a href="/wiki/Transaction-level_modeling" title="Transaction-level modeling">Transaction-level modeling</a></li> <li><a class="mw-selflink selflink">Register-transfer level</a> <ul><li><a href="/wiki/Hardware_description_language" title="Hardware description language">Hardware description language</a></li> <li><a href="/wiki/High-level_synthesis" title="High-level synthesis">High-level synthesis</a></li></ul></li> <li><a href="/wiki/Formal_equivalence_checking" title="Formal equivalence checking">Formal equivalence checking</a></li> <li><a href="/wiki/Synchronous_circuit" title="Synchronous circuit">Synchronous logic</a></li> <li><a href="/wiki/Asynchronous_circuit" title="Asynchronous circuit">Asynchronous logic</a></li> <li><a href="/wiki/Finite-state_machine" title="Finite-state machine">Finite-state machine</a> <ul><li><a href="/wiki/Hierarchical_state_machine" class="mw-redirect" title="Hierarchical state machine">Hierarchical state machine</a></li></ul></li></ul> </div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:center;">Applications</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"> <ul><li><a href="/wiki/Computer_hardware" title="Computer hardware">Computer hardware</a> <ul><li><a href="/wiki/Hardware_acceleration" title="Hardware acceleration">Hardware acceleration</a></li></ul></li> <li><a href="/wiki/Digital_audio" title="Digital audio">Digital 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