Higher-Order Time Sharing Masking | IACR Transactions on Cryptographic Hardware and Embedded Systems

<!DOCTYPE html> <html lang="en" xml:lang="en"> <head> <meta charset="utf-8"> <meta name="viewport" content="width=device-width, initial-scale=1.0"> <title> Higher-Order Time Sharing Masking | IACR Transactions on Cryptographic Hardware and Embedded Systems </title> <meta name="generator" content="Open Journal Systems 3.4.0.5"> <link rel="schema.DC" href="http://purl.org/dc/elements/1.1/" /> <meta name="DC.Creator.PersonalName" content="Dilip Kumar S. V."/> <meta name="DC.Creator.PersonalName" content="Siemen Dhooghe"/> <meta name="DC.Creator.PersonalName" content="Josep Balasch"/> <meta name="DC.Creator.PersonalName" content="Benedikt Gierlichs"/> <meta name="DC.Creator.PersonalName" content="Ingrid Verbauwhede"/> <meta name="DC.Date.created" scheme="ISO8601" content="2025-03-04"/> <meta name="DC.Date.dateSubmitted" scheme="ISO8601" content="2025-03-03"/> <meta name="DC.Date.issued" scheme="ISO8601" content="2025-03-04"/> <meta name="DC.Date.modified" scheme="ISO8601" content="2025-03-04"/> <meta name="DC.Description" xml:lang="en" content="At CHES 2024, Time Sharing Masking (TSM) was introduced as a novel low-latency masking technique for hardware circuits. TSM offers area and randomness efficiency, as well as glitch-extended PINI security, but it is limited to first-order security. We address this limitation and generalize TSM to higher-order security while maintaining all of TSM鈥檚 advantages. Additionally, we propose an area-latency tradeoff. We prove HO-TSM glitch-extended PINI security and successfully evaluate our circuits using formal verification tools. Furthermore, we demonstrate area- and latency-efficient implementations of the AES S-box, which do not exhibit leakage in TVLA on FPGA. Our proposed tradeoff enables a first-order secure implementation of a complete AES-128 encryption core with 92 kGE, 920 random bits per round, and 20 cycles of latency, which does not exhibit leakage in TVLA on FPGA."/> <meta name="DC.Format" scheme="IMT" content="application/pdf"/> <meta name="DC.Identifier" content="12047"/> <meta name="DC.Identifier.pageNumber" content="235-267"/> <meta name="DC.Identifier.DOI" content="10.46586/tches.v2025.i2.235-267"/> <meta name="DC.Identifier.URI" content="https://tches.iacr.org/index.php/TCHES/article/view/12047"/> <meta name="DC.Language" scheme="ISO639-1" content="en"/> <meta name="DC.Rights" content="Copyright (c) 2025 Dilip Kumar S. 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TSM offers area and randomness efficiency, as well as glitch-extended PINI security, but it is limited to first-order security. We address this limitation and generalize TSM to higher-order security while maintaining all of TSM鈥檚 advantages. Additionally, we propose an area-latency tradeoff. We prove HO-TSM glitch-extended PINI security and successfully evaluate our circuits using formal verification tools. Furthermore, we demonstrate area- and latency-efficient implementations of the AES S-box, which do not exhibit leakage in TVLA on FPGA. Our proposed tradeoff enables a first-order secure implementation of a complete AES-128 encryption core with 92 kGE, 920 random bits per round, and 20 cycles of latency, which does not exhibit leakage in TVLA on FPGA."/> <meta name="citation_keywords" xml:lang="en" content="Hardware"/> <meta name="citation_keywords" xml:lang="en" content="Masking"/> <meta name="citation_keywords" xml:lang="en" content="Probing Security"/> <meta name="citation_keywords" xml:lang="en" content="Side-Channel Analysis"/> <meta name="citation_keywords" xml:lang="en" content="Low-Latency"/> <meta name="citation_pdf_url" content="https://tches.iacr.org/index.php/TCHES/article/download/12047/11891"/> <link rel="stylesheet" href="https://tches.iacr.org/index.php/TCHES/$$$call$$$/page/page/css?name=stylesheet" type="text/css" /><link rel="stylesheet" href="https://tches.iacr.org/index.php/TCHES/$$$call$$$/page/page/css?name=font" type="text/css" /><link rel="stylesheet" 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class="main_entry"> <section class="item authors"> <h2 class="pkp_screen_reader">Authors</h2> <ul class="authors"> <li> <span class="name"> Dilip Kumar S. V. </span> <span class="affiliation"> COSIC, KU Leuven, Belgium </span> <span class="orcid"> <a href="https://orcid.org/0000-0003-0057-1658" target="_blank"> https://orcid.org/0000-0003-0057-1658 </a> </span> </li> <li> <span class="name"> Siemen Dhooghe </span> <span class="affiliation"> COSIC, KU Leuven, Belgium </span> <span class="orcid"> <a href="https://orcid.org/0000-0003-0591-7355" target="_blank"> https://orcid.org/0000-0003-0591-7355 </a> </span> </li> <li> <span class="name"> Josep Balasch </span> <span class="affiliation"> e-Media Research Lab, STADIUS, KU Leuven, Belgium </span> <span class="orcid"> <a href="https://orcid.org/0000-0002-6066-8710" target="_blank"> https://orcid.org/0000-0002-6066-8710 </a> </span> </li> <li> <span class="name"> Benedikt Gierlichs </span> <span class="affiliation"> COSIC, KU Leuven, Belgium </span> </li> <li> <span class="name"> Ingrid Verbauwhede </span> <span class="affiliation"> COSIC, KU Leuven, Belgium </span> <span class="orcid"> <a href="https://orcid.org/0000-0002-0879-076X" target="_blank"> https://orcid.org/0000-0002-0879-076X </a> </span> </li> </ul> </section> <section class="item doi"> <h2 class="label"> DOI: </h2> <span class="value"> <a href="https://doi.org/10.46586/tches.v2025.i2.235-267"> https://doi.org/10.46586/tches.v2025.i2.235-267 </a> </span> </section> <section class="item keywords"> <h2 class="label"> Keywords: </h2> <span class="value"> Hardware, Masking, Probing Security, Side-Channel Analysis, Low-Latency </span> </section> <section class="item abstract"> <h2 class="label">Abstract</h2> <p>At CHES 2024, Time Sharing Masking (TSM) was introduced as a novel low-latency masking technique for hardware circuits. TSM offers area and randomness efficiency, as well as glitch-extended PINI security, but it is limited to first-order security. We address this limitation and generalize TSM to higher-order security while maintaining all of TSM鈥檚 advantages. Additionally, we propose an area-latency tradeoff. We prove HO-TSM glitch-extended PINI security and successfully evaluate our circuits using formal verification tools. Furthermore, we demonstrate area- and latency-efficient implementations of the AES S-box, which do not exhibit leakage in TVLA on FPGA. Our proposed tradeoff enables a first-order secure implementation of a complete AES-128 encryption core with 92 kGE, 920 random bits per round, and 20 cycles of latency, which does not exhibit leakage in TVLA on FPGA.</p> </section> </div> <div class="entry_details"> <div class="item galleys"> <h2 class="pkp_screen_reader"> Downloads </h2> <ul class="value galleys_links"> <li> <a class="obj_galley_link pdf" href="https://tches.iacr.org/index.php/TCHES/article/view/12047/11891"> PDF </a> </li> </ul> </div> <div class="item published"> <section class="sub_item"> <h2 class="label"> Published </h2> <div class="value"> <span>2025-03-04</span> </div> </section> </div> <div class="item issue"> <section class="sub_item"> <h2 class="label"> Issue </h2> <div class="value"> <a class="title" href="https://tches.iacr.org/index.php/TCHES/issue/view/378"> Vol. 2025 No. 2 </a> </div> </section> <section class="sub_item"> <h2 class="label"> Section </h2> <div class="value"> Articles </div> </section> </div> <div class="item copyright"> <h2 class="label"> License </h2> <p>Copyright (c) 2025 Dilip Kumar S. V., Siemen Dhooghe, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede</p> <a rel="license" href="https://creativecommons.org/licenses/by/4.0/"><img alt="Creative Commons License" src="//i.creativecommons.org/l/by/4.0/88x31.png" /></a><p>This work is licensed under a <a rel="license" href="https://creativecommons.org/licenses/by/4.0/">Creative Commons Attribution 4.0 International License</a>.</p> </div> <div class="item citation"> <section class="sub_item citation_display"> <h2 class="label"> How to Cite </h2> <div class="value"> <div id="citationOutput" role="region" aria-live="polite"> <div class="csl-bib-body"> <div class="csl-entry">Kumar S. V., D., Dhooghe, S., Balasch, J., Gierlichs, B., & Verbauwhede, I. (2025). Higher-Order Time Sharing Masking. <i>IACR Transactions on Cryptographic Hardware and Embedded Systems</i>, <i>2025</i>(2), 235-267. <a href="https://doi.org/10.46586/tches.v2025.i2.235-267">https://doi.org/10.46586/tches.v2025.i2.235-267</a></div> </div> </div> <div class="citation_formats"> <button class="citation_formats_button label" aria-controls="cslCitationFormats" aria-expanded="false" data-csl-dropdown="true"> More Citation Formats </button> <div id="cslCitationFormats" class="citation_formats_list" aria-hidden="true"> <ul class="citation_formats_styles"> <li> <a aria-controls="citationOutput" href="https://tches.iacr.org/index.php/TCHES/citationstylelanguage/get/acm-sig-proceedings?submissionId=12047&publicationId=5598&issueId=378" data-load-citation data-json-href="https://tches.iacr.org/index.php/TCHES/citationstylelanguage/get/acm-sig-proceedings?submissionId=12047&publicationId=5598&issueId=378&return=json" > ACM </a> </li> <li> <a aria-controls="citationOutput" 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Higher-Order Time Sharing Masking | IACR Transactions on Cryptographic Hardware and Embedded Systems