TY - JFULL AU - Arash Azizi Mazreah and Mohammad T. Manzuri Shalmani and Hamid Barati and Ali Barati and Ali Sarchami PY - 2008/4/ TI - A Low Power SRAM Base on Novel Word-Line Decoding T2 - International Journal of Computer and Information Engineering SP - 648 EP - 653 VL - 2 SN - 1307-6892 UR - https://publications.waset.org/pdf/931 PU - World Academy of Science, Engineering and Technology NX - Open Science Index 15, 2008 N2 - This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25渭m CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results. ER -