{"title":"High Order Cascade Multibit \u03a3\u0394 Modulator for Wide Bandwidth Applications","authors":"S. Zouari, H. Daoud, M. Loulou, P. Loumeau, N. Masmoudi","volume":9,"journal":"International Journal of Electronics and Communication Engineering","pagesStart":1337,"pagesEnd":1344,"ISSN":"1307-6892","URL":"https:\/\/publications.waset.org\/pdf\/5283","abstract":"A wideband 2-1-1 cascaded \u03a3\u0394 modulator with a\nsingle-bit quantizer in the two first stages and a 4-bit quantizer in the\nfinal stage is developed. To reduce sensitivity of digital-to-analog\nconverter (DAC) nonlinearities in the feedback of the last stage,\ndynamic element matching (DEM) is introduced. This paper presents\ntwo modelling approaches: The first is MATLAB description and the\nsecond is VHDL-AMS modelling of the proposed architecture and\nexposes some high-level-simulation results allowing a behavioural\nstudy. The detail of both ideal and non-ideal behaviour modelling are\npresented. Then, the study of the effect of building blocks\nnonidealities is presented; especially the influences of nonlinearity,\nfinite operational amplifier gain, amplifier slew rate limitation and\ncapacitor mismatch. A VHDL-AMS description presents a good\nsolution to predict system-s performances and can provide sensitivity\ncurves giving the impact of nonidealities on the system performance.","references":"[1] Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama,\nSteve Kosic, jun Cao and Shu-Lap Chan, \" A 90-dB SNR 2.5-MHz\nOutput-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at\n8X Oversampling Ratio\", IEEE Journal of Solid-State Circuits, ,vol.35,\nNo 12, December 2000.W\n[2] Todd L.Brooks, D.H Robertson, D.F Kelly, A.Del Muro and\nS.W.Harston, \"A cascade Sigma-Delta Pipeline A\/D Converter with 1.25\nMHz Signal Bandwidth and 89 dB SNR\", IEEE Journal of Solid-\nCircuits, Vol 32, No.12, December 1997.\n[3] Matthew R.Miller and Craig S.Petrie, \"A multibit Sigma-Delta ADC for\nMultimode Receivers\", IEEE Journal of Solid- Circuits, Vol 38, No. 3,\nMarch 2003.\n[4] Yong-In Park, S.Karthikeyan, Wern Ming Koe, Zhongnong Jiang and\nTiak-Chean Tan, \u00ab A 16-Bit, 5 MHz Multi-Bit Sigma-Delta ADC Using\nAdaptively Randomized DWA\u00bb, IEEE Custom Integrated circuits\nconference, 2003.\n[5] K.Vleugels, S.Rabii and Bruce A.Wooley, \"A 2.5-V Sigma-Delta\nModulator for Broadband Communications Applications\", IEEE Journal\nof Solid- Circuits, Vol 36, No.12, December 2001.\n[6] F. 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