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The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to design and Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC. ASP-DAC recognizes excellent contributions with the Best Paper Award and 10-Year Retrospective Most Influential Paper Award. Selected papers will be invited to submit the extended version of their work to a Special Issue of Integration, the VLSI Journal. Areas of Interest: Original papers in, but not limited to, the following areas are invited. 1 System-Level Modeling and Design Methodology: 1.1. HW/SW co-design, co-simulation and co-verification 1.2. System-level design exploration, synthesis, and optimization 1.3. System-level formal verification 1.4. System-level modeling, simulation and validation 1.5. Networks-on-chip and NoC-based system design 2 Embedded, Cyberphysical (CPS) and IoT Systems, and Software: 2.1. Many- and multi-core SoC architecture 2.2. IP/platform-based SoC design 2.3. Dependable architecture 2.4. Cyber physical system and Internet of Things 2.5. Kernel, middleware, and virtual machine 2.6. Compiler and toolchain 2.7. Real-time system 2.8. Resource allocation for heterogeneous computing platform 2.9. Storage software and application 2.10. Human-computer interface 3 Memory Architecture and Near/In Memory Computing: 3.1. Storage system and memory architecture 3.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc. 3.3. Memory/storage hierarchies and management for emerging memory technologies 3.4. Near-memory and in-memory computing 4 Tools and Design Methods with and for Artificial Intelligence (AI): 4.1. Design method for learning on a chip 4.2. Deep neural network for EDA 4.3. Large language model (LLM) for circuit design and EDA 4.4. Tools and design methodologies for edge AI and TinyML 4.5. Efficient ML training and inference 5 Hardware Systems and Architectures for AI: 5.1. Hardware, device, architecture, and system-level design for deep neural networks 5.2. Hardware acceleration for large language model 5.3. Neural network acceleration co-design techniques 5.4. Novel reconfigurable architectures, including FPGAs for AI/MLs 6 Photonic/RF/Analog-Mixed Signal Design: 6.1. Analog/mixed-signal/RF synthesis 6.2. Analog layout, verification, and simulation techniques 6.3. High-frequency electromagnetic simulation of circuit 6.4. Mixed-signal design consideration 6.5. Communication and computing using photonics 7 Approximate, Bio-Inspired and Neuromorphic Computing: 7.1. Circuit and system techniques for approximate and stochastic computing 7.2. Neuromorphic computing 7.3. CAD for approximate and stochastic systems 7.4. CAD for bio-inspired and neuromorphic systems 8 High-Level, Behavioral, and Logic Synthesis and Optimization: 8.1. High-level/Behavioral synthesis tool and methodology 8.2. Combinational, sequential and asynchronous logic synthesis 8.3. Synthesis for deep neural networks 8.4. Technology mapping, resource scheduling, allocation and synthesis 8.5. Functional and logic timing ECO (Engineering change order) 8.6. Interaction between logic synthesis and physical design 9 Physical Design and Timing Analysis: 9.1. Floorplanning, partitioning and placement and routing optimization 9.2. Interconnect planning and synthesis 9.3. Clock network synthesis 9.4. Post layout and post-silicon optimization 9.5. Package/PCB/3D-IC routing 9.6. Extraction, TSV and package modeling 9.7. Deterministic/statistical timing analysis and optimization 10 Design for Manufacturability/Reliability and Low Power: 10.1. Reticle enhancement, lithography-related design and optimization 10.2. Resilience under manufacturing variation 10.3. Design for manufacturability, yield, and defect tolerance 10.4. Reliability, robustness, aging and soft error analysis 10.5. Power modeling, analysis and simulation 10.6. Low-power design and optimization at circuit and system levels 10.7. Thermal aware design and dynamic thermal management 10.8. Energy harvesting and battery management 10.9. Signal/Power integrity, EM modeling and analysis 11 Testing, Validation, Simulation, and Verification: 11.1. ATPG, BIST and DFT 11.2. System test and 3D IC test, Online test and fault tolerance 11.3. Memory test and repair 11.4. RTL and gate-leveling modeling, simulation, and verification 11.5. Circuit-level formal verification 11.6. Device/circuit-level simulation tool and methodology 12 Hardware and Embedded Security: 12.1. Hardware-based security 12.2. Detection and prevention of hardware Trojans 12.3. Side-channel attacks, fault attacks and countermeasures 12.4. Design and CAD for security 12.5. Cyberphysical system security 12.6. Nanoelectronic security 12.7. Supply chain security and anti-counterfeiting 12.8. Security/privacy for LLM/AI/ML 13 Emerging Devices, Technologies and Applications: 13.1. EDA and circuits design for quantum and Ising computing 13.2. Nanotechnology, MEMS 13.3. Biomedical, biochip, and biodata processing 13.4. Edge, fog and cloud computing 13.5. Energy-storage/smart-grid/smart-building design and optimization 13.6. Automotive system design and optimization 13.7. New transistor/device and process technology: spintronic, phase-change, single-electron, 2D materials, etc. Authors must submit full-length, double-columned, original papers, with a maximum of 6 pages in PDF format (including the abstract, figures and tables) and are recommended to format their papers based on the ACM template. One page of references is allowed, which does not count towards the 6-page limitation. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals. The submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, references and bibliographic citations. While research papers with open-source software are highly encouraged where the software will be made publicly available (via GitHub or similar), the authors’ identities need to be anonymized in the submitted paper for the double-blind review process. Issuing the paper as a technical report, posting the paper on a website, or presenting the paper at a workshop that does not publish formally reviewed proceedings, does not disqualify it from appearing in the proceedings. Note that each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by any author. </pre><div class="alert alert-warning"> Last updated by <a href="/researcher/1">Dou Sun</a> in 2024-05-26</div> </div> </div>  <div class="portlet" id="yw2"> <div class="portlet-decoration"> <div class="portlet-title"><i class="icon icon-thumbs-up"></i> Best Papers</div> </div> <div class="portlet-content"> <div id="yw3" class="grid-view"> <table class="table table-hover table-striped table-bordered table-condensed"> <thead> <tr> <th id="yw3_c0">Year</th><th id="yw3_c1">Best Papers</th></tr> </thead> <tbody> <tr class="odd"> <td>2020</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Towards+Area-Efficient+Optical+Neural+Networks%3A+An+FFT-based+Architecture">Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture</a></td></tr> <tr class="even"> <td>2020</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Equivalent+Capacitance+Guided+Dummy+Fill+Insertion+for+Timing+and+Manufacturability">Equivalent Capacitance Guided Dummy Fill Insertion for Timing and Manufacturability</a></td></tr> <tr class="odd"> <td>2019</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=GraphSAR%3A+A+Sparsity-Aware+Processing-in-Memory+Architecture+for+Large-Scale+Graph+Processing+on+ReRAMs">GraphSAR: A Sparsity-Aware Processing-in-Memory Architecture for Large-Scale Graph Processing on ReRAMs</a></td></tr> <tr class="even"> <td>2019</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Energy-Efficient%2C+Low-Latency+Realization+of+Neural+Networks+through+Boolean+Logic+Minimization">Energy-Efficient, Low-Latency Realization of Neural Networks through Boolean Logic Minimization</a></td></tr> <tr class="odd"> <td>2018</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Process+Variation+Aware+Data+Management+for+Magnetic+Skyrmions+Racetrack+Memory">Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory</a></td></tr> <tr class="even"> <td>2017</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Classification+Accuracy+Improvement+for+Neuromorphic+Computing+Systems+with+One-level+Precision+Synapses">Classification Accuracy Improvement for Neuromorphic Computing Systems with One-level Precision Synapses</a></td></tr> <tr class="odd"> <td>2017</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Spendthrift%3A+Machine+Learning+Based+Resource+and+Frequency+Scaling+for+Ambient+Energy+Harvesting+Nonvolatile+Processors">Spendthrift: Machine Learning Based Resource and Frequency Scaling for Ambient Energy Harvesting Nonvolatile Processors</a></td></tr> <tr class="even"> <td>2016</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Lattice-Based+Boolean+Diagrams%3A+Canonical%2C+Order-Independent+Graphical+Representations+of+Boolean+Functions">Lattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions</a></td></tr> <tr class="odd"> <td>2016</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Netlist+Reverse+Engineering+for+High-Level+Functionality+Reconstruction">Netlist Reverse Engineering for High-Level Functionality Reconstruction</a></td></tr> <tr class="even"> <td>2015</td><td><a target="_blank" href="http://scholar.google.com/scholar?q=Quantitative+Modeling+of+Racetrack+Memory%2C+A+Tradeoff+among+Area%2C+Performance%2C+and+Power">Quantitative Modeling of Racetrack Memory, A Tradeoff among Area, Performance, and Power</a></td></tr> </tbody> </table><div class="pager">Go to page: <ul id="yw4" class="yiiPager"><li class="first hidden"><a href="/conference/221"><< First</a></li> <li class="previous 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table-bordered table-condensed"> <thead> <tr> <th id="yw7_c0">Short</th><th id="yw7_c1">Full Name</th><th id="yw7_c2">Submission</th><th id="yw7_c3">Conference</th></tr> </thead> <tbody> <tr class="odd"> <td>iCMLDE</td><td><a href="/conference/3229">International Conference on Machine Learning and Data Engineering</a></td><td>2019-09-29</td><td>2019-12-02</td></tr> <tr class="even"> <td>SEBD</td><td><a href="/conference/3203">Italian Symposium on Advanced Database Systems</a></td><td>2019-03-18</td><td>2019-06-16</td></tr> <tr class="odd"> <td>MIE</td><td><a href="/conference/481">International Conference of the European Federation for Medical Informatics</a></td><td>2012-01-15</td><td>2012-08-26</td></tr> <tr class="even"> <td>ICSPS</td><td><a href="/conference/688">International Conference on Signal Processing Systems</a></td><td>2025-05-15</td><td>2025-10-24</td></tr> <tr class="odd"> <td>edC</td><td><a href="/conference/2839">electronic displays Conference</a></td><td>2018-10-05</td><td>2019-02-27</td></tr> <tr class="even"> <td>EUC</td><td><a href="/conference/694">International Conference on Embedded and Ubiquitous Computing</a></td><td>2024-09-01</td><td>2024-12-17</td></tr> <tr class="odd"> <td>ICIAR</td><td><a href="/conference/1273">International Conference on Image Analysis and Recognition</a></td><td>2020-02-10</td><td>2020-06-24</td></tr> <tr class="even"> <td>ISACR</td><td><a href="/conference/2874">International Symposium on Automation, Control and Robotics</a></td><td>2018-09-15</td><td>2018-09-28</td></tr> <tr class="odd"> <td>UAI</td><td><a href="/conference/416">Conference on Uncertainty in Artificial Intelligence</a></td><td>2025-02-10</td><td>2025-07-21</td></tr> </tbody> </table><div class="keys" style="display:none" title="/conference/221"><span>3229</span><span>3203</span><span>481</span><span>688</span><span>2839</span><span>694</span><span>1273</span><span>2874</span><span>416</span></div> </div></div> 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title="/conference/221"><span>66577</span><span>48304</span><span>15709</span><span>26722</span><span>15825</span><span>2152</span><span>974</span></div> </div> <div class="portlet" id="yw17"> <div class="portlet-decoration"> <div class="portlet-title"><i class="icon icon-gift"></i> Advertisment</div> </div> <div class="portlet-content"> <div align="center"> <div id="12717-20"><script src="//ads.themoneytizer.com/s/gen.js?type=20"></script><script src="//ads.themoneytizer.com/s/requestform.js?siteId=12717&formatId=20" ></script></div> </div>    </div> </div> </div> </div> </div> </div> </section>  <footer> <div class="subnav navbar"> <div class="navbar-inner"> <div class="container"> <a href="/conferences">4,996</a> Conferences | <a href="/journals">1,182</a> Journals | <a href="/researchers">71,419</a> Researchers | 446,256,445 PV <br/> Copyright © 2011-2025 myhuiban.com. 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